Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:52:31.298335 lava-dispatcher, installed at version: 2024.01
2 04:52:31.299132 start: 0 validate
3 04:52:31.299604 Start time: 2024-11-07 04:52:31.299575+00:00 (UTC)
4 04:52:31.300178 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:52:31.300734 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 04:52:31.343498 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:52:31.344040 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-235-gf366870b9966d%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 04:52:31.378298 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:52:31.378919 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-235-gf366870b9966d%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:52:31.412966 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:52:31.413485 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:52:31.450409 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 04:52:31.451097 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-235-gf366870b9966d%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 04:52:31.506152 validate duration: 0.21
16 04:52:31.508370 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:52:31.509267 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:52:31.510152 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:52:31.511405 Not decompressing ramdisk as can be used compressed.
20 04:52:31.512449 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 04:52:31.513123 saving as /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/ramdisk/initrd.cpio.gz
22 04:52:31.513772 total size: 5628169 (5 MB)
23 04:52:31.566861 progress 0 % (0 MB)
24 04:52:31.575224 progress 5 % (0 MB)
25 04:52:31.583013 progress 10 % (0 MB)
26 04:52:31.590226 progress 15 % (0 MB)
27 04:52:31.598079 progress 20 % (1 MB)
28 04:52:31.604595 progress 25 % (1 MB)
29 04:52:31.608636 progress 30 % (1 MB)
30 04:52:31.612728 progress 35 % (1 MB)
31 04:52:31.616446 progress 40 % (2 MB)
32 04:52:31.620513 progress 45 % (2 MB)
33 04:52:31.624192 progress 50 % (2 MB)
34 04:52:31.628226 progress 55 % (2 MB)
35 04:52:31.632283 progress 60 % (3 MB)
36 04:52:31.635865 progress 65 % (3 MB)
37 04:52:31.639876 progress 70 % (3 MB)
38 04:52:31.643529 progress 75 % (4 MB)
39 04:52:31.647559 progress 80 % (4 MB)
40 04:52:31.651015 progress 85 % (4 MB)
41 04:52:31.654935 progress 90 % (4 MB)
42 04:52:31.658530 progress 95 % (5 MB)
43 04:52:31.661801 progress 100 % (5 MB)
44 04:52:31.662451 5 MB downloaded in 0.15 s (36.10 MB/s)
45 04:52:31.663012 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:52:31.663940 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:52:31.664267 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:52:31.664543 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:52:31.665019 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/kernel/Image
51 04:52:31.665291 saving as /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/kernel/Image
52 04:52:31.665502 total size: 45713920 (43 MB)
53 04:52:31.665712 No compression specified
54 04:52:31.704231 progress 0 % (0 MB)
55 04:52:31.732700 progress 5 % (2 MB)
56 04:52:31.761043 progress 10 % (4 MB)
57 04:52:31.790051 progress 15 % (6 MB)
58 04:52:31.818800 progress 20 % (8 MB)
59 04:52:31.847275 progress 25 % (10 MB)
60 04:52:31.876151 progress 30 % (13 MB)
61 04:52:31.904982 progress 35 % (15 MB)
62 04:52:31.933654 progress 40 % (17 MB)
63 04:52:31.962005 progress 45 % (19 MB)
64 04:52:31.990777 progress 50 % (21 MB)
65 04:52:32.019174 progress 55 % (24 MB)
66 04:52:32.048308 progress 60 % (26 MB)
67 04:52:32.076711 progress 65 % (28 MB)
68 04:52:32.105129 progress 70 % (30 MB)
69 04:52:32.133686 progress 75 % (32 MB)
70 04:52:32.162124 progress 80 % (34 MB)
71 04:52:32.190487 progress 85 % (37 MB)
72 04:52:32.219015 progress 90 % (39 MB)
73 04:52:32.247318 progress 95 % (41 MB)
74 04:52:32.275003 progress 100 % (43 MB)
75 04:52:32.275592 43 MB downloaded in 0.61 s (71.46 MB/s)
76 04:52:32.276097 end: 1.2.1 http-download (duration 00:00:01) [common]
78 04:52:32.276918 end: 1.2 download-retry (duration 00:00:01) [common]
79 04:52:32.277196 start: 1.3 download-retry (timeout 00:09:59) [common]
80 04:52:32.277464 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 04:52:32.277943 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 04:52:32.278222 saving as /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/dtb/meson-g12b-a311d-libretech-cc.dtb
83 04:52:32.278432 total size: 54703 (0 MB)
84 04:52:32.278640 No compression specified
85 04:52:32.313577 progress 59 % (0 MB)
86 04:52:32.314463 progress 100 % (0 MB)
87 04:52:32.315019 0 MB downloaded in 0.04 s (1.43 MB/s)
88 04:52:32.315491 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:52:32.316358 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:52:32.316628 start: 1.4 download-retry (timeout 00:09:59) [common]
92 04:52:32.316893 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 04:52:32.317357 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 04:52:32.317603 saving as /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/nfsrootfs/full.rootfs.tar
95 04:52:32.317809 total size: 120894716 (115 MB)
96 04:52:32.318018 Using unxz to decompress xz
97 04:52:32.358233 progress 0 % (0 MB)
98 04:52:33.155333 progress 5 % (5 MB)
99 04:52:33.998206 progress 10 % (11 MB)
100 04:52:34.793141 progress 15 % (17 MB)
101 04:52:35.530097 progress 20 % (23 MB)
102 04:52:36.129972 progress 25 % (28 MB)
103 04:52:37.000223 progress 30 % (34 MB)
104 04:52:37.790099 progress 35 % (40 MB)
105 04:52:38.136805 progress 40 % (46 MB)
106 04:52:38.507902 progress 45 % (51 MB)
107 04:52:39.231760 progress 50 % (57 MB)
108 04:52:40.115452 progress 55 % (63 MB)
109 04:52:40.912839 progress 60 % (69 MB)
110 04:52:41.675631 progress 65 % (74 MB)
111 04:52:42.459251 progress 70 % (80 MB)
112 04:52:43.288314 progress 75 % (86 MB)
113 04:52:44.076437 progress 80 % (92 MB)
114 04:52:44.844829 progress 85 % (98 MB)
115 04:52:45.704130 progress 90 % (103 MB)
116 04:52:46.482322 progress 95 % (109 MB)
117 04:52:47.321843 progress 100 % (115 MB)
118 04:52:47.334440 115 MB downloaded in 15.02 s (7.68 MB/s)
119 04:52:47.335163 end: 1.4.1 http-download (duration 00:00:15) [common]
121 04:52:47.337006 end: 1.4 download-retry (duration 00:00:15) [common]
122 04:52:47.337595 start: 1.5 download-retry (timeout 00:09:44) [common]
123 04:52:47.338170 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 04:52:47.339134 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/modules.tar.xz
125 04:52:47.339651 saving as /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/modules/modules.tar
126 04:52:47.340144 total size: 11607584 (11 MB)
127 04:52:47.340621 Using unxz to decompress xz
128 04:52:47.386759 progress 0 % (0 MB)
129 04:52:47.452973 progress 5 % (0 MB)
130 04:52:47.527017 progress 10 % (1 MB)
131 04:52:47.625184 progress 15 % (1 MB)
132 04:52:47.718387 progress 20 % (2 MB)
133 04:52:47.798621 progress 25 % (2 MB)
134 04:52:47.873909 progress 30 % (3 MB)
135 04:52:47.947765 progress 35 % (3 MB)
136 04:52:48.024539 progress 40 % (4 MB)
137 04:52:48.100605 progress 45 % (5 MB)
138 04:52:48.184315 progress 50 % (5 MB)
139 04:52:48.261021 progress 55 % (6 MB)
140 04:52:48.345269 progress 60 % (6 MB)
141 04:52:48.425876 progress 65 % (7 MB)
142 04:52:48.501996 progress 70 % (7 MB)
143 04:52:48.584625 progress 75 % (8 MB)
144 04:52:48.666766 progress 80 % (8 MB)
145 04:52:48.745691 progress 85 % (9 MB)
146 04:52:48.823090 progress 90 % (9 MB)
147 04:52:48.901033 progress 95 % (10 MB)
148 04:52:48.978326 progress 100 % (11 MB)
149 04:52:48.989239 11 MB downloaded in 1.65 s (6.71 MB/s)
150 04:52:48.990132 end: 1.5.1 http-download (duration 00:00:02) [common]
152 04:52:48.991832 end: 1.5 download-retry (duration 00:00:02) [common]
153 04:52:48.992448 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 04:52:48.992986 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 04:53:06.382640 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/950953/extract-nfsrootfs-r2r9my0j
156 04:53:06.383257 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 04:53:06.383549 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 04:53:06.384191 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf
159 04:53:06.384641 makedir: /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin
160 04:53:06.384974 makedir: /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/tests
161 04:53:06.385294 makedir: /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/results
162 04:53:06.385639 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-add-keys
163 04:53:06.386287 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-add-sources
164 04:53:06.386839 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-background-process-start
165 04:53:06.387344 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-background-process-stop
166 04:53:06.387873 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-common-functions
167 04:53:06.388423 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-echo-ipv4
168 04:53:06.388914 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-install-packages
169 04:53:06.389390 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-installed-packages
170 04:53:06.389869 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-os-build
171 04:53:06.390344 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-probe-channel
172 04:53:06.390824 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-probe-ip
173 04:53:06.391296 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-target-ip
174 04:53:06.391816 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-target-mac
175 04:53:06.392340 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-target-storage
176 04:53:06.392839 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-test-case
177 04:53:06.393324 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-test-event
178 04:53:06.393796 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-test-feedback
179 04:53:06.394349 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-test-raise
180 04:53:06.394836 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-test-reference
181 04:53:06.395312 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-test-runner
182 04:53:06.395796 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-test-set
183 04:53:06.396299 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-test-shell
184 04:53:06.396806 Updating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-add-keys (debian)
185 04:53:06.397347 Updating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-add-sources (debian)
186 04:53:06.397865 Updating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-install-packages (debian)
187 04:53:06.398370 Updating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-installed-packages (debian)
188 04:53:06.398863 Updating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/bin/lava-os-build (debian)
189 04:53:06.399298 Creating /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/environment
190 04:53:06.399678 LAVA metadata
191 04:53:06.399939 - LAVA_JOB_ID=950953
192 04:53:06.400179 - LAVA_DISPATCHER_IP=192.168.6.2
193 04:53:06.400554 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 04:53:06.401542 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 04:53:06.401860 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 04:53:06.402070 skipped lava-vland-overlay
197 04:53:06.402308 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 04:53:06.402563 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 04:53:06.402783 skipped lava-multinode-overlay
200 04:53:06.403024 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 04:53:06.403273 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 04:53:06.403520 Loading test definitions
203 04:53:06.403792 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 04:53:06.404049 Using /lava-950953 at stage 0
205 04:53:06.405130 uuid=950953_1.6.2.4.1 testdef=None
206 04:53:06.405439 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 04:53:06.405701 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 04:53:06.407304 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 04:53:06.408118 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 04:53:06.410111 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 04:53:06.410954 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 04:53:06.412911 runner path: /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/0/tests/0_timesync-off test_uuid 950953_1.6.2.4.1
215 04:53:06.413505 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 04:53:06.414330 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 04:53:06.414555 Using /lava-950953 at stage 0
219 04:53:06.414914 Fetching tests from https://github.com/kernelci/test-definitions.git
220 04:53:06.415211 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/0/tests/1_kselftest-dt'
221 04:53:10.048823 Running '/usr/bin/git checkout kernelci.org
222 04:53:10.107770 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 04:53:10.109227 uuid=950953_1.6.2.4.5 testdef=None
224 04:53:10.109579 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 04:53:10.110354 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 04:53:10.113242 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 04:53:10.114080 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 04:53:10.117835 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 04:53:10.118707 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 04:53:10.122321 runner path: /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/0/tests/1_kselftest-dt test_uuid 950953_1.6.2.4.5
234 04:53:10.122608 BOARD='meson-g12b-a311d-libretech-cc'
235 04:53:10.122826 BRANCH='broonie-sound'
236 04:53:10.123032 SKIPFILE='/dev/null'
237 04:53:10.123235 SKIP_INSTALL='True'
238 04:53:10.123435 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 04:53:10.123640 TST_CASENAME=''
240 04:53:10.123842 TST_CMDFILES='dt'
241 04:53:10.124425 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 04:53:10.125233 Creating lava-test-runner.conf files
244 04:53:10.125448 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950953/lava-overlay-0eok60kf/lava-950953/0 for stage 0
245 04:53:10.125828 - 0_timesync-off
246 04:53:10.126085 - 1_kselftest-dt
247 04:53:10.126436 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 04:53:10.126730 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 04:53:33.330864 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 04:53:33.331336 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 04:53:33.331642 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 04:53:33.331961 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 04:53:33.332305 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 04:53:33.947534 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 04:53:33.948036 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 04:53:33.948311 extracting modules file /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950953/extract-nfsrootfs-r2r9my0j
257 04:53:35.299210 extracting modules file /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950953/extract-overlay-ramdisk-xx2mrlci/ramdisk
258 04:53:36.687014 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 04:53:36.687505 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 04:53:36.687805 [common] Applying overlay to NFS
261 04:53:36.688064 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950953/compress-overlay-epl52u5x/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950953/extract-nfsrootfs-r2r9my0j
262 04:53:39.442497 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 04:53:39.443020 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 04:53:39.443339 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 04:53:39.443613 Converting downloaded kernel to a uImage
266 04:53:39.443958 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/kernel/Image /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/kernel/uImage
267 04:53:39.944037 output: Image Name:
268 04:53:39.944494 output: Created: Thu Nov 7 04:53:39 2024
269 04:53:39.944710 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 04:53:39.944919 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 04:53:39.945123 output: Load Address: 01080000
272 04:53:39.945328 output: Entry Point: 01080000
273 04:53:39.945527 output:
274 04:53:39.945878 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 04:53:39.946162 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 04:53:39.946438 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 04:53:39.946703 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 04:53:39.946971 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 04:53:39.947242 Building ramdisk /var/lib/lava/dispatcher/tmp/950953/extract-overlay-ramdisk-xx2mrlci/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950953/extract-overlay-ramdisk-xx2mrlci/ramdisk
280 04:53:42.079636 >> 166792 blocks
281 04:53:49.798671 Adding RAMdisk u-boot header.
282 04:53:49.799124 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950953/extract-overlay-ramdisk-xx2mrlci/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950953/extract-overlay-ramdisk-xx2mrlci/ramdisk.cpio.gz.uboot
283 04:53:50.054544 output: Image Name:
284 04:53:50.054973 output: Created: Thu Nov 7 04:53:49 2024
285 04:53:50.055188 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 04:53:50.055395 output: Data Size: 23431987 Bytes = 22882.80 KiB = 22.35 MiB
287 04:53:50.055601 output: Load Address: 00000000
288 04:53:50.055802 output: Entry Point: 00000000
289 04:53:50.056057 output:
290 04:53:50.057074 rename /var/lib/lava/dispatcher/tmp/950953/extract-overlay-ramdisk-xx2mrlci/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/ramdisk/ramdisk.cpio.gz.uboot
291 04:53:50.057782 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 04:53:50.058327 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 04:53:50.058856 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 04:53:50.059308 No LXC device requested
295 04:53:50.059804 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 04:53:50.060356 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 04:53:50.060853 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 04:53:50.061260 Checking files for TFTP limit of 4294967296 bytes.
299 04:53:50.063896 end: 1 tftp-deploy (duration 00:01:19) [common]
300 04:53:50.064531 start: 2 uboot-action (timeout 00:05:00) [common]
301 04:53:50.065056 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 04:53:50.065554 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 04:53:50.066059 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 04:53:50.066588 Using kernel file from prepare-kernel: 950953/tftp-deploy-kf9bz88k/kernel/uImage
305 04:53:50.067213 substitutions:
306 04:53:50.067624 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 04:53:50.068118 - {DTB_ADDR}: 0x01070000
308 04:53:50.068537 - {DTB}: 950953/tftp-deploy-kf9bz88k/dtb/meson-g12b-a311d-libretech-cc.dtb
309 04:53:50.068945 - {INITRD}: 950953/tftp-deploy-kf9bz88k/ramdisk/ramdisk.cpio.gz.uboot
310 04:53:50.069349 - {KERNEL_ADDR}: 0x01080000
311 04:53:50.069744 - {KERNEL}: 950953/tftp-deploy-kf9bz88k/kernel/uImage
312 04:53:50.070139 - {LAVA_MAC}: None
313 04:53:50.070572 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/950953/extract-nfsrootfs-r2r9my0j
314 04:53:50.070975 - {NFS_SERVER_IP}: 192.168.6.2
315 04:53:50.071368 - {PRESEED_CONFIG}: None
316 04:53:50.071761 - {PRESEED_LOCAL}: None
317 04:53:50.072189 - {RAMDISK_ADDR}: 0x08000000
318 04:53:50.072582 - {RAMDISK}: 950953/tftp-deploy-kf9bz88k/ramdisk/ramdisk.cpio.gz.uboot
319 04:53:50.072976 - {ROOT_PART}: None
320 04:53:50.073364 - {ROOT}: None
321 04:53:50.073753 - {SERVER_IP}: 192.168.6.2
322 04:53:50.074143 - {TEE_ADDR}: 0x83000000
323 04:53:50.074528 - {TEE}: None
324 04:53:50.074917 Parsed boot commands:
325 04:53:50.075293 - setenv autoload no
326 04:53:50.075678 - setenv initrd_high 0xffffffff
327 04:53:50.076086 - setenv fdt_high 0xffffffff
328 04:53:50.076476 - dhcp
329 04:53:50.076859 - setenv serverip 192.168.6.2
330 04:53:50.077247 - tftpboot 0x01080000 950953/tftp-deploy-kf9bz88k/kernel/uImage
331 04:53:50.077635 - tftpboot 0x08000000 950953/tftp-deploy-kf9bz88k/ramdisk/ramdisk.cpio.gz.uboot
332 04:53:50.078027 - tftpboot 0x01070000 950953/tftp-deploy-kf9bz88k/dtb/meson-g12b-a311d-libretech-cc.dtb
333 04:53:50.078416 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950953/extract-nfsrootfs-r2r9my0j,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 04:53:50.078817 - bootm 0x01080000 0x08000000 0x01070000
335 04:53:50.079320 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 04:53:50.080889 start: 2.3 connect-device (timeout 00:05:00) [common]
338 04:53:50.081312 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 04:53:50.096283 Setting prompt string to ['lava-test: # ']
340 04:53:50.097816 end: 2.3 connect-device (duration 00:00:00) [common]
341 04:53:50.098429 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 04:53:50.098992 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 04:53:50.099513 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 04:53:50.100724 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 04:53:50.138866 >> OK - accepted request
346 04:53:50.141469 Returned 0 in 0 seconds
347 04:53:50.242610 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 04:53:50.244371 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 04:53:50.244963 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 04:53:50.245485 Setting prompt string to ['Hit any key to stop autoboot']
352 04:53:50.245958 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 04:53:50.247560 Trying 192.168.56.21...
354 04:53:50.248086 Connected to conserv1.
355 04:53:50.248517 Escape character is '^]'.
356 04:53:50.248944
357 04:53:50.249364 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 04:53:50.249802
359 04:54:01.761739 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 04:54:01.762435 bl2_stage_init 0x01
361 04:54:01.762942 bl2_stage_init 0x81
362 04:54:01.767224 hw id: 0x0000 - pwm id 0x01
363 04:54:01.767797 bl2_stage_init 0xc1
364 04:54:01.768325 bl2_stage_init 0x02
365 04:54:01.768785
366 04:54:01.772733 L0:00000000
367 04:54:01.773279 L1:20000703
368 04:54:01.773738 L2:00008067
369 04:54:01.774188 L3:14000000
370 04:54:01.778371 B2:00402000
371 04:54:01.778899 B1:e0f83180
372 04:54:01.779336
373 04:54:01.779771 TE: 58159
374 04:54:01.780250
375 04:54:01.783968 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 04:54:01.784496
377 04:54:01.784935 Board ID = 1
378 04:54:01.789570 Set A53 clk to 24M
379 04:54:01.790066 Set A73 clk to 24M
380 04:54:01.790504 Set clk81 to 24M
381 04:54:01.795145 A53 clk: 1200 MHz
382 04:54:01.795645 A73 clk: 1200 MHz
383 04:54:01.796112 CLK81: 166.6M
384 04:54:01.796544 smccc: 00012ab5
385 04:54:01.800656 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 04:54:01.806350 board id: 1
387 04:54:01.812281 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 04:54:01.822805 fw parse done
389 04:54:01.828897 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 04:54:01.871379 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 04:54:01.882245 PIEI prepare done
392 04:54:01.882743 fastboot data load
393 04:54:01.883183 fastboot data verify
394 04:54:01.887975 verify result: 266
395 04:54:01.893558 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 04:54:01.894055 LPDDR4 probe
397 04:54:01.894492 ddr clk to 1584MHz
398 04:54:01.901553 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 04:54:01.938782
400 04:54:01.939302 dmc_version 0001
401 04:54:01.945473 Check phy result
402 04:54:01.951324 INFO : End of CA training
403 04:54:01.951841 INFO : End of initialization
404 04:54:01.956954 INFO : Training has run successfully!
405 04:54:01.957455 Check phy result
406 04:54:01.962540 INFO : End of initialization
407 04:54:01.963033 INFO : End of read enable training
408 04:54:01.968197 INFO : End of fine write leveling
409 04:54:01.973731 INFO : End of Write leveling coarse delay
410 04:54:01.974239 INFO : Training has run successfully!
411 04:54:01.974681 Check phy result
412 04:54:01.979315 INFO : End of initialization
413 04:54:01.979814 INFO : End of read dq deskew training
414 04:54:01.984914 INFO : End of MPR read delay center optimization
415 04:54:01.990517 INFO : End of write delay center optimization
416 04:54:01.996169 INFO : End of read delay center optimization
417 04:54:01.996678 INFO : End of max read latency training
418 04:54:02.001748 INFO : Training has run successfully!
419 04:54:02.002286 1D training succeed
420 04:54:02.010877 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 04:54:02.058516 Check phy result
422 04:54:02.059067 INFO : End of initialization
423 04:54:02.080201 INFO : End of 2D read delay Voltage center optimization
424 04:54:02.100306 INFO : End of 2D read delay Voltage center optimization
425 04:54:02.152266 INFO : End of 2D write delay Voltage center optimization
426 04:54:02.201578 INFO : End of 2D write delay Voltage center optimization
427 04:54:02.207067 INFO : Training has run successfully!
428 04:54:02.207644
429 04:54:02.208143 channel==0
430 04:54:02.212614 RxClkDly_Margin_A0==78 ps 8
431 04:54:02.212951 TxDqDly_Margin_A0==98 ps 10
432 04:54:02.218179 RxClkDly_Margin_A1==88 ps 9
433 04:54:02.218570 TxDqDly_Margin_A1==88 ps 9
434 04:54:02.218805 TrainedVREFDQ_A0==74
435 04:54:02.223721 TrainedVREFDQ_A1==74
436 04:54:02.224192 VrefDac_Margin_A0==25
437 04:54:02.224447 DeviceVref_Margin_A0==40
438 04:54:02.229345 VrefDac_Margin_A1==25
439 04:54:02.229733 DeviceVref_Margin_A1==40
440 04:54:02.229972
441 04:54:02.230198
442 04:54:02.230422 channel==1
443 04:54:02.234930 RxClkDly_Margin_A0==98 ps 10
444 04:54:02.235318 TxDqDly_Margin_A0==88 ps 9
445 04:54:02.240552 RxClkDly_Margin_A1==88 ps 9
446 04:54:02.240974 TxDqDly_Margin_A1==88 ps 9
447 04:54:02.246265 TrainedVREFDQ_A0==77
448 04:54:02.246766 TrainedVREFDQ_A1==77
449 04:54:02.247048 VrefDac_Margin_A0==22
450 04:54:02.251728 DeviceVref_Margin_A0==37
451 04:54:02.252413 VrefDac_Margin_A1==24
452 04:54:02.257309 DeviceVref_Margin_A1==37
453 04:54:02.257788
454 04:54:02.258203 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 04:54:02.258608
456 04:54:02.290922 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 04:54:02.291588 2D training succeed
458 04:54:02.296513 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 04:54:02.302121 auto size-- 65535DDR cs0 size: 2048MB
460 04:54:02.302585 DDR cs1 size: 2048MB
461 04:54:02.307648 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 04:54:02.308135 cs0 DataBus test pass
463 04:54:02.313297 cs1 DataBus test pass
464 04:54:02.313742 cs0 AddrBus test pass
465 04:54:02.314146 cs1 AddrBus test pass
466 04:54:02.314542
467 04:54:02.318865 100bdlr_step_size ps== 420
468 04:54:02.319314 result report
469 04:54:02.324448 boot times 0Enable ddr reg access
470 04:54:02.329676 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 04:54:02.343201 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 04:54:02.915177 0.0;M3 CHK:0;cm4_sp_mode 0
473 04:54:02.915820 MVN_1=0x00000000
474 04:54:02.920569 MVN_2=0x00000000
475 04:54:02.926332 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 04:54:02.926779 OPS=0x10
477 04:54:02.927186 ring efuse init
478 04:54:02.927581 chipver efuse init
479 04:54:02.934542 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 04:54:02.935001 [0.018960 Inits done]
481 04:54:02.941306 secure task start!
482 04:54:02.941659 high task start!
483 04:54:02.941878 low task start!
484 04:54:02.942087 run into bl31
485 04:54:02.948799 NOTICE: BL31: v1.3(release):4fc40b1
486 04:54:02.956608 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 04:54:02.956986 NOTICE: BL31: G12A normal boot!
488 04:54:02.982086 NOTICE: BL31: BL33 decompress pass
489 04:54:02.987677 ERROR: Error initializing runtime service opteed_fast
490 04:54:04.220724
491 04:54:04.221174
492 04:54:04.229046 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 04:54:04.229503
494 04:54:04.229828 Model: Libre Computer AML-A311D-CC Alta
495 04:54:04.437607 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 04:54:04.460819 DRAM: 2 GiB (effective 3.8 GiB)
497 04:54:04.604044 Core: 408 devices, 31 uclasses, devicetree: separate
498 04:54:04.609706 WDT: Not starting watchdog@f0d0
499 04:54:04.642211 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 04:54:04.654448 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 04:54:04.659643 ** Bad device specification mmc 0 **
502 04:54:04.669771 Card did not respond to voltage select! : -110
503 04:54:04.677446 ** Bad device specification mmc 0 **
504 04:54:04.678112 Couldn't find partition mmc 0
505 04:54:04.687094 Card did not respond to voltage select! : -110
506 04:54:04.691274 ** Bad device specification mmc 0 **
507 04:54:04.691907 Couldn't find partition mmc 0
508 04:54:04.696413 Error: could not access storage.
509 04:54:05.962665 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 04:54:05.963345 bl2_stage_init 0x01
511 04:54:05.963833 bl2_stage_init 0x81
512 04:54:05.968148 hw id: 0x0000 - pwm id 0x01
513 04:54:05.968660 bl2_stage_init 0xc1
514 04:54:05.969125 bl2_stage_init 0x02
515 04:54:05.969578
516 04:54:05.973765 L0:00000000
517 04:54:05.974263 L1:20000703
518 04:54:05.974710 L2:00008067
519 04:54:05.975154 L3:14000000
520 04:54:05.979418 B2:00402000
521 04:54:05.979915 B1:e0f83180
522 04:54:05.980421
523 04:54:05.980870 TE: 58124
524 04:54:05.981316
525 04:54:05.984913 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 04:54:05.985415
527 04:54:05.985872 Board ID = 1
528 04:54:05.990540 Set A53 clk to 24M
529 04:54:05.991029 Set A73 clk to 24M
530 04:54:05.991486 Set clk81 to 24M
531 04:54:05.996096 A53 clk: 1200 MHz
532 04:54:05.996594 A73 clk: 1200 MHz
533 04:54:05.997046 CLK81: 166.6M
534 04:54:05.997495 smccc: 00012a91
535 04:54:06.001846 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 04:54:06.008244 board id: 1
537 04:54:06.013183 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 04:54:06.024102 fw parse done
539 04:54:06.029933 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 04:54:06.072544 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 04:54:06.083405 PIEI prepare done
542 04:54:06.083804 fastboot data load
543 04:54:06.084050 fastboot data verify
544 04:54:06.088983 verify result: 266
545 04:54:06.094701 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 04:54:06.095201 LPDDR4 probe
547 04:54:06.095534 ddr clk to 1584MHz
548 04:54:06.102618 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 04:54:06.139908
550 04:54:06.140314 dmc_version 0001
551 04:54:06.146447 Check phy result
552 04:54:06.152297 INFO : End of CA training
553 04:54:06.152536 INFO : End of initialization
554 04:54:06.157894 INFO : Training has run successfully!
555 04:54:06.158155 Check phy result
556 04:54:06.163613 INFO : End of initialization
557 04:54:06.163858 INFO : End of read enable training
558 04:54:06.169176 INFO : End of fine write leveling
559 04:54:06.174772 INFO : End of Write leveling coarse delay
560 04:54:06.175271 INFO : Training has run successfully!
561 04:54:06.175726 Check phy result
562 04:54:06.180334 INFO : End of initialization
563 04:54:06.180830 INFO : End of read dq deskew training
564 04:54:06.185940 INFO : End of MPR read delay center optimization
565 04:54:06.191663 INFO : End of write delay center optimization
566 04:54:06.197165 INFO : End of read delay center optimization
567 04:54:06.197658 INFO : End of max read latency training
568 04:54:06.202753 INFO : Training has run successfully!
569 04:54:06.203241 1D training succeed
570 04:54:06.211922 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 04:54:06.259642 Check phy result
572 04:54:06.260178 INFO : End of initialization
573 04:54:06.282170 INFO : End of 2D read delay Voltage center optimization
574 04:54:06.302373 INFO : End of 2D read delay Voltage center optimization
575 04:54:06.354505 INFO : End of 2D write delay Voltage center optimization
576 04:54:06.403803 INFO : End of 2D write delay Voltage center optimization
577 04:54:06.409499 INFO : Training has run successfully!
578 04:54:06.409996
579 04:54:06.410455 channel==0
580 04:54:06.415183 RxClkDly_Margin_A0==88 ps 9
581 04:54:06.415802 TxDqDly_Margin_A0==98 ps 10
582 04:54:06.420674 RxClkDly_Margin_A1==88 ps 9
583 04:54:06.421200 TxDqDly_Margin_A1==98 ps 10
584 04:54:06.421667 TrainedVREFDQ_A0==74
585 04:54:06.426256 TrainedVREFDQ_A1==74
586 04:54:06.426809 VrefDac_Margin_A0==25
587 04:54:06.427275 DeviceVref_Margin_A0==40
588 04:54:06.431857 VrefDac_Margin_A1==25
589 04:54:06.432447 DeviceVref_Margin_A1==40
590 04:54:06.432911
591 04:54:06.433364
592 04:54:06.437400 channel==1
593 04:54:06.437886 RxClkDly_Margin_A0==98 ps 10
594 04:54:06.438336 TxDqDly_Margin_A0==88 ps 9
595 04:54:06.442973 RxClkDly_Margin_A1==98 ps 10
596 04:54:06.443457 TxDqDly_Margin_A1==88 ps 9
597 04:54:06.448571 TrainedVREFDQ_A0==77
598 04:54:06.449059 TrainedVREFDQ_A1==77
599 04:54:06.449514 VrefDac_Margin_A0==22
600 04:54:06.454175 DeviceVref_Margin_A0==37
601 04:54:06.454653 VrefDac_Margin_A1==24
602 04:54:06.459785 DeviceVref_Margin_A1==37
603 04:54:06.460297
604 04:54:06.460754 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 04:54:06.461204
606 04:54:06.493380 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000018 00000016 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
607 04:54:06.493942 2D training succeed
608 04:54:06.498956 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 04:54:06.504593 auto size-- 65535DDR cs0 size: 2048MB
610 04:54:06.505103 DDR cs1 size: 2048MB
611 04:54:06.510176 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 04:54:06.510673 cs0 DataBus test pass
613 04:54:06.515755 cs1 DataBus test pass
614 04:54:06.516306 cs0 AddrBus test pass
615 04:54:06.516764 cs1 AddrBus test pass
616 04:54:06.517209
617 04:54:06.521368 100bdlr_step_size ps== 420
618 04:54:06.521874 result report
619 04:54:06.526961 boot times 0Enable ddr reg access
620 04:54:06.532395 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 04:54:06.545827 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 04:54:07.119603 0.0;M3 CHK:0;cm4_sp_mode 0
623 04:54:07.120326 MVN_1=0x00000000
624 04:54:07.125014 MVN_2=0x00000000
625 04:54:07.130976 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 04:54:07.131540 OPS=0x10
627 04:54:07.132062 ring efuse init
628 04:54:07.132546 chipver efuse init
629 04:54:07.136497 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 04:54:07.142032 [0.018961 Inits done]
631 04:54:07.142535 secure task start!
632 04:54:07.142983 high task start!
633 04:54:07.146650 low task start!
634 04:54:07.147131 run into bl31
635 04:54:07.153300 NOTICE: BL31: v1.3(release):4fc40b1
636 04:54:07.161170 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 04:54:07.161659 NOTICE: BL31: G12A normal boot!
638 04:54:07.186520 NOTICE: BL31: BL33 decompress pass
639 04:54:07.192168 ERROR: Error initializing runtime service opteed_fast
640 04:54:08.425158
641 04:54:08.425841
642 04:54:08.433583 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 04:54:08.434126
644 04:54:08.434593 Model: Libre Computer AML-A311D-CC Alta
645 04:54:08.641869 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 04:54:08.665187 DRAM: 2 GiB (effective 3.8 GiB)
647 04:54:08.808169 Core: 408 devices, 31 uclasses, devicetree: separate
648 04:54:08.814165 WDT: Not starting watchdog@f0d0
649 04:54:08.846387 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 04:54:08.858782 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 04:54:08.863704 ** Bad device specification mmc 0 **
652 04:54:08.874072 Card did not respond to voltage select! : -110
653 04:54:08.881670 ** Bad device specification mmc 0 **
654 04:54:08.881986 Couldn't find partition mmc 0
655 04:54:08.890113 Card did not respond to voltage select! : -110
656 04:54:08.895510 ** Bad device specification mmc 0 **
657 04:54:08.895976 Couldn't find partition mmc 0
658 04:54:08.900663 Error: could not access storage.
659 04:54:09.243237 Net: eth0: ethernet@ff3f0000
660 04:54:09.243664 starting USB...
661 04:54:09.495550 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 04:54:09.500082 Starting the controller
663 04:54:09.504215 USB XHCI 1.10
664 04:54:11.213743 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 04:54:11.214454 bl2_stage_init 0x01
666 04:54:11.214940 bl2_stage_init 0x81
667 04:54:11.219448 hw id: 0x0000 - pwm id 0x01
668 04:54:11.219972 bl2_stage_init 0xc1
669 04:54:11.220502 bl2_stage_init 0x02
670 04:54:11.220961
671 04:54:11.224831 L0:00000000
672 04:54:11.225348 L1:20000703
673 04:54:11.225807 L2:00008067
674 04:54:11.226253 L3:14000000
675 04:54:11.230515 B2:00402000
676 04:54:11.231028 B1:e0f83180
677 04:54:11.231484
678 04:54:11.231934 TE: 58124
679 04:54:11.232426
680 04:54:11.236054 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 04:54:11.236571
682 04:54:11.237036 Board ID = 1
683 04:54:11.241631 Set A53 clk to 24M
684 04:54:11.242161 Set A73 clk to 24M
685 04:54:11.242617 Set clk81 to 24M
686 04:54:11.247340 A53 clk: 1200 MHz
687 04:54:11.247857 A73 clk: 1200 MHz
688 04:54:11.248355 CLK81: 166.6M
689 04:54:11.248812 smccc: 00012a91
690 04:54:11.252925 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 04:54:11.258760 board id: 1
692 04:54:11.264679 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 04:54:11.275192 fw parse done
694 04:54:11.281082 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 04:54:11.323613 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 04:54:11.334546 PIEI prepare done
697 04:54:11.335183 fastboot data load
698 04:54:11.335511 fastboot data verify
699 04:54:11.340193 verify result: 266
700 04:54:11.345738 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 04:54:11.346194 LPDDR4 probe
702 04:54:11.346495 ddr clk to 1584MHz
703 04:54:11.353766 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 04:54:11.391037
705 04:54:11.391705 dmc_version 0001
706 04:54:11.397681 Check phy result
707 04:54:11.403557 INFO : End of CA training
708 04:54:11.404195 INFO : End of initialization
709 04:54:11.412514 INFO : Training has run successfully!
710 04:54:11.412975 Check phy result
711 04:54:11.414851 INFO : End of initialization
712 04:54:11.415464 INFO : End of read enable training
713 04:54:11.418121 INFO : End of fine write leveling
714 04:54:11.423618 INFO : End of Write leveling coarse delay
715 04:54:11.429272 INFO : Training has run successfully!
716 04:54:11.429835 Check phy result
717 04:54:11.430272 INFO : End of initialization
718 04:54:11.434885 INFO : End of read dq deskew training
719 04:54:11.440477 INFO : End of MPR read delay center optimization
720 04:54:11.441024 INFO : End of write delay center optimization
721 04:54:11.446046 INFO : End of read delay center optimization
722 04:54:11.451626 INFO : End of max read latency training
723 04:54:11.452204 INFO : Training has run successfully!
724 04:54:11.457295 1D training succeed
725 04:54:11.463229 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 04:54:11.510772 Check phy result
727 04:54:11.511219 INFO : End of initialization
728 04:54:11.532343 INFO : End of 2D read delay Voltage center optimization
729 04:54:11.552462 INFO : End of 2D read delay Voltage center optimization
730 04:54:11.604522 INFO : End of 2D write delay Voltage center optimization
731 04:54:11.653688 INFO : End of 2D write delay Voltage center optimization
732 04:54:11.659224 INFO : Training has run successfully!
733 04:54:11.659768
734 04:54:11.660262 channel==0
735 04:54:11.664808 RxClkDly_Margin_A0==88 ps 9
736 04:54:11.665344 TxDqDly_Margin_A0==98 ps 10
737 04:54:11.668092 RxClkDly_Margin_A1==88 ps 9
738 04:54:11.668614 TxDqDly_Margin_A1==98 ps 10
739 04:54:11.673648 TrainedVREFDQ_A0==74
740 04:54:11.674182 TrainedVREFDQ_A1==74
741 04:54:11.679244 VrefDac_Margin_A0==25
742 04:54:11.679775 DeviceVref_Margin_A0==40
743 04:54:11.680236 VrefDac_Margin_A1==25
744 04:54:11.684866 DeviceVref_Margin_A1==40
745 04:54:11.685398
746 04:54:11.685824
747 04:54:11.686234 channel==1
748 04:54:11.686635 RxClkDly_Margin_A0==98 ps 10
749 04:54:11.690444 TxDqDly_Margin_A0==98 ps 10
750 04:54:11.690977 RxClkDly_Margin_A1==88 ps 9
751 04:54:11.696073 TxDqDly_Margin_A1==88 ps 9
752 04:54:11.696613 TrainedVREFDQ_A0==77
753 04:54:11.697033 TrainedVREFDQ_A1==77
754 04:54:11.701663 VrefDac_Margin_A0==22
755 04:54:11.702192 DeviceVref_Margin_A0==37
756 04:54:11.707233 VrefDac_Margin_A1==24
757 04:54:11.707772 DeviceVref_Margin_A1==37
758 04:54:11.708237
759 04:54:11.712726 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 04:54:11.713262
761 04:54:11.740667 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
762 04:54:11.746319 2D training succeed
763 04:54:11.752409 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 04:54:11.752916 auto size-- 65535DDR cs0 size: 2048MB
765 04:54:11.757494 DDR cs1 size: 2048MB
766 04:54:11.757979 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 04:54:11.763018 cs0 DataBus test pass
768 04:54:11.763484 cs1 DataBus test pass
769 04:54:11.763892 cs0 AddrBus test pass
770 04:54:11.768557 cs1 AddrBus test pass
771 04:54:11.769003
772 04:54:11.769412 100bdlr_step_size ps== 420
773 04:54:11.769828 result report
774 04:54:11.774162 boot times 0Enable ddr reg access
775 04:54:11.781866 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 04:54:11.795316 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 04:54:12.367542 0.0;M3 CHK:0;cm4_sp_mode 0
778 04:54:12.368270 MVN_1=0x00000000
779 04:54:12.372900 MVN_2=0x00000000
780 04:54:12.378645 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 04:54:12.379138 OPS=0x10
782 04:54:12.379552 ring efuse init
783 04:54:12.379951 chipver efuse init
784 04:54:12.384226 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 04:54:12.389842 [0.018961 Inits done]
786 04:54:12.390314 secure task start!
787 04:54:12.390715 high task start!
788 04:54:12.394400 low task start!
789 04:54:12.394854 run into bl31
790 04:54:12.401024 NOTICE: BL31: v1.3(release):4fc40b1
791 04:54:12.408841 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 04:54:12.409315 NOTICE: BL31: G12A normal boot!
793 04:54:12.434308 NOTICE: BL31: BL33 decompress pass
794 04:54:12.439903 ERROR: Error initializing runtime service opteed_fast
795 04:54:13.672852
796 04:54:13.673490
797 04:54:13.681196 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 04:54:13.681716
799 04:54:13.682141 Model: Libre Computer AML-A311D-CC Alta
800 04:54:13.889721 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 04:54:13.912251 DRAM: 2 GiB (effective 3.8 GiB)
802 04:54:14.056072 Core: 408 devices, 31 uclasses, devicetree: separate
803 04:54:14.061907 WDT: Not starting watchdog@f0d0
804 04:54:14.094216 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 04:54:14.106687 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 04:54:14.111632 ** Bad device specification mmc 0 **
807 04:54:14.121895 Card did not respond to voltage select! : -110
808 04:54:14.129532 ** Bad device specification mmc 0 **
809 04:54:14.130002 Couldn't find partition mmc 0
810 04:54:14.137879 Card did not respond to voltage select! : -110
811 04:54:14.143414 ** Bad device specification mmc 0 **
812 04:54:14.143870 Couldn't find partition mmc 0
813 04:54:14.147568 Error: could not access storage.
814 04:54:14.492074 Net: eth0: ethernet@ff3f0000
815 04:54:14.492675 starting USB...
816 04:54:14.743892 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 04:54:14.744532 Starting the controller
818 04:54:14.750122 USB XHCI 1.10
819 04:54:16.912230 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 04:54:16.912885 bl2_stage_init 0x01
821 04:54:16.913361 bl2_stage_init 0x81
822 04:54:16.917696 hw id: 0x0000 - pwm id 0x01
823 04:54:16.918236 bl2_stage_init 0xc1
824 04:54:16.918729 bl2_stage_init 0x02
825 04:54:16.919206
826 04:54:16.923322 L0:00000000
827 04:54:16.923856 L1:20000703
828 04:54:16.924360 L2:00008067
829 04:54:16.924811 L3:14000000
830 04:54:16.928976 B2:00402000
831 04:54:16.929508 B1:e0f83180
832 04:54:16.929971
833 04:54:16.930420 TE: 58159
834 04:54:16.930870
835 04:54:16.934566 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 04:54:16.935107
837 04:54:16.935567 Board ID = 1
838 04:54:16.940198 Set A53 clk to 24M
839 04:54:16.940729 Set A73 clk to 24M
840 04:54:16.941187 Set clk81 to 24M
841 04:54:16.945677 A53 clk: 1200 MHz
842 04:54:16.946201 A73 clk: 1200 MHz
843 04:54:16.946660 CLK81: 166.6M
844 04:54:16.947105 smccc: 00012ab5
845 04:54:16.951285 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 04:54:16.956876 board id: 1
847 04:54:16.961874 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 04:54:16.973538 fw parse done
849 04:54:16.978811 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 04:54:17.021390 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 04:54:17.032934 PIEI prepare done
852 04:54:17.033509 fastboot data load
853 04:54:17.034014 fastboot data verify
854 04:54:17.038507 verify result: 266
855 04:54:17.044155 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 04:54:17.044708 LPDDR4 probe
857 04:54:17.045174 ddr clk to 1584MHz
858 04:54:17.051334 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 04:54:17.088449
860 04:54:17.089037 dmc_version 0001
861 04:54:17.095897 Check phy result
862 04:54:17.101887 INFO : End of CA training
863 04:54:17.102436 INFO : End of initialization
864 04:54:17.107584 INFO : Training has run successfully!
865 04:54:17.108161 Check phy result
866 04:54:17.113159 INFO : End of initialization
867 04:54:17.113689 INFO : End of read enable training
868 04:54:17.118656 INFO : End of fine write leveling
869 04:54:17.124316 INFO : End of Write leveling coarse delay
870 04:54:17.124845 INFO : Training has run successfully!
871 04:54:17.125312 Check phy result
872 04:54:17.129886 INFO : End of initialization
873 04:54:17.130418 INFO : End of read dq deskew training
874 04:54:17.135455 INFO : End of MPR read delay center optimization
875 04:54:17.141150 INFO : End of write delay center optimization
876 04:54:17.146740 INFO : End of read delay center optimization
877 04:54:17.147289 INFO : End of max read latency training
878 04:54:17.152313 INFO : Training has run successfully!
879 04:54:17.152853 1D training succeed
880 04:54:17.160672 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 04:54:17.208565 Check phy result
882 04:54:17.209178 INFO : End of initialization
883 04:54:17.229753 INFO : End of 2D read delay Voltage center optimization
884 04:54:17.249886 INFO : End of 2D read delay Voltage center optimization
885 04:54:17.302096 INFO : End of 2D write delay Voltage center optimization
886 04:54:17.351923 INFO : End of 2D write delay Voltage center optimization
887 04:54:17.357552 INFO : Training has run successfully!
888 04:54:17.358089
889 04:54:17.358551 channel==0
890 04:54:17.363119 RxClkDly_Margin_A0==78 ps 8
891 04:54:17.363658 TxDqDly_Margin_A0==98 ps 10
892 04:54:17.368708 RxClkDly_Margin_A1==88 ps 9
893 04:54:17.369243 TxDqDly_Margin_A1==98 ps 10
894 04:54:17.369729 TrainedVREFDQ_A0==74
895 04:54:17.374393 TrainedVREFDQ_A1==74
896 04:54:17.374999 VrefDac_Margin_A0==25
897 04:54:17.375488 DeviceVref_Margin_A0==40
898 04:54:17.379866 VrefDac_Margin_A1==24
899 04:54:17.380470 DeviceVref_Margin_A1==40
900 04:54:17.380925
901 04:54:17.381532
902 04:54:17.385567 channel==1
903 04:54:17.386124 RxClkDly_Margin_A0==98 ps 10
904 04:54:17.386615 TxDqDly_Margin_A0==88 ps 9
905 04:54:17.391136 RxClkDly_Margin_A1==88 ps 9
906 04:54:17.391655 TxDqDly_Margin_A1==88 ps 9
907 04:54:17.396773 TrainedVREFDQ_A0==77
908 04:54:17.397307 TrainedVREFDQ_A1==77
909 04:54:17.397749 VrefDac_Margin_A0==22
910 04:54:17.402325 DeviceVref_Margin_A0==37
911 04:54:17.402860 VrefDac_Margin_A1==24
912 04:54:17.407883 DeviceVref_Margin_A1==37
913 04:54:17.408442
914 04:54:17.408885 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 04:54:17.409317
916 04:54:17.441495 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
917 04:54:17.442109 2D training succeed
918 04:54:17.447164 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 04:54:17.452726 auto size-- 65535DDR cs0 size: 2048MB
920 04:54:17.453252 DDR cs1 size: 2048MB
921 04:54:17.458268 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 04:54:17.458804 cs0 DataBus test pass
923 04:54:17.463892 cs1 DataBus test pass
924 04:54:17.464467 cs0 AddrBus test pass
925 04:54:17.464906 cs1 AddrBus test pass
926 04:54:17.465334
927 04:54:17.469501 100bdlr_step_size ps== 420
928 04:54:17.470040 result report
929 04:54:17.475201 boot times 0Enable ddr reg access
930 04:54:17.479517 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 04:54:17.493803 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 04:54:18.065735 0.0;M3 CHK:0;cm4_sp_mode 0
933 04:54:18.066413 MVN_1=0x00000000
934 04:54:18.071327 MVN_2=0x00000000
935 04:54:18.077123 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 04:54:18.077684 OPS=0x10
937 04:54:18.078149 ring efuse init
938 04:54:18.078656 chipver efuse init
939 04:54:18.085356 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 04:54:18.085980 [0.018961 Inits done]
941 04:54:18.092719 secure task start!
942 04:54:18.093318 high task start!
943 04:54:18.093790 low task start!
944 04:54:18.094249 run into bl31
945 04:54:18.099628 NOTICE: BL31: v1.3(release):4fc40b1
946 04:54:18.106526 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 04:54:18.107136 NOTICE: BL31: G12A normal boot!
948 04:54:18.132673 NOTICE: BL31: BL33 decompress pass
949 04:54:18.138617 ERROR: Error initializing runtime service opteed_fast
950 04:54:19.371224
951 04:54:19.371888
952 04:54:19.379518 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 04:54:19.380121
954 04:54:19.380612 Model: Libre Computer AML-A311D-CC Alta
955 04:54:19.587572 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 04:54:19.611176 DRAM: 2 GiB (effective 3.8 GiB)
957 04:54:19.754413 Core: 408 devices, 31 uclasses, devicetree: separate
958 04:54:19.760304 WDT: Not starting watchdog@f0d0
959 04:54:19.792561 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 04:54:19.804972 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 04:54:19.809482 ** Bad device specification mmc 0 **
962 04:54:19.820330 Card did not respond to voltage select! : -110
963 04:54:19.827017 ** Bad device specification mmc 0 **
964 04:54:19.827556 Couldn't find partition mmc 0
965 04:54:19.836278 Card did not respond to voltage select! : -110
966 04:54:19.841837 ** Bad device specification mmc 0 **
967 04:54:19.842361 Couldn't find partition mmc 0
968 04:54:19.846889 Error: could not access storage.
969 04:54:20.190394 Net: eth0: ethernet@ff3f0000
970 04:54:20.191025 starting USB...
971 04:54:20.442219 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 04:54:20.442811 Starting the controller
973 04:54:20.449225 USB XHCI 1.10
974 04:54:22.312132 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 04:54:22.312781 bl2_stage_init 0x01
976 04:54:22.313251 bl2_stage_init 0x81
977 04:54:22.317662 hw id: 0x0000 - pwm id 0x01
978 04:54:22.318177 bl2_stage_init 0xc1
979 04:54:22.318635 bl2_stage_init 0x02
980 04:54:22.319082
981 04:54:22.323267 L0:00000000
982 04:54:22.323776 L1:20000703
983 04:54:22.324285 L2:00008067
984 04:54:22.324736 L3:14000000
985 04:54:22.326208 B2:00402000
986 04:54:22.326711 B1:e0f83180
987 04:54:22.327165
988 04:54:22.327615 TE: 58159
989 04:54:22.328105
990 04:54:22.337360 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 04:54:22.337882
992 04:54:22.338338 Board ID = 1
993 04:54:22.338776 Set A53 clk to 24M
994 04:54:22.339213 Set A73 clk to 24M
995 04:54:22.342975 Set clk81 to 24M
996 04:54:22.343484 A53 clk: 1200 MHz
997 04:54:22.343940 A73 clk: 1200 MHz
998 04:54:22.346462 CLK81: 166.6M
999 04:54:22.346970 smccc: 00012ab5
1000 04:54:22.352204 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 04:54:22.357571 board id: 1
1002 04:54:22.362795 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 04:54:22.373200 fw parse done
1004 04:54:22.379232 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 04:54:22.421777 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 04:54:22.432691 PIEI prepare done
1007 04:54:22.433196 fastboot data load
1008 04:54:22.433634 fastboot data verify
1009 04:54:22.438297 verify result: 266
1010 04:54:22.444021 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 04:54:22.444535 LPDDR4 probe
1012 04:54:22.444975 ddr clk to 1584MHz
1013 04:54:22.451944 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 04:54:22.489091
1015 04:54:22.489603 dmc_version 0001
1016 04:54:22.495776 Check phy result
1017 04:54:22.501662 INFO : End of CA training
1018 04:54:22.502140 INFO : End of initialization
1019 04:54:22.507217 INFO : Training has run successfully!
1020 04:54:22.507660 Check phy result
1021 04:54:22.512972 INFO : End of initialization
1022 04:54:22.513440 INFO : End of read enable training
1023 04:54:22.518395 INFO : End of fine write leveling
1024 04:54:22.524003 INFO : End of Write leveling coarse delay
1025 04:54:22.524483 INFO : Training has run successfully!
1026 04:54:22.524906 Check phy result
1027 04:54:22.529579 INFO : End of initialization
1028 04:54:22.530037 INFO : End of read dq deskew training
1029 04:54:22.535153 INFO : End of MPR read delay center optimization
1030 04:54:22.540890 INFO : End of write delay center optimization
1031 04:54:22.546374 INFO : End of read delay center optimization
1032 04:54:22.546837 INFO : End of max read latency training
1033 04:54:22.551971 INFO : Training has run successfully!
1034 04:54:22.552490 1D training succeed
1035 04:54:22.561145 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 04:54:22.608819 Check phy result
1037 04:54:22.609378 INFO : End of initialization
1038 04:54:22.631322 INFO : End of 2D read delay Voltage center optimization
1039 04:54:22.651550 INFO : End of 2D read delay Voltage center optimization
1040 04:54:22.703607 INFO : End of 2D write delay Voltage center optimization
1041 04:54:22.752930 INFO : End of 2D write delay Voltage center optimization
1042 04:54:22.758532 INFO : Training has run successfully!
1043 04:54:22.759005
1044 04:54:22.759434 channel==0
1045 04:54:22.764152 RxClkDly_Margin_A0==88 ps 9
1046 04:54:22.764630 TxDqDly_Margin_A0==98 ps 10
1047 04:54:22.769790 RxClkDly_Margin_A1==88 ps 9
1048 04:54:22.770264 TxDqDly_Margin_A1==98 ps 10
1049 04:54:22.770688 TrainedVREFDQ_A0==74
1050 04:54:22.775330 TrainedVREFDQ_A1==75
1051 04:54:22.775799 VrefDac_Margin_A0==24
1052 04:54:22.776263 DeviceVref_Margin_A0==40
1053 04:54:22.780935 VrefDac_Margin_A1==24
1054 04:54:22.781420 DeviceVref_Margin_A1==39
1055 04:54:22.781843
1056 04:54:22.782253
1057 04:54:22.786522 channel==1
1058 04:54:22.786983 RxClkDly_Margin_A0==98 ps 10
1059 04:54:22.787401 TxDqDly_Margin_A0==98 ps 10
1060 04:54:22.792095 RxClkDly_Margin_A1==98 ps 10
1061 04:54:22.792554 TxDqDly_Margin_A1==88 ps 9
1062 04:54:22.797830 TrainedVREFDQ_A0==77
1063 04:54:22.798392 TrainedVREFDQ_A1==77
1064 04:54:22.798823 VrefDac_Margin_A0==22
1065 04:54:22.803326 DeviceVref_Margin_A0==37
1066 04:54:22.803794 VrefDac_Margin_A1==22
1067 04:54:22.808928 DeviceVref_Margin_A1==37
1068 04:54:22.809396
1069 04:54:22.809816 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 04:54:22.814538
1071 04:54:22.842538 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1072 04:54:22.843051 2D training succeed
1073 04:54:22.848153 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 04:54:22.853721 auto size-- 65535DDR cs0 size: 2048MB
1075 04:54:22.854196 DDR cs1 size: 2048MB
1076 04:54:22.859310 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 04:54:22.859773 cs0 DataBus test pass
1078 04:54:22.864945 cs1 DataBus test pass
1079 04:54:22.865403 cs0 AddrBus test pass
1080 04:54:22.865819 cs1 AddrBus test pass
1081 04:54:22.866227
1082 04:54:22.870523 100bdlr_step_size ps== 420
1083 04:54:22.871003 result report
1084 04:54:22.876151 boot times 0Enable ddr reg access
1085 04:54:22.881534 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 04:54:22.895064 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 04:54:23.468865 0.0;M3 CHK:0;cm4_sp_mode 0
1088 04:54:23.469478 MVN_1=0x00000000
1089 04:54:23.474293 MVN_2=0x00000000
1090 04:54:23.480102 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 04:54:23.480574 OPS=0x10
1092 04:54:23.480991 ring efuse init
1093 04:54:23.481400 chipver efuse init
1094 04:54:23.485645 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 04:54:23.491251 [0.018961 Inits done]
1096 04:54:23.491713 secure task start!
1097 04:54:23.492162 high task start!
1098 04:54:23.495833 low task start!
1099 04:54:23.496323 run into bl31
1100 04:54:23.502527 NOTICE: BL31: v1.3(release):4fc40b1
1101 04:54:23.510300 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 04:54:23.510779 NOTICE: BL31: G12A normal boot!
1103 04:54:23.535596 NOTICE: BL31: BL33 decompress pass
1104 04:54:23.541302 ERROR: Error initializing runtime service opteed_fast
1105 04:54:24.774199
1106 04:54:24.774822
1107 04:54:24.782550 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 04:54:24.783025
1109 04:54:24.783453 Model: Libre Computer AML-A311D-CC Alta
1110 04:54:24.990198 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 04:54:25.014452 DRAM: 2 GiB (effective 3.8 GiB)
1112 04:54:25.157343 Core: 408 devices, 31 uclasses, devicetree: separate
1113 04:54:25.162985 WDT: Not starting watchdog@f0d0
1114 04:54:25.195486 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 04:54:25.208046 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 04:54:25.212077 ** Bad device specification mmc 0 **
1117 04:54:25.223291 Card did not respond to voltage select! : -110
1118 04:54:25.230396 ** Bad device specification mmc 0 **
1119 04:54:25.230880 Couldn't find partition mmc 0
1120 04:54:25.239157 Card did not respond to voltage select! : -110
1121 04:54:25.244625 ** Bad device specification mmc 0 **
1122 04:54:25.245070 Couldn't find partition mmc 0
1123 04:54:25.249764 Error: could not access storage.
1124 04:54:25.592560 Net: eth0: ethernet@ff3f0000
1125 04:54:25.593188 starting USB...
1126 04:54:25.844053 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 04:54:25.844642 Starting the controller
1128 04:54:25.850492 USB XHCI 1.10
1129 04:54:27.405284 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 04:54:27.413753 scanning usb for storage devices... 0 Storage Device(s) found
1132 04:54:27.465384 Hit any key to stop autoboot: 1
1133 04:54:27.466245 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 04:54:27.466866 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 04:54:27.467333 Setting prompt string to ['=>']
1136 04:54:27.467812 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 04:54:27.480440 0
1138 04:54:27.481299 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 04:54:27.481792 Sending with 10 millisecond of delay
1141 04:54:28.616495 => setenv autoload no
1142 04:54:28.627305 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1143 04:54:28.632261 setenv autoload no
1144 04:54:28.633013 Sending with 10 millisecond of delay
1146 04:54:30.429804 => setenv initrd_high 0xffffffff
1147 04:54:30.440601 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 04:54:30.441457 setenv initrd_high 0xffffffff
1149 04:54:30.442164 Sending with 10 millisecond of delay
1151 04:54:32.059898 => setenv fdt_high 0xffffffff
1152 04:54:32.070846 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 04:54:32.071879 setenv fdt_high 0xffffffff
1154 04:54:32.072694 Sending with 10 millisecond of delay
1156 04:54:32.370293 => dhcp
1157 04:54:32.382689 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 04:54:32.383390 dhcp
1159 04:54:32.383664 Speed: 1000, full duplex
1160 04:54:32.383891 BOOTP broadcast 1
1161 04:54:32.389503 DHCP client bound to address 192.168.6.27 (8 ms)
1162 04:54:32.390338 Sending with 10 millisecond of delay
1164 04:54:34.074677 => setenv serverip 192.168.6.2
1165 04:54:34.085632 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 04:54:34.086687 setenv serverip 192.168.6.2
1167 04:54:34.087537 Sending with 10 millisecond of delay
1169 04:54:37.812285 => tftpboot 0x01080000 950953/tftp-deploy-kf9bz88k/kernel/uImage
1170 04:54:37.823096 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 04:54:37.823922 tftpboot 0x01080000 950953/tftp-deploy-kf9bz88k/kernel/uImage
1172 04:54:37.824412 Speed: 1000, full duplex
1173 04:54:37.824830 Using ethernet@ff3f0000 device
1174 04:54:37.825559 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 04:54:37.831077 Filename '950953/tftp-deploy-kf9bz88k/kernel/uImage'.
1176 04:54:37.835066 Load address: 0x1080000
1177 04:54:40.621546 Loading: *################################################## 43.6 MiB
1178 04:54:40.622359 15.6 MiB/s
1179 04:54:40.622948 done
1180 04:54:40.625846 Bytes transferred = 45713984 (2b98a40 hex)
1181 04:54:40.626837 Sending with 10 millisecond of delay
1183 04:54:45.314621 => tftpboot 0x08000000 950953/tftp-deploy-kf9bz88k/ramdisk/ramdisk.cpio.gz.uboot
1184 04:54:45.325416 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 04:54:45.326250 tftpboot 0x08000000 950953/tftp-deploy-kf9bz88k/ramdisk/ramdisk.cpio.gz.uboot
1186 04:54:45.326701 Speed: 1000, full duplex
1187 04:54:45.327117 Using ethernet@ff3f0000 device
1188 04:54:45.328038 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 04:54:45.339829 Filename '950953/tftp-deploy-kf9bz88k/ramdisk/ramdisk.cpio.gz.uboot'.
1190 04:54:45.340380 Load address: 0x8000000
1191 04:54:51.836966 Loading: *####################T ############################# UDP wrong checksum 00000005 000034da
1192 04:54:56.837590 T UDP wrong checksum 00000005 000034da
1193 04:55:03.591523 T UDP wrong checksum 000000ff 00007452
1194 04:55:03.600423 UDP wrong checksum 000000ff 00000145
1195 04:55:06.841158 T UDP wrong checksum 00000005 000034da
1196 04:55:26.845183 T T T T UDP wrong checksum 00000005 000034da
1197 04:55:41.849286 T T
1198 04:55:41.849969 Retry count exceeded; starting again
1200 04:55:41.851526 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1203 04:55:41.853682 end: 2.4 uboot-commands (duration 00:01:52) [common]
1205 04:55:41.855390 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1207 04:55:41.856556 end: 2 uboot-action (duration 00:01:52) [common]
1209 04:55:41.858219 Cleaning after the job
1210 04:55:41.858816 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/ramdisk
1211 04:55:41.860304 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/kernel
1212 04:55:41.909160 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/dtb
1213 04:55:41.910010 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/nfsrootfs
1214 04:55:42.075108 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950953/tftp-deploy-kf9bz88k/modules
1215 04:55:42.097062 start: 4.1 power-off (timeout 00:00:30) [common]
1216 04:55:42.097730 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1217 04:55:42.131587 >> OK - accepted request
1218 04:55:42.133764 Returned 0 in 0 seconds
1219 04:55:42.234468 end: 4.1 power-off (duration 00:00:00) [common]
1221 04:55:42.235352 start: 4.2 read-feedback (timeout 00:10:00) [common]
1222 04:55:42.235968 Listened to connection for namespace 'common' for up to 1s
1223 04:55:43.236910 Finalising connection for namespace 'common'
1224 04:55:43.237401 Disconnecting from shell: Finalise
1225 04:55:43.237688 =>
1226 04:55:43.338462 end: 4.2 read-feedback (duration 00:00:01) [common]
1227 04:55:43.339053 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950953
1228 04:55:46.272671 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950953
1229 04:55:46.273308 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.