Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:41:50.716506 lava-dispatcher, installed at version: 2024.01
2 04:41:50.717423 start: 0 validate
3 04:41:50.717911 Start time: 2024-11-07 04:41:50.717882+00:00 (UTC)
4 04:41:50.718468 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:41:50.719033 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 04:41:50.763957 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:41:50.764607 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-235-gf366870b9966d%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 04:41:50.796099 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:41:50.796801 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-235-gf366870b9966d%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:41:50.829242 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:41:50.829769 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:41:50.862622 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 04:41:50.863140 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-235-gf366870b9966d%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 04:41:50.900544 validate duration: 0.18
16 04:41:50.901400 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:41:50.901733 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:41:50.902060 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:41:50.902647 Not decompressing ramdisk as can be used compressed.
20 04:41:50.903121 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 04:41:50.903415 saving as /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/ramdisk/initrd.cpio.gz
22 04:41:50.903693 total size: 5628169 (5 MB)
23 04:41:50.940011 progress 0 % (0 MB)
24 04:41:50.948004 progress 5 % (0 MB)
25 04:41:50.956654 progress 10 % (0 MB)
26 04:41:50.961324 progress 15 % (0 MB)
27 04:41:50.965793 progress 20 % (1 MB)
28 04:41:50.969748 progress 25 % (1 MB)
29 04:41:50.974019 progress 30 % (1 MB)
30 04:41:50.978389 progress 35 % (1 MB)
31 04:41:50.982281 progress 40 % (2 MB)
32 04:41:50.986513 progress 45 % (2 MB)
33 04:41:50.990533 progress 50 % (2 MB)
34 04:41:50.994793 progress 55 % (2 MB)
35 04:41:50.999032 progress 60 % (3 MB)
36 04:41:51.002824 progress 65 % (3 MB)
37 04:41:51.007140 progress 70 % (3 MB)
38 04:41:51.010939 progress 75 % (4 MB)
39 04:41:51.015176 progress 80 % (4 MB)
40 04:41:51.018991 progress 85 % (4 MB)
41 04:41:51.023240 progress 90 % (4 MB)
42 04:41:51.027502 progress 95 % (5 MB)
43 04:41:51.030968 progress 100 % (5 MB)
44 04:41:51.031665 5 MB downloaded in 0.13 s (41.95 MB/s)
45 04:41:51.032245 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:41:51.033168 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:41:51.033466 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:41:51.033740 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:41:51.034213 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/kernel/Image
51 04:41:51.034504 saving as /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/kernel/Image
52 04:41:51.034723 total size: 45713920 (43 MB)
53 04:41:51.034937 No compression specified
54 04:41:51.067711 progress 0 % (0 MB)
55 04:41:51.096089 progress 5 % (2 MB)
56 04:41:51.124210 progress 10 % (4 MB)
57 04:41:51.152542 progress 15 % (6 MB)
58 04:41:51.180950 progress 20 % (8 MB)
59 04:41:51.208875 progress 25 % (10 MB)
60 04:41:51.237262 progress 30 % (13 MB)
61 04:41:51.265303 progress 35 % (15 MB)
62 04:41:51.293427 progress 40 % (17 MB)
63 04:41:51.321158 progress 45 % (19 MB)
64 04:41:51.349505 progress 50 % (21 MB)
65 04:41:51.377644 progress 55 % (24 MB)
66 04:41:51.405626 progress 60 % (26 MB)
67 04:41:51.433859 progress 65 % (28 MB)
68 04:41:51.461961 progress 70 % (30 MB)
69 04:41:51.490013 progress 75 % (32 MB)
70 04:41:51.519967 progress 80 % (34 MB)
71 04:41:51.548073 progress 85 % (37 MB)
72 04:41:51.576250 progress 90 % (39 MB)
73 04:41:51.604067 progress 95 % (41 MB)
74 04:41:51.631901 progress 100 % (43 MB)
75 04:41:51.632501 43 MB downloaded in 0.60 s (72.93 MB/s)
76 04:41:51.632979 end: 1.2.1 http-download (duration 00:00:01) [common]
78 04:41:51.633803 end: 1.2 download-retry (duration 00:00:01) [common]
79 04:41:51.634080 start: 1.3 download-retry (timeout 00:09:59) [common]
80 04:41:51.634348 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 04:41:51.634830 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 04:41:51.635117 saving as /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/dtb/meson-g12b-a311d-libretech-cc.dtb
83 04:41:51.635329 total size: 54703 (0 MB)
84 04:41:51.635539 No compression specified
85 04:41:51.681261 progress 59 % (0 MB)
86 04:41:51.682106 progress 100 % (0 MB)
87 04:41:51.682650 0 MB downloaded in 0.05 s (1.10 MB/s)
88 04:41:51.683111 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:41:51.683933 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:41:51.684254 start: 1.4 download-retry (timeout 00:09:59) [common]
92 04:41:51.684523 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 04:41:51.684987 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 04:41:51.685234 saving as /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/nfsrootfs/full.rootfs.tar
95 04:41:51.685441 total size: 120894716 (115 MB)
96 04:41:51.685653 Using unxz to decompress xz
97 04:41:51.722999 progress 0 % (0 MB)
98 04:41:52.525729 progress 5 % (5 MB)
99 04:41:53.403796 progress 10 % (11 MB)
100 04:41:54.197519 progress 15 % (17 MB)
101 04:41:54.935030 progress 20 % (23 MB)
102 04:41:55.527023 progress 25 % (28 MB)
103 04:41:56.350874 progress 30 % (34 MB)
104 04:41:57.143749 progress 35 % (40 MB)
105 04:41:57.493551 progress 40 % (46 MB)
106 04:41:57.867637 progress 45 % (51 MB)
107 04:41:58.595248 progress 50 % (57 MB)
108 04:41:59.489385 progress 55 % (63 MB)
109 04:42:00.347460 progress 60 % (69 MB)
110 04:42:01.121752 progress 65 % (74 MB)
111 04:42:01.911631 progress 70 % (80 MB)
112 04:42:02.777981 progress 75 % (86 MB)
113 04:42:03.716331 progress 80 % (92 MB)
114 04:42:04.625933 progress 85 % (98 MB)
115 04:42:05.643726 progress 90 % (103 MB)
116 04:42:06.429943 progress 95 % (109 MB)
117 04:42:07.262776 progress 100 % (115 MB)
118 04:42:07.275265 115 MB downloaded in 15.59 s (7.40 MB/s)
119 04:42:07.276309 end: 1.4.1 http-download (duration 00:00:16) [common]
121 04:42:07.278077 end: 1.4 download-retry (duration 00:00:16) [common]
122 04:42:07.278638 start: 1.5 download-retry (timeout 00:09:44) [common]
123 04:42:07.279190 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 04:42:07.280057 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/modules.tar.xz
125 04:42:07.280556 saving as /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/modules/modules.tar
126 04:42:07.280995 total size: 11607584 (11 MB)
127 04:42:07.281449 Using unxz to decompress xz
128 04:42:07.325981 progress 0 % (0 MB)
129 04:42:07.392235 progress 5 % (0 MB)
130 04:42:07.467366 progress 10 % (1 MB)
131 04:42:07.563562 progress 15 % (1 MB)
132 04:42:07.655967 progress 20 % (2 MB)
133 04:42:07.736718 progress 25 % (2 MB)
134 04:42:07.813051 progress 30 % (3 MB)
135 04:42:07.886428 progress 35 % (3 MB)
136 04:42:07.962843 progress 40 % (4 MB)
137 04:42:08.039602 progress 45 % (5 MB)
138 04:42:08.123076 progress 50 % (5 MB)
139 04:42:08.199479 progress 55 % (6 MB)
140 04:42:08.283737 progress 60 % (6 MB)
141 04:42:08.363956 progress 65 % (7 MB)
142 04:42:08.440345 progress 70 % (7 MB)
143 04:42:08.522937 progress 75 % (8 MB)
144 04:42:08.606535 progress 80 % (8 MB)
145 04:42:08.686043 progress 85 % (9 MB)
146 04:42:08.764172 progress 90 % (9 MB)
147 04:42:08.843091 progress 95 % (10 MB)
148 04:42:08.922533 progress 100 % (11 MB)
149 04:42:08.933513 11 MB downloaded in 1.65 s (6.70 MB/s)
150 04:42:08.934261 end: 1.5.1 http-download (duration 00:00:02) [common]
152 04:42:08.936218 end: 1.5 download-retry (duration 00:00:02) [common]
153 04:42:08.936837 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 04:42:08.937432 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 04:42:26.500705 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/950936/extract-nfsrootfs-vzpqsnqd
156 04:42:26.501300 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
157 04:42:26.501649 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
158 04:42:26.502396 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu
159 04:42:26.502924 makedir: /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin
160 04:42:26.503343 makedir: /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/tests
161 04:42:26.503781 makedir: /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/results
162 04:42:26.504206 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-add-keys
163 04:42:26.504840 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-add-sources
164 04:42:26.505439 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-background-process-start
165 04:42:26.506037 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-background-process-stop
166 04:42:26.506659 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-common-functions
167 04:42:26.507250 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-echo-ipv4
168 04:42:26.507826 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-install-packages
169 04:42:26.508456 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-installed-packages
170 04:42:26.509030 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-os-build
171 04:42:26.509580 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-probe-channel
172 04:42:26.510149 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-probe-ip
173 04:42:26.510712 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-target-ip
174 04:42:26.511282 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-target-mac
175 04:42:26.511847 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-target-storage
176 04:42:26.512460 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-test-case
177 04:42:26.513044 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-test-event
178 04:42:26.513618 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-test-feedback
179 04:42:26.514195 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-test-raise
180 04:42:26.514754 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-test-reference
181 04:42:26.515322 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-test-runner
182 04:42:26.515909 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-test-set
183 04:42:26.516506 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-test-shell
184 04:42:26.517049 Updating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-add-keys (debian)
185 04:42:26.517612 Updating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-add-sources (debian)
186 04:42:26.518128 Updating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-install-packages (debian)
187 04:42:26.518638 Updating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-installed-packages (debian)
188 04:42:26.519211 Updating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/bin/lava-os-build (debian)
189 04:42:26.519679 Creating /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/environment
190 04:42:26.520116 LAVA metadata
191 04:42:26.520400 - LAVA_JOB_ID=950936
192 04:42:26.520624 - LAVA_DISPATCHER_IP=192.168.6.2
193 04:42:26.521020 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
194 04:42:26.522129 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 04:42:26.522466 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
196 04:42:26.522677 skipped lava-vland-overlay
197 04:42:26.522919 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 04:42:26.523175 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
199 04:42:26.523397 skipped lava-multinode-overlay
200 04:42:26.523640 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 04:42:26.523890 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
202 04:42:26.524175 Loading test definitions
203 04:42:26.524461 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
204 04:42:26.524684 Using /lava-950936 at stage 0
205 04:42:26.525801 uuid=950936_1.6.2.4.1 testdef=None
206 04:42:26.526122 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 04:42:26.526389 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
208 04:42:26.528058 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 04:42:26.528881 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
211 04:42:26.530885 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 04:42:26.531737 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
214 04:42:26.533676 runner path: /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/0/tests/0_timesync-off test_uuid 950936_1.6.2.4.1
215 04:42:26.534254 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 04:42:26.535073 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
218 04:42:26.535301 Using /lava-950936 at stage 0
219 04:42:26.535659 Fetching tests from https://github.com/kernelci/test-definitions.git
220 04:42:26.535954 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/0/tests/1_kselftest-rtc'
221 04:42:30.065961 Running '/usr/bin/git checkout kernelci.org
222 04:42:30.195835 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 04:42:30.198612 uuid=950936_1.6.2.4.5 testdef=None
224 04:42:30.199338 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 04:42:30.201017 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 04:42:30.207282 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 04:42:30.209173 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 04:42:30.217424 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 04:42:30.219334 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 04:42:30.227416 runner path: /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/0/tests/1_kselftest-rtc test_uuid 950936_1.6.2.4.5
234 04:42:30.228089 BOARD='meson-g12b-a311d-libretech-cc'
235 04:42:30.228581 BRANCH='broonie-sound'
236 04:42:30.229028 SKIPFILE='/dev/null'
237 04:42:30.229473 SKIP_INSTALL='True'
238 04:42:30.229910 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-235-gf366870b9966d/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 04:42:30.230356 TST_CASENAME=''
240 04:42:30.230793 TST_CMDFILES='rtc'
241 04:42:30.231960 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 04:42:30.233757 Creating lava-test-runner.conf files
244 04:42:30.234209 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950936/lava-overlay-j6_snimu/lava-950936/0 for stage 0
245 04:42:30.234925 - 0_timesync-off
246 04:42:30.235439 - 1_kselftest-rtc
247 04:42:30.236166 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 04:42:30.236777 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 04:42:53.546932 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 04:42:53.547392 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 04:42:53.547660 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 04:42:53.547934 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 04:42:53.548246 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 04:42:54.202683 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 04:42:54.203154 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 04:42:54.203429 extracting modules file /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950936/extract-nfsrootfs-vzpqsnqd
257 04:42:55.555709 extracting modules file /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950936/extract-overlay-ramdisk-l25e4z67/ramdisk
258 04:42:57.119373 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 04:42:57.120088 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 04:42:57.120424 [common] Applying overlay to NFS
261 04:42:57.120701 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950936/compress-overlay-j2o1hnva/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950936/extract-nfsrootfs-vzpqsnqd
262 04:43:00.311667 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 04:43:00.312316 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 04:43:00.312724 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 04:43:00.313054 Converting downloaded kernel to a uImage
266 04:43:00.313452 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/kernel/Image /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/kernel/uImage
267 04:43:00.786166 output: Image Name:
268 04:43:00.786591 output: Created: Thu Nov 7 04:43:00 2024
269 04:43:00.786805 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 04:43:00.787015 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 04:43:00.787220 output: Load Address: 01080000
272 04:43:00.787422 output: Entry Point: 01080000
273 04:43:00.787622 output:
274 04:43:00.787956 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 04:43:00.788279 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 04:43:00.788555 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 04:43:00.788812 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 04:43:00.789074 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 04:43:00.789335 Building ramdisk /var/lib/lava/dispatcher/tmp/950936/extract-overlay-ramdisk-l25e4z67/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950936/extract-overlay-ramdisk-l25e4z67/ramdisk
280 04:43:02.909621 >> 166792 blocks
281 04:43:10.605215 Adding RAMdisk u-boot header.
282 04:43:10.605660 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950936/extract-overlay-ramdisk-l25e4z67/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950936/extract-overlay-ramdisk-l25e4z67/ramdisk.cpio.gz.uboot
283 04:43:10.925188 output: Image Name:
284 04:43:10.925631 output: Created: Thu Nov 7 04:43:10 2024
285 04:43:10.925848 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 04:43:10.926056 output: Data Size: 23431765 Bytes = 22882.58 KiB = 22.35 MiB
287 04:43:10.926262 output: Load Address: 00000000
288 04:43:10.926465 output: Entry Point: 00000000
289 04:43:10.926668 output:
290 04:43:10.927368 rename /var/lib/lava/dispatcher/tmp/950936/extract-overlay-ramdisk-l25e4z67/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/ramdisk/ramdisk.cpio.gz.uboot
291 04:43:10.927837 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 04:43:10.928313 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 04:43:10.928902 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 04:43:10.929358 No LXC device requested
295 04:43:10.929863 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 04:43:10.930379 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 04:43:10.930876 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 04:43:10.931290 Checking files for TFTP limit of 4294967296 bytes.
299 04:43:10.934044 end: 1 tftp-deploy (duration 00:01:20) [common]
300 04:43:10.934673 start: 2 uboot-action (timeout 00:05:00) [common]
301 04:43:10.935205 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 04:43:10.935706 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 04:43:10.936257 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 04:43:10.936804 Using kernel file from prepare-kernel: 950936/tftp-deploy-bdspo4ot/kernel/uImage
305 04:43:10.937447 substitutions:
306 04:43:10.937878 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 04:43:10.938286 - {DTB_ADDR}: 0x01070000
308 04:43:10.938695 - {DTB}: 950936/tftp-deploy-bdspo4ot/dtb/meson-g12b-a311d-libretech-cc.dtb
309 04:43:10.939102 - {INITRD}: 950936/tftp-deploy-bdspo4ot/ramdisk/ramdisk.cpio.gz.uboot
310 04:43:10.939503 - {KERNEL_ADDR}: 0x01080000
311 04:43:10.939903 - {KERNEL}: 950936/tftp-deploy-bdspo4ot/kernel/uImage
312 04:43:10.940340 - {LAVA_MAC}: None
313 04:43:10.940787 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/950936/extract-nfsrootfs-vzpqsnqd
314 04:43:10.941196 - {NFS_SERVER_IP}: 192.168.6.2
315 04:43:10.941595 - {PRESEED_CONFIG}: None
316 04:43:10.941992 - {PRESEED_LOCAL}: None
317 04:43:10.942389 - {RAMDISK_ADDR}: 0x08000000
318 04:43:10.942783 - {RAMDISK}: 950936/tftp-deploy-bdspo4ot/ramdisk/ramdisk.cpio.gz.uboot
319 04:43:10.943180 - {ROOT_PART}: None
320 04:43:10.943571 - {ROOT}: None
321 04:43:10.943962 - {SERVER_IP}: 192.168.6.2
322 04:43:10.944387 - {TEE_ADDR}: 0x83000000
323 04:43:10.944778 - {TEE}: None
324 04:43:10.945173 Parsed boot commands:
325 04:43:10.945556 - setenv autoload no
326 04:43:10.945945 - setenv initrd_high 0xffffffff
327 04:43:10.946336 - setenv fdt_high 0xffffffff
328 04:43:10.946726 - dhcp
329 04:43:10.947112 - setenv serverip 192.168.6.2
330 04:43:10.947503 - tftpboot 0x01080000 950936/tftp-deploy-bdspo4ot/kernel/uImage
331 04:43:10.947899 - tftpboot 0x08000000 950936/tftp-deploy-bdspo4ot/ramdisk/ramdisk.cpio.gz.uboot
332 04:43:10.948321 - tftpboot 0x01070000 950936/tftp-deploy-bdspo4ot/dtb/meson-g12b-a311d-libretech-cc.dtb
333 04:43:10.948719 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950936/extract-nfsrootfs-vzpqsnqd,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 04:43:10.949123 - bootm 0x01080000 0x08000000 0x01070000
335 04:43:10.949643 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 04:43:10.951160 start: 2.3 connect-device (timeout 00:05:00) [common]
338 04:43:10.951589 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 04:43:10.967528 Setting prompt string to ['lava-test: # ']
340 04:43:10.969279 end: 2.3 connect-device (duration 00:00:00) [common]
341 04:43:10.969909 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 04:43:10.970483 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 04:43:10.971029 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 04:43:10.972230 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 04:43:11.010179 >> OK - accepted request
346 04:43:11.012517 Returned 0 in 0 seconds
347 04:43:11.113788 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 04:43:11.115526 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 04:43:11.116149 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 04:43:11.116694 Setting prompt string to ['Hit any key to stop autoboot']
352 04:43:11.117155 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 04:43:11.118831 Trying 192.168.56.21...
354 04:43:11.119341 Connected to conserv1.
355 04:43:11.119748 Escape character is '^]'.
356 04:43:11.120211
357 04:43:11.120633 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 04:43:11.121065
359 04:43:23.357858 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 04:43:23.358656 bl2_stage_init 0x01
361 04:43:23.359209 bl2_stage_init 0x81
362 04:43:23.363423 hw id: 0x0000 - pwm id 0x01
363 04:43:23.364128 bl2_stage_init 0xc1
364 04:43:23.364735 bl2_stage_init 0x02
365 04:43:23.365305
366 04:43:23.368992 L0:00000000
367 04:43:23.369615 L1:20000703
368 04:43:23.370150 L2:00008067
369 04:43:23.370687 L3:14000000
370 04:43:23.371943 B2:00402000
371 04:43:23.372578 B1:e0f83180
372 04:43:23.373122
373 04:43:23.373643 TE: 58159
374 04:43:23.374154
375 04:43:23.383095 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 04:43:23.383683
377 04:43:23.384303 Board ID = 1
378 04:43:23.384815 Set A53 clk to 24M
379 04:43:23.385338 Set A73 clk to 24M
380 04:43:23.388775 Set clk81 to 24M
381 04:43:23.389354 A53 clk: 1200 MHz
382 04:43:23.389869 A73 clk: 1200 MHz
383 04:43:23.392164 CLK81: 166.6M
384 04:43:23.392717 smccc: 00012ab5
385 04:43:23.397679 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 04:43:23.403250 board id: 1
387 04:43:23.407543 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 04:43:23.419134 fw parse done
389 04:43:23.424106 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 04:43:23.467641 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 04:43:23.478996 PIEI prepare done
392 04:43:23.479770 fastboot data load
393 04:43:23.480514 fastboot data verify
394 04:43:23.484609 verify result: 266
395 04:43:23.490089 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 04:43:23.490510 LPDDR4 probe
397 04:43:23.490769 ddr clk to 1584MHz
398 04:43:23.497990 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 04:43:23.534348
400 04:43:23.535260 dmc_version 0001
401 04:43:23.542487 Check phy result
402 04:43:23.547757 INFO : End of CA training
403 04:43:23.548317 INFO : End of initialization
404 04:43:23.553279 INFO : Training has run successfully!
405 04:43:23.553653 Check phy result
406 04:43:23.558886 INFO : End of initialization
407 04:43:23.559270 INFO : End of read enable training
408 04:43:23.564513 INFO : End of fine write leveling
409 04:43:23.569991 INFO : End of Write leveling coarse delay
410 04:43:23.570425 INFO : Training has run successfully!
411 04:43:23.570688 Check phy result
412 04:43:23.575604 INFO : End of initialization
413 04:43:23.575961 INFO : End of read dq deskew training
414 04:43:23.581283 INFO : End of MPR read delay center optimization
415 04:43:23.586881 INFO : End of write delay center optimization
416 04:43:23.592655 INFO : End of read delay center optimization
417 04:43:23.593021 INFO : End of max read latency training
418 04:43:23.598358 INFO : Training has run successfully!
419 04:43:23.598689 1D training succeed
420 04:43:23.606275 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 04:43:23.654006 Check phy result
422 04:43:23.654423 INFO : End of initialization
423 04:43:23.675542 INFO : End of 2D read delay Voltage center optimization
424 04:43:23.695464 INFO : End of 2D read delay Voltage center optimization
425 04:43:23.747527 INFO : End of 2D write delay Voltage center optimization
426 04:43:23.797697 INFO : End of 2D write delay Voltage center optimization
427 04:43:23.803196 INFO : Training has run successfully!
428 04:43:23.803681
429 04:43:23.804171 channel==0
430 04:43:23.808806 RxClkDly_Margin_A0==88 ps 9
431 04:43:23.809278 TxDqDly_Margin_A0==98 ps 10
432 04:43:23.812073 RxClkDly_Margin_A1==88 ps 9
433 04:43:23.812566 TxDqDly_Margin_A1==98 ps 10
434 04:43:23.817690 TrainedVREFDQ_A0==74
435 04:43:23.818175 TrainedVREFDQ_A1==74
436 04:43:23.823264 VrefDac_Margin_A0==25
437 04:43:23.823741 DeviceVref_Margin_A0==40
438 04:43:23.824221 VrefDac_Margin_A1==25
439 04:43:23.829196 DeviceVref_Margin_A1==40
440 04:43:23.829672
441 04:43:23.830120
442 04:43:23.830562 channel==1
443 04:43:23.831001 RxClkDly_Margin_A0==98 ps 10
444 04:43:23.832301 TxDqDly_Margin_A0==88 ps 9
445 04:43:23.837930 RxClkDly_Margin_A1==98 ps 10
446 04:43:23.838419 TxDqDly_Margin_A1==88 ps 9
447 04:43:23.838869 TrainedVREFDQ_A0==76
448 04:43:23.843486 TrainedVREFDQ_A1==77
449 04:43:23.843971 VrefDac_Margin_A0==22
450 04:43:23.849077 DeviceVref_Margin_A0==38
451 04:43:23.849559 VrefDac_Margin_A1==24
452 04:43:23.850006 DeviceVref_Margin_A1==37
453 04:43:23.850445
454 04:43:23.854714 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 04:43:23.855185
456 04:43:23.888219 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 04:43:23.888779 2D training succeed
458 04:43:23.893829 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 04:43:23.899532 auto size-- 65535DDR cs0 size: 2048MB
460 04:43:23.900043 DDR cs1 size: 2048MB
461 04:43:23.905032 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 04:43:23.905515 cs0 DataBus test pass
463 04:43:23.905960 cs1 DataBus test pass
464 04:43:23.910787 cs0 AddrBus test pass
465 04:43:23.911269 cs1 AddrBus test pass
466 04:43:23.911710
467 04:43:23.916260 100bdlr_step_size ps== 420
468 04:43:23.916745 result report
469 04:43:23.917181 boot times 0Enable ddr reg access
470 04:43:23.925826 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 04:43:23.939421 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 04:43:24.511641 0.0;M3 CHK:0;cm4_sp_mode 0
473 04:43:24.512333 MVN_1=0x00000000
474 04:43:24.517142 MVN_2=0x00000000
475 04:43:24.522894 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 04:43:24.523460 OPS=0x10
477 04:43:24.523931 ring efuse init
478 04:43:24.524425 chipver efuse init
479 04:43:24.531107 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 04:43:24.531657 [0.018960 Inits done]
481 04:43:24.538338 secure task start!
482 04:43:24.538907 high task start!
483 04:43:24.539362 low task start!
484 04:43:24.539807 run into bl31
485 04:43:24.545364 NOTICE: BL31: v1.3(release):4fc40b1
486 04:43:24.552707 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 04:43:24.553286 NOTICE: BL31: G12A normal boot!
488 04:43:24.578567 NOTICE: BL31: BL33 decompress pass
489 04:43:24.583245 ERROR: Error initializing runtime service opteed_fast
490 04:43:25.817126
491 04:43:25.817789
492 04:43:25.824790 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 04:43:25.825300
494 04:43:25.825764 Model: Libre Computer AML-A311D-CC Alta
495 04:43:26.033078 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 04:43:26.056519 DRAM: 2 GiB (effective 3.8 GiB)
497 04:43:26.200298 Core: 408 devices, 31 uclasses, devicetree: separate
498 04:43:26.205593 WDT: Not starting watchdog@f0d0
499 04:43:26.238326 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 04:43:26.250858 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 04:43:26.254862 ** Bad device specification mmc 0 **
502 04:43:26.266174 Card did not respond to voltage select! : -110
503 04:43:26.273337 ** Bad device specification mmc 0 **
504 04:43:26.273830 Couldn't find partition mmc 0
505 04:43:26.282103 Card did not respond to voltage select! : -110
506 04:43:26.287659 ** Bad device specification mmc 0 **
507 04:43:26.288195 Couldn't find partition mmc 0
508 04:43:26.291730 Error: could not access storage.
509 04:43:27.559014 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 04:43:27.559654 bl2_stage_init 0x01
511 04:43:27.560229 bl2_stage_init 0x81
512 04:43:27.564612 hw id: 0x0000 - pwm id 0x01
513 04:43:27.565127 bl2_stage_init 0xc1
514 04:43:27.565592 bl2_stage_init 0x02
515 04:43:27.566046
516 04:43:27.570176 L0:00000000
517 04:43:27.570663 L1:20000703
518 04:43:27.571119 L2:00008067
519 04:43:27.571569 L3:14000000
520 04:43:27.573152 B2:00402000
521 04:43:27.573634 B1:e0f83180
522 04:43:27.574085
523 04:43:27.574532 TE: 58159
524 04:43:27.574982
525 04:43:27.584320 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 04:43:27.584850
527 04:43:27.585312 Board ID = 1
528 04:43:27.585762 Set A53 clk to 24M
529 04:43:27.586209 Set A73 clk to 24M
530 04:43:27.589904 Set clk81 to 24M
531 04:43:27.590387 A53 clk: 1200 MHz
532 04:43:27.590842 A73 clk: 1200 MHz
533 04:43:27.595507 CLK81: 166.6M
534 04:43:27.596007 smccc: 00012ab5
535 04:43:27.601115 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 04:43:27.601601 board id: 1
537 04:43:27.609477 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 04:43:27.620316 fw parse done
539 04:43:27.625886 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 04:43:27.668824 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 04:43:27.679768 PIEI prepare done
542 04:43:27.680369 fastboot data load
543 04:43:27.680861 fastboot data verify
544 04:43:27.685458 verify result: 266
545 04:43:27.691018 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 04:43:27.691539 LPDDR4 probe
547 04:43:27.692043 ddr clk to 1584MHz
548 04:43:27.698656 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 04:43:27.735511
550 04:43:27.736083 dmc_version 0001
551 04:43:27.742008 Check phy result
552 04:43:27.748811 INFO : End of CA training
553 04:43:27.749322 INFO : End of initialization
554 04:43:27.754534 INFO : Training has run successfully!
555 04:43:27.755037 Check phy result
556 04:43:27.760060 INFO : End of initialization
557 04:43:27.760538 INFO : End of read enable training
558 04:43:27.765656 INFO : End of fine write leveling
559 04:43:27.771332 INFO : End of Write leveling coarse delay
560 04:43:27.771808 INFO : Training has run successfully!
561 04:43:27.772284 Check phy result
562 04:43:27.776900 INFO : End of initialization
563 04:43:27.777385 INFO : End of read dq deskew training
564 04:43:27.782391 INFO : End of MPR read delay center optimization
565 04:43:27.788120 INFO : End of write delay center optimization
566 04:43:27.793594 INFO : End of read delay center optimization
567 04:43:27.794058 INFO : End of max read latency training
568 04:43:27.799217 INFO : Training has run successfully!
569 04:43:27.799684 1D training succeed
570 04:43:27.807950 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 04:43:27.855319 Check phy result
572 04:43:27.855802 INFO : End of initialization
573 04:43:27.877771 INFO : End of 2D read delay Voltage center optimization
574 04:43:27.897869 INFO : End of 2D read delay Voltage center optimization
575 04:43:27.949995 INFO : End of 2D write delay Voltage center optimization
576 04:43:27.999847 INFO : End of 2D write delay Voltage center optimization
577 04:43:28.005355 INFO : Training has run successfully!
578 04:43:28.005828
579 04:43:28.006276 channel==0
580 04:43:28.010969 RxClkDly_Margin_A0==88 ps 9
581 04:43:28.011442 TxDqDly_Margin_A0==98 ps 10
582 04:43:28.016523 RxClkDly_Margin_A1==88 ps 9
583 04:43:28.016992 TxDqDly_Margin_A1==98 ps 10
584 04:43:28.017441 TrainedVREFDQ_A0==74
585 04:43:28.022098 TrainedVREFDQ_A1==74
586 04:43:28.022579 VrefDac_Margin_A0==24
587 04:43:28.023022 DeviceVref_Margin_A0==40
588 04:43:28.027776 VrefDac_Margin_A1==24
589 04:43:28.028292 DeviceVref_Margin_A1==40
590 04:43:28.028735
591 04:43:28.029181
592 04:43:28.033388 channel==1
593 04:43:28.033856 RxClkDly_Margin_A0==98 ps 10
594 04:43:28.034299 TxDqDly_Margin_A0==88 ps 9
595 04:43:28.038972 RxClkDly_Margin_A1==88 ps 9
596 04:43:28.039441 TxDqDly_Margin_A1==88 ps 9
597 04:43:28.044597 TrainedVREFDQ_A0==77
598 04:43:28.045070 TrainedVREFDQ_A1==77
599 04:43:28.045513 VrefDac_Margin_A0==22
600 04:43:28.050109 DeviceVref_Margin_A0==37
601 04:43:28.050567 VrefDac_Margin_A1==24
602 04:43:28.055785 DeviceVref_Margin_A1==37
603 04:43:28.056303
604 04:43:28.056748 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 04:43:28.057188
606 04:43:28.089318 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000017 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 04:43:28.089839 2D training succeed
608 04:43:28.094860 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 04:43:28.100491 auto size-- 65535DDR cs0 size: 2048MB
610 04:43:28.100964 DDR cs1 size: 2048MB
611 04:43:28.106088 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 04:43:28.106560 cs0 DataBus test pass
613 04:43:28.111695 cs1 DataBus test pass
614 04:43:28.112233 cs0 AddrBus test pass
615 04:43:28.112681 cs1 AddrBus test pass
616 04:43:28.113121
617 04:43:28.117287 100bdlr_step_size ps== 420
618 04:43:28.117772 result report
619 04:43:28.122878 boot times 0Enable ddr reg access
620 04:43:28.127416 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 04:43:28.140794 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 04:43:28.713561 0.0;M3 CHK:0;cm4_sp_mode 0
623 04:43:28.713993 MVN_1=0x00000000
624 04:43:28.719040 MVN_2=0x00000000
625 04:43:28.724850 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 04:43:28.725114 OPS=0x10
627 04:43:28.725328 ring efuse init
628 04:43:28.725534 chipver efuse init
629 04:43:28.730385 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 04:43:28.736156 [0.018961 Inits done]
631 04:43:28.736416 secure task start!
632 04:43:28.736626 high task start!
633 04:43:28.739577 low task start!
634 04:43:28.739821 run into bl31
635 04:43:28.747279 NOTICE: BL31: v1.3(release):4fc40b1
636 04:43:28.754455 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 04:43:28.754940 NOTICE: BL31: G12A normal boot!
638 04:43:28.780527 NOTICE: BL31: BL33 decompress pass
639 04:43:28.786231 ERROR: Error initializing runtime service opteed_fast
640 04:43:30.019125
641 04:43:30.019591
642 04:43:30.027091 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 04:43:30.027721
644 04:43:30.028241 Model: Libre Computer AML-A311D-CC Alta
645 04:43:30.235342 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 04:43:30.258536 DRAM: 2 GiB (effective 3.8 GiB)
647 04:43:30.403158 Core: 408 devices, 31 uclasses, devicetree: separate
648 04:43:30.407623 WDT: Not starting watchdog@f0d0
649 04:43:30.440479 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 04:43:30.453009 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 04:43:30.456820 ** Bad device specification mmc 0 **
652 04:43:30.468180 Card did not respond to voltage select! : -110
653 04:43:30.480894 ** Bad device specification mmc 0 **
654 04:43:30.481504 Couldn't find partition mmc 0
655 04:43:30.484236 Card did not respond to voltage select! : -110
656 04:43:30.489632 ** Bad device specification mmc 0 **
657 04:43:30.490174 Couldn't find partition mmc 0
658 04:43:30.494610 Error: could not access storage.
659 04:43:30.837209 Net: eth0: ethernet@ff3f0000
660 04:43:30.837844 starting USB...
661 04:43:31.088996 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 04:43:31.089616 Starting the controller
663 04:43:31.095862 USB XHCI 1.10
664 04:43:32.810125 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 04:43:32.810788 bl2_stage_init 0x01
666 04:43:32.811267 bl2_stage_init 0x81
667 04:43:32.815598 hw id: 0x0000 - pwm id 0x01
668 04:43:32.816121 bl2_stage_init 0xc1
669 04:43:32.816584 bl2_stage_init 0x02
670 04:43:32.817035
671 04:43:32.821161 L0:00000000
672 04:43:32.821652 L1:20000703
673 04:43:32.822106 L2:00008067
674 04:43:32.822548 L3:14000000
675 04:43:32.824089 B2:00402000
676 04:43:32.824572 B1:e0f83180
677 04:43:32.825050
678 04:43:32.825533 TE: 58159
679 04:43:32.826022
680 04:43:32.835165 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 04:43:32.835711
682 04:43:32.836218 Board ID = 1
683 04:43:32.836671 Set A53 clk to 24M
684 04:43:32.837115 Set A73 clk to 24M
685 04:43:32.840833 Set clk81 to 24M
686 04:43:32.841315 A53 clk: 1200 MHz
687 04:43:32.841765 A73 clk: 1200 MHz
688 04:43:32.846334 CLK81: 166.6M
689 04:43:32.846806 smccc: 00012ab5
690 04:43:32.852020 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 04:43:32.852499 board id: 1
692 04:43:32.857631 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 04:43:32.871377 fw parse done
694 04:43:32.876355 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 04:43:32.919032 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 04:43:32.930867 PIEI prepare done
697 04:43:32.931388 fastboot data load
698 04:43:32.931863 fastboot data verify
699 04:43:32.936488 verify result: 266
700 04:43:32.942058 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 04:43:32.942579 LPDDR4 probe
702 04:43:32.943043 ddr clk to 1584MHz
703 04:43:32.949077 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 04:43:32.986409
705 04:43:32.986957 dmc_version 0001
706 04:43:32.993071 Check phy result
707 04:43:32.999912 INFO : End of CA training
708 04:43:33.000426 INFO : End of initialization
709 04:43:33.005452 INFO : Training has run successfully!
710 04:43:33.005975 Check phy result
711 04:43:33.011010 INFO : End of initialization
712 04:43:33.011508 INFO : End of read enable training
713 04:43:33.014333 INFO : End of fine write leveling
714 04:43:33.019973 INFO : End of Write leveling coarse delay
715 04:43:33.025541 INFO : Training has run successfully!
716 04:43:33.026048 Check phy result
717 04:43:33.026511 INFO : End of initialization
718 04:43:33.031093 INFO : End of read dq deskew training
719 04:43:33.034463 INFO : End of MPR read delay center optimization
720 04:43:33.040047 INFO : End of write delay center optimization
721 04:43:33.045590 INFO : End of read delay center optimization
722 04:43:33.046082 INFO : End of max read latency training
723 04:43:33.051215 INFO : Training has run successfully!
724 04:43:33.051701 1D training succeed
725 04:43:33.058683 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 04:43:33.106488 Check phy result
727 04:43:33.107037 INFO : End of initialization
728 04:43:33.128757 INFO : End of 2D read delay Voltage center optimization
729 04:43:33.148909 INFO : End of 2D read delay Voltage center optimization
730 04:43:33.200500 INFO : End of 2D write delay Voltage center optimization
731 04:43:33.250797 INFO : End of 2D write delay Voltage center optimization
732 04:43:33.256355 INFO : Training has run successfully!
733 04:43:33.256876
734 04:43:33.257366 channel==0
735 04:43:33.262015 RxClkDly_Margin_A0==88 ps 9
736 04:43:33.262550 TxDqDly_Margin_A0==98 ps 10
737 04:43:33.265204 RxClkDly_Margin_A1==88 ps 9
738 04:43:33.265709 TxDqDly_Margin_A1==88 ps 9
739 04:43:33.270656 TrainedVREFDQ_A0==74
740 04:43:33.271162 TrainedVREFDQ_A1==74
741 04:43:33.276329 VrefDac_Margin_A0==24
742 04:43:33.276825 DeviceVref_Margin_A0==40
743 04:43:33.277278 VrefDac_Margin_A1==25
744 04:43:33.281820 DeviceVref_Margin_A1==40
745 04:43:33.282295
746 04:43:33.282747
747 04:43:33.283195 channel==1
748 04:43:33.283636 RxClkDly_Margin_A0==98 ps 10
749 04:43:33.285304 TxDqDly_Margin_A0==98 ps 10
750 04:43:33.290837 RxClkDly_Margin_A1==88 ps 9
751 04:43:33.291353 TxDqDly_Margin_A1==88 ps 9
752 04:43:33.291841 TrainedVREFDQ_A0==77
753 04:43:33.296416 TrainedVREFDQ_A1==77
754 04:43:33.296941 VrefDac_Margin_A0==22
755 04:43:33.302064 DeviceVref_Margin_A0==37
756 04:43:33.302557 VrefDac_Margin_A1==24
757 04:43:33.303016 DeviceVref_Margin_A1==37
758 04:43:33.303463
759 04:43:33.310968 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 04:43:33.311501
761 04:43:33.336735 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000018 00000018 00000017 00000018 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 04:43:33.342328 2D training succeed
763 04:43:33.345681 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 04:43:33.351250 auto size-- 65535DDR cs0 size: 2048MB
765 04:43:33.351736 DDR cs1 size: 2048MB
766 04:43:33.357026 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 04:43:33.357509 cs0 DataBus test pass
768 04:43:33.362467 cs1 DataBus test pass
769 04:43:33.362979 cs0 AddrBus test pass
770 04:43:33.363454 cs1 AddrBus test pass
771 04:43:33.363931
772 04:43:33.368092 100bdlr_step_size ps== 420
773 04:43:33.368629 result report
774 04:43:33.373714 boot times 0Enable ddr reg access
775 04:43:33.378226 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 04:43:33.391764 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 04:43:33.964736 0.0;M3 CHK:0;cm4_sp_mode 0
778 04:43:33.965398 MVN_1=0x00000000
779 04:43:33.970234 MVN_2=0x00000000
780 04:43:33.976060 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 04:43:33.976608 OPS=0x10
782 04:43:33.977068 ring efuse init
783 04:43:33.977515 chipver efuse init
784 04:43:33.981600 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 04:43:33.987272 [0.018960 Inits done]
786 04:43:33.987817 secure task start!
787 04:43:33.988333 high task start!
788 04:43:33.990852 low task start!
789 04:43:33.991391 run into bl31
790 04:43:33.998555 NOTICE: BL31: v1.3(release):4fc40b1
791 04:43:34.005369 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 04:43:34.005920 NOTICE: BL31: G12A normal boot!
793 04:43:34.031650 NOTICE: BL31: BL33 decompress pass
794 04:43:34.036433 ERROR: Error initializing runtime service opteed_fast
795 04:43:35.270197
796 04:43:35.270840
797 04:43:35.277638 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 04:43:35.278189
799 04:43:35.278664 Model: Libre Computer AML-A311D-CC Alta
800 04:43:35.486968 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 04:43:35.510504 DRAM: 2 GiB (effective 3.8 GiB)
802 04:43:35.653496 Core: 408 devices, 31 uclasses, devicetree: separate
803 04:43:35.658344 WDT: Not starting watchdog@f0d0
804 04:43:35.691521 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 04:43:35.703924 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 04:43:35.708956 ** Bad device specification mmc 0 **
807 04:43:35.719409 Card did not respond to voltage select! : -110
808 04:43:35.726920 ** Bad device specification mmc 0 **
809 04:43:35.727451 Couldn't find partition mmc 0
810 04:43:35.735425 Card did not respond to voltage select! : -110
811 04:43:35.740777 ** Bad device specification mmc 0 **
812 04:43:35.741312 Couldn't find partition mmc 0
813 04:43:35.745867 Error: could not access storage.
814 04:43:36.088292 Net: eth0: ethernet@ff3f0000
815 04:43:36.088913 starting USB...
816 04:43:36.340072 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 04:43:36.340663 Starting the controller
818 04:43:36.347089 USB XHCI 1.10
819 04:43:38.508712 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 04:43:38.509379 bl2_stage_init 0x01
821 04:43:38.509862 bl2_stage_init 0x81
822 04:43:38.514292 hw id: 0x0000 - pwm id 0x01
823 04:43:38.514842 bl2_stage_init 0xc1
824 04:43:38.515312 bl2_stage_init 0x02
825 04:43:38.515770
826 04:43:38.519957 L0:00000000
827 04:43:38.520534 L1:20000703
828 04:43:38.521000 L2:00008067
829 04:43:38.521459 L3:14000000
830 04:43:38.522937 B2:00402000
831 04:43:38.523464 B1:e0f83180
832 04:43:38.523930
833 04:43:38.524435 TE: 58124
834 04:43:38.524898
835 04:43:38.533966 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 04:43:38.534538
837 04:43:38.535004 Board ID = 1
838 04:43:38.535471 Set A53 clk to 24M
839 04:43:38.535922 Set A73 clk to 24M
840 04:43:38.539688 Set clk81 to 24M
841 04:43:38.540302 A53 clk: 1200 MHz
842 04:43:38.540787 A73 clk: 1200 MHz
843 04:43:38.543184 CLK81: 166.6M
844 04:43:38.543727 smccc: 00012a92
845 04:43:38.548680 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 04:43:38.554236 board id: 1
847 04:43:38.559505 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 04:43:38.569978 fw parse done
849 04:43:38.575939 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 04:43:38.617524 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 04:43:38.629506 PIEI prepare done
852 04:43:38.630076 fastboot data load
853 04:43:38.630547 fastboot data verify
854 04:43:38.635084 verify result: 266
855 04:43:38.640701 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 04:43:38.641270 LPDDR4 probe
857 04:43:38.641740 ddr clk to 1584MHz
858 04:43:38.648700 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 04:43:38.685985
860 04:43:38.686580 dmc_version 0001
861 04:43:38.692571 Check phy result
862 04:43:38.698436 INFO : End of CA training
863 04:43:38.698977 INFO : End of initialization
864 04:43:38.704075 INFO : Training has run successfully!
865 04:43:38.704630 Check phy result
866 04:43:38.709671 INFO : End of initialization
867 04:43:38.710231 INFO : End of read enable training
868 04:43:38.715274 INFO : End of fine write leveling
869 04:43:38.720874 INFO : End of Write leveling coarse delay
870 04:43:38.721432 INFO : Training has run successfully!
871 04:43:38.721902 Check phy result
872 04:43:38.726477 INFO : End of initialization
873 04:43:38.727031 INFO : End of read dq deskew training
874 04:43:38.732097 INFO : End of MPR read delay center optimization
875 04:43:38.737657 INFO : End of write delay center optimization
876 04:43:38.743234 INFO : End of read delay center optimization
877 04:43:38.743789 INFO : End of max read latency training
878 04:43:38.748853 INFO : Training has run successfully!
879 04:43:38.749405 1D training succeed
880 04:43:38.756999 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 04:43:38.805615 Check phy result
882 04:43:38.806205 INFO : End of initialization
883 04:43:38.828305 INFO : End of 2D read delay Voltage center optimization
884 04:43:38.848513 INFO : End of 2D read delay Voltage center optimization
885 04:43:38.899595 INFO : End of 2D write delay Voltage center optimization
886 04:43:38.949944 INFO : End of 2D write delay Voltage center optimization
887 04:43:38.955436 INFO : Training has run successfully!
888 04:43:38.956015
889 04:43:38.956496 channel==0
890 04:43:38.961026 RxClkDly_Margin_A0==88 ps 9
891 04:43:38.961588 TxDqDly_Margin_A0==98 ps 10
892 04:43:38.966656 RxClkDly_Margin_A1==88 ps 9
893 04:43:38.967209 TxDqDly_Margin_A1==98 ps 10
894 04:43:38.967702 TrainedVREFDQ_A0==74
895 04:43:38.972336 TrainedVREFDQ_A1==75
896 04:43:38.972914 VrefDac_Margin_A0==24
897 04:43:38.973356 DeviceVref_Margin_A0==40
898 04:43:38.977944 VrefDac_Margin_A1==25
899 04:43:38.978507 DeviceVref_Margin_A1==39
900 04:43:38.978974
901 04:43:38.979447
902 04:43:38.983421 channel==1
903 04:43:38.983955 RxClkDly_Margin_A0==98 ps 10
904 04:43:38.984437 TxDqDly_Margin_A0==88 ps 9
905 04:43:38.989076 RxClkDly_Margin_A1==88 ps 9
906 04:43:38.989601 TxDqDly_Margin_A1==88 ps 9
907 04:43:38.994620 TrainedVREFDQ_A0==77
908 04:43:38.995156 TrainedVREFDQ_A1==77
909 04:43:38.995594 VrefDac_Margin_A0==22
910 04:43:39.000257 DeviceVref_Margin_A0==37
911 04:43:39.000786 VrefDac_Margin_A1==24
912 04:43:39.005892 DeviceVref_Margin_A1==37
913 04:43:39.006424
914 04:43:39.006865 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 04:43:39.007300
916 04:43:39.039396 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000017 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 04:43:39.040075 2D training succeed
918 04:43:39.045029 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 04:43:39.050625 auto size-- 65535DDR cs0 size: 2048MB
920 04:43:39.051165 DDR cs1 size: 2048MB
921 04:43:39.056259 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 04:43:39.056821 cs0 DataBus test pass
923 04:43:39.061864 cs1 DataBus test pass
924 04:43:39.062400 cs0 AddrBus test pass
925 04:43:39.062840 cs1 AddrBus test pass
926 04:43:39.063272
927 04:43:39.067430 100bdlr_step_size ps== 420
928 04:43:39.068025 result report
929 04:43:39.073056 boot times 0Enable ddr reg access
930 04:43:39.078296 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 04:43:39.091743 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 04:43:39.665401 0.0;M3 CHK:0;cm4_sp_mode 0
933 04:43:39.666072 MVN_1=0x00000000
934 04:43:39.670964 MVN_2=0x00000000
935 04:43:39.676708 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 04:43:39.677244 OPS=0x10
937 04:43:39.677714 ring efuse init
938 04:43:39.678166 chipver efuse init
939 04:43:39.682293 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 04:43:39.687916 [0.018961 Inits done]
941 04:43:39.688485 secure task start!
942 04:43:39.688952 high task start!
943 04:43:39.692466 low task start!
944 04:43:39.692997 run into bl31
945 04:43:39.699124 NOTICE: BL31: v1.3(release):4fc40b1
946 04:43:39.706989 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 04:43:39.707523 NOTICE: BL31: G12A normal boot!
948 04:43:39.732945 NOTICE: BL31: BL33 decompress pass
949 04:43:39.738542 ERROR: Error initializing runtime service opteed_fast
950 04:43:40.971171
951 04:43:40.971724
952 04:43:40.979625 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 04:43:40.979969
954 04:43:40.980251 Model: Libre Computer AML-A311D-CC Alta
955 04:43:41.188065 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 04:43:41.211444 DRAM: 2 GiB (effective 3.8 GiB)
957 04:43:41.354434 Core: 408 devices, 31 uclasses, devicetree: separate
958 04:43:41.360340 WDT: Not starting watchdog@f0d0
959 04:43:41.392638 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 04:43:41.405109 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 04:43:41.410165 ** Bad device specification mmc 0 **
962 04:43:41.420377 Card did not respond to voltage select! : -110
963 04:43:41.428013 ** Bad device specification mmc 0 **
964 04:43:41.428341 Couldn't find partition mmc 0
965 04:43:41.436351 Card did not respond to voltage select! : -110
966 04:43:41.441931 ** Bad device specification mmc 0 **
967 04:43:41.442477 Couldn't find partition mmc 0
968 04:43:41.447007 Error: could not access storage.
969 04:43:41.790484 Net: eth0: ethernet@ff3f0000
970 04:43:41.790926 starting USB...
971 04:43:42.042256 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 04:43:42.042853 Starting the controller
973 04:43:42.049248 USB XHCI 1.10
974 04:43:43.908404 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 04:43:43.908826 bl2_stage_init 0x01
976 04:43:43.909075 bl2_stage_init 0x81
977 04:43:43.913975 hw id: 0x0000 - pwm id 0x01
978 04:43:43.914290 bl2_stage_init 0xc1
979 04:43:43.914532 bl2_stage_init 0x02
980 04:43:43.914766
981 04:43:43.919557 L0:00000000
982 04:43:43.919975 L1:20000703
983 04:43:43.920288 L2:00008067
984 04:43:43.920525 L3:14000000
985 04:43:43.925115 B2:00402000
986 04:43:43.925411 B1:e0f83180
987 04:43:43.925655
988 04:43:43.925890 TE: 58167
989 04:43:43.926122
990 04:43:43.930743 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 04:43:43.931055
992 04:43:43.931296 Board ID = 1
993 04:43:43.936366 Set A53 clk to 24M
994 04:43:43.936828 Set A73 clk to 24M
995 04:43:43.937223 Set clk81 to 24M
996 04:43:43.941963 A53 clk: 1200 MHz
997 04:43:43.942409 A73 clk: 1200 MHz
998 04:43:43.942682 CLK81: 166.6M
999 04:43:43.942920 smccc: 00012abd
1000 04:43:43.947476 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 04:43:43.953168 board id: 1
1002 04:43:43.959005 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 04:43:43.969697 fw parse done
1004 04:43:43.975744 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 04:43:44.018326 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 04:43:44.029111 PIEI prepare done
1007 04:43:44.029627 fastboot data load
1008 04:43:44.030100 fastboot data verify
1009 04:43:44.034727 verify result: 266
1010 04:43:44.040328 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 04:43:44.040879 LPDDR4 probe
1012 04:43:44.041359 ddr clk to 1584MHz
1013 04:43:44.047941 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 04:43:44.085654
1015 04:43:44.086266 dmc_version 0001
1016 04:43:44.092359 Check phy result
1017 04:43:44.098111 INFO : End of CA training
1018 04:43:44.098610 INFO : End of initialization
1019 04:43:44.103791 INFO : Training has run successfully!
1020 04:43:44.104373 Check phy result
1021 04:43:44.109381 INFO : End of initialization
1022 04:43:44.110000 INFO : End of read enable training
1023 04:43:44.114984 INFO : End of fine write leveling
1024 04:43:44.120601 INFO : End of Write leveling coarse delay
1025 04:43:44.121152 INFO : Training has run successfully!
1026 04:43:44.121620 Check phy result
1027 04:43:44.126159 INFO : End of initialization
1028 04:43:44.126693 INFO : End of read dq deskew training
1029 04:43:44.131790 INFO : End of MPR read delay center optimization
1030 04:43:44.137425 INFO : End of write delay center optimization
1031 04:43:44.143004 INFO : End of read delay center optimization
1032 04:43:44.143600 INFO : End of max read latency training
1033 04:43:44.148551 INFO : Training has run successfully!
1034 04:43:44.149151 1D training succeed
1035 04:43:44.157731 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 04:43:44.205451 Check phy result
1037 04:43:44.206101 INFO : End of initialization
1038 04:43:44.227158 INFO : End of 2D read delay Voltage center optimization
1039 04:43:44.247458 INFO : End of 2D read delay Voltage center optimization
1040 04:43:44.299527 INFO : End of 2D write delay Voltage center optimization
1041 04:43:44.348801 INFO : End of 2D write delay Voltage center optimization
1042 04:43:44.354325 INFO : Training has run successfully!
1043 04:43:44.354859
1044 04:43:44.355339 channel==0
1045 04:43:44.359889 RxClkDly_Margin_A0==88 ps 9
1046 04:43:44.360423 TxDqDly_Margin_A0==98 ps 10
1047 04:43:44.365705 RxClkDly_Margin_A1==88 ps 9
1048 04:43:44.366205 TxDqDly_Margin_A1==98 ps 10
1049 04:43:44.366668 TrainedVREFDQ_A0==74
1050 04:43:44.371087 TrainedVREFDQ_A1==74
1051 04:43:44.371681 VrefDac_Margin_A0==25
1052 04:43:44.372234 DeviceVref_Margin_A0==40
1053 04:43:44.376667 VrefDac_Margin_A1==25
1054 04:43:44.377209 DeviceVref_Margin_A1==40
1055 04:43:44.377675
1056 04:43:44.378133
1057 04:43:44.382322 channel==1
1058 04:43:44.382887 RxClkDly_Margin_A0==98 ps 10
1059 04:43:44.383403 TxDqDly_Margin_A0==88 ps 9
1060 04:43:44.387920 RxClkDly_Margin_A1==88 ps 9
1061 04:43:44.388527 TxDqDly_Margin_A1==88 ps 9
1062 04:43:44.393604 TrainedVREFDQ_A0==77
1063 04:43:44.394161 TrainedVREFDQ_A1==77
1064 04:43:44.394630 VrefDac_Margin_A0==23
1065 04:43:44.399115 DeviceVref_Margin_A0==37
1066 04:43:44.399663 VrefDac_Margin_A1==24
1067 04:43:44.404678 DeviceVref_Margin_A1==37
1068 04:43:44.405217
1069 04:43:44.405691 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 04:43:44.406142
1071 04:43:44.438379 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 04:43:44.438999 2D training succeed
1073 04:43:44.443950 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 04:43:44.449500 auto size-- 65535DDR cs0 size: 2048MB
1075 04:43:44.450021 DDR cs1 size: 2048MB
1076 04:43:44.455017 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 04:43:44.455572 cs0 DataBus test pass
1078 04:43:44.460649 cs1 DataBus test pass
1079 04:43:44.461240 cs0 AddrBus test pass
1080 04:43:44.461704 cs1 AddrBus test pass
1081 04:43:44.462160
1082 04:43:44.466218 100bdlr_step_size ps== 420
1083 04:43:44.466748 result report
1084 04:43:44.471764 boot times 0Enable ddr reg access
1085 04:43:44.477033 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 04:43:44.490619 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 04:43:45.064389 0.0;M3 CHK:0;cm4_sp_mode 0
1088 04:43:45.065068 MVN_1=0x00000000
1089 04:43:45.069843 MVN_2=0x00000000
1090 04:43:45.075661 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 04:43:45.076258 OPS=0x10
1092 04:43:45.076766 ring efuse init
1093 04:43:45.077262 chipver efuse init
1094 04:43:45.081137 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 04:43:45.086734 [0.018960 Inits done]
1096 04:43:45.087311 secure task start!
1097 04:43:45.087816 high task start!
1098 04:43:45.091253 low task start!
1099 04:43:45.091792 run into bl31
1100 04:43:45.097963 NOTICE: BL31: v1.3(release):4fc40b1
1101 04:43:45.105768 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 04:43:45.106321 NOTICE: BL31: G12A normal boot!
1103 04:43:45.131130 NOTICE: BL31: BL33 decompress pass
1104 04:43:45.136859 ERROR: Error initializing runtime service opteed_fast
1105 04:43:46.369835
1106 04:43:46.370501
1107 04:43:46.377265 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 04:43:46.377844
1109 04:43:46.378326 Model: Libre Computer AML-A311D-CC Alta
1110 04:43:46.585649 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 04:43:46.609799 DRAM: 2 GiB (effective 3.8 GiB)
1112 04:43:46.752910 Core: 408 devices, 31 uclasses, devicetree: separate
1113 04:43:46.758798 WDT: Not starting watchdog@f0d0
1114 04:43:46.791035 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 04:43:46.803351 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 04:43:46.808367 ** Bad device specification mmc 0 **
1117 04:43:46.818911 Card did not respond to voltage select! : -110
1118 04:43:46.826530 ** Bad device specification mmc 0 **
1119 04:43:46.827111 Couldn't find partition mmc 0
1120 04:43:46.834906 Card did not respond to voltage select! : -110
1121 04:43:46.840384 ** Bad device specification mmc 0 **
1122 04:43:46.840949 Couldn't find partition mmc 0
1123 04:43:46.845339 Error: could not access storage.
1124 04:43:47.187892 Net: eth0: ethernet@ff3f0000
1125 04:43:47.188609 starting USB...
1126 04:43:47.439580 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 04:43:47.440035 Starting the controller
1128 04:43:47.446501 USB XHCI 1.10
1129 04:43:49.000652 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 04:43:49.008136 scanning usb for storage devices... 0 Storage Device(s) found
1132 04:43:49.059898 Hit any key to stop autoboot: 1
1133 04:43:49.060935 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1134 04:43:49.061628 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1135 04:43:49.062154 Setting prompt string to ['=>']
1136 04:43:49.062683 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1137 04:43:49.065564 0
1138 04:43:49.066515 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 04:43:49.067057 Sending with 10 millisecond of delay
1141 04:43:50.202207 => setenv autoload no
1142 04:43:50.213053 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1143 04:43:50.218429 setenv autoload no
1144 04:43:50.219226 Sending with 10 millisecond of delay
1146 04:43:52.017343 => setenv initrd_high 0xffffffff
1147 04:43:52.028171 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1148 04:43:52.029113 setenv initrd_high 0xffffffff
1149 04:43:52.029892 Sending with 10 millisecond of delay
1151 04:43:53.646660 => setenv fdt_high 0xffffffff
1152 04:43:53.657222 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1153 04:43:53.657763 setenv fdt_high 0xffffffff
1154 04:43:53.658272 Sending with 10 millisecond of delay
1156 04:43:53.949723 => dhcp
1157 04:43:53.960271 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1158 04:43:53.960815 dhcp
1159 04:43:53.961074 Speed: 1000, full duplex
1160 04:43:53.961307 BOOTP broadcast 1
1161 04:43:53.967265 DHCP client bound to address 192.168.6.27 (8 ms)
1162 04:43:53.968116 Sending with 10 millisecond of delay
1164 04:43:55.645550 => setenv serverip 192.168.6.2
1165 04:43:55.656398 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1166 04:43:55.657404 setenv serverip 192.168.6.2
1167 04:43:55.658159 Sending with 10 millisecond of delay
1169 04:43:59.383294 => tftpboot 0x01080000 950936/tftp-deploy-bdspo4ot/kernel/uImage
1170 04:43:59.394183 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 04:43:59.395154 tftpboot 0x01080000 950936/tftp-deploy-bdspo4ot/kernel/uImage
1172 04:43:59.395663 Speed: 1000, full duplex
1173 04:43:59.396164 Using ethernet@ff3f0000 device
1174 04:43:59.396903 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 04:43:59.402367 Filename '950936/tftp-deploy-bdspo4ot/kernel/uImage'.
1176 04:43:59.405505 Load address: 0x1080000
1177 04:44:02.416628 Loading: *################################################## 43.6 MiB
1178 04:44:02.417327 14.5 MiB/s
1179 04:44:02.417812 done
1180 04:44:02.420220 Bytes transferred = 45713984 (2b98a40 hex)
1181 04:44:02.421098 Sending with 10 millisecond of delay
1183 04:44:07.109348 => tftpboot 0x08000000 950936/tftp-deploy-bdspo4ot/ramdisk/ramdisk.cpio.gz.uboot
1184 04:44:07.120204 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1185 04:44:07.121205 tftpboot 0x08000000 950936/tftp-deploy-bdspo4ot/ramdisk/ramdisk.cpio.gz.uboot
1186 04:44:07.121717 Speed: 1000, full duplex
1187 04:44:07.122187 Using ethernet@ff3f0000 device
1188 04:44:07.122957 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 04:44:07.131424 Filename '950936/tftp-deploy-bdspo4ot/ramdisk/ramdisk.cpio.gz.uboot'.
1190 04:44:07.132088 Load address: 0x8000000
1191 04:44:09.388720 Loading: *############ UDP wrong checksum 000000ff 00001afd
1192 04:44:09.425425 UDP wrong checksum 000000ff 0000b6ef
1193 04:44:13.646631 T ##################################### UDP wrong checksum 00000005 00002ea7
1194 04:44:18.648793 T UDP wrong checksum 00000005 00002ea7
1195 04:44:28.650906 T T UDP wrong checksum 00000005 00002ea7
1196 04:44:48.654828 T T T T UDP wrong checksum 00000005 00002ea7
1197 04:45:03.658933 T T
1198 04:45:03.659377 Retry count exceeded; starting again
1200 04:45:03.660957 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1203 04:45:03.662717 end: 2.4 uboot-commands (duration 00:01:53) [common]
1205 04:45:03.664237 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1207 04:45:03.665290 end: 2 uboot-action (duration 00:01:53) [common]
1209 04:45:03.666795 Cleaning after the job
1210 04:45:03.667349 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/ramdisk
1211 04:45:03.668798 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/kernel
1212 04:45:03.694167 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/dtb
1213 04:45:03.695473 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/nfsrootfs
1214 04:45:03.875067 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950936/tftp-deploy-bdspo4ot/modules
1215 04:45:03.898405 start: 4.1 power-off (timeout 00:00:30) [common]
1216 04:45:03.899074 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1217 04:45:03.933451 >> OK - accepted request
1218 04:45:03.935550 Returned 0 in 0 seconds
1219 04:45:04.036422 end: 4.1 power-off (duration 00:00:00) [common]
1221 04:45:04.037532 start: 4.2 read-feedback (timeout 00:10:00) [common]
1222 04:45:04.038204 Listened to connection for namespace 'common' for up to 1s
1223 04:45:05.038629 Finalising connection for namespace 'common'
1224 04:45:05.039131 Disconnecting from shell: Finalise
1225 04:45:05.039419 =>
1226 04:45:05.140349 end: 4.2 read-feedback (duration 00:00:01) [common]
1227 04:45:05.141096 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950936
1228 04:45:08.191137 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950936
1229 04:45:08.191741 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.