Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:59:27.233594 lava-dispatcher, installed at version: 2024.01
2 02:59:27.234427 start: 0 validate
3 02:59:27.234945 Start time: 2024-11-07 02:59:27.234913+00:00 (UTC)
4 02:59:27.235486 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:59:27.236065 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:59:27.276041 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:59:27.276574 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:59:27.309710 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:59:27.310380 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:59:27.341301 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:59:27.341826 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:59:27.375757 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:59:27.376370 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 02:59:27.411665 validate duration: 0.18
16 02:59:27.412691 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:59:27.413070 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:59:27.413483 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:59:27.414131 Not decompressing ramdisk as can be used compressed.
20 02:59:27.414660 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 02:59:27.415011 saving as /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/ramdisk/initrd.cpio.gz
22 02:59:27.415369 total size: 5628182 (5 MB)
23 02:59:27.452325 progress 0 % (0 MB)
24 02:59:27.456703 progress 5 % (0 MB)
25 02:59:27.461306 progress 10 % (0 MB)
26 02:59:27.465357 progress 15 % (0 MB)
27 02:59:27.469943 progress 20 % (1 MB)
28 02:59:27.474239 progress 25 % (1 MB)
29 02:59:27.478829 progress 30 % (1 MB)
30 02:59:27.483192 progress 35 % (1 MB)
31 02:59:27.487287 progress 40 % (2 MB)
32 02:59:27.491653 progress 45 % (2 MB)
33 02:59:27.495833 progress 50 % (2 MB)
34 02:59:27.500433 progress 55 % (2 MB)
35 02:59:27.505093 progress 60 % (3 MB)
36 02:59:27.509322 progress 65 % (3 MB)
37 02:59:27.513696 progress 70 % (3 MB)
38 02:59:27.517620 progress 75 % (4 MB)
39 02:59:27.522085 progress 80 % (4 MB)
40 02:59:27.525817 progress 85 % (4 MB)
41 02:59:27.529839 progress 90 % (4 MB)
42 02:59:27.533703 progress 95 % (5 MB)
43 02:59:27.537128 progress 100 % (5 MB)
44 02:59:27.537852 5 MB downloaded in 0.12 s (43.83 MB/s)
45 02:59:27.538433 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:59:27.539350 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:59:27.539650 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:59:27.539928 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:59:27.540444 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/kernel/Image
51 02:59:27.540738 saving as /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/kernel/Image
52 02:59:27.540954 total size: 45713920 (43 MB)
53 02:59:27.541169 No compression specified
54 02:59:27.576346 progress 0 % (0 MB)
55 02:59:27.605449 progress 5 % (2 MB)
56 02:59:27.634373 progress 10 % (4 MB)
57 02:59:27.662812 progress 15 % (6 MB)
58 02:59:27.691468 progress 20 % (8 MB)
59 02:59:27.719845 progress 25 % (10 MB)
60 02:59:27.748361 progress 30 % (13 MB)
61 02:59:27.777415 progress 35 % (15 MB)
62 02:59:27.806910 progress 40 % (17 MB)
63 02:59:27.837648 progress 45 % (19 MB)
64 02:59:27.867016 progress 50 % (21 MB)
65 02:59:27.895905 progress 55 % (24 MB)
66 02:59:27.925011 progress 60 % (26 MB)
67 02:59:27.953619 progress 65 % (28 MB)
68 02:59:27.982690 progress 70 % (30 MB)
69 02:59:28.011145 progress 75 % (32 MB)
70 02:59:28.040008 progress 80 % (34 MB)
71 02:59:28.068121 progress 85 % (37 MB)
72 02:59:28.096543 progress 90 % (39 MB)
73 02:59:28.124848 progress 95 % (41 MB)
74 02:59:28.152901 progress 100 % (43 MB)
75 02:59:28.153449 43 MB downloaded in 0.61 s (71.18 MB/s)
76 02:59:28.153957 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:59:28.154807 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:59:28.155105 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:59:28.155386 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:59:28.155871 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 02:59:28.156186 saving as /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/dtb/meson-g12b-a311d-libretech-cc.dtb
83 02:59:28.156438 total size: 54703 (0 MB)
84 02:59:28.156679 No compression specified
85 02:59:28.190443 progress 59 % (0 MB)
86 02:59:28.191305 progress 100 % (0 MB)
87 02:59:28.191867 0 MB downloaded in 0.04 s (1.47 MB/s)
88 02:59:28.192393 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:59:28.193226 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:59:28.193496 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:59:28.193762 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:59:28.194231 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 02:59:28.194478 saving as /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/nfsrootfs/full.rootfs.tar
95 02:59:28.194683 total size: 107552908 (102 MB)
96 02:59:28.194894 Using unxz to decompress xz
97 02:59:28.229235 progress 0 % (0 MB)
98 02:59:28.882800 progress 5 % (5 MB)
99 02:59:29.611739 progress 10 % (10 MB)
100 02:59:30.340100 progress 15 % (15 MB)
101 02:59:31.114224 progress 20 % (20 MB)
102 02:59:31.691581 progress 25 % (25 MB)
103 02:59:32.319905 progress 30 % (30 MB)
104 02:59:33.093215 progress 35 % (35 MB)
105 02:59:33.449412 progress 40 % (41 MB)
106 02:59:33.919034 progress 45 % (46 MB)
107 02:59:34.626996 progress 50 % (51 MB)
108 02:59:35.316158 progress 55 % (56 MB)
109 02:59:36.074734 progress 60 % (61 MB)
110 02:59:36.837325 progress 65 % (66 MB)
111 02:59:37.579002 progress 70 % (71 MB)
112 02:59:38.352517 progress 75 % (76 MB)
113 02:59:39.029684 progress 80 % (82 MB)
114 02:59:39.737995 progress 85 % (87 MB)
115 02:59:40.477613 progress 90 % (92 MB)
116 02:59:41.196803 progress 95 % (97 MB)
117 02:59:41.943726 progress 100 % (102 MB)
118 02:59:41.955660 102 MB downloaded in 13.76 s (7.45 MB/s)
119 02:59:41.956418 end: 1.4.1 http-download (duration 00:00:14) [common]
121 02:59:41.958037 end: 1.4 download-retry (duration 00:00:14) [common]
122 02:59:41.958553 start: 1.5 download-retry (timeout 00:09:45) [common]
123 02:59:41.959062 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 02:59:41.959872 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/modules.tar.xz
125 02:59:41.960369 saving as /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/modules/modules.tar
126 02:59:41.960777 total size: 11607084 (11 MB)
127 02:59:41.961195 Using unxz to decompress xz
128 02:59:42.005598 progress 0 % (0 MB)
129 02:59:42.072845 progress 5 % (0 MB)
130 02:59:42.151415 progress 10 % (1 MB)
131 02:59:42.268559 progress 15 % (1 MB)
132 02:59:42.379105 progress 20 % (2 MB)
133 02:59:42.475720 progress 25 % (2 MB)
134 02:59:42.555663 progress 30 % (3 MB)
135 02:59:42.630464 progress 35 % (3 MB)
136 02:59:42.709590 progress 40 % (4 MB)
137 02:59:42.790185 progress 45 % (5 MB)
138 02:59:42.876470 progress 50 % (5 MB)
139 02:59:42.954233 progress 55 % (6 MB)
140 02:59:43.042386 progress 60 % (6 MB)
141 02:59:43.124664 progress 65 % (7 MB)
142 02:59:43.201666 progress 70 % (7 MB)
143 02:59:43.283737 progress 75 % (8 MB)
144 02:59:43.370345 progress 80 % (8 MB)
145 02:59:43.452653 progress 85 % (9 MB)
146 02:59:43.533375 progress 90 % (9 MB)
147 02:59:43.613071 progress 95 % (10 MB)
148 02:59:43.690531 progress 100 % (11 MB)
149 02:59:43.702007 11 MB downloaded in 1.74 s (6.36 MB/s)
150 02:59:43.702593 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:59:43.703429 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:59:43.703700 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 02:59:43.703973 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 02:59:53.510515 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/951292/extract-nfsrootfs-889wda7d
156 02:59:53.511131 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 02:59:53.511425 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 02:59:53.512127 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8
159 02:59:53.512622 makedir: /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin
160 02:59:53.512971 makedir: /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/tests
161 02:59:53.513300 makedir: /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/results
162 02:59:53.513639 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-add-keys
163 02:59:53.514178 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-add-sources
164 02:59:53.514695 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-background-process-start
165 02:59:53.515216 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-background-process-stop
166 02:59:53.515753 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-common-functions
167 02:59:53.516287 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-echo-ipv4
168 02:59:53.516781 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-install-packages
169 02:59:53.517283 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-installed-packages
170 02:59:53.517773 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-os-build
171 02:59:53.518276 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-probe-channel
172 02:59:53.518786 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-probe-ip
173 02:59:53.519272 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-target-ip
174 02:59:53.519760 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-target-mac
175 02:59:53.520278 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-target-storage
176 02:59:53.520782 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-test-case
177 02:59:53.521282 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-test-event
178 02:59:53.521763 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-test-feedback
179 02:59:53.522256 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-test-raise
180 02:59:53.522763 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-test-reference
181 02:59:53.523253 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-test-runner
182 02:59:53.523748 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-test-set
183 02:59:53.524269 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-test-shell
184 02:59:53.524868 Updating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-install-packages (oe)
185 02:59:53.525428 Updating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/bin/lava-installed-packages (oe)
186 02:59:53.525892 Creating /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/environment
187 02:59:53.526276 LAVA metadata
188 02:59:53.526543 - LAVA_JOB_ID=951292
189 02:59:53.526766 - LAVA_DISPATCHER_IP=192.168.6.2
190 02:59:53.527145 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 02:59:53.528187 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 02:59:53.528527 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 02:59:53.528743 skipped lava-vland-overlay
194 02:59:53.528992 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 02:59:53.529253 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 02:59:53.529477 skipped lava-multinode-overlay
197 02:59:53.529724 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 02:59:53.529981 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 02:59:53.530238 Loading test definitions
200 02:59:53.530521 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 02:59:53.530743 Using /lava-951292 at stage 0
202 02:59:53.531968 uuid=951292_1.6.2.4.1 testdef=None
203 02:59:53.532319 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 02:59:53.532592 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 02:59:53.534465 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 02:59:53.535276 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 02:59:53.537679 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 02:59:53.538537 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 02:59:53.540805 runner path: /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/0/tests/0_dmesg test_uuid 951292_1.6.2.4.1
212 02:59:53.541394 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 02:59:53.542169 Creating lava-test-runner.conf files
215 02:59:53.542376 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/951292/lava-overlay-i_3bj3r8/lava-951292/0 for stage 0
216 02:59:53.542725 - 0_dmesg
217 02:59:53.543081 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 02:59:53.543364 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 02:59:53.565222 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 02:59:53.565659 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 02:59:53.565928 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 02:59:53.566202 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 02:59:53.566471 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 02:59:54.213849 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 02:59:54.214325 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 02:59:54.214578 extracting modules file /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/951292/extract-nfsrootfs-889wda7d
227 02:59:55.734591 extracting modules file /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/951292/extract-overlay-ramdisk-chu1k2mt/ramdisk
228 02:59:57.325146 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 02:59:57.325714 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
230 02:59:57.326058 [common] Applying overlay to NFS
231 02:59:57.326317 [common] Applying overlay /var/lib/lava/dispatcher/tmp/951292/compress-overlay-8mut0tco/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/951292/extract-nfsrootfs-889wda7d
232 02:59:57.362618 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 02:59:57.363099 start: 1.6.6 prepare-kernel (timeout 00:09:30) [common]
234 02:59:57.363436 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:30) [common]
235 02:59:57.363722 Converting downloaded kernel to a uImage
236 02:59:57.364140 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/kernel/Image /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/kernel/uImage
237 02:59:57.830762 output: Image Name:
238 02:59:57.831193 output: Created: Thu Nov 7 02:59:57 2024
239 02:59:57.831404 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 02:59:57.831610 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 02:59:57.831812 output: Load Address: 01080000
242 02:59:57.832049 output: Entry Point: 01080000
243 02:59:57.832256 output:
244 02:59:57.832596 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 02:59:57.832864 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 02:59:57.833135 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 02:59:57.833390 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 02:59:57.833651 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 02:59:57.833921 Building ramdisk /var/lib/lava/dispatcher/tmp/951292/extract-overlay-ramdisk-chu1k2mt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/951292/extract-overlay-ramdisk-chu1k2mt/ramdisk
250 03:00:00.018412 >> 166792 blocks
251 03:00:07.727583 Adding RAMdisk u-boot header.
252 03:00:07.728498 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/951292/extract-overlay-ramdisk-chu1k2mt/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/951292/extract-overlay-ramdisk-chu1k2mt/ramdisk.cpio.gz.uboot
253 03:00:07.971560 output: Image Name:
254 03:00:07.972202 output: Created: Thu Nov 7 03:00:07 2024
255 03:00:07.972731 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 03:00:07.973205 output: Data Size: 23433147 Bytes = 22883.93 KiB = 22.35 MiB
257 03:00:07.973648 output: Load Address: 00000000
258 03:00:07.974085 output: Entry Point: 00000000
259 03:00:07.974516 output:
260 03:00:07.975619 rename /var/lib/lava/dispatcher/tmp/951292/extract-overlay-ramdisk-chu1k2mt/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/ramdisk/ramdisk.cpio.gz.uboot
261 03:00:07.976436 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 03:00:07.977038 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 03:00:07.977619 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
264 03:00:07.978135 No LXC device requested
265 03:00:07.978690 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 03:00:07.979255 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
267 03:00:07.979806 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 03:00:07.980299 Checking files for TFTP limit of 4294967296 bytes.
269 03:00:07.983211 end: 1 tftp-deploy (duration 00:00:41) [common]
270 03:00:07.983839 start: 2 uboot-action (timeout 00:05:00) [common]
271 03:00:07.984459 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 03:00:07.985015 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 03:00:07.985567 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 03:00:07.986151 Using kernel file from prepare-kernel: 951292/tftp-deploy-ogd8eilf/kernel/uImage
275 03:00:07.986854 substitutions:
276 03:00:07.987307 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 03:00:07.987755 - {DTB_ADDR}: 0x01070000
278 03:00:07.988248 - {DTB}: 951292/tftp-deploy-ogd8eilf/dtb/meson-g12b-a311d-libretech-cc.dtb
279 03:00:07.988695 - {INITRD}: 951292/tftp-deploy-ogd8eilf/ramdisk/ramdisk.cpio.gz.uboot
280 03:00:07.989136 - {KERNEL_ADDR}: 0x01080000
281 03:00:07.989572 - {KERNEL}: 951292/tftp-deploy-ogd8eilf/kernel/uImage
282 03:00:07.990006 - {LAVA_MAC}: None
283 03:00:07.990486 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/951292/extract-nfsrootfs-889wda7d
284 03:00:07.990929 - {NFS_SERVER_IP}: 192.168.6.2
285 03:00:07.991363 - {PRESEED_CONFIG}: None
286 03:00:07.991793 - {PRESEED_LOCAL}: None
287 03:00:07.992259 - {RAMDISK_ADDR}: 0x08000000
288 03:00:07.992691 - {RAMDISK}: 951292/tftp-deploy-ogd8eilf/ramdisk/ramdisk.cpio.gz.uboot
289 03:00:07.993120 - {ROOT_PART}: None
290 03:00:07.993550 - {ROOT}: None
291 03:00:07.993983 - {SERVER_IP}: 192.168.6.2
292 03:00:07.994411 - {TEE_ADDR}: 0x83000000
293 03:00:07.994839 - {TEE}: None
294 03:00:07.995270 Parsed boot commands:
295 03:00:07.995689 - setenv autoload no
296 03:00:07.996141 - setenv initrd_high 0xffffffff
297 03:00:07.996571 - setenv fdt_high 0xffffffff
298 03:00:07.996999 - dhcp
299 03:00:07.997423 - setenv serverip 192.168.6.2
300 03:00:07.997846 - tftpboot 0x01080000 951292/tftp-deploy-ogd8eilf/kernel/uImage
301 03:00:07.998271 - tftpboot 0x08000000 951292/tftp-deploy-ogd8eilf/ramdisk/ramdisk.cpio.gz.uboot
302 03:00:07.998699 - tftpboot 0x01070000 951292/tftp-deploy-ogd8eilf/dtb/meson-g12b-a311d-libretech-cc.dtb
303 03:00:07.999126 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/951292/extract-nfsrootfs-889wda7d,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 03:00:07.999569 - bootm 0x01080000 0x08000000 0x01070000
305 03:00:08.000150 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 03:00:08.001800 start: 2.3 connect-device (timeout 00:05:00) [common]
308 03:00:08.002264 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 03:00:08.018564 Setting prompt string to ['lava-test: # ']
310 03:00:08.020195 end: 2.3 connect-device (duration 00:00:00) [common]
311 03:00:08.020868 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 03:00:08.021484 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 03:00:08.022060 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 03:00:08.023436 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 03:00:08.064671 >> OK - accepted request
316 03:00:08.066920 Returned 0 in 0 seconds
317 03:00:08.168131 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 03:00:08.169859 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 03:00:08.170520 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 03:00:08.171083 Setting prompt string to ['Hit any key to stop autoboot']
322 03:00:08.171592 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 03:00:08.173419 Trying 192.168.56.21...
324 03:00:08.173945 Connected to conserv1.
325 03:00:08.174401 Escape character is '^]'.
326 03:00:08.174861
327 03:00:08.175323 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 03:00:08.175779
329 03:00:20.001006 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 03:00:20.001393 bl2_stage_init 0x01
331 03:00:20.001608 bl2_stage_init 0x81
332 03:00:20.006476 hw id: 0x0000 - pwm id 0x01
333 03:00:20.006742 bl2_stage_init 0xc1
334 03:00:20.006949 bl2_stage_init 0x02
335 03:00:20.007149
336 03:00:20.012078 L0:00000000
337 03:00:20.012325 L1:20000703
338 03:00:20.012529 L2:00008067
339 03:00:20.012736 L3:14000000
340 03:00:20.017702 B2:00402000
341 03:00:20.017941 B1:e0f83180
342 03:00:20.018158
343 03:00:20.018358 TE: 58167
344 03:00:20.018559
345 03:00:20.023287 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 03:00:20.023540
347 03:00:20.023743 Board ID = 1
348 03:00:20.028992 Set A53 clk to 24M
349 03:00:20.029253 Set A73 clk to 24M
350 03:00:20.029454 Set clk81 to 24M
351 03:00:20.034536 A53 clk: 1200 MHz
352 03:00:20.034785 A73 clk: 1200 MHz
353 03:00:20.034986 CLK81: 166.6M
354 03:00:20.035184 smccc: 00012abd
355 03:00:20.040212 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 03:00:20.045829 board id: 1
357 03:00:20.050774 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 03:00:20.062331 fw parse done
359 03:00:20.067237 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 03:00:20.109857 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 03:00:20.121742 PIEI prepare done
362 03:00:20.121993 fastboot data load
363 03:00:20.122197 fastboot data verify
364 03:00:20.127318 verify result: 266
365 03:00:20.132974 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 03:00:20.133213 LPDDR4 probe
367 03:00:20.133413 ddr clk to 1584MHz
368 03:00:20.139900 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 03:00:20.178155
370 03:00:20.178437 dmc_version 0001
371 03:00:20.183886 Check phy result
372 03:00:20.190700 INFO : End of CA training
373 03:00:20.190962 INFO : End of initialization
374 03:00:20.196285 INFO : Training has run successfully!
375 03:00:20.196534 Check phy result
376 03:00:20.201951 INFO : End of initialization
377 03:00:20.202196 INFO : End of read enable training
378 03:00:20.207524 INFO : End of fine write leveling
379 03:00:20.213113 INFO : End of Write leveling coarse delay
380 03:00:20.213355 INFO : Training has run successfully!
381 03:00:20.213562 Check phy result
382 03:00:20.218718 INFO : End of initialization
383 03:00:20.218970 INFO : End of read dq deskew training
384 03:00:20.224321 INFO : End of MPR read delay center optimization
385 03:00:20.229988 INFO : End of write delay center optimization
386 03:00:20.235527 INFO : End of read delay center optimization
387 03:00:20.235778 INFO : End of max read latency training
388 03:00:20.241107 INFO : Training has run successfully!
389 03:00:20.241346 1D training succeed
390 03:00:20.249624 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 03:00:20.296999 Check phy result
392 03:00:20.297287 INFO : End of initialization
393 03:00:20.319414 INFO : End of 2D read delay Voltage center optimization
394 03:00:20.338923 INFO : End of 2D read delay Voltage center optimization
395 03:00:20.391148 INFO : End of 2D write delay Voltage center optimization
396 03:00:20.441296 INFO : End of 2D write delay Voltage center optimization
397 03:00:20.446811 INFO : Training has run successfully!
398 03:00:20.447065
399 03:00:20.447276 channel==0
400 03:00:20.452366 RxClkDly_Margin_A0==88 ps 9
401 03:00:20.452619 TxDqDly_Margin_A0==98 ps 10
402 03:00:20.458005 RxClkDly_Margin_A1==88 ps 9
403 03:00:20.458248 TxDqDly_Margin_A1==88 ps 9
404 03:00:20.458455 TrainedVREFDQ_A0==74
405 03:00:20.463565 TrainedVREFDQ_A1==74
406 03:00:20.463809 VrefDac_Margin_A0==25
407 03:00:20.464046 DeviceVref_Margin_A0==40
408 03:00:20.469138 VrefDac_Margin_A1==25
409 03:00:20.469384 DeviceVref_Margin_A1==40
410 03:00:20.469589
411 03:00:20.469792
412 03:00:20.469994 channel==1
413 03:00:20.474728 RxClkDly_Margin_A0==98 ps 10
414 03:00:20.474964 TxDqDly_Margin_A0==98 ps 10
415 03:00:20.480405 RxClkDly_Margin_A1==88 ps 9
416 03:00:20.480646 TxDqDly_Margin_A1==88 ps 9
417 03:00:20.486014 TrainedVREFDQ_A0==77
418 03:00:20.486252 TrainedVREFDQ_A1==77
419 03:00:20.486459 VrefDac_Margin_A0==22
420 03:00:20.491611 DeviceVref_Margin_A0==37
421 03:00:20.491854 VrefDac_Margin_A1==24
422 03:00:20.497225 DeviceVref_Margin_A1==37
423 03:00:20.497472
424 03:00:20.497683 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 03:00:20.497887
426 03:00:20.530796 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000019 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 03:00:20.531156 2D training succeed
428 03:00:20.536412 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 03:00:20.542047 auto size-- 65535DDR cs0 size: 2048MB
430 03:00:20.542316 DDR cs1 size: 2048MB
431 03:00:20.547554 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 03:00:20.547812 cs0 DataBus test pass
433 03:00:20.553136 cs1 DataBus test pass
434 03:00:20.553397 cs0 AddrBus test pass
435 03:00:20.553603 cs1 AddrBus test pass
436 03:00:20.553805
437 03:00:20.558758 100bdlr_step_size ps== 420
438 03:00:20.559015 result report
439 03:00:20.564408 boot times 0Enable ddr reg access
440 03:00:20.569604 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 03:00:20.583179 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 03:00:21.156952 0.0;M3 CHK:0;cm4_sp_mode 0
443 03:00:21.157333 MVN_1=0x00000000
444 03:00:21.162502 MVN_2=0x00000000
445 03:00:21.168219 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 03:00:21.168471 OPS=0x10
447 03:00:21.168692 ring efuse init
448 03:00:21.168895 chipver efuse init
449 03:00:21.176430 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 03:00:21.176682 [0.018961 Inits done]
451 03:00:21.183939 secure task start!
452 03:00:21.184219 high task start!
453 03:00:21.184427 low task start!
454 03:00:21.184630 run into bl31
455 03:00:21.190621 NOTICE: BL31: v1.3(release):4fc40b1
456 03:00:21.197825 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 03:00:21.198114 NOTICE: BL31: G12A normal boot!
458 03:00:21.223793 NOTICE: BL31: BL33 decompress pass
459 03:00:21.229539 ERROR: Error initializing runtime service opteed_fast
460 03:00:22.462459
461 03:00:22.463138
462 03:00:22.470848 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 03:00:22.471347
464 03:00:22.471805 Model: Libre Computer AML-A311D-CC Alta
465 03:00:22.678444 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 03:00:22.702555 DRAM: 2 GiB (effective 3.8 GiB)
467 03:00:22.845466 Core: 408 devices, 31 uclasses, devicetree: separate
468 03:00:22.850717 WDT: Not starting watchdog@f0d0
469 03:00:22.883755 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 03:00:22.896173 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 03:00:22.901108 ** Bad device specification mmc 0 **
472 03:00:22.911458 Card did not respond to voltage select! : -110
473 03:00:22.919106 ** Bad device specification mmc 0 **
474 03:00:22.919594 Couldn't find partition mmc 0
475 03:00:22.927409 Card did not respond to voltage select! : -110
476 03:00:22.932917 ** Bad device specification mmc 0 **
477 03:00:22.933404 Couldn't find partition mmc 0
478 03:00:22.937523 Error: could not access storage.
479 03:00:24.200552 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 03:00:24.201171 bl2_stage_init 0x01
481 03:00:24.201639 bl2_stage_init 0x81
482 03:00:24.206133 hw id: 0x0000 - pwm id 0x01
483 03:00:24.206616 bl2_stage_init 0xc1
484 03:00:24.207065 bl2_stage_init 0x02
485 03:00:24.207508
486 03:00:24.211644 L0:00000000
487 03:00:24.212163 L1:20000703
488 03:00:24.212612 L2:00008067
489 03:00:24.213050 L3:14000000
490 03:00:24.214734 B2:00402000
491 03:00:24.215204 B1:e0f83180
492 03:00:24.215647
493 03:00:24.216122 TE: 58167
494 03:00:24.216564
495 03:00:24.225943 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 03:00:24.226419
497 03:00:24.226865 Board ID = 1
498 03:00:24.227305 Set A53 clk to 24M
499 03:00:24.227740 Set A73 clk to 24M
500 03:00:24.231395 Set clk81 to 24M
501 03:00:24.231862 A53 clk: 1200 MHz
502 03:00:24.232352 A73 clk: 1200 MHz
503 03:00:24.237100 CLK81: 166.6M
504 03:00:24.237574 smccc: 00012abe
505 03:00:24.242605 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 03:00:24.243080 board id: 1
507 03:00:24.251125 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 03:00:24.261889 fw parse done
509 03:00:24.266979 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 03:00:24.310416 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 03:00:24.321281 PIEI prepare done
512 03:00:24.321758 fastboot data load
513 03:00:24.322207 fastboot data verify
514 03:00:24.326913 verify result: 266
515 03:00:24.332625 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 03:00:24.333097 LPDDR4 probe
517 03:00:24.333540 ddr clk to 1584MHz
518 03:00:24.340560 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 03:00:24.377752
520 03:00:24.378244 dmc_version 0001
521 03:00:24.384496 Check phy result
522 03:00:24.390295 INFO : End of CA training
523 03:00:24.390767 INFO : End of initialization
524 03:00:24.395899 INFO : Training has run successfully!
525 03:00:24.396416 Check phy result
526 03:00:24.401491 INFO : End of initialization
527 03:00:24.401960 INFO : End of read enable training
528 03:00:24.404825 INFO : End of fine write leveling
529 03:00:24.410363 INFO : End of Write leveling coarse delay
530 03:00:24.415966 INFO : Training has run successfully!
531 03:00:24.416484 Check phy result
532 03:00:24.416929 INFO : End of initialization
533 03:00:24.421722 INFO : End of read dq deskew training
534 03:00:24.427153 INFO : End of MPR read delay center optimization
535 03:00:24.427617 INFO : End of write delay center optimization
536 03:00:24.432788 INFO : End of read delay center optimization
537 03:00:24.438366 INFO : End of max read latency training
538 03:00:24.438830 INFO : Training has run successfully!
539 03:00:24.443969 1D training succeed
540 03:00:24.449933 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 03:00:24.497609 Check phy result
542 03:00:24.498084 INFO : End of initialization
543 03:00:24.518439 INFO : End of 2D read delay Voltage center optimization
544 03:00:24.539544 INFO : End of 2D read delay Voltage center optimization
545 03:00:24.591692 INFO : End of 2D write delay Voltage center optimization
546 03:00:24.641119 INFO : End of 2D write delay Voltage center optimization
547 03:00:24.646624 INFO : Training has run successfully!
548 03:00:24.647136
549 03:00:24.647592 channel==0
550 03:00:24.652083 RxClkDly_Margin_A0==88 ps 9
551 03:00:24.652575 TxDqDly_Margin_A0==98 ps 10
552 03:00:24.657811 RxClkDly_Margin_A1==88 ps 9
553 03:00:24.658297 TxDqDly_Margin_A1==98 ps 10
554 03:00:24.658747 TrainedVREFDQ_A0==74
555 03:00:24.663347 TrainedVREFDQ_A1==74
556 03:00:24.663823 VrefDac_Margin_A0==25
557 03:00:24.664313 DeviceVref_Margin_A0==40
558 03:00:24.669050 VrefDac_Margin_A1==25
559 03:00:24.669516 DeviceVref_Margin_A1==40
560 03:00:24.669960
561 03:00:24.670396
562 03:00:24.674476 channel==1
563 03:00:24.674949 RxClkDly_Margin_A0==98 ps 10
564 03:00:24.675388 TxDqDly_Margin_A0==88 ps 9
565 03:00:24.680169 RxClkDly_Margin_A1==88 ps 9
566 03:00:24.680677 TxDqDly_Margin_A1==88 ps 9
567 03:00:24.685729 TrainedVREFDQ_A0==77
568 03:00:24.686205 TrainedVREFDQ_A1==77
569 03:00:24.686650 VrefDac_Margin_A0==22
570 03:00:24.691318 DeviceVref_Margin_A0==37
571 03:00:24.691816 VrefDac_Margin_A1==24
572 03:00:24.696947 DeviceVref_Margin_A1==37
573 03:00:24.697477
574 03:00:24.697939 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 03:00:24.698402
576 03:00:24.730485 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
577 03:00:24.731020 2D training succeed
578 03:00:24.736147 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 03:00:24.741743 auto size-- 65535DDR cs0 size: 2048MB
580 03:00:24.742219 DDR cs1 size: 2048MB
581 03:00:24.747319 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 03:00:24.747789 cs0 DataBus test pass
583 03:00:24.752903 cs1 DataBus test pass
584 03:00:24.753378 cs0 AddrBus test pass
585 03:00:24.753821 cs1 AddrBus test pass
586 03:00:24.754259
587 03:00:24.758510 100bdlr_step_size ps== 420
588 03:00:24.759033 result report
589 03:00:24.764114 boot times 0Enable ddr reg access
590 03:00:24.769367 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 03:00:24.782795 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 03:00:25.356419 0.0;M3 CHK:0;cm4_sp_mode 0
593 03:00:25.357076 MVN_1=0x00000000
594 03:00:25.361873 MVN_2=0x00000000
595 03:00:25.367696 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 03:00:25.368272 OPS=0x10
597 03:00:25.368741 ring efuse init
598 03:00:25.369231 chipver efuse init
599 03:00:25.373284 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 03:00:25.378877 [0.018960 Inits done]
601 03:00:25.379371 secure task start!
602 03:00:25.379809 high task start!
603 03:00:25.383552 low task start!
604 03:00:25.384056 run into bl31
605 03:00:25.390040 NOTICE: BL31: v1.3(release):4fc40b1
606 03:00:25.397045 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 03:00:25.397520 NOTICE: BL31: G12A normal boot!
608 03:00:25.423262 NOTICE: BL31: BL33 decompress pass
609 03:00:25.428912 ERROR: Error initializing runtime service opteed_fast
610 03:00:26.661896
611 03:00:26.662559
612 03:00:26.670197 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 03:00:26.670700
614 03:00:26.671162 Model: Libre Computer AML-A311D-CC Alta
615 03:00:26.878730 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 03:00:26.901049 DRAM: 2 GiB (effective 3.8 GiB)
617 03:00:27.045094 Core: 408 devices, 31 uclasses, devicetree: separate
618 03:00:27.050491 WDT: Not starting watchdog@f0d0
619 03:00:27.083176 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 03:00:27.095706 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 03:00:27.100576 ** Bad device specification mmc 0 **
622 03:00:27.111031 Card did not respond to voltage select! : -110
623 03:00:27.118585 ** Bad device specification mmc 0 **
624 03:00:27.119074 Couldn't find partition mmc 0
625 03:00:27.126993 Card did not respond to voltage select! : -110
626 03:00:27.132472 ** Bad device specification mmc 0 **
627 03:00:27.132961 Couldn't find partition mmc 0
628 03:00:27.137494 Error: could not access storage.
629 03:00:27.481071 Net: eth0: ethernet@ff3f0000
630 03:00:27.481701 starting USB...
631 03:00:27.732919 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 03:00:27.733479 Starting the controller
633 03:00:27.739796 USB XHCI 1.10
634 03:00:29.452265 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 03:00:29.452877 bl2_stage_init 0x01
636 03:00:29.453125 bl2_stage_init 0x81
637 03:00:29.457719 hw id: 0x0000 - pwm id 0x01
638 03:00:29.458115 bl2_stage_init 0xc1
639 03:00:29.458672 bl2_stage_init 0x02
640 03:00:29.459375
641 03:00:29.463307 L0:00000000
642 03:00:29.463692 L1:20000703
643 03:00:29.464058 L2:00008067
644 03:00:29.464373 L3:14000000
645 03:00:29.468985 B2:00402000
646 03:00:29.469255 B1:e0f83180
647 03:00:29.469486
648 03:00:29.469708 TE: 58159
649 03:00:29.469927
650 03:00:29.474495 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 03:00:29.474755
652 03:00:29.474984 Board ID = 1
653 03:00:29.480237 Set A53 clk to 24M
654 03:00:29.480500 Set A73 clk to 24M
655 03:00:29.480725 Set clk81 to 24M
656 03:00:29.485739 A53 clk: 1200 MHz
657 03:00:29.486000 A73 clk: 1200 MHz
658 03:00:29.486224 CLK81: 166.6M
659 03:00:29.486440 smccc: 00012ab5
660 03:00:29.491335 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 03:00:29.496988 board id: 1
662 03:00:29.501958 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 03:00:29.513491 fw parse done
664 03:00:29.519414 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 03:00:29.561664 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 03:00:29.573035 PIEI prepare done
667 03:00:29.573498 fastboot data load
668 03:00:29.573827 fastboot data verify
669 03:00:29.578671 verify result: 266
670 03:00:29.584273 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 03:00:29.584651 LPDDR4 probe
672 03:00:29.584967 ddr clk to 1584MHz
673 03:00:29.592282 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 03:00:29.628735
675 03:00:29.629403 dmc_version 0001
676 03:00:29.636366 Check phy result
677 03:00:29.642222 INFO : End of CA training
678 03:00:29.642846 INFO : End of initialization
679 03:00:29.647737 INFO : Training has run successfully!
680 03:00:29.648409 Check phy result
681 03:00:29.653328 INFO : End of initialization
682 03:00:29.653925 INFO : End of read enable training
683 03:00:29.659130 INFO : End of fine write leveling
684 03:00:29.664568 INFO : End of Write leveling coarse delay
685 03:00:29.665160 INFO : Training has run successfully!
686 03:00:29.665608 Check phy result
687 03:00:29.670119 INFO : End of initialization
688 03:00:29.670681 INFO : End of read dq deskew training
689 03:00:29.675689 INFO : End of MPR read delay center optimization
690 03:00:29.681316 INFO : End of write delay center optimization
691 03:00:29.686900 INFO : End of read delay center optimization
692 03:00:29.687457 INFO : End of max read latency training
693 03:00:29.692543 INFO : Training has run successfully!
694 03:00:29.693136 1D training succeed
695 03:00:29.701631 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 03:00:29.749417 Check phy result
697 03:00:29.750081 INFO : End of initialization
698 03:00:29.770964 INFO : End of 2D read delay Voltage center optimization
699 03:00:29.791250 INFO : End of 2D read delay Voltage center optimization
700 03:00:29.843125 INFO : End of 2D write delay Voltage center optimization
701 03:00:29.892284 INFO : End of 2D write delay Voltage center optimization
702 03:00:29.897908 INFO : Training has run successfully!
703 03:00:29.898412
704 03:00:29.898854 channel==0
705 03:00:29.903475 RxClkDly_Margin_A0==88 ps 9
706 03:00:29.904027 TxDqDly_Margin_A0==98 ps 10
707 03:00:29.906818 RxClkDly_Margin_A1==88 ps 9
708 03:00:29.907317 TxDqDly_Margin_A1==98 ps 10
709 03:00:29.912570 TrainedVREFDQ_A0==74
710 03:00:29.913135 TrainedVREFDQ_A1==75
711 03:00:29.913631 VrefDac_Margin_A0==25
712 03:00:29.918032 DeviceVref_Margin_A0==40
713 03:00:29.918548 VrefDac_Margin_A1==25
714 03:00:29.923607 DeviceVref_Margin_A1==39
715 03:00:29.924142
716 03:00:29.924585
717 03:00:29.925021 channel==1
718 03:00:29.925450 RxClkDly_Margin_A0==88 ps 9
719 03:00:29.927112 TxDqDly_Margin_A0==98 ps 10
720 03:00:29.932630 RxClkDly_Margin_A1==98 ps 10
721 03:00:29.933131 TxDqDly_Margin_A1==88 ps 9
722 03:00:29.933573 TrainedVREFDQ_A0==77
723 03:00:29.938236 TrainedVREFDQ_A1==77
724 03:00:29.938745 VrefDac_Margin_A0==22
725 03:00:29.943854 DeviceVref_Margin_A0==37
726 03:00:29.944405 VrefDac_Margin_A1==22
727 03:00:29.944840 DeviceVref_Margin_A1==37
728 03:00:29.945269
729 03:00:29.952793 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 03:00:29.953302
731 03:00:29.980786 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
732 03:00:29.981341 2D training succeed
733 03:00:29.986521 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 03:00:29.991910 auto size-- 65535DDR cs0 size: 2048MB
735 03:00:29.992441 DDR cs1 size: 2048MB
736 03:00:29.997490 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 03:00:29.997995 cs0 DataBus test pass
738 03:00:30.003125 cs1 DataBus test pass
739 03:00:30.003628 cs0 AddrBus test pass
740 03:00:30.008712 cs1 AddrBus test pass
741 03:00:30.009210
742 03:00:30.009653 100bdlr_step_size ps== 420
743 03:00:30.010093 result report
744 03:00:30.014320 boot times 0Enable ddr reg access
745 03:00:30.020628 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 03:00:30.034058 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 03:00:30.606034 0.0;M3 CHK:0;cm4_sp_mode 0
748 03:00:30.606663 MVN_1=0x00000000
749 03:00:30.611558 MVN_2=0x00000000
750 03:00:30.617334 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 03:00:30.617850 OPS=0x10
752 03:00:30.618289 ring efuse init
753 03:00:30.618719 chipver efuse init
754 03:00:30.622897 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 03:00:30.628492 [0.018960 Inits done]
756 03:00:30.628988 secure task start!
757 03:00:30.629422 high task start!
758 03:00:30.633109 low task start!
759 03:00:30.633599 run into bl31
760 03:00:30.639746 NOTICE: BL31: v1.3(release):4fc40b1
761 03:00:30.647595 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 03:00:30.648129 NOTICE: BL31: G12A normal boot!
763 03:00:30.672912 NOTICE: BL31: BL33 decompress pass
764 03:00:30.678613 ERROR: Error initializing runtime service opteed_fast
765 03:00:31.911477
766 03:00:31.912184
767 03:00:31.919919 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 03:00:31.920500
769 03:00:31.920958 Model: Libre Computer AML-A311D-CC Alta
770 03:00:32.128320 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 03:00:32.151724 DRAM: 2 GiB (effective 3.8 GiB)
772 03:00:32.294694 Core: 408 devices, 31 uclasses, devicetree: separate
773 03:00:32.300650 WDT: Not starting watchdog@f0d0
774 03:00:32.332813 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 03:00:32.345267 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 03:00:32.350326 ** Bad device specification mmc 0 **
777 03:00:32.362012 Card did not respond to voltage select! : -110
778 03:00:32.368410 ** Bad device specification mmc 0 **
779 03:00:32.368972 Couldn't find partition mmc 0
780 03:00:32.376698 Card did not respond to voltage select! : -110
781 03:00:32.382119 ** Bad device specification mmc 0 **
782 03:00:32.382662 Couldn't find partition mmc 0
783 03:00:32.387134 Error: could not access storage.
784 03:00:32.730710 Net: eth0: ethernet@ff3f0000
785 03:00:32.731328 starting USB...
786 03:00:32.982608 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 03:00:32.983275 Starting the controller
788 03:00:32.989459 USB XHCI 1.10
789 03:00:35.151177 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 03:00:35.151814 bl2_stage_init 0x01
791 03:00:35.152345 bl2_stage_init 0x81
792 03:00:35.156571 hw id: 0x0000 - pwm id 0x01
793 03:00:35.157090 bl2_stage_init 0xc1
794 03:00:35.157549 bl2_stage_init 0x02
795 03:00:35.158002
796 03:00:35.162306 L0:00000000
797 03:00:35.162813 L1:20000703
798 03:00:35.163289 L2:00008067
799 03:00:35.163765 L3:14000000
800 03:00:35.165230 B2:00402000
801 03:00:35.165734 B1:e0f83180
802 03:00:35.166182
803 03:00:35.166627 TE: 58124
804 03:00:35.167067
805 03:00:35.176236 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 03:00:35.176751
807 03:00:35.177203 Board ID = 1
808 03:00:35.177642 Set A53 clk to 24M
809 03:00:35.178077 Set A73 clk to 24M
810 03:00:35.181783 Set clk81 to 24M
811 03:00:35.182284 A53 clk: 1200 MHz
812 03:00:35.182732 A73 clk: 1200 MHz
813 03:00:35.185482 CLK81: 166.6M
814 03:00:35.185980 smccc: 00012a91
815 03:00:35.191152 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 03:00:35.196589 board id: 1
817 03:00:35.201591 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 03:00:35.212259 fw parse done
819 03:00:35.218219 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 03:00:35.260827 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 03:00:35.271755 PIEI prepare done
822 03:00:35.272306 fastboot data load
823 03:00:35.272767 fastboot data verify
824 03:00:35.277353 verify result: 266
825 03:00:35.283006 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 03:00:35.283512 LPDDR4 probe
827 03:00:35.283958 ddr clk to 1584MHz
828 03:00:35.290898 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 03:00:35.328302
830 03:00:35.328847 dmc_version 0001
831 03:00:35.334884 Check phy result
832 03:00:35.340828 INFO : End of CA training
833 03:00:35.341349 INFO : End of initialization
834 03:00:35.346410 INFO : Training has run successfully!
835 03:00:35.346916 Check phy result
836 03:00:35.352027 INFO : End of initialization
837 03:00:35.352532 INFO : End of read enable training
838 03:00:35.357599 INFO : End of fine write leveling
839 03:00:35.363159 INFO : End of Write leveling coarse delay
840 03:00:35.363667 INFO : Training has run successfully!
841 03:00:35.364157 Check phy result
842 03:00:35.368791 INFO : End of initialization
843 03:00:35.369288 INFO : End of read dq deskew training
844 03:00:35.374389 INFO : End of MPR read delay center optimization
845 03:00:35.380036 INFO : End of write delay center optimization
846 03:00:35.385500 INFO : End of read delay center optimization
847 03:00:35.386010 INFO : End of max read latency training
848 03:00:35.391195 INFO : Training has run successfully!
849 03:00:35.391695 1D training succeed
850 03:00:35.399460 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 03:00:35.447963 Check phy result
852 03:00:35.448569 INFO : End of initialization
853 03:00:35.469669 INFO : End of 2D read delay Voltage center optimization
854 03:00:35.489872 INFO : End of 2D read delay Voltage center optimization
855 03:00:35.542011 INFO : End of 2D write delay Voltage center optimization
856 03:00:35.591380 INFO : End of 2D write delay Voltage center optimization
857 03:00:35.596829 INFO : Training has run successfully!
858 03:00:35.597336
859 03:00:35.597795 channel==0
860 03:00:35.602446 RxClkDly_Margin_A0==88 ps 9
861 03:00:35.602950 TxDqDly_Margin_A0==98 ps 10
862 03:00:35.605801 RxClkDly_Margin_A1==88 ps 9
863 03:00:35.606302 TxDqDly_Margin_A1==88 ps 9
864 03:00:35.611398 TrainedVREFDQ_A0==74
865 03:00:35.611915 TrainedVREFDQ_A1==74
866 03:00:35.612434 VrefDac_Margin_A0==25
867 03:00:35.616923 DeviceVref_Margin_A0==40
868 03:00:35.617436 VrefDac_Margin_A1==25
869 03:00:35.624782 DeviceVref_Margin_A1==40
870 03:00:35.625283
871 03:00:35.625714
872 03:00:35.626142 channel==1
873 03:00:35.626567 RxClkDly_Margin_A0==98 ps 10
874 03:00:35.628009 TxDqDly_Margin_A0==98 ps 10
875 03:00:35.628504 RxClkDly_Margin_A1==88 ps 9
876 03:00:35.633552 TxDqDly_Margin_A1==88 ps 9
877 03:00:35.634039 TrainedVREFDQ_A0==77
878 03:00:35.634474 TrainedVREFDQ_A1==77
879 03:00:35.639228 VrefDac_Margin_A0==22
880 03:00:35.639748 DeviceVref_Margin_A0==37
881 03:00:35.644782 VrefDac_Margin_A1==24
882 03:00:35.645279 DeviceVref_Margin_A1==37
883 03:00:35.645705
884 03:00:35.650346 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 03:00:35.650839
886 03:00:35.678336 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
887 03:00:35.683928 2D training succeed
888 03:00:35.689559 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 03:00:35.690058 auto size-- 65535DDR cs0 size: 2048MB
890 03:00:35.695162 DDR cs1 size: 2048MB
891 03:00:35.695647 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 03:00:35.700753 cs0 DataBus test pass
893 03:00:35.701238 cs1 DataBus test pass
894 03:00:35.701668 cs0 AddrBus test pass
895 03:00:35.706364 cs1 AddrBus test pass
896 03:00:35.706855
897 03:00:35.707286 100bdlr_step_size ps== 420
898 03:00:35.707723 result report
899 03:00:35.711950 boot times 0Enable ddr reg access
900 03:00:35.718830 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 03:00:35.732749 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 03:00:36.306829 0.0;M3 CHK:0;cm4_sp_mode 0
903 03:00:36.307465 MVN_1=0x00000000
904 03:00:36.312352 MVN_2=0x00000000
905 03:00:36.318213 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 03:00:36.318720 OPS=0x10
907 03:00:36.319181 ring efuse init
908 03:00:36.319628 chipver efuse init
909 03:00:36.323709 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 03:00:36.329266 [0.018961 Inits done]
911 03:00:36.329766 secure task start!
912 03:00:36.330213 high task start!
913 03:00:36.333509 low task start!
914 03:00:36.334006 run into bl31
915 03:00:36.340529 NOTICE: BL31: v1.3(release):4fc40b1
916 03:00:36.348224 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 03:00:36.348748 NOTICE: BL31: G12A normal boot!
918 03:00:36.373696 NOTICE: BL31: BL33 decompress pass
919 03:00:36.378471 ERROR: Error initializing runtime service opteed_fast
920 03:00:37.612309
921 03:00:37.612986
922 03:00:37.620141 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 03:00:37.620683
924 03:00:37.621154 Model: Libre Computer AML-A311D-CC Alta
925 03:00:37.829120 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 03:00:37.852108 DRAM: 2 GiB (effective 3.8 GiB)
927 03:00:37.995527 Core: 408 devices, 31 uclasses, devicetree: separate
928 03:00:38.000686 WDT: Not starting watchdog@f0d0
929 03:00:38.033598 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 03:00:38.046002 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 03:00:38.050213 ** Bad device specification mmc 0 **
932 03:00:38.061489 Card did not respond to voltage select! : -110
933 03:00:38.068335 ** Bad device specification mmc 0 **
934 03:00:38.068851 Couldn't find partition mmc 0
935 03:00:38.077449 Card did not respond to voltage select! : -110
936 03:00:38.082880 ** Bad device specification mmc 0 **
937 03:00:38.083391 Couldn't find partition mmc 0
938 03:00:38.087270 Error: could not access storage.
939 03:00:38.431217 Net: eth0: ethernet@ff3f0000
940 03:00:38.431852 starting USB...
941 03:00:38.683308 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 03:00:38.683936 Starting the controller
943 03:00:38.689296 USB XHCI 1.10
944 03:00:40.550812 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
945 03:00:40.551505 bl2_stage_init 0x81
946 03:00:40.556245 hw id: 0x0000 - pwm id 0x01
947 03:00:40.556766 bl2_stage_init 0xc1
948 03:00:40.557226 bl2_stage_init 0x02
949 03:00:40.557676
950 03:00:40.561842 L0:00000000
951 03:00:40.562338 L1:20000703
952 03:00:40.562797 L2:00008067
953 03:00:40.563243 L3:14000000
954 03:00:40.563739 B2:00402000
955 03:00:40.564801 B1:e0f83180
956 03:00:40.565299
957 03:00:40.565755 TE: 58150
958 03:00:40.566204
959 03:00:40.575901 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
960 03:00:40.576464
961 03:00:40.576923 Board ID = 1
962 03:00:40.577371 Set A53 clk to 24M
963 03:00:40.577813 Set A73 clk to 24M
964 03:00:40.581587 Set clk81 to 24M
965 03:00:40.582081 A53 clk: 1200 MHz
966 03:00:40.582532 A73 clk: 1200 MHz
967 03:00:40.587093 CLK81: 166.6M
968 03:00:40.587578 smccc: 00012aac
969 03:00:40.592700 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
970 03:00:40.593193 board id: 1
971 03:00:40.601195 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
972 03:00:40.611864 fw parse done
973 03:00:40.617863 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
974 03:00:40.660478 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
975 03:00:40.671419 PIEI prepare done
976 03:00:40.671944 fastboot data load
977 03:00:40.672442 fastboot data verify
978 03:00:40.677000 verify result: 266
979 03:00:40.682595 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
980 03:00:40.683068 LPDDR4 probe
981 03:00:40.683498 ddr clk to 1584MHz
982 03:00:40.690897 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
983 03:00:40.727826
984 03:00:40.728383 dmc_version 0001
985 03:00:40.734465 Check phy result
986 03:00:40.740387 INFO : End of CA training
987 03:00:40.740860 INFO : End of initialization
988 03:00:40.746637 INFO : Training has run successfully!
989 03:00:40.747162 Check phy result
990 03:00:40.752003 INFO : End of initialization
991 03:00:40.752503 INFO : End of read enable training
992 03:00:40.755207 INFO : End of fine write leveling
993 03:00:40.760566 INFO : End of Write leveling coarse delay
994 03:00:40.766108 INFO : Training has run successfully!
995 03:00:40.766644 Check phy result
996 03:00:40.767099 INFO : End of initialization
997 03:00:40.771946 INFO : End of read dq deskew training
998 03:00:40.776517 INFO : End of MPR read delay center optimization
999 03:00:40.781760 INFO : End of write delay center optimization
1000 03:00:40.782366 INFO : End of read delay center optimization
1001 03:00:40.787556 INFO : End of max read latency training
1002 03:00:40.793297 INFO : Training has run successfully!
1003 03:00:40.793774 1D training succeed
1004 03:00:40.798188 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 03:00:40.847607 Check phy result
1006 03:00:40.848156 INFO : End of initialization
1007 03:00:40.869321 INFO : End of 2D read delay Voltage center optimization
1008 03:00:40.889520 INFO : End of 2D read delay Voltage center optimization
1009 03:00:40.941569 INFO : End of 2D write delay Voltage center optimization
1010 03:00:40.991047 INFO : End of 2D write delay Voltage center optimization
1011 03:00:40.996544 INFO : Training has run successfully!
1012 03:00:40.997058
1013 03:00:40.997502 channel==0
1014 03:00:41.002116 RxClkDly_Margin_A0==88 ps 9
1015 03:00:41.002619 TxDqDly_Margin_A0==98 ps 10
1016 03:00:41.007798 RxClkDly_Margin_A1==88 ps 9
1017 03:00:41.008315 TxDqDly_Margin_A1==98 ps 10
1018 03:00:41.008757 TrainedVREFDQ_A0==74
1019 03:00:41.013299 TrainedVREFDQ_A1==74
1020 03:00:41.013786 VrefDac_Margin_A0==25
1021 03:00:41.014230 DeviceVref_Margin_A0==40
1022 03:00:41.018905 VrefDac_Margin_A1==25
1023 03:00:41.019382 DeviceVref_Margin_A1==40
1024 03:00:41.019816
1025 03:00:41.020285
1026 03:00:41.024515 channel==1
1027 03:00:41.024990 RxClkDly_Margin_A0==98 ps 10
1028 03:00:41.025425 TxDqDly_Margin_A0==98 ps 10
1029 03:00:41.030088 RxClkDly_Margin_A1==88 ps 9
1030 03:00:41.030558 TxDqDly_Margin_A1==88 ps 9
1031 03:00:41.035779 TrainedVREFDQ_A0==77
1032 03:00:41.036282 TrainedVREFDQ_A1==77
1033 03:00:41.036718 VrefDac_Margin_A0==22
1034 03:00:41.041275 DeviceVref_Margin_A0==37
1035 03:00:41.041740 VrefDac_Margin_A1==24
1036 03:00:41.046903 DeviceVref_Margin_A1==37
1037 03:00:41.047386
1038 03:00:41.047826 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1039 03:00:41.048295
1040 03:00:41.080512 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
1041 03:00:41.081070 2D training succeed
1042 03:00:41.086094 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1043 03:00:41.091811 auto size-- 65535DDR cs0 size: 2048MB
1044 03:00:41.092357 DDR cs1 size: 2048MB
1045 03:00:41.097296 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1046 03:00:41.097771 cs0 DataBus test pass
1047 03:00:41.102902 cs1 DataBus test pass
1048 03:00:41.103371 cs0 AddrBus test pass
1049 03:00:41.103802 cs1 AddrBus test pass
1050 03:00:41.104269
1051 03:00:41.108506 100bdlr_step_size ps== 420
1052 03:00:41.108986 result report
1053 03:00:41.114069 boot times 0Enable ddr reg access
1054 03:00:41.119426 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1055 03:00:41.132804 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1056 03:00:41.706675 0.0;M3 CHK:0;cm4_sp_mode 0
1057 03:00:41.707305 MVN_1=0x00000000
1058 03:00:41.712168 MVN_2=0x00000000
1059 03:00:41.717931 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1060 03:00:41.718473 OPS=0x10
1061 03:00:41.718956 ring efuse init
1062 03:00:41.719421 chipver efuse init
1063 03:00:41.723471 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1064 03:00:41.729079 [0.018960 Inits done]
1065 03:00:41.729594 secure task start!
1066 03:00:41.730059 high task start!
1067 03:00:41.733657 low task start!
1068 03:00:41.734163 run into bl31
1069 03:00:41.740325 NOTICE: BL31: v1.3(release):4fc40b1
1070 03:00:41.748139 NOTICE: BL31: Built : 15:58:17, May 22 2019
1071 03:00:41.748674 NOTICE: BL31: G12A normal boot!
1072 03:00:41.774086 NOTICE: BL31: BL33 decompress pass
1073 03:00:41.779769 ERROR: Error initializing runtime service opteed_fast
1074 03:00:43.012715
1075 03:00:43.013278
1076 03:00:43.021124 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1077 03:00:43.021579
1078 03:00:43.021944 Model: Libre Computer AML-A311D-CC Alta
1079 03:00:43.229394 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1080 03:00:43.251884 DRAM: 2 GiB (effective 3.8 GiB)
1081 03:00:43.395858 Core: 408 devices, 31 uclasses, devicetree: separate
1082 03:00:43.401696 WDT: Not starting watchdog@f0d0
1083 03:00:43.434018 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1084 03:00:43.446422 Loading Environment from FAT... Card did not respond to voltage select! : -110
1085 03:00:43.451400 ** Bad device specification mmc 0 **
1086 03:00:43.461732 Card did not respond to voltage select! : -110
1087 03:00:43.469386 ** Bad device specification mmc 0 **
1088 03:00:43.469873 Couldn't find partition mmc 0
1089 03:00:43.477717 Card did not respond to voltage select! : -110
1090 03:00:43.483240 ** Bad device specification mmc 0 **
1091 03:00:43.483726 Couldn't find partition mmc 0
1092 03:00:43.488296 Error: could not access storage.
1093 03:00:43.830798 Net: eth0: ethernet@ff3f0000
1094 03:00:43.831392 starting USB...
1095 03:00:44.082607 Bus usb@ff500000: Register 3000140 NbrPorts 3
1096 03:00:44.083137 Starting the controller
1097 03:00:44.089563 USB XHCI 1.10
1098 03:00:45.643766 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1099 03:00:45.652047 scanning usb for storage devices... 0 Storage Device(s) found
1101 03:00:45.703887 Hit any key to stop autoboot: 1
1102 03:00:45.704706 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1103 03:00:45.705313 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1104 03:00:45.705805 Setting prompt string to ['=>']
1105 03:00:45.706314 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1106 03:00:45.719496 0
1107 03:00:45.720383 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1108 03:00:45.720904 Sending with 10 millisecond of delay
1110 03:00:46.855831 => setenv autoload no
1111 03:00:46.866725 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1112 03:00:46.872139 setenv autoload no
1113 03:00:46.872960 Sending with 10 millisecond of delay
1115 03:00:48.671227 => setenv initrd_high 0xffffffff
1116 03:00:48.681986 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1117 03:00:48.682790 setenv initrd_high 0xffffffff
1118 03:00:48.683484 Sending with 10 millisecond of delay
1120 03:00:50.300229 => setenv fdt_high 0xffffffff
1121 03:00:50.310914 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1122 03:00:50.311585 setenv fdt_high 0xffffffff
1123 03:00:50.312109 Sending with 10 millisecond of delay
1125 03:00:50.603667 => dhcp
1126 03:00:50.614374 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1127 03:00:50.614968 dhcp
1128 03:00:50.615262 Speed: 1000, full duplex
1129 03:00:50.615531 BOOTP broadcast 1
1130 03:00:50.627137 DHCP client bound to address 192.168.6.27 (12 ms)
1131 03:00:50.627661 Sending with 10 millisecond of delay
1133 03:00:52.304773 => setenv serverip 192.168.6.2
1134 03:00:52.315792 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1135 03:00:52.317006 setenv serverip 192.168.6.2
1136 03:00:52.317856 Sending with 10 millisecond of delay
1138 03:00:56.043243 => tftpboot 0x01080000 951292/tftp-deploy-ogd8eilf/kernel/uImage
1139 03:00:56.054079 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1140 03:00:56.055176 tftpboot 0x01080000 951292/tftp-deploy-ogd8eilf/kernel/uImage
1141 03:00:56.055813 Speed: 1000, full duplex
1142 03:00:56.056504 Using ethernet@ff3f0000 device
1143 03:00:56.057208 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1144 03:00:56.062646 Filename '951292/tftp-deploy-ogd8eilf/kernel/uImage'.
1145 03:00:56.066483 Load address: 0x1080000
1146 03:00:59.083839 Loading: *################################################## 43.6 MiB
1147 03:00:59.084628 14.4 MiB/s
1148 03:00:59.085209 done
1149 03:00:59.088139 Bytes transferred = 45713984 (2b98a40 hex)
1150 03:00:59.089095 Sending with 10 millisecond of delay
1152 03:01:03.777472 => tftpboot 0x08000000 951292/tftp-deploy-ogd8eilf/ramdisk/ramdisk.cpio.gz.uboot
1153 03:01:03.788316 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1154 03:01:03.789282 tftpboot 0x08000000 951292/tftp-deploy-ogd8eilf/ramdisk/ramdisk.cpio.gz.uboot
1155 03:01:03.789748 Speed: 1000, full duplex
1156 03:01:03.790162 Using ethernet@ff3f0000 device
1157 03:01:03.791430 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1158 03:01:03.799963 Filename '951292/tftp-deploy-ogd8eilf/ramdisk/ramdisk.cpio.gz.uboot'.
1159 03:01:03.802858 Load address: 0x8000000
1160 03:01:09.638449 Loading: *#################T ####### UDP wrong checksum 000000ff 00006b0b
1161 03:01:09.652134 UDP wrong checksum 000000ff 0000f3fd
1162 03:01:10.411362 ######################### UDP wrong checksum 00000005 0000de60
1163 03:01:11.140547 UDP wrong checksum 000000ff 00009ea3
1164 03:01:11.192640 UDP wrong checksum 000000ff 00003196
1165 03:01:15.413856 T UDP wrong checksum 00000005 0000de60
1166 03:01:25.415862 T T UDP wrong checksum 00000005 0000de60
1167 03:01:28.772342 UDP wrong checksum 000000ff 00001e58
1168 03:01:28.813134 UDP wrong checksum 000000ff 0000b84a
1169 03:01:45.419926 T T T T UDP wrong checksum 00000005 0000de60
1170 03:02:00.424056 T T
1171 03:02:00.424746 Retry count exceeded; starting again
1173 03:02:00.426327 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1176 03:02:00.428477 end: 2.4 uboot-commands (duration 00:01:52) [common]
1178 03:02:00.430010 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1180 03:02:00.431106 end: 2 uboot-action (duration 00:01:52) [common]
1182 03:02:00.432782 Cleaning after the job
1183 03:02:00.433373 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/ramdisk
1184 03:02:00.434708 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/kernel
1185 03:02:00.483785 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/dtb
1186 03:02:00.484607 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/nfsrootfs
1187 03:02:00.643590 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951292/tftp-deploy-ogd8eilf/modules
1188 03:02:00.665276 start: 4.1 power-off (timeout 00:00:30) [common]
1189 03:02:00.665927 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1190 03:02:00.699589 >> OK - accepted request
1191 03:02:00.701658 Returned 0 in 0 seconds
1192 03:02:00.802372 end: 4.1 power-off (duration 00:00:00) [common]
1194 03:02:00.803305 start: 4.2 read-feedback (timeout 00:10:00) [common]
1195 03:02:00.803965 Listened to connection for namespace 'common' for up to 1s
1196 03:02:01.804383 Finalising connection for namespace 'common'
1197 03:02:01.805176 Disconnecting from shell: Finalise
1198 03:02:01.805733 =>
1199 03:02:01.906855 end: 4.2 read-feedback (duration 00:00:01) [common]
1200 03:02:01.907572 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/951292
1201 03:02:03.735225 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/951292
1202 03:02:03.735845 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.