Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:03:11.530623 lava-dispatcher, installed at version: 2024.01
2 05:03:11.531414 start: 0 validate
3 05:03:11.531895 Start time: 2024-11-07 05:03:11.531865+00:00 (UTC)
4 05:03:11.532517 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:03:11.533059 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 05:03:11.572115 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:03:11.572674 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 05:03:11.600202 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:03:11.600841 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:03:11.629978 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:03:11.630482 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 05:03:11.667638 validate duration: 0.14
14 05:03:11.668735 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:03:11.669104 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:03:11.669438 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:03:11.670018 Not decompressing ramdisk as can be used compressed.
18 05:03:11.670462 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 05:03:11.670711 saving as /var/lib/lava/dispatcher/tmp/951313/tftp-deploy-myho6boz/ramdisk/rootfs.cpio.gz
20 05:03:11.670968 total size: 47897469 (45 MB)
21 05:03:11.703295 progress 0 % (0 MB)
22 05:03:11.733939 progress 5 % (2 MB)
23 05:03:11.763345 progress 10 % (4 MB)
24 05:03:11.792476 progress 15 % (6 MB)
25 05:03:11.821765 progress 20 % (9 MB)
26 05:03:11.850665 progress 25 % (11 MB)
27 05:03:11.879531 progress 30 % (13 MB)
28 05:03:11.908549 progress 35 % (16 MB)
29 05:03:11.937255 progress 40 % (18 MB)
30 05:03:11.966116 progress 45 % (20 MB)
31 05:03:11.994875 progress 50 % (22 MB)
32 05:03:12.023907 progress 55 % (25 MB)
33 05:03:12.053220 progress 60 % (27 MB)
34 05:03:12.081836 progress 65 % (29 MB)
35 05:03:12.110723 progress 70 % (32 MB)
36 05:03:12.139404 progress 75 % (34 MB)
37 05:03:12.168170 progress 80 % (36 MB)
38 05:03:12.196942 progress 85 % (38 MB)
39 05:03:12.225926 progress 90 % (41 MB)
40 05:03:12.254442 progress 95 % (43 MB)
41 05:03:12.282098 progress 100 % (45 MB)
42 05:03:12.282835 45 MB downloaded in 0.61 s (74.66 MB/s)
43 05:03:12.283395 end: 1.1.1 http-download (duration 00:00:01) [common]
45 05:03:12.284325 end: 1.1 download-retry (duration 00:00:01) [common]
46 05:03:12.284630 start: 1.2 download-retry (timeout 00:09:59) [common]
47 05:03:12.284907 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 05:03:12.285390 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/kernel/Image
49 05:03:12.285663 saving as /var/lib/lava/dispatcher/tmp/951313/tftp-deploy-myho6boz/kernel/Image
50 05:03:12.285877 total size: 45713920 (43 MB)
51 05:03:12.286090 No compression specified
52 05:03:12.323451 progress 0 % (0 MB)
53 05:03:12.350432 progress 5 % (2 MB)
54 05:03:12.377227 progress 10 % (4 MB)
55 05:03:12.404047 progress 15 % (6 MB)
56 05:03:12.430854 progress 20 % (8 MB)
57 05:03:12.457293 progress 25 % (10 MB)
58 05:03:12.484003 progress 30 % (13 MB)
59 05:03:12.511068 progress 35 % (15 MB)
60 05:03:12.538656 progress 40 % (17 MB)
61 05:03:12.567495 progress 45 % (19 MB)
62 05:03:12.595201 progress 50 % (21 MB)
63 05:03:12.622378 progress 55 % (24 MB)
64 05:03:12.649436 progress 60 % (26 MB)
65 05:03:12.675783 progress 65 % (28 MB)
66 05:03:12.702873 progress 70 % (30 MB)
67 05:03:12.729698 progress 75 % (32 MB)
68 05:03:12.756461 progress 80 % (34 MB)
69 05:03:12.782867 progress 85 % (37 MB)
70 05:03:12.810031 progress 90 % (39 MB)
71 05:03:12.836865 progress 95 % (41 MB)
72 05:03:12.862851 progress 100 % (43 MB)
73 05:03:12.863373 43 MB downloaded in 0.58 s (75.49 MB/s)
74 05:03:12.863870 end: 1.2.1 http-download (duration 00:00:01) [common]
76 05:03:12.864762 end: 1.2 download-retry (duration 00:00:01) [common]
77 05:03:12.865048 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:03:12.865316 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:03:12.865778 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 05:03:12.866033 saving as /var/lib/lava/dispatcher/tmp/951313/tftp-deploy-myho6boz/dtb/meson-g12b-a311d-libretech-cc.dtb
81 05:03:12.866244 total size: 54703 (0 MB)
82 05:03:12.866456 No compression specified
83 05:03:12.903478 progress 59 % (0 MB)
84 05:03:12.904371 progress 100 % (0 MB)
85 05:03:12.904950 0 MB downloaded in 0.04 s (1.35 MB/s)
86 05:03:12.905417 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:03:12.906249 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:03:12.906518 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:03:12.906786 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:03:12.907254 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/modules.tar.xz
92 05:03:12.907536 saving as /var/lib/lava/dispatcher/tmp/951313/tftp-deploy-myho6boz/modules/modules.tar
93 05:03:12.907748 total size: 11607084 (11 MB)
94 05:03:12.907962 Using unxz to decompress xz
95 05:03:12.941522 progress 0 % (0 MB)
96 05:03:13.008850 progress 5 % (0 MB)
97 05:03:13.084965 progress 10 % (1 MB)
98 05:03:13.183903 progress 15 % (1 MB)
99 05:03:13.279443 progress 20 % (2 MB)
100 05:03:13.361113 progress 25 % (2 MB)
101 05:03:13.437197 progress 30 % (3 MB)
102 05:03:13.511435 progress 35 % (3 MB)
103 05:03:13.589299 progress 40 % (4 MB)
104 05:03:13.665887 progress 45 % (5 MB)
105 05:03:13.749810 progress 50 % (5 MB)
106 05:03:13.826703 progress 55 % (6 MB)
107 05:03:13.911817 progress 60 % (6 MB)
108 05:03:13.992464 progress 65 % (7 MB)
109 05:03:14.069263 progress 70 % (7 MB)
110 05:03:14.151246 progress 75 % (8 MB)
111 05:03:14.235315 progress 80 % (8 MB)
112 05:03:14.315605 progress 85 % (9 MB)
113 05:03:14.394715 progress 90 % (9 MB)
114 05:03:14.472977 progress 95 % (10 MB)
115 05:03:14.550666 progress 100 % (11 MB)
116 05:03:14.562855 11 MB downloaded in 1.66 s (6.69 MB/s)
117 05:03:14.563466 end: 1.4.1 http-download (duration 00:00:02) [common]
119 05:03:14.564695 end: 1.4 download-retry (duration 00:00:02) [common]
120 05:03:14.565250 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 05:03:14.565774 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 05:03:14.566272 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:03:14.566777 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 05:03:14.567784 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v
125 05:03:14.568664 makedir: /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin
126 05:03:14.569302 makedir: /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/tests
127 05:03:14.569912 makedir: /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/results
128 05:03:14.570519 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-add-keys
129 05:03:14.571462 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-add-sources
130 05:03:14.572442 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-background-process-start
131 05:03:14.573391 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-background-process-stop
132 05:03:14.574442 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-common-functions
133 05:03:14.575366 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-echo-ipv4
134 05:03:14.576309 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-install-packages
135 05:03:14.577213 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-installed-packages
136 05:03:14.578097 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-os-build
137 05:03:14.578977 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-probe-channel
138 05:03:14.579861 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-probe-ip
139 05:03:14.580798 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-target-ip
140 05:03:14.581704 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-target-mac
141 05:03:14.582597 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-target-storage
142 05:03:14.583500 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-test-case
143 05:03:14.584497 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-test-event
144 05:03:14.585535 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-test-feedback
145 05:03:14.586464 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-test-raise
146 05:03:14.587368 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-test-reference
147 05:03:14.588308 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-test-runner
148 05:03:14.589223 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-test-set
149 05:03:14.590139 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-test-shell
150 05:03:14.591051 Updating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-install-packages (oe)
151 05:03:14.592043 Updating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/bin/lava-installed-packages (oe)
152 05:03:14.592878 Creating /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/environment
153 05:03:14.593581 LAVA metadata
154 05:03:14.594056 - LAVA_JOB_ID=951313
155 05:03:14.594480 - LAVA_DISPATCHER_IP=192.168.6.2
156 05:03:14.595137 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 05:03:14.596969 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 05:03:14.597556 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 05:03:14.597966 skipped lava-vland-overlay
160 05:03:14.598453 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 05:03:14.598954 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 05:03:14.599377 skipped lava-multinode-overlay
163 05:03:14.599855 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 05:03:14.600390 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 05:03:14.600864 Loading test definitions
166 05:03:14.601404 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 05:03:14.601868 Using /lava-951313 at stage 0
168 05:03:14.604075 uuid=951313_1.5.2.4.1 testdef=None
169 05:03:14.604398 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 05:03:14.604669 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 05:03:14.606455 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 05:03:14.607260 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 05:03:14.609484 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 05:03:14.610323 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 05:03:14.612457 runner path: /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/0/tests/0_igt-gpu-panfrost test_uuid 951313_1.5.2.4.1
178 05:03:14.613079 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 05:03:14.613896 Creating lava-test-runner.conf files
181 05:03:14.614105 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/951313/lava-overlay-lh70fz8v/lava-951313/0 for stage 0
182 05:03:14.614455 - 0_igt-gpu-panfrost
183 05:03:14.614801 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 05:03:14.615081 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 05:03:14.638523 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 05:03:14.638932 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 05:03:14.639200 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 05:03:14.639467 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 05:03:14.639730 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 05:03:21.552260 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 05:03:21.553062 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 05:03:21.553583 extracting modules file /var/lib/lava/dispatcher/tmp/951313/tftp-deploy-myho6boz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/951313/extract-overlay-ramdisk-44e1sogz/ramdisk
193 05:03:22.988230 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 05:03:22.988712 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 05:03:22.988990 [common] Applying overlay /var/lib/lava/dispatcher/tmp/951313/compress-overlay-n1bojqyw/overlay-1.5.2.5.tar.gz to ramdisk
196 05:03:22.989204 [common] Applying overlay /var/lib/lava/dispatcher/tmp/951313/compress-overlay-n1bojqyw/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/951313/extract-overlay-ramdisk-44e1sogz/ramdisk
197 05:03:23.019614 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 05:03:23.020068 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 05:03:23.020352 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 05:03:23.020579 Converting downloaded kernel to a uImage
201 05:03:23.020883 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/951313/tftp-deploy-myho6boz/kernel/Image /var/lib/lava/dispatcher/tmp/951313/tftp-deploy-myho6boz/kernel/uImage
202 05:03:23.513994 output: Image Name:
203 05:03:23.514418 output: Created: Thu Nov 7 05:03:23 2024
204 05:03:23.514640 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 05:03:23.514852 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 05:03:23.515058 output: Load Address: 01080000
207 05:03:23.515263 output: Entry Point: 01080000
208 05:03:23.515465 output:
209 05:03:23.515803 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 05:03:23.516116 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 05:03:23.516404 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 05:03:23.516668 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 05:03:23.516933 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 05:03:23.517209 Building ramdisk /var/lib/lava/dispatcher/tmp/951313/extract-overlay-ramdisk-44e1sogz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/951313/extract-overlay-ramdisk-44e1sogz/ramdisk
215 05:03:30.164211 >> 502380 blocks
216 05:03:50.999007 Adding RAMdisk u-boot header.
217 05:03:50.999714 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/951313/extract-overlay-ramdisk-44e1sogz/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/951313/extract-overlay-ramdisk-44e1sogz/ramdisk.cpio.gz.uboot
218 05:03:51.651400 output: Image Name:
219 05:03:51.651822 output: Created: Thu Nov 7 05:03:51 2024
220 05:03:51.652114 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 05:03:51.652528 output: Data Size: 65714033 Bytes = 64173.86 KiB = 62.67 MiB
222 05:03:51.652926 output: Load Address: 00000000
223 05:03:51.653319 output: Entry Point: 00000000
224 05:03:51.653707 output:
225 05:03:51.654743 rename /var/lib/lava/dispatcher/tmp/951313/extract-overlay-ramdisk-44e1sogz/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/951313/tftp-deploy-myho6boz/ramdisk/ramdisk.cpio.gz.uboot
226 05:03:51.655452 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 05:03:51.656013 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 05:03:51.656546 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 05:03:51.656993 No LXC device requested
230 05:03:51.657487 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 05:03:51.657987 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 05:03:51.658472 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 05:03:51.658886 Checking files for TFTP limit of 4294967296 bytes.
234 05:03:51.661544 end: 1 tftp-deploy (duration 00:00:40) [common]
235 05:03:51.662111 start: 2 uboot-action (timeout 00:05:00) [common]
236 05:03:51.662628 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 05:03:51.663120 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 05:03:51.663614 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 05:03:51.664160 Using kernel file from prepare-kernel: 951313/tftp-deploy-myho6boz/kernel/uImage
240 05:03:51.664764 substitutions:
241 05:03:51.665167 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 05:03:51.665564 - {DTB_ADDR}: 0x01070000
243 05:03:51.665960 - {DTB}: 951313/tftp-deploy-myho6boz/dtb/meson-g12b-a311d-libretech-cc.dtb
244 05:03:51.666354 - {INITRD}: 951313/tftp-deploy-myho6boz/ramdisk/ramdisk.cpio.gz.uboot
245 05:03:51.666749 - {KERNEL_ADDR}: 0x01080000
246 05:03:51.667137 - {KERNEL}: 951313/tftp-deploy-myho6boz/kernel/uImage
247 05:03:51.667527 - {LAVA_MAC}: None
248 05:03:51.667954 - {PRESEED_CONFIG}: None
249 05:03:51.668379 - {PRESEED_LOCAL}: None
250 05:03:51.668770 - {RAMDISK_ADDR}: 0x08000000
251 05:03:51.669156 - {RAMDISK}: 951313/tftp-deploy-myho6boz/ramdisk/ramdisk.cpio.gz.uboot
252 05:03:51.669547 - {ROOT_PART}: None
253 05:03:51.669933 - {ROOT}: None
254 05:03:51.670319 - {SERVER_IP}: 192.168.6.2
255 05:03:51.670708 - {TEE_ADDR}: 0x83000000
256 05:03:51.671093 - {TEE}: None
257 05:03:51.671478 Parsed boot commands:
258 05:03:51.671852 - setenv autoload no
259 05:03:51.672256 - setenv initrd_high 0xffffffff
260 05:03:51.672642 - setenv fdt_high 0xffffffff
261 05:03:51.673023 - dhcp
262 05:03:51.673404 - setenv serverip 192.168.6.2
263 05:03:51.673785 - tftpboot 0x01080000 951313/tftp-deploy-myho6boz/kernel/uImage
264 05:03:51.674167 - tftpboot 0x08000000 951313/tftp-deploy-myho6boz/ramdisk/ramdisk.cpio.gz.uboot
265 05:03:51.674552 - tftpboot 0x01070000 951313/tftp-deploy-myho6boz/dtb/meson-g12b-a311d-libretech-cc.dtb
266 05:03:51.674935 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 05:03:51.675322 - bootm 0x01080000 0x08000000 0x01070000
268 05:03:51.675806 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 05:03:51.677382 start: 2.3 connect-device (timeout 00:05:00) [common]
271 05:03:51.677821 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 05:03:51.692441 Setting prompt string to ['lava-test: # ']
273 05:03:51.693922 end: 2.3 connect-device (duration 00:00:00) [common]
274 05:03:51.694510 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 05:03:51.695049 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 05:03:51.695559 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 05:03:51.696718 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 05:03:51.732142 >> OK - accepted request
279 05:03:51.734277 Returned 0 in 0 seconds
280 05:03:51.835354 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 05:03:51.836988 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 05:03:51.837546 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 05:03:51.838038 Setting prompt string to ['Hit any key to stop autoboot']
285 05:03:51.838497 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 05:03:51.840064 Trying 192.168.56.21...
287 05:03:51.840545 Connected to conserv1.
288 05:03:51.840960 Escape character is '^]'.
289 05:03:51.841377
290 05:03:51.841794 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 05:03:51.842207
292 05:04:02.976297 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 05:04:02.976716 bl2_stage_init 0x01
294 05:04:02.976954 bl2_stage_init 0x81
295 05:04:02.981837 hw id: 0x0000 - pwm id 0x01
296 05:04:02.982139 bl2_stage_init 0xc1
297 05:04:02.982351 bl2_stage_init 0x02
298 05:04:02.982553
299 05:04:02.987370 L0:00000000
300 05:04:02.987628 L1:20000703
301 05:04:02.987834 L2:00008067
302 05:04:02.988070 L3:14000000
303 05:04:02.993038 B2:00402000
304 05:04:02.993298 B1:e0f83180
305 05:04:02.993503
306 05:04:02.993704 TE: 58124
307 05:04:02.993903
308 05:04:02.998801 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 05:04:02.999071
310 05:04:02.999281 Board ID = 1
311 05:04:03.004206 Set A53 clk to 24M
312 05:04:03.004448 Set A73 clk to 24M
313 05:04:03.004651 Set clk81 to 24M
314 05:04:03.009794 A53 clk: 1200 MHz
315 05:04:03.010043 A73 clk: 1200 MHz
316 05:04:03.010249 CLK81: 166.6M
317 05:04:03.010448 smccc: 00012a92
318 05:04:03.015483 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 05:04:03.021128 board id: 1
320 05:04:03.026983 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 05:04:03.037472 fw parse done
322 05:04:03.043482 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 05:04:03.086028 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 05:04:03.096898 PIEI prepare done
325 05:04:03.097138 fastboot data load
326 05:04:03.097340 fastboot data verify
327 05:04:03.102726 verify result: 266
328 05:04:03.108327 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 05:04:03.108571 LPDDR4 probe
330 05:04:03.108772 ddr clk to 1584MHz
331 05:04:03.116165 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 05:04:03.153520
333 05:04:03.153801 dmc_version 0001
334 05:04:03.160226 Check phy result
335 05:04:03.165957 INFO : End of CA training
336 05:04:03.166185 INFO : End of initialization
337 05:04:03.171726 INFO : Training has run successfully!
338 05:04:03.171961 Check phy result
339 05:04:03.177206 INFO : End of initialization
340 05:04:03.177442 INFO : End of read enable training
341 05:04:03.182836 INFO : End of fine write leveling
342 05:04:03.188463 INFO : End of Write leveling coarse delay
343 05:04:03.188700 INFO : Training has run successfully!
344 05:04:03.188903 Check phy result
345 05:04:03.193925 INFO : End of initialization
346 05:04:03.194159 INFO : End of read dq deskew training
347 05:04:03.199720 INFO : End of MPR read delay center optimization
348 05:04:03.205223 INFO : End of write delay center optimization
349 05:04:03.210804 INFO : End of read delay center optimization
350 05:04:03.211043 INFO : End of max read latency training
351 05:04:03.216403 INFO : Training has run successfully!
352 05:04:03.216633 1D training succeed
353 05:04:03.225556 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 05:04:03.273162 Check phy result
355 05:04:03.273465 INFO : End of initialization
356 05:04:03.294927 INFO : End of 2D read delay Voltage center optimization
357 05:04:03.315188 INFO : End of 2D read delay Voltage center optimization
358 05:04:03.367364 INFO : End of 2D write delay Voltage center optimization
359 05:04:03.416777 INFO : End of 2D write delay Voltage center optimization
360 05:04:03.422290 INFO : Training has run successfully!
361 05:04:03.422548
362 05:04:03.422760 channel==0
363 05:04:03.427808 RxClkDly_Margin_A0==88 ps 9
364 05:04:03.428085 TxDqDly_Margin_A0==98 ps 10
365 05:04:03.431095 RxClkDly_Margin_A1==88 ps 9
366 05:04:03.431336 TxDqDly_Margin_A1==88 ps 9
367 05:04:03.436813 TrainedVREFDQ_A0==74
368 05:04:03.437074 TrainedVREFDQ_A1==74
369 05:04:03.437286 VrefDac_Margin_A0==25
370 05:04:03.442265 DeviceVref_Margin_A0==40
371 05:04:03.442508 VrefDac_Margin_A1==25
372 05:04:03.447960 DeviceVref_Margin_A1==40
373 05:04:03.448590
374 05:04:03.449077
375 05:04:03.449523 channel==1
376 05:04:03.449960 RxClkDly_Margin_A0==98 ps 10
377 05:04:03.453712 TxDqDly_Margin_A0==98 ps 10
378 05:04:03.454196 RxClkDly_Margin_A1==98 ps 10
379 05:04:03.459169 TxDqDly_Margin_A1==88 ps 9
380 05:04:03.459635 TrainedVREFDQ_A0==77
381 05:04:03.460105 TrainedVREFDQ_A1==77
382 05:04:03.464775 VrefDac_Margin_A0==22
383 05:04:03.465241 DeviceVref_Margin_A0==37
384 05:04:03.470294 VrefDac_Margin_A1==22
385 05:04:03.470749 DeviceVref_Margin_A1==37
386 05:04:03.471186
387 05:04:03.475928 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 05:04:03.476436
389 05:04:03.503935 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 05:04:03.509560 2D training succeed
391 05:04:03.515144 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 05:04:03.515645 auto size-- 65535DDR cs0 size: 2048MB
393 05:04:03.520842 DDR cs1 size: 2048MB
394 05:04:03.521339 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 05:04:03.526331 cs0 DataBus test pass
396 05:04:03.526819 cs1 DataBus test pass
397 05:04:03.527258 cs0 AddrBus test pass
398 05:04:03.531933 cs1 AddrBus test pass
399 05:04:03.532464
400 05:04:03.532904 100bdlr_step_size ps== 420
401 05:04:03.533347 result report
402 05:04:03.537580 boot times 0Enable ddr reg access
403 05:04:03.545198 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 05:04:03.558716 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 05:04:04.132309 0.0;M3 CHK:0;cm4_sp_mode 0
406 05:04:04.132990 MVN_1=0x00000000
407 05:04:04.137789 MVN_2=0x00000000
408 05:04:04.143423 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 05:04:04.143929 OPS=0x10
410 05:04:04.144457 ring efuse init
411 05:04:04.144922 chipver efuse init
412 05:04:04.149028 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 05:04:04.154622 [0.018961 Inits done]
414 05:04:04.155155 secure task start!
415 05:04:04.155615 high task start!
416 05:04:04.159207 low task start!
417 05:04:04.159697 run into bl31
418 05:04:04.165861 NOTICE: BL31: v1.3(release):4fc40b1
419 05:04:04.173659 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 05:04:04.174155 NOTICE: BL31: G12A normal boot!
421 05:04:04.199061 NOTICE: BL31: BL33 decompress pass
422 05:04:04.204849 ERROR: Error initializing runtime service opteed_fast
423 05:04:05.437815
424 05:04:05.438510
425 05:04:05.446073 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 05:04:05.446639
427 05:04:05.447116 Model: Libre Computer AML-A311D-CC Alta
428 05:04:05.654638 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 05:04:05.677852 DRAM: 2 GiB (effective 3.8 GiB)
430 05:04:05.820822 Core: 408 devices, 31 uclasses, devicetree: separate
431 05:04:05.826684 WDT: Not starting watchdog@f0d0
432 05:04:05.859059 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 05:04:05.871394 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 05:04:05.876371 ** Bad device specification mmc 0 **
435 05:04:05.886874 Card did not respond to voltage select! : -110
436 05:04:05.894463 ** Bad device specification mmc 0 **
437 05:04:05.894947 Couldn't find partition mmc 0
438 05:04:05.902857 Card did not respond to voltage select! : -110
439 05:04:05.908286 ** Bad device specification mmc 0 **
440 05:04:05.908769 Couldn't find partition mmc 0
441 05:04:05.913327 Error: could not access storage.
442 05:04:07.176587 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 05:04:07.177237 bl2_stage_init 0x01
444 05:04:07.177723 bl2_stage_init 0x81
445 05:04:07.182153 hw id: 0x0000 - pwm id 0x01
446 05:04:07.182645 bl2_stage_init 0xc1
447 05:04:07.183101 bl2_stage_init 0x02
448 05:04:07.183549
449 05:04:07.187723 L0:00000000
450 05:04:07.188239 L1:20000703
451 05:04:07.188692 L2:00008067
452 05:04:07.189135 L3:14000000
453 05:04:07.190617 B2:00402000
454 05:04:07.191095 B1:e0f83180
455 05:04:07.191540
456 05:04:07.192017 TE: 58124
457 05:04:07.192489
458 05:04:07.201808 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 05:04:07.202305
460 05:04:07.202760 Board ID = 1
461 05:04:07.203203 Set A53 clk to 24M
462 05:04:07.203644 Set A73 clk to 24M
463 05:04:07.207402 Set clk81 to 24M
464 05:04:07.207883 A53 clk: 1200 MHz
465 05:04:07.208368 A73 clk: 1200 MHz
466 05:04:07.213165 CLK81: 166.6M
467 05:04:07.213642 smccc: 00012a92
468 05:04:07.218605 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 05:04:07.219082 board id: 1
470 05:04:07.227236 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 05:04:07.237909 fw parse done
472 05:04:07.243842 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 05:04:07.286488 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 05:04:07.297346 PIEI prepare done
475 05:04:07.297834 fastboot data load
476 05:04:07.298291 fastboot data verify
477 05:04:07.303091 verify result: 266
478 05:04:07.308616 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 05:04:07.309092 LPDDR4 probe
480 05:04:07.309538 ddr clk to 1584MHz
481 05:04:07.316586 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 05:04:07.353852
483 05:04:07.354339 dmc_version 0001
484 05:04:07.360538 Check phy result
485 05:04:07.366398 INFO : End of CA training
486 05:04:07.366886 INFO : End of initialization
487 05:04:07.372029 INFO : Training has run successfully!
488 05:04:07.372516 Check phy result
489 05:04:07.377586 INFO : End of initialization
490 05:04:07.378065 INFO : End of read enable training
491 05:04:07.383313 INFO : End of fine write leveling
492 05:04:07.388802 INFO : End of Write leveling coarse delay
493 05:04:07.389284 INFO : Training has run successfully!
494 05:04:07.389731 Check phy result
495 05:04:07.394402 INFO : End of initialization
496 05:04:07.394878 INFO : End of read dq deskew training
497 05:04:07.400033 INFO : End of MPR read delay center optimization
498 05:04:07.405619 INFO : End of write delay center optimization
499 05:04:07.411260 INFO : End of read delay center optimization
500 05:04:07.411760 INFO : End of max read latency training
501 05:04:07.416853 INFO : Training has run successfully!
502 05:04:07.417348 1D training succeed
503 05:04:07.426056 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 05:04:07.473605 Check phy result
505 05:04:07.474140 INFO : End of initialization
506 05:04:07.496248 INFO : End of 2D read delay Voltage center optimization
507 05:04:07.516431 INFO : End of 2D read delay Voltage center optimization
508 05:04:07.568557 INFO : End of 2D write delay Voltage center optimization
509 05:04:07.617900 INFO : End of 2D write delay Voltage center optimization
510 05:04:07.623390 INFO : Training has run successfully!
511 05:04:07.623879
512 05:04:07.624403 channel==0
513 05:04:07.628982 RxClkDly_Margin_A0==88 ps 9
514 05:04:07.629462 TxDqDly_Margin_A0==108 ps 11
515 05:04:07.634572 RxClkDly_Margin_A1==88 ps 9
516 05:04:07.635044 TxDqDly_Margin_A1==88 ps 9
517 05:04:07.635498 TrainedVREFDQ_A0==74
518 05:04:07.640335 TrainedVREFDQ_A1==74
519 05:04:07.640833 VrefDac_Margin_A0==25
520 05:04:07.641283 DeviceVref_Margin_A0==40
521 05:04:07.645762 VrefDac_Margin_A1==24
522 05:04:07.646236 DeviceVref_Margin_A1==40
523 05:04:07.646681
524 05:04:07.647123
525 05:04:07.651372 channel==1
526 05:04:07.651848 RxClkDly_Margin_A0==98 ps 10
527 05:04:07.652340 TxDqDly_Margin_A0==98 ps 10
528 05:04:07.656967 RxClkDly_Margin_A1==98 ps 10
529 05:04:07.657443 TxDqDly_Margin_A1==88 ps 9
530 05:04:07.662567 TrainedVREFDQ_A0==77
531 05:04:07.663049 TrainedVREFDQ_A1==77
532 05:04:07.663498 VrefDac_Margin_A0==22
533 05:04:07.668309 DeviceVref_Margin_A0==37
534 05:04:07.668785 VrefDac_Margin_A1==22
535 05:04:07.673763 DeviceVref_Margin_A1==37
536 05:04:07.674233
537 05:04:07.674684 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 05:04:07.679364
539 05:04:07.707380 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000018 00000017 00000018 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
540 05:04:07.707901 2D training succeed
541 05:04:07.712946 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 05:04:07.718560 auto size-- 65535DDR cs0 size: 2048MB
543 05:04:07.719044 DDR cs1 size: 2048MB
544 05:04:07.724187 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 05:04:07.724668 cs0 DataBus test pass
546 05:04:07.729746 cs1 DataBus test pass
547 05:04:07.730227 cs0 AddrBus test pass
548 05:04:07.730677 cs1 AddrBus test pass
549 05:04:07.731125
550 05:04:07.735403 100bdlr_step_size ps== 420
551 05:04:07.735893 result report
552 05:04:07.740976 boot times 0Enable ddr reg access
553 05:04:07.746465 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 05:04:07.759898 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 05:04:08.333662 0.0;M3 CHK:0;cm4_sp_mode 0
556 05:04:08.334337 MVN_1=0x00000000
557 05:04:08.339032 MVN_2=0x00000000
558 05:04:08.344812 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 05:04:08.345350 OPS=0x10
560 05:04:08.345815 ring efuse init
561 05:04:08.346302 chipver efuse init
562 05:04:08.350428 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 05:04:08.356063 [0.018961 Inits done]
564 05:04:08.356560 secure task start!
565 05:04:08.356993 high task start!
566 05:04:08.360560 low task start!
567 05:04:08.361030 run into bl31
568 05:04:08.367368 NOTICE: BL31: v1.3(release):4fc40b1
569 05:04:08.375066 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 05:04:08.375542 NOTICE: BL31: G12A normal boot!
571 05:04:08.400519 NOTICE: BL31: BL33 decompress pass
572 05:04:08.406118 ERROR: Error initializing runtime service opteed_fast
573 05:04:09.639428
574 05:04:09.640152
575 05:04:09.647581 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 05:04:09.648112
577 05:04:09.648578 Model: Libre Computer AML-A311D-CC Alta
578 05:04:09.856090 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 05:04:09.879481 DRAM: 2 GiB (effective 3.8 GiB)
580 05:04:10.022395 Core: 408 devices, 31 uclasses, devicetree: separate
581 05:04:10.028325 WDT: Not starting watchdog@f0d0
582 05:04:10.060504 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 05:04:10.072891 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 05:04:10.077970 ** Bad device specification mmc 0 **
585 05:04:10.088262 Card did not respond to voltage select! : -110
586 05:04:10.096022 ** Bad device specification mmc 0 **
587 05:04:10.096515 Couldn't find partition mmc 0
588 05:04:10.104275 Card did not respond to voltage select! : -110
589 05:04:10.109798 ** Bad device specification mmc 0 **
590 05:04:10.110285 Couldn't find partition mmc 0
591 05:04:10.114890 Error: could not access storage.
592 05:04:10.457318 Net: eth0: ethernet@ff3f0000
593 05:04:10.457941 starting USB...
594 05:04:10.709167 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 05:04:10.709766 Starting the controller
596 05:04:10.716212 USB XHCI 1.10
597 05:04:12.425808 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 05:04:12.426510 bl2_stage_init 0x01
599 05:04:12.426992 bl2_stage_init 0x81
600 05:04:12.431072 hw id: 0x0000 - pwm id 0x01
601 05:04:12.431568 bl2_stage_init 0xc1
602 05:04:12.432076 bl2_stage_init 0x02
603 05:04:12.432530
604 05:04:12.436850 L0:00000000
605 05:04:12.437334 L1:20000703
606 05:04:12.437787 L2:00008067
607 05:04:12.438232 L3:14000000
608 05:04:12.442273 B2:00402000
609 05:04:12.442745 B1:e0f83180
610 05:04:12.443224
611 05:04:12.443699 TE: 58159
612 05:04:12.444205
613 05:04:12.448071 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 05:04:12.448585
615 05:04:12.449037 Board ID = 1
616 05:04:12.453505 Set A53 clk to 24M
617 05:04:12.453980 Set A73 clk to 24M
618 05:04:12.454426 Set clk81 to 24M
619 05:04:12.459071 A53 clk: 1200 MHz
620 05:04:12.459550 A73 clk: 1200 MHz
621 05:04:12.460026 CLK81: 166.6M
622 05:04:12.460472 smccc: 00012ab5
623 05:04:12.464756 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 05:04:12.470288 board id: 1
625 05:04:12.476214 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 05:04:12.486820 fw parse done
627 05:04:12.492846 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 05:04:12.535443 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 05:04:12.545864 PIEI prepare done
630 05:04:12.549378 fastboot data load
631 05:04:12.549861 fastboot data verify
632 05:04:12.550317 verify result: 266
633 05:04:12.555026 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 05:04:12.555525 LPDDR4 probe
635 05:04:12.560482 ddr clk to 1584MHz
636 05:04:12.565778 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 05:04:12.602767
638 05:04:12.603257 dmc_version 0001
639 05:04:12.609449 Check phy result
640 05:04:12.615281 INFO : End of CA training
641 05:04:12.615806 INFO : End of initialization
642 05:04:12.621104 INFO : Training has run successfully!
643 05:04:12.621591 Check phy result
644 05:04:12.626496 INFO : End of initialization
645 05:04:12.626972 INFO : End of read enable training
646 05:04:12.629788 INFO : End of fine write leveling
647 05:04:12.635310 INFO : End of Write leveling coarse delay
648 05:04:12.641069 INFO : Training has run successfully!
649 05:04:12.641550 Check phy result
650 05:04:12.641996 INFO : End of initialization
651 05:04:12.646507 INFO : End of read dq deskew training
652 05:04:12.652187 INFO : End of MPR read delay center optimization
653 05:04:12.652667 INFO : End of write delay center optimization
654 05:04:12.657789 INFO : End of read delay center optimization
655 05:04:12.663360 INFO : End of max read latency training
656 05:04:12.663833 INFO : Training has run successfully!
657 05:04:12.669093 1D training succeed
658 05:04:12.674901 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 05:04:12.721505 Check phy result
660 05:04:12.721984 INFO : End of initialization
661 05:04:12.744214 INFO : End of 2D read delay Voltage center optimization
662 05:04:12.764224 INFO : End of 2D read delay Voltage center optimization
663 05:04:12.816289 INFO : End of 2D write delay Voltage center optimization
664 05:04:12.865438 INFO : End of 2D write delay Voltage center optimization
665 05:04:12.870979 INFO : Training has run successfully!
666 05:04:12.871444
667 05:04:12.871893 channel==0
668 05:04:12.876598 RxClkDly_Margin_A0==88 ps 9
669 05:04:12.877072 TxDqDly_Margin_A0==98 ps 10
670 05:04:12.879864 RxClkDly_Margin_A1==88 ps 9
671 05:04:12.880364 TxDqDly_Margin_A1==88 ps 9
672 05:04:12.885507 TrainedVREFDQ_A0==74
673 05:04:12.885991 TrainedVREFDQ_A1==74
674 05:04:12.886443 VrefDac_Margin_A0==25
675 05:04:12.891218 DeviceVref_Margin_A0==40
676 05:04:12.891691 VrefDac_Margin_A1==25
677 05:04:12.896722 DeviceVref_Margin_A1==40
678 05:04:12.897206
679 05:04:12.897656
680 05:04:12.898097 channel==1
681 05:04:12.898535 RxClkDly_Margin_A0==98 ps 10
682 05:04:12.902335 TxDqDly_Margin_A0==98 ps 10
683 05:04:12.902808 RxClkDly_Margin_A1==98 ps 10
684 05:04:12.907897 TxDqDly_Margin_A1==88 ps 9
685 05:04:12.908408 TrainedVREFDQ_A0==77
686 05:04:12.908858 TrainedVREFDQ_A1==77
687 05:04:12.913509 VrefDac_Margin_A0==22
688 05:04:12.913983 DeviceVref_Margin_A0==37
689 05:04:12.919200 VrefDac_Margin_A1==22
690 05:04:12.919675 DeviceVref_Margin_A1==37
691 05:04:12.920149
692 05:04:12.924723 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 05:04:12.925196
694 05:04:12.952688 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 05:04:12.958410 2D training succeed
696 05:04:12.963777 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 05:04:12.964283 auto size-- 65535DDR cs0 size: 2048MB
698 05:04:12.969360 DDR cs1 size: 2048MB
699 05:04:12.969829 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 05:04:12.975042 cs0 DataBus test pass
701 05:04:12.975517 cs1 DataBus test pass
702 05:04:12.975959 cs0 AddrBus test pass
703 05:04:12.980566 cs1 AddrBus test pass
704 05:04:12.981043
705 05:04:12.981489 100bdlr_step_size ps== 420
706 05:04:12.981936 result report
707 05:04:12.986159 boot times 0Enable ddr reg access
708 05:04:12.993837 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 05:04:13.007239 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 05:04:13.579441 0.0;M3 CHK:0;cm4_sp_mode 0
711 05:04:13.580172 MVN_1=0x00000000
712 05:04:13.584847 MVN_2=0x00000000
713 05:04:13.590607 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 05:04:13.591152 OPS=0x10
715 05:04:13.591595 ring efuse init
716 05:04:13.592064 chipver efuse init
717 05:04:13.596170 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 05:04:13.601734 [0.018960 Inits done]
719 05:04:13.602198 secure task start!
720 05:04:13.602627 high task start!
721 05:04:13.606278 low task start!
722 05:04:13.606740 run into bl31
723 05:04:13.613081 NOTICE: BL31: v1.3(release):4fc40b1
724 05:04:13.620806 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 05:04:13.621308 NOTICE: BL31: G12A normal boot!
726 05:04:13.646153 NOTICE: BL31: BL33 decompress pass
727 05:04:13.651824 ERROR: Error initializing runtime service opteed_fast
728 05:04:14.884912
729 05:04:14.885574
730 05:04:14.893156 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 05:04:14.893657
732 05:04:14.894113 Model: Libre Computer AML-A311D-CC Alta
733 05:04:15.101688 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 05:04:15.124945 DRAM: 2 GiB (effective 3.8 GiB)
735 05:04:15.267921 Core: 408 devices, 31 uclasses, devicetree: separate
736 05:04:15.273802 WDT: Not starting watchdog@f0d0
737 05:04:15.306062 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 05:04:15.318533 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 05:04:15.323504 ** Bad device specification mmc 0 **
740 05:04:15.333826 Card did not respond to voltage select! : -110
741 05:04:15.341466 ** Bad device specification mmc 0 **
742 05:04:15.341948 Couldn't find partition mmc 0
743 05:04:15.349815 Card did not respond to voltage select! : -110
744 05:04:15.355352 ** Bad device specification mmc 0 **
745 05:04:15.355829 Couldn't find partition mmc 0
746 05:04:15.360442 Error: could not access storage.
747 05:04:15.702876 Net: eth0: ethernet@ff3f0000
748 05:04:15.703523 starting USB...
749 05:04:15.954785 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 05:04:15.955387 Starting the controller
751 05:04:15.961642 USB XHCI 1.10
752 05:04:18.126606 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 05:04:18.127269 bl2_stage_init 0x01
754 05:04:18.127747 bl2_stage_init 0x81
755 05:04:18.132179 hw id: 0x0000 - pwm id 0x01
756 05:04:18.132675 bl2_stage_init 0xc1
757 05:04:18.133131 bl2_stage_init 0x02
758 05:04:18.133579
759 05:04:18.137709 L0:00000000
760 05:04:18.138188 L1:20000703
761 05:04:18.138640 L2:00008067
762 05:04:18.139079 L3:14000000
763 05:04:18.143236 B2:00402000
764 05:04:18.143714 B1:e0f83180
765 05:04:18.144199
766 05:04:18.144648 TE: 58124
767 05:04:18.145094
768 05:04:18.148773 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 05:04:18.149260
770 05:04:18.149711 Board ID = 1
771 05:04:18.154435 Set A53 clk to 24M
772 05:04:18.154912 Set A73 clk to 24M
773 05:04:18.155361 Set clk81 to 24M
774 05:04:18.160058 A53 clk: 1200 MHz
775 05:04:18.160536 A73 clk: 1200 MHz
776 05:04:18.160981 CLK81: 166.6M
777 05:04:18.161421 smccc: 00012a92
778 05:04:18.165629 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 05:04:18.171220 board id: 1
780 05:04:18.177151 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 05:04:18.187773 fw parse done
782 05:04:18.193774 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 05:04:18.236433 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 05:04:18.247176 PIEI prepare done
785 05:04:18.247647 fastboot data load
786 05:04:18.248136 fastboot data verify
787 05:04:18.252869 verify result: 266
788 05:04:18.258438 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 05:04:18.258911 LPDDR4 probe
790 05:04:18.259350 ddr clk to 1584MHz
791 05:04:18.266441 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 05:04:18.303702
793 05:04:18.304211 dmc_version 0001
794 05:04:18.310376 Check phy result
795 05:04:18.316220 INFO : End of CA training
796 05:04:18.316685 INFO : End of initialization
797 05:04:18.321853 INFO : Training has run successfully!
798 05:04:18.322324 Check phy result
799 05:04:18.327441 INFO : End of initialization
800 05:04:18.327908 INFO : End of read enable training
801 05:04:18.330834 INFO : End of fine write leveling
802 05:04:18.336342 INFO : End of Write leveling coarse delay
803 05:04:18.341967 INFO : Training has run successfully!
804 05:04:18.342432 Check phy result
805 05:04:18.342874 INFO : End of initialization
806 05:04:18.347601 INFO : End of read dq deskew training
807 05:04:18.353157 INFO : End of MPR read delay center optimization
808 05:04:18.353630 INFO : End of write delay center optimization
809 05:04:18.358820 INFO : End of read delay center optimization
810 05:04:18.364332 INFO : End of max read latency training
811 05:04:18.364798 INFO : Training has run successfully!
812 05:04:18.369938 1D training succeed
813 05:04:18.376074 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 05:04:18.423671 Check phy result
815 05:04:18.424306 INFO : End of initialization
816 05:04:18.446061 INFO : End of 2D read delay Voltage center optimization
817 05:04:18.465999 INFO : End of 2D read delay Voltage center optimization
818 05:04:18.518008 INFO : End of 2D write delay Voltage center optimization
819 05:04:18.567196 INFO : End of 2D write delay Voltage center optimization
820 05:04:18.572713 INFO : Training has run successfully!
821 05:04:18.573209
822 05:04:18.573664 channel==0
823 05:04:18.580314 RxClkDly_Margin_A0==88 ps 9
824 05:04:18.580790 TxDqDly_Margin_A0==98 ps 10
825 05:04:18.583956 RxClkDly_Margin_A1==98 ps 10
826 05:04:18.584498 TxDqDly_Margin_A1==88 ps 9
827 05:04:18.584935 TrainedVREFDQ_A0==74
828 05:04:18.589683 TrainedVREFDQ_A1==74
829 05:04:18.590202 VrefDac_Margin_A0==25
830 05:04:18.590633 DeviceVref_Margin_A0==40
831 05:04:18.595082 VrefDac_Margin_A1==25
832 05:04:18.595545 DeviceVref_Margin_A1==40
833 05:04:18.595969
834 05:04:18.596431
835 05:04:18.600435 channel==1
836 05:04:18.600893 RxClkDly_Margin_A0==98 ps 10
837 05:04:18.601319 TxDqDly_Margin_A0==98 ps 10
838 05:04:18.605923 RxClkDly_Margin_A1==98 ps 10
839 05:04:18.606378 TxDqDly_Margin_A1==108 ps 11
840 05:04:18.611557 TrainedVREFDQ_A0==77
841 05:04:18.612054 TrainedVREFDQ_A1==77
842 05:04:18.612498 VrefDac_Margin_A0==22
843 05:04:18.617127 DeviceVref_Margin_A0==37
844 05:04:18.617589 VrefDac_Margin_A1==22
845 05:04:18.620665 DeviceVref_Margin_A1==37
846 05:04:18.621115
847 05:04:18.626275 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 05:04:18.626771
849 05:04:18.654202 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
850 05:04:18.659783 2D training succeed
851 05:04:18.665254 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 05:04:18.665717 auto size-- 65535DDR cs0 size: 2048MB
853 05:04:18.670867 DDR cs1 size: 2048MB
854 05:04:18.671322 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 05:04:18.676471 cs0 DataBus test pass
856 05:04:18.676927 cs1 DataBus test pass
857 05:04:18.677352 cs0 AddrBus test pass
858 05:04:18.682065 cs1 AddrBus test pass
859 05:04:18.682516
860 05:04:18.682941 100bdlr_step_size ps== 432
861 05:04:18.687662 result report
862 05:04:18.688135 boot times 0Enable ddr reg access
863 05:04:18.695900 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 05:04:18.709281 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 05:04:19.281507 0.0;M3 CHK:0;cm4_sp_mode 0
866 05:04:19.282161 MVN_1=0x00000000
867 05:04:19.286922 MVN_2=0x00000000
868 05:04:19.292662 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 05:04:19.293149 OPS=0x10
870 05:04:19.293603 ring efuse init
871 05:04:19.294044 chipver efuse init
872 05:04:19.298155 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 05:04:19.303907 [0.018961 Inits done]
874 05:04:19.304431 secure task start!
875 05:04:19.304877 high task start!
876 05:04:19.308346 low task start!
877 05:04:19.308817 run into bl31
878 05:04:19.314982 NOTICE: BL31: v1.3(release):4fc40b1
879 05:04:19.322786 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 05:04:19.323272 NOTICE: BL31: G12A normal boot!
881 05:04:19.348177 NOTICE: BL31: BL33 decompress pass
882 05:04:19.353815 ERROR: Error initializing runtime service opteed_fast
883 05:04:20.586931
884 05:04:20.587610
885 05:04:20.595208 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 05:04:20.595702
887 05:04:20.596196 Model: Libre Computer AML-A311D-CC Alta
888 05:04:20.803621 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 05:04:20.826966 DRAM: 2 GiB (effective 3.8 GiB)
890 05:04:20.970020 Core: 408 devices, 31 uclasses, devicetree: separate
891 05:04:20.975775 WDT: Not starting watchdog@f0d0
892 05:04:21.007997 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 05:04:21.020550 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 05:04:21.024585 ** Bad device specification mmc 0 **
895 05:04:21.035818 Card did not respond to voltage select! : -110
896 05:04:21.043502 ** Bad device specification mmc 0 **
897 05:04:21.044017 Couldn't find partition mmc 0
898 05:04:21.051757 Card did not respond to voltage select! : -110
899 05:04:21.057320 ** Bad device specification mmc 0 **
900 05:04:21.057805 Couldn't find partition mmc 0
901 05:04:21.062386 Error: could not access storage.
902 05:04:21.405033 Net: eth0: ethernet@ff3f0000
903 05:04:21.405633 starting USB...
904 05:04:21.656854 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 05:04:21.657471 Starting the controller
906 05:04:21.663660 USB XHCI 1.10
907 05:04:23.525568 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 05:04:23.526226 bl2_stage_init 0x01
909 05:04:23.526697 bl2_stage_init 0x81
910 05:04:23.531025 hw id: 0x0000 - pwm id 0x01
911 05:04:23.531520 bl2_stage_init 0xc1
912 05:04:23.531975 bl2_stage_init 0x02
913 05:04:23.532489
914 05:04:23.536623 L0:00000000
915 05:04:23.537111 L1:20000703
916 05:04:23.537555 L2:00008067
917 05:04:23.537994 L3:14000000
918 05:04:23.539505 B2:00402000
919 05:04:23.540010 B1:e0f83180
920 05:04:23.540473
921 05:04:23.540918 TE: 58124
922 05:04:23.541356
923 05:04:23.550657 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 05:04:23.551188
925 05:04:23.551642 Board ID = 1
926 05:04:23.552119 Set A53 clk to 24M
927 05:04:23.552564 Set A73 clk to 24M
928 05:04:23.556312 Set clk81 to 24M
929 05:04:23.556797 A53 clk: 1200 MHz
930 05:04:23.557237 A73 clk: 1200 MHz
931 05:04:23.561863 CLK81: 166.6M
932 05:04:23.562336 smccc: 00012a92
933 05:04:23.567494 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 05:04:23.568022 board id: 1
935 05:04:23.576084 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 05:04:23.586725 fw parse done
937 05:04:23.593507 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 05:04:23.635392 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 05:04:23.646242 PIEI prepare done
940 05:04:23.646706 fastboot data load
941 05:04:23.647138 fastboot data verify
942 05:04:23.651825 verify result: 266
943 05:04:23.657511 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 05:04:23.657976 LPDDR4 probe
945 05:04:23.658406 ddr clk to 1584MHz
946 05:04:23.665490 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 05:04:23.702848
948 05:04:23.703317 dmc_version 0001
949 05:04:23.709548 Check phy result
950 05:04:23.715448 INFO : End of CA training
951 05:04:23.715906 INFO : End of initialization
952 05:04:23.721017 INFO : Training has run successfully!
953 05:04:23.721541 Check phy result
954 05:04:23.726689 INFO : End of initialization
955 05:04:23.727164 INFO : End of read enable training
956 05:04:23.729911 INFO : End of fine write leveling
957 05:04:23.735407 INFO : End of Write leveling coarse delay
958 05:04:23.741075 INFO : Training has run successfully!
959 05:04:23.741545 Check phy result
960 05:04:23.741991 INFO : End of initialization
961 05:04:23.746703 INFO : End of read dq deskew training
962 05:04:23.752319 INFO : End of MPR read delay center optimization
963 05:04:23.752796 INFO : End of write delay center optimization
964 05:04:23.757878 INFO : End of read delay center optimization
965 05:04:23.763447 INFO : End of max read latency training
966 05:04:23.763922 INFO : Training has run successfully!
967 05:04:23.768983 1D training succeed
968 05:04:23.774858 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 05:04:23.822410 Check phy result
970 05:04:23.822889 INFO : End of initialization
971 05:04:23.844136 INFO : End of 2D read delay Voltage center optimization
972 05:04:23.864527 INFO : End of 2D read delay Voltage center optimization
973 05:04:23.916587 INFO : End of 2D write delay Voltage center optimization
974 05:04:23.965889 INFO : End of 2D write delay Voltage center optimization
975 05:04:23.971451 INFO : Training has run successfully!
976 05:04:23.971922
977 05:04:23.972428 channel==0
978 05:04:23.976983 RxClkDly_Margin_A0==88 ps 9
979 05:04:23.977458 TxDqDly_Margin_A0==98 ps 10
980 05:04:23.982704 RxClkDly_Margin_A1==88 ps 9
981 05:04:23.983173 TxDqDly_Margin_A1==98 ps 10
982 05:04:23.983624 TrainedVREFDQ_A0==74
983 05:04:23.988229 TrainedVREFDQ_A1==75
984 05:04:23.988706 VrefDac_Margin_A0==25
985 05:04:23.989151 DeviceVref_Margin_A0==40
986 05:04:23.993816 VrefDac_Margin_A1==25
987 05:04:23.994287 DeviceVref_Margin_A1==39
988 05:04:23.994726
989 05:04:23.995165
990 05:04:23.999408 channel==1
991 05:04:23.999879 RxClkDly_Margin_A0==98 ps 10
992 05:04:24.000360 TxDqDly_Margin_A0==88 ps 9
993 05:04:24.004987 RxClkDly_Margin_A1==88 ps 9
994 05:04:24.005458 TxDqDly_Margin_A1==88 ps 9
995 05:04:24.010706 TrainedVREFDQ_A0==77
996 05:04:24.011182 TrainedVREFDQ_A1==77
997 05:04:24.011623 VrefDac_Margin_A0==22
998 05:04:24.016217 DeviceVref_Margin_A0==37
999 05:04:24.016723 VrefDac_Margin_A1==24
1000 05:04:24.021859 DeviceVref_Margin_A1==37
1001 05:04:24.022421
1002 05:04:24.022878 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 05:04:24.023353
1004 05:04:24.055503 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1005 05:04:24.056114 2D training succeed
1006 05:04:24.060948 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 05:04:24.066588 auto size-- 65535DDR cs0 size: 2048MB
1008 05:04:24.067033 DDR cs1 size: 2048MB
1009 05:04:24.072095 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 05:04:24.072534 cs0 DataBus test pass
1011 05:04:24.077692 cs1 DataBus test pass
1012 05:04:24.078127 cs0 AddrBus test pass
1013 05:04:24.078536 cs1 AddrBus test pass
1014 05:04:24.078940
1015 05:04:24.083283 100bdlr_step_size ps== 420
1016 05:04:24.083730 result report
1017 05:04:24.088871 boot times 0Enable ddr reg access
1018 05:04:24.094150 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 05:04:24.106634 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 05:04:24.681585 0.0;M3 CHK:0;cm4_sp_mode 0
1021 05:04:24.682216 MVN_1=0x00000000
1022 05:04:24.686853 MVN_2=0x00000000
1023 05:04:24.692653 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 05:04:24.693110 OPS=0x10
1025 05:04:24.693529 ring efuse init
1026 05:04:24.693934 chipver efuse init
1027 05:04:24.700917 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 05:04:24.701374 [0.018961 Inits done]
1029 05:04:24.701786 secure task start!
1030 05:04:24.708401 high task start!
1031 05:04:24.708850 low task start!
1032 05:04:24.709258 run into bl31
1033 05:04:24.715066 NOTICE: BL31: v1.3(release):4fc40b1
1034 05:04:24.722876 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 05:04:24.723330 NOTICE: BL31: G12A normal boot!
1036 05:04:24.748791 NOTICE: BL31: BL33 decompress pass
1037 05:04:24.754525 ERROR: Error initializing runtime service opteed_fast
1038 05:04:25.987536
1039 05:04:25.988162
1040 05:04:25.995930 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 05:04:25.996417
1042 05:04:25.996829 Model: Libre Computer AML-A311D-CC Alta
1043 05:04:26.204261 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 05:04:26.227627 DRAM: 2 GiB (effective 3.8 GiB)
1045 05:04:26.370857 Core: 408 devices, 31 uclasses, devicetree: separate
1046 05:04:26.376605 WDT: Not starting watchdog@f0d0
1047 05:04:26.408849 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 05:04:26.421208 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 05:04:26.426185 ** Bad device specification mmc 0 **
1050 05:04:26.436564 Card did not respond to voltage select! : -110
1051 05:04:26.444229 ** Bad device specification mmc 0 **
1052 05:04:26.444672 Couldn't find partition mmc 0
1053 05:04:26.452520 Card did not respond to voltage select! : -110
1054 05:04:26.458035 ** Bad device specification mmc 0 **
1055 05:04:26.458477 Couldn't find partition mmc 0
1056 05:04:26.463081 Error: could not access storage.
1057 05:04:26.806675 Net: eth0: ethernet@ff3f0000
1058 05:04:26.807253 starting USB...
1059 05:04:27.058473 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 05:04:27.058972 Starting the controller
1061 05:04:27.065375 USB XHCI 1.10
1062 05:04:28.619507 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 05:04:28.627702 scanning usb for storage devices... 0 Storage Device(s) found
1065 05:04:28.679245 Hit any key to stop autoboot: 1
1066 05:04:28.680014 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 05:04:28.680590 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 05:04:28.681041 Setting prompt string to ['=>']
1069 05:04:28.681498 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 05:04:28.695092 0
1071 05:04:28.695926 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 05:04:28.696426 Sending with 10 millisecond of delay
1074 05:04:29.831050 => setenv autoload no
1075 05:04:29.841831 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1076 05:04:29.846713 setenv autoload no
1077 05:04:29.847460 Sending with 10 millisecond of delay
1079 05:04:31.644771 => setenv initrd_high 0xffffffff
1080 05:04:31.655561 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 05:04:31.656456 setenv initrd_high 0xffffffff
1082 05:04:31.657179 Sending with 10 millisecond of delay
1084 05:04:33.273065 => setenv fdt_high 0xffffffff
1085 05:04:33.283849 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 05:04:33.284719 setenv fdt_high 0xffffffff
1087 05:04:33.285429 Sending with 10 millisecond of delay
1089 05:04:33.577238 => dhcp
1090 05:04:33.588047 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 05:04:33.588876 dhcp
1092 05:04:33.589316 Speed: 1000, full duplex
1093 05:04:33.589729 BOOTP broadcast 1
1094 05:04:33.596811 DHCP client bound to address 192.168.6.27 (8 ms)
1095 05:04:33.597536 Sending with 10 millisecond of delay
1097 05:04:35.273582 => setenv serverip 192.168.6.2
1098 05:04:35.284367 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 05:04:35.285245 setenv serverip 192.168.6.2
1100 05:04:35.285929 Sending with 10 millisecond of delay
1102 05:04:39.008581 => tftpboot 0x01080000 951313/tftp-deploy-myho6boz/kernel/uImage
1103 05:04:39.019375 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1104 05:04:39.020272 tftpboot 0x01080000 951313/tftp-deploy-myho6boz/kernel/uImage
1105 05:04:39.020730 Speed: 1000, full duplex
1106 05:04:39.021145 Using ethernet@ff3f0000 device
1107 05:04:39.022134 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 05:04:39.027685 Filename '951313/tftp-deploy-myho6boz/kernel/uImage'.
1109 05:04:39.031601 Load address: 0x1080000
1110 05:04:41.854865 Loading: *################################################## 43.6 MiB
1111 05:04:41.855486 15.4 MiB/s
1112 05:04:41.855910 done
1113 05:04:41.859059 Bytes transferred = 45713984 (2b98a40 hex)
1114 05:04:41.859848 Sending with 10 millisecond of delay
1116 05:04:46.545510 => tftpboot 0x08000000 951313/tftp-deploy-myho6boz/ramdisk/ramdisk.cpio.gz.uboot
1117 05:04:46.556310 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1118 05:04:46.557126 tftpboot 0x08000000 951313/tftp-deploy-myho6boz/ramdisk/ramdisk.cpio.gz.uboot
1119 05:04:46.557576 Speed: 1000, full duplex
1120 05:04:46.557990 Using ethernet@ff3f0000 device
1121 05:04:46.559006 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 05:04:46.571051 Filename '951313/tftp-deploy-myho6boz/ramdisk/ramdisk.cpio.gz.uboot'.
1123 05:04:46.571583 Load address: 0x8000000
1124 05:04:55.881478 Loading: *########T ######################################### UDP wrong checksum 0000000f 000085e3
1125 05:05:00.882415 T UDP wrong checksum 0000000f 000085e3
1126 05:05:10.885671 T T UDP wrong checksum 0000000f 000085e3
1127 05:05:45.893586 T T T T T T
1128 05:05:45.894218 Retry count exceeded; starting again
1130 05:05:45.895636 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
1133 05:05:45.897541 end: 2.4 uboot-commands (duration 00:01:54) [common]
1135 05:05:45.898861 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1137 05:05:45.899850 end: 2 uboot-action (duration 00:01:54) [common]
1139 05:05:45.901375 Cleaning after the job
1140 05:05:45.901920 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951313/tftp-deploy-myho6boz/ramdisk
1141 05:05:45.903108 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951313/tftp-deploy-myho6boz/kernel
1142 05:05:45.948047 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951313/tftp-deploy-myho6boz/dtb
1143 05:05:45.948846 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951313/tftp-deploy-myho6boz/modules
1144 05:05:45.969645 start: 4.1 power-off (timeout 00:00:30) [common]
1145 05:05:45.970297 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1146 05:05:46.003662 >> OK - accepted request
1147 05:05:46.005746 Returned 0 in 0 seconds
1148 05:05:46.106880 end: 4.1 power-off (duration 00:00:00) [common]
1150 05:05:46.108627 start: 4.2 read-feedback (timeout 00:10:00) [common]
1151 05:05:46.109748 Listened to connection for namespace 'common' for up to 1s
1152 05:05:47.110567 Finalising connection for namespace 'common'
1153 05:05:47.111311 Disconnecting from shell: Finalise
1154 05:05:47.111818 =>
1155 05:05:47.212891 end: 4.2 read-feedback (duration 00:00:01) [common]
1156 05:05:47.213581 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/951313
1157 05:05:47.932291 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/951313
1158 05:05:47.932901 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.