Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 8
- Errors: 0
- Boot result: PASS
- Kernel Errors: 6
1 05:17:52.072165 lava-dispatcher, installed at version: 2024.01
2 05:17:52.072947 start: 0 validate
3 05:17:52.073421 Start time: 2024-11-07 05:17:52.073390+00:00 (UTC)
4 05:17:52.073954 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:17:52.074498 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 05:17:52.115876 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:17:52.116450 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 05:17:52.146577 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:17:52.147184 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:17:52.177325 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:17:52.177801 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:17:52.209765 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:17:52.210247 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 05:17:52.246816 validate duration: 0.17
16 05:17:52.247676 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:17:52.248037 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:17:52.248390 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:17:52.248964 Not decompressing ramdisk as can be used compressed.
20 05:17:52.249424 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 05:17:52.249716 saving as /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/ramdisk/initrd.cpio.gz
22 05:17:52.249993 total size: 5628169 (5 MB)
23 05:17:52.287121 progress 0 % (0 MB)
24 05:17:52.294774 progress 5 % (0 MB)
25 05:17:52.302663 progress 10 % (0 MB)
26 05:17:52.309724 progress 15 % (0 MB)
27 05:17:52.313955 progress 20 % (1 MB)
28 05:17:52.317681 progress 25 % (1 MB)
29 05:17:52.321783 progress 30 % (1 MB)
30 05:17:52.325857 progress 35 % (1 MB)
31 05:17:52.329480 progress 40 % (2 MB)
32 05:17:52.333477 progress 45 % (2 MB)
33 05:17:52.337063 progress 50 % (2 MB)
34 05:17:52.341041 progress 55 % (2 MB)
35 05:17:52.345032 progress 60 % (3 MB)
36 05:17:52.348632 progress 65 % (3 MB)
37 05:17:52.352630 progress 70 % (3 MB)
38 05:17:52.356313 progress 75 % (4 MB)
39 05:17:52.360242 progress 80 % (4 MB)
40 05:17:52.363766 progress 85 % (4 MB)
41 05:17:52.367716 progress 90 % (4 MB)
42 05:17:52.371478 progress 95 % (5 MB)
43 05:17:52.374737 progress 100 % (5 MB)
44 05:17:52.375399 5 MB downloaded in 0.13 s (42.81 MB/s)
45 05:17:52.375953 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:17:52.376921 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:17:52.377247 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:17:52.377543 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:17:52.378026 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/kernel/Image
51 05:17:52.378313 saving as /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/kernel/Image
52 05:17:52.378537 total size: 45713920 (43 MB)
53 05:17:52.378757 No compression specified
54 05:17:52.412535 progress 0 % (0 MB)
55 05:17:52.440660 progress 5 % (2 MB)
56 05:17:52.468936 progress 10 % (4 MB)
57 05:17:52.497282 progress 15 % (6 MB)
58 05:17:52.525431 progress 20 % (8 MB)
59 05:17:52.553519 progress 25 % (10 MB)
60 05:17:52.581659 progress 30 % (13 MB)
61 05:17:52.609701 progress 35 % (15 MB)
62 05:17:52.637761 progress 40 % (17 MB)
63 05:17:52.665680 progress 45 % (19 MB)
64 05:17:52.693697 progress 50 % (21 MB)
65 05:17:52.721755 progress 55 % (24 MB)
66 05:17:52.750138 progress 60 % (26 MB)
67 05:17:52.777721 progress 65 % (28 MB)
68 05:17:52.805574 progress 70 % (30 MB)
69 05:17:52.833652 progress 75 % (32 MB)
70 05:17:52.862005 progress 80 % (34 MB)
71 05:17:52.889535 progress 85 % (37 MB)
72 05:17:52.917626 progress 90 % (39 MB)
73 05:17:52.945463 progress 95 % (41 MB)
74 05:17:52.973317 progress 100 % (43 MB)
75 05:17:52.973876 43 MB downloaded in 0.60 s (73.23 MB/s)
76 05:17:52.974375 end: 1.2.1 http-download (duration 00:00:01) [common]
78 05:17:52.975229 end: 1.2 download-retry (duration 00:00:01) [common]
79 05:17:52.975526 start: 1.3 download-retry (timeout 00:09:59) [common]
80 05:17:52.975806 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 05:17:52.976310 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 05:17:52.976593 saving as /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/dtb/meson-g12b-a311d-libretech-cc.dtb
83 05:17:52.976813 total size: 54703 (0 MB)
84 05:17:52.977032 No compression specified
85 05:17:53.016440 progress 59 % (0 MB)
86 05:17:53.017304 progress 100 % (0 MB)
87 05:17:53.017899 0 MB downloaded in 0.04 s (1.27 MB/s)
88 05:17:53.018392 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:17:53.019247 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:17:53.019531 start: 1.4 download-retry (timeout 00:09:59) [common]
92 05:17:53.019808 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 05:17:53.020307 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 05:17:53.020572 saving as /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/nfsrootfs/full.rootfs.tar
95 05:17:53.020787 total size: 120894716 (115 MB)
96 05:17:53.021007 Using unxz to decompress xz
97 05:17:53.061666 progress 0 % (0 MB)
98 05:17:53.860585 progress 5 % (5 MB)
99 05:17:54.709412 progress 10 % (11 MB)
100 05:17:55.508340 progress 15 % (17 MB)
101 05:17:56.250930 progress 20 % (23 MB)
102 05:17:56.844282 progress 25 % (28 MB)
103 05:17:57.695654 progress 30 % (34 MB)
104 05:17:58.482121 progress 35 % (40 MB)
105 05:17:58.828341 progress 40 % (46 MB)
106 05:17:59.199487 progress 45 % (51 MB)
107 05:17:59.918273 progress 50 % (57 MB)
108 05:18:00.804272 progress 55 % (63 MB)
109 05:18:01.588387 progress 60 % (69 MB)
110 05:18:02.346773 progress 65 % (74 MB)
111 05:18:03.123751 progress 70 % (80 MB)
112 05:18:03.945570 progress 75 % (86 MB)
113 05:18:04.730551 progress 80 % (92 MB)
114 05:18:05.488389 progress 85 % (98 MB)
115 05:18:06.338095 progress 90 % (103 MB)
116 05:18:07.111323 progress 95 % (109 MB)
117 05:18:07.941450 progress 100 % (115 MB)
118 05:18:07.954423 115 MB downloaded in 14.93 s (7.72 MB/s)
119 05:18:07.955297 end: 1.4.1 http-download (duration 00:00:15) [common]
121 05:18:07.956976 end: 1.4 download-retry (duration 00:00:15) [common]
122 05:18:07.957509 start: 1.5 download-retry (timeout 00:09:44) [common]
123 05:18:07.958035 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 05:18:07.958928 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/modules.tar.xz
125 05:18:07.959402 saving as /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/modules/modules.tar
126 05:18:07.959817 total size: 11607084 (11 MB)
127 05:18:07.960271 Using unxz to decompress xz
128 05:18:07.998835 progress 0 % (0 MB)
129 05:18:08.078323 progress 5 % (0 MB)
130 05:18:08.166451 progress 10 % (1 MB)
131 05:18:08.280925 progress 15 % (1 MB)
132 05:18:08.388985 progress 20 % (2 MB)
133 05:18:08.483633 progress 25 % (2 MB)
134 05:18:08.572955 progress 30 % (3 MB)
135 05:18:08.659416 progress 35 % (3 MB)
136 05:18:08.749954 progress 40 % (4 MB)
137 05:18:08.839083 progress 45 % (5 MB)
138 05:18:08.937769 progress 50 % (5 MB)
139 05:18:09.028881 progress 55 % (6 MB)
140 05:18:09.129302 progress 60 % (6 MB)
141 05:18:09.223829 progress 65 % (7 MB)
142 05:18:09.313739 progress 70 % (7 MB)
143 05:18:09.409740 progress 75 % (8 MB)
144 05:18:09.508319 progress 80 % (8 MB)
145 05:18:09.603014 progress 85 % (9 MB)
146 05:18:09.695168 progress 90 % (9 MB)
147 05:18:09.785927 progress 95 % (10 MB)
148 05:18:09.876233 progress 100 % (11 MB)
149 05:18:09.889197 11 MB downloaded in 1.93 s (5.74 MB/s)
150 05:18:09.890066 end: 1.5.1 http-download (duration 00:00:02) [common]
152 05:18:09.891749 end: 1.5 download-retry (duration 00:00:02) [common]
153 05:18:09.892328 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 05:18:09.892846 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 05:18:26.200597 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/951357/extract-nfsrootfs-6yd7u1kw
156 05:18:26.201204 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 05:18:26.201490 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 05:18:26.202119 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us
159 05:18:26.202552 makedir: /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin
160 05:18:26.202876 makedir: /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/tests
161 05:18:26.203188 makedir: /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/results
162 05:18:26.203514 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-add-keys
163 05:18:26.204060 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-add-sources
164 05:18:26.204575 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-background-process-start
165 05:18:26.205101 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-background-process-stop
166 05:18:26.205689 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-common-functions
167 05:18:26.206207 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-echo-ipv4
168 05:18:26.206687 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-install-packages
169 05:18:26.207152 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-installed-packages
170 05:18:26.207688 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-os-build
171 05:18:26.208206 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-probe-channel
172 05:18:26.208687 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-probe-ip
173 05:18:26.209143 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-target-ip
174 05:18:26.209608 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-target-mac
175 05:18:26.210071 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-target-storage
176 05:18:26.210537 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-test-case
177 05:18:26.211003 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-test-event
178 05:18:26.211458 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-test-feedback
179 05:18:26.211911 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-test-raise
180 05:18:26.212408 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-test-reference
181 05:18:26.212898 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-test-runner
182 05:18:26.213400 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-test-set
183 05:18:26.213867 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-test-shell
184 05:18:26.214339 Updating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-add-keys (debian)
185 05:18:26.214854 Updating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-add-sources (debian)
186 05:18:26.215342 Updating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-install-packages (debian)
187 05:18:26.215826 Updating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-installed-packages (debian)
188 05:18:26.216346 Updating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/bin/lava-os-build (debian)
189 05:18:26.216775 Creating /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/environment
190 05:18:26.217129 LAVA metadata
191 05:18:26.217386 - LAVA_JOB_ID=951357
192 05:18:26.217600 - LAVA_DISPATCHER_IP=192.168.6.2
193 05:18:26.217951 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 05:18:26.218884 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 05:18:26.219189 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 05:18:26.219393 skipped lava-vland-overlay
197 05:18:26.219632 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 05:18:26.219884 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 05:18:26.220134 skipped lava-multinode-overlay
200 05:18:26.220376 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 05:18:26.220626 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 05:18:26.220870 Loading test definitions
203 05:18:26.221143 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 05:18:26.221362 Using /lava-951357 at stage 0
205 05:18:26.222440 uuid=951357_1.6.2.4.1 testdef=None
206 05:18:26.222738 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 05:18:26.222998 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 05:18:26.224578 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 05:18:26.225365 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 05:18:26.227253 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 05:18:26.228147 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 05:18:26.230030 runner path: /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/0/tests/0_timesync-off test_uuid 951357_1.6.2.4.1
215 05:18:26.230611 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 05:18:26.231425 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 05:18:26.231649 Using /lava-951357 at stage 0
219 05:18:26.232019 Fetching tests from https://github.com/kernelci/test-definitions.git
220 05:18:26.232321 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/0/tests/1_kselftest-alsa'
221 05:18:29.815284 Running '/usr/bin/git checkout kernelci.org
222 05:18:30.266472 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 05:18:30.267912 uuid=951357_1.6.2.4.5 testdef=None
224 05:18:30.268506 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 05:18:30.269982 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 05:18:30.275310 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 05:18:30.276941 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 05:18:30.284039 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 05:18:30.285697 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 05:18:30.292670 runner path: /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/0/tests/1_kselftest-alsa test_uuid 951357_1.6.2.4.5
234 05:18:30.293200 BOARD='meson-g12b-a311d-libretech-cc'
235 05:18:30.293613 BRANCH='broonie-sound'
236 05:18:30.294008 SKIPFILE='/dev/null'
237 05:18:30.294408 SKIP_INSTALL='True'
238 05:18:30.294800 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 05:18:30.295205 TST_CASENAME=''
240 05:18:30.295598 TST_CMDFILES='alsa'
241 05:18:30.296621 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 05:18:30.298169 Creating lava-test-runner.conf files
244 05:18:30.298579 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/951357/lava-overlay-ink_i6us/lava-951357/0 for stage 0
245 05:18:30.299247 - 0_timesync-off
246 05:18:30.299712 - 1_kselftest-alsa
247 05:18:30.300393 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 05:18:30.300940 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 05:18:53.651191 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 05:18:53.651647 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 05:18:53.651943 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 05:18:53.652287 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 05:18:53.652581 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 05:18:54.262003 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 05:18:54.262493 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 05:18:54.262762 extracting modules file /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/951357/extract-nfsrootfs-6yd7u1kw
257 05:18:55.855133 extracting modules file /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/951357/extract-overlay-ramdisk-_72t2rh9/ramdisk
258 05:18:57.452334 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 05:18:57.452820 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 05:18:57.453100 [common] Applying overlay to NFS
261 05:18:57.453315 [common] Applying overlay /var/lib/lava/dispatcher/tmp/951357/compress-overlay-1_i6phd8/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/951357/extract-nfsrootfs-6yd7u1kw
262 05:19:00.740118 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 05:19:00.740698 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 05:19:00.741032 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 05:19:00.741317 Converting downloaded kernel to a uImage
266 05:19:00.741687 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/kernel/Image /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/kernel/uImage
267 05:19:01.217822 output: Image Name:
268 05:19:01.218247 output: Created: Thu Nov 7 05:19:00 2024
269 05:19:01.218458 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 05:19:01.218664 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 05:19:01.218865 output: Load Address: 01080000
272 05:19:01.219067 output: Entry Point: 01080000
273 05:19:01.219265 output:
274 05:19:01.219599 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 05:19:01.219865 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 05:19:01.220195 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 05:19:01.220458 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 05:19:01.220718 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 05:19:01.220976 Building ramdisk /var/lib/lava/dispatcher/tmp/951357/extract-overlay-ramdisk-_72t2rh9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/951357/extract-overlay-ramdisk-_72t2rh9/ramdisk
280 05:19:03.431164 >> 166792 blocks
281 05:19:11.183042 Adding RAMdisk u-boot header.
282 05:19:11.183904 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/951357/extract-overlay-ramdisk-_72t2rh9/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/951357/extract-overlay-ramdisk-_72t2rh9/ramdisk.cpio.gz.uboot
283 05:19:11.421989 output: Image Name:
284 05:19:11.422421 output: Created: Thu Nov 7 05:19:11 2024
285 05:19:11.422632 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 05:19:11.422838 output: Data Size: 23432262 Bytes = 22883.07 KiB = 22.35 MiB
287 05:19:11.423041 output: Load Address: 00000000
288 05:19:11.423241 output: Entry Point: 00000000
289 05:19:11.423441 output:
290 05:19:11.424147 rename /var/lib/lava/dispatcher/tmp/951357/extract-overlay-ramdisk-_72t2rh9/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/ramdisk/ramdisk.cpio.gz.uboot
291 05:19:11.424873 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 05:19:11.425414 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 05:19:11.425972 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 05:19:11.426420 No LXC device requested
295 05:19:11.426913 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 05:19:11.427418 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 05:19:11.427905 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 05:19:11.428349 Checking files for TFTP limit of 4294967296 bytes.
299 05:19:11.430980 end: 1 tftp-deploy (duration 00:01:19) [common]
300 05:19:11.431542 start: 2 uboot-action (timeout 00:05:00) [common]
301 05:19:11.432088 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 05:19:11.432588 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 05:19:11.433085 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 05:19:11.433603 Using kernel file from prepare-kernel: 951357/tftp-deploy-dwn9kkvn/kernel/uImage
305 05:19:11.434226 substitutions:
306 05:19:11.434633 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 05:19:11.435033 - {DTB_ADDR}: 0x01070000
308 05:19:11.435430 - {DTB}: 951357/tftp-deploy-dwn9kkvn/dtb/meson-g12b-a311d-libretech-cc.dtb
309 05:19:11.435831 - {INITRD}: 951357/tftp-deploy-dwn9kkvn/ramdisk/ramdisk.cpio.gz.uboot
310 05:19:11.436278 - {KERNEL_ADDR}: 0x01080000
311 05:19:11.436674 - {KERNEL}: 951357/tftp-deploy-dwn9kkvn/kernel/uImage
312 05:19:11.437064 - {LAVA_MAC}: None
313 05:19:11.437489 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/951357/extract-nfsrootfs-6yd7u1kw
314 05:19:11.437886 - {NFS_SERVER_IP}: 192.168.6.2
315 05:19:11.438274 - {PRESEED_CONFIG}: None
316 05:19:11.438662 - {PRESEED_LOCAL}: None
317 05:19:11.439046 - {RAMDISK_ADDR}: 0x08000000
318 05:19:11.439433 - {RAMDISK}: 951357/tftp-deploy-dwn9kkvn/ramdisk/ramdisk.cpio.gz.uboot
319 05:19:11.439820 - {ROOT_PART}: None
320 05:19:11.440242 - {ROOT}: None
321 05:19:11.440633 - {SERVER_IP}: 192.168.6.2
322 05:19:11.441021 - {TEE_ADDR}: 0x83000000
323 05:19:11.441404 - {TEE}: None
324 05:19:11.441788 Parsed boot commands:
325 05:19:11.442160 - setenv autoload no
326 05:19:11.442544 - setenv initrd_high 0xffffffff
327 05:19:11.442926 - setenv fdt_high 0xffffffff
328 05:19:11.443311 - dhcp
329 05:19:11.443692 - setenv serverip 192.168.6.2
330 05:19:11.444104 - tftpboot 0x01080000 951357/tftp-deploy-dwn9kkvn/kernel/uImage
331 05:19:11.444500 - tftpboot 0x08000000 951357/tftp-deploy-dwn9kkvn/ramdisk/ramdisk.cpio.gz.uboot
332 05:19:11.444890 - tftpboot 0x01070000 951357/tftp-deploy-dwn9kkvn/dtb/meson-g12b-a311d-libretech-cc.dtb
333 05:19:11.445277 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/951357/extract-nfsrootfs-6yd7u1kw,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 05:19:11.445681 - bootm 0x01080000 0x08000000 0x01070000
335 05:19:11.446174 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 05:19:11.447641 start: 2.3 connect-device (timeout 00:05:00) [common]
338 05:19:11.448082 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 05:19:11.463415 Setting prompt string to ['lava-test: # ']
340 05:19:11.464966 end: 2.3 connect-device (duration 00:00:00) [common]
341 05:19:11.465571 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 05:19:11.466135 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 05:19:11.466674 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 05:19:11.468175 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 05:19:11.507347 >> OK - accepted request
346 05:19:11.509477 Returned 0 in 0 seconds
347 05:19:11.610571 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 05:19:11.612228 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 05:19:11.612778 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 05:19:11.613276 Setting prompt string to ['Hit any key to stop autoboot']
352 05:19:11.613724 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 05:19:11.615271 Trying 192.168.56.21...
354 05:19:11.615740 Connected to conserv1.
355 05:19:11.616181 Escape character is '^]'.
356 05:19:11.616593
357 05:19:11.616999 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 05:19:11.617414
359 05:19:22.570784 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 05:19:22.571500 bl2_stage_init 0x01
361 05:19:22.572056 bl2_stage_init 0x81
362 05:19:22.576265 hw id: 0x0000 - pwm id 0x01
363 05:19:22.576835 bl2_stage_init 0xc1
364 05:19:22.577302 bl2_stage_init 0x02
365 05:19:22.577756
366 05:19:22.581831 L0:00000000
367 05:19:22.582357 L1:20000703
368 05:19:22.582815 L2:00008067
369 05:19:22.583267 L3:14000000
370 05:19:22.584661 B2:00402000
371 05:19:22.585164 B1:e0f83180
372 05:19:22.585598
373 05:19:22.586036 TE: 58124
374 05:19:22.586473
375 05:19:22.595722 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 05:19:22.596243
377 05:19:22.596680 Board ID = 1
378 05:19:22.597110 Set A53 clk to 24M
379 05:19:22.597538 Set A73 clk to 24M
380 05:19:22.601289 Set clk81 to 24M
381 05:19:22.601769 A53 clk: 1200 MHz
382 05:19:22.602199 A73 clk: 1200 MHz
383 05:19:22.604965 CLK81: 166.6M
384 05:19:22.605434 smccc: 00012a92
385 05:19:22.610389 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 05:19:22.616086 board id: 1
387 05:19:22.621161 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 05:19:22.631858 fw parse done
389 05:19:22.637811 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 05:19:22.680482 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 05:19:22.691386 PIEI prepare done
392 05:19:22.691898 fastboot data load
393 05:19:22.692373 fastboot data verify
394 05:19:22.696969 verify result: 266
395 05:19:22.702573 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 05:19:22.703096 LPDDR4 probe
397 05:19:22.703564 ddr clk to 1584MHz
398 05:19:22.710593 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 05:19:22.747883
400 05:19:22.748544 dmc_version 0001
401 05:19:22.754439 Check phy result
402 05:19:22.760230 INFO : End of CA training
403 05:19:22.760716 INFO : End of initialization
404 05:19:22.765855 INFO : Training has run successfully!
405 05:19:22.766333 Check phy result
406 05:19:22.771408 INFO : End of initialization
407 05:19:22.771887 INFO : End of read enable training
408 05:19:22.777065 INFO : End of fine write leveling
409 05:19:22.782646 INFO : End of Write leveling coarse delay
410 05:19:22.783126 INFO : Training has run successfully!
411 05:19:22.783577 Check phy result
412 05:19:22.788265 INFO : End of initialization
413 05:19:22.788758 INFO : End of read dq deskew training
414 05:19:22.793822 INFO : End of MPR read delay center optimization
415 05:19:22.799461 INFO : End of write delay center optimization
416 05:19:22.805044 INFO : End of read delay center optimization
417 05:19:22.805544 INFO : End of max read latency training
418 05:19:22.810658 INFO : Training has run successfully!
419 05:19:22.811138 1D training succeed
420 05:19:22.819833 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 05:19:22.867480 Check phy result
422 05:19:22.868022 INFO : End of initialization
423 05:19:22.889176 INFO : End of 2D read delay Voltage center optimization
424 05:19:22.909316 INFO : End of 2D read delay Voltage center optimization
425 05:19:22.961212 INFO : End of 2D write delay Voltage center optimization
426 05:19:23.010427 INFO : End of 2D write delay Voltage center optimization
427 05:19:23.016082 INFO : Training has run successfully!
428 05:19:23.016568
429 05:19:23.017024 channel==0
430 05:19:23.021628 RxClkDly_Margin_A0==88 ps 9
431 05:19:23.022121 TxDqDly_Margin_A0==98 ps 10
432 05:19:23.024860 RxClkDly_Margin_A1==88 ps 9
433 05:19:23.025328 TxDqDly_Margin_A1==98 ps 10
434 05:19:23.030444 TrainedVREFDQ_A0==74
435 05:19:23.030952 TrainedVREFDQ_A1==74
436 05:19:23.036089 VrefDac_Margin_A0==25
437 05:19:23.036572 DeviceVref_Margin_A0==40
438 05:19:23.037026 VrefDac_Margin_A1==25
439 05:19:23.041575 DeviceVref_Margin_A1==40
440 05:19:23.042063
441 05:19:23.042517
442 05:19:23.042967 channel==1
443 05:19:23.043410 RxClkDly_Margin_A0==88 ps 9
444 05:19:23.047148 TxDqDly_Margin_A0==98 ps 10
445 05:19:23.047629 RxClkDly_Margin_A1==98 ps 10
446 05:19:23.052752 TxDqDly_Margin_A1==88 ps 9
447 05:19:23.053247 TrainedVREFDQ_A0==77
448 05:19:23.053701 TrainedVREFDQ_A1==77
449 05:19:23.058408 VrefDac_Margin_A0==22
450 05:19:23.058890 DeviceVref_Margin_A0==37
451 05:19:23.064450 VrefDac_Margin_A1==22
452 05:19:23.065012 DeviceVref_Margin_A1==37
453 05:19:23.065466
454 05:19:23.069726 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 05:19:23.070214
456 05:19:23.097680 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 05:19:23.103176 2D training succeed
458 05:19:23.108870 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 05:19:23.109486 auto size-- 65535DDR cs0 size: 2048MB
460 05:19:23.114330 DDR cs1 size: 2048MB
461 05:19:23.114867 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 05:19:23.119897 cs0 DataBus test pass
463 05:19:23.120396 cs1 DataBus test pass
464 05:19:23.120897 cs0 AddrBus test pass
465 05:19:23.125491 cs1 AddrBus test pass
466 05:19:23.126008
467 05:19:23.126490 100bdlr_step_size ps== 420
468 05:19:23.126965 result report
469 05:19:23.131102 boot times 0Enable ddr reg access
470 05:19:23.138802 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 05:19:23.152253 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 05:19:23.724312 0.0;M3 CHK:0;cm4_sp_mode 0
473 05:19:23.724768 MVN_1=0x00000000
474 05:19:23.729697 MVN_2=0x00000000
475 05:19:23.735453 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 05:19:23.735736 OPS=0x10
477 05:19:23.735968 ring efuse init
478 05:19:23.736254 chipver efuse init
479 05:19:23.741086 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 05:19:23.746695 [0.018961 Inits done]
481 05:19:23.746958 secure task start!
482 05:19:23.747186 high task start!
483 05:19:23.751245 low task start!
484 05:19:23.751509 run into bl31
485 05:19:23.757996 NOTICE: BL31: v1.3(release):4fc40b1
486 05:19:23.765689 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 05:19:23.765966 NOTICE: BL31: G12A normal boot!
488 05:19:23.791044 NOTICE: BL31: BL33 decompress pass
489 05:19:23.796787 ERROR: Error initializing runtime service opteed_fast
490 05:19:25.029830
491 05:19:25.030522
492 05:19:25.038112 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 05:19:25.038637
494 05:19:25.039086 Model: Libre Computer AML-A311D-CC Alta
495 05:19:25.246903 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 05:19:25.270161 DRAM: 2 GiB (effective 3.8 GiB)
497 05:19:25.413042 Core: 408 devices, 31 uclasses, devicetree: separate
498 05:19:25.418883 WDT: Not starting watchdog@f0d0
499 05:19:25.451080 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 05:19:25.463553 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 05:19:25.468486 ** Bad device specification mmc 0 **
502 05:19:25.478851 Card did not respond to voltage select! : -110
503 05:19:25.486559 ** Bad device specification mmc 0 **
504 05:19:25.487075 Couldn't find partition mmc 0
505 05:19:25.494948 Card did not respond to voltage select! : -110
506 05:19:25.500371 ** Bad device specification mmc 0 **
507 05:19:25.500916 Couldn't find partition mmc 0
508 05:19:25.505448 Error: could not access storage.
509 05:19:26.771003 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
510 05:19:26.771711 bl2_stage_init 0x81
511 05:19:26.776579 hw id: 0x0000 - pwm id 0x01
512 05:19:26.777115 bl2_stage_init 0xc1
513 05:19:26.777594 bl2_stage_init 0x02
514 05:19:26.778060
515 05:19:26.782138 L0:00000000
516 05:19:26.782668 L1:20000703
517 05:19:26.783133 L2:00008067
518 05:19:26.783592 L3:14000000
519 05:19:26.784091 B2:00402000
520 05:19:26.784978 B1:e0f83180
521 05:19:26.785482
522 05:19:26.785955 TE: 58150
523 05:19:26.786415
524 05:19:26.796164 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 05:19:26.796704
526 05:19:26.797176 Board ID = 1
527 05:19:26.797642 Set A53 clk to 24M
528 05:19:26.798099 Set A73 clk to 24M
529 05:19:26.801721 Set clk81 to 24M
530 05:19:26.802234 A53 clk: 1200 MHz
531 05:19:26.802704 A73 clk: 1200 MHz
532 05:19:26.807353 CLK81: 166.6M
533 05:19:26.807866 smccc: 00012aab
534 05:19:26.812910 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 05:19:26.813449 board id: 1
536 05:19:26.821561 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 05:19:26.832160 fw parse done
538 05:19:26.838097 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 05:19:26.880729 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 05:19:26.891647 PIEI prepare done
541 05:19:26.892204 fastboot data load
542 05:19:26.892678 fastboot data verify
543 05:19:26.897423 verify result: 266
544 05:19:26.902966 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 05:19:26.903484 LPDDR4 probe
546 05:19:26.903938 ddr clk to 1584MHz
547 05:19:26.910946 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 05:19:26.948227
549 05:19:26.948776 dmc_version 0001
550 05:19:26.954867 Check phy result
551 05:19:26.960751 INFO : End of CA training
552 05:19:26.961265 INFO : End of initialization
553 05:19:26.966343 INFO : Training has run successfully!
554 05:19:26.966849 Check phy result
555 05:19:26.971933 INFO : End of initialization
556 05:19:26.972468 INFO : End of read enable training
557 05:19:26.977628 INFO : End of fine write leveling
558 05:19:26.983114 INFO : End of Write leveling coarse delay
559 05:19:26.983620 INFO : Training has run successfully!
560 05:19:26.984113 Check phy result
561 05:19:26.988726 INFO : End of initialization
562 05:19:26.989239 INFO : End of read dq deskew training
563 05:19:26.994361 INFO : End of MPR read delay center optimization
564 05:19:26.999948 INFO : End of write delay center optimization
565 05:19:27.005654 INFO : End of read delay center optimization
566 05:19:27.006174 INFO : End of max read latency training
567 05:19:27.011147 INFO : Training has run successfully!
568 05:19:27.011672 1D training succeed
569 05:19:27.020341 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 05:19:27.068060 Check phy result
571 05:19:27.068680 INFO : End of initialization
572 05:19:27.089752 INFO : End of 2D read delay Voltage center optimization
573 05:19:27.109928 INFO : End of 2D read delay Voltage center optimization
574 05:19:27.161971 INFO : End of 2D write delay Voltage center optimization
575 05:19:27.211316 INFO : End of 2D write delay Voltage center optimization
576 05:19:27.216878 INFO : Training has run successfully!
577 05:19:27.217403
578 05:19:27.217868 channel==0
579 05:19:27.222529 RxClkDly_Margin_A0==88 ps 9
580 05:19:27.223039 TxDqDly_Margin_A0==98 ps 10
581 05:19:27.228113 RxClkDly_Margin_A1==88 ps 9
582 05:19:27.228635 TxDqDly_Margin_A1==98 ps 10
583 05:19:27.229108 TrainedVREFDQ_A0==74
584 05:19:27.233648 TrainedVREFDQ_A1==75
585 05:19:27.234157 VrefDac_Margin_A0==25
586 05:19:27.234624 DeviceVref_Margin_A0==40
587 05:19:27.239259 VrefDac_Margin_A1==24
588 05:19:27.239784 DeviceVref_Margin_A1==39
589 05:19:27.240307
590 05:19:27.240775
591 05:19:27.244875 channel==1
592 05:19:27.245393 RxClkDly_Margin_A0==98 ps 10
593 05:19:27.245864 TxDqDly_Margin_A0==88 ps 9
594 05:19:27.250478 RxClkDly_Margin_A1==88 ps 9
595 05:19:27.251001 TxDqDly_Margin_A1==88 ps 9
596 05:19:27.256130 TrainedVREFDQ_A0==76
597 05:19:27.256651 TrainedVREFDQ_A1==77
598 05:19:27.257118 VrefDac_Margin_A0==22
599 05:19:27.261668 DeviceVref_Margin_A0==38
600 05:19:27.262183 VrefDac_Margin_A1==24
601 05:19:27.267289 DeviceVref_Margin_A1==37
602 05:19:27.267801
603 05:19:27.268320 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 05:19:27.268783
605 05:19:27.300892 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
606 05:19:27.301519 2D training succeed
607 05:19:27.306466 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 05:19:27.312075 auto size-- 65535DDR cs0 size: 2048MB
609 05:19:27.312593 DDR cs1 size: 2048MB
610 05:19:27.317648 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 05:19:27.318157 cs0 DataBus test pass
612 05:19:27.323254 cs1 DataBus test pass
613 05:19:27.323789 cs0 AddrBus test pass
614 05:19:27.324288 cs1 AddrBus test pass
615 05:19:27.324736
616 05:19:27.328861 100bdlr_step_size ps== 420
617 05:19:27.329389 result report
618 05:19:27.334469 boot times 0Enable ddr reg access
619 05:19:27.339755 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 05:19:27.353216 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 05:19:27.926835 0.0;M3 CHK:0;cm4_sp_mode 0
622 05:19:27.927271 MVN_1=0x00000000
623 05:19:27.932366 MVN_2=0x00000000
624 05:19:27.938046 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 05:19:27.938560 OPS=0x10
626 05:19:27.938968 ring efuse init
627 05:19:27.939362 chipver efuse init
628 05:19:27.943642 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 05:19:27.949229 [0.018961 Inits done]
630 05:19:27.949669 secure task start!
631 05:19:27.950060 high task start!
632 05:19:27.953807 low task start!
633 05:19:27.954239 run into bl31
634 05:19:27.960596 NOTICE: BL31: v1.3(release):4fc40b1
635 05:19:27.968299 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 05:19:27.968750 NOTICE: BL31: G12A normal boot!
637 05:19:27.993637 NOTICE: BL31: BL33 decompress pass
638 05:19:27.999282 ERROR: Error initializing runtime service opteed_fast
639 05:19:29.232464
640 05:19:29.232913
641 05:19:29.240795 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 05:19:29.241247
643 05:19:29.241639 Model: Libre Computer AML-A311D-CC Alta
644 05:19:29.449287 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 05:19:29.472776 DRAM: 2 GiB (effective 3.8 GiB)
646 05:19:29.615688 Core: 408 devices, 31 uclasses, devicetree: separate
647 05:19:29.621529 WDT: Not starting watchdog@f0d0
648 05:19:29.653634 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 05:19:29.666162 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 05:19:29.671124 ** Bad device specification mmc 0 **
651 05:19:29.681414 Card did not respond to voltage select! : -110
652 05:19:29.689132 ** Bad device specification mmc 0 **
653 05:19:29.689580 Couldn't find partition mmc 0
654 05:19:29.697462 Card did not respond to voltage select! : -110
655 05:19:29.702863 ** Bad device specification mmc 0 **
656 05:19:29.703305 Couldn't find partition mmc 0
657 05:19:29.707970 Error: could not access storage.
658 05:19:30.051726 Net: eth0: ethernet@ff3f0000
659 05:19:30.052363 starting USB...
660 05:19:30.303422 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 05:19:30.303968 Starting the controller
662 05:19:30.310406 USB XHCI 1.10
663 05:19:32.022700 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
664 05:19:32.023350 bl2_stage_init 0x01
665 05:19:32.023779 bl2_stage_init 0x81
666 05:19:32.028300 hw id: 0x0000 - pwm id 0x01
667 05:19:32.028836 bl2_stage_init 0xc1
668 05:19:32.029259 bl2_stage_init 0x02
669 05:19:32.029667
670 05:19:32.033780 L0:00000000
671 05:19:32.034308 L1:20000703
672 05:19:32.034734 L2:00008067
673 05:19:32.035144 L3:14000000
674 05:19:32.036699 B2:00402000
675 05:19:32.037139 B1:e0f83180
676 05:19:32.037545
677 05:19:32.037947 TE: 58167
678 05:19:32.038346
679 05:19:32.047833 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 05:19:32.048309
681 05:19:32.048716 Board ID = 1
682 05:19:32.049115 Set A53 clk to 24M
683 05:19:32.049509 Set A73 clk to 24M
684 05:19:32.053451 Set clk81 to 24M
685 05:19:32.053885 A53 clk: 1200 MHz
686 05:19:32.054286 A73 clk: 1200 MHz
687 05:19:32.058971 CLK81: 166.6M
688 05:19:32.059400 smccc: 00012abe
689 05:19:32.064654 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 05:19:32.065102 board id: 1
691 05:19:32.073435 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 05:19:32.083743 fw parse done
693 05:19:32.089713 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 05:19:32.132403 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 05:19:32.143291 PIEI prepare done
696 05:19:32.143777 fastboot data load
697 05:19:32.144231 fastboot data verify
698 05:19:32.148920 verify result: 266
699 05:19:32.154500 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 05:19:32.154929 LPDDR4 probe
701 05:19:32.155329 ddr clk to 1584MHz
702 05:19:32.162469 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 05:19:32.199728
704 05:19:32.200216 dmc_version 0001
705 05:19:32.206418 Check phy result
706 05:19:32.212263 INFO : End of CA training
707 05:19:32.212700 INFO : End of initialization
708 05:19:32.217876 INFO : Training has run successfully!
709 05:19:32.218310 Check phy result
710 05:19:32.223509 INFO : End of initialization
711 05:19:32.223942 INFO : End of read enable training
712 05:19:32.229085 INFO : End of fine write leveling
713 05:19:32.234695 INFO : End of Write leveling coarse delay
714 05:19:32.235131 INFO : Training has run successfully!
715 05:19:32.235533 Check phy result
716 05:19:32.240269 INFO : End of initialization
717 05:19:32.240704 INFO : End of read dq deskew training
718 05:19:32.245858 INFO : End of MPR read delay center optimization
719 05:19:32.251460 INFO : End of write delay center optimization
720 05:19:32.257114 INFO : End of read delay center optimization
721 05:19:32.257572 INFO : End of max read latency training
722 05:19:32.262721 INFO : Training has run successfully!
723 05:19:32.263230 1D training succeed
724 05:19:32.271866 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 05:19:32.319497 Check phy result
726 05:19:32.320032 INFO : End of initialization
727 05:19:32.341140 INFO : End of 2D read delay Voltage center optimization
728 05:19:32.361185 INFO : End of 2D read delay Voltage center optimization
729 05:19:32.413152 INFO : End of 2D write delay Voltage center optimization
730 05:19:32.462400 INFO : End of 2D write delay Voltage center optimization
731 05:19:32.468259 INFO : Training has run successfully!
732 05:19:32.468759
733 05:19:32.469199 channel==0
734 05:19:32.473494 RxClkDly_Margin_A0==88 ps 9
735 05:19:32.473966 TxDqDly_Margin_A0==98 ps 10
736 05:19:32.479128 RxClkDly_Margin_A1==88 ps 9
737 05:19:32.479628 TxDqDly_Margin_A1==98 ps 10
738 05:19:32.480113 TrainedVREFDQ_A0==74
739 05:19:32.484668 TrainedVREFDQ_A1==75
740 05:19:32.485143 VrefDac_Margin_A0==25
741 05:19:32.485587 DeviceVref_Margin_A0==40
742 05:19:32.490286 VrefDac_Margin_A1==23
743 05:19:32.490738 DeviceVref_Margin_A1==39
744 05:19:32.491134
745 05:19:32.491528
746 05:19:32.495857 channel==1
747 05:19:32.496335 RxClkDly_Margin_A0==98 ps 10
748 05:19:32.496752 TxDqDly_Margin_A0==98 ps 10
749 05:19:32.501506 RxClkDly_Margin_A1==88 ps 9
750 05:19:32.501985 TxDqDly_Margin_A1==88 ps 9
751 05:19:32.507123 TrainedVREFDQ_A0==77
752 05:19:32.507597 TrainedVREFDQ_A1==77
753 05:19:32.508027 VrefDac_Margin_A0==22
754 05:19:32.512638 DeviceVref_Margin_A0==37
755 05:19:32.513080 VrefDac_Margin_A1==24
756 05:19:32.518253 DeviceVref_Margin_A1==37
757 05:19:32.518706
758 05:19:32.519106 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 05:19:32.519502
760 05:19:32.551909 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
761 05:19:32.552534 2D training succeed
762 05:19:32.557472 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 05:19:32.563120 auto size-- 65535DDR cs0 size: 2048MB
764 05:19:32.563634 DDR cs1 size: 2048MB
765 05:19:32.568640 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 05:19:32.569112 cs0 DataBus test pass
767 05:19:32.574297 cs1 DataBus test pass
768 05:19:32.574751 cs0 AddrBus test pass
769 05:19:32.575165 cs1 AddrBus test pass
770 05:19:32.575562
771 05:19:32.579836 100bdlr_step_size ps== 420
772 05:19:32.580339 result report
773 05:19:32.585427 boot times 0Enable ddr reg access
774 05:19:32.590808 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 05:19:32.604313 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 05:19:33.176395 0.0;M3 CHK:0;cm4_sp_mode 0
777 05:19:33.177031 MVN_1=0x00000000
778 05:19:33.181814 MVN_2=0x00000000
779 05:19:33.187521 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 05:19:33.187822 OPS=0x10
781 05:19:33.188139 ring efuse init
782 05:19:33.188543 chipver efuse init
783 05:19:33.193164 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 05:19:33.198768 [0.018961 Inits done]
785 05:19:33.199239 secure task start!
786 05:19:33.199647 high task start!
787 05:19:33.203372 low task start!
788 05:19:33.203819 run into bl31
789 05:19:33.209987 NOTICE: BL31: v1.3(release):4fc40b1
790 05:19:33.217817 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 05:19:33.218253 NOTICE: BL31: G12A normal boot!
792 05:19:33.243219 NOTICE: BL31: BL33 decompress pass
793 05:19:33.248841 ERROR: Error initializing runtime service opteed_fast
794 05:19:34.481878
795 05:19:34.482506
796 05:19:34.490151 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 05:19:34.490600
798 05:19:34.491003 Model: Libre Computer AML-A311D-CC Alta
799 05:19:34.698757 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 05:19:34.722007 DRAM: 2 GiB (effective 3.8 GiB)
801 05:19:34.865009 Core: 408 devices, 31 uclasses, devicetree: separate
802 05:19:34.870820 WDT: Not starting watchdog@f0d0
803 05:19:34.903127 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 05:19:34.915553 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 05:19:34.920632 ** Bad device specification mmc 0 **
806 05:19:34.930861 Card did not respond to voltage select! : -110
807 05:19:34.938503 ** Bad device specification mmc 0 **
808 05:19:34.938962 Couldn't find partition mmc 0
809 05:19:34.946842 Card did not respond to voltage select! : -110
810 05:19:34.952430 ** Bad device specification mmc 0 **
811 05:19:34.952888 Couldn't find partition mmc 0
812 05:19:34.957430 Error: could not access storage.
813 05:19:35.300076 Net: eth0: ethernet@ff3f0000
814 05:19:35.300696 starting USB...
815 05:19:35.551892 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 05:19:35.552570 Starting the controller
817 05:19:35.558779 USB XHCI 1.10
818 05:19:37.721124 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
819 05:19:37.721769 bl2_stage_init 0x81
820 05:19:37.726781 hw id: 0x0000 - pwm id 0x01
821 05:19:37.727237 bl2_stage_init 0xc1
822 05:19:37.727653 bl2_stage_init 0x02
823 05:19:37.728097
824 05:19:37.732270 L0:00000000
825 05:19:37.732716 L1:20000703
826 05:19:37.733125 L2:00008067
827 05:19:37.733523 L3:14000000
828 05:19:37.733921 B2:00402000
829 05:19:37.738083 B1:e0f83180
830 05:19:37.738524
831 05:19:37.738934 TE: 58150
832 05:19:37.739336
833 05:19:37.743520 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
834 05:19:37.743960
835 05:19:37.744667 Board ID = 1
836 05:19:37.749109 Set A53 clk to 24M
837 05:19:37.749602 Set A73 clk to 24M
838 05:19:37.750047 Set clk81 to 24M
839 05:19:37.754760 A53 clk: 1200 MHz
840 05:19:37.755237 A73 clk: 1200 MHz
841 05:19:37.755679 CLK81: 166.6M
842 05:19:37.756156 smccc: 00012aac
843 05:19:37.760447 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
844 05:19:37.766086 board id: 1
845 05:19:37.771774 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
846 05:19:37.782416 fw parse done
847 05:19:37.788453 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
848 05:19:37.830912 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
849 05:19:37.841747 PIEI prepare done
850 05:19:37.842234 fastboot data load
851 05:19:37.842676 fastboot data verify
852 05:19:37.847410 verify result: 266
853 05:19:37.853021 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
854 05:19:37.853504 LPDDR4 probe
855 05:19:37.853944 ddr clk to 1584MHz
856 05:19:37.860994 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
857 05:19:37.898212
858 05:19:37.898705 dmc_version 0001
859 05:19:37.904899 Check phy result
860 05:19:37.910781 INFO : End of CA training
861 05:19:37.911261 INFO : End of initialization
862 05:19:37.916401 INFO : Training has run successfully!
863 05:19:37.916891 Check phy result
864 05:19:37.922037 INFO : End of initialization
865 05:19:37.922513 INFO : End of read enable training
866 05:19:37.927580 INFO : End of fine write leveling
867 05:19:37.933184 INFO : End of Write leveling coarse delay
868 05:19:37.933666 INFO : Training has run successfully!
869 05:19:37.934103 Check phy result
870 05:19:37.938796 INFO : End of initialization
871 05:19:37.939278 INFO : End of read dq deskew training
872 05:19:37.944382 INFO : End of MPR read delay center optimization
873 05:19:37.950047 INFO : End of write delay center optimization
874 05:19:37.955588 INFO : End of read delay center optimization
875 05:19:37.956102 INFO : End of max read latency training
876 05:19:37.961175 INFO : Training has run successfully!
877 05:19:37.961660 1D training succeed
878 05:19:37.970384 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
879 05:19:38.017934 Check phy result
880 05:19:38.018422 INFO : End of initialization
881 05:19:38.039607 INFO : End of 2D read delay Voltage center optimization
882 05:19:38.059699 INFO : End of 2D read delay Voltage center optimization
883 05:19:38.111610 INFO : End of 2D write delay Voltage center optimization
884 05:19:38.160795 INFO : End of 2D write delay Voltage center optimization
885 05:19:38.166399 INFO : Training has run successfully!
886 05:19:38.166903
887 05:19:38.167369 channel==0
888 05:19:38.172084 RxClkDly_Margin_A0==88 ps 9
889 05:19:38.172586 TxDqDly_Margin_A0==98 ps 10
890 05:19:38.177596 RxClkDly_Margin_A1==88 ps 9
891 05:19:38.178094 TxDqDly_Margin_A1==98 ps 10
892 05:19:38.178585 TrainedVREFDQ_A0==74
893 05:19:38.183217 TrainedVREFDQ_A1==74
894 05:19:38.183787 VrefDac_Margin_A0==25
895 05:19:38.184379 DeviceVref_Margin_A0==40
896 05:19:38.188820 VrefDac_Margin_A1==25
897 05:19:38.189376 DeviceVref_Margin_A1==40
898 05:19:38.189811
899 05:19:38.190241
900 05:19:38.194398 channel==1
901 05:19:38.194887 RxClkDly_Margin_A0==98 ps 10
902 05:19:38.195317 TxDqDly_Margin_A0==98 ps 10
903 05:19:38.200080 RxClkDly_Margin_A1==98 ps 10
904 05:19:38.200568 TxDqDly_Margin_A1==98 ps 10
905 05:19:38.205596 TrainedVREFDQ_A0==77
906 05:19:38.206092 TrainedVREFDQ_A1==78
907 05:19:38.206528 VrefDac_Margin_A0==22
908 05:19:38.211189 DeviceVref_Margin_A0==37
909 05:19:38.211671 VrefDac_Margin_A1==22
910 05:19:38.216784 DeviceVref_Margin_A1==36
911 05:19:38.217271
912 05:19:38.217704 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
913 05:19:38.222389
914 05:19:38.250395 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
915 05:19:38.250909 2D training succeed
916 05:19:38.256074 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
917 05:19:38.261591 auto size-- 65535DDR cs0 size: 2048MB
918 05:19:38.262075 DDR cs1 size: 2048MB
919 05:19:38.267201 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
920 05:19:38.267673 cs0 DataBus test pass
921 05:19:38.272788 cs1 DataBus test pass
922 05:19:38.273256 cs0 AddrBus test pass
923 05:19:38.273678 cs1 AddrBus test pass
924 05:19:38.274099
925 05:19:38.278368 100bdlr_step_size ps== 420
926 05:19:38.278850 result report
927 05:19:38.284072 boot times 0Enable ddr reg access
928 05:19:38.289544 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
929 05:19:38.303036 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
930 05:19:38.874980 0.0;M3 CHK:0;cm4_sp_mode 0
931 05:19:38.875633 MVN_1=0x00000000
932 05:19:38.880442 MVN_2=0x00000000
933 05:19:38.886227 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
934 05:19:38.886738 OPS=0x10
935 05:19:38.887201 ring efuse init
936 05:19:38.887652 chipver efuse init
937 05:19:38.891823 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
938 05:19:38.897403 [0.018961 Inits done]
939 05:19:38.897906 secure task start!
940 05:19:38.898361 high task start!
941 05:19:38.901989 low task start!
942 05:19:38.902483 run into bl31
943 05:19:38.908649 NOTICE: BL31: v1.3(release):4fc40b1
944 05:19:38.916459 NOTICE: BL31: Built : 15:58:17, May 22 2019
945 05:19:38.916970 NOTICE: BL31: G12A normal boot!
946 05:19:38.941899 NOTICE: BL31: BL33 decompress pass
947 05:19:38.947572 ERROR: Error initializing runtime service opteed_fast
948 05:19:40.180570
949 05:19:40.181216
950 05:19:40.188922 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
951 05:19:40.189441
952 05:19:40.189876 Model: Libre Computer AML-A311D-CC Alta
953 05:19:40.397298 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
954 05:19:40.420720 DRAM: 2 GiB (effective 3.8 GiB)
955 05:19:40.563673 Core: 408 devices, 31 uclasses, devicetree: separate
956 05:19:40.569556 WDT: Not starting watchdog@f0d0
957 05:19:40.601811 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
958 05:19:40.614246 Loading Environment from FAT... Card did not respond to voltage select! : -110
959 05:19:40.619246 ** Bad device specification mmc 0 **
960 05:19:40.629565 Card did not respond to voltage select! : -110
961 05:19:40.637218 ** Bad device specification mmc 0 **
962 05:19:40.637722 Couldn't find partition mmc 0
963 05:19:40.645564 Card did not respond to voltage select! : -110
964 05:19:40.651065 ** Bad device specification mmc 0 **
965 05:19:40.651549 Couldn't find partition mmc 0
966 05:19:40.656164 Error: could not access storage.
967 05:19:40.998904 Net: eth0: ethernet@ff3f0000
968 05:19:40.999469 starting USB...
969 05:19:41.250754 Bus usb@ff500000: Register 3000140 NbrPorts 3
970 05:19:41.251309 Starting the controller
971 05:19:41.257733 USB XHCI 1.10
972 05:19:43.121246 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
973 05:19:43.121678 bl2_stage_init 0x81
974 05:19:43.126834 hw id: 0x0000 - pwm id 0x01
975 05:19:43.127133 bl2_stage_init 0xc1
976 05:19:43.127350 bl2_stage_init 0x02
977 05:19:43.127556
978 05:19:43.132445 L0:00000000
979 05:19:43.132833 L1:20000703
980 05:19:43.133154 L2:00008067
981 05:19:43.133461 L3:14000000
982 05:19:43.133765 B2:00402000
983 05:19:43.135185 B1:e0f83180
984 05:19:43.135559
985 05:19:43.135872 TE: 58150
986 05:19:43.136141
987 05:19:43.146345 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
988 05:19:43.146630
989 05:19:43.146847 Board ID = 1
990 05:19:43.147049 Set A53 clk to 24M
991 05:19:43.147248 Set A73 clk to 24M
992 05:19:43.151877 Set clk81 to 24M
993 05:19:43.152276 A53 clk: 1200 MHz
994 05:19:43.152598 A73 clk: 1200 MHz
995 05:19:43.157479 CLK81: 166.6M
996 05:19:43.157857 smccc: 00012aab
997 05:19:43.163080 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
998 05:19:43.163460 board id: 1
999 05:19:43.171896 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1000 05:19:43.182421 fw parse done
1001 05:19:43.188553 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1002 05:19:43.230921 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 05:19:43.241802 PIEI prepare done
1004 05:19:43.242283 fastboot data load
1005 05:19:43.242696 fastboot data verify
1006 05:19:43.247362 verify result: 266
1007 05:19:43.252928 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1008 05:19:43.253372 LPDDR4 probe
1009 05:19:43.253767 ddr clk to 1584MHz
1010 05:19:43.260946 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1011 05:19:43.298260
1012 05:19:43.298747 dmc_version 0001
1013 05:19:43.304897 Check phy result
1014 05:19:43.310942 INFO : End of CA training
1015 05:19:43.311448 INFO : End of initialization
1016 05:19:43.316350 INFO : Training has run successfully!
1017 05:19:43.316845 Check phy result
1018 05:19:43.321939 INFO : End of initialization
1019 05:19:43.322393 INFO : End of read enable training
1020 05:19:43.325248 INFO : End of fine write leveling
1021 05:19:43.330758 INFO : End of Write leveling coarse delay
1022 05:19:43.336392 INFO : Training has run successfully!
1023 05:19:43.336845 Check phy result
1024 05:19:43.337253 INFO : End of initialization
1025 05:19:43.341988 INFO : End of read dq deskew training
1026 05:19:43.345372 INFO : End of MPR read delay center optimization
1027 05:19:43.350965 INFO : End of write delay center optimization
1028 05:19:43.356578 INFO : End of read delay center optimization
1029 05:19:43.357027 INFO : End of max read latency training
1030 05:19:43.362132 INFO : Training has run successfully!
1031 05:19:43.362583 1D training succeed
1032 05:19:43.370400 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1033 05:19:43.418060 Check phy result
1034 05:19:43.418636 INFO : End of initialization
1035 05:19:43.439785 INFO : End of 2D read delay Voltage center optimization
1036 05:19:43.459962 INFO : End of 2D read delay Voltage center optimization
1037 05:19:43.512085 INFO : End of 2D write delay Voltage center optimization
1038 05:19:43.561529 INFO : End of 2D write delay Voltage center optimization
1039 05:19:43.567033 INFO : Training has run successfully!
1040 05:19:43.567523
1041 05:19:43.567944 channel==0
1042 05:19:43.572613 RxClkDly_Margin_A0==88 ps 9
1043 05:19:43.573077 TxDqDly_Margin_A0==98 ps 10
1044 05:19:43.578234 RxClkDly_Margin_A1==88 ps 9
1045 05:19:43.578686 TxDqDly_Margin_A1==88 ps 9
1046 05:19:43.579105 TrainedVREFDQ_A0==74
1047 05:19:43.583926 TrainedVREFDQ_A1==74
1048 05:19:43.584422 VrefDac_Margin_A0==25
1049 05:19:43.584839 DeviceVref_Margin_A0==40
1050 05:19:43.589425 VrefDac_Margin_A1==25
1051 05:19:43.589880 DeviceVref_Margin_A1==40
1052 05:19:43.590292
1053 05:19:43.590701
1054 05:19:43.591109 channel==1
1055 05:19:43.594996 RxClkDly_Margin_A0==98 ps 10
1056 05:19:43.595452 TxDqDly_Margin_A0==88 ps 9
1057 05:19:43.600595 RxClkDly_Margin_A1==88 ps 9
1058 05:19:43.601046 TxDqDly_Margin_A1==88 ps 9
1059 05:19:43.606128 TrainedVREFDQ_A0==77
1060 05:19:43.606587 TrainedVREFDQ_A1==77
1061 05:19:43.607003 VrefDac_Margin_A0==22
1062 05:19:43.611946 DeviceVref_Margin_A0==37
1063 05:19:43.612429 VrefDac_Margin_A1==24
1064 05:19:43.617403 DeviceVref_Margin_A1==37
1065 05:19:43.617855
1066 05:19:43.618269 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1067 05:19:43.618675
1068 05:19:43.650877 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000016 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1069 05:19:43.651361 2D training succeed
1070 05:19:43.656484 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1071 05:19:43.662071 auto size-- 65535DDR cs0 size: 2048MB
1072 05:19:43.662536 DDR cs1 size: 2048MB
1073 05:19:43.667739 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1074 05:19:43.668232 cs0 DataBus test pass
1075 05:19:43.673268 cs1 DataBus test pass
1076 05:19:43.673721 cs0 AddrBus test pass
1077 05:19:43.674127 cs1 AddrBus test pass
1078 05:19:43.674524
1079 05:19:43.678876 100bdlr_step_size ps== 420
1080 05:19:43.679341 result report
1081 05:19:43.684480 boot times 0Enable ddr reg access
1082 05:19:43.689691 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1083 05:19:43.703142 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1084 05:19:44.277081 0.0;M3 CHK:0;cm4_sp_mode 0
1085 05:19:44.277704 MVN_1=0x00000000
1086 05:19:44.282358 MVN_2=0x00000000
1087 05:19:44.288074 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1088 05:19:44.288534 OPS=0x10
1089 05:19:44.288947 ring efuse init
1090 05:19:44.289351 chipver efuse init
1091 05:19:44.296376 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1092 05:19:44.296847 [0.018961 Inits done]
1093 05:19:44.297262 secure task start!
1094 05:19:44.303904 high task start!
1095 05:19:44.304392 low task start!
1096 05:19:44.304806 run into bl31
1097 05:19:44.310567 NOTICE: BL31: v1.3(release):4fc40b1
1098 05:19:44.318390 NOTICE: BL31: Built : 15:58:17, May 22 2019
1099 05:19:44.318866 NOTICE: BL31: G12A normal boot!
1100 05:19:44.343742 NOTICE: BL31: BL33 decompress pass
1101 05:19:44.349338 ERROR: Error initializing runtime service opteed_fast
1102 05:19:45.582358
1103 05:19:45.582982
1104 05:19:45.590730 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1105 05:19:45.591142
1106 05:19:45.591367 Model: Libre Computer AML-A311D-CC Alta
1107 05:19:45.799264 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1108 05:19:45.822645 DRAM: 2 GiB (effective 3.8 GiB)
1109 05:19:45.965591 Core: 408 devices, 31 uclasses, devicetree: separate
1110 05:19:45.971416 WDT: Not starting watchdog@f0d0
1111 05:19:46.003693 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1112 05:19:46.016192 Loading Environment from FAT... Card did not respond to voltage select! : -110
1113 05:19:46.021066 ** Bad device specification mmc 0 **
1114 05:19:46.031392 Card did not respond to voltage select! : -110
1115 05:19:46.039083 ** Bad device specification mmc 0 **
1116 05:19:46.039639 Couldn't find partition mmc 0
1117 05:19:46.047367 Card did not respond to voltage select! : -110
1118 05:19:46.052863 ** Bad device specification mmc 0 **
1119 05:19:46.053414 Couldn't find partition mmc 0
1120 05:19:46.057930 Error: could not access storage.
1121 05:19:46.400605 Net: eth0: ethernet@ff3f0000
1122 05:19:46.401296 starting USB...
1123 05:19:46.652391 Bus usb@ff500000: Register 3000140 NbrPorts 3
1124 05:19:46.653038 Starting the controller
1125 05:19:46.659132 USB XHCI 1.10
1126 05:19:48.213292 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1127 05:19:48.221515 scanning usb for storage devices... 0 Storage Device(s) found
1129 05:19:48.273301 Hit any key to stop autoboot: 1
1130 05:19:48.274131 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1131 05:19:48.274762 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1132 05:19:48.275290 Setting prompt string to ['=>']
1133 05:19:48.275812 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1134 05:19:48.288871 0
1135 05:19:48.289780 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1136 05:19:48.290313 Sending with 10 millisecond of delay
1138 05:19:49.425168 => setenv autoload no
1139 05:19:49.436049 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1140 05:19:49.441446 setenv autoload no
1141 05:19:49.442245 Sending with 10 millisecond of delay
1143 05:19:51.239259 => setenv initrd_high 0xffffffff
1144 05:19:51.250093 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1145 05:19:51.250990 setenv initrd_high 0xffffffff
1146 05:19:51.251751 Sending with 10 millisecond of delay
1148 05:19:52.868268 => setenv fdt_high 0xffffffff
1149 05:19:52.879091 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1150 05:19:52.879964 setenv fdt_high 0xffffffff
1151 05:19:52.880770 Sending with 10 millisecond of delay
1153 05:19:53.172656 => dhcp
1154 05:19:53.183427 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1155 05:19:53.184359 dhcp
1156 05:19:53.184848 Speed: 1000, full duplex
1157 05:19:53.185307 BOOTP broadcast 1
1158 05:19:53.193633 DHCP client bound to address 192.168.6.27 (10 ms)
1159 05:19:53.194380 Sending with 10 millisecond of delay
1161 05:19:54.870987 => setenv serverip 192.168.6.2
1162 05:19:54.881849 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1163 05:19:54.882814 setenv serverip 192.168.6.2
1164 05:19:54.883553 Sending with 10 millisecond of delay
1166 05:19:58.607773 => tftpboot 0x01080000 951357/tftp-deploy-dwn9kkvn/kernel/uImage
1167 05:19:58.618978 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1168 05:19:58.619924 tftpboot 0x01080000 951357/tftp-deploy-dwn9kkvn/kernel/uImage
1169 05:19:58.620490 Speed: 1000, full duplex
1170 05:19:58.620959 Using ethernet@ff3f0000 device
1171 05:19:58.621519 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1172 05:19:58.626901 Filename '951357/tftp-deploy-dwn9kkvn/kernel/uImage'.
1173 05:19:58.630875 Load address: 0x1080000
1174 05:20:01.447322 Loading: *################################################## 43.6 MiB
1175 05:20:01.447952 15.5 MiB/s
1176 05:20:01.448443 done
1177 05:20:01.451715 Bytes transferred = 45713984 (2b98a40 hex)
1178 05:20:01.452533 Sending with 10 millisecond of delay
1180 05:20:06.139791 => tftpboot 0x08000000 951357/tftp-deploy-dwn9kkvn/ramdisk/ramdisk.cpio.gz.uboot
1181 05:20:06.150625 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1182 05:20:06.151433 tftpboot 0x08000000 951357/tftp-deploy-dwn9kkvn/ramdisk/ramdisk.cpio.gz.uboot
1183 05:20:06.151887 Speed: 1000, full duplex
1184 05:20:06.152351 Using ethernet@ff3f0000 device
1185 05:20:06.153086 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1186 05:20:06.164999 Filename '951357/tftp-deploy-dwn9kkvn/ramdisk/ramdisk.cpio.gz.uboot'.
1187 05:20:06.165468 Load address: 0x8000000
1188 05:20:12.827692 Loading: *######################T ############################ 22.3 MiB
1189 05:20:12.828372 3.4 MiB/s
1190 05:20:12.828738 done
1191 05:20:12.832226 Bytes transferred = 23432326 (1658c86 hex)
1192 05:20:12.832981 Sending with 10 millisecond of delay
1194 05:20:18.003293 => tftpboot 0x01070000 951357/tftp-deploy-dwn9kkvn/dtb/meson-g12b-a311d-libretech-cc.dtb
1195 05:20:18.014162 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:53)
1196 05:20:18.015185 tftpboot 0x01070000 951357/tftp-deploy-dwn9kkvn/dtb/meson-g12b-a311d-libretech-cc.dtb
1197 05:20:18.015725 Speed: 1000, full duplex
1198 05:20:18.016327 Using ethernet@ff3f0000 device
1199 05:20:18.019059 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1200 05:20:18.026617 Filename '951357/tftp-deploy-dwn9kkvn/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1201 05:20:18.036883 Load address: 0x1070000
1202 05:20:18.046849 Loading: *################################################## 53.4 KiB
1203 05:20:18.047353 3.1 MiB/s
1204 05:20:18.047799 done
1205 05:20:18.053258 Bytes transferred = 54703 (d5af hex)
1206 05:20:18.054034 Sending with 10 millisecond of delay
1208 05:20:31.355330 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/951357/extract-nfsrootfs-6yd7u1kw,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1209 05:20:31.366375 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:40)
1210 05:20:31.367457 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/951357/extract-nfsrootfs-6yd7u1kw,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1211 05:20:31.368348 Sending with 10 millisecond of delay
1213 05:20:33.708067 => bootm 0x01080000 0x08000000 0x01070000
1214 05:20:33.718990 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1215 05:20:33.719587 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:38)
1216 05:20:33.720744 bootm 0x01080000 0x08000000 0x01070000
1217 05:20:33.721276 ## Booting kernel from Legacy Image at 01080000 ...
1218 05:20:33.723836 Image Name:
1219 05:20:33.729392 Image Type: AArch64 Linux Kernel Image (uncompressed)
1220 05:20:33.729993 Data Size: 45713920 Bytes = 43.6 MiB
1221 05:20:33.734897 Load Address: 01080000
1222 05:20:33.735515 Entry Point: 01080000
1223 05:20:33.929983 Verifying Checksum ... OK
1224 05:20:33.930705 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1225 05:20:33.935494 Image Name:
1226 05:20:33.940986 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1227 05:20:33.941583 Data Size: 23432262 Bytes = 22.3 MiB
1228 05:20:33.946556 Load Address: 00000000
1229 05:20:33.947097 Entry Point: 00000000
1230 05:20:34.048722 Verifying Checksum ... OK
1231 05:20:34.049299 ## Flattened Device Tree blob at 01070000
1232 05:20:34.054326 Booting using the fdt blob at 0x1070000
1233 05:20:34.054846 Working FDT set to 1070000
1234 05:20:34.058717 Loading Kernel Image
1235 05:20:34.209370 Loading Ramdisk to 7e9a7000, end 7ffffc46 ... OK
1236 05:20:34.217709 Loading Device Tree to 000000007e996000, end 000000007e9a65ae ... OK
1237 05:20:34.218212 Working FDT set to 7e996000
1238 05:20:34.218617
1239 05:20:34.219489 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1240 05:20:34.220122 start: 2.4.4 auto-login-action (timeout 00:03:37) [common]
1241 05:20:34.220590 Setting prompt string to ['Linux version [0-9]']
1242 05:20:34.221215 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1243 05:20:34.221704 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1244 05:20:34.222704 Starting kernel ...
1245 05:20:34.223162
1246 05:20:34.257954 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1247 05:20:34.258990 start: 2.4.4.1 login-action (timeout 00:03:37) [common]
1248 05:20:34.259528 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1249 05:20:34.260029 Setting prompt string to []
1250 05:20:34.260532 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1251 05:20:34.260983 Using line separator: #'\n'#
1252 05:20:34.261385 No login prompt set.
1253 05:20:34.261811 Parsing kernel messages
1254 05:20:34.262206 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1255 05:20:34.262960 [login-action] Waiting for messages, (timeout 00:03:37)
1256 05:20:34.263446 Waiting using forced prompt support (timeout 00:01:49)
1257 05:20:34.278078 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j366286-arm64-gcc-12-defconfig-jzlrg) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Nov 7 02:30:35 UTC 2024
1258 05:20:34.278656 [ 0.000000] KASLR disabled due to lack of seed
1259 05:20:34.283635 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1260 05:20:34.289185 [ 0.000000] efi: UEFI not found.
1261 05:20:34.294675 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1262 05:20:34.305619 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1263 05:20:34.311085 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1264 05:20:34.322072 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1265 05:20:34.333076 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1266 05:20:34.344154 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1267 05:20:34.349747 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1268 05:20:34.355199 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1269 05:20:34.360756 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1270 05:20:34.366254 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1271 05:20:34.371893 [ 0.000000] Zone ranges:
1272 05:20:34.377307 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1273 05:20:34.377809 [ 0.000000] DMA32 empty
1274 05:20:34.382908 [ 0.000000] Normal empty
1275 05:20:34.388345 [ 0.000000] Movable zone start for each node
1276 05:20:34.388841 [ 0.000000] Early memory node ranges
1277 05:20:34.393880 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1278 05:20:34.399382 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1279 05:20:34.410381 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1280 05:20:34.415495 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1281 05:20:34.439713 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1282 05:20:34.445275 [ 0.000000] psci: probing for conduit method from DT.
1283 05:20:34.445776 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1284 05:20:34.450871 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1285 05:20:34.456296 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1286 05:20:34.461904 [ 0.000000] psci: SMC Calling Convention v1.1
1287 05:20:34.467374 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1288 05:20:34.472904 [ 0.000000] Detected VIPT I-cache on CPU0
1289 05:20:34.478389 [ 0.000000] CPU features: detected: ARM erratum 845719
1290 05:20:34.483935 [ 0.000000] alternatives: applying boot alternatives
1291 05:20:34.500438 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/951357/extract-nfsrootfs-6yd7u1kw,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1292 05:20:34.511496 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1293 05:20:34.517050 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1294 05:20:34.522556 <6>[ 0.000000] Fallback order for Node 0: 0
1295 05:20:34.528130 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1296 05:20:34.533636 <6>[ 0.000000] Policy zone: DMA
1297 05:20:34.539147 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1298 05:20:34.544638 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1299 05:20:34.550201 <6>[ 0.000000] software IO TLB: area num 8.
1300 05:20:34.559157 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1301 05:20:34.605905 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1302 05:20:34.611412 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1303 05:20:34.614943 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1304 05:20:34.620423 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1305 05:20:34.625990 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1306 05:20:34.631479 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1307 05:20:34.642455 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1308 05:20:34.648057 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1309 05:20:34.653546 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1310 05:20:34.664537 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1311 05:20:34.670092 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1312 05:20:34.675631 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1313 05:20:34.681131 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1314 05:20:34.687523 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1315 05:20:34.700192 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1316 05:20:34.711169 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1317 05:20:34.716830 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1318 05:20:34.722262 <6>[ 0.008795] Console: colour dummy device 80x25
1319 05:20:34.733245 <6>[ 0.012938] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1320 05:20:34.738981 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1321 05:20:34.744369 <6>[ 0.028189] LSM: initializing lsm=capability
1322 05:20:34.749958 <6>[ 0.032727] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1323 05:20:34.755388 <6>[ 0.040210] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1324 05:20:34.760945 <6>[ 0.052299] rcu: Hierarchical SRCU implementation.
1325 05:20:34.766452 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1326 05:20:34.777410 <6>[ 0.058880] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1327 05:20:34.785928 <6>[ 0.071578] EFI services will not be available.
1328 05:20:34.786447 <6>[ 0.075225] smp: Bringing up secondary CPUs ...
1329 05:20:34.798179 <6>[ 0.077132] Detected VIPT I-cache on CPU1
1330 05:20:34.803665 <6>[ 0.077250] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1331 05:20:34.809186 <6>[ 0.078582] CPU features: detected: Spectre-v2
1332 05:20:34.818190 <6>[ 0.078596] CPU features: detected: Spectre-v4
1333 05:20:34.818716 <6>[ 0.078601] CPU features: detected: Spectre-BHB
1334 05:20:34.823767 <6>[ 0.078607] CPU features: detected: ARM erratum 858921
1335 05:20:34.829304 <6>[ 0.078615] Detected VIPT I-cache on CPU2
1336 05:20:34.834834 <6>[ 0.078688] arch_timer: Enabling local workaround for ARM erratum 858921
1337 05:20:34.840332 <6>[ 0.078705] arch_timer: CPU2: Trapping CNTVCT access
1338 05:20:34.851307 <6>[ 0.078715] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1339 05:20:34.851832 <6>[ 0.083572] Detected VIPT I-cache on CPU3
1340 05:20:34.862335 <6>[ 0.083617] arch_timer: Enabling local workaround for ARM erratum 858921
1341 05:20:34.862850 <6>[ 0.083627] arch_timer: CPU3: Trapping CNTVCT access
1342 05:20:34.873366 <6>[ 0.083634] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1343 05:20:34.873872 <6>[ 0.087610] Detected VIPT I-cache on CPU4
1344 05:20:34.884403 <6>[ 0.087656] arch_timer: Enabling local workaround for ARM erratum 858921
1345 05:20:34.890047 <6>[ 0.087666] arch_timer: CPU4: Trapping CNTVCT access
1346 05:20:34.895507 <6>[ 0.087673] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1347 05:20:34.901010 <6>[ 0.091606] Detected VIPT I-cache on CPU5
1348 05:20:34.906552 <6>[ 0.091653] arch_timer: Enabling local workaround for ARM erratum 858921
1349 05:20:34.912085 <6>[ 0.091663] arch_timer: CPU5: Trapping CNTVCT access
1350 05:20:34.917610 <6>[ 0.091670] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1351 05:20:34.923104 <6>[ 0.091782] smp: Brought up 1 node, 6 CPUs
1352 05:20:34.928622 <6>[ 0.213012] SMP: Total of 6 processors activated.
1353 05:20:34.929113 <6>[ 0.217917] CPU: All CPU(s) started at EL2
1354 05:20:34.934130 <6>[ 0.222267] CPU features: detected: 32-bit EL0 Support
1355 05:20:34.939660 <6>[ 0.227579] CPU features: detected: 32-bit EL1 Support
1356 05:20:34.945190 <6>[ 0.232924] CPU features: detected: CRC32 instructions
1357 05:20:34.950703 <6>[ 0.238329] alternatives: applying system-wide alternatives
1358 05:20:34.967199 <6>[ 0.245517] Memory: 3557436K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187796K reserved, 262144K cma-reserved)
1359 05:20:34.974170 <6>[ 0.259859] devtmpfs: initialized
1360 05:20:34.985125 <6>[ 0.269023] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1361 05:20:34.990763 <6>[ 0.273376] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1362 05:20:34.996277 <6>[ 0.284171] 21392 pages in range for non-PLT usage
1363 05:20:35.001770 <6>[ 0.284180] 512912 pages in range for PLT usage
1364 05:20:35.007271 <6>[ 0.285731] pinctrl core: initialized pinctrl subsystem
1365 05:20:35.007773 <6>[ 0.297813] DMI not present or invalid.
1366 05:20:35.012866 <6>[ 0.302093] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1367 05:20:35.023805 <6>[ 0.306840] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1368 05:20:35.029367 <6>[ 0.313615] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1369 05:20:35.040340 <6>[ 0.321718] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1370 05:20:35.045994 <6>[ 0.329208] audit: initializing netlink subsys (disabled)
1371 05:20:35.051440 <5>[ 0.334935] audit: type=2000 audit(0.256:1): state=initialized audit_enabled=0 res=1
1372 05:20:35.056992 <6>[ 0.336349] thermal_sys: Registered thermal governor 'step_wise'
1373 05:20:35.062476 <6>[ 0.342714] thermal_sys: Registered thermal governor 'power_allocator'
1374 05:20:35.068016 <6>[ 0.348975] cpuidle: using governor menu
1375 05:20:35.073536 <6>[ 0.360004] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1376 05:20:35.079037 <6>[ 0.366887] ASID allocator initialised with 65536 entries
1377 05:20:35.087279 <6>[ 0.374425] Serial: AMBA PL011 UART driver
1378 05:20:35.097036 <6>[ 0.384977] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1379 05:20:35.112358 <6>[ 0.400502] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1380 05:20:35.123345 <6>[ 0.403172] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1381 05:20:35.129014 <6>[ 0.416333] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1382 05:20:35.134440 <6>[ 0.419544] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1383 05:20:35.145424 <6>[ 0.427971] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1384 05:20:35.151034 <6>[ 0.435594] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1385 05:20:35.162002 <6>[ 0.449183] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1386 05:20:35.167555 <6>[ 0.451412] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1387 05:20:35.173092 <6>[ 0.457893] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1388 05:20:35.178616 <6>[ 0.464871] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1389 05:20:35.189578 <6>[ 0.471340] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1390 05:20:35.195141 <6>[ 0.478325] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1391 05:20:35.200670 <6>[ 0.484795] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1392 05:20:35.206162 <6>[ 0.491779] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1393 05:20:35.211695 <6>[ 0.499790] ACPI: Interpreter disabled.
1394 05:20:35.217238 <6>[ 0.505244] iommu: Default domain type: Translated
1395 05:20:35.222782 <6>[ 0.507313] iommu: DMA domain TLB invalidation policy: strict mode
1396 05:20:35.228398 <5>[ 0.513995] SCSI subsystem initialized
1397 05:20:35.233754 <6>[ 0.517888] usbcore: registered new interface driver usbfs
1398 05:20:35.239242 <6>[ 0.523370] usbcore: registered new interface driver hub
1399 05:20:35.244828 <6>[ 0.528895] usbcore: registered new device driver usb
1400 05:20:35.250279 <6>[ 0.535148] pps_core: LinuxPPS API ver. 1 registered
1401 05:20:35.255890 <6>[ 0.539306] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1402 05:20:35.261375 <6>[ 0.548626] PTP clock support registered
1403 05:20:35.266970 <6>[ 0.552866] EDAC MC: Ver: 3.0.0
1404 05:20:35.272363 <6>[ 0.556513] scmi_core: SCMI protocol bus registered
1405 05:20:35.272840 <6>[ 0.562134] FPGA manager framework
1406 05:20:35.277962 <6>[ 0.564893] Advanced Linux Sound Architecture Driver Initialized.
1407 05:20:35.283380 <6>[ 0.571865] vgaarb: loaded
1408 05:20:35.288978 <6>[ 0.574370] clocksource: Switched to clocksource arch_sys_counter
1409 05:20:35.294480 <5>[ 0.580536] VFS: Disk quotas dquot_6.6.0
1410 05:20:35.300027 <6>[ 0.584522] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1411 05:20:35.305502 <6>[ 0.591884] pnp: PnP ACPI: disabled
1412 05:20:35.311012 <6>[ 0.600266] NET: Registered PF_INET protocol family
1413 05:20:35.316514 <6>[ 0.600556] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1414 05:20:35.327596 <6>[ 0.610721] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1415 05:20:35.333118 <6>[ 0.616722] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1416 05:20:35.344135 <6>[ 0.624618] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1417 05:20:35.349669 <6>[ 0.632857] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1418 05:20:35.355216 <6>[ 0.640650] TCP: Hash tables configured (established 32768 bind 32768)
1419 05:20:35.360756 <6>[ 0.647133] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1420 05:20:35.371711 <6>[ 0.653982] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1421 05:20:35.377374 <6>[ 0.661396] NET: Registered PF_UNIX/PF_LOCAL protocol family
1422 05:20:35.382920 <6>[ 0.667483] RPC: Registered named UNIX socket transport module.
1423 05:20:35.388347 <6>[ 0.673264] RPC: Registered udp transport module.
1424 05:20:35.393914 <6>[ 0.678169] RPC: Registered tcp transport module.
1425 05:20:35.399417 <6>[ 0.683084] RPC: Registered tcp-with-tls transport module.
1426 05:20:35.405041 <6>[ 0.688777] RPC: Registered tcp NFSv4.1 backchannel transport module.
1427 05:20:35.410783 <6>[ 0.695425] PCI: CLS 0 bytes, default 64
1428 05:20:35.411272 <6>[ 0.699744] Unpacking initramfs...
1429 05:20:35.416312 <6>[ 0.709079] kvm [1]: nv: 554 coarse grained trap handlers
1430 05:20:35.421811 <6>[ 0.709381] kvm [1]: IPA Size Limit: 40 bits
1431 05:20:35.427321 <6>[ 0.715063] kvm [1]: vgic interrupt IRQ9
1432 05:20:35.432901 <6>[ 0.717753] kvm [1]: Hyp nVHE mode initialized successfully
1433 05:20:35.438361 <5>[ 0.724914] Initialise system trusted keyrings
1434 05:20:35.443917 <6>[ 0.728361] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1435 05:20:35.449424 <6>[ 0.735081] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1436 05:20:35.454892 <5>[ 0.741092] NFS: Registering the id_resolver key type
1437 05:20:35.460442 <5>[ 0.746143] Key type id_resolver registered
1438 05:20:35.466059 <5>[ 0.750509] Key type id_legacy registered
1439 05:20:35.471486 <6>[ 0.754762] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1440 05:20:35.477062 <6>[ 0.761636] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1441 05:20:35.484404 <6>[ 0.769413] 9p: Installing v9fs 9p2000 file system support
1442 05:20:35.522513 <5>[ 0.816134] Key type asymmetric registered
1443 05:20:35.528087 <5>[ 0.816179] Asymmetric key parser 'x509' registered
1444 05:20:35.537040 <6>[ 0.820039] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1445 05:20:35.542606 <6>[ 0.827560] io scheduler mq-deadline registered
1446 05:20:35.548132 <6>[ 0.832300] io scheduler kyber registered
1447 05:20:35.548641 <6>[ 0.836564] io scheduler bfq registered
1448 05:20:35.556537 <6>[ 0.842459] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1449 05:20:35.580451 <6>[ 0.870404] ledtrig-cpu: registered to indicate activity on CPUs
1450 05:20:35.613155 <6>[ 0.901875] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1451 05:20:35.633032 <6>[ 0.915541] Serial: 8250/16550 driver, 4 ports�<6>[ 0.920191] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1452 05:20:35.638623 <6>[ 0.929823] printk: legacy console [ttyAML0] enabled
1453 05:20:35.644193 <6>[ 0.929823] printk: legacy console [ttyAML0] enabled
1454 05:20:35.649710 <6>[ 0.934635] printk: legacy bootconsole [meson0] disabled
1455 05:20:35.655258 <6>[ 0.934635] printk: legacy bootconsole [meson0] disabled
1456 05:20:35.660785 <6>[ 0.947156] msm_serial: driver initialized
1457 05:20:35.666343 <6>[ 0.950608] SuperH (H)SCI(F) driver initialized
1458 05:20:35.666833 <6>[ 0.955099] STM32 USART driver initialized
1459 05:20:35.671945 <5>[ 0.961318] random: crng init done
1460 05:20:35.679082 <6>[ 0.967040] loop: module loaded
1461 05:20:35.679567 <6>[ 0.968335] megasas: 07.727.03.00-rc1
1462 05:20:35.684510 <6>[ 0.977196] tun: Universal TUN/TAP device driver, 1.6
1463 05:20:35.690074 <6>[ 0.978407] thunder_xcv, ver 1.0
1464 05:20:35.695596 <6>[ 0.980363] thunder_bgx, ver 1.0
1465 05:20:35.696113 <6>[ 0.983837] nicpf, ver 1.0
1466 05:20:35.701159 <6>[ 0.988392] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1467 05:20:35.706691 <6>[ 0.994218] hns3: Copyright (c) 2017 Huawei Corporation.
1468 05:20:35.712273 <6>[ 0.999806] hclge is initializing
1469 05:20:35.717783 <6>[ 1.003350] e1000: Intel(R) PRO/1000 Network Driver
1470 05:20:35.723322 <6>[ 1.008426] e1000: Copyright (c) 1999-2006 Intel Corporation.
1471 05:20:35.728959 <6>[ 1.014450] e1000e: Intel(R) PRO/1000 Network Driver
1472 05:20:35.734407 <6>[ 1.019607] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1473 05:20:35.740087 <6>[ 1.025792] igb: Intel(R) Gigabit Ethernet Network Driver
1474 05:20:35.745506 <6>[ 1.031392] igb: Copyright (c) 2007-2014 Intel Corporation.
1475 05:20:35.751072 <6>[ 1.037237] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1476 05:20:35.756586 <6>[ 1.043711] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1477 05:20:35.762169 <6>[ 1.050483] sky2: driver version 1.30
1478 05:20:35.767696 <6>[ 1.055552] VFIO - User Level meta-driver version: 0.3
1479 05:20:35.773225 <6>[ 1.063017] usbcore: registered new interface driver usb-storage
1480 05:20:35.779346 <6>[ 1.069283] i2c_dev: i2c /dev entries driver
1481 05:20:35.792189 <6>[ 1.080286] sdhci: Secure Digital Host Controller Interface driver
1482 05:20:35.792715 <6>[ 1.081089] sdhci: Copyright(c) Pierre Ossman
1483 05:20:35.803235 <6>[ 1.086871] Synopsys Designware Multimedia Card Interface Driver
1484 05:20:35.808849 <6>[ 1.093321] sdhci-pltfm: SDHCI platform and OF driver helper
1485 05:20:35.809341 <6>[ 1.100980] meson-sm: secure-monitor enabled
1486 05:20:35.821664 <6>[ 1.103594] usbcore: registered new interface driver usbhid
1487 05:20:35.822177 <6>[ 1.108154] usbhid: USB HID core driver
1488 05:20:35.829287 <6>[ 1.122919] NET: Registered PF_PACKET protocol family
1489 05:20:35.834820 <6>[ 1.123007] 9pnet: Installing 9P2000 support
1490 05:20:35.841866 <5>[ 1.127167] Key type dns_resolver registered
1491 05:20:35.847422 <6>[ 1.138714] registered taskstats version 1
1492 05:20:35.852952 <5>[ 1.138872] Loading compiled-in X.509 certificates
1493 05:20:35.856541 <6>[ 1.147549] Demotion targets for Node 0: null
1494 05:20:35.897109 <6>[ 1.190690] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1495 05:20:35.902594 <6>[ 1.190735] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1496 05:20:35.913650 <4>[ 1.200885] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1497 05:20:35.919237 <4>[ 1.203515] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1498 05:20:35.924779 <6>[ 1.211077] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1499 05:20:35.930338 <6>[ 1.220338] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1500 05:20:35.941376 <6>[ 1.223781] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1501 05:20:35.952484 <6>[ 1.231759] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1502 05:20:35.958101 <6>[ 1.241294] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1503 05:20:35.963598 <6>[ 1.247516] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1504 05:20:35.969146 <6>[ 1.253141] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1505 05:20:35.974701 <6>[ 1.261026] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1506 05:20:35.980265 <6>[ 1.268313] hub 1-0:1.0: USB hub found
1507 05:20:35.985790 <6>[ 1.271795] hub 1-0:1.0: 2 ports detected
1508 05:20:35.991365 <6>[ 1.277859] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1509 05:20:35.996886 <6>[ 1.284753] hub 2-0:1.0: USB hub found
1510 05:20:36.001975 <6>[ 1.288340] hub 2-0:1.0: 1 port detected
1511 05:20:36.023090 <6>[ 1.314122] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1512 05:20:36.041703 <6>[ 1.332040] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1513 05:20:36.076796 <6>[ 1.366816] Trying to probe devices needed for running init ...
1514 05:20:36.237057 <6>[ 1.526406] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1515 05:20:36.377569 <6>[ 1.665681] mmc0: new ultra high speed SDR104 SDXC card at address e624
1516 05:20:36.383191 <6>[ 1.667686] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1517 05:20:36.383686 <6>[ 1.670792] Freeing initrd memory: 22880K
1518 05:20:36.387042 <6>[ 1.673132] mmcblk0: p1
1519 05:20:36.422541 <6>[ 1.716137] hub 1-1:1.0: USB hub found
1520 05:20:36.428289 <6>[ 1.716442] hub 1-1:1.0: 4 ports detected
1521 05:20:36.493217 <6>[ 1.782509] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1522 05:20:36.535288 <6>[ 1.828789] hub 2-1:1.0: USB hub found
1523 05:20:36.540921 <6>[ 1.829610] hub 2-1:1.0: 4 ports detected
1524 05:20:48.352963 <6>[ 13.646436] clk: Disabling unused clocks
1525 05:20:48.358347 <6>[ 13.646605] PM: genpd: Disabling unused power domains
1526 05:20:48.366790 <6>[ 13.650291] ALSA device list:
1527 05:20:48.367415 <6>[ 13.653501] No soundcards found.
1528 05:20:48.372785 <6>[ 13.665658] Freeing unused kernel memory: 10432K
1529 05:20:48.383347 <6>[ 13.665766] Run /init as init process
1530 05:20:48.383830 Loading, please wait...
1531 05:20:48.420960 Starting systemd-udevd version 252.22-1~deb12u1
1532 05:20:48.857275 <6>[ 14.148801] mc: Linux media interface: v0.10
1533 05:20:48.871977 <6>[ 14.160165] videodev: Linux video capture interface: v2.00
1534 05:20:48.877590 <4>[ 14.162470] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1535 05:20:48.886048 <3>[ 14.164386] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1536 05:20:48.906802 <6>[ 14.194883] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1537 05:20:48.912318 <6>[ 14.196130] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1538 05:20:48.915739 <6>[ 14.202565] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1539 05:20:48.926821 <6>[ 14.208811] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1540 05:20:48.927392 <6>[ 14.214070] meson-vrtc ff8000a8.rtc: registered as rtc0
1541 05:20:48.937812 <6>[ 14.216088] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1542 05:20:48.943399 <6>[ 14.219570] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1543 05:20:48.948967 <6>[ 14.219585] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1544 05:20:48.954624 <6>[ 14.219590] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1545 05:20:48.965634 <6>[ 14.219595] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1546 05:20:48.971230 <6>[ 14.219599] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1547 05:20:48.976859 <6>[ 14.219604] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1548 05:20:48.982350 <6>[ 14.219608] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1549 05:20:48.988011 <6>[ 14.219685] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1550 05:20:48.993455 <6>[ 14.219689] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1551 05:20:49.004425 <6>[ 14.219693] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1552 05:20:49.010094 <6>[ 14.222034] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1553 05:20:49.015632 <6>[ 14.304709] panfrost ffe40000.gpu: clock rate = 24000000
1554 05:20:49.026627 <3>[ 14.308471] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1555 05:20:49.032275 <6>[ 14.320773] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1556 05:20:49.043256 <6>[ 14.325334] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1557 05:20:49.054324 <4>[ 14.328012] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1558 05:20:49.065394 <6>[ 14.333712] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1559 05:20:49.076494 <6>[ 14.342886] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1560 05:20:49.082098 <6>[ 14.365751] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1561 05:20:49.087668 <6>[ 14.366789] Registered IR keymap rc-empty
1562 05:20:49.093186 <6>[ 14.376735] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1563 05:20:49.104250 <6>[ 14.384781] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1564 05:20:49.115331 <6>[ 14.386529] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1565 05:20:49.120972 <6>[ 14.394924] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1566 05:20:49.126515 <6>[ 14.404289] rc rc0: sw decoder init
1567 05:20:49.132050 <6>[ 14.414872] meson-ir ff808000.ir: receiver initialized
1568 05:20:49.139230 <6>[ 14.415327] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1569 05:20:49.150293 <6>[ 14.435506] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1570 05:20:49.155926 <3>[ 14.439179] meson-drm ff900000.vpu: DSI transceiver device is disabled
1571 05:20:49.162000 <6>[ 14.450002] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1572 05:20:49.183886 <6>[ 14.471955] usbcore: registered new device driver onboard-usb-dev
1573 05:20:49.188640 <6>[ 14.475639] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1574 05:20:49.369288 <6>[ 14.639138] Console: switching to colour frame buffer device 128x48
1575 05:20:49.375210 <6>[ 14.658336] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1576 05:20:49.606436 <6>[ 14.900097] hub 1-1:1.0: USB hub found
1577 05:20:49.612172 <6>[ 14.900445] hub 1-1:1.0: 4 ports detected
1578 05:20:49.754176 <4>[ 15.042394] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1579 05:20:49.759795 <3>[ 15.044753] onboard-usb-dev 1-1: Failed to suspend device, error -32
1580 05:20:49.766743 <3>[ 15.051191] onboard-usb-dev 1-1: can't set config #1, error -71
1581 05:20:49.782173 <4>[ 15.070428] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1582 05:20:49.787794 <3>[ 15.072759] onboard-usb-dev 1-1: Failed to suspend device, error -32
1583 05:20:49.793304 <6>[ 15.072797] onboard-usb-dev 1-1: USB disconnect, device number 2
1584 05:20:49.798927 Begin: Loading essential drivers ... done.
1585 05:20:49.804399 Begin: Running /scripts/init-premount ... done.
1586 05:20:49.810002 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1587 05:20:49.815486 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1588 05:20:49.821057 Device /sys/class/net/end0 found
1589 05:20:49.821510 done.
1590 05:20:49.829408 Begin: Waiting up to 180 secs for any network device to become available ... done.
1591 05:20:49.871867 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.155687] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1592 05:20:49.872527
1593 05:20:49.961115 <6>[ 15.246496] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=26)
1594 05:20:49.975087 <6>[ 15.263191] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1595 05:20:49.981147 <6>[ 15.265376] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1596 05:20:49.990147 <6>[ 15.273100] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1597 05:20:50.049108 <6>[ 15.338405] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1598 05:20:50.246707 <6>[ 15.540183] hub 1-1:1.0: USB hub found
1599 05:20:50.252302 <6>[ 15.540490] hub 1-1:1.0: 4 ports detected
1600 05:20:50.378865 <6>[ 15.668074] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1601 05:20:50.634770 <6>[ 15.924051] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1602 05:20:51.430342 IP-Config: no response after 2 secs - giving up
1603 05:20:51.475826 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1604 05:20:52.708775 <4>[ 18.002413] rc rc0: two consecutive events of type space
1605 05:20:52.940966 <6>[ 18.228473] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1606 05:20:53.689730 IP-Config: end0 guessed broadcast address 192.168.6.255
1607 05:20:53.695287 IP-Config: end0 complete (dhcp from 192.168.6.1):
1608 05:20:53.700769 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1609 05:20:53.711756 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1610 05:20:53.712235 rootserver: 192.168.6.1 rootpath:
1611 05:20:53.715312 filename :
1612 05:20:53.810361 done.
1613 05:20:53.821200 Begin: Running /scripts/nfs-bottom ... done.
1614 05:20:53.840319 Begin: Running /scripts/init-bottom ... done.
1615 05:20:54.177196 <30>[ 19.466326] systemd[1]: System time before build time, advancing clock.
1616 05:20:54.226012 <6>[ 19.519681] NET: Registered PF_INET6 protocol family
1617 05:20:54.231651 <6>[ 19.520481] Segment Routing with IPv6
1618 05:20:54.236851 <6>[ 19.523215] In-situ OAM (IOAM) with IPv6
1619 05:20:54.317938 <30>[ 19.583926] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1620 05:20:54.323575 <30>[ 19.611336] systemd[1]: Detected architecture arm64.
1621 05:20:54.324066
1622 05:20:54.330896 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1623 05:20:54.331348
1624 05:20:54.346012 <30>[ 19.635948] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1625 05:20:55.079064 <30>[ 20.367758] systemd[1]: Queued start job for default target graphical.target.
1626 05:20:55.122811 <30>[ 20.410949] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1627 05:20:55.130340 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1628 05:20:55.148205 <30>[ 20.436359] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1629 05:20:55.156587 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1630 05:20:55.168259 <30>[ 20.456404] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1631 05:20:55.177263 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1632 05:20:55.188344 <30>[ 20.475947] systemd[1]: Created slice user.slice - User and Session Slice.
1633 05:20:55.194352 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1634 05:20:55.216256 <30>[ 20.498945] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1635 05:20:55.220314 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1636 05:20:55.238692 <30>[ 20.526908] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1637 05:20:55.250706 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1638 05:20:55.267344 <30>[ 20.546802] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1639 05:20:55.278353 <30>[ 20.561019] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1640 05:20:55.285971 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1641 05:20:55.291625 <30>[ 20.582638] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1642 05:20:55.302574 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1643 05:20:55.318442 <30>[ 20.606677] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1644 05:20:55.332193 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1645 05:20:55.337687 <30>[ 20.626727] systemd[1]: Reached target paths.target - Path Units.
1646 05:20:55.346106 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1647 05:20:55.351657 <30>[ 20.642656] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1648 05:20:55.363319 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1649 05:20:55.368901 <30>[ 20.658620] systemd[1]: Reached target slices.target - Slice Units.
1650 05:20:55.377068 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1651 05:20:55.382711 <30>[ 20.674675] systemd[1]: Reached target swap.target - Swaps.
1652 05:20:55.390527 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1653 05:20:55.402520 <30>[ 20.690706] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1654 05:20:55.411370 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1655 05:20:55.426803 <30>[ 20.715025] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1656 05:20:55.436019 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1657 05:20:55.448305 <30>[ 20.736547] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1658 05:20:55.461721 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1659 05:20:55.467235 <30>[ 20.755648] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1660 05:20:55.480118 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1661 05:20:55.485643 <30>[ 20.774858] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1662 05:20:55.492535 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1663 05:20:55.503661 <30>[ 20.791519] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1664 05:20:55.512399 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1665 05:20:55.524121 <30>[ 20.812392] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1666 05:20:55.529726 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1667 05:20:55.542449 <30>[ 20.830725] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1668 05:20:55.550939 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1669 05:20:55.590321 <30>[ 20.878586] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1670 05:20:55.597049 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1671 05:20:55.611904 <30>[ 20.900145] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1672 05:20:55.619399 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1673 05:20:55.662548 <30>[ 20.950717] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1674 05:20:55.669893 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1675 05:20:55.690049 <30>[ 20.971067] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1676 05:20:55.701138 <30>[ 20.987927] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1677 05:20:55.708243 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1678 05:20:55.725052 <30>[ 21.013325] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1679 05:20:55.733014 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1680 05:20:55.749046 <30>[ 21.037311] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1681 05:20:55.756634 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1682 05:20:55.772831 <30>[ 21.061101] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1683 05:20:55.778376 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1684 05:20:55.788819 <6>[ 21.072104] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1685 05:20:55.826568 <30>[ 21.114774] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1686 05:20:55.834840 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1687 05:20:55.849122 <30>[ 21.137383] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1688 05:20:55.856378 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1689 05:20:55.868872 <30>[ 21.157148] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1690 05:20:55.874460 <6>[ 21.160244] fuse: init (API version 7.41)
1691 05:20:55.878378 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1692 05:20:55.894377 <30>[ 21.182664] systemd[1]: Starting systemd-journald.service - Journal Service...
1693 05:20:55.900769 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1694 05:20:55.921457 <30>[ 21.209738] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1695 05:20:55.929001 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1696 05:20:55.943122 <30>[ 21.231400] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1697 05:20:55.952497 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1698 05:20:55.970895 <30>[ 21.259171] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1699 05:20:55.979754 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1700 05:20:55.998954 <30>[ 21.287225] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1701 05:20:56.007029 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1702 05:20:56.025778 <30>[ 21.313992] systemd[1]: Started systemd-journald.service - Journal Service.
1703 05:20:56.032590 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1704 05:20:56.046091 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1705 05:20:56.063383 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1706 05:20:56.079413 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1707 05:20:56.096031 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1708 05:20:56.109078 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1709 05:20:56.121052 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1710 05:20:56.133013 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1711 05:20:56.145093 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1712 05:20:56.156880 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1713 05:20:56.168950 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1714 05:20:56.180257 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1715 05:20:56.192167 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1716 05:20:56.204208 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1717 05:20:56.216999 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1718 05:20:56.277936 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1719 05:20:56.288322 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1720 05:20:56.300473 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1721 05:20:56.315725 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1722 05:20:56.335394 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1723 05:20:56.342723 <46>[ 21.629965] systemd-journald[227]: Received client request to flush runtime journal.
1724 05:20:56.356828 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1725 05:20:56.374687 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1726 05:20:56.382135 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1727 05:20:56.398916 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1728 05:20:56.415238 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1729 05:20:56.440520 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1730 05:20:56.451564 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1731 05:20:56.490109 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1732 05:20:56.662303 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1733 05:20:56.679041 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1734 05:20:56.698083 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1735 05:20:56.733952 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1736 05:20:56.747757 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1737 05:20:56.760189 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1738 05:20:56.924108 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1739 05:20:56.982150 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1740 05:20:57.027321 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1741 05:20:57.066094 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1742 05:20:57.114807 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1743 05:20:57.128586 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1744 05:20:57.164346 <5>[ 22.452557] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1745 05:20:57.186100 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1746 05:20:57.215612 <5>[ 22.503765] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1747 05:20:57.221194 <5>[ 22.504568] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1748 05:20:57.226719 <4>[ 22.514531] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1749 05:20:57.234864 <6>[ 22.520910] cfg80211: failed to load regulatory.db
1750 05:20:57.299695 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1751 05:20:57.318769 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1752 05:20:57.330334 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1753 05:20:57.347339 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1754 05:20:57.386078 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1755 05:20:57.398638 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1756 05:20:57.454904 <46>[ 22.734036] systemd-journald[227]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1757 05:20:57.471557 <46>[ 22.746525] systemd-journald[227]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1758 05:20:57.478168 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1759 05:20:57.489355 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1760 05:20:57.504234 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1761 05:20:57.521504 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1762 05:20:57.533780 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1763 05:20:57.548158 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1764 05:20:57.555174 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1765 05:20:57.611206 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1766 05:20:57.635044 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1767 05:20:57.643478 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1768 05:20:57.670679 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1769 05:20:57.706668 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1770 05:20:57.712995 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1771 05:20:57.725272 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1772 05:20:57.740923 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1773 05:20:57.753439 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1774 05:20:57.765373 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1775 05:20:57.814459 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1776 05:20:57.834100 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1777 05:20:57.858768 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1778 05:20:57.921566 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1779 05:20:57.928262 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1780 05:20:57.944064 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1781 05:20:57.954935 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1782 05:20:57.981734 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1783 05:20:57.996834 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1784 05:20:58.008297 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1785 05:20:58.037749 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1786 05:20:58.054082 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1787 05:20:58.065509 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1788 05:20:58.079866 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1789 05:20:58.090731 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1790 05:20:58.106373 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1791 05:20:58.154598 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1792 05:20:58.205088 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1793 05:20:58.249479
1794 05:20:58.250013 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1795 05:20:58.250436
1796 05:20:58.256703 debian-bookworm-arm64 login: root (automatic login)
1797 05:20:58.257172
1798 05:20:58.376072 Linux debian-bookworm-arm64 6.12.0-rc2 #1 SMP PREEMPT Thu Nov 7 02:30:35 UTC 2024 aarch64
1799 05:20:58.376629
1800 05:20:58.381592 The programs included with the Debian GNU/Linux system are free software;
1801 05:20:58.390582 the exact distribution terms for each program are described in the
1802 05:20:58.391079 individual files in /usr/share/doc/*/copyright.
1803 05:20:58.391498
1804 05:20:58.396267 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1805 05:20:58.401395 permitted by applicable law.
1806 05:20:59.071030 Matched prompt #10: / #
1808 05:20:59.072672 Setting prompt string to ['/ #']
1809 05:20:59.073252 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1811 05:20:59.074623 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1812 05:20:59.075153 start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
1813 05:20:59.075582 Setting prompt string to ['/ #']
1814 05:20:59.076008 Forcing a shell prompt, looking for ['/ #']
1816 05:20:59.126986 / #
1817 05:20:59.127735 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1818 05:20:59.128269 Waiting using forced prompt support (timeout 00:02:30)
1819 05:20:59.133855
1820 05:20:59.134691 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1821 05:20:59.135242 start: 2.4.6 export-device-env (timeout 00:03:12) [common]
1822 05:20:59.135694 Sending with 10 millisecond of delay
1824 05:21:04.128951 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/951357/extract-nfsrootfs-6yd7u1kw'
1825 05:21:04.139906 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/951357/extract-nfsrootfs-6yd7u1kw'
1826 05:21:04.140709 Sending with 10 millisecond of delay
1828 05:21:06.238494 / # export NFS_SERVER_IP='192.168.6.2'
1829 05:21:06.249452 export NFS_SERVER_IP='192.168.6.2'
1830 05:21:06.250383 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1831 05:21:06.250968 end: 2.4 uboot-commands (duration 00:01:55) [common]
1832 05:21:06.251560 end: 2 uboot-action (duration 00:01:55) [common]
1833 05:21:06.252189 start: 3 lava-test-retry (timeout 00:06:46) [common]
1834 05:21:06.252788 start: 3.1 lava-test-shell (timeout 00:06:46) [common]
1835 05:21:06.253255 Using namespace: common
1837 05:21:06.354429 / # #
1838 05:21:06.355382 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1839 05:21:06.361156 #
1840 05:21:06.361921 Using /lava-951357
1842 05:21:06.463032 / # export SHELL=/bin/bash
1843 05:21:06.469283 export SHELL=/bin/bash
1845 05:21:06.570719 / # . /lava-951357/environment
1846 05:21:06.575959 . /lava-951357/environment
1848 05:21:06.681729 / # /lava-951357/bin/lava-test-runner /lava-951357/0
1849 05:21:06.682650 Test shell timeout: 10s (minimum of the action and connection timeout)
1850 05:21:06.685957 /lava-951357/bin/lava-test-runner /lava-951357/0
1851 05:21:06.889605 + export TESTRUN_ID=0_timesync-off
1852 05:21:06.897366 + TESTRUN_ID=0_timesync-off
1853 05:21:06.897891 + cd /lava-951357/0/tests/0_timesync-off
1854 05:21:06.898315 ++ cat uuid
1855 05:21:06.903186 + UUID=951357_1.6.2.4.1
1856 05:21:06.903674 + set +x
1857 05:21:06.911817 <LAVA_SIGNAL_STARTRUN 0_timesync-off 951357_1.6.2.4.1>
1858 05:21:06.912329 + systemctl stop systemd-timesyncd
1859 05:21:06.913044 Received signal: <STARTRUN> 0_timesync-off 951357_1.6.2.4.1
1860 05:21:06.913490 Starting test lava.0_timesync-off (951357_1.6.2.4.1)
1861 05:21:06.914022 Skipping test definition patterns.
1862 05:21:06.951384 + set +x
1863 05:21:06.951941 <LAVA_SIGNAL_ENDRUN 0_timesync-off 951357_1.6.2.4.1>
1864 05:21:06.952663 Received signal: <ENDRUN> 0_timesync-off 951357_1.6.2.4.1
1865 05:21:06.953160 Ending use of test pattern.
1866 05:21:06.953569 Ending test lava.0_timesync-off (951357_1.6.2.4.1), duration 0.04
1868 05:21:07.054473 + export TESTRUN_ID=1_kselftest-alsa
1869 05:21:07.062941 + TESTRUN_ID=1_kselftest-alsa
1870 05:21:07.063499 + cd /lava-951357/0/tests/1_kselftest-alsa
1871 05:21:07.063969 ++ cat uuid
1872 05:21:07.072257 + UUID=951357_1.6.2.4.5
1873 05:21:07.072797 + set +x
1874 05:21:07.077755 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 951357_1.6.2.4.5>
1875 05:21:07.078270 + cd ./automated/linux/kselftest/
1876 05:21:07.078991 Received signal: <STARTRUN> 1_kselftest-alsa 951357_1.6.2.4.5
1877 05:21:07.079454 Starting test lava.1_kselftest-alsa (951357_1.6.2.4.5)
1878 05:21:07.080029 Skipping test definition patterns.
1879 05:21:07.107334 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1880 05:21:07.147814 INFO: install_deps skipped
1881 05:21:07.258398 --2024-11-07 05:21:07-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/kselftest.tar.xz
1882 05:21:07.290989 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1883 05:21:07.432759 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1884 05:21:07.578068 HTTP request sent, awaiting response... 200 OK
1885 05:21:07.578697 Length: 6924864 (6.6M) [application/octet-stream]
1886 05:21:07.583524 Saving to: 'kselftest_armhf.tar.gz'
1887 05:21:07.584113
1888 05:21:08.860450
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 49.92K 180KB/s
kselftest_armhf.tar 3%[ ] 218.67K 394KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.05MB/s
kselftest_armhf.tar 47%[========> ] 3.16M 2.79MB/s
kselftest_armhf.tar 100%[===================>] 6.60M 5.17MB/s in 1.3s
1889 05:21:08.861122
1890 05:21:08.965032 2024-11-07 05:21:08 (5.17 MB/s) - 'kselftest_armhf.tar.gz' saved [6924864/6924864]
1891 05:21:08.965689
1892 05:21:18.252440 skiplist:
1893 05:21:18.253101 ========================================
1894 05:21:18.258234 ========================================
1895 05:21:18.304504 alsa:mixer-test
1896 05:21:18.305157 alsa:pcm-test
1897 05:21:18.305633 alsa:test-pcmtest-driver
1898 05:21:18.308479 alsa:utimer-test
1899 05:21:18.322739 ============== Tests to run ===============
1900 05:21:18.323301 alsa:mixer-test
1901 05:21:18.328436 alsa:pcm-test
1902 05:21:18.329006 alsa:test-pcmtest-driver
1903 05:21:18.329436 alsa:utimer-test
1904 05:21:18.335612 ===========End Tests to run ===============
1905 05:21:18.336190 shardfile-alsa pass
1906 05:21:18.496181 <12>[ 43.787414] kselftest: Running tests in alsa
1907 05:21:18.501238 TAP version 13
1908 05:21:18.509947 1..4
1909 05:21:18.536722 # timeout set to 45
1910 05:21:18.537334 # selftests: alsa: mixer-test
1911 05:21:18.704386 # TAP version 13
1912 05:21:18.704977 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1913 05:21:18.709753 # 1..427
1914 05:21:18.710091 # ok 1 get_value.LCALTA.60
1915 05:21:18.710301 # # LCALTA.60 TDMOUT_A SRC SEL
1916 05:21:18.715381 # ok 2 name.LCALTA.60
1917 05:21:18.715885 # ok 3 write_default.LCALTA.60
1918 05:21:18.718897 # ok 4 write_valid.LCALTA.60
1919 05:21:18.724355 # ok 5 write_invalid.LCALTA.60
1920 05:21:18.724807 # ok 6 event_missing.LCALTA.60
1921 05:21:18.729987 # ok 7 event_spurious.LCALTA.60
1922 05:21:18.730340 # ok 8 get_value.LCALTA.59
1923 05:21:18.735501 # # LCALTA.59 TDMOUT_B SRC SEL
1924 05:21:18.735872 # ok 9 name.LCALTA.59
1925 05:21:18.739349 # ok 10 write_default.LCALTA.59
1926 05:21:18.739678 # ok 11 write_valid.LCALTA.59
1927 05:21:18.744648 # ok 12 write_invalid.LCALTA.59
1928 05:21:18.744988 # ok 13 event_missing.LCALTA.59
1929 05:21:18.750211 # ok 14 event_spurious.LCALTA.59
1930 05:21:18.750706 # ok 15 get_value.LCALTA.58
1931 05:21:18.756218 # # LCALTA.58 TDMOUT_C SRC SEL
1932 05:21:18.756951 # ok 16 name.LCALTA.58
1933 05:21:18.761303 # ok 17 write_default.LCALTA.58
1934 05:21:18.762011 # ok 18 write_valid.LCALTA.58
1935 05:21:18.766826 # ok 19 write_invalid.LCALTA.58
1936 05:21:18.767462 # ok 20 event_missing.LCALTA.58
1937 05:21:18.772309 # ok 21 event_spurious.LCALTA.58
1938 05:21:18.772958 # ok 22 get_value.LCALTA.57
1939 05:21:18.777957 # # LCALTA.57 TDMIN_A SRC SEL
1940 05:21:18.778587 # ok 23 name.LCALTA.57
1941 05:21:18.783431 # ok 24 write_default.LCALTA.57
1942 05:21:18.784083 # ok 25 write_valid.LCALTA.57
1943 05:21:18.789064 # ok 26 write_invalid.LCALTA.57
1944 05:21:18.789812 # ok 27 event_missing.LCALTA.57
1945 05:21:18.794559 # ok 28 event_spurious.LCALTA.57
1946 05:21:18.795249 # ok 29 get_value.LCALTA.56
1947 05:21:18.800122 # # LCALTA.56 TDMIN_B SRC SEL
1948 05:21:18.800829 # ok 30 name.LCALTA.56
1949 05:21:18.801424 # ok 31 write_default.LCALTA.56
1950 05:21:18.805897 # ok 32 write_valid.LCALTA.56
1951 05:21:18.806532 # ok 33 write_invalid.LCALTA.56
1952 05:21:18.811353 # ok 34 event_missing.LCALTA.56
1953 05:21:18.822485 # ok 35 event_<3>[ 44.103498] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1954 05:21:18.828068 spurious.LCALTA.56
1955 05:21:18.828683 # ok 36 get_value.LCALTA.55
1956 05:21:18.833570 # # LCALTA.55 TDMIN_C SRC SEL
1957 05:21:18.834065 # ok 37 name.LCALTA.55
1958 05:21:18.839345 # ok 38 write_default.LCALTA.55
1959 05:21:18.839945 # ok 39 write_valid.LCALTA.55
1960 05:21:18.845103 # ok 40 write_invalid.LCALTA.55
1961 05:21:18.845625 # ok 41 event_missing.LCALTA.55
1962 05:21:18.850340 # ok 42 event_spurious.LCALTA.55
1963 05:21:18.851048 # ok 43 get_value.LCALTA.54
1964 05:21:18.855563 # # LCALTA.54 ACODEC Left DAC Sel
1965 05:21:18.856256 # ok 44 name.LCALTA.54
1966 05:21:18.856834 # ok 45 write_default.LCALTA.54
1967 05:21:18.861193 # ok 46 write_valid.LCALTA.54
1968 05:21:18.861821 # ok 47 write_invalid.LCALTA.54
1969 05:21:18.866989 # ok 48 event_missing.LCALTA.54
1970 05:21:18.872334 # ok 49 event_spurious.LCALTA.54
1971 05:21:18.872773 # ok 50 get_value.LCALTA.53
1972 05:21:18.878049 # # LCALTA.53 ACODEC Right DAC Sel
1973 05:21:18.879285 # ok 51 name.LCALTA.53
1974 05:21:18.880386 # ok 52 write_default.LCALTA.53
1975 05:21:18.883601 # ok 53 write_valid.LCALTA.53
1976 05:21:18.884720 # ok 54 write_invalid.LCALTA.53
1977 05:21:18.889227 # ok 55 event_missing.LCALTA.53
1978 05:21:18.890841 # ok 56 event_spurious.LCALTA.53
1979 05:21:18.894667 # ok 57 get_value.LCALTA.52
1980 05:21:18.900122 # # LCALTA.52 TOACODEC OUT EN Switch
1981 05:21:18.900739 # ok 58 name.LCALTA.52
1982 05:21:18.901220 # ok 59 write_default.LCALTA.52
1983 05:21:18.905577 # ok 60 write_valid.LCALTA.52
1984 05:21:18.906209 # ok 61 write_invalid.LCALTA.52
1985 05:21:18.911170 # ok 62 event_missing.LCALTA.52
1986 05:21:18.911786 # ok 63 event_spurious.LCALTA.52
1987 05:21:18.916670 # ok 64 get_value.LCALTA.51
1988 05:21:18.917230 # # LCALTA.51 TOACODEC SRC
1989 05:21:18.922136 # ok 65 name.LCALTA.51
1990 05:21:18.922695 # ok 66 write_default.LCALTA.51
1991 05:21:18.927660 # ok 67 write_valid.LCALTA.51
1992 05:21:18.928273 # ok 68 write_invalid.LCALTA.51
1993 05:21:18.933347 # ok 69 event_missing.LCALTA.51
1994 05:21:18.933956 # ok 70 event_spurious.LCALTA.51
1995 05:21:18.938839 # ok 71 get_value.LCALTA.50
1996 05:21:18.939407 # # LCALTA.50 TOHDMITX SPDIF SRC
1997 05:21:18.944352 # ok 72 name.LCALTA.50
1998 05:21:18.944909 # ok 73 write_default.LCALTA.50
1999 05:21:18.949895 # ok 74 write_valid.LCALTA.50
2000 05:21:18.950454 # ok 75 write_invalid.LCALTA.50
2001 05:21:18.955652 # ok 76 event_missing.LCALTA.50
2002 05:21:18.956779 # ok 77 event_spurious.LCALTA.50
2003 05:21:18.961145 # ok 78 get_value.LCALTA.49
2004 05:21:18.961728 # # LCALTA.49 TOHDMITX Switch
2005 05:21:18.966675 # ok 79 name.LCALTA.49
2006 05:21:18.967282 # ok 80 write_default.LCALTA.49
2007 05:21:18.972285 # ok 81 write_valid.LCALTA.49
2008 05:21:18.972869 # ok 82 write_invalid.LCALTA.49
2009 05:21:18.977662 # ok 83 event_missing.LCALTA.49
2010 05:21:18.978264 # ok 84 event_spurious.LCALTA.49
2011 05:21:18.983241 # ok 85 get_value.LCALTA.48
2012 05:21:18.983862 # # LCALTA.48 TOHDMITX I2S SRC
2013 05:21:18.984413 # ok 86 name.LCALTA.48
2014 05:21:18.988741 # ok 87 write_default.LCALTA.48
2015 05:21:18.989331 # ok 88 write_valid.LCALTA.48
2016 05:21:18.994265 # ok 89 write_invalid.LCALTA.48
2017 05:21:18.994827 # ok 90 event_missing.LCALTA.48
2018 05:21:18.999965 # ok 91 event_spurious.LCALTA.48
2019 05:21:19.000626 # ok 92 get_value.LCALTA.47
2020 05:21:19.005370 # # LCALTA.47 TODDR_C SRC SEL
2021 05:21:19.005730 # ok 93 name.LCALTA.47
2022 05:21:19.010969 # ok 94 write_default.LCALTA.47
2023 05:21:19.011541 # ok 95 write_valid.LCALTA.47
2024 05:21:19.016547 # ok 96 write_invalid.LCALTA.47
2025 05:21:19.017151 # ok 97 event_missing.LCALTA.47
2026 05:21:19.022174 # ok 98 event_spurious.LCALTA.47
2027 05:21:19.022763 # ok 99 get_value.LCALTA.46
2028 05:21:19.027601 # # LCALTA.46 TODDR_B SRC SEL
2029 05:21:19.028230 # ok 100 name.LCALTA.46
2030 05:21:19.033127 # ok 101 write_default.LCALTA.46
2031 05:21:19.033703 # ok 102 write_valid.LCALTA.46
2032 05:21:19.038642 # ok 103 write_invalid.LCALTA.46
2033 05:21:19.039206 # ok 104 event_missing.LCALTA.46
2034 05:21:19.044220 # ok 105 event_spurious.LCALTA.46
2035 05:21:19.044798 # ok 106 get_value.LCALTA.45
2036 05:21:19.049753 # # LCALTA.45 TODDR_A SRC SEL
2037 05:21:19.050323 # ok 107 name.LCALTA.45
2038 05:21:19.055280 # ok 108 write_default.LCALTA.45
2039 05:21:19.055840 # ok 109 write_valid.LCALTA.45
2040 05:21:19.060877 # ok 110 write_invalid.LCALTA.45
2041 05:21:19.061427 # ok 111 event_missing.LCALTA.45
2042 05:21:19.066428 # ok 112 event_spurious.LCALTA.45
2043 05:21:19.066975 # ok 113 get_value.LCALTA.44
2044 05:21:19.072042 # # LCALTA.44 FRDDR_C SINK 3 SEL
2045 05:21:19.073216 # ok 114 name.LCALTA.44
2046 05:21:19.077534 # ok 115 write_default.LCALTA.44
2047 05:21:19.078104 # ok 116 write_valid.LCALTA.44
2048 05:21:19.083124 # ok 117 write_invalid.LCALTA.44
2049 05:21:19.083671 # ok 118 event_missing.LCALTA.44
2050 05:21:19.088545 # ok 119 event_spurious.LCALTA.44
2051 05:21:19.089130 # ok 120 get_value.LCALTA.43
2052 05:21:19.094193 # # LCALTA.43 FRDDR_C SINK 2 SEL
2053 05:21:19.094780 # ok 121 name.LCALTA.43
2054 05:21:19.099672 # ok 122 write_default.LCALTA.43
2055 05:21:19.100258 # ok 123 write_valid.LCALTA.43
2056 05:21:19.105272 # ok 124 write_invalid.LCALTA.43
2057 05:21:19.105858 # ok 125 event_missing.LCALTA.43
2058 05:21:19.110826 # ok 126 event_spurious.LCALTA.43
2059 05:21:19.111440 # ok 127 get_value.LCALTA.42
2060 05:21:19.116394 # # LCALTA.42 FRDDR_C SINK 1 SEL
2061 05:21:19.116993 # ok 128 name.LCALTA.42
2062 05:21:19.121920 # ok 129 write_default.LCALTA.42
2063 05:21:19.122515 # ok 130 write_valid.LCALTA.42
2064 05:21:19.127403 # ok 131 write_invalid.LCALTA.42
2065 05:21:19.128022 # ok 132 event_missing.LCALTA.42
2066 05:21:19.133002 # ok 133 event_spurious.LCALTA.42
2067 05:21:19.133620 # ok 134 get_value.LCALTA.41
2068 05:21:19.138505 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
2069 05:21:19.139086 # ok 135 name.LCALTA.41
2070 05:21:19.144172 # ok 136 write_default.LCALTA.41
2071 05:21:19.144779 # ok 137 write_valid.LCALTA.41
2072 05:21:19.149581 # ok 138 write_invalid.LCALTA.41
2073 05:21:19.150190 # ok 139 event_missing.LCALTA.41
2074 05:21:19.155172 # ok 140 event_spurious.LCALTA.41
2075 05:21:19.155778 # ok 141 get_value.LCALTA.40
2076 05:21:19.160666 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
2077 05:21:19.161273 # ok 142 name.LCALTA.40
2078 05:21:19.166264 # ok 143 write_default.LCALTA.40
2079 05:21:19.171783 # ok 144 write_valid.LCALTA.40
2080 05:21:19.172395 # ok 145 write_invalid.LCALTA.40
2081 05:21:19.177348 # ok 146 event_missing.LCALTA.40
2082 05:21:19.177912 # ok 147 event_spurious.LCALTA.40
2083 05:21:19.182926 # ok 148 get_value.LCALTA.39
2084 05:21:19.183490 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
2085 05:21:19.188441 # ok 149 name.LCALTA.39
2086 05:21:19.189016 # ok 150 write_default.LCALTA.39
2087 05:21:19.194004 # ok 151 write_valid.LCALTA.39
2088 05:21:19.194557 # ok 152 write_invalid.LCALTA.39
2089 05:21:19.199537 # ok 153 event_missing.LCALTA.39
2090 05:21:19.200125 # ok 154 event_spurious.LCALTA.39
2091 05:21:19.205176 # ok 155 get_value.LCALTA.38
2092 05:21:19.205744 # # LCALTA.38 FRDDR_B SINK 3 SEL
2093 05:21:19.210633 # ok 156 name.LCALTA.38
2094 05:21:19.211198 # ok 157 write_default.LCALTA.38
2095 05:21:19.216256 # ok 158 write_valid.LCALTA.38
2096 05:21:19.216834 # ok 159 write_invalid.LCALTA.38
2097 05:21:19.221717 # ok 160 event_missing.LCALTA.38
2098 05:21:19.222285 # ok 161 event_spurious.LCALTA.38
2099 05:21:19.227302 # ok 162 get_value.LCALTA.37
2100 05:21:19.227868 # # LCALTA.37 FRDDR_B SINK 2 SEL
2101 05:21:19.232819 # ok 163 name.LCALTA.37
2102 05:21:19.233388 # ok 164 write_default.LCALTA.37
2103 05:21:19.238364 # ok 165 write_valid.LCALTA.37
2104 05:21:19.238952 # ok 166 write_invalid.LCALTA.37
2105 05:21:19.243908 # ok 167 event_missing.LCALTA.37
2106 05:21:19.244521 # ok 168 event_spurious.LCALTA.37
2107 05:21:19.249458 # ok 169 get_value.LCALTA.36
2108 05:21:19.249793 # # LCALTA.36 FRDDR_B SINK 1 SEL
2109 05:21:19.255033 # ok 170 name.LCALTA.36
2110 05:21:19.255617 # ok 171 write_default.LCALTA.36
2111 05:21:19.260423 # ok 172 write_valid.LCALTA.36
2112 05:21:19.260770 # ok 173 write_invalid.LCALTA.36
2113 05:21:19.266172 # ok 174 event_missing.LCALTA.36
2114 05:21:19.266779 # ok 175 event_spurious.LCALTA.36
2115 05:21:19.271686 # ok 176 get_value.LCALTA.35
2116 05:21:19.272324 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
2117 05:21:19.277183 # ok 177 name.LCALTA.35
2118 05:21:19.277770 # ok 178 write_default.LCALTA.35
2119 05:21:19.282711 # ok 179 write_valid.LCALTA.35
2120 05:21:19.283280 # ok 180 write_invalid.LCALTA.35
2121 05:21:19.288279 # ok 181 event_missing.LCALTA.35
2122 05:21:19.288833 # ok 182 event_spurious.LCALTA.35
2123 05:21:19.293800 # ok 183 get_value.LCALTA.34
2124 05:21:19.299374 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
2125 05:21:19.299961 # ok 184 name.LCALTA.34
2126 05:21:19.300463 # ok 185 write_default.LCALTA.34
2127 05:21:19.304929 # ok 186 write_valid.LCALTA.34
2128 05:21:19.305491 # ok 187 write_invalid.LCALTA.34
2129 05:21:19.310444 # ok 188 event_missing.LCALTA.34
2130 05:21:19.316022 # ok 189 event_spurious.LCALTA.34
2131 05:21:19.316596 # ok 190 get_value.LCALTA.33
2132 05:21:19.321554 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
2133 05:21:19.322107 # ok 191 name.LCALTA.33
2134 05:21:19.327147 # ok 192 write_default.LCALTA.33
2135 05:21:19.327691 # ok 193 write_valid.LCALTA.33
2136 05:21:19.332649 # ok 194 write_invalid.LCALTA.33
2137 05:21:19.333191 # ok 195 event_missing.LCALTA.33
2138 05:21:19.338213 # ok 196 event_spurious.LCALTA.33
2139 05:21:19.338763 # ok 197 get_value.LCALTA.32
2140 05:21:19.343739 # # LCALTA.32 FRDDR_A SINK 3 SEL
2141 05:21:19.344319 # ok 198 name.LCALTA.32
2142 05:21:19.349259 # ok 199 write_default.LCALTA.32
2143 05:21:19.349789 # ok 200 write_valid.LCALTA.32
2144 05:21:19.354754 # ok 201 write_invalid.LCALTA.32
2145 05:21:19.355268 # ok 202 event_missing.LCALTA.32
2146 05:21:19.360303 # ok 203 event_spurious.LCALTA.32
2147 05:21:19.360819 # ok 204 get_value.LCALTA.31
2148 05:21:19.365835 # # LCALTA.31 FRDDR_A SINK 2 SEL
2149 05:21:19.366350 # ok 205 name.LCALTA.31
2150 05:21:19.371367 # ok 206 write_default.LCALTA.31
2151 05:21:19.371876 # ok 207 write_valid.LCALTA.31
2152 05:21:19.376953 # ok 208 write_invalid.LCALTA.31
2153 05:21:19.377461 # ok 209 event_missing.LCALTA.31
2154 05:21:19.382489 # ok 210 event_spurious.LCALTA.31
2155 05:21:19.383004 # ok 211 get_value.LCALTA.30
2156 05:21:19.388117 # # LCALTA.30 FRDDR_A SINK 1 SEL
2157 05:21:19.388626 # ok 212 name.LCALTA.30
2158 05:21:19.393577 # ok 213 write_default.LCALTA.30
2159 05:21:19.394081 # ok 214 write_valid.LCALTA.30
2160 05:21:19.399121 # ok 215 write_invalid.LCALTA.30
2161 05:21:19.399625 # ok 216 event_missing.LCALTA.30
2162 05:21:19.404681 # ok 217 event_spurious.LCALTA.30
2163 05:21:19.405201 # ok 218 get_value.LCALTA.29
2164 05:21:19.410298 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2165 05:21:19.410878 # ok 219 name.LCALTA.29
2166 05:21:19.415870 # ok 220 write_default.LCALTA.29
2167 05:21:19.416755 # ok 221 write_valid.LCALTA.29
2168 05:21:19.421370 # ok 222 write_invalid.LCALTA.29
2169 05:21:19.421895 # ok 223 event_missing.LCALTA.29
2170 05:21:19.426886 # ok 224 event_spurious.LCALTA.29
2171 05:21:19.427411 # ok 225 get_value.LCALTA.28
2172 05:21:19.432408 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2173 05:21:19.432929 # ok 226 name.LCALTA.28
2174 05:21:19.437957 # ok 227 write_default.LCALTA.28
2175 05:21:19.438474 # ok 228 write_valid.LCALTA.28
2176 05:21:19.443575 # ok 229 write_invalid.LCALTA.28
2177 05:21:19.444358 # ok 230 event_missing.LCALTA.28
2178 05:21:19.449130 # ok 231 event_spurious.LCALTA.28
2179 05:21:19.449669 # ok 232 get_value.LCALTA.27
2180 05:21:19.454591 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2181 05:21:19.455121 # ok 233 name.LCALTA.27
2182 05:21:19.460165 # ok 234 write_default.LCALTA.27
2183 05:21:19.460694 # ok 235 write_valid.LCALTA.27
2184 05:21:19.465686 # ok 236 write_invalid.LCALTA.27
2185 05:21:19.471245 # ok 237 event_missing.LCALTA.27
2186 05:21:19.471761 # ok 238 event_spurious.LCALTA.27
2187 05:21:19.476799 # ok 239 get_value.LCALTA.26
2188 05:21:19.477316 # # LCALTA.26 ELD
2189 05:21:19.477778 # ok 240 name.LCALTA.26
2190 05:21:19.482346 # # ELD is not writeable
2191 05:21:19.482855 # ok 241 # SKIP write_default.LCALTA.26
2192 05:21:19.487869 # # ELD is not writeable
2193 05:21:19.488425 # ok 242 # SKIP write_valid.LCALTA.26
2194 05:21:19.493459 # # ELD is not writeable
2195 05:21:19.493976 # ok 243 # SKIP write_invalid.LCALTA.26
2196 05:21:19.498965 # ok 244 event_missing.LCALTA.26
2197 05:21:19.499491 # ok 245 event_spurious.LCALTA.26
2198 05:21:19.504520 # ok 246 get_value.LCALTA.25
2199 05:21:19.510094 # # LCALTA.25 IEC958 Playback Default
2200 05:21:19.510611 # ok 247 name.LCALTA.25
2201 05:21:19.511064 # ok 248 write_default.LCALTA.25
2202 05:21:19.515704 # ok 249 # SKIP write_valid.LCALTA.25
2203 05:21:19.521189 # ok 250 # SKIP write_invalid.LCALTA.25
2204 05:21:19.521848 # ok 251 event_missing.LCALTA.25
2205 05:21:19.526774 # ok 252 event_spurious.LCALTA.25
2206 05:21:19.527382 # ok 253 get_value.LCALTA.24
2207 05:21:19.532267 # # LCALTA.24 IEC958 Playback Mask
2208 05:21:19.532805 # ok 254 name.LCALTA.24
2209 05:21:19.537821 # # IEC958 Playback Mask is not writeable
2210 05:21:19.538363 # ok 255 # SKIP write_default.LCALTA.24
2211 05:21:19.543376 # # IEC958 Playback Mask is not writeable
2212 05:21:19.548900 # ok 256 # SKIP write_valid.LCALTA.24
2213 05:21:19.549460 # # IEC958 Playback Mask is not writeable
2214 05:21:19.554425 # ok 257 # SKIP write_invalid.LCALTA.24
2215 05:21:19.559970 # ok 258 event_missing.LCALTA.24
2216 05:21:19.560539 # ok 259 event_spurious.LCALTA.24
2217 05:21:19.565561 # ok 260 get_value.LCALTA.23
2218 05:21:19.566126 # # LCALTA.23 Playback Channel Map
2219 05:21:19.571115 # ok 261 name.LCALTA.23
2220 05:21:19.571641 # # Playback Channel Map is not writeable
2221 05:21:19.576666 # ok 262 # SKIP write_default.LCALTA.23
2222 05:21:19.582162 # # Playback Channel Map is not writeable
2223 05:21:19.582693 # ok 263 # SKIP write_valid.LCALTA.23
2224 05:21:19.587783 # # Playback Channel Map is not writeable
2225 05:21:19.588395 # ok 264 # SKIP write_invalid.LCALTA.23
2226 05:21:19.593245 # ok 265 event_missing.LCALTA.23
2227 05:21:19.598815 # ok 266 event_spurious.LCALTA.23
2228 05:21:19.599505 # ok 267 get_value.LCALTA.22
2229 05:21:19.604360 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2230 05:21:19.604881 # ok 268 name.LCALTA.22
2231 05:21:19.609906 # ok 269 write_default.LCALTA.22
2232 05:21:19.610436 # ok 270 write_valid.LCALTA.22
2233 05:21:19.615463 # ok 271 write_invalid.LCALTA.22
2234 05:21:19.616091 # ok 272 event_missing.LCALTA.22
2235 05:21:19.621187 # ok 273 event_spurious.LCALTA.22
2236 05:21:19.621710 # ok 274 get_value.LCALTA.21
2237 05:21:19.626530 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2238 05:21:19.627037 # ok 275 name.LCALTA.21
2239 05:21:19.632229 # ok 276 write_default.LCALTA.21
2240 05:21:19.632798 # ok 277 write_valid.LCALTA.21
2241 05:21:19.637657 # ok 278 write_invalid.LCALTA.21
2242 05:21:19.638303 # ok 279 event_missing.LCALTA.21
2243 05:21:19.643165 # ok 280 event_spurious.LCALTA.21
2244 05:21:19.643674 # ok 281 get_value.LCALTA.20
2245 05:21:19.648753 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2246 05:21:19.649320 # ok 282 name.LCALTA.20
2247 05:21:19.654251 # ok 283 write_default.LCALTA.20
2248 05:21:19.654760 # ok 284 write_valid.LCALTA.20
2249 05:21:19.659794 # ok 285 write_invalid.LCALTA.20
2250 05:21:19.660339 # ok 286 event_missing.LCALTA.20
2251 05:21:19.665425 # ok 287 event_spurious.LCALTA.20
2252 05:21:19.666019 # ok 288 get_value.LCALTA.19
2253 05:21:19.670886 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2254 05:21:19.671394 # ok 289 name.LCALTA.19
2255 05:21:19.676453 # ok 290 write_default.LCALTA.19
2256 05:21:19.676967 # ok 291 write_valid.LCALTA.19
2257 05:21:19.682099 # ok 292 write_invalid.LCALTA.19
2258 05:21:19.682609 # ok 293 event_missing.LCALTA.19
2259 05:21:19.687589 # ok 294 event_spurious.LCALTA.19
2260 05:21:19.688130 # ok 295 get_value.LCALTA.18
2261 05:21:19.693105 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2262 05:21:19.693614 # ok 296 name.LCALTA.18
2263 05:21:19.698711 # ok 297 write_default.LCALTA.18
2264 05:21:19.704288 # ok 298 write_valid.LCALTA.18
2265 05:21:19.704832 # ok 299 write_invalid.LCALTA.18
2266 05:21:19.709750 # ok 300 event_missing.LCALTA.18
2267 05:21:19.710271 # ok 301 event_spurious.LCALTA.18
2268 05:21:19.715249 # ok 302 get_value.LCALTA.17
2269 05:21:19.715766 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2270 05:21:19.720862 # ok 303 name.LCALTA.17
2271 05:21:19.721370 # ok 304 write_default.LCALTA.17
2272 05:21:19.726418 # ok 305 write_valid.LCALTA.17
2273 05:21:19.726995 # ok 306 write_invalid.LCALTA.17
2274 05:21:19.731924 # ok 307 event_missing.LCALTA.17
2275 05:21:19.733028 # ok 308 event_spurious.LCALTA.17
2276 05:21:19.737540 # ok 309 get_value.LCALTA.16
2277 05:21:19.738113 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2278 05:21:19.743156 # ok 310 name.LCALTA.16
2279 05:21:19.743708 # ok 311 write_default.LCALTA.16
2280 05:21:19.748558 # ok 312 write_valid.LCALTA.16
2281 05:21:19.749094 # ok 313 write_invalid.LCALTA.16
2282 05:21:19.754083 # ok 314 event_missing.LCALTA.16
2283 05:21:19.754585 # ok 315 event_spurious.LCALTA.16
2284 05:21:19.759657 # ok 316 get_value.LCALTA.15
2285 05:21:19.760200 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2286 05:21:19.765208 # ok 317 name.LCALTA.15
2287 05:21:19.765725 # ok 318 write_default.LCALTA.15
2288 05:21:19.770698 # ok 319 write_valid.LCALTA.15
2289 05:21:19.770984 # ok 320 write_invalid.LCALTA.15
2290 05:21:19.776311 # ok 321 event_missing.LCALTA.15
2291 05:21:19.776593 # ok 322 event_spurious.LCALTA.15
2292 05:21:19.781837 # ok 323 get_value.LCALTA.14
2293 05:21:19.787370 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2294 05:21:19.787663 # ok 324 name.LCALTA.14
2295 05:21:19.787869 # ok 325 write_default.LCALTA.14
2296 05:21:19.793009 # ok 326 write_valid.LCALTA.14
2297 05:21:19.793529 # ok 327 write_invalid.LCALTA.14
2298 05:21:19.798458 # ok 328 event_missing.LCALTA.14
2299 05:21:19.804149 # ok 329 event_spurious.LCALTA.14
2300 05:21:19.804753 # ok 330 get_value.LCALTA.13
2301 05:21:19.809571 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2302 05:21:19.810087 # ok 331 name.LCALTA.13
2303 05:21:19.815211 # ok 332 write_default.LCALTA.13
2304 05:21:19.815783 # ok 333 write_valid.LCALTA.13
2305 05:21:19.820538 # ok 334 write_invalid.LCALTA.13
2306 05:21:19.820826 # ok 335 event_missing.LCALTA.13
2307 05:21:19.826217 # ok 336 event_spurious.LCALTA.13
2308 05:21:19.826739 # ok 337 get_value.LCALTA.12
2309 05:21:19.831745 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2310 05:21:19.832295 # ok 338 name.LCALTA.12
2311 05:21:19.837304 # ok 339 write_default.LCALTA.12
2312 05:21:19.837815 # ok 340 write_valid.LCALTA.12
2313 05:21:19.842848 # ok 341 write_invalid.LCALTA.12
2314 05:21:19.843361 # ok 342 event_missing.LCALTA.12
2315 05:21:19.848479 # ok 343 event_spurious.LCALTA.12
2316 05:21:19.849107 # ok 344 get_value.LCALTA.11
2317 05:21:19.854063 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2318 05:21:19.854609 # ok 345 name.LCALTA.11
2319 05:21:19.859550 # ok 346 write_default.LCALTA.11
2320 05:21:19.860118 # ok 347 write_valid.LCALTA.11
2321 05:21:19.865222 # ok 348 write_invalid.LCALTA.11
2322 05:21:19.865816 # ok 349 event_missing.LCALTA.11
2323 05:21:19.870678 # ok 350 event_spurious.LCALTA.11
2324 05:21:19.871201 # ok 351 get_value.LCALTA.10
2325 05:21:19.876166 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2326 05:21:19.876683 # ok 352 name.LCALTA.10
2327 05:21:19.881699 # ok 353 write_default.LCALTA.10
2328 05:21:19.882213 # ok 354 write_valid.LCALTA.10
2329 05:21:19.887235 # ok 355 write_invalid.LCALTA.10
2330 05:21:19.887825 # ok 356 event_missing.LCALTA.10
2331 05:21:19.892837 # ok 357 event_spurious.LCALTA.10
2332 05:21:19.893430 # ok 358 get_value.LCALTA.9
2333 05:21:19.898339 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2334 05:21:19.898856 # ok 359 name.LCALTA.9
2335 05:21:19.903910 # ok 360 write_default.LCALTA.9
2336 05:21:19.904195 # ok 361 write_valid.LCALTA.9
2337 05:21:19.909445 # ok 362 write_invalid.LCALTA.9
2338 05:21:19.909981 # ok 363 event_missing.LCALTA.9
2339 05:21:19.915037 # ok 364 event_spurious.LCALTA.9
2340 05:21:19.915550 # ok 365 get_value.LCALTA.8
2341 05:21:19.920593 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2342 05:21:19.921114 # ok 366 name.LCALTA.8
2343 05:21:19.926200 # ok 367 write_default.LCALTA.8
2344 05:21:19.926706 # ok 368 write_valid.LCALTA.8
2345 05:21:19.931631 # ok 369 write_invalid.LCALTA.8
2346 05:21:19.932191 # ok 370 event_missing.LCALTA.8
2347 05:21:19.937106 # ok 371 event_spurious.LCALTA.8
2348 05:21:19.937648 # ok 372 get_value.LCALTA.7
2349 05:21:19.942691 # # LCALTA.7 ACODEC Unmute Ramp Switch
2350 05:21:19.942964 # ok 373 name.LCALTA.7
2351 05:21:19.948236 # ok 374 write_default.LCALTA.7
2352 05:21:19.948779 # ok 375 write_valid.LCALTA.7
2353 05:21:19.953788 # ok 376 write_invalid.LCALTA.7
2354 05:21:19.954324 # ok 377 event_missing.LCALTA.7
2355 05:21:19.959351 # ok 378 event_spurious.LCALTA.7
2356 05:21:19.959865 # ok 379 get_value.LCALTA.6
2357 05:21:19.964871 # # LCALTA.6 ACODEC Mute Ramp Switch
2358 05:21:19.965464 # ok 380 name.LCALTA.6
2359 05:21:19.970492 # ok 381 write_default.LCALTA.6
2360 05:21:19.971023 # ok 382 write_valid.LCALTA.6
2361 05:21:19.975916 # ok 383 write_invalid.LCALTA.6
2362 05:21:19.976233 # ok 384 event_missing.LCALTA.6
2363 05:21:19.981420 # ok 385 event_spurious.LCALTA.6
2364 05:21:19.981704 # ok 386 get_value.LCALTA.5
2365 05:21:19.987087 # # LCALTA.5 ACODEC Volume Ramp Switch
2366 05:21:19.987640 # ok 387 name.LCALTA.5
2367 05:21:19.992599 # ok 388 write_default.LCALTA.5
2368 05:21:19.992915 # ok 389 write_valid.LCALTA.5
2369 05:21:19.998452 # ok 390 write_invalid.LCALTA.5
2370 05:21:19.998778 # ok 391 event_missing.LCALTA.5
2371 05:21:20.003720 # ok 392 event_spurious.LCALTA.5
2372 05:21:20.004069 # ok 393 get_value.LCALTA.4
2373 05:21:20.009137 # # LCALTA.4 ACODEC Ramp Rate
2374 05:21:20.009455 # ok 394 name.LCALTA.4
2375 05:21:20.015234 # ok 395 write_default.LCALTA.4
2376 05:21:20.015601 # ok 396 write_valid.LCALTA.4
2377 05:21:20.020288 # ok 397 write_invalid.LCALTA.4
2378 05:21:20.020648 # ok 398 event_missing.LCALTA.4
2379 05:21:20.025916 # ok 399 event_spurious.LCALTA.4
2380 05:21:20.026275 # ok 400 get_value.LCALTA.3
2381 05:21:20.031354 # # LCALTA.3 ACODEC Playback Volume
2382 05:21:20.031699 # ok 401 name.LCALTA.3
2383 05:21:20.037130 # ok 402 write_default.LCALTA.3
2384 05:21:20.037470 # ok 403 write_valid.LCALTA.3
2385 05:21:20.042628 # ok 404 write_invalid.LCALTA.3
2386 05:21:20.042975 # ok 405 event_missing.LCALTA.3
2387 05:21:20.048420 # ok 406 event_spurious.LCALTA.3
2388 05:21:20.048772 # ok 407 get_value.LCALTA.2
2389 05:21:20.053561 # # LCALTA.2 ACODEC Playback Switch
2390 05:21:20.053971 # ok 408 name.LCALTA.2
2391 05:21:20.059165 # ok 409 write_default.LCALTA.2
2392 05:21:20.059744 # ok 410 write_valid.LCALTA.2
2393 05:21:20.064674 # ok 411 write_invalid.LCALTA.2
2394 05:21:20.065234 # ok 412 event_missing.LCALTA.2
2395 05:21:20.070157 # ok 413 event_spurious.LCALTA.2
2396 05:21:20.070657 # ok 414 get_value.LCALTA.1
2397 05:21:20.075725 # # LCALTA.1 ACODEC Playback Channel Mode
2398 05:21:20.076396 # ok 415 name.LCALTA.1
2399 05:21:20.081254 # ok 416 write_default.LCALTA.1
2400 05:21:20.081789 # ok 417 write_valid.LCALTA.1
2401 05:21:20.086813 # ok 418 write_invalid.LCALTA.1
2402 05:21:20.087367 # ok 419 event_missing.LCALTA.1
2403 05:21:20.092301 # ok 420 event_spurious.LCALTA.1
2404 05:21:20.092792 # ok 421 get_value.LCALTA.0
2405 05:21:20.097915 # # LCALTA.0 TOACODEC Lane Select
2406 05:21:20.098467 # ok 422 name.LCALTA.0
2407 05:21:20.103417 # ok 423 write_default.LCALTA.0
2408 05:21:20.103754 # ok 424 write_valid.LCALTA.0
2409 05:21:20.109171 # ok 425 write_invalid.LCALTA.0
2410 05:21:20.109885 # ok 426 event_missing.LCALTA.0
2411 05:21:20.114533 # ok 427 event_spurious.LCALTA.0
2412 05:21:20.120129 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2413 05:21:20.120675 ok 1 selftests: alsa: mixer-test
2414 05:21:20.125619 # timeout set to 45
2415 05:21:20.126148 # selftests: alsa: pcm-test
2416 05:21:20.126594 # TAP version 13
2417 05:21:20.131189 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2418 05:21:20.131737 # # LCALTA.0 - fe.dai-link-0 (*)
2419 05:21:20.136731 # # LCALTA.0 - fe.dai-link-1 (*)
2420 05:21:20.142244 # # LCALTA.0 - fe.dai-link-2 (*)
2421 05:21:20.142770 # # LCALTA.0 - fe.dai-link-3 (*)
2422 05:21:20.147831 # # LCALTA.0 - fe.dai-link-4 (*)
2423 05:21:20.148450 # # LCALTA.0 - fe.dai-link-5 (*)
2424 05:21:20.148896 # 1..42
2425 05:21:20.153421 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2426 05:21:20.158952 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2427 05:21:20.164444 # # snd_pcm_hw_params: Invalid argument
2428 05:21:20.170042 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2429 05:21:20.170536 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2430 05:21:20.175518 # # snd_pcm_hw_params: Invalid argument
2431 05:21:20.181100 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2432 05:21:20.186617 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2433 05:21:20.192181 # # snd_pcm_hw_params: Invalid argument
2434 05:21:20.197691 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2435 05:21:20.198177 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2436 05:21:20.203227 # # snd_pcm_hw_params: Invalid argument
2437 05:21:20.208812 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2438 05:21:20.214345 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2439 05:21:20.214829 # # snd_pcm_hw_params: Invalid argument
2440 05:21:20.225451 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2441 05:21:20.225942 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2442 05:21:20.231071 # # snd_pcm_hw_params: Invalid argument
2443 05:21:20.236535 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2444 05:21:20.242107 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2445 05:21:20.242591 # # snd_pcm_hw_params: Invalid argument
2446 05:21:20.247635 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2447 05:21:20.253281 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2448 05:21:20.258733 # # snd_pcm_hw_params: Invalid argument
2449 05:21:20.264310 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2450 05:21:20.269899 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2451 05:21:20.270611 # # snd_pcm_hw_params: Invalid argument
2452 05:21:20.275393 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2453 05:21:20.280951 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2454 05:21:20.286470 # # snd_pcm_hw_params: Invalid argument
2455 05:21:20.292135 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2456 05:21:20.292687 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2457 05:21:20.297616 # # snd_pcm_hw_params: Invalid argument
2458 05:21:20.303123 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2459 05:21:20.308662 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2460 05:21:20.314223 # # snd_pcm_hw_params: Invalid argument
2461 05:21:20.319758 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2462 05:21:20.320345 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2463 05:21:20.325309 # # snd_pcm_hw_params: Invalid argument
2464 05:21:20.330848 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2465 05:21:20.336397 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2466 05:21:20.341973 # # snd_pcm_hw_params: Invalid argument
2467 05:21:20.347483 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2468 05:21:20.348008 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2469 05:21:20.353084 # # snd_pcm_hw_params: Invalid argument
2470 05:21:20.358560 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2471 05:21:20.364186 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2472 05:21:20.364776 # # snd_pcm_hw_params: Invalid argument
2473 05:21:20.369676 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2474 05:21:20.375229 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2475 05:21:20.380763 # # snd_pcm_hw_params: Invalid argument
2476 05:21:20.386318 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2477 05:21:20.391859 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2478 05:21:20.392430 # # snd_pcm_hw_params: Invalid argument
2479 05:21:20.397395 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2480 05:21:20.402968 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2481 05:21:20.408516 # # snd_pcm_hw_params: Invalid argument
2482 05:21:20.414154 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2483 05:21:20.419658 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2484 05:21:20.420315 # # snd_pcm_hw_params: Invalid argument
2485 05:21:20.425132 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2486 05:21:20.430682 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2487 05:21:20.436248 # # snd_pcm_hw_params: Invalid argument
2488 05:21:20.441767 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2489 05:21:20.442272 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2490 05:21:20.447364 # # snd_pcm_hw_params: Invalid argument
2491 05:21:20.452867 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2492 05:21:20.458408 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2493 05:21:20.463958 # # snd_pcm_hw_params: Invalid argument
2494 05:21:20.469508 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2495 05:21:20.470021 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2496 05:21:20.475107 # # snd_pcm_hw_params: Invalid argument
2497 05:21:20.480610 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2498 05:21:20.486125 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2499 05:21:20.491742 # # snd_pcm_hw_params: Invalid argument
2500 05:21:20.497249 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2501 05:21:20.497758 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2502 05:21:20.502810 # # snd_pcm_hw_params: Invalid argument
2503 05:21:20.508362 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2504 05:21:20.513893 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2505 05:21:20.519426 # # snd_pcm_hw_params: Invalid argument
2506 05:21:20.525011 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2507 05:21:20.525528 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2508 05:21:20.530534 # # snd_pcm_hw_params: Invalid argument
2509 05:21:20.536234 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2510 05:21:20.541749 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2511 05:21:20.547178 # # snd_pcm_hw_params: Invalid argument
2512 05:21:20.552741 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2513 05:21:20.553262 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2514 05:21:20.558302 # # snd_pcm_hw_params: Invalid argument
2515 05:21:20.563846 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2516 05:21:20.569404 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2517 05:21:20.574921 # # snd_pcm_hw_params: Invalid argument
2518 05:21:20.580487 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2519 05:21:20.581012 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2520 05:21:20.586005 # # snd_pcm_hw_params: Invalid argument
2521 05:21:20.591574 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2522 05:21:20.597203 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2523 05:21:20.597825 # # snd_pcm_hw_params: Invalid argument
2524 05:21:20.608251 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2525 05:21:20.608849 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2526 05:21:20.613757 # # snd_pcm_hw_params: Invalid argument
2527 05:21:20.619301 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2528 05:21:20.624878 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2529 05:21:20.630478 # # snd_pcm_hw_params: Invalid argument
2530 05:21:20.636051 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2531 05:21:20.636579 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2532 05:21:20.641572 # # snd_pcm_hw_params: Invalid argument
2533 05:21:20.647132 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2534 05:21:20.652655 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2535 05:21:20.653168 # # snd_pcm_hw_params: Invalid argument
2536 05:21:20.663728 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2537 05:21:20.664285 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2538 05:21:20.669312 # # snd_pcm_hw_params: Invalid argument
2539 05:21:20.674835 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2540 05:21:20.680400 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2541 05:21:20.680917 # # snd_pcm_hw_params: Invalid argument
2542 05:21:20.685944 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2543 05:21:20.691505 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2544 05:21:20.697009 # # snd_pcm_hw_params: Invalid argument
2545 05:21:20.702592 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2546 05:21:20.708128 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2547 05:21:20.708642 # # snd_pcm_hw_params: Invalid argument
2548 05:21:20.713693 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2549 05:21:20.719255 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2550 05:21:20.724747 # # snd_pcm_hw_params: Invalid argument
2551 05:21:20.730301 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2552 05:21:20.730805 ok 2 selftests: alsa: pcm-test
2553 05:21:20.735849 # timeout set to 45
2554 05:21:20.736385 # selftests: alsa: test-pcmtest-driver
2555 05:21:20.741417 # TAP version 13
2556 05:21:20.741921 # 1..5
2557 05:21:20.742324 # # Starting 5 tests from 1 test cases.
2558 05:21:20.746923 # # RUN pcmtest.playback ...
2559 05:21:20.752502 # # SKIP Can't read patterns. Probably, module isn't loaded
2560 05:21:20.758021 # # OK pcmtest.playback
2561 05:21:20.763583 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2562 05:21:20.769257 # # RUN pcmtest.capture ...
2563 05:21:20.774654 # # SKIP Can't read patterns. Probably, module isn't loaded
2564 05:21:20.775161 # # OK pcmtest.capture
2565 05:21:20.785721 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2566 05:21:20.786249 # # RUN pcmtest.ni_capture ...
2567 05:21:20.791308 # # SKIP Can't read patterns. Probably, module isn't loaded
2568 05:21:20.796845 # # OK pcmtest.ni_capture
2569 05:21:20.802436 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2570 05:21:20.807950 # # RUN pcmtest.ni_playback ...
2571 05:21:20.813515 # # SKIP Can't read patterns. Probably, module isn't loaded
2572 05:21:20.819038 # # OK pcmtest.ni_playback
2573 05:21:20.824611 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2574 05:21:20.830246 # # RUN pcmtest.reset_ioctl ...
2575 05:21:20.835660 # # SKIP Can't read patterns. Probably, module isn't loaded
2576 05:21:20.836207 # # OK pcmtest.reset_ioctl
2577 05:21:20.846755 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2578 05:21:20.847282 # # PASSED: 5 / 5 tests passed.
2579 05:21:20.852359 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2580 05:21:20.857854 ok 3 selftests: alsa: test-pcmtest-driver
2581 05:21:20.858356 # timeout set to 45
2582 05:21:20.863429 # selftests: alsa: utimer-test
2583 05:21:20.863932 # TAP version 13
2584 05:21:20.864380 # 1..2
2585 05:21:20.868974 # # Starting 2 tests from 2 test cases.
2586 05:21:20.874523 # # RUN global.wrong_timers_test ...
2587 05:21:20.875018 # # OK global.wrong_timers_test
2588 05:21:20.880083 # ok 1 global.wrong_timers_test
2589 05:21:20.880592 # # RUN timer_f.utimer ...
2590 05:21:20.891234 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2591 05:21:20.896695 # # utimer: Test terminated by assertion
2592 05:21:20.897199 # # FAIL timer_f.utimer
2593 05:21:20.902251 # not ok 2 timer_f.utimer
2594 05:21:20.902758 # # FAILED: 1 / 2 tests passed.
2595 05:21:20.907793 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2596 05:21:20.913557 not ok 4 selftests: alsa: utimer-test # exit=1
2597 05:21:21.412408 alsa_mixer-test_get_value_LCALTA_60 pass
2598 05:21:21.417806 alsa_mixer-test_name_LCALTA_60 pass
2599 05:21:21.418370 alsa_mixer-test_write_default_LCALTA_60 pass
2600 05:21:21.423414 alsa_mixer-test_write_valid_LCALTA_60 pass
2601 05:21:21.428858 alsa_mixer-test_write_invalid_LCALTA_60 pass
2602 05:21:21.434504 alsa_mixer-test_event_missing_LCALTA_60 pass
2603 05:21:21.435044 alsa_mixer-test_event_spurious_LCALTA_60 pass
2604 05:21:21.440051 alsa_mixer-test_get_value_LCALTA_59 pass
2605 05:21:21.445527 alsa_mixer-test_name_LCALTA_59 pass
2606 05:21:21.446043 alsa_mixer-test_write_default_LCALTA_59 pass
2607 05:21:21.451131 alsa_mixer-test_write_valid_LCALTA_59 pass
2608 05:21:21.456622 alsa_mixer-test_write_invalid_LCALTA_59 pass
2609 05:21:21.457155 alsa_mixer-test_event_missing_LCALTA_59 pass
2610 05:21:21.462237 alsa_mixer-test_event_spurious_LCALTA_59 pass
2611 05:21:21.467706 alsa_mixer-test_get_value_LCALTA_58 pass
2612 05:21:21.468260 alsa_mixer-test_name_LCALTA_58 pass
2613 05:21:21.473385 alsa_mixer-test_write_default_LCALTA_58 pass
2614 05:21:21.478843 alsa_mixer-test_write_valid_LCALTA_58 pass
2615 05:21:21.479371 alsa_mixer-test_write_invalid_LCALTA_58 pass
2616 05:21:21.484378 alsa_mixer-test_event_missing_LCALTA_58 pass
2617 05:21:21.489884 alsa_mixer-test_event_spurious_LCALTA_58 pass
2618 05:21:21.495473 alsa_mixer-test_get_value_LCALTA_57 pass
2619 05:21:21.496023 alsa_mixer-test_name_LCALTA_57 pass
2620 05:21:21.501178 alsa_mixer-test_write_default_LCALTA_57 pass
2621 05:21:21.506620 alsa_mixer-test_write_valid_LCALTA_57 pass
2622 05:21:21.507106 alsa_mixer-test_write_invalid_LCALTA_57 pass
2623 05:21:21.512302 alsa_mixer-test_event_missing_LCALTA_57 pass
2624 05:21:21.517804 alsa_mixer-test_event_spurious_LCALTA_57 pass
2625 05:21:21.518356 alsa_mixer-test_get_value_LCALTA_56 pass
2626 05:21:21.523481 alsa_mixer-test_name_LCALTA_56 pass
2627 05:21:21.528913 alsa_mixer-test_write_default_LCALTA_56 pass
2628 05:21:21.529453 alsa_mixer-test_write_valid_LCALTA_56 pass
2629 05:21:21.534443 alsa_mixer-test_write_invalid_LCALTA_56 pass
2630 05:21:21.540109 alsa_mixer-test_event_missing_LCALTA_56 pass
2631 05:21:21.545570 alsa_mixer-test_event_spurious_LCALTA_56 pass
2632 05:21:21.546177 alsa_mixer-test_get_value_LCALTA_55 pass
2633 05:21:21.551028 alsa_mixer-test_name_LCALTA_55 pass
2634 05:21:21.556593 alsa_mixer-test_write_default_LCALTA_55 pass
2635 05:21:21.557174 alsa_mixer-test_write_valid_LCALTA_55 pass
2636 05:21:21.562157 alsa_mixer-test_write_invalid_LCALTA_55 pass
2637 05:21:21.567736 alsa_mixer-test_event_missing_LCALTA_55 pass
2638 05:21:21.568423 alsa_mixer-test_event_spurious_LCALTA_55 pass
2639 05:21:21.573269 alsa_mixer-test_get_value_LCALTA_54 pass
2640 05:21:21.578736 alsa_mixer-test_name_LCALTA_54 pass
2641 05:21:21.579358 alsa_mixer-test_write_default_LCALTA_54 pass
2642 05:21:21.584357 alsa_mixer-test_write_valid_LCALTA_54 pass
2643 05:21:21.589849 alsa_mixer-test_write_invalid_LCALTA_54 pass
2644 05:21:21.590420 alsa_mixer-test_event_missing_LCALTA_54 pass
2645 05:21:21.595368 alsa_mixer-test_event_spurious_LCALTA_54 pass
2646 05:21:21.600958 alsa_mixer-test_get_value_LCALTA_53 pass
2647 05:21:21.601531 alsa_mixer-test_name_LCALTA_53 pass
2648 05:21:21.606472 alsa_mixer-test_write_default_LCALTA_53 pass
2649 05:21:21.612058 alsa_mixer-test_write_valid_LCALTA_53 pass
2650 05:21:21.617518 alsa_mixer-test_write_invalid_LCALTA_53 pass
2651 05:21:21.618065 alsa_mixer-test_event_missing_LCALTA_53 pass
2652 05:21:21.623119 alsa_mixer-test_event_spurious_LCALTA_53 pass
2653 05:21:21.628677 alsa_mixer-test_get_value_LCALTA_52 pass
2654 05:21:21.629257 alsa_mixer-test_name_LCALTA_52 pass
2655 05:21:21.634233 alsa_mixer-test_write_default_LCALTA_52 pass
2656 05:21:21.639727 alsa_mixer-test_write_valid_LCALTA_52 pass
2657 05:21:21.640334 alsa_mixer-test_write_invalid_LCALTA_52 pass
2658 05:21:21.645321 alsa_mixer-test_event_missing_LCALTA_52 pass
2659 05:21:21.650803 alsa_mixer-test_event_spurious_LCALTA_52 pass
2660 05:21:21.651344 alsa_mixer-test_get_value_LCALTA_51 pass
2661 05:21:21.656317 alsa_mixer-test_name_LCALTA_51 pass
2662 05:21:21.661844 alsa_mixer-test_write_default_LCALTA_51 pass
2663 05:21:21.662382 alsa_mixer-test_write_valid_LCALTA_51 pass
2664 05:21:21.667405 alsa_mixer-test_write_invalid_LCALTA_51 pass
2665 05:21:21.672968 alsa_mixer-test_event_missing_LCALTA_51 pass
2666 05:21:21.678506 alsa_mixer-test_event_spurious_LCALTA_51 pass
2667 05:21:21.679059 alsa_mixer-test_get_value_LCALTA_50 pass
2668 05:21:21.684077 alsa_mixer-test_name_LCALTA_50 pass
2669 05:21:21.689611 alsa_mixer-test_write_default_LCALTA_50 pass
2670 05:21:21.690153 alsa_mixer-test_write_valid_LCALTA_50 pass
2671 05:21:21.695166 alsa_mixer-test_write_invalid_LCALTA_50 pass
2672 05:21:21.700673 alsa_mixer-test_event_missing_LCALTA_50 pass
2673 05:21:21.701218 alsa_mixer-test_event_spurious_LCALTA_50 pass
2674 05:21:21.706278 alsa_mixer-test_get_value_LCALTA_49 pass
2675 05:21:21.711838 alsa_mixer-test_name_LCALTA_49 pass
2676 05:21:21.712424 alsa_mixer-test_write_default_LCALTA_49 pass
2677 05:21:21.717423 alsa_mixer-test_write_valid_LCALTA_49 pass
2678 05:21:21.722932 alsa_mixer-test_write_invalid_LCALTA_49 pass
2679 05:21:21.728514 alsa_mixer-test_event_missing_LCALTA_49 pass
2680 05:21:21.729092 alsa_mixer-test_event_spurious_LCALTA_49 pass
2681 05:21:21.733993 alsa_mixer-test_get_value_LCALTA_48 pass
2682 05:21:21.734530 alsa_mixer-test_name_LCALTA_48 pass
2683 05:21:21.739526 alsa_mixer-test_write_default_LCALTA_48 pass
2684 05:21:21.745091 alsa_mixer-test_write_valid_LCALTA_48 pass
2685 05:21:21.750661 alsa_mixer-test_write_invalid_LCALTA_48 pass
2686 05:21:21.751219 alsa_mixer-test_event_missing_LCALTA_48 pass
2687 05:21:21.756252 alsa_mixer-test_event_spurious_LCALTA_48 pass
2688 05:21:21.761803 alsa_mixer-test_get_value_LCALTA_47 pass
2689 05:21:21.762328 alsa_mixer-test_name_LCALTA_47 pass
2690 05:21:21.767382 alsa_mixer-test_write_default_LCALTA_47 pass
2691 05:21:21.772870 alsa_mixer-test_write_valid_LCALTA_47 pass
2692 05:21:21.773379 alsa_mixer-test_write_invalid_LCALTA_47 pass
2693 05:21:21.778421 alsa_mixer-test_event_missing_LCALTA_47 pass
2694 05:21:21.783939 alsa_mixer-test_event_spurious_LCALTA_47 pass
2695 05:21:21.789507 alsa_mixer-test_get_value_LCALTA_46 pass
2696 05:21:21.790020 alsa_mixer-test_name_LCALTA_46 pass
2697 05:21:21.795082 alsa_mixer-test_write_default_LCALTA_46 pass
2698 05:21:21.800569 alsa_mixer-test_write_valid_LCALTA_46 pass
2699 05:21:21.801101 alsa_mixer-test_write_invalid_LCALTA_46 pass
2700 05:21:21.806072 alsa_mixer-test_event_missing_LCALTA_46 pass
2701 05:21:21.811664 alsa_mixer-test_event_spurious_LCALTA_46 pass
2702 05:21:21.812270 alsa_mixer-test_get_value_LCALTA_45 pass
2703 05:21:21.817337 alsa_mixer-test_name_LCALTA_45 pass
2704 05:21:21.822730 alsa_mixer-test_write_default_LCALTA_45 pass
2705 05:21:21.823245 alsa_mixer-test_write_valid_LCALTA_45 pass
2706 05:21:21.828350 alsa_mixer-test_write_invalid_LCALTA_45 pass
2707 05:21:21.833869 alsa_mixer-test_event_missing_LCALTA_45 pass
2708 05:21:21.834321 alsa_mixer-test_event_spurious_LCALTA_45 pass
2709 05:21:21.839394 alsa_mixer-test_get_value_LCALTA_44 pass
2710 05:21:21.844921 alsa_mixer-test_name_LCALTA_44 pass
2711 05:21:21.845373 alsa_mixer-test_write_default_LCALTA_44 pass
2712 05:21:21.850484 alsa_mixer-test_write_valid_LCALTA_44 pass
2713 05:21:21.856049 alsa_mixer-test_write_invalid_LCALTA_44 pass
2714 05:21:21.861596 alsa_mixer-test_event_missing_LCALTA_44 pass
2715 05:21:21.862067 alsa_mixer-test_event_spurious_LCALTA_44 pass
2716 05:21:21.867144 alsa_mixer-test_get_value_LCALTA_43 pass
2717 05:21:21.872687 alsa_mixer-test_name_LCALTA_43 pass
2718 05:21:21.873155 alsa_mixer-test_write_default_LCALTA_43 pass
2719 05:21:21.878224 alsa_mixer-test_write_valid_LCALTA_43 pass
2720 05:21:21.883815 alsa_mixer-test_write_invalid_LCALTA_43 pass
2721 05:21:21.884316 alsa_mixer-test_event_missing_LCALTA_43 pass
2722 05:21:21.889399 alsa_mixer-test_event_spurious_LCALTA_43 pass
2723 05:21:21.894857 alsa_mixer-test_get_value_LCALTA_42 pass
2724 05:21:21.895308 alsa_mixer-test_name_LCALTA_42 pass
2725 05:21:21.900403 alsa_mixer-test_write_default_LCALTA_42 pass
2726 05:21:21.905943 alsa_mixer-test_write_valid_LCALTA_42 pass
2727 05:21:21.906398 alsa_mixer-test_write_invalid_LCALTA_42 pass
2728 05:21:21.911492 alsa_mixer-test_event_missing_LCALTA_42 pass
2729 05:21:21.917067 alsa_mixer-test_event_spurious_LCALTA_42 pass
2730 05:21:21.922596 alsa_mixer-test_get_value_LCALTA_41 pass
2731 05:21:21.923057 alsa_mixer-test_name_LCALTA_41 pass
2732 05:21:21.928205 alsa_mixer-test_write_default_LCALTA_41 pass
2733 05:21:21.933687 alsa_mixer-test_write_valid_LCALTA_41 pass
2734 05:21:21.934146 alsa_mixer-test_write_invalid_LCALTA_41 pass
2735 05:21:21.939265 alsa_mixer-test_event_missing_LCALTA_41 pass
2736 05:21:21.944803 alsa_mixer-test_event_spurious_LCALTA_41 pass
2737 05:21:21.945279 alsa_mixer-test_get_value_LCALTA_40 pass
2738 05:21:21.950390 alsa_mixer-test_name_LCALTA_40 pass
2739 05:21:21.955908 alsa_mixer-test_write_default_LCALTA_40 pass
2740 05:21:21.956405 alsa_mixer-test_write_valid_LCALTA_40 pass
2741 05:21:21.961443 alsa_mixer-test_write_invalid_LCALTA_40 pass
2742 05:21:21.966979 alsa_mixer-test_event_missing_LCALTA_40 pass
2743 05:21:21.972493 alsa_mixer-test_event_spurious_LCALTA_40 pass
2744 05:21:21.972948 alsa_mixer-test_get_value_LCALTA_39 pass
2745 05:21:21.978074 alsa_mixer-test_name_LCALTA_39 pass
2746 05:21:21.983648 alsa_mixer-test_write_default_LCALTA_39 pass
2747 05:21:21.984121 alsa_mixer-test_write_valid_LCALTA_39 pass
2748 05:21:21.989152 alsa_mixer-test_write_invalid_LCALTA_39 pass
2749 05:21:21.994691 alsa_mixer-test_event_missing_LCALTA_39 pass
2750 05:21:21.995139 alsa_mixer-test_event_spurious_LCALTA_39 pass
2751 05:21:22.000264 alsa_mixer-test_get_value_LCALTA_38 pass
2752 05:21:22.005790 alsa_mixer-test_name_LCALTA_38 pass
2753 05:21:22.006244 alsa_mixer-test_write_default_LCALTA_38 pass
2754 05:21:22.011380 alsa_mixer-test_write_valid_LCALTA_38 pass
2755 05:21:22.016925 alsa_mixer-test_write_invalid_LCALTA_38 pass
2756 05:21:22.017389 alsa_mixer-test_event_missing_LCALTA_38 pass
2757 05:21:22.022478 alsa_mixer-test_event_spurious_LCALTA_38 pass
2758 05:21:22.028002 alsa_mixer-test_get_value_LCALTA_37 pass
2759 05:21:22.028472 alsa_mixer-test_name_LCALTA_37 pass
2760 05:21:22.033497 alsa_mixer-test_write_default_LCALTA_37 pass
2761 05:21:22.039052 alsa_mixer-test_write_valid_LCALTA_37 pass
2762 05:21:22.044573 alsa_mixer-test_write_invalid_LCALTA_37 pass
2763 05:21:22.045029 alsa_mixer-test_event_missing_LCALTA_37 pass
2764 05:21:22.050125 alsa_mixer-test_event_spurious_LCALTA_37 pass
2765 05:21:22.055671 alsa_mixer-test_get_value_LCALTA_36 pass
2766 05:21:22.056156 alsa_mixer-test_name_LCALTA_36 pass
2767 05:21:22.061215 alsa_mixer-test_write_default_LCALTA_36 pass
2768 05:21:22.066800 alsa_mixer-test_write_valid_LCALTA_36 pass
2769 05:21:22.067268 alsa_mixer-test_write_invalid_LCALTA_36 pass
2770 05:21:22.072358 alsa_mixer-test_event_missing_LCALTA_36 pass
2771 05:21:22.077872 alsa_mixer-test_event_spurious_LCALTA_36 pass
2772 05:21:22.078318 alsa_mixer-test_get_value_LCALTA_35 pass
2773 05:21:22.083411 alsa_mixer-test_name_LCALTA_35 pass
2774 05:21:22.088955 alsa_mixer-test_write_default_LCALTA_35 pass
2775 05:21:22.089396 alsa_mixer-test_write_valid_LCALTA_35 pass
2776 05:21:22.094497 alsa_mixer-test_write_invalid_LCALTA_35 pass
2777 05:21:22.100083 alsa_mixer-test_event_missing_LCALTA_35 pass
2778 05:21:22.105609 alsa_mixer-test_event_spurious_LCALTA_35 pass
2779 05:21:22.106065 alsa_mixer-test_get_value_LCALTA_34 pass
2780 05:21:22.111160 alsa_mixer-test_name_LCALTA_34 pass
2781 05:21:22.116701 alsa_mixer-test_write_default_LCALTA_34 pass
2782 05:21:22.117158 alsa_mixer-test_write_valid_LCALTA_34 pass
2783 05:21:22.122349 alsa_mixer-test_write_invalid_LCALTA_34 pass
2784 05:21:22.127772 alsa_mixer-test_event_missing_LCALTA_34 pass
2785 05:21:22.128250 alsa_mixer-test_event_spurious_LCALTA_34 pass
2786 05:21:22.133376 alsa_mixer-test_get_value_LCALTA_33 pass
2787 05:21:22.138885 alsa_mixer-test_name_LCALTA_33 pass
2788 05:21:22.139341 alsa_mixer-test_write_default_LCALTA_33 pass
2789 05:21:22.144434 alsa_mixer-test_write_valid_LCALTA_33 pass
2790 05:21:22.149986 alsa_mixer-test_write_invalid_LCALTA_33 pass
2791 05:21:22.155526 alsa_mixer-test_event_missing_LCALTA_33 pass
2792 05:21:22.156020 alsa_mixer-test_event_spurious_LCALTA_33 pass
2793 05:21:22.161070 alsa_mixer-test_get_value_LCALTA_32 pass
2794 05:21:22.161522 alsa_mixer-test_name_LCALTA_32 pass
2795 05:21:22.166599 alsa_mixer-test_write_default_LCALTA_32 pass
2796 05:21:22.172189 alsa_mixer-test_write_valid_LCALTA_32 pass
2797 05:21:22.177719 alsa_mixer-test_write_invalid_LCALTA_32 pass
2798 05:21:22.178167 alsa_mixer-test_event_missing_LCALTA_32 pass
2799 05:21:22.183383 alsa_mixer-test_event_spurious_LCALTA_32 pass
2800 05:21:22.188818 alsa_mixer-test_get_value_LCALTA_31 pass
2801 05:21:22.189273 alsa_mixer-test_name_LCALTA_31 pass
2802 05:21:22.194377 alsa_mixer-test_write_default_LCALTA_31 pass
2803 05:21:22.199910 alsa_mixer-test_write_valid_LCALTA_31 pass
2804 05:21:22.200407 alsa_mixer-test_write_invalid_LCALTA_31 pass
2805 05:21:22.205451 alsa_mixer-test_event_missing_LCALTA_31 pass
2806 05:21:22.211001 alsa_mixer-test_event_spurious_LCALTA_31 pass
2807 05:21:22.216545 alsa_mixer-test_get_value_LCALTA_30 pass
2808 05:21:22.216999 alsa_mixer-test_name_LCALTA_30 pass
2809 05:21:22.222088 alsa_mixer-test_write_default_LCALTA_30 pass
2810 05:21:22.227628 alsa_mixer-test_write_valid_LCALTA_30 pass
2811 05:21:22.228101 alsa_mixer-test_write_invalid_LCALTA_30 pass
2812 05:21:22.233253 alsa_mixer-test_event_missing_LCALTA_30 pass
2813 05:21:22.238736 alsa_mixer-test_event_spurious_LCALTA_30 pass
2814 05:21:22.239184 alsa_mixer-test_get_value_LCALTA_29 pass
2815 05:21:22.244357 alsa_mixer-test_name_LCALTA_29 pass
2816 05:21:22.249824 alsa_mixer-test_write_default_LCALTA_29 pass
2817 05:21:22.250271 alsa_mixer-test_write_valid_LCALTA_29 pass
2818 05:21:22.255372 alsa_mixer-test_write_invalid_LCALTA_29 pass
2819 05:21:22.260920 alsa_mixer-test_event_missing_LCALTA_29 pass
2820 05:21:22.261391 alsa_mixer-test_event_spurious_LCALTA_29 pass
2821 05:21:22.266456 alsa_mixer-test_get_value_LCALTA_28 pass
2822 05:21:22.272030 alsa_mixer-test_name_LCALTA_28 pass
2823 05:21:22.272483 alsa_mixer-test_write_default_LCALTA_28 pass
2824 05:21:22.277548 alsa_mixer-test_write_valid_LCALTA_28 pass
2825 05:21:22.283071 alsa_mixer-test_write_invalid_LCALTA_28 pass
2826 05:21:22.288637 alsa_mixer-test_event_missing_LCALTA_28 pass
2827 05:21:22.289095 alsa_mixer-test_event_spurious_LCALTA_28 pass
2828 05:21:22.294271 alsa_mixer-test_get_value_LCALTA_27 pass
2829 05:21:22.299758 alsa_mixer-test_name_LCALTA_27 pass
2830 05:21:22.300256 alsa_mixer-test_write_default_LCALTA_27 pass
2831 05:21:22.305390 alsa_mixer-test_write_valid_LCALTA_27 pass
2832 05:21:22.310837 alsa_mixer-test_write_invalid_LCALTA_27 pass
2833 05:21:22.311276 alsa_mixer-test_event_missing_LCALTA_27 pass
2834 05:21:22.316396 alsa_mixer-test_event_spurious_LCALTA_27 pass
2835 05:21:22.321919 alsa_mixer-test_get_value_LCALTA_26 pass
2836 05:21:22.322377 alsa_mixer-test_name_LCALTA_26 pass
2837 05:21:22.327473 alsa_mixer-test_write_default_LCALTA_26 skip
2838 05:21:22.333038 alsa_mixer-test_write_valid_LCALTA_26 skip
2839 05:21:22.333554 alsa_mixer-test_write_invalid_LCALTA_26 skip
2840 05:21:22.338538 alsa_mixer-test_event_missing_LCALTA_26 pass
2841 05:21:22.344077 alsa_mixer-test_event_spurious_LCALTA_26 pass
2842 05:21:22.349638 alsa_mixer-test_get_value_LCALTA_25 pass
2843 05:21:22.350095 alsa_mixer-test_name_LCALTA_25 pass
2844 05:21:22.355290 alsa_mixer-test_write_default_LCALTA_25 pass
2845 05:21:22.360761 alsa_mixer-test_write_valid_LCALTA_25 skip
2846 05:21:22.361227 alsa_mixer-test_write_invalid_LCALTA_25 skip
2847 05:21:22.366404 alsa_mixer-test_event_missing_LCALTA_25 pass
2848 05:21:22.371851 alsa_mixer-test_event_spurious_LCALTA_25 pass
2849 05:21:22.372358 alsa_mixer-test_get_value_LCALTA_24 pass
2850 05:21:22.377392 alsa_mixer-test_name_LCALTA_24 pass
2851 05:21:22.382954 alsa_mixer-test_write_default_LCALTA_24 skip
2852 05:21:22.383429 alsa_mixer-test_write_valid_LCALTA_24 skip
2853 05:21:22.388485 alsa_mixer-test_write_invalid_LCALTA_24 skip
2854 05:21:22.394034 alsa_mixer-test_event_missing_LCALTA_24 pass
2855 05:21:22.399581 alsa_mixer-test_event_spurious_LCALTA_24 pass
2856 05:21:22.400063 alsa_mixer-test_get_value_LCALTA_23 pass
2857 05:21:22.405145 alsa_mixer-test_name_LCALTA_23 pass
2858 05:21:22.410671 alsa_mixer-test_write_default_LCALTA_23 skip
2859 05:21:22.411120 alsa_mixer-test_write_valid_LCALTA_23 skip
2860 05:21:22.416264 alsa_mixer-test_write_invalid_LCALTA_23 skip
2861 05:21:22.421766 alsa_mixer-test_event_missing_LCALTA_23 pass
2862 05:21:22.422215 alsa_mixer-test_event_spurious_LCALTA_23 pass
2863 05:21:22.427374 alsa_mixer-test_get_value_LCALTA_22 pass
2864 05:21:22.433019 alsa_mixer-test_name_LCALTA_22 pass
2865 05:21:22.433534 alsa_mixer-test_write_default_LCALTA_22 pass
2866 05:21:22.438432 alsa_mixer-test_write_valid_LCALTA_22 pass
2867 05:21:22.443965 alsa_mixer-test_write_invalid_LCALTA_22 pass
2868 05:21:22.444498 alsa_mixer-test_event_missing_LCALTA_22 pass
2869 05:21:22.449479 alsa_mixer-test_event_spurious_LCALTA_22 pass
2870 05:21:22.455026 alsa_mixer-test_get_value_LCALTA_21 pass
2871 05:21:22.455472 alsa_mixer-test_name_LCALTA_21 pass
2872 05:21:22.460572 alsa_mixer-test_write_default_LCALTA_21 pass
2873 05:21:22.466125 alsa_mixer-test_write_valid_LCALTA_21 pass
2874 05:21:22.471669 alsa_mixer-test_write_invalid_LCALTA_21 pass
2875 05:21:22.472148 alsa_mixer-test_event_missing_LCALTA_21 pass
2876 05:21:22.477258 alsa_mixer-test_event_spurious_LCALTA_21 pass
2877 05:21:22.482754 alsa_mixer-test_get_value_LCALTA_20 pass
2878 05:21:22.483191 alsa_mixer-test_name_LCALTA_20 pass
2879 05:21:22.488429 alsa_mixer-test_write_default_LCALTA_20 pass
2880 05:21:22.493940 alsa_mixer-test_write_valid_LCALTA_20 pass
2881 05:21:22.494386 alsa_mixer-test_write_invalid_LCALTA_20 pass
2882 05:21:22.499457 alsa_mixer-test_event_missing_LCALTA_20 pass
2883 05:21:22.504978 alsa_mixer-test_event_spurious_LCALTA_20 pass
2884 05:21:22.505440 alsa_mixer-test_get_value_LCALTA_19 pass
2885 05:21:22.510498 alsa_mixer-test_name_LCALTA_19 pass
2886 05:21:22.516064 alsa_mixer-test_write_default_LCALTA_19 pass
2887 05:21:22.516520 alsa_mixer-test_write_valid_LCALTA_19 pass
2888 05:21:22.521574 alsa_mixer-test_write_invalid_LCALTA_19 pass
2889 05:21:22.527176 alsa_mixer-test_event_missing_LCALTA_19 pass
2890 05:21:22.532737 alsa_mixer-test_event_spurious_LCALTA_19 pass
2891 05:21:22.533263 alsa_mixer-test_get_value_LCALTA_18 pass
2892 05:21:22.538294 alsa_mixer-test_name_LCALTA_18 pass
2893 05:21:22.543793 alsa_mixer-test_write_default_LCALTA_18 pass
2894 05:21:22.544280 alsa_mixer-test_write_valid_LCALTA_18 pass
2895 05:21:22.549465 alsa_mixer-test_write_invalid_LCALTA_18 pass
2896 05:21:22.554872 alsa_mixer-test_event_missing_LCALTA_18 pass
2897 05:21:22.555340 alsa_mixer-test_event_spurious_LCALTA_18 pass
2898 05:21:22.560460 alsa_mixer-test_get_value_LCALTA_17 pass
2899 05:21:22.565966 alsa_mixer-test_name_LCALTA_17 pass
2900 05:21:22.566419 alsa_mixer-test_write_default_LCALTA_17 pass
2901 05:21:22.571519 alsa_mixer-test_write_valid_LCALTA_17 pass
2902 05:21:22.577060 alsa_mixer-test_write_invalid_LCALTA_17 pass
2903 05:21:22.582589 alsa_mixer-test_event_missing_LCALTA_17 pass
2904 05:21:22.583028 alsa_mixer-test_event_spurious_LCALTA_17 pass
2905 05:21:22.588196 alsa_mixer-test_get_value_LCALTA_16 pass
2906 05:21:22.588637 alsa_mixer-test_name_LCALTA_16 pass
2907 05:21:22.593671 alsa_mixer-test_write_default_LCALTA_16 pass
2908 05:21:22.599291 alsa_mixer-test_write_valid_LCALTA_16 pass
2909 05:21:22.604792 alsa_mixer-test_write_invalid_LCALTA_16 pass
2910 05:21:22.605235 alsa_mixer-test_event_missing_LCALTA_16 pass
2911 05:21:22.610435 alsa_mixer-test_event_spurious_LCALTA_16 pass
2912 05:21:22.615882 alsa_mixer-test_get_value_LCALTA_15 pass
2913 05:21:22.616357 alsa_mixer-test_name_LCALTA_15 pass
2914 05:21:22.621476 alsa_mixer-test_write_default_LCALTA_15 pass
2915 05:21:22.626986 alsa_mixer-test_write_valid_LCALTA_15 pass
2916 05:21:22.627425 alsa_mixer-test_write_invalid_LCALTA_15 pass
2917 05:21:22.632650 alsa_mixer-test_event_missing_LCALTA_15 pass
2918 05:21:22.638091 alsa_mixer-test_event_spurious_LCALTA_15 pass
2919 05:21:22.643629 alsa_mixer-test_get_value_LCALTA_14 pass
2920 05:21:22.644108 alsa_mixer-test_name_LCALTA_14 pass
2921 05:21:22.649180 alsa_mixer-test_write_default_LCALTA_14 pass
2922 05:21:22.654716 alsa_mixer-test_write_valid_LCALTA_14 pass
2923 05:21:22.655152 alsa_mixer-test_write_invalid_LCALTA_14 pass
2924 05:21:22.660299 alsa_mixer-test_event_missing_LCALTA_14 pass
2925 05:21:22.665815 alsa_mixer-test_event_spurious_LCALTA_14 pass
2926 05:21:22.666261 alsa_mixer-test_get_value_LCALTA_13 pass
2927 05:21:22.671437 alsa_mixer-test_name_LCALTA_13 pass
2928 05:21:22.676911 alsa_mixer-test_write_default_LCALTA_13 pass
2929 05:21:22.677348 alsa_mixer-test_write_valid_LCALTA_13 pass
2930 05:21:22.682462 alsa_mixer-test_write_invalid_LCALTA_13 pass
2931 05:21:22.688026 alsa_mixer-test_event_missing_LCALTA_13 pass
2932 05:21:22.688471 alsa_mixer-test_event_spurious_LCALTA_13 pass
2933 05:21:22.693566 alsa_mixer-test_get_value_LCALTA_12 pass
2934 05:21:22.699077 alsa_mixer-test_name_LCALTA_12 pass
2935 05:21:22.699528 alsa_mixer-test_write_default_LCALTA_12 pass
2936 05:21:22.704641 alsa_mixer-test_write_valid_LCALTA_12 pass
2937 05:21:22.710183 alsa_mixer-test_write_invalid_LCALTA_12 pass
2938 05:21:22.715724 alsa_mixer-test_event_missing_LCALTA_12 pass
2939 05:21:22.716209 alsa_mixer-test_event_spurious_LCALTA_12 pass
2940 05:21:22.721322 alsa_mixer-test_get_value_LCALTA_11 pass
2941 05:21:22.726825 alsa_mixer-test_name_LCALTA_11 pass
2942 05:21:22.727263 alsa_mixer-test_write_default_LCALTA_11 pass
2943 05:21:22.732478 alsa_mixer-test_write_valid_LCALTA_11 pass
2944 05:21:22.737923 alsa_mixer-test_write_invalid_LCALTA_11 pass
2945 05:21:22.738372 alsa_mixer-test_event_missing_LCALTA_11 pass
2946 05:21:22.743479 alsa_mixer-test_event_spurious_LCALTA_11 pass
2947 05:21:22.749013 alsa_mixer-test_get_value_LCALTA_10 pass
2948 05:21:22.749462 alsa_mixer-test_name_LCALTA_10 pass
2949 05:21:22.754553 alsa_mixer-test_write_default_LCALTA_10 pass
2950 05:21:22.760125 alsa_mixer-test_write_valid_LCALTA_10 pass
2951 05:21:22.760562 alsa_mixer-test_write_invalid_LCALTA_10 pass
2952 05:21:22.765641 alsa_mixer-test_event_missing_LCALTA_10 pass
2953 05:21:22.771194 alsa_mixer-test_event_spurious_LCALTA_10 pass
2954 05:21:22.776748 alsa_mixer-test_get_value_LCALTA_9 pass
2955 05:21:22.777197 alsa_mixer-test_name_LCALTA_9 pass
2956 05:21:22.782325 alsa_mixer-test_write_default_LCALTA_9 pass
2957 05:21:22.787851 alsa_mixer-test_write_valid_LCALTA_9 pass
2958 05:21:22.788325 alsa_mixer-test_write_invalid_LCALTA_9 pass
2959 05:21:22.793467 alsa_mixer-test_event_missing_LCALTA_9 pass
2960 05:21:22.798931 alsa_mixer-test_event_spurious_LCALTA_9 pass
2961 05:21:22.799370 alsa_mixer-test_get_value_LCALTA_8 pass
2962 05:21:22.804499 alsa_mixer-test_name_LCALTA_8 pass
2963 05:21:22.810031 alsa_mixer-test_write_default_LCALTA_8 pass
2964 05:21:22.810464 alsa_mixer-test_write_valid_LCALTA_8 pass
2965 05:21:22.815568 alsa_mixer-test_write_invalid_LCALTA_8 pass
2966 05:21:22.821105 alsa_mixer-test_event_missing_LCALTA_8 pass
2967 05:21:22.821548 alsa_mixer-test_event_spurious_LCALTA_8 pass
2968 05:21:22.826656 alsa_mixer-test_get_value_LCALTA_7 pass
2969 05:21:22.832234 alsa_mixer-test_name_LCALTA_7 pass
2970 05:21:22.832744 alsa_mixer-test_write_default_LCALTA_7 pass
2971 05:21:22.837745 alsa_mixer-test_write_valid_LCALTA_7 pass
2972 05:21:22.843307 alsa_mixer-test_write_invalid_LCALTA_7 pass
2973 05:21:22.843752 alsa_mixer-test_event_missing_LCALTA_7 pass
2974 05:21:22.848833 alsa_mixer-test_event_spurious_LCALTA_7 pass
2975 05:21:22.854486 alsa_mixer-test_get_value_LCALTA_6 pass
2976 05:21:22.854920 alsa_mixer-test_name_LCALTA_6 pass
2977 05:21:22.859940 alsa_mixer-test_write_default_LCALTA_6 pass
2978 05:21:22.865494 alsa_mixer-test_write_valid_LCALTA_6 pass
2979 05:21:22.865935 alsa_mixer-test_write_invalid_LCALTA_6 pass
2980 05:21:22.871031 alsa_mixer-test_event_missing_LCALTA_6 pass
2981 05:21:22.876583 alsa_mixer-test_event_spurious_LCALTA_6 pass
2982 05:21:22.877024 alsa_mixer-test_get_value_LCALTA_5 pass
2983 05:21:22.882125 alsa_mixer-test_name_LCALTA_5 pass
2984 05:21:22.887669 alsa_mixer-test_write_default_LCALTA_5 pass
2985 05:21:22.888130 alsa_mixer-test_write_valid_LCALTA_5 pass
2986 05:21:22.893222 alsa_mixer-test_write_invalid_LCALTA_5 pass
2987 05:21:22.898745 alsa_mixer-test_event_missing_LCALTA_5 pass
2988 05:21:22.899202 alsa_mixer-test_event_spurious_LCALTA_5 pass
2989 05:21:22.904327 alsa_mixer-test_get_value_LCALTA_4 pass
2990 05:21:22.909855 alsa_mixer-test_name_LCALTA_4 pass
2991 05:21:22.910293 alsa_mixer-test_write_default_LCALTA_4 pass
2992 05:21:22.915458 alsa_mixer-test_write_valid_LCALTA_4 pass
2993 05:21:22.920959 alsa_mixer-test_write_invalid_LCALTA_4 pass
2994 05:21:22.921401 alsa_mixer-test_event_missing_LCALTA_4 pass
2995 05:21:22.926503 alsa_mixer-test_event_spurious_LCALTA_4 pass
2996 05:21:22.932108 alsa_mixer-test_get_value_LCALTA_3 pass
2997 05:21:22.932614 alsa_mixer-test_name_LCALTA_3 pass
2998 05:21:22.937585 alsa_mixer-test_write_default_LCALTA_3 pass
2999 05:21:22.943131 alsa_mixer-test_write_valid_LCALTA_3 pass
3000 05:21:22.943571 alsa_mixer-test_write_invalid_LCALTA_3 pass
3001 05:21:22.948672 alsa_mixer-test_event_missing_LCALTA_3 pass
3002 05:21:22.954217 alsa_mixer-test_event_spurious_LCALTA_3 pass
3003 05:21:22.954652 alsa_mixer-test_get_value_LCALTA_2 pass
3004 05:21:22.959749 alsa_mixer-test_name_LCALTA_2 pass
3005 05:21:22.965329 alsa_mixer-test_write_default_LCALTA_2 pass
3006 05:21:22.965779 alsa_mixer-test_write_valid_LCALTA_2 pass
3007 05:21:22.970868 alsa_mixer-test_write_invalid_LCALTA_2 pass
3008 05:21:22.976478 alsa_mixer-test_event_missing_LCALTA_2 pass
3009 05:21:22.981971 alsa_mixer-test_event_spurious_LCALTA_2 pass
3010 05:21:22.982402 alsa_mixer-test_get_value_LCALTA_1 pass
3011 05:21:22.987508 alsa_mixer-test_name_LCALTA_1 pass
3012 05:21:22.987937 alsa_mixer-test_write_default_LCALTA_1 pass
3013 05:21:22.993047 alsa_mixer-test_write_valid_LCALTA_1 pass
3014 05:21:22.998612 alsa_mixer-test_write_invalid_LCALTA_1 pass
3015 05:21:23.004193 alsa_mixer-test_event_missing_LCALTA_1 pass
3016 05:21:23.004633 alsa_mixer-test_event_spurious_LCALTA_1 pass
3017 05:21:23.009769 alsa_mixer-test_get_value_LCALTA_0 pass
3018 05:21:23.010209 alsa_mixer-test_name_LCALTA_0 pass
3019 05:21:23.015308 alsa_mixer-test_write_default_LCALTA_0 pass
3020 05:21:23.020850 alsa_mixer-test_write_valid_LCALTA_0 pass
3021 05:21:23.026418 alsa_mixer-test_write_invalid_LCALTA_0 pass
3022 05:21:23.026852 alsa_mixer-test_event_missing_LCALTA_0 pass
3023 05:21:23.031921 alsa_mixer-test_event_spurious_LCALTA_0 pass
3024 05:21:23.032463 alsa_mixer-test pass
3025 05:21:23.037482 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
3026 05:21:23.042971 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
3027 05:21:23.048507 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
3028 05:21:23.054050 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
3029 05:21:23.054472 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
3030 05:21:23.059588 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
3031 05:21:23.065174 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
3032 05:21:23.070705 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
3033 05:21:23.076268 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
3034 05:21:23.081802 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
3035 05:21:23.082233 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
3036 05:21:23.087337 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
3037 05:21:23.092909 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
3038 05:21:23.098495 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
3039 05:21:23.104021 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
3040 05:21:23.109536 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
3041 05:21:23.109970 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
3042 05:21:23.115094 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
3043 05:21:23.120617 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
3044 05:21:23.126181 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
3045 05:21:23.131751 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
3046 05:21:23.137291 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
3047 05:21:23.137726 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
3048 05:21:23.142819 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
3049 05:21:23.148360 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
3050 05:21:23.153885 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
3051 05:21:23.159472 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
3052 05:21:23.164997 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
3053 05:21:23.165426 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
3054 05:21:23.170551 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
3055 05:21:23.176097 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
3056 05:21:23.181634 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
3057 05:21:23.187189 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
3058 05:21:23.192731 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
3059 05:21:23.198289 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
3060 05:21:23.198717 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
3061 05:21:23.203834 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
3062 05:21:23.209370 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
3063 05:21:23.214904 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
3064 05:21:23.220492 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
3065 05:21:23.226012 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
3066 05:21:23.226435 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
3067 05:21:23.231571 alsa_pcm-test pass
3068 05:21:23.237131 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3069 05:21:23.248202 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3070 05:21:23.253758 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3071 05:21:23.264839 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3072 05:21:23.270506 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3073 05:21:23.275937 alsa_test-pcmtest-driver pass
3074 05:21:23.281515 alsa_utimer-test_global_wrong_timers_test pass
3075 05:21:23.281937 alsa_utimer-test_timer_f_utimer fail
3076 05:21:23.287001 alsa_utimer-test fail
3077 05:21:23.287422 + ../../utils/send-to-lava.sh ./output/result.txt
3078 05:21:23.292568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
3079 05:21:23.293463 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
3081 05:21:23.303664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
3082 05:21:23.304377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
3084 05:21:23.309471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
3085 05:21:23.310150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
3087 05:21:23.327082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
3088 05:21:23.327796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
3090 05:21:23.373333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
3091 05:21:23.374122 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
3093 05:21:23.427772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
3094 05:21:23.428583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
3096 05:21:23.480065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
3097 05:21:23.480906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
3099 05:21:23.531037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
3100 05:21:23.531870 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
3102 05:21:23.582936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
3103 05:21:23.583771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
3105 05:21:23.627678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
3106 05:21:23.628468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
3108 05:21:23.686158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
3109 05:21:23.686970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
3111 05:21:23.742290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
3112 05:21:23.743082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
3114 05:21:23.803689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
3115 05:21:23.804479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
3117 05:21:23.851849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
3118 05:21:23.852664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
3120 05:21:23.901300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
3121 05:21:23.902049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
3123 05:21:23.964155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
3124 05:21:23.964999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
3126 05:21:24.015962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
3127 05:21:24.016835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
3129 05:21:24.070572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
3130 05:21:24.071423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
3132 05:21:24.126563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
3133 05:21:24.127375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
3135 05:21:24.176339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
3136 05:21:24.177387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
3138 05:21:24.221851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
3139 05:21:24.222671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
3141 05:21:24.266873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
3142 05:21:24.267688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
3144 05:21:24.315073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
3145 05:21:24.316145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
3147 05:21:24.364652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
3148 05:21:24.365498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
3150 05:21:24.416013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
3151 05:21:24.416889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
3153 05:21:24.468246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3154 05:21:24.469075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3156 05:21:24.523874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3157 05:21:24.524723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3159 05:21:24.591307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3160 05:21:24.592169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3162 05:21:24.656015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3163 05:21:24.656830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3165 05:21:24.705396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3166 05:21:24.706216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3168 05:21:24.749165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3169 05:21:24.749975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3171 05:21:24.808724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3172 05:21:24.809493 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3174 05:21:24.858164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3175 05:21:24.859095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3177 05:21:24.911018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3178 05:21:24.911879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3180 05:21:24.972139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3181 05:21:24.973083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3183 05:21:25.017263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3184 05:21:25.018128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3186 05:21:25.068069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3187 05:21:25.068945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3189 05:21:25.117525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3190 05:21:25.118160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3192 05:21:25.167092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3193 05:21:25.167927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3195 05:21:25.213534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3196 05:21:25.214439 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3198 05:21:25.274785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3199 05:21:25.275646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3201 05:21:25.325408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3202 05:21:25.326307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3204 05:21:25.383240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3205 05:21:25.383907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3207 05:21:25.433514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3208 05:21:25.434162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3210 05:21:25.479036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3211 05:21:25.480033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3213 05:21:25.555598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3214 05:21:25.556641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3216 05:21:25.605117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3217 05:21:25.605995 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3219 05:21:25.655194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3220 05:21:25.656103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3222 05:21:25.699588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3223 05:21:25.700524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3225 05:21:25.749682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3226 05:21:25.750651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3228 05:21:25.809567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3229 05:21:25.810532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3231 05:21:25.855083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3232 05:21:25.856141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3234 05:21:25.911607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3235 05:21:25.912534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3237 05:21:25.962473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3238 05:21:25.963339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3240 05:21:26.009536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3241 05:21:26.010315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3243 05:21:26.067046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3244 05:21:26.067884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3246 05:21:26.124228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3247 05:21:26.125058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3249 05:21:26.184923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3250 05:21:26.185728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3252 05:21:26.236220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3253 05:21:26.237000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3255 05:21:26.294232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3256 05:21:26.295063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3258 05:21:26.349180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3259 05:21:26.350080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3261 05:21:26.404311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3262 05:21:26.405151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3264 05:21:26.461128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3265 05:21:26.461961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3267 05:21:26.512830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3268 05:21:26.513638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3270 05:21:26.561091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3271 05:21:26.561913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3273 05:21:26.607423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3274 05:21:26.608189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3276 05:21:26.664117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3277 05:21:26.664882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3279 05:21:26.717138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3280 05:21:26.717871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3282 05:21:26.767752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3283 05:21:26.768530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3285 05:21:26.820909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3286 05:21:26.821643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3288 05:21:26.865512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3289 05:21:26.866270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3291 05:21:26.910892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3292 05:21:26.911612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3294 05:21:26.969753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3295 05:21:26.970489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3297 05:21:27.019966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3298 05:21:27.020776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3300 05:21:27.078332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3301 05:21:27.079147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3303 05:21:27.125375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3304 05:21:27.126141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3306 05:21:27.170246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3307 05:21:27.171033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3309 05:21:27.223762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3310 05:21:27.224554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3312 05:21:27.271825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3313 05:21:27.272734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3315 05:21:27.328795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3316 05:21:27.329557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3318 05:21:27.374893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3319 05:21:27.375703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3321 05:21:27.425353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3322 05:21:27.426105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3324 05:21:27.474518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3325 05:21:27.475311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3327 05:21:27.528383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3328 05:21:27.529230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3330 05:21:27.580443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3331 05:21:27.581273 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3333 05:21:27.627549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3334 05:21:27.628342 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3336 05:21:27.678555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3337 05:21:27.679352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3339 05:21:27.729251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3340 05:21:27.729990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3342 05:21:27.773518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3343 05:21:27.774300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3345 05:21:27.822695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3346 05:21:27.823435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3348 05:21:27.874529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3349 05:21:27.875319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3351 05:21:27.926054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3352 05:21:27.926807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3354 05:21:27.971938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3355 05:21:27.972788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3357 05:21:28.017059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3358 05:21:28.017828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3360 05:21:28.065596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3361 05:21:28.066394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3363 05:21:28.111698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3364 05:21:28.112500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3366 05:21:28.161788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3367 05:21:28.162588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3369 05:21:28.210547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3370 05:21:28.211309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3372 05:21:28.255735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3373 05:21:28.256543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3375 05:21:28.301372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3376 05:21:28.302202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3378 05:21:28.349394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3379 05:21:28.350189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3381 05:21:28.402817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3382 05:21:28.403676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3384 05:21:28.445531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3385 05:21:28.446326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3387 05:21:28.498013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3388 05:21:28.498868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3390 05:21:28.548239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3391 05:21:28.549057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3393 05:21:28.769500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3394 05:21:28.770203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3396 05:21:28.813271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3397 05:21:28.813922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3399 05:21:28.866043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3400 05:21:28.866953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3402 05:21:28.911574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3403 05:21:28.912491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3405 05:21:28.963956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3406 05:21:28.964878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3408 05:21:29.013475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3409 05:21:29.014145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3411 05:21:29.068147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3412 05:21:29.069056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3414 05:21:29.124941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3415 05:21:29.125781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3417 05:21:29.170364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3418 05:21:29.171246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3420 05:21:29.222921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3421 05:21:29.223749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3423 05:21:29.278730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3424 05:21:29.279630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3426 05:21:29.325470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3427 05:21:29.326288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3429 05:21:29.378752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3430 05:21:29.379647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3432 05:21:29.430526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3433 05:21:29.431431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3435 05:21:29.476676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3436 05:21:29.477567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3438 05:21:29.525461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3439 05:21:29.526984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3441 05:21:29.569315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3442 05:21:29.570191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3444 05:21:29.617017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3445 05:21:29.617870 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3447 05:21:29.671723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3448 05:21:29.672641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3450 05:21:29.724483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3451 05:21:29.725344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3453 05:21:29.769617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3454 05:21:29.770524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3456 05:21:29.824095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3457 05:21:29.824952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3459 05:21:29.870742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3460 05:21:29.871634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3462 05:21:29.922968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3463 05:21:29.923790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3465 05:21:29.969560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3466 05:21:29.970449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3468 05:21:30.022681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3469 05:21:30.023510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3471 05:21:30.072323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3472 05:21:30.073159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3474 05:21:30.120793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3475 05:21:30.121625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3477 05:21:30.173069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3478 05:21:30.173892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3480 05:21:30.218256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3481 05:21:30.219031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3483 05:21:30.268858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3484 05:21:30.269915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3486 05:21:30.324101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3487 05:21:30.324901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3489 05:21:30.375672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3490 05:21:30.376557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3492 05:21:30.440377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3493 05:21:30.441184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3495 05:21:30.493778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3496 05:21:30.494562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3498 05:21:30.538947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3499 05:21:30.539747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3501 05:21:30.595902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3502 05:21:30.596752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3504 05:21:30.649031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3505 05:21:30.649771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3507 05:21:30.703296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3508 05:21:30.704082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3510 05:21:30.753038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3511 05:21:30.753810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3513 05:21:30.805494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3514 05:21:30.806274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3516 05:21:30.856303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3517 05:21:30.857128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3519 05:21:30.910461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3520 05:21:30.911267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3522 05:21:30.957837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3523 05:21:30.958646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3525 05:21:31.007831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3526 05:21:31.008705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3528 05:21:31.054319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3529 05:21:31.055302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3531 05:21:31.103833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3532 05:21:31.104725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3534 05:21:31.154940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3535 05:21:31.155777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3537 05:21:31.209556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3538 05:21:31.210406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3540 05:21:31.254789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3541 05:21:31.255621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3543 05:21:31.297557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3544 05:21:31.298360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3546 05:21:31.345495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3547 05:21:31.346411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3549 05:21:31.399485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3550 05:21:31.400382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3552 05:21:31.443500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3553 05:21:31.444329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3555 05:21:31.499664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3556 05:21:31.500531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3558 05:21:31.552639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3559 05:21:31.553450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3561 05:21:31.604037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3562 05:21:31.604891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3564 05:21:31.656571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3565 05:21:31.657355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3567 05:21:31.699949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3568 05:21:31.700795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3570 05:21:31.746057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3571 05:21:31.746827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3573 05:21:31.790082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3574 05:21:31.790906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3576 05:21:31.841226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3577 05:21:31.842010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3579 05:21:31.893427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3580 05:21:31.894240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3582 05:21:31.936277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3583 05:21:31.937046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3585 05:21:31.988187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3586 05:21:31.989067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3588 05:21:32.040522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3589 05:21:32.041509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3591 05:21:32.094271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3592 05:21:32.095109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3594 05:21:32.144279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3595 05:21:32.145089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3597 05:21:32.194879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3598 05:21:32.195686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3600 05:21:32.246322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3601 05:21:32.247108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3603 05:21:32.297026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3604 05:21:32.297852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3606 05:21:32.343316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3607 05:21:32.344107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3609 05:21:32.387752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3610 05:21:32.388618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3612 05:21:32.446459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3613 05:21:32.447253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3615 05:21:32.492562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3616 05:21:32.493181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3618 05:21:32.548845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3619 05:21:32.549728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3621 05:21:32.593636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3622 05:21:32.594263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3624 05:21:32.645146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3625 05:21:32.646470 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3627 05:21:32.691857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3628 05:21:32.692896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3630 05:21:32.742194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3631 05:21:32.743057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3633 05:21:32.794715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3634 05:21:32.795723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3636 05:21:32.849205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3637 05:21:32.850085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3639 05:21:32.901614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3640 05:21:32.902475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3642 05:21:32.948298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3643 05:21:32.949182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3645 05:21:33.009444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3646 05:21:33.010289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3648 05:21:33.065278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3649 05:21:33.066121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3651 05:21:33.119757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3652 05:21:33.120587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3654 05:21:33.168967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3655 05:21:33.169764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3657 05:21:33.220213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3658 05:21:33.221136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3660 05:21:33.265936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3661 05:21:33.266729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3663 05:21:33.310815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3664 05:21:33.311635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3666 05:21:33.356604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3667 05:21:33.357410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3669 05:21:33.411304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3670 05:21:33.412163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3672 05:21:33.462178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3673 05:21:33.463061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3675 05:21:33.524478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3676 05:21:33.525163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3678 05:21:33.571926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3679 05:21:33.572684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3681 05:21:33.624553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3682 05:21:33.625235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3684 05:21:33.672761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3685 05:21:33.673617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3687 05:21:33.722064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3688 05:21:33.722843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3690 05:21:33.777750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3691 05:21:33.778554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3693 05:21:33.827592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3694 05:21:33.828373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3696 05:21:33.878086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3697 05:21:33.878814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3699 05:21:33.921624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3700 05:21:33.922410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3702 05:21:33.980315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3703 05:21:33.981248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3705 05:21:34.032287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3706 05:21:34.033072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3708 05:21:34.078993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3709 05:21:34.079751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3711 05:21:34.123953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3712 05:21:34.124737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3714 05:21:34.177602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3715 05:21:34.178392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3717 05:21:34.231787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3718 05:21:34.232661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3720 05:21:34.283556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3721 05:21:34.284409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3723 05:21:34.346302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3724 05:21:34.347130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3726 05:21:34.402223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3727 05:21:34.403034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3729 05:21:34.458796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3730 05:21:34.459560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3732 05:21:34.515829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3733 05:21:34.516659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3735 05:21:34.576583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3736 05:21:34.577418 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3738 05:21:34.623968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3739 05:21:34.624737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3741 05:21:34.671899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3742 05:21:34.672619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3744 05:21:34.724103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3745 05:21:34.724807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3747 05:21:34.779186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3748 05:21:34.779932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3750 05:21:34.839212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3751 05:21:34.840113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3753 05:21:34.888332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3754 05:21:34.888957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3756 05:21:34.938942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3757 05:21:34.939616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3759 05:21:35.001744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3760 05:21:35.002370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3762 05:21:35.047343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3763 05:21:35.050749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3765 05:21:35.097385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3766 05:21:35.098281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3768 05:21:35.146950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3769 05:21:35.148020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3771 05:21:35.196179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3772 05:21:35.197085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3774 05:21:35.240603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3775 05:21:35.242319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3777 05:21:35.298964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3778 05:21:35.299859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3780 05:21:35.357457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3781 05:21:35.358367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3783 05:21:35.416281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3784 05:21:35.417230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3786 05:21:35.466958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3787 05:21:35.467825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3789 05:21:35.519476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3790 05:21:35.520418 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3792 05:21:35.569246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3793 05:21:35.569916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3795 05:21:35.621192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3796 05:21:35.621822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3798 05:21:35.664091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3799 05:21:35.664694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3801 05:21:35.714911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3802 05:21:35.715519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3804 05:21:35.771432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3805 05:21:35.772045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3807 05:21:35.831127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3808 05:21:35.831734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3810 05:21:35.876108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3811 05:21:35.877101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3813 05:21:35.927458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3814 05:21:35.928466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3816 05:21:35.983906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3817 05:21:35.984828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3819 05:21:36.040816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3820 05:21:36.041871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3822 05:21:36.092546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3823 05:21:36.093582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3825 05:21:36.148470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3826 05:21:36.149521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3828 05:21:36.195515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3829 05:21:36.196541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3831 05:21:36.255144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3832 05:21:36.256093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3834 05:21:36.312840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3835 05:21:36.313805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3837 05:21:36.368385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3838 05:21:36.369311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3840 05:21:36.419906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3841 05:21:36.420891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3843 05:21:36.473698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3844 05:21:36.474675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3846 05:21:36.531757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3847 05:21:36.532903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3849 05:21:36.589097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3850 05:21:36.589821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3852 05:21:36.642412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3853 05:21:36.643287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3855 05:21:36.688286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3856 05:21:36.688939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3858 05:21:36.747173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3859 05:21:36.747886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3861 05:21:36.790088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3862 05:21:36.790706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3864 05:21:36.842380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3865 05:21:36.843015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3867 05:21:36.896944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3868 05:21:36.897539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3870 05:21:36.943176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3871 05:21:36.943807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3873 05:21:36.988961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3874 05:21:36.989917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3876 05:21:37.047066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3877 05:21:37.048108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3879 05:21:37.091855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3880 05:21:37.092768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3882 05:21:37.137611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3883 05:21:37.138502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3885 05:21:37.188106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3886 05:21:37.189021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3888 05:21:37.238815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3889 05:21:37.239736 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3891 05:21:37.284108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3892 05:21:37.285008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3894 05:21:37.336094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3895 05:21:37.337008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3897 05:21:37.395552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3898 05:21:37.396483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3900 05:21:37.448095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3901 05:21:37.449004 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3903 05:21:37.502058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3904 05:21:37.503073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3906 05:21:37.555739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3907 05:21:37.556689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3909 05:21:37.609320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3910 05:21:37.610220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3912 05:21:37.664101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3913 05:21:37.665001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3915 05:21:37.715956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3916 05:21:37.716901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3918 05:21:37.770396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3919 05:21:37.771265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3921 05:21:37.824724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3922 05:21:37.825612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3924 05:21:37.875418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3925 05:21:37.876323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3927 05:21:37.935578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3928 05:21:37.936494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3930 05:21:37.979679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3931 05:21:37.980594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3933 05:21:38.027064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3934 05:21:38.027936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3936 05:21:38.084201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3937 05:21:38.085069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3939 05:21:38.134561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3940 05:21:38.135448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3942 05:21:38.187785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3943 05:21:38.188657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3945 05:21:38.234203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3946 05:21:38.235059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3948 05:21:38.286679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3949 05:21:38.287505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3951 05:21:38.337988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3952 05:21:38.338861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3954 05:21:38.394366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3955 05:21:38.395223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3957 05:21:38.453259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3958 05:21:38.454154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3960 05:21:38.498728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3961 05:21:38.499708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3963 05:21:38.556471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3964 05:21:38.557039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3966 05:21:38.610499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3967 05:21:38.611331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3969 05:21:38.656522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3970 05:21:38.657254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3972 05:21:38.707237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3973 05:21:38.707934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3975 05:21:38.756262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3976 05:21:38.756981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3978 05:21:38.811526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3979 05:21:38.812259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3981 05:21:38.863084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3982 05:21:38.863788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3984 05:21:38.915227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3985 05:21:38.915952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3987 05:21:38.967935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3988 05:21:38.968689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3990 05:21:39.027053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3991 05:21:39.027848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3993 05:21:39.074060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3994 05:21:39.074788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3996 05:21:39.121973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3997 05:21:39.122706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3999 05:21:39.177457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
4000 05:21:39.178176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
4002 05:21:39.229013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
4003 05:21:39.229760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
4005 05:21:39.281472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
4006 05:21:39.282190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
4008 05:21:39.326642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
4009 05:21:39.327368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
4011 05:21:39.377492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
4012 05:21:39.378241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
4014 05:21:39.430470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
4015 05:21:39.431217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
4017 05:21:39.489131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
4018 05:21:39.489912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
4020 05:21:39.541663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
4021 05:21:39.542311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
4023 05:21:39.600534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
4024 05:21:39.601138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
4026 05:21:39.657298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
4027 05:21:39.658043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
4029 05:21:39.705013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
4030 05:21:39.705917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
4032 05:21:39.761061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
4033 05:21:39.761855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
4035 05:21:39.812205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
4036 05:21:39.812986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
4038 05:21:39.867720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
4039 05:21:39.868553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
4041 05:21:39.914838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
4042 05:21:39.915603 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
4044 05:21:39.970462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
4045 05:21:39.971187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
4047 05:21:40.023259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
4048 05:21:40.024043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
4050 05:21:40.075414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
4051 05:21:40.076125 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
4053 05:21:40.121445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
4054 05:21:40.122208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
4056 05:21:40.170190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
4057 05:21:40.170907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
4059 05:21:40.214204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
4060 05:21:40.214925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
4062 05:21:40.266543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
4063 05:21:40.267249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
4065 05:21:40.319083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
4066 05:21:40.319886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
4068 05:21:40.374113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
4069 05:21:40.374914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
4071 05:21:40.428515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
4072 05:21:40.429333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
4074 05:21:40.480384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
4075 05:21:40.481192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
4077 05:21:40.534800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
4078 05:21:40.535421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
4080 05:21:40.591290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
4081 05:21:40.592141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
4083 05:21:40.644186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
4084 05:21:40.644996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
4086 05:21:40.699823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
4087 05:21:40.700615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
4089 05:21:40.744201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
4090 05:21:40.744955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
4092 05:21:40.794195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
4093 05:21:40.794967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
4095 05:21:40.849394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
4096 05:21:40.850161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
4098 05:21:40.907009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
4099 05:21:40.907765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
4101 05:21:40.960644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
4102 05:21:40.961377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
4104 05:21:41.010791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
4105 05:21:41.011531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
4107 05:21:41.067843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
4108 05:21:41.068645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
4110 05:21:41.120814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
4111 05:21:41.121545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
4113 05:21:41.171733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
4114 05:21:41.172541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
4116 05:21:41.226632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
4117 05:21:41.227401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
4119 05:21:41.278249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
4120 05:21:41.278998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
4122 05:21:41.327919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
4123 05:21:41.328680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
4125 05:21:41.379606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
4126 05:21:41.380394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
4128 05:21:41.431699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
4129 05:21:41.432519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
4131 05:21:41.486833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
4132 05:21:41.487578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
4134 05:21:41.537336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
4135 05:21:41.538155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
4137 05:21:41.597518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
4138 05:21:41.598344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
4140 05:21:41.642983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
4141 05:21:41.643729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
4143 05:21:41.688397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
4144 05:21:41.689125 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
4146 05:21:41.747673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
4147 05:21:41.748453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
4149 05:21:41.793335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
4150 05:21:41.794064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
4152 05:21:41.846298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
4153 05:21:41.847040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4155 05:21:41.899611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4156 05:21:41.900399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4158 05:21:41.946739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4159 05:21:41.947498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4161 05:21:42.005464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4162 05:21:42.006238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4164 05:21:42.061421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4165 05:21:42.062201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4167 05:21:42.110419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4168 05:21:42.111175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4170 05:21:42.163372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4171 05:21:42.164143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4173 05:21:42.212609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4174 05:21:42.213362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4176 05:21:42.259386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4177 05:21:42.260144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4179 05:21:42.313925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4180 05:21:42.314686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4182 05:21:42.361408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4183 05:21:42.362188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4185 05:21:42.416827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4186 05:21:42.417636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4188 05:21:42.467812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4189 05:21:42.468642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4191 05:21:42.517057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4192 05:21:42.517878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4194 05:21:42.574693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4195 05:21:42.575529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4197 05:21:42.625772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4198 05:21:42.626554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4200 05:21:42.671306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4201 05:21:42.672066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4203 05:21:42.723907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4204 05:21:42.724706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4206 05:21:42.771460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4207 05:21:42.772281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4209 05:21:42.825437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4210 05:21:42.826226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4212 05:21:42.876359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4213 05:21:42.877121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4215 05:21:42.929222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4216 05:21:42.929980 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4218 05:21:42.980606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4219 05:21:42.981373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4221 05:21:43.032478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4222 05:21:43.033255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4224 05:21:43.079453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4225 05:21:43.080278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4227 05:21:43.135089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4228 05:21:43.135845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4230 05:21:43.190631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4231 05:21:43.191363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4233 05:21:43.235941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4234 05:21:43.236785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4236 05:21:43.281141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4237 05:21:43.281865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4239 05:21:43.326809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4240 05:21:43.327542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4242 05:21:43.373281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4243 05:21:43.374130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4245 05:21:43.423184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4246 05:21:43.423961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4248 05:21:43.469927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4249 05:21:43.470686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4251 05:21:43.529573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4252 05:21:43.530399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4254 05:21:43.584427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4255 05:21:43.585218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4257 05:21:43.642563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4258 05:21:43.643333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4260 05:21:43.688224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4261 05:21:43.688983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4263 05:21:43.747608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4264 05:21:43.748403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4266 05:21:43.800236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4267 05:21:43.801005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4269 05:21:43.850248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4270 05:21:43.851003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4272 05:21:43.902509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4273 05:21:43.903260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4275 05:21:43.950702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4276 05:21:43.951454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4278 05:21:44.004614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4279 05:21:44.005372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4281 05:21:44.055218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4282 05:21:44.056013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4284 05:21:44.107156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4285 05:21:44.107905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4287 05:21:44.152620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4288 05:21:44.153369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4290 05:21:44.203212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4291 05:21:44.203964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4293 05:21:44.261422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4294 05:21:44.262184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4296 05:21:44.313567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4297 05:21:44.314329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4299 05:21:44.361149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4300 05:21:44.361906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4302 05:21:44.413455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4303 05:21:44.414248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4305 05:21:44.472756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4306 05:21:44.473612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4308 05:21:44.519023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4309 05:21:44.519876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4311 05:21:44.567094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4312 05:21:44.567925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4314 05:21:44.629095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4315 05:21:44.629972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4317 05:21:44.683936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4318 05:21:44.684875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4320 05:21:44.732836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4321 05:21:44.733714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4323 05:21:44.788640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4324 05:21:44.789524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4326 05:21:44.832679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4327 05:21:44.833591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4329 05:21:44.879145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4330 05:21:44.879745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4332 05:21:44.930842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4333 05:21:44.931505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4335 05:21:44.991118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4336 05:21:44.991911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4338 05:21:45.040774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4339 05:21:45.041398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4341 05:21:45.093954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4342 05:21:45.094549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4344 05:21:45.144188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4345 05:21:45.144849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4347 05:21:45.196638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4348 05:21:45.197373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4350 05:21:45.243800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4351 05:21:45.244419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4353 05:21:45.295997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4354 05:21:45.296599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4356 05:21:45.340387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4357 05:21:45.341293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4359 05:21:45.395940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4360 05:21:45.396849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4362 05:21:45.446720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4364 05:21:45.449634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4365 05:21:45.504264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4366 05:21:45.505140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4368 05:21:45.554564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4369 05:21:45.555464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4371 05:21:45.605828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4372 05:21:45.606676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4374 05:21:45.669478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4375 05:21:45.670350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4377 05:21:45.720349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4378 05:21:45.721172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4380 05:21:45.778183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4381 05:21:45.778988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4383 05:21:45.825265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4384 05:21:45.826179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4386 05:21:45.872046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4387 05:21:45.872842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4389 05:21:45.935014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4390 05:21:45.935852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4392 05:21:45.983604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4393 05:21:45.984394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4395 05:21:46.032973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4396 05:21:46.033782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4398 05:21:46.082958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4399 05:21:46.083745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4401 05:21:46.137531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4402 05:21:46.138357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4404 05:21:46.183500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4405 05:21:46.184347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4407 05:21:46.228924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4408 05:21:46.229671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4410 05:21:46.276515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4411 05:21:46.277262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4413 05:21:46.327065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4414 05:21:46.327810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4416 05:21:46.372489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4417 05:21:46.373250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4419 05:21:46.418452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4420 05:21:46.419348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4422 05:21:46.473935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4423 05:21:46.474764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4425 05:21:46.518137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4426 05:21:46.518920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4428 05:21:46.566516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4429 05:21:46.567288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4431 05:21:46.615910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4432 05:21:46.616740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4434 05:21:46.663611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4435 05:21:46.664394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4437 05:21:46.719030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4438 05:21:46.719783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4440 05:21:46.774225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4441 05:21:46.775708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4443 05:21:46.821342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4444 05:21:46.822773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4446 05:21:46.874032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4447 05:21:46.875483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4449 05:21:46.926937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4450 05:21:46.928402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4452 05:21:46.986890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4453 05:21:46.988249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4455 05:21:47.044687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4456 05:21:47.046030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4458 05:21:47.100637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4459 05:21:47.102004 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4461 05:21:47.151895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4462 05:21:47.152804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4464 05:21:47.202360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4465 05:21:47.203719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4467 05:21:47.255503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4468 05:21:47.256400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4470 05:21:47.300102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4471 05:21:47.301452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4473 05:21:47.350555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4474 05:21:47.352027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4476 05:21:47.402891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4477 05:21:47.404275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4479 05:21:47.450384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4480 05:21:47.451285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4482 05:21:47.499898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4483 05:21:47.501263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4485 05:21:47.559135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4486 05:21:47.560050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4488 05:21:47.611619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4489 05:21:47.612530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4491 05:21:47.660513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4492 05:21:47.661923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4494 05:21:47.719867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4495 05:21:47.721314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4497 05:21:47.771731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4498 05:21:47.773169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4500 05:21:47.825687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4501 05:21:47.827052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4503 05:21:47.876574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4504 05:21:47.877527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4506 05:21:47.937370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4507 05:21:47.938230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4509 05:21:47.983268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4510 05:21:47.984402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4512 05:21:48.036658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4513 05:21:48.037569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4515 05:21:48.082496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4516 05:21:48.083344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4518 05:21:48.128849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4520 05:21:48.134108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4521 05:21:48.135045 + set +x
4522 05:21:48.140220 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 951357_1.6.2.4.5>
4523 05:21:48.141112 <LAVA_TEST_RUNNER EXIT>
4524 05:21:48.142185 Received signal: <ENDRUN> 1_kselftest-alsa 951357_1.6.2.4.5
4525 05:21:48.143079 Ending use of test pattern.
4526 05:21:48.143829 Ending test lava.1_kselftest-alsa (951357_1.6.2.4.5), duration 41.06
4528 05:21:48.146941 ok: lava_test_shell seems to have completed
4529 05:21:48.177485 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4530 05:21:48.179602 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4531 05:21:48.180391 end: 3 lava-test-retry (duration 00:00:42) [common]
4532 05:21:48.181068 start: 4 finalize (timeout 00:06:04) [common]
4533 05:21:48.181685 start: 4.1 power-off (timeout 00:00:30) [common]
4534 05:21:48.182766 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4535 05:21:48.218411 >> OK - accepted request
4536 05:21:48.221272 Returned 0 in 0 seconds
4537 05:21:48.322987 end: 4.1 power-off (duration 00:00:00) [common]
4539 05:21:48.326379 start: 4.2 read-feedback (timeout 00:06:04) [common]
4540 05:21:48.328586 Listened to connection for namespace 'common' for up to 1s
4541 05:21:49.328844 Finalising connection for namespace 'common'
4542 05:21:49.329655 Disconnecting from shell: Finalise
4543 05:21:49.330212 / #
4544 05:21:49.431678 end: 4.2 read-feedback (duration 00:00:01) [common]
4545 05:21:49.433244 end: 4 finalize (duration 00:00:01) [common]
4546 05:21:49.434496 Cleaning after the job
4547 05:21:49.435690 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/ramdisk
4548 05:21:49.456533 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/kernel
4549 05:21:49.498513 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/dtb
4550 05:21:49.499338 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/nfsrootfs
4551 05:21:49.692500 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951357/tftp-deploy-dwn9kkvn/modules
4552 05:21:49.714694 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/951357
4553 05:21:52.963866 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/951357
4554 05:21:52.964447 Job finished correctly