Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:09:51.833297 lava-dispatcher, installed at version: 2024.01
2 05:09:51.834054 start: 0 validate
3 05:09:51.834520 Start time: 2024-11-07 05:09:51.834491+00:00 (UTC)
4 05:09:51.835067 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:09:51.835596 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 05:09:51.878608 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:09:51.879134 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 05:09:51.907364 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:09:51.908299 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:09:51.941052 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:09:51.941804 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:09:51.975861 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:09:51.976339 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 05:09:52.020714 validate duration: 0.19
16 05:09:52.022243 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:09:52.022885 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:09:52.023491 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:09:52.024498 Not decompressing ramdisk as can be used compressed.
20 05:09:52.025277 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 05:09:52.025799 saving as /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/ramdisk/initrd.cpio.gz
22 05:09:52.026307 total size: 5628169 (5 MB)
23 05:09:52.073232 progress 0 % (0 MB)
24 05:09:52.082044 progress 5 % (0 MB)
25 05:09:52.091055 progress 10 % (0 MB)
26 05:09:52.099059 progress 15 % (0 MB)
27 05:09:52.107082 progress 20 % (1 MB)
28 05:09:52.111214 progress 25 % (1 MB)
29 05:09:52.115340 progress 30 % (1 MB)
30 05:09:52.119505 progress 35 % (1 MB)
31 05:09:52.123192 progress 40 % (2 MB)
32 05:09:52.127274 progress 45 % (2 MB)
33 05:09:52.131045 progress 50 % (2 MB)
34 05:09:52.135355 progress 55 % (2 MB)
35 05:09:52.139502 progress 60 % (3 MB)
36 05:09:52.143180 progress 65 % (3 MB)
37 05:09:52.147297 progress 70 % (3 MB)
38 05:09:52.150983 progress 75 % (4 MB)
39 05:09:52.155106 progress 80 % (4 MB)
40 05:09:52.158891 progress 85 % (4 MB)
41 05:09:52.162950 progress 90 % (4 MB)
42 05:09:52.167061 progress 95 % (5 MB)
43 05:09:52.170361 progress 100 % (5 MB)
44 05:09:52.171017 5 MB downloaded in 0.14 s (37.09 MB/s)
45 05:09:52.171581 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:09:52.172549 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:09:52.172868 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:09:52.173156 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:09:52.173634 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/kernel/Image
51 05:09:52.173912 saving as /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/kernel/Image
52 05:09:52.174136 total size: 45713920 (43 MB)
53 05:09:52.174355 No compression specified
54 05:09:52.213228 progress 0 % (0 MB)
55 05:09:52.241973 progress 5 % (2 MB)
56 05:09:52.271437 progress 10 % (4 MB)
57 05:09:52.300463 progress 15 % (6 MB)
58 05:09:52.329306 progress 20 % (8 MB)
59 05:09:52.358176 progress 25 % (10 MB)
60 05:09:52.386975 progress 30 % (13 MB)
61 05:09:52.416395 progress 35 % (15 MB)
62 05:09:52.445370 progress 40 % (17 MB)
63 05:09:52.473907 progress 45 % (19 MB)
64 05:09:52.503916 progress 50 % (21 MB)
65 05:09:52.535536 progress 55 % (24 MB)
66 05:09:52.565169 progress 60 % (26 MB)
67 05:09:52.593669 progress 65 % (28 MB)
68 05:09:52.622551 progress 70 % (30 MB)
69 05:09:52.651793 progress 75 % (32 MB)
70 05:09:52.680707 progress 80 % (34 MB)
71 05:09:52.709856 progress 85 % (37 MB)
72 05:09:52.738313 progress 90 % (39 MB)
73 05:09:52.767197 progress 95 % (41 MB)
74 05:09:52.796166 progress 100 % (43 MB)
75 05:09:52.796691 43 MB downloaded in 0.62 s (70.03 MB/s)
76 05:09:52.797176 end: 1.2.1 http-download (duration 00:00:01) [common]
78 05:09:52.798000 end: 1.2 download-retry (duration 00:00:01) [common]
79 05:09:52.798277 start: 1.3 download-retry (timeout 00:09:59) [common]
80 05:09:52.798545 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 05:09:52.799022 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 05:09:52.799299 saving as /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/dtb/meson-g12b-a311d-libretech-cc.dtb
83 05:09:52.799509 total size: 54703 (0 MB)
84 05:09:52.799719 No compression specified
85 05:09:52.844781 progress 59 % (0 MB)
86 05:09:52.845639 progress 100 % (0 MB)
87 05:09:52.846193 0 MB downloaded in 0.05 s (1.12 MB/s)
88 05:09:52.846663 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:09:52.847490 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:09:52.847758 start: 1.4 download-retry (timeout 00:09:59) [common]
92 05:09:52.848051 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 05:09:52.848521 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 05:09:52.848774 saving as /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/nfsrootfs/full.rootfs.tar
95 05:09:52.848983 total size: 120894716 (115 MB)
96 05:09:52.849194 Using unxz to decompress xz
97 05:09:52.887561 progress 0 % (0 MB)
98 05:09:53.709837 progress 5 % (5 MB)
99 05:09:54.544317 progress 10 % (11 MB)
100 05:09:55.343539 progress 15 % (17 MB)
101 05:09:56.094589 progress 20 % (23 MB)
102 05:09:56.688225 progress 25 % (28 MB)
103 05:09:57.502602 progress 30 % (34 MB)
104 05:09:58.293653 progress 35 % (40 MB)
105 05:09:58.664484 progress 40 % (46 MB)
106 05:09:59.043750 progress 45 % (51 MB)
107 05:09:59.780019 progress 50 % (57 MB)
108 05:10:00.685509 progress 55 % (63 MB)
109 05:10:01.518012 progress 60 % (69 MB)
110 05:10:02.280571 progress 65 % (74 MB)
111 05:10:03.059729 progress 70 % (80 MB)
112 05:10:03.879239 progress 75 % (86 MB)
113 05:10:04.664629 progress 80 % (92 MB)
114 05:10:05.420083 progress 85 % (98 MB)
115 05:10:06.271778 progress 90 % (103 MB)
116 05:10:07.042747 progress 95 % (109 MB)
117 05:10:07.866023 progress 100 % (115 MB)
118 05:10:07.878445 115 MB downloaded in 15.03 s (7.67 MB/s)
119 05:10:07.879059 end: 1.4.1 http-download (duration 00:00:15) [common]
121 05:10:07.880003 end: 1.4 download-retry (duration 00:00:15) [common]
122 05:10:07.880314 start: 1.5 download-retry (timeout 00:09:44) [common]
123 05:10:07.880842 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 05:10:07.881682 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/modules.tar.xz
125 05:10:07.882165 saving as /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/modules/modules.tar
126 05:10:07.882608 total size: 11607084 (11 MB)
127 05:10:07.882871 Using unxz to decompress xz
128 05:10:07.920162 progress 0 % (0 MB)
129 05:10:07.986794 progress 5 % (0 MB)
130 05:10:08.062026 progress 10 % (1 MB)
131 05:10:08.158066 progress 15 % (1 MB)
132 05:10:08.248954 progress 20 % (2 MB)
133 05:10:08.328787 progress 25 % (2 MB)
134 05:10:08.404242 progress 30 % (3 MB)
135 05:10:08.478326 progress 35 % (3 MB)
136 05:10:08.555612 progress 40 % (4 MB)
137 05:10:08.632018 progress 45 % (5 MB)
138 05:10:08.715904 progress 50 % (5 MB)
139 05:10:08.792705 progress 55 % (6 MB)
140 05:10:08.877587 progress 60 % (6 MB)
141 05:10:08.958053 progress 65 % (7 MB)
142 05:10:09.034494 progress 70 % (7 MB)
143 05:10:09.116105 progress 75 % (8 MB)
144 05:10:09.199284 progress 80 % (8 MB)
145 05:10:09.279190 progress 85 % (9 MB)
146 05:10:09.357721 progress 90 % (9 MB)
147 05:10:09.435493 progress 95 % (10 MB)
148 05:10:09.512717 progress 100 % (11 MB)
149 05:10:09.523753 11 MB downloaded in 1.64 s (6.75 MB/s)
150 05:10:09.524720 end: 1.5.1 http-download (duration 00:00:02) [common]
152 05:10:09.526564 end: 1.5 download-retry (duration 00:00:02) [common]
153 05:10:09.527136 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 05:10:09.527708 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 05:10:26.544056 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/951328/extract-nfsrootfs-17s3_sea
156 05:10:26.544666 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 05:10:26.544955 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 05:10:26.545694 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93
159 05:10:26.546171 makedir: /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin
160 05:10:26.546505 makedir: /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/tests
161 05:10:26.546821 makedir: /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/results
162 05:10:26.547156 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-add-keys
163 05:10:26.547702 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-add-sources
164 05:10:26.548254 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-background-process-start
165 05:10:26.548775 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-background-process-stop
166 05:10:26.549345 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-common-functions
167 05:10:26.549852 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-echo-ipv4
168 05:10:26.550458 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-install-packages
169 05:10:26.550963 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-installed-packages
170 05:10:26.551442 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-os-build
171 05:10:26.551959 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-probe-channel
172 05:10:26.552515 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-probe-ip
173 05:10:26.553005 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-target-ip
174 05:10:26.553484 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-target-mac
175 05:10:26.553966 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-target-storage
176 05:10:26.554453 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-test-case
177 05:10:26.554931 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-test-event
178 05:10:26.555409 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-test-feedback
179 05:10:26.555887 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-test-raise
180 05:10:26.556405 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-test-reference
181 05:10:26.556885 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-test-runner
182 05:10:26.557401 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-test-set
183 05:10:26.557883 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-test-shell
184 05:10:26.558374 Updating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-add-keys (debian)
185 05:10:26.558920 Updating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-add-sources (debian)
186 05:10:26.559490 Updating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-install-packages (debian)
187 05:10:26.560057 Updating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-installed-packages (debian)
188 05:10:26.560591 Updating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/bin/lava-os-build (debian)
189 05:10:26.561035 Creating /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/environment
190 05:10:26.561413 LAVA metadata
191 05:10:26.561670 - LAVA_JOB_ID=951328
192 05:10:26.561886 - LAVA_DISPATCHER_IP=192.168.6.2
193 05:10:26.562255 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 05:10:26.563227 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 05:10:26.563539 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 05:10:26.563746 skipped lava-vland-overlay
197 05:10:26.564003 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 05:10:26.564263 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 05:10:26.564481 skipped lava-multinode-overlay
200 05:10:26.564722 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 05:10:26.564971 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 05:10:26.565218 Loading test definitions
203 05:10:26.565493 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 05:10:26.565713 Using /lava-951328 at stage 0
205 05:10:26.566946 uuid=951328_1.6.2.4.1 testdef=None
206 05:10:26.567254 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 05:10:26.567515 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 05:10:26.569107 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 05:10:26.569893 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 05:10:26.571804 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 05:10:26.572655 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 05:10:26.574498 runner path: /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/0/tests/0_timesync-off test_uuid 951328_1.6.2.4.1
215 05:10:26.575063 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 05:10:26.575877 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 05:10:26.576128 Using /lava-951328 at stage 0
219 05:10:26.576496 Fetching tests from https://github.com/kernelci/test-definitions.git
220 05:10:26.576797 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/0/tests/1_kselftest-dt'
221 05:10:29.987705 Running '/usr/bin/git checkout kernelci.org
222 05:10:30.438821 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 05:10:30.440606 uuid=951328_1.6.2.4.5 testdef=None
224 05:10:30.441238 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 05:10:30.442686 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 05:10:30.448257 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 05:10:30.449844 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 05:10:30.457100 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 05:10:30.458747 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 05:10:30.465819 runner path: /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/0/tests/1_kselftest-dt test_uuid 951328_1.6.2.4.5
234 05:10:30.466354 BOARD='meson-g12b-a311d-libretech-cc'
235 05:10:30.466757 BRANCH='broonie-sound'
236 05:10:30.467149 SKIPFILE='/dev/null'
237 05:10:30.467539 SKIP_INSTALL='True'
238 05:10:30.467926 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 05:10:30.468372 TST_CASENAME=''
240 05:10:30.468764 TST_CMDFILES='dt'
241 05:10:30.469805 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 05:10:30.471353 Creating lava-test-runner.conf files
244 05:10:30.471760 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/951328/lava-overlay-__ccwt93/lava-951328/0 for stage 0
245 05:10:30.472472 - 0_timesync-off
246 05:10:30.472935 - 1_kselftest-dt
247 05:10:30.473559 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 05:10:30.474096 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 05:10:53.774858 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 05:10:53.775309 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 05:10:53.775574 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 05:10:53.775847 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 05:10:53.776476 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 05:10:54.409030 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 05:10:54.409560 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 05:10:54.409863 extracting modules file /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/modules/modules.tar to /var/lib/lava/dispatcher/tmp/951328/extract-nfsrootfs-17s3_sea
257 05:10:55.913908 extracting modules file /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/modules/modules.tar to /var/lib/lava/dispatcher/tmp/951328/extract-overlay-ramdisk-nujb44xp/ramdisk
258 05:10:57.313257 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 05:10:57.313754 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 05:10:57.314051 [common] Applying overlay to NFS
261 05:10:57.314272 [common] Applying overlay /var/lib/lava/dispatcher/tmp/951328/compress-overlay-axgs10_9/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/951328/extract-nfsrootfs-17s3_sea
262 05:11:00.082777 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 05:11:00.083270 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 05:11:00.083548 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 05:11:00.083783 Converting downloaded kernel to a uImage
266 05:11:00.084119 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/kernel/Image /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/kernel/uImage
267 05:11:00.550315 output: Image Name:
268 05:11:00.550748 output: Created: Thu Nov 7 05:11:00 2024
269 05:11:00.550961 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 05:11:00.551169 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 05:11:00.551371 output: Load Address: 01080000
272 05:11:00.551572 output: Entry Point: 01080000
273 05:11:00.551770 output:
274 05:11:00.552137 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 05:11:00.552423 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 05:11:00.552693 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 05:11:00.552946 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 05:11:00.553209 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 05:11:00.553471 Building ramdisk /var/lib/lava/dispatcher/tmp/951328/extract-overlay-ramdisk-nujb44xp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/951328/extract-overlay-ramdisk-nujb44xp/ramdisk
280 05:11:02.666089 >> 166792 blocks
281 05:11:10.436808 Adding RAMdisk u-boot header.
282 05:11:10.437515 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/951328/extract-overlay-ramdisk-nujb44xp/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/951328/extract-overlay-ramdisk-nujb44xp/ramdisk.cpio.gz.uboot
283 05:11:10.686015 output: Image Name:
284 05:11:10.686442 output: Created: Thu Nov 7 05:11:10 2024
285 05:11:10.686653 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 05:11:10.686860 output: Data Size: 23432415 Bytes = 22883.22 KiB = 22.35 MiB
287 05:11:10.687064 output: Load Address: 00000000
288 05:11:10.687263 output: Entry Point: 00000000
289 05:11:10.687464 output:
290 05:11:10.688153 rename /var/lib/lava/dispatcher/tmp/951328/extract-overlay-ramdisk-nujb44xp/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/ramdisk/ramdisk.cpio.gz.uboot
291 05:11:10.688948 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 05:11:10.689552 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 05:11:10.690172 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 05:11:10.690665 No LXC device requested
295 05:11:10.691213 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 05:11:10.691774 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 05:11:10.692367 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 05:11:10.692827 Checking files for TFTP limit of 4294967296 bytes.
299 05:11:10.695745 end: 1 tftp-deploy (duration 00:01:19) [common]
300 05:11:10.696405 start: 2 uboot-action (timeout 00:05:00) [common]
301 05:11:10.697011 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 05:11:10.697562 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 05:11:10.698119 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 05:11:10.698695 Using kernel file from prepare-kernel: 951328/tftp-deploy-079xnn9n/kernel/uImage
305 05:11:10.699386 substitutions:
306 05:11:10.699836 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 05:11:10.700313 - {DTB_ADDR}: 0x01070000
308 05:11:10.700758 - {DTB}: 951328/tftp-deploy-079xnn9n/dtb/meson-g12b-a311d-libretech-cc.dtb
309 05:11:10.701203 - {INITRD}: 951328/tftp-deploy-079xnn9n/ramdisk/ramdisk.cpio.gz.uboot
310 05:11:10.701640 - {KERNEL_ADDR}: 0x01080000
311 05:11:10.702074 - {KERNEL}: 951328/tftp-deploy-079xnn9n/kernel/uImage
312 05:11:10.702506 - {LAVA_MAC}: None
313 05:11:10.702978 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/951328/extract-nfsrootfs-17s3_sea
314 05:11:10.703418 - {NFS_SERVER_IP}: 192.168.6.2
315 05:11:10.703849 - {PRESEED_CONFIG}: None
316 05:11:10.704321 - {PRESEED_LOCAL}: None
317 05:11:10.704758 - {RAMDISK_ADDR}: 0x08000000
318 05:11:10.705187 - {RAMDISK}: 951328/tftp-deploy-079xnn9n/ramdisk/ramdisk.cpio.gz.uboot
319 05:11:10.705619 - {ROOT_PART}: None
320 05:11:10.706050 - {ROOT}: None
321 05:11:10.706478 - {SERVER_IP}: 192.168.6.2
322 05:11:10.706902 - {TEE_ADDR}: 0x83000000
323 05:11:10.707326 - {TEE}: None
324 05:11:10.707753 Parsed boot commands:
325 05:11:10.708201 - setenv autoload no
326 05:11:10.708631 - setenv initrd_high 0xffffffff
327 05:11:10.709054 - setenv fdt_high 0xffffffff
328 05:11:10.709478 - dhcp
329 05:11:10.709904 - setenv serverip 192.168.6.2
330 05:11:10.710332 - tftpboot 0x01080000 951328/tftp-deploy-079xnn9n/kernel/uImage
331 05:11:10.710765 - tftpboot 0x08000000 951328/tftp-deploy-079xnn9n/ramdisk/ramdisk.cpio.gz.uboot
332 05:11:10.711194 - tftpboot 0x01070000 951328/tftp-deploy-079xnn9n/dtb/meson-g12b-a311d-libretech-cc.dtb
333 05:11:10.711625 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/951328/extract-nfsrootfs-17s3_sea,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 05:11:10.712094 - bootm 0x01080000 0x08000000 0x01070000
335 05:11:10.712650 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 05:11:10.714289 start: 2.3 connect-device (timeout 00:05:00) [common]
338 05:11:10.714754 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 05:11:10.729952 Setting prompt string to ['lava-test: # ']
340 05:11:10.731576 end: 2.3 connect-device (duration 00:00:00) [common]
341 05:11:10.732300 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 05:11:10.732927 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 05:11:10.733523 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 05:11:10.734764 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 05:11:10.772116 >> OK - accepted request
346 05:11:10.774321 Returned 0 in 0 seconds
347 05:11:10.875505 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 05:11:10.877392 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 05:11:10.878005 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 05:11:10.878563 Setting prompt string to ['Hit any key to stop autoboot']
352 05:11:10.879060 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 05:11:10.880784 Trying 192.168.56.21...
354 05:11:10.881300 Connected to conserv1.
355 05:11:10.881749 Escape character is '^]'.
356 05:11:10.882204
357 05:11:10.882658 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 05:11:10.883117
359 05:11:22.139072 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 05:11:22.139750 bl2_stage_init 0x01
361 05:11:22.140308 bl2_stage_init 0x81
362 05:11:22.144611 hw id: 0x0000 - pwm id 0x01
363 05:11:22.145206 bl2_stage_init 0xc1
364 05:11:22.145675 bl2_stage_init 0x02
365 05:11:22.146129
366 05:11:22.150159 L0:00000000
367 05:11:22.150680 L1:20000703
368 05:11:22.151138 L2:00008067
369 05:11:22.151587 L3:14000000
370 05:11:22.155911 B2:00402000
371 05:11:22.156446 B1:e0f83180
372 05:11:22.156882
373 05:11:22.157316 TE: 58159
374 05:11:22.157748
375 05:11:22.161382 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 05:11:22.161848
377 05:11:22.162282 Board ID = 1
378 05:11:22.167161 Set A53 clk to 24M
379 05:11:22.167628 Set A73 clk to 24M
380 05:11:22.168092 Set clk81 to 24M
381 05:11:22.172529 A53 clk: 1200 MHz
382 05:11:22.172992 A73 clk: 1200 MHz
383 05:11:22.173422 CLK81: 166.6M
384 05:11:22.173847 smccc: 00012ab5
385 05:11:22.178184 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 05:11:22.183700 board id: 1
387 05:11:22.189742 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 05:11:22.200367 fw parse done
389 05:11:22.206309 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 05:11:22.248894 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 05:11:22.259708 PIEI prepare done
392 05:11:22.260227 fastboot data load
393 05:11:22.260665 fastboot data verify
394 05:11:22.265365 verify result: 266
395 05:11:22.270980 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 05:11:22.271451 LPDDR4 probe
397 05:11:22.271887 ddr clk to 1584MHz
398 05:11:22.278909 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 05:11:22.316239
400 05:11:22.316756 dmc_version 0001
401 05:11:22.322909 Check phy result
402 05:11:22.328713 INFO : End of CA training
403 05:11:22.329186 INFO : End of initialization
404 05:11:22.334292 INFO : Training has run successfully!
405 05:11:22.334750 Check phy result
406 05:11:22.339947 INFO : End of initialization
407 05:11:22.340441 INFO : End of read enable training
408 05:11:22.345519 INFO : End of fine write leveling
409 05:11:22.351092 INFO : End of Write leveling coarse delay
410 05:11:22.351556 INFO : Training has run successfully!
411 05:11:22.352024 Check phy result
412 05:11:22.356705 INFO : End of initialization
413 05:11:22.357171 INFO : End of read dq deskew training
414 05:11:22.362273 INFO : End of MPR read delay center optimization
415 05:11:22.368033 INFO : End of write delay center optimization
416 05:11:22.373501 INFO : End of read delay center optimization
417 05:11:22.373987 INFO : End of max read latency training
418 05:11:22.379197 INFO : Training has run successfully!
419 05:11:22.379681 1D training succeed
420 05:11:22.388398 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 05:11:22.436189 Check phy result
422 05:11:22.436842 INFO : End of initialization
423 05:11:22.457656 INFO : End of 2D read delay Voltage center optimization
424 05:11:22.477942 INFO : End of 2D read delay Voltage center optimization
425 05:11:22.529947 INFO : End of 2D write delay Voltage center optimization
426 05:11:22.579393 INFO : End of 2D write delay Voltage center optimization
427 05:11:22.584916 INFO : Training has run successfully!
428 05:11:22.585390
429 05:11:22.585831 channel==0
430 05:11:22.590413 RxClkDly_Margin_A0==88 ps 9
431 05:11:22.590881 TxDqDly_Margin_A0==98 ps 10
432 05:11:22.596075 RxClkDly_Margin_A1==88 ps 9
433 05:11:22.596533 TxDqDly_Margin_A1==98 ps 10
434 05:11:22.596971 TrainedVREFDQ_A0==74
435 05:11:22.601687 TrainedVREFDQ_A1==74
436 05:11:22.602149 VrefDac_Margin_A0==25
437 05:11:22.602584 DeviceVref_Margin_A0==40
438 05:11:22.607271 VrefDac_Margin_A1==25
439 05:11:22.607741 DeviceVref_Margin_A1==40
440 05:11:22.608229
441 05:11:22.608667
442 05:11:22.612931 channel==1
443 05:11:22.613389 RxClkDly_Margin_A0==98 ps 10
444 05:11:22.613821 TxDqDly_Margin_A0==98 ps 10
445 05:11:22.618494 RxClkDly_Margin_A1==98 ps 10
446 05:11:22.618963 TxDqDly_Margin_A1==88 ps 9
447 05:11:22.624085 TrainedVREFDQ_A0==77
448 05:11:22.624552 TrainedVREFDQ_A1==77
449 05:11:22.624988 VrefDac_Margin_A0==22
450 05:11:22.629604 DeviceVref_Margin_A0==37
451 05:11:22.630090 VrefDac_Margin_A1==22
452 05:11:22.635270 DeviceVref_Margin_A1==37
453 05:11:22.635729
454 05:11:22.636202 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 05:11:22.640908
456 05:11:22.668794 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 05:11:22.669359 2D training succeed
458 05:11:22.674357 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 05:11:22.679956 auto size-- 65535DDR cs0 size: 2048MB
460 05:11:22.680453 DDR cs1 size: 2048MB
461 05:11:22.685563 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 05:11:22.686023 cs0 DataBus test pass
463 05:11:22.691137 cs1 DataBus test pass
464 05:11:22.691592 cs0 AddrBus test pass
465 05:11:22.692059 cs1 AddrBus test pass
466 05:11:22.692491
467 05:11:22.696745 100bdlr_step_size ps== 420
468 05:11:22.697221 result report
469 05:11:22.702340 boot times 0Enable ddr reg access
470 05:11:22.707800 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 05:11:22.721280 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 05:11:23.295065 0.0;M3 CHK:0;cm4_sp_mode 0
473 05:11:23.295749 MVN_1=0x00000000
474 05:11:23.300488 MVN_2=0x00000000
475 05:11:23.306248 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 05:11:23.306828 OPS=0x10
477 05:11:23.307294 ring efuse init
478 05:11:23.307739 chipver efuse init
479 05:11:23.311866 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 05:11:23.317428 [0.018961 Inits done]
481 05:11:23.317951 secure task start!
482 05:11:23.318403 high task start!
483 05:11:23.322052 low task start!
484 05:11:23.322560 run into bl31
485 05:11:23.328675 NOTICE: BL31: v1.3(release):4fc40b1
486 05:11:23.336509 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 05:11:23.337079 NOTICE: BL31: G12A normal boot!
488 05:11:23.362065 NOTICE: BL31: BL33 decompress pass
489 05:11:23.367635 ERROR: Error initializing runtime service opteed_fast
490 05:11:24.600567
491 05:11:24.601237
492 05:11:24.608926 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 05:11:24.609457
494 05:11:24.609905 Model: Libre Computer AML-A311D-CC Alta
495 05:11:24.817517 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 05:11:24.840807 DRAM: 2 GiB (effective 3.8 GiB)
497 05:11:24.983776 Core: 408 devices, 31 uclasses, devicetree: separate
498 05:11:24.989670 WDT: Not starting watchdog@f0d0
499 05:11:25.021946 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 05:11:25.034567 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 05:11:25.041253 ** Bad device specification mmc 0 **
502 05:11:25.051857 Card did not respond to voltage select! : -110
503 05:11:25.057549 ** Bad device specification mmc 0 **
504 05:11:25.058176 Couldn't find partition mmc 0
505 05:11:25.070161 Card did not respond to voltage select! : -110
506 05:11:25.071290 ** Bad device specification mmc 0 **
507 05:11:25.071655 Couldn't find partition mmc 0
508 05:11:25.076326 Error: could not access storage.
509 05:11:26.339598 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 05:11:26.340401 bl2_stage_init 0x01
511 05:11:26.340873 bl2_stage_init 0x81
512 05:11:26.345048 hw id: 0x0000 - pwm id 0x01
513 05:11:26.345573 bl2_stage_init 0xc1
514 05:11:26.346024 bl2_stage_init 0x02
515 05:11:26.346466
516 05:11:26.350607 L0:00000000
517 05:11:26.351129 L1:20000703
518 05:11:26.351595 L2:00008067
519 05:11:26.352062 L3:14000000
520 05:11:26.356227 B2:00402000
521 05:11:26.356756 B1:e0f83180
522 05:11:26.357194
523 05:11:26.357662 TE: 58124
524 05:11:26.358113
525 05:11:26.361820 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 05:11:26.362311
527 05:11:26.362755 Board ID = 1
528 05:11:26.367433 Set A53 clk to 24M
529 05:11:26.367917 Set A73 clk to 24M
530 05:11:26.368397 Set clk81 to 24M
531 05:11:26.373011 A53 clk: 1200 MHz
532 05:11:26.373499 A73 clk: 1200 MHz
533 05:11:26.373935 CLK81: 166.6M
534 05:11:26.374364 smccc: 00012a92
535 05:11:26.378626 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 05:11:26.384211 board id: 1
537 05:11:26.390092 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 05:11:26.400855 fw parse done
539 05:11:26.406759 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 05:11:26.449366 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 05:11:26.460343 PIEI prepare done
542 05:11:26.460911 fastboot data load
543 05:11:26.461365 fastboot data verify
544 05:11:26.466007 verify result: 266
545 05:11:26.471541 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 05:11:26.472090 LPDDR4 probe
547 05:11:26.472536 ddr clk to 1584MHz
548 05:11:26.479633 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 05:11:26.516833
550 05:11:26.517395 dmc_version 0001
551 05:11:26.523526 Check phy result
552 05:11:26.529339 INFO : End of CA training
553 05:11:26.529854 INFO : End of initialization
554 05:11:26.534976 INFO : Training has run successfully!
555 05:11:26.535536 Check phy result
556 05:11:26.540566 INFO : End of initialization
557 05:11:26.540865 INFO : End of read enable training
558 05:11:26.546104 INFO : End of fine write leveling
559 05:11:26.551760 INFO : End of Write leveling coarse delay
560 05:11:26.552322 INFO : Training has run successfully!
561 05:11:26.552771 Check phy result
562 05:11:26.557272 INFO : End of initialization
563 05:11:26.557853 INFO : End of read dq deskew training
564 05:11:26.562930 INFO : End of MPR read delay center optimization
565 05:11:26.568617 INFO : End of write delay center optimization
566 05:11:26.574203 INFO : End of read delay center optimization
567 05:11:26.574732 INFO : End of max read latency training
568 05:11:26.579664 INFO : Training has run successfully!
569 05:11:26.580182 1D training succeed
570 05:11:26.588835 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 05:11:26.636457 Check phy result
572 05:11:26.637001 INFO : End of initialization
573 05:11:26.659162 INFO : End of 2D read delay Voltage center optimization
574 05:11:26.679209 INFO : End of 2D read delay Voltage center optimization
575 05:11:26.731262 INFO : End of 2D write delay Voltage center optimization
576 05:11:26.780618 INFO : End of 2D write delay Voltage center optimization
577 05:11:26.786194 INFO : Training has run successfully!
578 05:11:26.786672
579 05:11:26.787130 channel==0
580 05:11:26.791814 RxClkDly_Margin_A0==88 ps 9
581 05:11:26.792328 TxDqDly_Margin_A0==98 ps 10
582 05:11:26.797576 RxClkDly_Margin_A1==88 ps 9
583 05:11:26.798122 TxDqDly_Margin_A1==98 ps 10
584 05:11:26.798570 TrainedVREFDQ_A0==74
585 05:11:26.802998 TrainedVREFDQ_A1==74
586 05:11:26.803471 VrefDac_Margin_A0==24
587 05:11:26.803906 DeviceVref_Margin_A0==40
588 05:11:26.808634 VrefDac_Margin_A1==25
589 05:11:26.809104 DeviceVref_Margin_A1==40
590 05:11:26.809539
591 05:11:26.809973
592 05:11:26.814207 channel==1
593 05:11:26.814687 RxClkDly_Margin_A0==98 ps 10
594 05:11:26.815127 TxDqDly_Margin_A0==98 ps 10
595 05:11:26.819793 RxClkDly_Margin_A1==98 ps 10
596 05:11:26.820289 TxDqDly_Margin_A1==88 ps 9
597 05:11:26.825613 TrainedVREFDQ_A0==77
598 05:11:26.826079 TrainedVREFDQ_A1==77
599 05:11:26.826516 VrefDac_Margin_A0==22
600 05:11:26.831058 DeviceVref_Margin_A0==37
601 05:11:26.831570 VrefDac_Margin_A1==22
602 05:11:26.836594 DeviceVref_Margin_A1==37
603 05:11:26.837063
604 05:11:26.837496 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 05:11:26.842187
606 05:11:26.870198 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 05:11:26.870784 2D training succeed
608 05:11:26.875780 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 05:11:26.881532 auto size-- 65535DDR cs0 size: 2048MB
610 05:11:26.882010 DDR cs1 size: 2048MB
611 05:11:26.887179 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 05:11:26.887657 cs0 DataBus test pass
613 05:11:26.892635 cs1 DataBus test pass
614 05:11:26.893109 cs0 AddrBus test pass
615 05:11:26.893546 cs1 AddrBus test pass
616 05:11:26.893975
617 05:11:26.898215 100bdlr_step_size ps== 420
618 05:11:26.898692 result report
619 05:11:26.903833 boot times 0Enable ddr reg access
620 05:11:26.909225 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 05:11:26.922698 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 05:11:27.496631 0.0;M3 CHK:0;cm4_sp_mode 0
623 05:11:27.497323 MVN_1=0x00000000
624 05:11:27.501995 MVN_2=0x00000000
625 05:11:27.507769 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 05:11:27.508368 OPS=0x10
627 05:11:27.508839 ring efuse init
628 05:11:27.509319 chipver efuse init
629 05:11:27.513363 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 05:11:27.518935 [0.018961 Inits done]
631 05:11:27.519420 secure task start!
632 05:11:27.519857 high task start!
633 05:11:27.523565 low task start!
634 05:11:27.524069 run into bl31
635 05:11:27.530159 NOTICE: BL31: v1.3(release):4fc40b1
636 05:11:27.538015 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 05:11:27.538598 NOTICE: BL31: G12A normal boot!
638 05:11:27.563364 NOTICE: BL31: BL33 decompress pass
639 05:11:27.569005 ERROR: Error initializing runtime service opteed_fast
640 05:11:28.802187
641 05:11:28.802887
642 05:11:28.810551 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 05:11:28.811126
644 05:11:28.811640 Model: Libre Computer AML-A311D-CC Alta
645 05:11:29.019013 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 05:11:29.042267 DRAM: 2 GiB (effective 3.8 GiB)
647 05:11:29.185415 Core: 408 devices, 31 uclasses, devicetree: separate
648 05:11:29.191202 WDT: Not starting watchdog@f0d0
649 05:11:29.223379 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 05:11:29.235955 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 05:11:29.240854 ** Bad device specification mmc 0 **
652 05:11:29.251239 Card did not respond to voltage select! : -110
653 05:11:29.258846 ** Bad device specification mmc 0 **
654 05:11:29.259360 Couldn't find partition mmc 0
655 05:11:29.267204 Card did not respond to voltage select! : -110
656 05:11:29.272743 ** Bad device specification mmc 0 **
657 05:11:29.273266 Couldn't find partition mmc 0
658 05:11:29.277850 Error: could not access storage.
659 05:11:29.621263 Net: eth0: ethernet@ff3f0000
660 05:11:29.621870 starting USB...
661 05:11:29.873174 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 05:11:29.873739 Starting the controller
663 05:11:29.880219 USB XHCI 1.10
664 05:11:31.588146 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 05:11:31.588840 bl2_stage_init 0x01
666 05:11:31.589322 bl2_stage_init 0x81
667 05:11:31.593702 hw id: 0x0000 - pwm id 0x01
668 05:11:31.594223 bl2_stage_init 0xc1
669 05:11:31.594684 bl2_stage_init 0x02
670 05:11:31.595134
671 05:11:31.599360 L0:00000000
672 05:11:31.599869 L1:20000703
673 05:11:31.600575 L2:00008067
674 05:11:31.601030 L3:14000000
675 05:11:31.602297 B2:00402000
676 05:11:31.602742 B1:e0f83180
677 05:11:31.603153
678 05:11:31.603562 TE: 58124
679 05:11:31.603965
680 05:11:31.613314 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 05:11:31.613780
682 05:11:31.614196 Board ID = 1
683 05:11:31.614605 Set A53 clk to 24M
684 05:11:31.615009 Set A73 clk to 24M
685 05:11:31.618915 Set clk81 to 24M
686 05:11:31.619363 A53 clk: 1200 MHz
687 05:11:31.619772 A73 clk: 1200 MHz
688 05:11:31.622516 CLK81: 166.6M
689 05:11:31.622968 smccc: 00012a92
690 05:11:31.628012 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 05:11:31.633578 board id: 1
692 05:11:31.638764 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 05:11:31.649422 fw parse done
694 05:11:31.655419 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 05:11:31.697843 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 05:11:31.708835 PIEI prepare done
697 05:11:31.709307 fastboot data load
698 05:11:31.709733 fastboot data verify
699 05:11:31.714406 verify result: 266
700 05:11:31.720047 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 05:11:31.720587 LPDDR4 probe
702 05:11:31.721032 ddr clk to 1584MHz
703 05:11:31.727973 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 05:11:32.030003
705 05:11:32.030662 dmc_version 0001
706 05:11:32.031138 Check phy result
707 05:11:32.031595 INFO : End of CA training
708 05:11:32.032095 INFO : End of initialization
709 05:11:32.032563 INFO : Training has run successfully!
710 05:11:32.033021 Check phy result
711 05:11:32.033534 INFO : End of initialization
712 05:11:32.034023 INFO : End of read enable training
713 05:11:32.034473 INFO : End of fine write leveling
714 05:11:32.034921 INFO : End of Write leveling coarse delay
715 05:11:32.035367 INFO : Training has run successfully!
716 05:11:32.035809 Check phy result
717 05:11:32.036285 INFO : End of initialization
718 05:11:32.036735 INFO : End of read dq deskew training
719 05:11:32.037177 INFO : End of MPR read delay center optimization
720 05:11:32.037615 INFO : End of write delay center optimization
721 05:11:32.038054 INFO : End of read delay center optimization
722 05:11:32.038492 INFO : End of max read latency training
723 05:11:32.038988 INFO : Training has run successfully!
724 05:11:32.039471 1D training succeed
725 05:11:32.039928 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 05:11:32.040421 Check phy result
727 05:11:32.040862 INFO : End of initialization
728 05:11:32.041296 INFO : End of 2D read delay Voltage center optimization
729 05:11:32.041728 INFO : End of 2D read delay Voltage center optimization
730 05:11:32.042159 INFO : End of 2D write delay Voltage center optimization
731 05:11:32.043006 INFO : End of 2D write delay Voltage center optimization
732 05:11:32.043497 INFO : Training has run successfully!
733 05:11:32.043943
734 05:11:32.044481 channel==0
735 05:11:32.044969 RxClkDly_Margin_A0==88 ps 9
736 05:11:32.045415 TxDqDly_Margin_A0==98 ps 10
737 05:11:32.045957 RxClkDly_Margin_A1==88 ps 9
738 05:11:32.046410 TxDqDly_Margin_A1==98 ps 10
739 05:11:32.050161 TrainedVREFDQ_A0==74
740 05:11:32.050766 TrainedVREFDQ_A1==74
741 05:11:32.051253 VrefDac_Margin_A0==25
742 05:11:32.055743 DeviceVref_Margin_A0==40
743 05:11:32.056354 VrefDac_Margin_A1==25
744 05:11:32.056834 DeviceVref_Margin_A1==40
745 05:11:32.057290
746 05:11:32.057742
747 05:11:32.061372 channel==1
748 05:11:32.061937 RxClkDly_Margin_A0==98 ps 10
749 05:11:32.066994 TxDqDly_Margin_A0==88 ps 9
750 05:11:32.067604 RxClkDly_Margin_A1==98 ps 10
751 05:11:32.068126 TxDqDly_Margin_A1==88 ps 9
752 05:11:32.072604 TrainedVREFDQ_A0==76
753 05:11:32.073196 TrainedVREFDQ_A1==77
754 05:11:32.073670 VrefDac_Margin_A0==22
755 05:11:32.078171 DeviceVref_Margin_A0==38
756 05:11:32.078728 VrefDac_Margin_A1==22
757 05:11:32.083755 DeviceVref_Margin_A1==37
758 05:11:32.084353
759 05:11:32.089371 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 05:11:32.089932
761 05:11:32.117317 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
762 05:11:32.117944 2D training succeed
763 05:11:32.122982 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 05:11:32.128549 auto size-- 65535DDR cs0 size: 2048MB
765 05:11:32.129126 DDR cs1 size: 2048MB
766 05:11:32.134159 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 05:11:32.134726 cs0 DataBus test pass
768 05:11:32.139770 cs1 DataBus test pass
769 05:11:32.140379 cs0 AddrBus test pass
770 05:11:32.140839 cs1 AddrBus test pass
771 05:11:32.141287
772 05:11:32.145368 100bdlr_step_size ps== 420
773 05:11:32.145949 result report
774 05:11:32.150939 boot times 0Enable ddr reg access
775 05:11:32.157043 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 05:11:32.170446 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 05:11:32.744176 0.0;M3 CHK:0;cm4_sp_mode 0
778 05:11:32.744870 MVN_1=0x00000000
779 05:11:32.750514 MVN_2=0x00000000
780 05:11:32.755342 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 05:11:32.755684 OPS=0x10
782 05:11:32.755911 ring efuse init
783 05:11:32.756172 chipver efuse init
784 05:11:32.760896 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 05:11:32.766463 [0.018961 Inits done]
786 05:11:32.766802 secure task start!
787 05:11:32.767053 high task start!
788 05:11:32.771013 low task start!
789 05:11:32.771343 run into bl31
790 05:11:32.777736 NOTICE: BL31: v1.3(release):4fc40b1
791 05:11:32.785518 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 05:11:32.786045 NOTICE: BL31: G12A normal boot!
793 05:11:32.810971 NOTICE: BL31: BL33 decompress pass
794 05:11:32.816640 ERROR: Error initializing runtime service opteed_fast
795 05:11:34.049709
796 05:11:34.050383
797 05:11:34.057978 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 05:11:34.058522
799 05:11:34.058994 Model: Libre Computer AML-A311D-CC Alta
800 05:11:34.266468 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 05:11:34.289778 DRAM: 2 GiB (effective 3.8 GiB)
802 05:11:34.432791 Core: 408 devices, 31 uclasses, devicetree: separate
803 05:11:34.438610 WDT: Not starting watchdog@f0d0
804 05:11:34.470894 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 05:11:34.483393 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 05:11:34.488314 ** Bad device specification mmc 0 **
807 05:11:34.498635 Card did not respond to voltage select! : -110
808 05:11:34.506300 ** Bad device specification mmc 0 **
809 05:11:34.506672 Couldn't find partition mmc 0
810 05:11:34.514854 Card did not respond to voltage select! : -110
811 05:11:34.520174 ** Bad device specification mmc 0 **
812 05:11:34.520646 Couldn't find partition mmc 0
813 05:11:34.525209 Error: could not access storage.
814 05:11:34.867714 Net: eth0: ethernet@ff3f0000
815 05:11:34.868427 starting USB...
816 05:11:35.119556 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 05:11:35.120184 Starting the controller
818 05:11:35.126439 USB XHCI 1.10
819 05:11:37.288325 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 05:11:37.288990 bl2_stage_init 0x01
821 05:11:37.289467 bl2_stage_init 0x81
822 05:11:37.293980 hw id: 0x0000 - pwm id 0x01
823 05:11:37.294478 bl2_stage_init 0xc1
824 05:11:37.294935 bl2_stage_init 0x02
825 05:11:37.295385
826 05:11:37.299461 L0:00000000
827 05:11:37.299943 L1:20000703
828 05:11:37.300478 L2:00008067
829 05:11:37.300932 L3:14000000
830 05:11:37.305034 B2:00402000
831 05:11:37.305514 B1:e0f83180
832 05:11:37.305963
833 05:11:37.306407 TE: 58159
834 05:11:37.306860
835 05:11:37.310647 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 05:11:37.311129
837 05:11:37.311585 Board ID = 1
838 05:11:37.316279 Set A53 clk to 24M
839 05:11:37.316775 Set A73 clk to 24M
840 05:11:37.317229 Set clk81 to 24M
841 05:11:37.321892 A53 clk: 1200 MHz
842 05:11:37.322368 A73 clk: 1200 MHz
843 05:11:37.322817 CLK81: 166.6M
844 05:11:37.323259 smccc: 00012ab5
845 05:11:37.327392 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 05:11:37.333078 board id: 1
847 05:11:37.338996 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 05:11:37.349595 fw parse done
849 05:11:37.355570 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 05:11:37.398306 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 05:11:37.409055 PIEI prepare done
852 05:11:37.409600 fastboot data load
853 05:11:37.410058 fastboot data verify
854 05:11:37.414694 verify result: 266
855 05:11:37.420272 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 05:11:37.420764 LPDDR4 probe
857 05:11:37.421219 ddr clk to 1584MHz
858 05:11:37.428284 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 05:11:37.465511
860 05:11:37.466015 dmc_version 0001
861 05:11:37.472222 Check phy result
862 05:11:37.478059 INFO : End of CA training
863 05:11:37.478534 INFO : End of initialization
864 05:11:37.483655 INFO : Training has run successfully!
865 05:11:37.484167 Check phy result
866 05:11:37.489265 INFO : End of initialization
867 05:11:37.489745 INFO : End of read enable training
868 05:11:37.494902 INFO : End of fine write leveling
869 05:11:37.500447 INFO : End of Write leveling coarse delay
870 05:11:37.500763 INFO : Training has run successfully!
871 05:11:37.500989 Check phy result
872 05:11:37.506065 INFO : End of initialization
873 05:11:37.506469 INFO : End of read dq deskew training
874 05:11:37.511641 INFO : End of MPR read delay center optimization
875 05:11:37.517243 INFO : End of write delay center optimization
876 05:11:37.522899 INFO : End of read delay center optimization
877 05:11:37.523196 INFO : End of max read latency training
878 05:11:37.528442 INFO : Training has run successfully!
879 05:11:37.528740 1D training succeed
880 05:11:37.537680 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 05:11:37.585274 Check phy result
882 05:11:37.585651 INFO : End of initialization
883 05:11:37.606826 INFO : End of 2D read delay Voltage center optimization
884 05:11:37.627071 INFO : End of 2D read delay Voltage center optimization
885 05:11:37.678897 INFO : End of 2D write delay Voltage center optimization
886 05:11:37.728193 INFO : End of 2D write delay Voltage center optimization
887 05:11:37.733708 INFO : Training has run successfully!
888 05:11:37.734190
889 05:11:37.734646 channel==0
890 05:11:37.739377 RxClkDly_Margin_A0==88 ps 9
891 05:11:37.739855 TxDqDly_Margin_A0==98 ps 10
892 05:11:37.742671 RxClkDly_Margin_A1==88 ps 9
893 05:11:37.743148 TxDqDly_Margin_A1==98 ps 10
894 05:11:37.748229 TrainedVREFDQ_A0==74
895 05:11:37.748703 TrainedVREFDQ_A1==74
896 05:11:37.753806 VrefDac_Margin_A0==25
897 05:11:37.754319 DeviceVref_Margin_A0==40
898 05:11:37.754772 VrefDac_Margin_A1==25
899 05:11:37.759435 DeviceVref_Margin_A1==40
900 05:11:37.759945
901 05:11:37.760425
902 05:11:37.760857 channel==1
903 05:11:37.761281 RxClkDly_Margin_A0==98 ps 10
904 05:11:37.762876 TxDqDly_Margin_A0==98 ps 10
905 05:11:37.768344 RxClkDly_Margin_A1==88 ps 9
906 05:11:37.768804 TxDqDly_Margin_A1==98 ps 10
907 05:11:37.769240 TrainedVREFDQ_A0==77
908 05:11:37.774046 TrainedVREFDQ_A1==77
909 05:11:37.774505 VrefDac_Margin_A0==22
910 05:11:37.779547 DeviceVref_Margin_A0==37
911 05:11:37.780028 VrefDac_Margin_A1==24
912 05:11:37.780456 DeviceVref_Margin_A1==37
913 05:11:37.780882
914 05:11:37.785215 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 05:11:37.785683
916 05:11:37.818743 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
917 05:11:37.819232 2D training succeed
918 05:11:37.824336 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 05:11:37.829916 auto size-- 65535DDR cs0 size: 2048MB
920 05:11:37.830375 DDR cs1 size: 2048MB
921 05:11:37.835463 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 05:11:37.835921 cs0 DataBus test pass
923 05:11:37.836379 cs1 DataBus test pass
924 05:11:37.841080 cs0 AddrBus test pass
925 05:11:37.841552 cs1 AddrBus test pass
926 05:11:37.841980
927 05:11:37.846684 100bdlr_step_size ps== 420
928 05:11:37.847169 result report
929 05:11:37.847603 boot times 0Enable ddr reg access
930 05:11:37.856671 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 05:11:37.870121 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 05:11:38.442209 0.0;M3 CHK:0;cm4_sp_mode 0
933 05:11:38.442855 MVN_1=0x00000000
934 05:11:38.447608 MVN_2=0x00000000
935 05:11:38.453377 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 05:11:38.453871 OPS=0x10
937 05:11:38.454320 ring efuse init
938 05:11:38.454760 chipver efuse init
939 05:11:38.458992 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 05:11:38.464567 [0.018961 Inits done]
941 05:11:38.465042 secure task start!
942 05:11:38.465489 high task start!
943 05:11:38.469161 low task start!
944 05:11:38.469637 run into bl31
945 05:11:38.475814 NOTICE: BL31: v1.3(release):4fc40b1
946 05:11:38.483604 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 05:11:38.484116 NOTICE: BL31: G12A normal boot!
948 05:11:38.509005 NOTICE: BL31: BL33 decompress pass
949 05:11:38.514637 ERROR: Error initializing runtime service opteed_fast
950 05:11:39.747614
951 05:11:39.748333
952 05:11:39.755876 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 05:11:39.756400
954 05:11:39.756861 Model: Libre Computer AML-A311D-CC Alta
955 05:11:39.964313 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 05:11:39.987672 DRAM: 2 GiB (effective 3.8 GiB)
957 05:11:40.130665 Core: 408 devices, 31 uclasses, devicetree: separate
958 05:11:40.136527 WDT: Not starting watchdog@f0d0
959 05:11:40.168812 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 05:11:40.181264 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 05:11:40.186244 ** Bad device specification mmc 0 **
962 05:11:40.196576 Card did not respond to voltage select! : -110
963 05:11:40.204267 ** Bad device specification mmc 0 **
964 05:11:40.204742 Couldn't find partition mmc 0
965 05:11:40.212551 Card did not respond to voltage select! : -110
966 05:11:40.218081 ** Bad device specification mmc 0 **
967 05:11:40.218560 Couldn't find partition mmc 0
968 05:11:40.223145 Error: could not access storage.
969 05:11:40.565694 Net: eth0: ethernet@ff3f0000
970 05:11:40.566374 starting USB...
971 05:11:40.817544 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 05:11:40.818155 Starting the controller
973 05:11:40.824557 USB XHCI 1.10
974 05:11:42.688057 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 05:11:42.688729 bl2_stage_init 0x01
976 05:11:42.689203 bl2_stage_init 0x81
977 05:11:42.693668 hw id: 0x0000 - pwm id 0x01
978 05:11:42.694188 bl2_stage_init 0xc1
979 05:11:42.694645 bl2_stage_init 0x02
980 05:11:42.695095
981 05:11:42.699242 L0:00000000
982 05:11:42.699749 L1:20000703
983 05:11:42.700246 L2:00008067
984 05:11:42.700696 L3:14000000
985 05:11:42.704840 B2:00402000
986 05:11:42.705343 B1:e0f83180
987 05:11:42.705798
988 05:11:42.706250 TE: 58159
989 05:11:42.706703
990 05:11:42.710430 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 05:11:42.710941
992 05:11:42.711400 Board ID = 1
993 05:11:42.716050 Set A53 clk to 24M
994 05:11:42.716554 Set A73 clk to 24M
995 05:11:42.717001 Set clk81 to 24M
996 05:11:42.721646 A53 clk: 1200 MHz
997 05:11:42.722163 A73 clk: 1200 MHz
998 05:11:42.722619 CLK81: 166.6M
999 05:11:42.723064 smccc: 00012ab5
1000 05:11:42.727221 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 05:11:42.732832 board id: 1
1002 05:11:42.738712 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 05:11:42.749365 fw parse done
1004 05:11:42.755368 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 05:11:42.797972 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 05:11:42.808858 PIEI prepare done
1007 05:11:42.809366 fastboot data load
1008 05:11:42.809803 fastboot data verify
1009 05:11:42.814582 verify result: 266
1010 05:11:42.820179 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 05:11:42.820687 LPDDR4 probe
1012 05:11:42.821121 ddr clk to 1584MHz
1013 05:11:42.828281 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 05:11:42.865579
1015 05:11:42.866081 dmc_version 0001
1016 05:11:42.872257 Check phy result
1017 05:11:42.877992 INFO : End of CA training
1018 05:11:42.878483 INFO : End of initialization
1019 05:11:42.883635 INFO : Training has run successfully!
1020 05:11:42.884178 Check phy result
1021 05:11:42.889298 INFO : End of initialization
1022 05:11:42.889806 INFO : End of read enable training
1023 05:11:42.892642 INFO : End of fine write leveling
1024 05:11:42.898183 INFO : End of Write leveling coarse delay
1025 05:11:42.903895 INFO : Training has run successfully!
1026 05:11:42.904424 Check phy result
1027 05:11:42.904878 INFO : End of initialization
1028 05:11:42.909407 INFO : End of read dq deskew training
1029 05:11:42.914976 INFO : End of MPR read delay center optimization
1030 05:11:42.915478 INFO : End of write delay center optimization
1031 05:11:42.920626 INFO : End of read delay center optimization
1032 05:11:42.926225 INFO : End of max read latency training
1033 05:11:42.926729 INFO : Training has run successfully!
1034 05:11:42.931749 1D training succeed
1035 05:11:42.937517 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 05:11:42.985120 Check phy result
1037 05:11:42.985645 INFO : End of initialization
1038 05:11:43.007569 INFO : End of 2D read delay Voltage center optimization
1039 05:11:43.027726 INFO : End of 2D read delay Voltage center optimization
1040 05:11:43.079572 INFO : End of 2D write delay Voltage center optimization
1041 05:11:43.128850 INFO : End of 2D write delay Voltage center optimization
1042 05:11:43.134384 INFO : Training has run successfully!
1043 05:11:43.134889
1044 05:11:43.135349 channel==0
1045 05:11:43.140009 RxClkDly_Margin_A0==88 ps 9
1046 05:11:43.140522 TxDqDly_Margin_A0==98 ps 10
1047 05:11:43.145604 RxClkDly_Margin_A1==88 ps 9
1048 05:11:43.146114 TxDqDly_Margin_A1==88 ps 9
1049 05:11:43.146572 TrainedVREFDQ_A0==74
1050 05:11:43.151192 TrainedVREFDQ_A1==75
1051 05:11:43.151694 VrefDac_Margin_A0==24
1052 05:11:43.152183 DeviceVref_Margin_A0==40
1053 05:11:43.156818 VrefDac_Margin_A1==25
1054 05:11:43.157335 DeviceVref_Margin_A1==39
1055 05:11:43.157785
1056 05:11:43.158228
1057 05:11:43.158670 channel==1
1058 05:11:43.162412 RxClkDly_Margin_A0==88 ps 9
1059 05:11:43.162917 TxDqDly_Margin_A0==88 ps 9
1060 05:11:43.168010 RxClkDly_Margin_A1==98 ps 10
1061 05:11:43.168523 TxDqDly_Margin_A1==88 ps 9
1062 05:11:43.173605 TrainedVREFDQ_A0==76
1063 05:11:43.174116 TrainedVREFDQ_A1==77
1064 05:11:43.174573 VrefDac_Margin_A0==22
1065 05:11:43.179206 DeviceVref_Margin_A0==38
1066 05:11:43.179709 VrefDac_Margin_A1==22
1067 05:11:43.184807 DeviceVref_Margin_A1==37
1068 05:11:43.185306
1069 05:11:43.185756 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 05:11:43.186200
1071 05:11:43.218366 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 05:11:43.218973 2D training succeed
1073 05:11:43.224098 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 05:11:43.229665 auto size-- 65535DDR cs0 size: 2048MB
1075 05:11:43.230219 DDR cs1 size: 2048MB
1076 05:11:43.235253 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 05:11:43.235798 cs0 DataBus test pass
1078 05:11:43.240846 cs1 DataBus test pass
1079 05:11:43.241389 cs0 AddrBus test pass
1080 05:11:43.241845 cs1 AddrBus test pass
1081 05:11:43.242291
1082 05:11:43.246466 100bdlr_step_size ps== 420
1083 05:11:43.247029 result report
1084 05:11:43.252099 boot times 0Enable ddr reg access
1085 05:11:43.257226 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 05:11:43.270613 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 05:11:43.842607 0.0;M3 CHK:0;cm4_sp_mode 0
1088 05:11:43.843211 MVN_1=0x00000000
1089 05:11:43.848099 MVN_2=0x00000000
1090 05:11:43.853854 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 05:11:43.854362 OPS=0x10
1092 05:11:43.854818 ring efuse init
1093 05:11:43.855260 chipver efuse init
1094 05:11:43.859446 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 05:11:43.865048 [0.018961 Inits done]
1096 05:11:43.865557 secure task start!
1097 05:11:43.866008 high task start!
1098 05:11:43.869621 low task start!
1099 05:11:43.870127 run into bl31
1100 05:11:43.876229 NOTICE: BL31: v1.3(release):4fc40b1
1101 05:11:43.884061 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 05:11:43.884580 NOTICE: BL31: G12A normal boot!
1103 05:11:43.909370 NOTICE: BL31: BL33 decompress pass
1104 05:11:43.915057 ERROR: Error initializing runtime service opteed_fast
1105 05:11:45.148075
1106 05:11:45.148721
1107 05:11:45.156435 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 05:11:45.156997
1109 05:11:45.157460 Model: Libre Computer AML-A311D-CC Alta
1110 05:11:45.364866 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 05:11:45.388254 DRAM: 2 GiB (effective 3.8 GiB)
1112 05:11:45.531195 Core: 408 devices, 31 uclasses, devicetree: separate
1113 05:11:45.537098 WDT: Not starting watchdog@f0d0
1114 05:11:45.569386 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 05:11:45.581761 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 05:11:45.586774 ** Bad device specification mmc 0 **
1117 05:11:45.597128 Card did not respond to voltage select! : -110
1118 05:11:45.604748 ** Bad device specification mmc 0 **
1119 05:11:45.605294 Couldn't find partition mmc 0
1120 05:11:45.613108 Card did not respond to voltage select! : -110
1121 05:11:45.618627 ** Bad device specification mmc 0 **
1122 05:11:45.619180 Couldn't find partition mmc 0
1123 05:11:45.623673 Error: could not access storage.
1124 05:11:45.966369 Net: eth0: ethernet@ff3f0000
1125 05:11:45.967070 starting USB...
1126 05:11:46.218194 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 05:11:46.218914 Starting the controller
1128 05:11:46.225102 USB XHCI 1.10
1129 05:11:47.781297 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 05:11:47.789611 scanning usb for storage devices... 0 Storage Device(s) found
1132 05:11:47.841523 Hit any key to stop autoboot: 1
1133 05:11:47.842489 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 05:11:47.843181 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 05:11:47.843695 Setting prompt string to ['=>']
1136 05:11:47.844266 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 05:11:47.857051 0
1138 05:11:47.858092 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 05:11:47.858655 Sending with 10 millisecond of delay
1141 05:11:48.993708 => setenv autoload no
1142 05:11:49.004595 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 05:11:49.010020 setenv autoload no
1144 05:11:49.010816 Sending with 10 millisecond of delay
1146 05:11:50.808094 => setenv initrd_high 0xffffffff
1147 05:11:50.818969 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 05:11:50.819960 setenv initrd_high 0xffffffff
1149 05:11:50.820789 Sending with 10 millisecond of delay
1151 05:11:52.437885 => setenv fdt_high 0xffffffff
1152 05:11:52.448767 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 05:11:52.449835 setenv fdt_high 0xffffffff
1154 05:11:52.450669 Sending with 10 millisecond of delay
1156 05:11:52.742714 => dhcp
1157 05:11:52.753573 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 05:11:52.754515 dhcp
1159 05:11:52.754998 Speed: 1000, full duplex
1160 05:11:52.755459 BOOTP broadcast 1
1161 05:11:52.762036 DHCP client bound to address 192.168.6.27 (8 ms)
1162 05:11:52.762832 Sending with 10 millisecond of delay
1164 05:11:54.440084 => setenv serverip 192.168.6.2
1165 05:11:54.450954 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 05:11:54.451939 setenv serverip 192.168.6.2
1167 05:11:54.452728 Sending with 10 millisecond of delay
1169 05:11:58.177543 => tftpboot 0x01080000 951328/tftp-deploy-079xnn9n/kernel/uImage
1170 05:11:58.188407 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1171 05:11:58.189355 tftpboot 0x01080000 951328/tftp-deploy-079xnn9n/kernel/uImage
1172 05:11:58.189846 Speed: 1000, full duplex
1173 05:11:58.190304 Using ethernet@ff3f0000 device
1174 05:11:58.191739 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 05:11:58.197222 Filename '951328/tftp-deploy-079xnn9n/kernel/uImage'.
1176 05:11:58.200735 Load address: 0x1080000
1177 05:12:01.060488 Loading: *################################################## 43.6 MiB
1178 05:12:01.061153 15.2 MiB/s
1179 05:12:01.061642 done
1180 05:12:01.065010 Bytes transferred = 45713984 (2b98a40 hex)
1181 05:12:01.065894 Sending with 10 millisecond of delay
1183 05:12:05.754301 => tftpboot 0x08000000 951328/tftp-deploy-079xnn9n/ramdisk/ramdisk.cpio.gz.uboot
1184 05:12:05.765142 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 05:12:05.766049 tftpboot 0x08000000 951328/tftp-deploy-079xnn9n/ramdisk/ramdisk.cpio.gz.uboot
1186 05:12:05.766539 Speed: 1000, full duplex
1187 05:12:05.766996 Using ethernet@ff3f0000 device
1188 05:12:05.768129 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 05:12:05.779680 Filename '951328/tftp-deploy-079xnn9n/ramdisk/ramdisk.cpio.gz.uboot'.
1190 05:12:05.780164 Load address: 0x8000000
1191 05:12:12.475523 Loading: *###################T ############################## UDP wrong checksum 00000005 0000e3f4
1192 05:12:17.475971 T UDP wrong checksum 00000005 0000e3f4
1193 05:12:27.479228 T T UDP wrong checksum 00000005 0000e3f4
1194 05:12:47.480021 T T T UDP wrong checksum 00000005 0000e3f4
1195 05:13:02.487155 T T T
1196 05:13:02.487570 Retry count exceeded; starting again
1198 05:13:02.488958 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1201 05:13:02.490749 end: 2.4 uboot-commands (duration 00:01:52) [common]
1203 05:13:02.492181 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1205 05:13:02.493300 end: 2 uboot-action (duration 00:01:52) [common]
1207 05:13:02.494801 Cleaning after the job
1208 05:13:02.495347 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/ramdisk
1209 05:13:02.496752 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/kernel
1210 05:13:02.522761 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/dtb
1211 05:13:02.524035 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/nfsrootfs
1212 05:13:02.624552 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951328/tftp-deploy-079xnn9n/modules
1213 05:13:02.643007 start: 4.1 power-off (timeout 00:00:30) [common]
1214 05:13:02.643700 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1215 05:13:02.677346 >> OK - accepted request
1216 05:13:02.679287 Returned 0 in 0 seconds
1217 05:13:02.780060 end: 4.1 power-off (duration 00:00:00) [common]
1219 05:13:02.781032 start: 4.2 read-feedback (timeout 00:10:00) [common]
1220 05:13:02.781669 Listened to connection for namespace 'common' for up to 1s
1221 05:13:03.781884 Finalising connection for namespace 'common'
1222 05:13:03.782339 Disconnecting from shell: Finalise
1223 05:13:03.782639 =>
1224 05:13:03.883385 end: 4.2 read-feedback (duration 00:00:01) [common]
1225 05:13:03.883958 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/951328
1226 05:13:06.727337 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/951328
1227 05:13:06.727949 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.