Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:22:32.256153 lava-dispatcher, installed at version: 2024.01
2 05:22:32.256946 start: 0 validate
3 05:22:32.257427 Start time: 2024-11-07 05:22:32.257396+00:00 (UTC)
4 05:22:32.257978 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:22:32.258546 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 05:22:32.299759 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:22:32.300351 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 05:22:32.333562 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:22:32.334193 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:22:32.362949 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:22:32.363477 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:22:32.394251 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:22:32.394767 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-238-g2fd094b86c8ae%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 05:22:32.430132 validate duration: 0.17
16 05:22:32.431056 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:22:32.431397 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:22:32.431752 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:22:32.432369 Not decompressing ramdisk as can be used compressed.
20 05:22:32.432856 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 05:22:32.433150 saving as /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/ramdisk/initrd.cpio.gz
22 05:22:32.433434 total size: 5628140 (5 MB)
23 05:22:32.471843 progress 0 % (0 MB)
24 05:22:32.476075 progress 5 % (0 MB)
25 05:22:32.480332 progress 10 % (0 MB)
26 05:22:32.484170 progress 15 % (0 MB)
27 05:22:32.488418 progress 20 % (1 MB)
28 05:22:32.492153 progress 25 % (1 MB)
29 05:22:32.496242 progress 30 % (1 MB)
30 05:22:32.500493 progress 35 % (1 MB)
31 05:22:32.504218 progress 40 % (2 MB)
32 05:22:32.508359 progress 45 % (2 MB)
33 05:22:32.512057 progress 50 % (2 MB)
34 05:22:32.516191 progress 55 % (2 MB)
35 05:22:32.520257 progress 60 % (3 MB)
36 05:22:32.523855 progress 65 % (3 MB)
37 05:22:32.527923 progress 70 % (3 MB)
38 05:22:32.531571 progress 75 % (4 MB)
39 05:22:32.535580 progress 80 % (4 MB)
40 05:22:32.539296 progress 85 % (4 MB)
41 05:22:32.543388 progress 90 % (4 MB)
42 05:22:32.547399 progress 95 % (5 MB)
43 05:22:32.550758 progress 100 % (5 MB)
44 05:22:32.551493 5 MB downloaded in 0.12 s (45.47 MB/s)
45 05:22:32.552082 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:22:32.552986 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:22:32.553277 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:22:32.553551 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:22:32.554022 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/kernel/Image
51 05:22:32.554293 saving as /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/kernel/Image
52 05:22:32.554504 total size: 45713920 (43 MB)
53 05:22:32.554716 No compression specified
54 05:22:32.594393 progress 0 % (0 MB)
55 05:22:32.623505 progress 5 % (2 MB)
56 05:22:32.653887 progress 10 % (4 MB)
57 05:22:32.684302 progress 15 % (6 MB)
58 05:22:32.714430 progress 20 % (8 MB)
59 05:22:32.744536 progress 25 % (10 MB)
60 05:22:32.774808 progress 30 % (13 MB)
61 05:22:32.805109 progress 35 % (15 MB)
62 05:22:32.835727 progress 40 % (17 MB)
63 05:22:32.865388 progress 45 % (19 MB)
64 05:22:32.895800 progress 50 % (21 MB)
65 05:22:32.926143 progress 55 % (24 MB)
66 05:22:32.956710 progress 60 % (26 MB)
67 05:22:32.986562 progress 65 % (28 MB)
68 05:22:33.017095 progress 70 % (30 MB)
69 05:22:33.047819 progress 75 % (32 MB)
70 05:22:33.078298 progress 80 % (34 MB)
71 05:22:33.108237 progress 85 % (37 MB)
72 05:22:33.138591 progress 90 % (39 MB)
73 05:22:33.168962 progress 95 % (41 MB)
74 05:22:33.198453 progress 100 % (43 MB)
75 05:22:33.198998 43 MB downloaded in 0.64 s (67.65 MB/s)
76 05:22:33.199472 end: 1.2.1 http-download (duration 00:00:01) [common]
78 05:22:33.200330 end: 1.2 download-retry (duration 00:00:01) [common]
79 05:22:33.200607 start: 1.3 download-retry (timeout 00:09:59) [common]
80 05:22:33.200873 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 05:22:33.201319 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 05:22:33.201590 saving as /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/dtb/meson-g12b-a311d-libretech-cc.dtb
83 05:22:33.201797 total size: 54703 (0 MB)
84 05:22:33.202005 No compression specified
85 05:22:33.242277 progress 59 % (0 MB)
86 05:22:33.243142 progress 100 % (0 MB)
87 05:22:33.243692 0 MB downloaded in 0.04 s (1.25 MB/s)
88 05:22:33.244199 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:22:33.245026 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:22:33.245294 start: 1.4 download-retry (timeout 00:09:59) [common]
92 05:22:33.245557 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 05:22:33.246029 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 05:22:33.246277 saving as /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/nfsrootfs/full.rootfs.tar
95 05:22:33.246482 total size: 474398908 (452 MB)
96 05:22:33.246693 Using unxz to decompress xz
97 05:22:33.286092 progress 0 % (0 MB)
98 05:22:34.515729 progress 5 % (22 MB)
99 05:22:35.957738 progress 10 % (45 MB)
100 05:22:36.415410 progress 15 % (67 MB)
101 05:22:37.266695 progress 20 % (90 MB)
102 05:22:37.803656 progress 25 % (113 MB)
103 05:22:38.179630 progress 30 % (135 MB)
104 05:22:38.805936 progress 35 % (158 MB)
105 05:22:39.739925 progress 40 % (181 MB)
106 05:22:40.607237 progress 45 % (203 MB)
107 05:22:41.242942 progress 50 % (226 MB)
108 05:22:41.902485 progress 55 % (248 MB)
109 05:22:43.135315 progress 60 % (271 MB)
110 05:22:44.618170 progress 65 % (294 MB)
111 05:22:46.288012 progress 70 % (316 MB)
112 05:22:49.411697 progress 75 % (339 MB)
113 05:22:51.847770 progress 80 % (361 MB)
114 05:22:54.786430 progress 85 % (384 MB)
115 05:22:57.955341 progress 90 % (407 MB)
116 05:23:01.152352 progress 95 % (429 MB)
117 05:23:04.316755 progress 100 % (452 MB)
118 05:23:04.329680 452 MB downloaded in 31.08 s (14.56 MB/s)
119 05:23:04.330622 end: 1.4.1 http-download (duration 00:00:31) [common]
121 05:23:04.332454 end: 1.4 download-retry (duration 00:00:31) [common]
122 05:23:04.333101 start: 1.5 download-retry (timeout 00:09:28) [common]
123 05:23:04.333677 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 05:23:04.334535 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-238-g2fd094b86c8ae/arm64/defconfig/gcc-12/modules.tar.xz
125 05:23:04.335029 saving as /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/modules/modules.tar
126 05:23:04.335476 total size: 11607084 (11 MB)
127 05:23:04.335935 Using unxz to decompress xz
128 05:23:04.380430 progress 0 % (0 MB)
129 05:23:04.450200 progress 5 % (0 MB)
130 05:23:04.525944 progress 10 % (1 MB)
131 05:23:04.626351 progress 15 % (1 MB)
132 05:23:04.718189 progress 20 % (2 MB)
133 05:23:04.798841 progress 25 % (2 MB)
134 05:23:04.875665 progress 30 % (3 MB)
135 05:23:04.950254 progress 35 % (3 MB)
136 05:23:05.027764 progress 40 % (4 MB)
137 05:23:05.104356 progress 45 % (5 MB)
138 05:23:05.188956 progress 50 % (5 MB)
139 05:23:05.268360 progress 55 % (6 MB)
140 05:23:05.354414 progress 60 % (6 MB)
141 05:23:05.435229 progress 65 % (7 MB)
142 05:23:05.512426 progress 70 % (7 MB)
143 05:23:05.594928 progress 75 % (8 MB)
144 05:23:05.678785 progress 80 % (8 MB)
145 05:23:05.760288 progress 85 % (9 MB)
146 05:23:05.838781 progress 90 % (9 MB)
147 05:23:05.916302 progress 95 % (10 MB)
148 05:23:05.993022 progress 100 % (11 MB)
149 05:23:06.004492 11 MB downloaded in 1.67 s (6.63 MB/s)
150 05:23:06.005409 end: 1.5.1 http-download (duration 00:00:02) [common]
152 05:23:06.007200 end: 1.5 download-retry (duration 00:00:02) [common]
153 05:23:06.007771 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 05:23:06.008392 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 05:23:21.419351 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/951358/extract-nfsrootfs-fiefuc0o
156 05:23:21.419949 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 05:23:21.420290 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 05:23:21.421064 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld
159 05:23:21.421556 makedir: /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin
160 05:23:21.421937 makedir: /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/tests
161 05:23:21.422330 makedir: /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/results
162 05:23:21.422676 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-add-keys
163 05:23:21.423263 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-add-sources
164 05:23:21.423843 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-background-process-start
165 05:23:21.424386 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-background-process-stop
166 05:23:21.424917 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-common-functions
167 05:23:21.425412 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-echo-ipv4
168 05:23:21.425895 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-install-packages
169 05:23:21.426379 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-installed-packages
170 05:23:21.426870 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-os-build
171 05:23:21.427348 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-probe-channel
172 05:23:21.427827 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-probe-ip
173 05:23:21.428383 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-target-ip
174 05:23:21.428868 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-target-mac
175 05:23:21.429370 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-target-storage
176 05:23:21.429885 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-test-case
177 05:23:21.430418 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-test-event
178 05:23:21.430909 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-test-feedback
179 05:23:21.431384 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-test-raise
180 05:23:21.431857 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-test-reference
181 05:23:21.432378 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-test-runner
182 05:23:21.432870 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-test-set
183 05:23:21.433399 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-test-shell
184 05:23:21.433903 Updating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-install-packages (oe)
185 05:23:21.434438 Updating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/bin/lava-installed-packages (oe)
186 05:23:21.434870 Creating /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/environment
187 05:23:21.435250 LAVA metadata
188 05:23:21.435505 - LAVA_JOB_ID=951358
189 05:23:21.435717 - LAVA_DISPATCHER_IP=192.168.6.2
190 05:23:21.436114 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 05:23:21.437067 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 05:23:21.437370 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 05:23:21.437580 skipped lava-vland-overlay
194 05:23:21.437819 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 05:23:21.438072 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 05:23:21.438289 skipped lava-multinode-overlay
197 05:23:21.438528 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 05:23:21.438778 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 05:23:21.439022 Loading test definitions
200 05:23:21.439296 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 05:23:21.439512 Using /lava-951358 at stage 0
202 05:23:21.440697 uuid=951358_1.6.2.4.1 testdef=None
203 05:23:21.441004 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 05:23:21.441265 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 05:23:21.443029 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 05:23:21.443813 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 05:23:21.446019 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 05:23:21.446840 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 05:23:21.448936 runner path: /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 951358_1.6.2.4.1
212 05:23:21.449483 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 05:23:21.450229 Creating lava-test-runner.conf files
215 05:23:21.450427 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/951358/lava-overlay-kwf5q1ld/lava-951358/0 for stage 0
216 05:23:21.450766 - 0_v4l2-decoder-conformance-vp9
217 05:23:21.451095 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 05:23:21.451365 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 05:23:21.472879 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 05:23:21.473238 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 05:23:21.473493 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 05:23:21.473756 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 05:23:21.474013 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 05:23:22.097184 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 05:23:22.097670 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 05:23:22.097939 extracting modules file /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/951358/extract-nfsrootfs-fiefuc0o
227 05:23:23.493219 extracting modules file /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/951358/extract-overlay-ramdisk-f1aof78f/ramdisk
228 05:23:24.908893 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 05:23:24.909378 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 05:23:24.909722 [common] Applying overlay to NFS
231 05:23:24.909961 [common] Applying overlay /var/lib/lava/dispatcher/tmp/951358/compress-overlay-goqb9d6u/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/951358/extract-nfsrootfs-fiefuc0o
232 05:23:24.939241 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 05:23:24.939656 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 05:23:24.939946 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 05:23:24.940208 Converting downloaded kernel to a uImage
236 05:23:24.940530 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/kernel/Image /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/kernel/uImage
237 05:23:25.507130 output: Image Name:
238 05:23:25.507554 output: Created: Thu Nov 7 05:23:24 2024
239 05:23:25.507783 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 05:23:25.508032 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 05:23:25.508251 output: Load Address: 01080000
242 05:23:25.508459 output: Entry Point: 01080000
243 05:23:25.508664 output:
244 05:23:25.509002 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 05:23:25.509282 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 05:23:25.509564 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 05:23:25.509830 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 05:23:25.510100 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 05:23:25.510376 Building ramdisk /var/lib/lava/dispatcher/tmp/951358/extract-overlay-ramdisk-f1aof78f/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/951358/extract-overlay-ramdisk-f1aof78f/ramdisk
250 05:23:27.827887 >> 166792 blocks
251 05:23:35.572622 Adding RAMdisk u-boot header.
252 05:23:35.573072 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/951358/extract-overlay-ramdisk-f1aof78f/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/951358/extract-overlay-ramdisk-f1aof78f/ramdisk.cpio.gz.uboot
253 05:23:35.994139 output: Image Name:
254 05:23:35.994731 output: Created: Thu Nov 7 05:23:35 2024
255 05:23:35.995066 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 05:23:35.995339 output: Data Size: 23432099 Bytes = 22882.91 KiB = 22.35 MiB
257 05:23:35.995606 output: Load Address: 00000000
258 05:23:35.995872 output: Entry Point: 00000000
259 05:23:35.996679 output:
260 05:23:35.999035 rename /var/lib/lava/dispatcher/tmp/951358/extract-overlay-ramdisk-f1aof78f/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/ramdisk/ramdisk.cpio.gz.uboot
261 05:23:36.000640 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 05:23:36.001839 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 05:23:36.002878 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 05:23:36.003861 No LXC device requested
265 05:23:36.005081 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 05:23:36.006159 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 05:23:36.007239 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 05:23:36.008126 Checking files for TFTP limit of 4294967296 bytes.
269 05:23:36.014973 end: 1 tftp-deploy (duration 00:01:04) [common]
270 05:23:36.016478 start: 2 uboot-action (timeout 00:05:00) [common]
271 05:23:36.017729 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 05:23:36.019172 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 05:23:36.020434 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 05:23:36.021063 Using kernel file from prepare-kernel: 951358/tftp-deploy-kzcjs9zu/kernel/uImage
275 05:23:36.021681 substitutions:
276 05:23:36.022173 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 05:23:36.022631 - {DTB_ADDR}: 0x01070000
278 05:23:36.023013 - {DTB}: 951358/tftp-deploy-kzcjs9zu/dtb/meson-g12b-a311d-libretech-cc.dtb
279 05:23:36.023367 - {INITRD}: 951358/tftp-deploy-kzcjs9zu/ramdisk/ramdisk.cpio.gz.uboot
280 05:23:36.023750 - {KERNEL_ADDR}: 0x01080000
281 05:23:36.024312 - {KERNEL}: 951358/tftp-deploy-kzcjs9zu/kernel/uImage
282 05:23:36.025129 - {LAVA_MAC}: None
283 05:23:36.026081 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/951358/extract-nfsrootfs-fiefuc0o
284 05:23:36.026860 - {NFS_SERVER_IP}: 192.168.6.2
285 05:23:36.027712 - {PRESEED_CONFIG}: None
286 05:23:36.028547 - {PRESEED_LOCAL}: None
287 05:23:36.029394 - {RAMDISK_ADDR}: 0x08000000
288 05:23:36.030143 - {RAMDISK}: 951358/tftp-deploy-kzcjs9zu/ramdisk/ramdisk.cpio.gz.uboot
289 05:23:36.030967 - {ROOT_PART}: None
290 05:23:36.031720 - {ROOT}: None
291 05:23:36.032614 - {SERVER_IP}: 192.168.6.2
292 05:23:36.033324 - {TEE_ADDR}: 0x83000000
293 05:23:36.033945 - {TEE}: None
294 05:23:36.034671 Parsed boot commands:
295 05:23:36.035310 - setenv autoload no
296 05:23:36.036104 - setenv initrd_high 0xffffffff
297 05:23:36.036407 - setenv fdt_high 0xffffffff
298 05:23:36.036679 - dhcp
299 05:23:36.036943 - setenv serverip 192.168.6.2
300 05:23:36.037251 - tftpboot 0x01080000 951358/tftp-deploy-kzcjs9zu/kernel/uImage
301 05:23:36.037549 - tftpboot 0x08000000 951358/tftp-deploy-kzcjs9zu/ramdisk/ramdisk.cpio.gz.uboot
302 05:23:36.037840 - tftpboot 0x01070000 951358/tftp-deploy-kzcjs9zu/dtb/meson-g12b-a311d-libretech-cc.dtb
303 05:23:36.038107 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/951358/extract-nfsrootfs-fiefuc0o,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 05:23:36.038376 - bootm 0x01080000 0x08000000 0x01070000
305 05:23:36.038778 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 05:23:36.039891 start: 2.3 connect-device (timeout 00:05:00) [common]
308 05:23:36.040261 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 05:23:36.053945 Setting prompt string to ['lava-test: # ']
310 05:23:36.055363 end: 2.3 connect-device (duration 00:00:00) [common]
311 05:23:36.055842 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 05:23:36.056314 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 05:23:36.056815 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 05:23:36.057790 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 05:23:36.101105 >> OK - accepted request
316 05:23:36.103804 Returned 0 in 0 seconds
317 05:23:36.206072 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 05:23:36.209393 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 05:23:36.210610 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 05:23:36.211624 Setting prompt string to ['Hit any key to stop autoboot']
322 05:23:36.212581 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 05:23:36.215530 Trying 192.168.56.21...
324 05:23:36.216573 Connected to conserv1.
325 05:23:36.217413 Escape character is '^]'.
326 05:23:36.218258
327 05:23:36.219038 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 05:23:36.219864
329 05:23:47.801925 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 05:23:47.802597 bl2_stage_init 0x01
331 05:23:47.803064 bl2_stage_init 0x81
332 05:23:47.807490 hw id: 0x0000 - pwm id 0x01
333 05:23:47.808036 bl2_stage_init 0xc1
334 05:23:47.808485 bl2_stage_init 0x02
335 05:23:47.808917
336 05:23:47.813088 L0:00000000
337 05:23:47.813588 L1:20000703
338 05:23:47.814025 L2:00008067
339 05:23:47.814454 L3:14000000
340 05:23:47.818680 B2:00402000
341 05:23:47.819170 B1:e0f83180
342 05:23:47.819619
343 05:23:47.820090 TE: 58124
344 05:23:47.820527
345 05:23:47.824266 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 05:23:47.824740
347 05:23:47.825176 Board ID = 1
348 05:23:47.829903 Set A53 clk to 24M
349 05:23:47.830380 Set A73 clk to 24M
350 05:23:47.830816 Set clk81 to 24M
351 05:23:47.835443 A53 clk: 1200 MHz
352 05:23:47.835916 A73 clk: 1200 MHz
353 05:23:47.836383 CLK81: 166.6M
354 05:23:47.836807 smccc: 00012a92
355 05:23:47.841024 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 05:23:47.846650 board id: 1
357 05:23:47.852495 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 05:23:47.863217 fw parse done
359 05:23:47.868297 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 05:23:47.911785 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 05:23:47.922672 PIEI prepare done
362 05:23:47.923169 fastboot data load
363 05:23:47.923607 fastboot data verify
364 05:23:47.928287 verify result: 266
365 05:23:47.933899 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 05:23:47.934381 LPDDR4 probe
367 05:23:47.934817 ddr clk to 1584MHz
368 05:23:47.941851 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 05:23:47.979161
370 05:23:47.979663 dmc_version 0001
371 05:23:47.985805 Check phy result
372 05:23:47.991700 INFO : End of CA training
373 05:23:47.992218 INFO : End of initialization
374 05:23:47.997272 INFO : Training has run successfully!
375 05:23:47.997759 Check phy result
376 05:23:48.002871 INFO : End of initialization
377 05:23:48.003339 INFO : End of read enable training
378 05:23:48.006130 INFO : End of fine write leveling
379 05:23:48.011726 INFO : End of Write leveling coarse delay
380 05:23:48.017307 INFO : Training has run successfully!
381 05:23:48.017806 Check phy result
382 05:23:48.018241 INFO : End of initialization
383 05:23:48.022955 INFO : End of read dq deskew training
384 05:23:48.028493 INFO : End of MPR read delay center optimization
385 05:23:48.028989 INFO : End of write delay center optimization
386 05:23:48.034104 INFO : End of read delay center optimization
387 05:23:48.039701 INFO : End of max read latency training
388 05:23:48.040229 INFO : Training has run successfully!
389 05:23:48.045234 1D training succeed
390 05:23:48.051232 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 05:23:48.098858 Check phy result
392 05:23:48.099375 INFO : End of initialization
393 05:23:48.121509 INFO : End of 2D read delay Voltage center optimization
394 05:23:48.141821 INFO : End of 2D read delay Voltage center optimization
395 05:23:48.193772 INFO : End of 2D write delay Voltage center optimization
396 05:23:48.243177 INFO : End of 2D write delay Voltage center optimization
397 05:23:48.248782 INFO : Training has run successfully!
398 05:23:48.249277
399 05:23:48.249736 channel==0
400 05:23:48.254219 RxClkDly_Margin_A0==88 ps 9
401 05:23:48.254682 TxDqDly_Margin_A0==98 ps 10
402 05:23:48.259879 RxClkDly_Margin_A1==88 ps 9
403 05:23:48.260386 TxDqDly_Margin_A1==98 ps 10
404 05:23:48.260836 TrainedVREFDQ_A0==74
405 05:23:48.265541 TrainedVREFDQ_A1==75
406 05:23:48.266024 VrefDac_Margin_A0==25
407 05:23:48.266462 DeviceVref_Margin_A0==40
408 05:23:48.271081 VrefDac_Margin_A1==25
409 05:23:48.271543 DeviceVref_Margin_A1==39
410 05:23:48.271974
411 05:23:48.272440
412 05:23:48.276763 channel==1
413 05:23:48.277229 RxClkDly_Margin_A0==98 ps 10
414 05:23:48.277660 TxDqDly_Margin_A0==88 ps 9
415 05:23:48.282209 RxClkDly_Margin_A1==98 ps 10
416 05:23:48.282693 TxDqDly_Margin_A1==88 ps 9
417 05:23:48.287892 TrainedVREFDQ_A0==76
418 05:23:48.288412 TrainedVREFDQ_A1==77
419 05:23:48.288855 VrefDac_Margin_A0==22
420 05:23:48.293582 DeviceVref_Margin_A0==38
421 05:23:48.294049 VrefDac_Margin_A1==22
422 05:23:48.299110 DeviceVref_Margin_A1==37
423 05:23:48.299594
424 05:23:48.300077 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 05:23:48.300522
426 05:23:48.332785 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000018 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000018 dram_vref_reg_value 0x 00000060
427 05:23:48.333409 2D training succeed
428 05:23:48.338319 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 05:23:48.343734 auto size-- 65535DDR cs0 size: 2048MB
430 05:23:48.344286 DDR cs1 size: 2048MB
431 05:23:48.349441 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 05:23:48.349928 cs0 DataBus test pass
433 05:23:48.355036 cs1 DataBus test pass
434 05:23:48.355514 cs0 AddrBus test pass
435 05:23:48.355950 cs1 AddrBus test pass
436 05:23:48.356419
437 05:23:48.360700 100bdlr_step_size ps== 420
438 05:23:48.361177 result report
439 05:23:48.366140 boot times 0Enable ddr reg access
440 05:23:48.371561 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 05:23:48.385110 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 05:23:48.958707 0.0;M3 CHK:0;cm4_sp_mode 0
443 05:23:48.959385 MVN_1=0x00000000
444 05:23:48.964191 MVN_2=0x00000000
445 05:23:48.969990 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 05:23:48.970492 OPS=0x10
447 05:23:48.970950 ring efuse init
448 05:23:48.971396 chipver efuse init
449 05:23:48.978282 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 05:23:48.978806 [0.018961 Inits done]
451 05:23:48.979260 secure task start!
452 05:23:48.985807 high task start!
453 05:23:48.986291 low task start!
454 05:23:48.986739 run into bl31
455 05:23:48.992382 NOTICE: BL31: v1.3(release):4fc40b1
456 05:23:49.000160 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 05:23:49.000662 NOTICE: BL31: G12A normal boot!
458 05:23:49.025599 NOTICE: BL31: BL33 decompress pass
459 05:23:49.031257 ERROR: Error initializing runtime service opteed_fast
460 05:23:50.264811
461 05:23:50.265643
462 05:23:50.272490 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 05:23:50.273618
464 05:23:50.274285 Model: Libre Computer AML-A311D-CC Alta
465 05:23:50.481060 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 05:23:50.504349 DRAM: 2 GiB (effective 3.8 GiB)
467 05:23:50.647400 Core: 408 devices, 31 uclasses, devicetree: separate
468 05:23:50.653207 WDT: Not starting watchdog@f0d0
469 05:23:50.685548 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 05:23:50.697947 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 05:23:50.702881 ** Bad device specification mmc 0 **
472 05:23:50.713172 Card did not respond to voltage select! : -110
473 05:23:50.720900 ** Bad device specification mmc 0 **
474 05:23:50.721235 Couldn't find partition mmc 0
475 05:23:50.729314 Card did not respond to voltage select! : -110
476 05:23:50.734838 ** Bad device specification mmc 0 **
477 05:23:50.735353 Couldn't find partition mmc 0
478 05:23:50.739918 Error: could not access storage.
479 05:23:52.002551 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
480 05:23:52.003161 bl2_stage_init 0x81
481 05:23:52.008107 hw id: 0x0000 - pwm id 0x01
482 05:23:52.008629 bl2_stage_init 0xc1
483 05:23:52.009056 bl2_stage_init 0x02
484 05:23:52.009469
485 05:23:52.013647 L0:00000000
486 05:23:52.014144 L1:20000703
487 05:23:52.014557 L2:00008067
488 05:23:52.014957 L3:14000000
489 05:23:52.015348 B2:00402000
490 05:23:52.019286 B1:e0f83180
491 05:23:52.019800
492 05:23:52.020258 TE: 58150
493 05:23:52.020674
494 05:23:52.024884 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 05:23:52.025403
496 05:23:52.025816 Board ID = 1
497 05:23:52.030480 Set A53 clk to 24M
498 05:23:52.030968 Set A73 clk to 24M
499 05:23:52.031376 Set clk81 to 24M
500 05:23:52.036089 A53 clk: 1200 MHz
501 05:23:52.036589 A73 clk: 1200 MHz
502 05:23:52.037003 CLK81: 166.6M
503 05:23:52.037405 smccc: 00012aac
504 05:23:52.041642 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 05:23:52.047263 board id: 1
506 05:23:52.053063 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 05:23:52.063715 fw parse done
508 05:23:52.069672 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 05:23:52.112318 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 05:23:52.123222 PIEI prepare done
511 05:23:52.123709 fastboot data load
512 05:23:52.124165 fastboot data verify
513 05:23:52.128869 verify result: 266
514 05:23:52.134456 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 05:23:52.134925 LPDDR4 probe
516 05:23:52.135337 ddr clk to 1584MHz
517 05:23:52.142462 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 05:23:52.178815
519 05:23:52.179323 dmc_version 0001
520 05:23:52.186401 Check phy result
521 05:23:52.192311 INFO : End of CA training
522 05:23:52.192787 INFO : End of initialization
523 05:23:52.197846 INFO : Training has run successfully!
524 05:23:52.198317 Check phy result
525 05:23:52.203443 INFO : End of initialization
526 05:23:52.203915 INFO : End of read enable training
527 05:23:52.209035 INFO : End of fine write leveling
528 05:23:52.214626 INFO : End of Write leveling coarse delay
529 05:23:52.215099 INFO : Training has run successfully!
530 05:23:52.215509 Check phy result
531 05:23:52.220338 INFO : End of initialization
532 05:23:52.220818 INFO : End of read dq deskew training
533 05:23:52.225844 INFO : End of MPR read delay center optimization
534 05:23:52.231435 INFO : End of write delay center optimization
535 05:23:52.237072 INFO : End of read delay center optimization
536 05:23:52.237553 INFO : End of max read latency training
537 05:23:52.242654 INFO : Training has run successfully!
538 05:23:52.243136 1D training succeed
539 05:23:52.251791 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 05:23:52.299504 Check phy result
541 05:23:52.300111 INFO : End of initialization
542 05:23:52.321188 INFO : End of 2D read delay Voltage center optimization
543 05:23:52.340514 INFO : End of 2D read delay Voltage center optimization
544 05:23:52.393631 INFO : End of 2D write delay Voltage center optimization
545 05:23:52.442898 INFO : End of 2D write delay Voltage center optimization
546 05:23:52.448423 INFO : Training has run successfully!
547 05:23:52.448900
548 05:23:52.449318 channel==0
549 05:23:52.454043 RxClkDly_Margin_A0==88 ps 9
550 05:23:52.454517 TxDqDly_Margin_A0==98 ps 10
551 05:23:52.457395 RxClkDly_Margin_A1==88 ps 9
552 05:23:52.457855 TxDqDly_Margin_A1==88 ps 9
553 05:23:52.462965 TrainedVREFDQ_A0==74
554 05:23:52.463443 TrainedVREFDQ_A1==74
555 05:23:52.463856 VrefDac_Margin_A0==25
556 05:23:52.468578 DeviceVref_Margin_A0==40
557 05:23:52.469042 VrefDac_Margin_A1==25
558 05:23:52.474155 DeviceVref_Margin_A1==40
559 05:23:52.474637
560 05:23:52.475050
561 05:23:52.475450 channel==1
562 05:23:52.475842 RxClkDly_Margin_A0==98 ps 10
563 05:23:52.479726 TxDqDly_Margin_A0==88 ps 9
564 05:23:52.480225 RxClkDly_Margin_A1==98 ps 10
565 05:23:52.485350 TxDqDly_Margin_A1==88 ps 9
566 05:23:52.485808 TrainedVREFDQ_A0==77
567 05:23:52.486216 TrainedVREFDQ_A1==77
568 05:23:52.490943 VrefDac_Margin_A0==22
569 05:23:52.491404 DeviceVref_Margin_A0==37
570 05:23:52.496544 VrefDac_Margin_A1==22
571 05:23:52.496996 DeviceVref_Margin_A1==37
572 05:23:52.497408
573 05:23:52.502214 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 05:23:52.502730
575 05:23:52.530118 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
576 05:23:52.535807 2D training succeed
577 05:23:52.541423 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 05:23:52.541914 auto size-- 65535DDR cs0 size: 2048MB
579 05:23:52.547001 DDR cs1 size: 2048MB
580 05:23:52.547475 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 05:23:52.552576 cs0 DataBus test pass
582 05:23:52.553045 cs1 DataBus test pass
583 05:23:52.553451 cs0 AddrBus test pass
584 05:23:52.558131 cs1 AddrBus test pass
585 05:23:52.558603
586 05:23:52.559013 100bdlr_step_size ps== 420
587 05:23:52.559424 result report
588 05:23:52.563751 boot times 0Enable ddr reg access
589 05:23:52.571410 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 05:23:52.584746 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 05:23:53.157902 0.0;M3 CHK:0;cm4_sp_mode 0
592 05:23:53.158543 MVN_1=0x00000000
593 05:23:53.163731 MVN_2=0x00000000
594 05:23:53.169226 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 05:23:53.169515 OPS=0x10
596 05:23:53.169740 ring efuse init
597 05:23:53.169956 chipver efuse init
598 05:23:53.174638 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 05:23:53.180270 [0.018961 Inits done]
600 05:23:53.180525 secure task start!
601 05:23:53.180729 high task start!
602 05:23:53.184748 low task start!
603 05:23:53.184974 run into bl31
604 05:23:53.191422 NOTICE: BL31: v1.3(release):4fc40b1
605 05:23:53.199336 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 05:23:53.199563 NOTICE: BL31: G12A normal boot!
607 05:23:53.224671 NOTICE: BL31: BL33 decompress pass
608 05:23:53.230484 ERROR: Error initializing runtime service opteed_fast
609 05:23:54.463467
610 05:23:54.464194
611 05:23:54.471876 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 05:23:54.472425
613 05:23:54.472896 Model: Libre Computer AML-A311D-CC Alta
614 05:23:54.680297 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 05:23:54.703770 DRAM: 2 GiB (effective 3.8 GiB)
616 05:23:54.846699 Core: 408 devices, 31 uclasses, devicetree: separate
617 05:23:54.852489 WDT: Not starting watchdog@f0d0
618 05:23:54.884798 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 05:23:54.897168 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 05:23:54.902217 ** Bad device specification mmc 0 **
621 05:23:54.912857 Card did not respond to voltage select! : -110
622 05:23:54.920295 ** Bad device specification mmc 0 **
623 05:23:54.920818 Couldn't find partition mmc 0
624 05:23:54.928735 Card did not respond to voltage select! : -110
625 05:23:54.934137 ** Bad device specification mmc 0 **
626 05:23:54.934670 Couldn't find partition mmc 0
627 05:23:54.939168 Error: could not access storage.
628 05:23:55.282633 Net: eth0: ethernet@ff3f0000
629 05:23:55.283043 starting USB...
630 05:23:55.534480 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 05:23:55.535114 Starting the controller
632 05:23:55.541369 USB XHCI 1.10
633 05:23:57.252954 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
634 05:23:57.253645 bl2_stage_init 0x81
635 05:23:57.258342 hw id: 0x0000 - pwm id 0x01
636 05:23:57.258853 bl2_stage_init 0xc1
637 05:23:57.259322 bl2_stage_init 0x02
638 05:23:57.259772
639 05:23:57.264084 L0:00000000
640 05:23:57.264591 L1:20000703
641 05:23:57.265047 L2:00008067
642 05:23:57.265498 L3:14000000
643 05:23:57.265939 B2:00402000
644 05:23:57.266901 B1:e0f83180
645 05:23:57.267379
646 05:23:57.267826 TE: 58150
647 05:23:57.268340
648 05:23:57.277867 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
649 05:23:57.278367
650 05:23:57.278822 Board ID = 1
651 05:23:57.279263 Set A53 clk to 24M
652 05:23:57.279703 Set A73 clk to 24M
653 05:23:57.283519 Set clk81 to 24M
654 05:23:57.284030 A53 clk: 1200 MHz
655 05:23:57.284483 A73 clk: 1200 MHz
656 05:23:57.289121 CLK81: 166.6M
657 05:23:57.289602 smccc: 00012aac
658 05:23:57.294804 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
659 05:23:57.295290 board id: 1
660 05:23:57.303283 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
661 05:23:57.313978 fw parse done
662 05:23:57.320039 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
663 05:23:57.362658 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
664 05:23:57.373396 PIEI prepare done
665 05:23:57.373893 fastboot data load
666 05:23:57.374346 fastboot data verify
667 05:23:57.378983 verify result: 266
668 05:23:57.384586 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
669 05:23:57.385082 LPDDR4 probe
670 05:23:57.385530 ddr clk to 1584MHz
671 05:23:57.392615 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
672 05:23:57.429933
673 05:23:57.430563 dmc_version 0001
674 05:23:57.436523 Check phy result
675 05:23:57.442364 INFO : End of CA training
676 05:23:57.442867 INFO : End of initialization
677 05:23:57.448058 INFO : Training has run successfully!
678 05:23:57.448608 Check phy result
679 05:23:57.453695 INFO : End of initialization
680 05:23:57.454187 INFO : End of read enable training
681 05:23:57.456992 INFO : End of fine write leveling
682 05:23:57.462506 INFO : End of Write leveling coarse delay
683 05:23:57.468183 INFO : Training has run successfully!
684 05:23:57.468681 Check phy result
685 05:23:57.469100 INFO : End of initialization
686 05:23:57.473727 INFO : End of read dq deskew training
687 05:23:57.477107 INFO : End of MPR read delay center optimization
688 05:23:57.482688 INFO : End of write delay center optimization
689 05:23:57.488270 INFO : End of read delay center optimization
690 05:23:57.488774 INFO : End of max read latency training
691 05:23:57.493955 INFO : Training has run successfully!
692 05:23:57.494541 1D training succeed
693 05:23:57.502154 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 05:23:57.549758 Check phy result
695 05:23:57.550333 INFO : End of initialization
696 05:23:57.571509 INFO : End of 2D read delay Voltage center optimization
697 05:23:57.591731 INFO : End of 2D read delay Voltage center optimization
698 05:23:57.643760 INFO : End of 2D write delay Voltage center optimization
699 05:23:57.693116 INFO : End of 2D write delay Voltage center optimization
700 05:23:57.698753 INFO : Training has run successfully!
701 05:23:57.699300
702 05:23:57.699729 channel==0
703 05:23:57.704384 RxClkDly_Margin_A0==88 ps 9
704 05:23:57.704893 TxDqDly_Margin_A0==98 ps 10
705 05:23:57.709972 RxClkDly_Margin_A1==88 ps 9
706 05:23:57.710479 TxDqDly_Margin_A1==88 ps 9
707 05:23:57.710909 TrainedVREFDQ_A0==74
708 05:23:57.715481 TrainedVREFDQ_A1==74
709 05:23:57.716033 VrefDac_Margin_A0==25
710 05:23:57.716467 DeviceVref_Margin_A0==40
711 05:23:57.721110 VrefDac_Margin_A1==25
712 05:23:57.721610 DeviceVref_Margin_A1==40
713 05:23:57.722033
714 05:23:57.722443
715 05:23:57.722848 channel==1
716 05:23:57.726697 RxClkDly_Margin_A0==98 ps 10
717 05:23:57.727195 TxDqDly_Margin_A0==88 ps 9
718 05:23:57.732346 RxClkDly_Margin_A1==98 ps 10
719 05:23:57.732860 TxDqDly_Margin_A1==88 ps 9
720 05:23:57.737944 TrainedVREFDQ_A0==76
721 05:23:57.738457 TrainedVREFDQ_A1==77
722 05:23:57.738884 VrefDac_Margin_A0==22
723 05:23:57.743574 DeviceVref_Margin_A0==38
724 05:23:57.744107 VrefDac_Margin_A1==24
725 05:23:57.749101 DeviceVref_Margin_A1==37
726 05:23:57.749604
727 05:23:57.750025 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
728 05:23:57.750435
729 05:23:57.782682 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
730 05:23:57.783245 2D training succeed
731 05:23:57.788339 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
732 05:23:57.793818 auto size-- 65535DDR cs0 size: 2048MB
733 05:23:57.794354 DDR cs1 size: 2048MB
734 05:23:57.799446 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
735 05:23:57.799967 cs0 DataBus test pass
736 05:23:57.805014 cs1 DataBus test pass
737 05:23:57.805514 cs0 AddrBus test pass
738 05:23:57.805932 cs1 AddrBus test pass
739 05:23:57.806340
740 05:23:57.810614 100bdlr_step_size ps== 420
741 05:23:57.811127 result report
742 05:23:57.816245 boot times 0Enable ddr reg access
743 05:23:57.821455 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
744 05:23:57.834974 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
745 05:23:58.408605 0.0;M3 CHK:0;cm4_sp_mode 0
746 05:23:58.409236 MVN_1=0x00000000
747 05:23:58.414107 MVN_2=0x00000000
748 05:23:58.419851 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
749 05:23:58.420442 OPS=0x10
750 05:23:58.420840 ring efuse init
751 05:23:58.421226 chipver efuse init
752 05:23:58.425428 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
753 05:23:58.430954 [0.018960 Inits done]
754 05:23:58.431420 secure task start!
755 05:23:58.431807 high task start!
756 05:23:58.435580 low task start!
757 05:23:58.436101 run into bl31
758 05:23:58.442182 NOTICE: BL31: v1.3(release):4fc40b1
759 05:23:58.450041 NOTICE: BL31: Built : 15:58:17, May 22 2019
760 05:23:58.450385 NOTICE: BL31: G12A normal boot!
761 05:23:58.475380 NOTICE: BL31: BL33 decompress pass
762 05:23:58.481037 ERROR: Error initializing runtime service opteed_fast
763 05:23:59.714028
764 05:23:59.714668
765 05:23:59.722350 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
766 05:23:59.722847
767 05:23:59.723269 Model: Libre Computer AML-A311D-CC Alta
768 05:23:59.930857 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
769 05:23:59.954227 DRAM: 2 GiB (effective 3.8 GiB)
770 05:24:00.097258 Core: 408 devices, 31 uclasses, devicetree: separate
771 05:24:00.103015 WDT: Not starting watchdog@f0d0
772 05:24:00.135319 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
773 05:24:00.147694 Loading Environment from FAT... Card did not respond to voltage select! : -110
774 05:24:00.152701 ** Bad device specification mmc 0 **
775 05:24:00.163040 Card did not respond to voltage select! : -110
776 05:24:00.170679 ** Bad device specification mmc 0 **
777 05:24:00.171149 Couldn't find partition mmc 0
778 05:24:00.179031 Card did not respond to voltage select! : -110
779 05:24:00.184531 ** Bad device specification mmc 0 **
780 05:24:00.184996 Couldn't find partition mmc 0
781 05:24:00.189601 Error: could not access storage.
782 05:24:00.532186 Net: eth0: ethernet@ff3f0000
783 05:24:00.532821 starting USB...
784 05:24:00.784018 Bus usb@ff500000: Register 3000140 NbrPorts 3
785 05:24:00.784627 Starting the controller
786 05:24:00.790866 USB XHCI 1.10
787 05:24:02.952870 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
788 05:24:02.953489 bl2_stage_init 0x01
789 05:24:02.953909 bl2_stage_init 0x81
790 05:24:02.958487 hw id: 0x0000 - pwm id 0x01
791 05:24:02.958958 bl2_stage_init 0xc1
792 05:24:02.959374 bl2_stage_init 0x02
793 05:24:02.959779
794 05:24:02.964077 L0:00000000
795 05:24:02.964543 L1:20000703
796 05:24:02.964952 L2:00008067
797 05:24:02.965352 L3:14000000
798 05:24:02.969608 B2:00402000
799 05:24:02.970069 B1:e0f83180
800 05:24:02.970473
801 05:24:02.970873 TE: 58124
802 05:24:02.971271
803 05:24:02.975249 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
804 05:24:02.975711
805 05:24:02.976167 Board ID = 1
806 05:24:02.980848 Set A53 clk to 24M
807 05:24:02.981306 Set A73 clk to 24M
808 05:24:02.981713 Set clk81 to 24M
809 05:24:02.986428 A53 clk: 1200 MHz
810 05:24:02.986891 A73 clk: 1200 MHz
811 05:24:02.987297 CLK81: 166.6M
812 05:24:02.987697 smccc: 00012a92
813 05:24:02.992162 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
814 05:24:02.997637 board id: 1
815 05:24:03.003582 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
816 05:24:03.014134 fw parse done
817 05:24:03.020209 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
818 05:24:03.062674 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
819 05:24:03.073551 PIEI prepare done
820 05:24:03.074036 fastboot data load
821 05:24:03.074452 fastboot data verify
822 05:24:03.079119 verify result: 266
823 05:24:03.084703 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
824 05:24:03.085163 LPDDR4 probe
825 05:24:03.085573 ddr clk to 1584MHz
826 05:24:03.092809 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
827 05:24:03.129970
828 05:24:03.130451 dmc_version 0001
829 05:24:03.136747 Check phy result
830 05:24:03.142541 INFO : End of CA training
831 05:24:03.142994 INFO : End of initialization
832 05:24:03.148096 INFO : Training has run successfully!
833 05:24:03.148555 Check phy result
834 05:24:03.153687 INFO : End of initialization
835 05:24:03.154136 INFO : End of read enable training
836 05:24:03.159294 INFO : End of fine write leveling
837 05:24:03.164907 INFO : End of Write leveling coarse delay
838 05:24:03.165360 INFO : Training has run successfully!
839 05:24:03.165766 Check phy result
840 05:24:03.170546 INFO : End of initialization
841 05:24:03.170997 INFO : End of read dq deskew training
842 05:24:03.176102 INFO : End of MPR read delay center optimization
843 05:24:03.181725 INFO : End of write delay center optimization
844 05:24:03.187299 INFO : End of read delay center optimization
845 05:24:03.187761 INFO : End of max read latency training
846 05:24:03.192924 INFO : Training has run successfully!
847 05:24:03.193383 1D training succeed
848 05:24:03.202059 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 05:24:03.249662 Check phy result
850 05:24:03.250133 INFO : End of initialization
851 05:24:03.272278 INFO : End of 2D read delay Voltage center optimization
852 05:24:03.292500 INFO : End of 2D read delay Voltage center optimization
853 05:24:03.344610 INFO : End of 2D write delay Voltage center optimization
854 05:24:03.393951 INFO : End of 2D write delay Voltage center optimization
855 05:24:03.399464 INFO : Training has run successfully!
856 05:24:03.399926
857 05:24:03.400504 channel==0
858 05:24:03.405075 RxClkDly_Margin_A0==88 ps 9
859 05:24:03.405535 TxDqDly_Margin_A0==108 ps 11
860 05:24:03.410692 RxClkDly_Margin_A1==88 ps 9
861 05:24:03.411164 TxDqDly_Margin_A1==98 ps 10
862 05:24:03.411589 TrainedVREFDQ_A0==74
863 05:24:03.416399 TrainedVREFDQ_A1==74
864 05:24:03.416924 VrefDac_Margin_A0==25
865 05:24:03.421932 DeviceVref_Margin_A0==40
866 05:24:03.422426 VrefDac_Margin_A1==24
867 05:24:03.422820 DeviceVref_Margin_A1==40
868 05:24:03.423207
869 05:24:03.423595
870 05:24:03.427483 channel==1
871 05:24:03.427929 RxClkDly_Margin_A0==98 ps 10
872 05:24:03.428354 TxDqDly_Margin_A0==98 ps 10
873 05:24:03.433082 RxClkDly_Margin_A1==88 ps 9
874 05:24:03.433526 TxDqDly_Margin_A1==88 ps 9
875 05:24:03.438713 TrainedVREFDQ_A0==77
876 05:24:03.439161 TrainedVREFDQ_A1==77
877 05:24:03.439551 VrefDac_Margin_A0==22
878 05:24:03.444264 DeviceVref_Margin_A0==37
879 05:24:03.444706 VrefDac_Margin_A1==24
880 05:24:03.449859 DeviceVref_Margin_A1==37
881 05:24:03.450301
882 05:24:03.450695 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
883 05:24:03.455441
884 05:24:03.483445 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
885 05:24:03.483929 2D training succeed
886 05:24:03.489068 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
887 05:24:03.494719 auto size-- 65535DDR cs0 size: 2048MB
888 05:24:03.495167 DDR cs1 size: 2048MB
889 05:24:03.500276 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
890 05:24:03.500750 cs0 DataBus test pass
891 05:24:03.505873 cs1 DataBus test pass
892 05:24:03.506332 cs0 AddrBus test pass
893 05:24:03.506720 cs1 AddrBus test pass
894 05:24:03.507101
895 05:24:03.511470 100bdlr_step_size ps== 420
896 05:24:03.511931 result report
897 05:24:03.517072 boot times 0Enable ddr reg access
898 05:24:03.522589 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
899 05:24:03.536040 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
900 05:24:04.109759 0.0;M3 CHK:0;cm4_sp_mode 0
901 05:24:04.110382 MVN_1=0x00000000
902 05:24:04.115207 MVN_2=0x00000000
903 05:24:04.120961 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
904 05:24:04.121426 OPS=0x10
905 05:24:04.121840 ring efuse init
906 05:24:04.122241 chipver efuse init
907 05:24:04.126601 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
908 05:24:04.132184 [0.018961 Inits done]
909 05:24:04.132641 secure task start!
910 05:24:04.133049 high task start!
911 05:24:04.136728 low task start!
912 05:24:04.137182 run into bl31
913 05:24:04.143413 NOTICE: BL31: v1.3(release):4fc40b1
914 05:24:04.151219 NOTICE: BL31: Built : 15:58:17, May 22 2019
915 05:24:04.151680 NOTICE: BL31: G12A normal boot!
916 05:24:04.177057 NOTICE: BL31: BL33 decompress pass
917 05:24:04.182745 ERROR: Error initializing runtime service opteed_fast
918 05:24:05.415521
919 05:24:05.415951
920 05:24:05.423918 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
921 05:24:05.424325
922 05:24:05.424633 Model: Libre Computer AML-A311D-CC Alta
923 05:24:05.632416 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
924 05:24:05.655723 DRAM: 2 GiB (effective 3.8 GiB)
925 05:24:05.798685 Core: 408 devices, 31 uclasses, devicetree: separate
926 05:24:05.804560 WDT: Not starting watchdog@f0d0
927 05:24:05.836913 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
928 05:24:05.849268 Loading Environment from FAT... Card did not respond to voltage select! : -110
929 05:24:05.854279 ** Bad device specification mmc 0 **
930 05:24:05.864588 Card did not respond to voltage select! : -110
931 05:24:05.872243 ** Bad device specification mmc 0 **
932 05:24:05.872510 Couldn't find partition mmc 0
933 05:24:05.880606 Card did not respond to voltage select! : -110
934 05:24:05.886138 ** Bad device specification mmc 0 **
935 05:24:05.886528 Couldn't find partition mmc 0
936 05:24:05.891179 Error: could not access storage.
937 05:24:06.233753 Net: eth0: ethernet@ff3f0000
938 05:24:06.234320 starting USB...
939 05:24:06.485628 Bus usb@ff500000: Register 3000140 NbrPorts 3
940 05:24:06.486237 Starting the controller
941 05:24:06.492521 USB XHCI 1.10
942 05:24:08.352697 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
943 05:24:08.353131 bl2_stage_init 0x01
944 05:24:08.353351 bl2_stage_init 0x81
945 05:24:08.358051 hw id: 0x0000 - pwm id 0x01
946 05:24:08.358440 bl2_stage_init 0xc1
947 05:24:08.358758 bl2_stage_init 0x02
948 05:24:08.359067
949 05:24:08.364288 L0:00000000
950 05:24:08.364816 L1:20000703
951 05:24:08.365247 L2:00008067
952 05:24:08.365667 L3:14000000
953 05:24:08.366712 B2:00402000
954 05:24:08.367161 B1:e0f83180
955 05:24:08.367570
956 05:24:08.367976 TE: 58167
957 05:24:08.368454
958 05:24:08.377721 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
959 05:24:08.378227
960 05:24:08.378658 Board ID = 1
961 05:24:08.379073 Set A53 clk to 24M
962 05:24:08.379402 Set A73 clk to 24M
963 05:24:08.383425 Set clk81 to 24M
964 05:24:08.383903 A53 clk: 1200 MHz
965 05:24:08.384372 A73 clk: 1200 MHz
966 05:24:08.386933 CLK81: 166.6M
967 05:24:08.387395 smccc: 00012abd
968 05:24:08.392644 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
969 05:24:08.398018 board id: 1
970 05:24:08.403247 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
971 05:24:08.415133 fw parse done
972 05:24:08.419758 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
973 05:24:08.462416 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
974 05:24:08.473447 PIEI prepare done
975 05:24:08.473974 fastboot data load
976 05:24:08.474370 fastboot data verify
977 05:24:08.478913 verify result: 266
978 05:24:08.484541 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
979 05:24:08.484989 LPDDR4 probe
980 05:24:08.485381 ddr clk to 1584MHz
981 05:24:08.492578 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
982 05:24:08.529860
983 05:24:08.530284 dmc_version 0001
984 05:24:08.536556 Check phy result
985 05:24:08.542723 INFO : End of CA training
986 05:24:08.543078 INFO : End of initialization
987 05:24:08.548071 INFO : Training has run successfully!
988 05:24:08.548412 Check phy result
989 05:24:08.553595 INFO : End of initialization
990 05:24:08.553936 INFO : End of read enable training
991 05:24:08.556862 INFO : End of fine write leveling
992 05:24:08.562409 INFO : End of Write leveling coarse delay
993 05:24:08.568068 INFO : Training has run successfully!
994 05:24:08.568427 Check phy result
995 05:24:08.568648 INFO : End of initialization
996 05:24:08.573592 INFO : End of read dq deskew training
997 05:24:08.579147 INFO : End of MPR read delay center optimization
998 05:24:08.579579 INFO : End of write delay center optimization
999 05:24:08.584776 INFO : End of read delay center optimization
1000 05:24:08.590413 INFO : End of max read latency training
1001 05:24:08.590720 INFO : Training has run successfully!
1002 05:24:08.595906 1D training succeed
1003 05:24:08.601962 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 05:24:08.649526 Check phy result
1005 05:24:08.649861 INFO : End of initialization
1006 05:24:08.671061 INFO : End of 2D read delay Voltage center optimization
1007 05:24:08.691208 INFO : End of 2D read delay Voltage center optimization
1008 05:24:08.743361 INFO : End of 2D write delay Voltage center optimization
1009 05:24:08.792519 INFO : End of 2D write delay Voltage center optimization
1010 05:24:08.797912 INFO : Training has run successfully!
1011 05:24:08.798233
1012 05:24:08.798458 channel==0
1013 05:24:08.803502 RxClkDly_Margin_A0==88 ps 9
1014 05:24:08.803947 TxDqDly_Margin_A0==98 ps 10
1015 05:24:08.809247 RxClkDly_Margin_A1==78 ps 8
1016 05:24:08.809792 TxDqDly_Margin_A1==98 ps 10
1017 05:24:08.810268 TrainedVREFDQ_A0==74
1018 05:24:08.814831 TrainedVREFDQ_A1==75
1019 05:24:08.815338 VrefDac_Margin_A0==25
1020 05:24:08.815803 DeviceVref_Margin_A0==40
1021 05:24:08.820463 VrefDac_Margin_A1==25
1022 05:24:08.820966 DeviceVref_Margin_A1==39
1023 05:24:08.821427
1024 05:24:08.821878
1025 05:24:08.826037 channel==1
1026 05:24:08.826546 RxClkDly_Margin_A0==98 ps 10
1027 05:24:08.827004 TxDqDly_Margin_A0==98 ps 10
1028 05:24:08.831593 RxClkDly_Margin_A1==88 ps 9
1029 05:24:08.832122 TxDqDly_Margin_A1==88 ps 9
1030 05:24:08.837233 TrainedVREFDQ_A0==77
1031 05:24:08.837735 TrainedVREFDQ_A1==77
1032 05:24:08.838195 VrefDac_Margin_A0==22
1033 05:24:08.842726 DeviceVref_Margin_A0==37
1034 05:24:08.843221 VrefDac_Margin_A1==24
1035 05:24:08.848384 DeviceVref_Margin_A1==37
1036 05:24:08.848882
1037 05:24:08.849339 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1038 05:24:08.849787
1039 05:24:08.881920 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1040 05:24:08.882452 2D training succeed
1041 05:24:08.887537 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1042 05:24:08.893162 auto size-- 65535DDR cs0 size: 2048MB
1043 05:24:08.893670 DDR cs1 size: 2048MB
1044 05:24:08.898725 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1045 05:24:08.899215 cs0 DataBus test pass
1046 05:24:08.904328 cs1 DataBus test pass
1047 05:24:08.904826 cs0 AddrBus test pass
1048 05:24:08.905282 cs1 AddrBus test pass
1049 05:24:08.905729
1050 05:24:08.909934 100bdlr_step_size ps== 420
1051 05:24:08.910438 result report
1052 05:24:08.915539 boot times 0Enable ddr reg access
1053 05:24:08.920911 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1054 05:24:08.934414 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1055 05:24:09.506477 0.0;M3 CHK:0;cm4_sp_mode 0
1056 05:24:09.507159 MVN_1=0x00000000
1057 05:24:09.511810 MVN_2=0x00000000
1058 05:24:09.517566 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1059 05:24:09.518090 OPS=0x10
1060 05:24:09.518557 ring efuse init
1061 05:24:09.519010 chipver efuse init
1062 05:24:09.523141 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1063 05:24:09.528761 [0.018961 Inits done]
1064 05:24:09.529273 secure task start!
1065 05:24:09.529734 high task start!
1066 05:24:09.533384 low task start!
1067 05:24:09.533896 run into bl31
1068 05:24:09.540010 NOTICE: BL31: v1.3(release):4fc40b1
1069 05:24:09.547859 NOTICE: BL31: Built : 15:58:17, May 22 2019
1070 05:24:09.548407 NOTICE: BL31: G12A normal boot!
1071 05:24:09.573217 NOTICE: BL31: BL33 decompress pass
1072 05:24:09.578835 ERROR: Error initializing runtime service opteed_fast
1073 05:24:10.811872
1074 05:24:10.812567
1075 05:24:10.820083 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1076 05:24:10.820590
1077 05:24:10.821049 Model: Libre Computer AML-A311D-CC Alta
1078 05:24:11.028681 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1079 05:24:11.051918 DRAM: 2 GiB (effective 3.8 GiB)
1080 05:24:11.194938 Core: 408 devices, 31 uclasses, devicetree: separate
1081 05:24:11.200794 WDT: Not starting watchdog@f0d0
1082 05:24:11.232986 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1083 05:24:11.245529 Loading Environment from FAT... Card did not respond to voltage select! : -110
1084 05:24:11.250456 ** Bad device specification mmc 0 **
1085 05:24:11.260843 Card did not respond to voltage select! : -110
1086 05:24:11.268466 ** Bad device specification mmc 0 **
1087 05:24:11.268954 Couldn't find partition mmc 0
1088 05:24:11.276781 Card did not respond to voltage select! : -110
1089 05:24:11.282299 ** Bad device specification mmc 0 **
1090 05:24:11.282779 Couldn't find partition mmc 0
1091 05:24:11.287354 Error: could not access storage.
1092 05:24:11.629844 Net: eth0: ethernet@ff3f0000
1093 05:24:11.630484 starting USB...
1094 05:24:11.881742 Bus usb@ff500000: Register 3000140 NbrPorts 3
1095 05:24:11.882286 Starting the controller
1096 05:24:11.888623 USB XHCI 1.10
1097 05:24:13.443002 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1098 05:24:13.451203 scanning usb for storage devices... 0 Storage Device(s) found
1100 05:24:13.502975 Hit any key to stop autoboot: 1
1101 05:24:13.503880 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1102 05:24:13.504535 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1103 05:24:13.505036 Setting prompt string to ['=>']
1104 05:24:13.505549 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1105 05:24:13.518670 0
1106 05:24:13.519636 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1107 05:24:13.520211 Sending with 10 millisecond of delay
1109 05:24:14.655092 => setenv autoload no
1110 05:24:14.665939 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1111 05:24:14.671213 setenv autoload no
1112 05:24:14.672022 Sending with 10 millisecond of delay
1114 05:24:16.469264 => setenv initrd_high 0xffffffff
1115 05:24:16.480117 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1116 05:24:16.481043 setenv initrd_high 0xffffffff
1117 05:24:16.481803 Sending with 10 millisecond of delay
1119 05:24:18.098396 => setenv fdt_high 0xffffffff
1120 05:24:18.109244 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1121 05:24:18.110135 setenv fdt_high 0xffffffff
1122 05:24:18.110900 Sending with 10 millisecond of delay
1124 05:24:18.402827 => dhcp
1125 05:24:18.413672 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1126 05:24:18.414582 dhcp
1127 05:24:18.415072 Speed: 1000, full duplex
1128 05:24:18.415532 BOOTP broadcast 1
1129 05:24:18.424764 DHCP client bound to address 192.168.6.27 (11 ms)
1130 05:24:18.425546 Sending with 10 millisecond of delay
1132 05:24:20.102308 => setenv serverip 192.168.6.2
1133 05:24:20.113152 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1134 05:24:20.114090 setenv serverip 192.168.6.2
1135 05:24:20.114826 Sending with 10 millisecond of delay
1137 05:24:23.838571 => tftpboot 0x01080000 951358/tftp-deploy-kzcjs9zu/kernel/uImage
1138 05:24:23.849418 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1139 05:24:23.850291 tftpboot 0x01080000 951358/tftp-deploy-kzcjs9zu/kernel/uImage
1140 05:24:23.850795 Speed: 1000, full duplex
1141 05:24:23.851265 Using ethernet@ff3f0000 device
1142 05:24:23.852091 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1143 05:24:23.857649 Filename '951358/tftp-deploy-kzcjs9zu/kernel/uImage'.
1144 05:24:23.861669 Load address: 0x1080000
1145 05:24:26.693007 Loading: *################################################## 43.6 MiB
1146 05:24:26.693630 15.4 MiB/s
1147 05:24:26.694060 done
1148 05:24:26.697569 Bytes transferred = 45713984 (2b98a40 hex)
1149 05:24:26.698363 Sending with 10 millisecond of delay
1151 05:24:31.387957 => tftpboot 0x08000000 951358/tftp-deploy-kzcjs9zu/ramdisk/ramdisk.cpio.gz.uboot
1152 05:24:31.398769 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1153 05:24:31.399585 tftpboot 0x08000000 951358/tftp-deploy-kzcjs9zu/ramdisk/ramdisk.cpio.gz.uboot
1154 05:24:31.400063 Speed: 1000, full duplex
1155 05:24:31.400488 Using ethernet@ff3f0000 device
1156 05:24:31.401689 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1157 05:24:31.410126 Filename '951358/tftp-deploy-kzcjs9zu/ramdisk/ramdisk.cpio.gz.uboot'.
1158 05:24:31.410662 Load address: 0x8000000
1159 05:24:32.592366 Loading: *###################### UDP wrong checksum 000000ff 00002b62
1160 05:24:32.633931 UDP wrong checksum 000000ff 0000bc54
1161 05:24:38.006845 T ########################### UDP wrong checksum 00000005 0000ed9c
1162 05:24:43.008973 T UDP wrong checksum 00000005 0000ed9c
1163 05:24:53.010927 T T UDP wrong checksum 00000005 0000ed9c
1164 05:25:13.015007 T T T T UDP wrong checksum 00000005 0000ed9c
1165 05:25:28.019033 T T
1166 05:25:28.019477 Retry count exceeded; starting again
1168 05:25:28.020384 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1171 05:25:28.021548 end: 2.4 uboot-commands (duration 00:01:52) [common]
1173 05:25:28.022266 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1175 05:25:28.022816 end: 2 uboot-action (duration 00:01:52) [common]
1177 05:25:28.023631 Cleaning after the job
1178 05:25:28.023953 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/ramdisk
1179 05:25:28.025011 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/kernel
1180 05:25:28.047612 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/dtb
1181 05:25:28.048435 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/nfsrootfs
1182 05:25:28.416950 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/951358/tftp-deploy-kzcjs9zu/modules
1183 05:25:28.446883 start: 4.1 power-off (timeout 00:00:30) [common]
1184 05:25:28.447567 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1185 05:25:28.487013 >> OK - accepted request
1186 05:25:28.489094 Returned 0 in 0 seconds
1187 05:25:28.590075 end: 4.1 power-off (duration 00:00:00) [common]
1189 05:25:28.591164 start: 4.2 read-feedback (timeout 00:10:00) [common]
1190 05:25:28.591854 Listened to connection for namespace 'common' for up to 1s
1191 05:25:29.592750 Finalising connection for namespace 'common'
1192 05:25:29.593207 Disconnecting from shell: Finalise
1193 05:25:29.593484 =>
1194 05:25:29.694140 end: 4.2 read-feedback (duration 00:00:01) [common]
1195 05:25:29.694530 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/951358
1196 05:25:32.262262 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/951358
1197 05:25:32.262877 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.