Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 15:04:55.511772 lava-dispatcher, installed at version: 2024.01
2 15:04:55.512627 start: 0 validate
3 15:04:55.513128 Start time: 2024-11-07 15:04:55.513098+00:00 (UTC)
4 15:04:55.513688 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 15:04:55.514223 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 15:04:55.555368 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 15:04:55.555920 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-239-gba19e4550e25a%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 15:04:55.591696 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 15:04:55.592341 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-239-gba19e4550e25a%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 15:04:56.644956 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 15:04:56.645487 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 15:04:56.677013 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 15:04:56.677848 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-239-gba19e4550e25a%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 15:04:56.721263 validate duration: 1.21
16 15:04:56.722833 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 15:04:56.723443 start: 1.1 download-retry (timeout 00:10:00) [common]
18 15:04:56.724066 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 15:04:56.725076 Not decompressing ramdisk as can be used compressed.
20 15:04:56.725810 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 15:04:56.726301 saving as /var/lib/lava/dispatcher/tmp/953450/tftp-deploy-ouv51k85/ramdisk/initrd.cpio.gz
22 15:04:56.726814 total size: 4775763 (4 MB)
23 15:04:56.774401 progress 0 % (0 MB)
24 15:04:56.781539 progress 5 % (0 MB)
25 15:04:56.787964 progress 10 % (0 MB)
26 15:04:56.794391 progress 15 % (0 MB)
27 15:04:56.798574 progress 20 % (0 MB)
28 15:04:56.804632 progress 25 % (1 MB)
29 15:04:56.809590 progress 30 % (1 MB)
30 15:04:56.813293 progress 35 % (1 MB)
31 15:04:56.816587 progress 40 % (1 MB)
32 15:04:56.820055 progress 45 % (2 MB)
33 15:04:56.823288 progress 50 % (2 MB)
34 15:04:56.826947 progress 55 % (2 MB)
35 15:04:56.830364 progress 60 % (2 MB)
36 15:04:56.833625 progress 65 % (2 MB)
37 15:04:56.837323 progress 70 % (3 MB)
38 15:04:56.840651 progress 75 % (3 MB)
39 15:04:56.843851 progress 80 % (3 MB)
40 15:04:56.847148 progress 85 % (3 MB)
41 15:04:56.850661 progress 90 % (4 MB)
42 15:04:56.853690 progress 95 % (4 MB)
43 15:04:56.856700 progress 100 % (4 MB)
44 15:04:56.857379 4 MB downloaded in 0.13 s (34.88 MB/s)
45 15:04:56.857940 end: 1.1.1 http-download (duration 00:00:00) [common]
47 15:04:56.858875 end: 1.1 download-retry (duration 00:00:00) [common]
48 15:04:56.859187 start: 1.2 download-retry (timeout 00:10:00) [common]
49 15:04:56.859473 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 15:04:56.860007 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 15:04:56.860307 saving as /var/lib/lava/dispatcher/tmp/953450/tftp-deploy-ouv51k85/kernel/zImage
52 15:04:56.860534 total size: 11440640 (10 MB)
53 15:04:56.860763 No compression specified
54 15:04:56.900182 progress 0 % (0 MB)
55 15:04:56.907756 progress 5 % (0 MB)
56 15:04:56.915278 progress 10 % (1 MB)
57 15:04:56.923062 progress 15 % (1 MB)
58 15:04:56.930517 progress 20 % (2 MB)
59 15:04:56.938300 progress 25 % (2 MB)
60 15:04:56.945835 progress 30 % (3 MB)
61 15:04:56.953629 progress 35 % (3 MB)
62 15:04:56.961076 progress 40 % (4 MB)
63 15:04:56.968831 progress 45 % (4 MB)
64 15:04:56.976264 progress 50 % (5 MB)
65 15:04:56.984052 progress 55 % (6 MB)
66 15:04:56.991438 progress 60 % (6 MB)
67 15:04:56.998722 progress 65 % (7 MB)
68 15:04:57.006484 progress 70 % (7 MB)
69 15:04:57.014122 progress 75 % (8 MB)
70 15:04:57.021879 progress 80 % (8 MB)
71 15:04:57.029153 progress 85 % (9 MB)
72 15:04:57.036795 progress 90 % (9 MB)
73 15:04:57.043929 progress 95 % (10 MB)
74 15:04:57.050945 progress 100 % (10 MB)
75 15:04:57.051496 10 MB downloaded in 0.19 s (57.14 MB/s)
76 15:04:57.052020 end: 1.2.1 http-download (duration 00:00:00) [common]
78 15:04:57.052890 end: 1.2 download-retry (duration 00:00:00) [common]
79 15:04:57.053190 start: 1.3 download-retry (timeout 00:10:00) [common]
80 15:04:57.053495 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 15:04:57.054027 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 15:04:57.054324 saving as /var/lib/lava/dispatcher/tmp/953450/tftp-deploy-ouv51k85/dtb/am335x-boneblack.dtb
83 15:04:57.054545 total size: 70568 (0 MB)
84 15:04:57.054767 No compression specified
85 15:04:57.091100 progress 46 % (0 MB)
86 15:04:57.091960 progress 92 % (0 MB)
87 15:04:57.092632 progress 100 % (0 MB)
88 15:04:57.093012 0 MB downloaded in 0.04 s (1.75 MB/s)
89 15:04:57.093482 end: 1.3.1 http-download (duration 00:00:00) [common]
91 15:04:57.094378 end: 1.3 download-retry (duration 00:00:00) [common]
92 15:04:57.094661 start: 1.4 download-retry (timeout 00:10:00) [common]
93 15:04:57.094950 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 15:04:57.095432 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 15:04:57.095681 saving as /var/lib/lava/dispatcher/tmp/953450/tftp-deploy-ouv51k85/nfsrootfs/full.rootfs.tar
96 15:04:57.095910 total size: 117747780 (112 MB)
97 15:04:57.096176 Using unxz to decompress xz
98 15:04:57.139543 progress 0 % (0 MB)
99 15:04:57.863174 progress 5 % (5 MB)
100 15:04:58.630771 progress 10 % (11 MB)
101 15:04:59.415302 progress 15 % (16 MB)
102 15:05:00.142901 progress 20 % (22 MB)
103 15:05:00.718832 progress 25 % (28 MB)
104 15:05:01.525178 progress 30 % (33 MB)
105 15:05:02.344865 progress 35 % (39 MB)
106 15:05:02.679116 progress 40 % (44 MB)
107 15:05:03.031874 progress 45 % (50 MB)
108 15:05:03.690396 progress 50 % (56 MB)
109 15:05:04.496539 progress 55 % (61 MB)
110 15:05:05.245160 progress 60 % (67 MB)
111 15:05:05.965825 progress 65 % (73 MB)
112 15:05:06.733612 progress 70 % (78 MB)
113 15:05:07.503118 progress 75 % (84 MB)
114 15:05:08.232681 progress 80 % (89 MB)
115 15:05:08.937503 progress 85 % (95 MB)
116 15:05:09.720775 progress 90 % (101 MB)
117 15:05:10.480723 progress 95 % (106 MB)
118 15:05:11.320030 progress 100 % (112 MB)
119 15:05:11.332414 112 MB downloaded in 14.24 s (7.89 MB/s)
120 15:05:11.333555 end: 1.4.1 http-download (duration 00:00:14) [common]
122 15:05:11.335645 end: 1.4 download-retry (duration 00:00:14) [common]
123 15:05:11.336370 start: 1.5 download-retry (timeout 00:09:45) [common]
124 15:05:11.337039 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 15:05:11.338054 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 15:05:11.338647 saving as /var/lib/lava/dispatcher/tmp/953450/tftp-deploy-ouv51k85/modules/modules.tar
127 15:05:11.339169 total size: 6607640 (6 MB)
128 15:05:11.339702 Using unxz to decompress xz
129 15:05:11.379458 progress 0 % (0 MB)
130 15:05:11.416193 progress 5 % (0 MB)
131 15:05:11.459910 progress 10 % (0 MB)
132 15:05:11.503923 progress 15 % (0 MB)
133 15:05:11.548594 progress 20 % (1 MB)
134 15:05:11.596027 progress 25 % (1 MB)
135 15:05:11.640125 progress 30 % (1 MB)
136 15:05:11.682889 progress 35 % (2 MB)
137 15:05:11.726597 progress 40 % (2 MB)
138 15:05:11.769958 progress 45 % (2 MB)
139 15:05:11.813498 progress 50 % (3 MB)
140 15:05:11.856739 progress 55 % (3 MB)
141 15:05:11.902118 progress 60 % (3 MB)
142 15:05:11.949165 progress 65 % (4 MB)
143 15:05:11.992492 progress 70 % (4 MB)
144 15:05:12.038887 progress 75 % (4 MB)
145 15:05:12.081482 progress 80 % (5 MB)
146 15:05:12.124210 progress 85 % (5 MB)
147 15:05:12.167322 progress 90 % (5 MB)
148 15:05:12.210591 progress 95 % (6 MB)
149 15:05:12.254401 progress 100 % (6 MB)
150 15:05:12.267358 6 MB downloaded in 0.93 s (6.79 MB/s)
151 15:05:12.268277 end: 1.5.1 http-download (duration 00:00:01) [common]
153 15:05:12.269879 end: 1.5 download-retry (duration 00:00:01) [common]
154 15:05:12.270400 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 15:05:12.270915 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 15:05:29.117506 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/953450/extract-nfsrootfs-fcatw78g
157 15:05:29.118109 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 15:05:29.118399 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 15:05:29.119185 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22
160 15:05:29.119643 makedir: /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin
161 15:05:29.119974 makedir: /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/tests
162 15:05:29.120328 makedir: /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/results
163 15:05:29.120666 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-add-keys
164 15:05:29.121194 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-add-sources
165 15:05:29.121701 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-background-process-start
166 15:05:29.122212 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-background-process-stop
167 15:05:29.122729 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-common-functions
168 15:05:29.123253 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-echo-ipv4
169 15:05:29.123803 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-install-packages
170 15:05:29.124323 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-installed-packages
171 15:05:29.124806 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-os-build
172 15:05:29.125279 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-probe-channel
173 15:05:29.125756 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-probe-ip
174 15:05:29.126300 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-target-ip
175 15:05:29.126890 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-target-mac
176 15:05:29.127385 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-target-storage
177 15:05:29.127882 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-test-case
178 15:05:29.128425 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-test-event
179 15:05:29.128914 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-test-feedback
180 15:05:29.129406 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-test-raise
181 15:05:29.129888 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-test-reference
182 15:05:29.130369 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-test-runner
183 15:05:29.130857 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-test-set
184 15:05:29.131374 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-test-shell
185 15:05:29.131924 Updating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-add-keys (debian)
186 15:05:29.132513 Updating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-add-sources (debian)
187 15:05:29.133024 Updating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-install-packages (debian)
188 15:05:29.133530 Updating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-installed-packages (debian)
189 15:05:29.134029 Updating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/bin/lava-os-build (debian)
190 15:05:29.134464 Creating /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/environment
191 15:05:29.134849 LAVA metadata
192 15:05:29.135117 - LAVA_JOB_ID=953450
193 15:05:29.135336 - LAVA_DISPATCHER_IP=192.168.6.2
194 15:05:29.135717 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 15:05:29.136738 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 15:05:29.137071 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 15:05:29.137281 skipped lava-vland-overlay
198 15:05:29.137522 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 15:05:29.137777 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 15:05:29.137997 skipped lava-multinode-overlay
201 15:05:29.138239 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 15:05:29.138491 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 15:05:29.138739 Loading test definitions
204 15:05:29.139017 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 15:05:29.139238 Using /lava-953450 at stage 0
206 15:05:29.140366 uuid=953450_1.6.2.4.1 testdef=None
207 15:05:29.140684 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 15:05:29.140951 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 15:05:29.142596 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 15:05:29.143401 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 15:05:29.145418 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 15:05:29.146264 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 15:05:29.148153 runner path: /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/0/tests/0_timesync-off test_uuid 953450_1.6.2.4.1
216 15:05:29.148746 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 15:05:29.149575 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 15:05:29.149806 Using /lava-953450 at stage 0
220 15:05:29.150171 Fetching tests from https://github.com/kernelci/test-definitions.git
221 15:05:29.150467 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/0/tests/1_kselftest-dt'
222 15:05:32.570901 Running '/usr/bin/git checkout kernelci.org
223 15:05:33.007879 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 15:05:33.009386 uuid=953450_1.6.2.4.5 testdef=None
225 15:05:33.009764 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 15:05:33.010556 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 15:05:33.013728 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 15:05:33.014625 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 15:05:33.019470 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 15:05:33.020978 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 15:05:33.026714 runner path: /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/0/tests/1_kselftest-dt test_uuid 953450_1.6.2.4.5
235 15:05:33.027158 BOARD='beaglebone-black'
236 15:05:33.027390 BRANCH='broonie-sound'
237 15:05:33.027610 SKIPFILE='/dev/null'
238 15:05:33.027844 SKIP_INSTALL='True'
239 15:05:33.028098 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 15:05:33.028330 TST_CASENAME=''
241 15:05:33.028535 TST_CMDFILES='dt'
242 15:05:33.029256 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 15:05:33.030118 Creating lava-test-runner.conf files
245 15:05:33.030329 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/953450/lava-overlay-dm2qqv22/lava-953450/0 for stage 0
246 15:05:33.030728 - 0_timesync-off
247 15:05:33.031017 - 1_kselftest-dt
248 15:05:33.031392 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 15:05:33.031702 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 15:05:56.730679 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 15:05:56.731140 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 15:05:56.731408 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 15:05:56.731681 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 15:05:56.731950 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 15:05:57.101072 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 15:05:57.101822 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 15:05:57.102098 extracting modules file /var/lib/lava/dispatcher/tmp/953450/tftp-deploy-ouv51k85/modules/modules.tar to /var/lib/lava/dispatcher/tmp/953450/extract-nfsrootfs-fcatw78g
258 15:05:57.975430 extracting modules file /var/lib/lava/dispatcher/tmp/953450/tftp-deploy-ouv51k85/modules/modules.tar to /var/lib/lava/dispatcher/tmp/953450/extract-overlay-ramdisk-fi6ub813/ramdisk
259 15:05:58.885045 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 15:05:58.885531 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 15:05:58.885829 [common] Applying overlay to NFS
262 15:05:58.886060 [common] Applying overlay /var/lib/lava/dispatcher/tmp/953450/compress-overlay-qf8389ak/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/953450/extract-nfsrootfs-fcatw78g
263 15:06:01.648143 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 15:06:01.648618 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 15:06:01.648921 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 15:06:01.649218 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 15:06:01.649493 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 15:06:01.649770 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 15:06:01.650040 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 15:06:01.650311 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 15:06:01.650573 Building ramdisk /var/lib/lava/dispatcher/tmp/953450/extract-overlay-ramdisk-fi6ub813/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/953450/extract-overlay-ramdisk-fi6ub813/ramdisk
272 15:06:02.682429 >> 74896 blocks
273 15:06:07.244836 Adding RAMdisk u-boot header.
274 15:06:07.245603 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/953450/extract-overlay-ramdisk-fi6ub813/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/953450/extract-overlay-ramdisk-fi6ub813/ramdisk.cpio.gz.uboot
275 15:06:07.404367 output: Image Name:
276 15:06:07.404764 output: Created: Thu Nov 7 15:06:07 2024
277 15:06:07.404977 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 15:06:07.405184 output: Data Size: 14788941 Bytes = 14442.33 KiB = 14.10 MiB
279 15:06:07.405389 output: Load Address: 00000000
280 15:06:07.405589 output: Entry Point: 00000000
281 15:06:07.405789 output:
282 15:06:07.406411 rename /var/lib/lava/dispatcher/tmp/953450/extract-overlay-ramdisk-fi6ub813/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/953450/tftp-deploy-ouv51k85/ramdisk/ramdisk.cpio.gz.uboot
283 15:06:07.407249 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 15:06:07.407861 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 15:06:07.408549 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 15:06:07.409049 No LXC device requested
287 15:06:07.409603 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 15:06:07.410169 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 15:06:07.410723 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 15:06:07.411187 Checking files for TFTP limit of 4294967296 bytes.
291 15:06:07.414285 end: 1 tftp-deploy (duration 00:01:11) [common]
292 15:06:07.414944 start: 2 uboot-action (timeout 00:05:00) [common]
293 15:06:07.415525 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 15:06:07.416120 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 15:06:07.416684 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 15:06:07.417515 substitutions:
297 15:06:07.417979 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 15:06:07.418430 - {DTB_ADDR}: 0x88000000
299 15:06:07.418877 - {DTB}: 953450/tftp-deploy-ouv51k85/dtb/am335x-boneblack.dtb
300 15:06:07.419318 - {INITRD}: 953450/tftp-deploy-ouv51k85/ramdisk/ramdisk.cpio.gz.uboot
301 15:06:07.419767 - {KERNEL_ADDR}: 0x82000000
302 15:06:07.420253 - {KERNEL}: 953450/tftp-deploy-ouv51k85/kernel/zImage
303 15:06:07.420695 - {LAVA_MAC}: None
304 15:06:07.421176 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/953450/extract-nfsrootfs-fcatw78g
305 15:06:07.421621 - {NFS_SERVER_IP}: 192.168.6.2
306 15:06:07.422056 - {PRESEED_CONFIG}: None
307 15:06:07.422493 - {PRESEED_LOCAL}: None
308 15:06:07.422930 - {RAMDISK_ADDR}: 0x83000000
309 15:06:07.423366 - {RAMDISK}: 953450/tftp-deploy-ouv51k85/ramdisk/ramdisk.cpio.gz.uboot
310 15:06:07.423805 - {ROOT_PART}: None
311 15:06:07.424283 - {ROOT}: None
312 15:06:07.424721 - {SERVER_IP}: 192.168.6.2
313 15:06:07.425154 - {TEE_ADDR}: 0x83000000
314 15:06:07.425595 - {TEE}: None
315 15:06:07.426031 Parsed boot commands:
316 15:06:07.426451 - setenv autoload no
317 15:06:07.426882 - setenv initrd_high 0xffffffff
318 15:06:07.427312 - setenv fdt_high 0xffffffff
319 15:06:07.427737 - dhcp
320 15:06:07.428196 - setenv serverip 192.168.6.2
321 15:06:07.428628 - tftp 0x82000000 953450/tftp-deploy-ouv51k85/kernel/zImage
322 15:06:07.429065 - tftp 0x83000000 953450/tftp-deploy-ouv51k85/ramdisk/ramdisk.cpio.gz.uboot
323 15:06:07.429497 - setenv initrd_size ${filesize}
324 15:06:07.429921 - tftp 0x88000000 953450/tftp-deploy-ouv51k85/dtb/am335x-boneblack.dtb
325 15:06:07.430348 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/953450/extract-nfsrootfs-fcatw78g,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 15:06:07.430793 - bootz 0x82000000 0x83000000 0x88000000
327 15:06:07.431444 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 15:06:07.433152 start: 2.3 connect-device (timeout 00:05:00) [common]
330 15:06:07.433622 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 15:06:07.449852 Setting prompt string to ['lava-test: # ']
332 15:06:07.451458 end: 2.3 connect-device (duration 00:00:00) [common]
333 15:06:07.452152 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 15:06:07.452768 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 15:06:07.453629 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 15:06:07.454930 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 15:06:07.489862 >> OK - accepted request
338 15:06:07.491960 Returned 0 in 0 seconds
339 15:06:07.593196 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 15:06:07.595003 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 15:06:07.595615 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 15:06:07.596260 Setting prompt string to ['Hit any key to stop autoboot']
344 15:06:07.596774 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 15:06:07.598469 Trying 192.168.56.21...
346 15:06:07.598992 Connected to conserv1.
347 15:06:07.599475 Escape character is '^]'.
348 15:06:07.599957
349 15:06:07.600459 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 15:06:07.600921
351 15:06:15.766164
352 15:06:15.766828 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 15:06:15.770262 Trying to boot from MMC1
354 15:06:16.343899
355 15:06:16.344627
356 15:06:16.345090 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 15:06:16.345536
358 15:06:16.349307 CPU : AM335X-GP rev 2.1
359 15:06:16.349802 Model: TI AM335x BeagleBone Black
360 15:06:16.353396 DRAM: 512 MiB
361 15:06:16.436302 Core: 160 devices, 18 uclasses, devicetree: separate
362 15:06:16.445901 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 15:06:19.816642 7[r[999;999H[6n8NAND:
364 15:06:19.817311 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 15:06:19.821805 Trying to boot from MMC1
366 15:06:20.394065
367 15:06:20.394608
368 15:06:20.394942 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 15:06:20.395286
370 15:06:20.399487 CPU : AM335X-GP rev 2.1
371 15:06:20.399863 Model: TI AM335x BeagleBone Black
372 15:06:20.403301 DRAM: 512 MiB
373 15:06:20.486750 Core: 160 devices, 18 uclasses, devicetree: separate
374 15:06:20.496291 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 15:06:22.523251 7[r[999;999H[6n8NAND:
376 15:06:22.523678 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 15:06:22.528451 Trying to boot from MMC1
378 15:06:23.103414
379 15:06:23.103823
380 15:06:23.104074 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 15:06:23.104288
382 15:06:23.108906 CPU : AM335X-GP rev 2.1
383 15:06:23.109170 Model: TI AM335x BeagleBone Black
384 15:06:23.112485 DRAM: 512 MiB
385 15:06:23.196128 Core: 160 devices, 18 uclasses, devicetree: separate
386 15:06:23.205756 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 15:06:23.710934 7[r[999;999H[6n8NAND: 0 MiB
388 15:06:23.721203 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 15:06:23.794129 Loading Environment from FAT... Unable to use mmc 0:1...
390 15:06:23.815485 <ethaddr> not set. Validating first E-fuse MAC
391 15:06:23.845830 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 15:06:23.904124 Hit any key to stop autoboot: 2
394 15:06:23.905152 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 15:06:23.905539 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 15:06:23.905820 Setting prompt string to ['=>']
397 15:06:23.906092 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 15:06:23.914174 0
399 15:06:23.914835 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 15:06:23.915124 Sending with 10 millisecond of delay
402 15:06:25.049636 => setenv autoload no
403 15:06:25.063085 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
404 15:06:25.068035 setenv autoload no
405 15:06:25.068768 Sending with 10 millisecond of delay
407 15:06:26.865858 => setenv initrd_high 0xffffffff
408 15:06:26.876413 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 15:06:26.876957 setenv initrd_high 0xffffffff
410 15:06:26.877408 Sending with 10 millisecond of delay
412 15:06:28.493981 => setenv fdt_high 0xffffffff
413 15:06:28.504810 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 15:06:28.505819 setenv fdt_high 0xffffffff
415 15:06:28.506585 Sending with 10 millisecond of delay
417 15:06:28.802676 => dhcp
418 15:06:28.813561 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 15:06:28.814500 dhcp
420 15:06:28.814986 link up on port 0, speed 100, full duplex
421 15:06:28.815457 BOOTP broadcast 1
422 15:06:28.851568 DHCP client bound to address 192.168.6.12 (32 ms)
423 15:06:28.852472 Sending with 10 millisecond of delay
425 15:06:30.538069 => setenv serverip 192.168.6.2
426 15:06:30.548923 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
427 15:06:30.549921 setenv serverip 192.168.6.2
428 15:06:30.550680 Sending with 10 millisecond of delay
430 15:06:34.035912 => tftp 0x82000000 953450/tftp-deploy-ouv51k85/kernel/zImage
431 15:06:34.046804 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
432 15:06:34.047670 tftp 0x82000000 953450/tftp-deploy-ouv51k85/kernel/zImage
433 15:06:34.048180 link up on port 0, speed 100, full duplex
434 15:06:34.051906 Using ethernet@4a100000 device
435 15:06:34.057382 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 15:06:34.057865 Filename '953450/tftp-deploy-ouv51k85/kernel/zImage'.
437 15:06:34.064553 Load address: 0x82000000
438 15:06:36.396342 Loading: *################################################## 10.9 MiB
439 15:06:36.396990 4.7 MiB/s
440 15:06:36.397432 done
441 15:06:36.400683 Bytes transferred = 11440640 (ae9200 hex)
442 15:06:36.401614 Sending with 10 millisecond of delay
444 15:06:40.846975 => tftp 0x83000000 953450/tftp-deploy-ouv51k85/ramdisk/ramdisk.cpio.gz.uboot
445 15:06:40.857534 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 15:06:40.858062 tftp 0x83000000 953450/tftp-deploy-ouv51k85/ramdisk/ramdisk.cpio.gz.uboot
447 15:06:40.858314 link up on port 0, speed 100, full duplex
448 15:06:40.862062 Using ethernet@4a100000 device
449 15:06:40.867805 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 15:06:40.876473 Filename '953450/tftp-deploy-ouv51k85/ramdisk/ramdisk.cpio.gz.uboot'.
451 15:06:40.877078 Load address: 0x83000000
452 15:06:43.743099 Loading: *################################################## 14.1 MiB
453 15:06:43.743723 4.9 MiB/s
454 15:06:43.744264 done
455 15:06:43.747333 Bytes transferred = 14789005 (e1a98d hex)
456 15:06:43.748188 Sending with 10 millisecond of delay
458 15:06:45.605355 => setenv initrd_size ${filesize}
459 15:06:45.616152 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
460 15:06:45.616991 setenv initrd_size ${filesize}
461 15:06:45.617791 Sending with 10 millisecond of delay
463 15:06:49.762503 => tftp 0x88000000 953450/tftp-deploy-ouv51k85/dtb/am335x-boneblack.dtb
464 15:06:49.773311 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 15:06:49.774220 tftp 0x88000000 953450/tftp-deploy-ouv51k85/dtb/am335x-boneblack.dtb
466 15:06:49.774688 link up on port 0, speed 100, full duplex
467 15:06:49.778001 Using ethernet@4a100000 device
468 15:06:49.784066 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 15:06:49.791042 Filename '953450/tftp-deploy-ouv51k85/dtb/am335x-boneblack.dtb'.
470 15:06:49.791529 Load address: 0x88000000
471 15:06:49.805218 Loading: *################################################## 68.9 KiB
472 15:06:49.814987 4.2 MiB/s
473 15:06:49.815445 done
474 15:06:49.815878 Bytes transferred = 70568 (113a8 hex)
475 15:06:49.816624 Sending with 10 millisecond of delay
477 15:07:02.995353 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/953450/extract-nfsrootfs-fcatw78g,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 15:07:03.006161 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
479 15:07:03.007043 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/953450/extract-nfsrootfs-fcatw78g,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 15:07:03.007773 Sending with 10 millisecond of delay
482 15:07:05.347296 => bootz 0x82000000 0x83000000 0x88000000
483 15:07:05.357896 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 15:07:05.358296 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
485 15:07:05.358880 bootz 0x82000000 0x83000000 0x88000000
486 15:07:05.359145 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
487 15:07:05.359878 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 15:07:05.365495 Image Name:
489 15:07:05.365841 Created: 2024-11-07 15:06:07 UTC
490 15:07:05.374467 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 15:07:05.374958 Data Size: 14788941 Bytes = 14.1 MiB
492 15:07:05.382598 Load Address: 00000000
493 15:07:05.382915 Entry Point: 00000000
494 15:07:05.551251 Verifying Checksum ... OK
495 15:07:05.551700 ## Flattened Device Tree blob at 88000000
496 15:07:05.557787 Booting using the fdt blob at 0x88000000
497 15:07:05.563029 Using Device Tree in place at 88000000, end 880143a7
498 15:07:05.576360
499 15:07:05.576789 Starting kernel ...
500 15:07:05.577023
501 15:07:05.577772 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 15:07:05.578320 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
503 15:07:05.579001 Setting prompt string to ['Linux version [0-9]']
504 15:07:05.579488 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 15:07:05.580116 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 15:07:06.424477 [ 0.000000] Booting Linux on physical CPU 0x0
507 15:07:06.430509 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
508 15:07:06.431038 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 15:07:06.431334 Setting prompt string to []
510 15:07:06.431637 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 15:07:06.431914 Using line separator: #'\n'#
512 15:07:06.432193 No login prompt set.
513 15:07:06.432439 Parsing kernel messages
514 15:07:06.432662 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 15:07:06.433108 [login-action] Waiting for messages, (timeout 00:04:01)
516 15:07:06.433361 Waiting using forced prompt support (timeout 00:02:00)
517 15:07:06.447380 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j366897-arm-gcc-12-multi-v7-defconfig-vdwck) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Nov 7 14:20:38 UTC 2024
518 15:07:06.453173 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 15:07:06.458580 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 15:07:06.470283 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 15:07:06.475936 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 15:07:06.481660 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 15:07:06.482168 [ 0.000000] Memory policy: Data cache writeback
524 15:07:06.489081 [ 0.000000] efi: UEFI not found.
525 15:07:06.493045 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 15:07:06.499486 [ 0.000000] Zone ranges:
527 15:07:06.505044 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 15:07:06.510805 [ 0.000000] Normal empty
529 15:07:06.511332 [ 0.000000] HighMem empty
530 15:07:06.513917 [ 0.000000] Movable zone start for each node
531 15:07:06.519610 [ 0.000000] Early memory node ranges
532 15:07:06.525387 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 15:07:06.533511 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 15:07:06.558783 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 15:07:06.564496 [ 0.000000] AM335X ES2.1 (sgx neon)
536 15:07:06.576121 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
537 15:07:06.593702 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/953450/extract-nfsrootfs-fcatw78g,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 15:07:06.605429 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 15:07:06.610998 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 15:07:06.616720 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 15:07:06.626707 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 15:07:06.655938 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 15:07:06.661955 <6>[ 0.000000] trace event string verifier disabled
544 15:07:06.662434 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 15:07:06.667749 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 15:07:06.679165 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 15:07:06.684883 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 15:07:06.692130 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 15:07:06.706588 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 15:07:06.724244 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 15:07:06.730961 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 15:07:06.822764 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 15:07:06.831409 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 15:07:06.843913 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 15:07:06.851471 <6>[ 0.019157] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 15:07:06.861331 <6>[ 0.033951] Console: colour dummy device 80x30
557 15:07:06.867417 Matched prompt #6: WARNING:
558 15:07:06.867935 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 15:07:06.872966 <3>[ 0.038852] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 15:07:06.878585 <3>[ 0.045925] This ensures that you still see kernel messages. Please
561 15:07:06.881877 <3>[ 0.052655] update your kernel commandline.
562 15:07:06.922509 <6>[ 0.057271] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 15:07:06.928300 <6>[ 0.096168] CPU: Testing write buffer coherency: ok
564 15:07:06.934308 <6>[ 0.101536] CPU0: Spectre v2: using BPIALL workaround
565 15:07:06.934767 <6>[ 0.107004] pid_max: default: 32768 minimum: 301
566 15:07:06.945726 <6>[ 0.112196] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 15:07:06.952676 <6>[ 0.120018] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 15:07:06.959723 <6>[ 0.129374] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 15:07:06.967042 <6>[ 0.136376] Setting up static identity map for 0x80300000 - 0x803000ac
570 15:07:06.973520 <6>[ 0.146021] rcu: Hierarchical SRCU implementation.
571 15:07:06.981611 <6>[ 0.151304] rcu: Max phase no-delay instances is 1000.
572 15:07:06.990069 <6>[ 0.162416] EFI services will not be available.
573 15:07:06.995841 <6>[ 0.167699] smp: Bringing up secondary CPUs ...
574 15:07:07.001701 <6>[ 0.172748] smp: Brought up 1 node, 1 CPU
575 15:07:07.009870 <6>[ 0.177149] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 15:07:07.015897 <6>[ 0.183915] CPU: All CPU(s) started in SVC mode.
577 15:07:07.028084 <6>[ 0.189093] Memory: 406000K/522240K available (16384K kernel code, 2542K rwdata, 6784K rodata, 2048K init, 431K bss, 49048K reserved, 65536K cma-reserved, 0K highmem)
578 15:07:07.034333 <6>[ 0.205377] devtmpfs: initialized
579 15:07:07.056081 <6>[ 0.222474] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 15:07:07.067456 <6>[ 0.231063] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 15:07:07.073346 <6>[ 0.241525] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 15:07:07.083310 <6>[ 0.253874] pinctrl core: initialized pinctrl subsystem
583 15:07:07.093592 <6>[ 0.264503] DMI not present or invalid.
584 15:07:07.101771 <6>[ 0.270362] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 15:07:07.111185 <6>[ 0.279249] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 15:07:07.126330 <6>[ 0.290812] thermal_sys: Registered thermal governor 'step_wise'
587 15:07:07.126893 <6>[ 0.290977] cpuidle: using governor menu
588 15:07:07.154030 <6>[ 0.326609] No ATAGs?
589 15:07:07.160252 <6>[ 0.329255] hw-breakpoint: debug architecture 0x4 unsupported.
590 15:07:07.170647 <6>[ 0.341334] Serial: AMBA PL011 UART driver
591 15:07:07.202889 <6>[ 0.375314] iommu: Default domain type: Translated
592 15:07:07.211852 <6>[ 0.380664] iommu: DMA domain TLB invalidation policy: strict mode
593 15:07:07.239067 <5>[ 0.410930] SCSI subsystem initialized
594 15:07:07.244899 <6>[ 0.415831] usbcore: registered new interface driver usbfs
595 15:07:07.250718 <6>[ 0.421889] usbcore: registered new interface driver hub
596 15:07:07.257415 <6>[ 0.427679] usbcore: registered new device driver usb
597 15:07:07.263482 <6>[ 0.434201] pps_core: LinuxPPS API ver. 1 registered
598 15:07:07.274715 <6>[ 0.439633] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 15:07:07.281956 <6>[ 0.449320] PTP clock support registered
600 15:07:07.282480 <6>[ 0.453785] EDAC MC: Ver: 3.0.0
601 15:07:07.330698 <6>[ 0.500714] scmi_core: SCMI protocol bus registered
602 15:07:07.345788 <6>[ 0.518056] vgaarb: loaded
603 15:07:07.358377 <6>[ 0.531069] clocksource: Switched to clocksource dmtimer
604 15:07:07.395055 <6>[ 0.567246] NET: Registered PF_INET protocol family
605 15:07:07.407515 <6>[ 0.572948] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 15:07:07.413447 <6>[ 0.581767] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 15:07:07.424787 <6>[ 0.590698] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 15:07:07.430624 <6>[ 0.598960] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 15:07:07.442095 <6>[ 0.607245] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 15:07:07.448045 <6>[ 0.614972] TCP: Hash tables configured (established 4096 bind 4096)
611 15:07:07.453772 <6>[ 0.621897] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 15:07:07.459712 <6>[ 0.628909] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 15:07:07.467234 <6>[ 0.636515] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 15:07:07.558356 <6>[ 0.725319] RPC: Registered named UNIX socket transport module.
615 15:07:07.558973 <6>[ 0.731706] RPC: Registered udp transport module.
616 15:07:07.564212 <6>[ 0.736848] RPC: Registered tcp transport module.
617 15:07:07.569912 <6>[ 0.741968] RPC: Registered tcp-with-tls transport module.
618 15:07:07.582837 <6>[ 0.747877] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 15:07:07.583364 <6>[ 0.754801] PCI: CLS 0 bytes, default 64
620 15:07:07.590071 <5>[ 0.760581] Initialise system trusted keyrings
621 15:07:07.609658 <6>[ 0.779173] Trying to unpack rootfs image as initramfs...
622 15:07:07.669980 <6>[ 0.836370] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 15:07:07.674813 <6>[ 0.843917] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 15:07:07.710405 <5>[ 0.882976] NFS: Registering the id_resolver key type
625 15:07:07.716258 <5>[ 0.888575] Key type id_resolver registered
626 15:07:07.722013 <5>[ 0.893255] Key type id_legacy registered
627 15:07:07.727778 <6>[ 0.897696] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 15:07:07.737354 <6>[ 0.904898] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 15:07:07.815874 <5>[ 0.988340] Key type asymmetric registered
630 15:07:07.821690 <5>[ 0.992916] Asymmetric key parser 'x509' registered
631 15:07:07.833107 <6>[ 0.998345] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 15:07:07.833530 <6>[ 1.006263] io scheduler mq-deadline registered
633 15:07:07.838820 <6>[ 1.011196] io scheduler kyber registered
634 15:07:07.844364 <6>[ 1.015687] io scheduler bfq registered
635 15:07:07.943492 <6>[ 1.112399] ledtrig-cpu: registered to indicate activity on CPUs
636 15:07:08.478111 <6>[ 1.407762] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 15:07:08.478558 <6>[ 1.437101] msm_serial: driver initialized
638 15:07:08.478809 <6>[ 1.442118] SuperH (H)SCI(F) driver initialized
639 15:07:08.479041 <6>[ 1.447298] STMicroelectronics ASC driver initialized
640 15:07:08.479269 <6>[ 1.452984] STM32 USART driver initialized
641 15:07:08.479500 <6>[ 1.583573] brd: module loaded
642 15:07:08.479923 <6>[ 1.609023] loop: module loaded
643 15:07:08.480722 <6>[ 1.650132] CAN device driver interface
644 15:07:08.486599 <6>[ 1.655471] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 15:07:08.492344 <6>[ 1.662577] e1000e: Intel(R) PRO/1000 Network Driver
646 15:07:08.498084 <6>[ 1.667965] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 15:07:08.503834 <6>[ 1.674440] igb: Intel(R) Gigabit Ethernet Network Driver
648 15:07:08.510744 <6>[ 1.680266] igb: Copyright (c) 2007-2014 Intel Corporation.
649 15:07:08.522613 <6>[ 1.689597] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 15:07:08.528506 <6>[ 1.695754] usbcore: registered new interface driver pegasus
651 15:07:08.534180 <6>[ 1.701912] usbcore: registered new interface driver asix
652 15:07:08.540023 <6>[ 1.707763] usbcore: registered new interface driver ax88179_178a
653 15:07:08.545769 <6>[ 1.714362] usbcore: registered new interface driver cdc_ether
654 15:07:08.551566 <6>[ 1.720657] usbcore: registered new interface driver smsc75xx
655 15:07:08.557383 <6>[ 1.726892] usbcore: registered new interface driver smsc95xx
656 15:07:08.563181 <6>[ 1.733117] usbcore: registered new interface driver net1080
657 15:07:08.568941 <6>[ 1.739247] usbcore: registered new interface driver cdc_subset
658 15:07:08.574653 <6>[ 1.745657] usbcore: registered new interface driver zaurus
659 15:07:08.582241 <6>[ 1.751701] usbcore: registered new interface driver cdc_ncm
660 15:07:08.592176 <6>[ 1.761220] usbcore: registered new interface driver usb-storage
661 15:07:08.873563 <6>[ 2.044193] i2c_dev: i2c /dev entries driver
662 15:07:08.943933 <5>[ 2.108477] cpuidle: enable-method property 'ti,am3352' found operations
663 15:07:08.949762 <6>[ 2.118137] sdhci: Secure Digital Host Controller Interface driver
664 15:07:08.957327 <6>[ 2.124957] sdhci: Copyright(c) Pierre Ossman
665 15:07:08.964614 <6>[ 2.131415] Synopsys Designware Multimedia Card Interface Driver
666 15:07:08.970040 <6>[ 2.139391] sdhci-pltfm: SDHCI platform and OF driver helper
667 15:07:09.087861 <6>[ 2.253093] usbcore: registered new interface driver usbhid
668 15:07:09.088517 <6>[ 2.259139] usbhid: USB HID core driver
669 15:07:09.138348 <6>[ 2.308379] NET: Registered PF_INET6 protocol family
670 15:07:09.170195 <6>[ 2.342927] Segment Routing with IPv6
671 15:07:09.176025 <6>[ 2.347079] In-situ OAM (IOAM) with IPv6
672 15:07:09.182806 <6>[ 2.351482] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 15:07:09.190321 <6>[ 2.358853] NET: Registered PF_PACKET protocol family
674 15:07:09.196196 <6>[ 2.364417] can: controller area network core
675 15:07:09.196711 <6>[ 2.369241] NET: Registered PF_CAN protocol family
676 15:07:09.201942 <6>[ 2.374469] can: raw protocol
677 15:07:09.207719 <6>[ 2.377794] can: broadcast manager protocol
678 15:07:09.214708 <6>[ 2.382391] can: netlink gateway - max_hops=1
679 15:07:09.215203 <5>[ 2.387886] Key type dns_resolver registered
680 15:07:09.220410 <6>[ 2.392984] ThumbEE CPU extension supported.
681 15:07:09.226800 <5>[ 2.397672] Registering SWP/SWPB emulation handler
682 15:07:09.234793 <3>[ 2.403372] omap_voltage_late_init: Voltage driver support not added
683 15:07:09.422507 <5>[ 2.592515] Loading compiled-in X.509 certificates
684 15:07:09.545718 <6>[ 2.705405] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 15:07:09.552975 <6>[ 2.722167] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 15:07:09.579394 <3>[ 2.746027] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 15:07:09.789609 <3>[ 2.956131] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 15:07:09.992296 <6>[ 3.163037] OMAP GPIO hardware version 0.1
689 15:07:10.012739 <6>[ 3.181769] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 15:07:10.125091 <4>[ 3.293776] at24 2-0054: supply vcc not found, using dummy regulator
691 15:07:10.160100 <4>[ 3.328819] at24 2-0055: supply vcc not found, using dummy regulator
692 15:07:10.197914 <4>[ 3.366636] at24 2-0056: supply vcc not found, using dummy regulator
693 15:07:10.244935 <4>[ 3.413674] at24 2-0057: supply vcc not found, using dummy regulator
694 15:07:10.277560 <6>[ 3.447128] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 15:07:10.353062 <3>[ 3.518576] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 15:07:10.377607 <6>[ 3.539459] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 15:07:10.399784 <4>[ 3.565779] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 15:07:10.407542 <4>[ 3.575011] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 15:07:10.543289 <6>[ 3.712287] omap_rng 48310000.rng: Random Number Generator ver. 20
700 15:07:10.566943 <5>[ 3.738651] random: crng init done
701 15:07:10.615485 <6>[ 3.788008] Freeing initrd memory: 14444K
702 15:07:10.625237 <6>[ 3.792678] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 15:07:10.677859 <6>[ 3.844340] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 15:07:10.683576 <6>[ 3.854664] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 15:07:10.691800 <6>[ 3.862005] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 15:07:10.703266 <6>[ 3.869464] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 15:07:10.714860 <6>[ 3.877596] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 15:07:10.722383 <6>[ 3.889232] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
709 15:07:10.733298 <5>[ 3.898248] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 15:07:10.761174 <3>[ 3.928179] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 15:07:10.766972 <6>[ 3.936771] edma 49000000.dma: TI EDMA DMA engine driver
712 15:07:10.838738 <3>[ 4.005013] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 15:07:10.853447 <6>[ 4.019409] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 15:07:10.866435 <3>[ 4.036550] l3-aon-clkctrl:0000:0: failed to disable
715 15:07:10.916211 <6>[ 4.083050] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 15:07:10.921829 <6>[ 4.092519] printk: legacy console [ttyS0] enabled
717 15:07:10.927511 <6>[ 4.092519] printk: legacy console [ttyS0] enabled
718 15:07:10.935706 <6>[ 4.102855] printk: legacy bootconsole [omap8250] disabled
719 15:07:10.938997 <6>[ 4.102855] printk: legacy bootconsole [omap8250] disabled
720 15:07:10.976671 <4>[ 4.142659] tps65217-pmic: Failed to locate of_node [id: -1]
721 15:07:10.980279 <4>[ 4.150053] tps65217-bl: Failed to locate of_node [id: -1]
722 15:07:10.999160 <6>[ 4.169787] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 15:07:11.015132 <6>[ 4.176749] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 15:07:11.026930 <6>[ 4.190446] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 15:07:11.032567 <6>[ 4.202305] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 15:07:11.054744 <6>[ 4.222157] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 15:07:11.060662 <6>[ 4.231214] sdhci-omap 48060000.mmc: Got CD GPIO
728 15:07:11.068696 <4>[ 4.236391] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 15:07:11.083397 <4>[ 4.250081] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 15:07:11.089927 <4>[ 4.258740] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 15:07:11.099708 <4>[ 4.267400] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 15:07:11.173646 <6>[ 4.342058] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 15:07:11.208061 <6>[ 4.375503] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 15:07:11.228534 <6>[ 4.395091] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 15:07:11.235380 <6>[ 4.404014] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 15:07:11.279452 <6>[ 4.443008] mmc0: new high speed SDHC card at address 1234
737 15:07:11.280072 <6>[ 4.450327] mmcblk0: mmc0:1234 SA32G 29.1 GiB
738 15:07:11.286782 <6>[ 4.459498] mmcblk0: p1
739 15:07:11.316438 <6>[ 4.483451] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
740 15:07:11.324978 <6>[ 4.494744] mmc1: new high speed MMC card at address 0001
741 15:07:11.337519 <6>[ 4.508353] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
742 15:07:11.347530 <6>[ 4.517522] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
743 15:07:11.355297 <6>[ 4.525609] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
744 15:07:11.364874 <6>[ 4.533937] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
745 15:07:13.435926 <6>[ 6.602933] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 15:07:13.509391 <5>[ 6.641997] Sending DHCP requests ., OK
747 15:07:13.520589 <6>[ 6.686373] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
748 15:07:13.521132 <6>[ 6.694543] IP-Config: Complete:
749 15:07:13.531942 <6>[ 6.698085] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
750 15:07:13.537577 <6>[ 6.708605] host=192.168.6.12, domain=, nis-domain=(none)
751 15:07:13.549940 <6>[ 6.714815] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
752 15:07:13.550397 <6>[ 6.714848] nameserver0=10.255.253.1
753 15:07:13.556056 <6>[ 6.727438] clk: Disabling unused clocks
754 15:07:13.561826 <6>[ 6.732158] PM: genpd: Disabling unused power domains
755 15:07:13.581272 <6>[ 6.750646] Freeing unused kernel image (initmem) memory: 2048K
756 15:07:13.589106 <6>[ 6.760810] Run /init as init process
757 15:07:13.614422 Loading, please wait...
758 15:07:13.689631 Starting systemd-udevd version 252.22-1~deb12u1
759 15:07:16.678134 <4>[ 9.844012] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 15:07:16.916601 <4>[ 10.082482] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 15:07:17.058756 <6>[ 10.231666] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
762 15:07:17.069269 <6>[ 10.237564] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
763 15:07:17.300605 <6>[ 10.472404] hub 1-0:1.0: USB hub found
764 15:07:17.339235 <6>[ 10.509651] hub 1-0:1.0: 1 port detected
765 15:07:17.345211 <6>[ 10.516847] tda998x 0-0070: found TDA19988
766 15:07:20.284918 Begin: Loading essential drivers ... done.
767 15:07:20.290470 Begin: Running /scripts/init-premount ... done.
768 15:07:20.296085 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
769 15:07:20.311208 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
770 15:07:20.311773 Device /sys/class/net/eth0 found
771 15:07:20.312218 done.
772 15:07:20.390837 Begin: Waiting up to 180 secs for any network device to become available ... done.
773 15:07:20.461802 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
774 15:07:20.484297 IP-Config: eth0 guessed broadcast address 192.168.6.255
775 15:07:20.489973 IP-Config: eth0 complete (dhcp from 192.168.6.1):
776 15:07:20.495476 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
777 15:07:20.504284 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
778 15:07:20.510036 rootserver: 192.168.6.1 rootpath:
779 15:07:20.510338 filename :
780 15:07:20.628111 done.
781 15:07:20.636995 Begin: Running /scripts/nfs-bottom ... done.
782 15:07:20.713201 Begin: Running /scripts/init-bottom ... done.
783 15:07:22.189370 <30>[ 15.358386] systemd[1]: System time before build time, advancing clock.
784 15:07:22.343617 <30>[ 15.486482] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 15:07:22.352554 <30>[ 15.523447] systemd[1]: Detected architecture arm.
786 15:07:22.365619
787 15:07:22.366078 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 15:07:22.366494
789 15:07:22.391934 <30>[ 15.561751] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 15:07:24.536495 <30>[ 17.705228] systemd[1]: Queued start job for default target graphical.target.
791 15:07:24.553165 <30>[ 17.719769] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 15:07:24.560755 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 15:07:24.591637 <30>[ 17.757741] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 15:07:24.599075 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 15:07:24.628931 <30>[ 17.794651] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 15:07:24.636313 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 15:07:24.669376 <30>[ 17.835603] systemd[1]: Created slice user.slice - User and Session Slice.
798 15:07:24.676133 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 15:07:24.701716 <30>[ 17.863165] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 15:07:24.707784 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 15:07:24.725751 <30>[ 17.892993] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 15:07:24.733710 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 15:07:24.766700 <30>[ 17.923025] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 15:07:24.773205 <30>[ 17.943469] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 15:07:24.781769 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 15:07:24.804982 <30>[ 17.972427] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 15:07:24.813291 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 15:07:24.835666 <30>[ 18.002775] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 15:07:24.844162 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 15:07:24.865555 <30>[ 18.032911] systemd[1]: Reached target paths.target - Path Units.
811 15:07:24.870689 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 15:07:24.895186 <30>[ 18.062537] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 15:07:24.902578 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 15:07:24.925042 <30>[ 18.092412] systemd[1]: Reached target slices.target - Slice Units.
815 15:07:24.930525 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 15:07:24.955264 <30>[ 18.122645] systemd[1]: Reached target swap.target - Swaps.
817 15:07:24.959373 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 15:07:24.985612 <30>[ 18.152750] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 15:07:24.994523 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 15:07:25.016572 <30>[ 18.183647] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 15:07:25.024886 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 15:07:25.104842 <30>[ 18.267143] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 15:07:25.118127 <30>[ 18.284881] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 15:07:25.126064 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 15:07:25.148405 <30>[ 18.314737] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 15:07:25.155835 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 15:07:25.177913 <30>[ 18.345065] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 15:07:25.186087 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 15:07:25.211162 <30>[ 18.377116] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 15:07:25.216830 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 15:07:25.247611 <30>[ 18.413499] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 15:07:25.255161 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 15:07:25.282457 <30>[ 18.443673] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 15:07:25.301133 <30>[ 18.462276] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 15:07:25.349413 <30>[ 18.517466] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 15:07:25.375529 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 15:07:25.424887 <30>[ 18.592782] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 15:07:25.452658 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 15:07:25.537780 <30>[ 18.704682] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 15:07:25.564555 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 15:07:25.617345 <30>[ 18.784888] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 15:07:25.644518 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 15:07:25.695898 <30>[ 18.863808] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 15:07:25.723369 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 15:07:25.774882 <30>[ 18.943303] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 15:07:25.796748 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 15:07:25.855787 <30>[ 19.023037] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 15:07:25.885360 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 15:07:25.935408 <30>[ 19.103704] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 15:07:25.957352 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 15:07:26.014994 <30>[ 19.183310] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 15:07:26.038298 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 15:07:26.072506 <28>[ 19.234122] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 15:07:26.080986 <28>[ 19.248304] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 15:07:26.131462 <30>[ 19.300169] systemd[1]: Starting systemd-journald.service - Journal Service...
856 15:07:26.154657 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 15:07:26.232567 <30>[ 19.400633] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 15:07:26.254663 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 15:07:26.296865 <30>[ 19.465053] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 15:07:26.354036 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 15:07:26.418089 <30>[ 19.584652] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 15:07:26.464466 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 15:07:26.537535 <30>[ 19.705066] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 15:07:26.576060 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 15:07:26.632382 <30>[ 19.800795] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 15:07:26.694996 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 15:07:26.716168 <30>[ 19.884416] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 15:07:26.747242 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 15:07:26.788171 <30>[ 19.955370] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 15:07:26.824277 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 15:07:26.985914 <30>[ 20.154860] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 15:07:27.016085 <30>[ 20.183838] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 15:07:27.044989 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 15:07:27.066177 <30>[ 20.233723] systemd[1]: Started systemd-journald.service - Journal Service.
875 15:07:27.073111 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
876 15:07:27.107350 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 15:07:27.130467 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
878 15:07:27.166429 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
879 15:07:27.190684 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
880 15:07:27.226207 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
881 15:07:27.255279 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
882 15:07:27.277426 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
883 15:07:27.298231 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
884 15:07:27.334902 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
885 15:07:27.398455 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
886 15:07:27.469256 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
887 15:07:27.517103 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
888 15:07:27.564945 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
889 15:07:27.654750 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
890 15:07:27.796228 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
891 15:07:27.925981 <46>[ 21.094147] systemd-journald[163]: Received client request to flush runtime journal.
892 15:07:27.987351 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
893 15:07:28.065493 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
894 15:07:28.867380 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
895 15:07:28.957324 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
896 15:07:29.628833 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
897 15:07:29.830149 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
898 15:07:29.856573 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
899 15:07:29.874883 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
900 15:07:29.956263 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
901 15:07:29.997998 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
902 15:07:30.939311 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
903 15:07:31.015801 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
904 15:07:31.237618 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
905 15:07:31.406601 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
906 15:07:31.515017 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
907 15:07:33.412289 [[0m[0;31m* [0m] (1 of 5) Job systemd-udev-trigger.s…vice/start running (8s / no limit)
908 15:07:33.612364 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
909 15:07:33.765452 [K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
910 15:07:34.372072 <5>[ 27.540647] cfg80211: Loading compiled-in X.509 certificates for regulatory database
911 15:07:34.643448 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
912 15:07:35.891843 <5>[ 29.063616] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
913 15:07:35.904366 <5>[ 29.071731] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
914 15:07:35.910077 <4>[ 29.080541] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
915 15:07:35.917994 <6>[ 29.089640] cfg80211: failed to load regulatory.db
916 15:07:36.094954 <46>[ 29.254597] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
917 15:07:36.242181 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - N<46>[ 29.396382] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
918 15:07:36.242808 etwork Time Synchronization.
919 15:07:36.951592 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
920 15:07:45.462089 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
921 15:07:45.491139 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
922 15:07:45.516629 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
923 15:07:45.536461 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
924 15:07:45.609881 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
925 15:07:45.686128 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
926 15:07:45.757203 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
927 15:07:45.824253 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
928 15:07:45.876641 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
929 15:07:45.900511 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
930 15:07:45.941895 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
931 15:07:45.968606 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
932 15:07:46.011344 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
933 15:07:46.055096 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
934 15:07:46.081628 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
935 15:07:46.108753 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
936 15:07:46.140730 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
937 15:07:46.170619 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
938 15:07:46.201366 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
939 15:07:46.224711 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
940 15:07:46.254784 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
941 15:07:46.274772 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
942 15:07:46.301294 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
943 15:07:46.375186 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
944 15:07:46.408946 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
945 15:07:46.499188 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
946 15:07:46.578524 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
947 15:07:46.668618 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
948 15:07:46.729547 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
949 15:07:46.745333 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
950 15:07:46.938372 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
951 15:07:47.024217 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
952 15:07:47.057258 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
953 15:07:47.064527 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
954 15:07:47.095131 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
955 15:07:47.354060 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
956 15:07:47.655021 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
957 15:07:47.698385 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
958 15:07:47.728696 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
959 15:07:47.819466 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
960 15:07:47.987826 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
961 15:07:48.122308
962 15:07:48.125746 Debian GNU/Linux 12 worm-armhf login: root (automatic login)
963 15:07:48.126254
964 15:07:48.414258 Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Thu Nov 7 14:20:38 UTC 2024 armv7l
965 15:07:48.415150
966 15:07:48.419903 The programs included with the Debian GNU/Linux system are free software;
967 15:07:48.423290 the exact distribution terms for each program are described in the
968 15:07:48.428722 individual files in /usr/share/doc/*/copyright.
969 15:07:48.429293
970 15:07:48.434211 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
971 15:07:48.438940 permitted by applicable law.
972 15:07:53.097584 Unable to match end of the kernel message
974 15:07:53.098524 Setting prompt string to ['/ #']
975 15:07:53.098835 end: 2.4.4.1 login-action (duration 00:00:47) [common]
977 15:07:53.099545 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
978 15:07:53.099833 start: 2.4.5 expect-shell-connection (timeout 00:03:14) [common]
979 15:07:53.100106 Setting prompt string to ['/ #']
980 15:07:53.100321 Forcing a shell prompt, looking for ['/ #']
982 15:07:53.150876 / #
983 15:07:53.151408 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
984 15:07:53.151688 Waiting using forced prompt support (timeout 00:02:30)
985 15:07:53.156066
986 15:07:53.161661 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
987 15:07:53.162013 start: 2.4.6 export-device-env (timeout 00:03:14) [common]
988 15:07:53.162262 Sending with 10 millisecond of delay
990 15:07:58.151275 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/953450/extract-nfsrootfs-fcatw78g'
991 15:07:58.162266 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/953450/extract-nfsrootfs-fcatw78g'
992 15:07:58.163112 Sending with 10 millisecond of delay
994 15:08:00.265989 / # export NFS_SERVER_IP='192.168.6.2'
995 15:08:00.276971 export NFS_SERVER_IP='192.168.6.2'
996 15:08:00.278199 end: 2.4.6 export-device-env (duration 00:00:07) [common]
997 15:08:00.278860 end: 2.4 uboot-commands (duration 00:01:53) [common]
998 15:08:00.279502 end: 2 uboot-action (duration 00:01:53) [common]
999 15:08:00.280183 start: 3 lava-test-retry (timeout 00:06:56) [common]
1000 15:08:00.280841 start: 3.1 lava-test-shell (timeout 00:06:56) [common]
1001 15:08:00.281364 Using namespace: common
1003 15:08:00.382706 / # #
1004 15:08:00.383584 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1005 15:08:00.387125 #
1006 15:08:00.393091 Using /lava-953450
1008 15:08:00.494414 / # export SHELL=/bin/bash
1009 15:08:00.498852 export SHELL=/bin/bash
1011 15:08:00.606288 / # . /lava-953450/environment
1012 15:08:00.611723 . /lava-953450/environment
1014 15:08:00.725376 / # /lava-953450/bin/lava-test-runner /lava-953450/0
1015 15:08:00.726721 Test shell timeout: 10s (minimum of the action and connection timeout)
1016 15:08:00.730479 /lava-953450/bin/lava-test-runner /lava-953450/0
1017 15:08:01.127042 + export TESTRUN_ID=0_timesync-off
1018 15:08:01.134874 + TESTRUN_ID=0_timesync-off
1019 15:08:01.135844 + cd /lava-953450/0/tests/0_timesync-off
1020 15:08:01.136754 ++ cat uuid
1021 15:08:01.150771 + UUID=953450_1.6.2.4.1
1022 15:08:01.151714 + set +x
1023 15:08:01.159367 <LAVA_SIGNAL_STARTRUN 0_timesync-off 953450_1.6.2.4.1>
1024 15:08:01.160388 + systemctl stop systemd-timesyncd
1025 15:08:01.161565 Received signal: <STARTRUN> 0_timesync-off 953450_1.6.2.4.1
1026 15:08:01.162433 Starting test lava.0_timesync-off (953450_1.6.2.4.1)
1027 15:08:01.163441 Skipping test definition patterns.
1028 15:08:01.441103 + set +x
1029 15:08:01.441747 <LAVA_SIGNAL_ENDRUN 0_timesync-off 953450_1.6.2.4.1>
1030 15:08:01.442453 Received signal: <ENDRUN> 0_timesync-off 953450_1.6.2.4.1
1031 15:08:01.442977 Ending use of test pattern.
1032 15:08:01.443399 Ending test lava.0_timesync-off (953450_1.6.2.4.1), duration 0.28
1034 15:08:01.622496 + export TESTRUN_ID=1_kselftest-dt
1035 15:08:01.630358 + TESTRUN_ID=1_kselftest-dt
1036 15:08:01.630924 + cd /lava-953450/0/tests/1_kselftest-dt
1037 15:08:01.631393 ++ cat uuid
1038 15:08:01.647089 + UUID=953450_1.6.2.4.5
1039 15:08:01.647682 + set +x
1040 15:08:01.652668 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 953450_1.6.2.4.5>
1041 15:08:01.653214 + cd ./automated/linux/kselftest/
1042 15:08:01.653951 Received signal: <STARTRUN> 1_kselftest-dt 953450_1.6.2.4.5
1043 15:08:01.654430 Starting test lava.1_kselftest-dt (953450_1.6.2.4.5)
1044 15:08:01.654956 Skipping test definition patterns.
1045 15:08:01.682918 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1046 15:08:01.819446 INFO: install_deps skipped
1047 15:08:02.386649 --2024-11-07 15:08:02-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1048 15:08:02.411081 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1049 15:08:02.552781 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1050 15:08:02.692223 HTTP request sent, awaiting response... 200 OK
1051 15:08:02.693257 Length: 4097444 (3.9M) [application/octet-stream]
1052 15:08:02.697548 Saving to: 'kselftest_armhf.tar.gz'
1053 15:08:02.698338
1054 15:08:04.385927
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 182KB/s
kselftest_armhf.tar 5%[> ] 218.67K 397KB/s
kselftest_armhf.tar 20%[===> ] 806.92K 978KB/s
kselftest_armhf.tar 27%[====> ] 1.09M 1.03MB/s
kselftest_armhf.tar 59%[==========> ] 2.34M 1.86MB/s
kselftest_armhf.tar 77%[==============> ] 3.03M 1.96MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.32MB/s in 1.7s
1055 15:08:04.386372
1056 15:08:04.902182 2024-11-07 15:08:04 (2.32 MB/s) - 'kselftest_armhf.tar.gz' saved [4097444/4097444]
1057 15:08:04.902579
1058 15:08:17.747487 skiplist:
1059 15:08:17.748147 ========================================
1060 15:08:17.752332 ========================================
1061 15:08:17.850616 dt:test_unprobed_devices.sh
1062 15:08:17.880584 ============== Tests to run ===============
1063 15:08:17.890806 dt:test_unprobed_devices.sh
1064 15:08:17.894651 ===========End Tests to run ===============
1065 15:08:17.902518 shardfile-dt pass
1066 15:08:18.134280 <12>[ 71.308784] kselftest: Running tests in dt
1067 15:08:18.162211 TAP version 13
1068 15:08:18.187134 1..1
1069 15:08:18.241013 # timeout set to 45
1070 15:08:18.241406 # selftests: dt: test_unprobed_devices.sh
1071 15:08:19.064467 # TAP version 13
1072 15:08:44.032968 # 1..257
1073 15:08:44.199720 # ok 1 / # SKIP
1074 15:08:44.221380 # ok 2 /clk_mcasp0
1075 15:08:44.292868 # ok 3 /clk_mcasp0_fixed # SKIP
1076 15:08:44.364514 # ok 4 /cpus/cpu@0 # SKIP
1077 15:08:44.437074 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1078 15:08:44.457010 # ok 6 /fixedregulator0
1079 15:08:44.481489 # ok 7 /leds
1080 15:08:44.497773 # ok 8 /ocp
1081 15:08:44.522670 # ok 9 /ocp/interconnect@44c00000
1082 15:08:44.546133 # ok 10 /ocp/interconnect@44c00000/segment@0
1083 15:08:44.573171 # ok 11 /ocp/interconnect@44c00000/segment@100000
1084 15:08:44.592448 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1085 15:08:44.668347 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1086 15:08:44.685176 # ok 14 /ocp/interconnect@44c00000/segment@200000
1087 15:08:44.714410 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1088 15:08:44.818354 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1089 15:08:44.889117 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1090 15:08:44.962377 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1091 15:08:45.034702 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1092 15:08:45.112521 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1093 15:08:45.195514 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1094 15:08:45.262531 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1095 15:08:45.334517 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1096 15:08:45.405334 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1097 15:08:45.479112 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1098 15:08:45.550486 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1099 15:08:45.622799 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1100 15:08:45.695594 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1101 15:08:45.766612 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1102 15:08:45.836755 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1103 15:08:45.909446 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1104 15:08:45.986048 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1105 15:08:46.057147 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1106 15:08:46.138792 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1107 15:08:46.234236 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1108 15:08:46.302676 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1109 15:08:46.375558 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1110 15:08:46.448191 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1111 15:08:46.522201 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1112 15:08:46.604361 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1113 15:08:46.675602 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1114 15:08:46.747284 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1115 15:08:46.819061 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1116 15:08:46.890364 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1117 15:08:46.964265 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1118 15:08:47.035538 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1119 15:08:47.108948 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1120 15:08:47.179668 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1121 15:08:47.251228 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1122 15:08:47.318277 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1123 15:08:47.390039 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1124 15:08:47.472273 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1125 15:08:47.546923 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1126 15:08:47.620402 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1127 15:08:47.691029 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1128 15:08:47.759452 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1129 15:08:47.836551 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1130 15:08:47.904337 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1131 15:08:47.975329 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1132 15:08:48.047785 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1133 15:08:48.123246 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1134 15:08:48.196987 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1135 15:08:48.270379 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1136 15:08:48.340531 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1137 15:08:48.409178 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1138 15:08:48.489873 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1139 15:08:48.565468 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1140 15:08:48.639569 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1141 15:08:48.719034 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1142 15:08:48.788740 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1143 15:08:48.862831 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1144 15:08:48.937301 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1145 15:08:49.010532 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1146 15:08:49.077758 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1147 15:08:49.150829 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1148 15:08:49.221976 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1149 15:08:49.294132 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1150 15:08:49.365801 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1151 15:08:49.438122 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1152 15:08:49.510859 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1153 15:08:49.586973 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1154 15:08:49.660437 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1155 15:08:49.727647 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1156 15:08:49.806783 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1157 15:08:49.872382 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1158 15:08:49.945089 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1159 15:08:50.016987 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1160 15:08:50.088796 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1161 15:08:50.162712 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1162 15:08:50.235524 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1163 15:08:50.305280 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1164 15:08:50.377873 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1165 15:08:50.455931 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1166 15:08:50.526152 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1167 15:08:50.546459 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1168 15:08:50.570736 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1169 15:08:50.594549 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1170 15:08:50.623787 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1171 15:08:50.642871 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1172 15:08:50.666625 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1173 15:08:50.690760 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1174 15:08:50.712594 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1175 15:08:50.819315 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1176 15:08:50.848177 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1177 15:08:50.869175 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1178 15:08:50.892469 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1179 15:08:50.998380 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1180 15:08:51.078091 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1181 15:08:51.151436 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1182 15:08:51.219111 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1183 15:08:51.294170 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1184 15:08:51.365059 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1185 15:08:51.437996 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1186 15:08:51.509779 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1187 15:08:51.587393 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1188 15:08:51.655923 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1189 15:08:51.728546 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1190 15:08:51.800974 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1191 15:08:51.877376 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1192 15:08:51.952893 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1193 15:08:52.021594 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1194 15:08:52.094368 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1195 15:08:52.115856 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1196 15:08:52.186845 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1197 15:08:52.256576 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1198 15:08:52.329763 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1199 15:08:52.352406 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1200 15:08:52.424885 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1201 15:08:52.451572 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1202 15:08:52.517863 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1203 15:08:52.541285 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1204 15:08:52.565744 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1205 15:08:52.593308 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1206 15:08:52.617023 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1207 15:08:52.637127 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1208 15:08:52.664901 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1209 15:08:52.688593 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1210 15:08:52.760155 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1211 15:08:52.782331 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1212 15:08:52.804761 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1213 15:08:52.877626 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1214 15:08:52.948955 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1215 15:08:52.970393 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1216 15:08:53.070643 # not ok 144 /ocp/interconnect@47c00000
1217 15:08:53.145808 # not ok 145 /ocp/interconnect@47c00000/segment@0
1218 15:08:53.162303 # ok 146 /ocp/interconnect@48000000
1219 15:08:53.186096 # ok 147 /ocp/interconnect@48000000/segment@0
1220 15:08:53.211651 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1221 15:08:53.234735 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1222 15:08:53.263069 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1223 15:08:53.285591 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1224 15:08:53.307053 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1225 15:08:53.329858 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1226 15:08:53.352262 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1227 15:08:53.427233 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1228 15:08:53.501649 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1229 15:08:53.519619 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1230 15:08:53.544393 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1231 15:08:53.570766 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1232 15:08:53.591011 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1233 15:08:53.616983 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1234 15:08:53.643359 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1235 15:08:53.666897 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1236 15:08:53.686560 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1237 15:08:53.708951 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1238 15:08:53.733650 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1239 15:08:53.756163 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1240 15:08:53.780604 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1241 15:08:53.803094 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1242 15:08:53.829506 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1243 15:08:53.850496 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1244 15:08:53.874895 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1245 15:08:53.901967 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1246 15:08:53.927140 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1247 15:08:53.945548 # ok 175 /ocp/interconnect@48000000/segment@100000
1248 15:08:53.973395 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1249 15:08:53.997954 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1250 15:08:54.069532 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1251 15:08:54.138509 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1252 15:08:54.209421 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1253 15:08:54.287508 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1254 15:08:54.357722 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1255 15:08:54.431001 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1256 15:08:54.496824 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1257 15:08:54.576431 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1258 15:08:54.591967 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1259 15:08:54.615755 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1260 15:08:54.639479 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1261 15:08:54.667283 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1262 15:08:54.687192 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1263 15:08:54.715762 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1264 15:08:54.736656 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1265 15:08:54.763619 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1266 15:08:54.787272 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1267 15:08:54.806826 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1268 15:08:54.834645 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1269 15:08:54.856995 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1270 15:08:54.878896 # ok 198 /ocp/interconnect@48000000/segment@200000
1271 15:08:54.900777 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1272 15:08:54.973660 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1273 15:08:54.993714 # ok 201 /ocp/interconnect@48000000/segment@300000
1274 15:08:55.019972 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1275 15:08:55.046839 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1276 15:08:55.066685 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1277 15:08:55.093916 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1278 15:08:55.117242 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1279 15:08:55.136470 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1280 15:08:55.217197 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1281 15:08:55.233157 # ok 209 /ocp/interconnect@4a000000
1282 15:08:55.255115 # ok 210 /ocp/interconnect@4a000000/segment@0
1283 15:08:55.278304 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1284 15:08:55.302456 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1285 15:08:55.327259 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1286 15:08:55.353859 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1287 15:08:55.425321 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1288 15:08:55.529134 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1289 15:08:55.599196 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1290 15:08:55.702274 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1291 15:08:55.773275 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1292 15:08:55.844743 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1293 15:08:55.943456 # not ok 221 /ocp/interconnect@4b140000
1294 15:08:56.016295 # not ok 222 /ocp/interconnect@4b140000/segment@0
1295 15:08:56.092166 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1296 15:08:56.112884 # ok 224 /ocp/target-module@40300000
1297 15:08:56.131642 # ok 225 /ocp/target-module@40300000/sram@0
1298 15:08:56.207097 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1299 15:08:56.281438 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1300 15:08:56.296071 # ok 228 /ocp/target-module@47400000
1301 15:08:56.325829 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1302 15:08:56.345389 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1303 15:08:56.365507 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1304 15:08:56.392959 # ok 232 /ocp/target-module@47400000/usb@1400
1305 15:08:56.415281 # ok 233 /ocp/target-module@47400000/usb@1800
1306 15:08:56.433175 # ok 234 /ocp/target-module@47810000
1307 15:08:56.460294 # ok 235 /ocp/target-module@49000000
1308 15:08:56.483633 # ok 236 /ocp/target-module@49000000/dma@0
1309 15:08:56.504562 # ok 237 /ocp/target-module@49800000
1310 15:08:56.531167 # ok 238 /ocp/target-module@49800000/dma@0
1311 15:08:56.545957 # ok 239 /ocp/target-module@49900000
1312 15:08:56.569442 # ok 240 /ocp/target-module@49900000/dma@0
1313 15:08:56.594504 # ok 241 /ocp/target-module@49a00000
1314 15:08:56.616833 # ok 242 /ocp/target-module@49a00000/dma@0
1315 15:08:56.642490 # ok 243 /ocp/target-module@4c000000
1316 15:08:56.715435 # not ok 244 /ocp/target-module@4c000000/emif@0
1317 15:08:56.740633 # ok 245 /ocp/target-module@50000000
1318 15:08:56.762469 # ok 246 /ocp/target-module@53100000
1319 15:08:56.831033 # not ok 247 /ocp/target-module@53100000/sham@0
1320 15:08:56.854312 # ok 248 /ocp/target-module@53500000
1321 15:08:56.924665 # not ok 249 /ocp/target-module@53500000/aes@0
1322 15:08:56.946246 # ok 250 /ocp/target-module@56000000
1323 15:08:57.055623 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1324 15:08:57.123594 # ok 252 /opp-table # SKIP
1325 15:08:57.190469 # ok 253 /soc # SKIP
1326 15:08:57.211000 # ok 254 /sound
1327 15:08:57.239881 # ok 255 /target-module@4b000000
1328 15:08:57.264766 # ok 256 /target-module@4b000000/target-module@140000
1329 15:08:57.281390 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1330 15:08:57.289780 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1331 15:08:57.299127 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1332 15:08:59.563017 dt_test_unprobed_devices_sh_ skip
1333 15:08:59.568676 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1334 15:08:59.574091 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1335 15:08:59.574462 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1336 15:08:59.579839 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1337 15:08:59.585377 dt_test_unprobed_devices_sh_fixedregulator0 pass
1338 15:08:59.591020 dt_test_unprobed_devices_sh_leds pass
1339 15:08:59.591382 dt_test_unprobed_devices_sh_ocp pass
1340 15:08:59.596562 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1341 15:08:59.602104 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1342 15:08:59.607821 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1343 15:08:59.618911 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1344 15:08:59.624454 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1345 15:08:59.630036 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1346 15:08:59.641249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1347 15:08:59.646861 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1348 15:08:59.658193 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1349 15:08:59.669395 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1350 15:08:59.680611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1351 15:08:59.686263 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1352 15:08:59.697474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1353 15:08:59.708760 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1354 15:08:59.719957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1355 15:08:59.731154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1356 15:08:59.736839 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1357 15:08:59.747963 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1358 15:08:59.759136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1359 15:08:59.770282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1360 15:08:59.781529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1361 15:08:59.787126 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1362 15:08:59.798305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1363 15:08:59.809560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1364 15:08:59.820756 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1365 15:08:59.826326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1366 15:08:59.837516 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1367 15:08:59.848774 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1368 15:08:59.859897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1369 15:08:59.871095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1370 15:08:59.876711 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1371 15:08:59.887865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1372 15:08:59.899103 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1373 15:08:59.910262 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1374 15:08:59.921492 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1375 15:08:59.932667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1376 15:08:59.943845 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1377 15:08:59.955058 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1378 15:08:59.966204 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1379 15:08:59.977469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1380 15:08:59.988619 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1381 15:08:59.999781 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1382 15:09:00.010963 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1383 15:09:00.022184 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1384 15:09:00.033467 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1385 15:09:00.044541 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1386 15:09:00.055760 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1387 15:09:00.067043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1388 15:09:00.078267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1389 15:09:00.089352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1390 15:09:00.100590 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1391 15:09:00.111799 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1392 15:09:00.122926 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1393 15:09:00.134136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1394 15:09:00.145308 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1395 15:09:00.156504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1396 15:09:00.162102 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1397 15:09:00.173304 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1398 15:09:00.184483 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1399 15:09:00.195687 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1400 15:09:00.206874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1401 15:09:00.218092 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1402 15:09:00.229258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1403 15:09:00.240492 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1404 15:09:00.251656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1405 15:09:00.262886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1406 15:09:00.274043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1407 15:09:00.285226 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1408 15:09:00.296400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1409 15:09:00.307724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1410 15:09:00.318891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1411 15:09:00.330030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1412 15:09:00.341223 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1413 15:09:00.352409 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1414 15:09:00.358066 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1415 15:09:00.369227 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1416 15:09:00.380459 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1417 15:09:00.391602 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1418 15:09:00.402780 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1419 15:09:00.408458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1420 15:09:00.425156 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1421 15:09:00.436387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1422 15:09:00.442028 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1423 15:09:00.458732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1424 15:09:00.469970 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1425 15:09:00.481098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1426 15:09:00.486783 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1427 15:09:00.497906 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1428 15:09:00.509068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1429 15:09:00.514734 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1430 15:09:00.525905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1431 15:09:00.537038 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1432 15:09:00.542715 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1433 15:09:00.553903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1434 15:09:00.559488 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1435 15:09:00.570648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1436 15:09:00.581833 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1437 15:09:00.593071 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1438 15:09:00.604307 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1439 15:09:00.615453 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1440 15:09:00.626622 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1441 15:09:00.637855 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1442 15:09:00.649072 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1443 15:09:00.660272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1444 15:09:00.671426 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1445 15:09:00.682583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1446 15:09:00.693762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1447 15:09:00.710561 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1448 15:09:00.721754 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1449 15:09:00.732963 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1450 15:09:00.744153 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1451 15:09:00.755354 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1452 15:09:00.772147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1453 15:09:00.783296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1454 15:09:00.794481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1455 15:09:00.805700 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1456 15:09:00.811342 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1457 15:09:00.822461 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1458 15:09:00.833656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1459 15:09:00.839398 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1460 15:09:00.850455 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1461 15:09:00.856179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1462 15:09:00.867268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1463 15:09:00.872904 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1464 15:09:00.884064 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1465 15:09:00.889665 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1466 15:09:00.900814 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1467 15:09:00.906532 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1468 15:09:00.917583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1469 15:09:00.928768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1470 15:09:00.940089 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1471 15:09:00.951198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1472 15:09:00.962398 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1473 15:09:00.968042 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1474 15:09:00.979133 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1475 15:09:00.984826 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1476 15:09:00.990399 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1477 15:09:00.996045 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1478 15:09:01.001582 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1479 15:09:01.007194 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1480 15:09:01.018324 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1481 15:09:01.024010 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1482 15:09:01.029567 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1483 15:09:01.040677 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1484 15:09:01.046343 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1485 15:09:01.057480 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1486 15:09:01.063121 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1487 15:09:01.074308 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1488 15:09:01.079935 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1489 15:09:01.091053 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1490 15:09:01.096732 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1491 15:09:01.107838 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1492 15:09:01.113509 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1493 15:09:01.124620 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1494 15:09:01.130305 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1495 15:09:01.141393 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1496 15:09:01.147066 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1497 15:09:01.152689 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1498 15:09:01.163839 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1499 15:09:01.169442 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1500 15:09:01.180562 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1501 15:09:01.186208 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1502 15:09:01.197371 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1503 15:09:01.203027 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1504 15:09:01.214365 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1505 15:09:01.219890 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1506 15:09:01.225484 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1507 15:09:01.236481 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1508 15:09:01.242146 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1509 15:09:01.253276 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1510 15:09:01.264463 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1511 15:09:01.275660 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1512 15:09:01.286836 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1513 15:09:01.298050 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1514 15:09:01.309231 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1515 15:09:01.320580 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1516 15:09:01.331650 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1517 15:09:01.337292 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1518 15:09:01.348452 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1519 15:09:01.354082 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1520 15:09:01.365189 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1521 15:09:01.370879 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1522 15:09:01.382183 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1523 15:09:01.387616 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1524 15:09:01.398849 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1525 15:09:01.404463 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1526 15:09:01.415570 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1527 15:09:01.421293 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1528 15:09:01.432403 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1529 15:09:01.438003 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1530 15:09:01.449281 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1531 15:09:01.454869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1532 15:09:01.460461 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1533 15:09:01.471616 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1534 15:09:01.477250 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1535 15:09:01.488438 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1536 15:09:01.494186 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1537 15:09:01.505255 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1538 15:09:01.510900 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1539 15:09:01.522137 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1540 15:09:01.527762 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1541 15:09:01.533354 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1542 15:09:01.538949 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1543 15:09:01.550182 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1544 15:09:01.561380 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1545 15:09:01.567033 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1546 15:09:01.572663 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1547 15:09:01.583826 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1548 15:09:01.595042 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1549 15:09:01.606266 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1550 15:09:01.617502 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1551 15:09:01.623114 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1552 15:09:01.628662 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1553 15:09:01.634309 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1554 15:09:01.639906 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1555 15:09:01.645678 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1556 15:09:01.651140 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1557 15:09:01.662324 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1558 15:09:01.667955 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1559 15:09:01.673491 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1560 15:09:01.679085 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1561 15:09:01.684785 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1562 15:09:01.696050 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1563 15:09:01.701638 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1564 15:09:01.707226 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1565 15:09:01.712889 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1566 15:09:01.718440 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1567 15:09:01.724116 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1568 15:09:01.729640 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1569 15:09:01.735246 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1570 15:09:01.740844 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1571 15:09:01.746351 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1572 15:09:01.752110 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1573 15:09:01.757669 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1574 15:09:01.763203 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1575 15:09:01.768812 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1576 15:09:01.774433 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1577 15:09:01.780123 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1578 15:09:01.785666 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1579 15:09:01.791230 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1580 15:09:01.796866 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1581 15:09:01.802554 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1582 15:09:01.807973 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1583 15:09:01.808304 dt_test_unprobed_devices_sh_opp-table skip
1584 15:09:01.813606 dt_test_unprobed_devices_sh_soc skip
1585 15:09:01.819196 dt_test_unprobed_devices_sh_sound pass
1586 15:09:01.824787 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1587 15:09:01.830424 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1588 15:09:01.836035 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1589 15:09:01.841618 dt_test_unprobed_devices_sh fail
1590 15:09:01.842060 + ../../utils/send-to-lava.sh ./output/result.txt
1591 15:09:01.849575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1592 15:09:01.850406 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1594 15:09:01.861461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1595 15:09:01.862186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1597 15:09:01.953187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1598 15:09:01.954070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1600 15:09:02.039806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1601 15:09:02.040766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1603 15:09:02.129687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1604 15:09:02.130596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1606 15:09:02.222294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1607 15:09:02.223220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1609 15:09:02.305193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1610 15:09:02.306062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1612 15:09:02.388266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1613 15:09:02.389140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1615 15:09:02.479132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1616 15:09:02.480049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1618 15:09:02.573869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1619 15:09:02.574572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1621 15:09:02.665589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1622 15:09:02.666482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1624 15:09:02.752359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1625 15:09:02.753215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1627 15:09:02.846402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1628 15:09:02.847257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1630 15:09:02.940299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1631 15:09:02.941175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1633 15:09:03.025407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1634 15:09:03.026241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1636 15:09:03.119937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1637 15:09:03.120608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1639 15:09:03.212276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1640 15:09:03.213078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1642 15:09:03.304194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1643 15:09:03.305448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1645 15:09:03.389714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1646 15:09:03.390596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1648 15:09:03.481567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1649 15:09:03.482426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1651 15:09:03.567023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1652 15:09:03.567689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1654 15:09:03.653542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1655 15:09:03.654326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1657 15:09:03.744934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1658 15:09:03.745716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1660 15:09:03.828962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1661 15:09:03.829594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1663 15:09:03.915031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1664 15:09:03.915880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1666 15:09:04.005677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1667 15:09:04.006440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1669 15:09:04.096217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1670 15:09:04.097107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1672 15:09:04.195861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1673 15:09:04.196820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1675 15:09:04.287513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1676 15:09:04.288533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1678 15:09:04.372318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1679 15:09:04.373201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1681 15:09:04.460546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1682 15:09:04.461417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1684 15:09:04.551267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1685 15:09:04.551933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1687 15:09:04.634445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1688 15:09:04.635311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1690 15:09:04.721556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1691 15:09:04.722470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1693 15:09:04.807442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1694 15:09:04.808070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1696 15:09:04.893952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1697 15:09:04.894956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1699 15:09:04.976922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1700 15:09:04.977905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1702 15:09:05.061933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1703 15:09:05.062797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1705 15:09:05.149479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1706 15:09:05.150356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1708 15:09:05.239605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1709 15:09:05.240578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1711 15:09:05.324684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1712 15:09:05.325569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1714 15:09:05.410133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1715 15:09:05.410784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1717 15:09:05.495508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1718 15:09:05.496436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1720 15:09:05.581687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1721 15:09:05.582319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1723 15:09:05.671179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1724 15:09:05.672031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1726 15:09:05.756980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1727 15:09:05.757843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1729 15:09:05.848310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1730 15:09:05.849132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1732 15:09:05.933750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1733 15:09:05.934581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1735 15:09:06.021392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1736 15:09:06.022255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1738 15:09:06.111847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1739 15:09:06.112740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1741 15:09:06.197509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1742 15:09:06.198401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1744 15:09:06.287525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1745 15:09:06.288442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1747 15:09:06.372749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1748 15:09:06.373602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1750 15:09:06.460459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1751 15:09:06.461343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1753 15:09:06.552938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1754 15:09:06.553618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1756 15:09:06.638545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1757 15:09:06.639207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1759 15:09:06.779188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1760 15:09:06.779813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1762 15:09:06.871568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1763 15:09:06.872450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1765 15:09:06.962275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1766 15:09:06.963108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1768 15:09:07.054386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1769 15:09:07.055268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1771 15:09:07.146014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1772 15:09:07.146864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1774 15:09:07.238754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1775 15:09:07.239612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1777 15:09:07.330348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1778 15:09:07.331198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1780 15:09:07.416947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1781 15:09:07.417841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1783 15:09:07.508022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1784 15:09:07.508880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1786 15:09:07.598213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1787 15:09:07.599307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1789 15:09:07.687729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1790 15:09:07.688727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1792 15:09:07.780533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1793 15:09:07.781568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1795 15:09:07.889499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1796 15:09:07.890181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1798 15:09:07.984602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1799 15:09:07.985289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1801 15:09:08.077523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1802 15:09:08.078303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1804 15:09:08.167110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1805 15:09:08.167917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1807 15:09:08.253019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1808 15:09:08.253655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1810 15:09:08.339429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1811 15:09:08.340140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1813 15:09:08.431406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1814 15:09:08.432123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1816 15:09:08.524348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1817 15:09:08.525042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1819 15:09:08.618434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1820 15:09:08.619736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1822 15:09:08.709635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1823 15:09:08.710582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1825 15:09:08.801917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1826 15:09:08.802817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1828 15:09:08.887799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1829 15:09:08.888715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1831 15:09:08.973280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1832 15:09:08.974143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1834 15:09:09.065529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1835 15:09:09.066460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1837 15:09:09.156554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1838 15:09:09.157446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1840 15:09:09.252248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1841 15:09:09.253202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1843 15:09:09.341088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1844 15:09:09.341926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1846 15:09:09.433107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1847 15:09:09.433998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1849 15:09:09.525674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1850 15:09:09.526579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1852 15:09:09.618577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1853 15:09:09.619431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1855 15:09:09.705262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1856 15:09:09.706145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1858 15:09:09.800846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1859 15:09:09.801760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1861 15:09:09.894585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1862 15:09:09.895276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1864 15:09:09.984554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1865 15:09:09.985183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1867 15:09:10.077029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1868 15:09:10.077663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1870 15:09:10.169513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1871 15:09:10.170434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1873 15:09:10.257718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1874 15:09:10.258631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1876 15:09:10.347996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1877 15:09:10.348929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1879 15:09:10.443434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1880 15:09:10.444393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1882 15:09:10.537832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1883 15:09:10.538532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1885 15:09:10.622819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1886 15:09:10.623494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1888 15:09:10.713730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1889 15:09:10.714395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1891 15:09:10.799902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1892 15:09:10.800611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1894 15:09:10.885511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1895 15:09:10.886193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1897 15:09:10.973238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1898 15:09:10.973917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1900 15:09:11.058855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1901 15:09:11.059534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1903 15:09:11.144955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1904 15:09:11.145628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1906 15:09:11.228269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1907 15:09:11.228945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1909 15:09:11.314160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1910 15:09:11.314832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1912 15:09:11.400468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1913 15:09:11.401111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1915 15:09:11.493934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1916 15:09:11.494875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1918 15:09:11.580128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1919 15:09:11.581085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1921 15:09:11.672980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1922 15:09:11.673822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1924 15:09:11.761624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1925 15:09:11.762473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1927 15:09:11.848850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1928 15:09:11.849711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1930 15:09:11.942721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1931 15:09:11.943579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1933 15:09:12.035763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1934 15:09:12.036735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1936 15:09:12.137674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1937 15:09:12.138927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1939 15:09:12.231946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1940 15:09:12.232919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1942 15:09:12.330185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1943 15:09:12.331113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1945 15:09:12.421449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1946 15:09:12.422081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1948 15:09:12.506769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1949 15:09:12.507402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1951 15:09:12.597722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1953 15:09:12.600852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1954 15:09:12.689571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1956 15:09:12.692634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1957 15:09:12.776386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1959 15:09:12.778620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1960 15:09:12.869598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1961 15:09:12.871372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1963 15:09:12.959832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1964 15:09:12.960597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1966 15:09:13.046507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1967 15:09:13.047221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1969 15:09:13.146844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1970 15:09:13.147730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1972 15:09:13.228042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1973 15:09:13.228913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1975 15:09:13.319681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1976 15:09:13.320596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1978 15:09:13.406336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1979 15:09:13.407165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1981 15:09:13.498525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1982 15:09:13.499368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1984 15:09:13.584952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1985 15:09:13.585781 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1987 15:09:13.671419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1988 15:09:13.672232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1990 15:09:13.758020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1991 15:09:13.758715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1993 15:09:13.851398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1994 15:09:13.852049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1996 15:09:13.942514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1997 15:09:13.943172 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1999 15:09:14.034804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2000 15:09:14.035824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2002 15:09:14.126713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2003 15:09:14.127787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2005 15:09:14.217742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2006 15:09:14.218710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2008 15:09:14.308029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2009 15:09:14.308970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2011 15:09:14.395463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2012 15:09:14.396504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2014 15:09:14.492080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2015 15:09:14.493148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2017 15:09:14.583600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2018 15:09:14.584667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2020 15:09:14.673142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2021 15:09:14.674127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2023 15:09:14.761313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2024 15:09:14.762348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2026 15:09:14.852608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2027 15:09:14.853643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2029 15:09:14.937086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2030 15:09:14.938005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2032 15:09:15.023748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2033 15:09:15.024805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2035 15:09:15.116613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2036 15:09:15.117628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2038 15:09:15.203221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2039 15:09:15.204229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2041 15:09:15.293076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2042 15:09:15.294066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2044 15:09:15.378651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2045 15:09:15.379671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2047 15:09:15.465460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2048 15:09:15.466508 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2050 15:09:15.557305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2051 15:09:15.558213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2053 15:09:15.644564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2054 15:09:15.645444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2056 15:09:15.736342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2057 15:09:15.737277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2059 15:09:15.830249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2060 15:09:15.831166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2062 15:09:15.922959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2063 15:09:15.923955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2065 15:09:16.018413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2066 15:09:16.019545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2068 15:09:16.104263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2069 15:09:16.105485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2071 15:09:16.192522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2072 15:09:16.193589 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2074 15:09:16.285126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2075 15:09:16.286070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2077 15:09:16.373887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2078 15:09:16.375024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2080 15:09:16.467768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2081 15:09:16.469109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2083 15:09:16.560326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2084 15:09:16.561488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2086 15:09:16.646618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2087 15:09:16.647884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2089 15:09:16.738195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2090 15:09:16.739283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2092 15:09:16.825102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2093 15:09:16.826181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2095 15:09:16.914296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2096 15:09:16.915335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2098 15:09:16.999328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2099 15:09:17.000385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2101 15:09:17.086363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2102 15:09:17.087395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2104 15:09:17.177244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2105 15:09:17.178337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2107 15:09:17.261415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2108 15:09:17.262596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2110 15:09:17.345049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2111 15:09:17.346207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2113 15:09:17.441795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2114 15:09:17.442574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2116 15:09:17.533460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2117 15:09:17.534208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2119 15:09:17.621467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2120 15:09:17.622214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2122 15:09:17.710827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2123 15:09:17.711545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2125 15:09:17.798114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2126 15:09:17.798845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2128 15:09:17.890235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2129 15:09:17.890975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2131 15:09:17.977321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2132 15:09:17.978118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2134 15:09:18.067117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2135 15:09:18.067874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2137 15:09:18.156282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2138 15:09:18.157031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2140 15:09:18.243914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2141 15:09:18.244712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2143 15:09:18.334317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2144 15:09:18.335062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2146 15:09:18.438133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2147 15:09:18.439426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2149 15:09:18.527834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2150 15:09:18.528686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2152 15:09:18.619132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2153 15:09:18.619902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2155 15:09:18.704692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2156 15:09:18.705293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2158 15:09:18.790537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2159 15:09:18.791309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2161 15:09:18.876648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2162 15:09:18.877384 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2164 15:09:18.968891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2165 15:09:18.969724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2167 15:09:19.054595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2168 15:09:19.055428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2170 15:09:19.140681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2171 15:09:19.141490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2173 15:09:19.225850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2174 15:09:19.226582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2176 15:09:19.316327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2177 15:09:19.317077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2179 15:09:19.404728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2180 15:09:19.405490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2182 15:09:19.493309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2183 15:09:19.494059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2185 15:09:19.574416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2186 15:09:19.575203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2188 15:09:19.659263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2189 15:09:19.659995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2191 15:09:19.744301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2192 15:09:19.745021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2194 15:09:19.826121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2195 15:09:19.826941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2197 15:09:19.911871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2198 15:09:19.912691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2200 15:09:19.997582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2201 15:09:19.998414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2203 15:09:20.083218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2204 15:09:20.084056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2206 15:09:20.173862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2207 15:09:20.174664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2209 15:09:20.264462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2210 15:09:20.265245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2212 15:09:20.349549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2213 15:09:20.350345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2215 15:09:20.436367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2216 15:09:20.437201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2218 15:09:20.523039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2219 15:09:20.523838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2221 15:09:20.607782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2222 15:09:20.608614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2224 15:09:20.699733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2225 15:09:20.700545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2227 15:09:20.786556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2228 15:09:20.787301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2230 15:09:20.873630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2231 15:09:20.874366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2233 15:09:20.964504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2234 15:09:20.965146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2236 15:09:21.055952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2237 15:09:21.056834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2239 15:09:21.148291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2240 15:09:21.149065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2242 15:09:21.236740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2243 15:09:21.237518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2245 15:09:21.327192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2246 15:09:21.327952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2248 15:09:21.419279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2249 15:09:21.420093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2251 15:09:21.505863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2252 15:09:21.506657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2254 15:09:21.587848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2255 15:09:21.588653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2257 15:09:21.681023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2258 15:09:21.681779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2260 15:09:21.772269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2261 15:09:21.773023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2263 15:09:21.862684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2264 15:09:21.863454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2266 15:09:21.949062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2267 15:09:21.949809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2269 15:09:22.042068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2270 15:09:22.042793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2272 15:09:22.130400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2274 15:09:22.133503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2275 15:09:22.221306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2276 15:09:22.222026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2278 15:09:22.308268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2279 15:09:22.308987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2281 15:09:22.392857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2282 15:09:22.393616 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2284 15:09:22.484116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2285 15:09:22.484863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2287 15:09:22.568950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2288 15:09:22.569738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2290 15:09:22.660404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2291 15:09:22.661172 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2293 15:09:22.753040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2294 15:09:22.753896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2296 15:09:22.863508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2297 15:09:22.864148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2299 15:09:22.987339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2300 15:09:22.988385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2302 15:09:23.090832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2303 15:09:23.091817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2305 15:09:23.190489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2306 15:09:23.191220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2308 15:09:23.284982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2309 15:09:23.285977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2311 15:09:23.393651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2312 15:09:23.394577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2314 15:09:23.491604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2315 15:09:23.492545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2317 15:09:23.591575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2318 15:09:23.592509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2320 15:09:23.684956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2321 15:09:23.685840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2323 15:09:23.797939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2324 15:09:23.798842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2326 15:09:23.901450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2327 15:09:23.902352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2329 15:09:24.015450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2330 15:09:24.016410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2332 15:09:24.135548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2333 15:09:24.136498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2335 15:09:24.231755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2336 15:09:24.232720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2338 15:09:24.333071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2339 15:09:24.333914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2341 15:09:24.422686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2342 15:09:24.423521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2344 15:09:24.508060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2345 15:09:24.508885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2347 15:09:24.598538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2348 15:09:24.599367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2350 15:09:24.688852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2351 15:09:24.689647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2353 15:09:24.773523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2354 15:09:24.774302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2356 15:09:24.867818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2357 15:09:24.868645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2359 15:09:24.962190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2360 15:09:24.963131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2362 15:09:25.052434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2363 15:09:25.053372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2365 15:09:25.134675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2366 15:09:25.135270 + set +x
2367 15:09:25.135976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2369 15:09:25.138785 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 953450_1.6.2.4.5>
2370 15:09:25.139502 Received signal: <ENDRUN> 1_kselftest-dt 953450_1.6.2.4.5
2371 15:09:25.139959 Ending use of test pattern.
2372 15:09:25.140414 Ending test lava.1_kselftest-dt (953450_1.6.2.4.5), duration 83.49
2374 15:09:25.145063 <LAVA_TEST_RUNNER EXIT>
2375 15:09:25.145767 ok: lava_test_shell seems to have completed
2376 15:09:25.158890 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2377 15:09:25.160808 end: 3.1 lava-test-shell (duration 00:01:25) [common]
2378 15:09:25.161382 end: 3 lava-test-retry (duration 00:01:25) [common]
2379 15:09:25.162000 start: 4 finalize (timeout 00:05:32) [common]
2380 15:09:25.162588 start: 4.1 power-off (timeout 00:00:30) [common]
2381 15:09:25.163607 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2382 15:09:25.197277 >> OK - accepted request
2383 15:09:25.199320 Returned 0 in 0 seconds
2384 15:09:25.300529 end: 4.1 power-off (duration 00:00:00) [common]
2386 15:09:25.302242 start: 4.2 read-feedback (timeout 00:05:31) [common]
2387 15:09:25.303376 Listened to connection for namespace 'common' for up to 1s
2388 15:09:25.304322 Listened to connection for namespace 'common' for up to 1s
2389 15:09:26.304192 Finalising connection for namespace 'common'
2390 15:09:26.304944 Disconnecting from shell: Finalise
2391 15:09:26.305477 / #
2392 15:09:26.406525 end: 4.2 read-feedback (duration 00:00:01) [common]
2393 15:09:26.407315 end: 4 finalize (duration 00:00:01) [common]
2394 15:09:26.408138 Cleaning after the job
2395 15:09:26.408836 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953450/tftp-deploy-ouv51k85/ramdisk
2396 15:09:26.411508 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953450/tftp-deploy-ouv51k85/kernel
2397 15:09:26.413468 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953450/tftp-deploy-ouv51k85/dtb
2398 15:09:26.414661 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953450/tftp-deploy-ouv51k85/nfsrootfs
2399 15:09:26.454562 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953450/tftp-deploy-ouv51k85/modules
2400 15:09:26.462407 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/953450
2401 15:09:29.553953 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/953450
2402 15:09:29.554522 Job finished correctly