Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 14:38:14.437798 lava-dispatcher, installed at version: 2024.01
2 14:38:14.438609 start: 0 validate
3 14:38:14.439129 Start time: 2024-11-07 14:38:14.439098+00:00 (UTC)
4 14:38:14.439693 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 14:38:14.440283 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 14:38:14.485662 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 14:38:14.486204 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-239-gba19e4550e25a%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 14:38:15.530329 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 14:38:15.530974 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-239-gba19e4550e25a%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 14:38:20.601024 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 14:38:20.601556 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-239-gba19e4550e25a%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 14:38:21.659809 validate duration: 7.22
14 14:38:21.660683 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 14:38:21.661055 start: 1.1 download-retry (timeout 00:10:00) [common]
16 14:38:21.661358 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 14:38:21.662018 Not decompressing ramdisk as can be used compressed.
18 14:38:21.662446 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 14:38:21.662683 saving as /var/lib/lava/dispatcher/tmp/953550/tftp-deploy-18laxw67/ramdisk/rootfs.cpio.gz
20 14:38:21.662952 total size: 8181887 (7 MB)
21 14:38:21.716655 progress 0 % (0 MB)
22 14:38:21.728808 progress 5 % (0 MB)
23 14:38:21.740412 progress 10 % (0 MB)
24 14:38:21.753115 progress 15 % (1 MB)
25 14:38:21.759952 progress 20 % (1 MB)
26 14:38:21.765777 progress 25 % (1 MB)
27 14:38:21.771126 progress 30 % (2 MB)
28 14:38:21.776982 progress 35 % (2 MB)
29 14:38:21.782461 progress 40 % (3 MB)
30 14:38:21.788158 progress 45 % (3 MB)
31 14:38:21.793454 progress 50 % (3 MB)
32 14:38:21.799074 progress 55 % (4 MB)
33 14:38:21.804422 progress 60 % (4 MB)
34 14:38:21.810163 progress 65 % (5 MB)
35 14:38:21.815441 progress 70 % (5 MB)
36 14:38:21.821126 progress 75 % (5 MB)
37 14:38:21.826427 progress 80 % (6 MB)
38 14:38:21.832367 progress 85 % (6 MB)
39 14:38:21.837692 progress 90 % (7 MB)
40 14:38:21.843224 progress 95 % (7 MB)
41 14:38:21.848039 progress 100 % (7 MB)
42 14:38:21.848675 7 MB downloaded in 0.19 s (42.02 MB/s)
43 14:38:21.849205 end: 1.1.1 http-download (duration 00:00:00) [common]
45 14:38:21.850096 end: 1.1 download-retry (duration 00:00:00) [common]
46 14:38:21.850403 start: 1.2 download-retry (timeout 00:10:00) [common]
47 14:38:21.850672 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 14:38:21.851143 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm64/defconfig/gcc-12/kernel/Image
49 14:38:21.851406 saving as /var/lib/lava/dispatcher/tmp/953550/tftp-deploy-18laxw67/kernel/Image
50 14:38:21.851614 total size: 45713920 (43 MB)
51 14:38:21.851824 No compression specified
52 14:38:21.891917 progress 0 % (0 MB)
53 14:38:21.919862 progress 5 % (2 MB)
54 14:38:21.948215 progress 10 % (4 MB)
55 14:38:21.976396 progress 15 % (6 MB)
56 14:38:22.004846 progress 20 % (8 MB)
57 14:38:22.033003 progress 25 % (10 MB)
58 14:38:22.061268 progress 30 % (13 MB)
59 14:38:22.089396 progress 35 % (15 MB)
60 14:38:22.118033 progress 40 % (17 MB)
61 14:38:22.146333 progress 45 % (19 MB)
62 14:38:22.174575 progress 50 % (21 MB)
63 14:38:22.202945 progress 55 % (24 MB)
64 14:38:22.231104 progress 60 % (26 MB)
65 14:38:22.259335 progress 65 % (28 MB)
66 14:38:22.287678 progress 70 % (30 MB)
67 14:38:22.315732 progress 75 % (32 MB)
68 14:38:22.344200 progress 80 % (34 MB)
69 14:38:22.372128 progress 85 % (37 MB)
70 14:38:22.400036 progress 90 % (39 MB)
71 14:38:22.428559 progress 95 % (41 MB)
72 14:38:22.456313 progress 100 % (43 MB)
73 14:38:22.456818 43 MB downloaded in 0.61 s (72.04 MB/s)
74 14:38:22.457298 end: 1.2.1 http-download (duration 00:00:01) [common]
76 14:38:22.458150 end: 1.2 download-retry (duration 00:00:01) [common]
77 14:38:22.458432 start: 1.3 download-retry (timeout 00:09:59) [common]
78 14:38:22.458697 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 14:38:22.459161 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 14:38:22.459426 saving as /var/lib/lava/dispatcher/tmp/953550/tftp-deploy-18laxw67/dtb/meson-g12b-a311d-libretech-cc.dtb
81 14:38:22.459634 total size: 54703 (0 MB)
82 14:38:22.459844 No compression specified
83 14:38:22.494712 progress 59 % (0 MB)
84 14:38:22.495549 progress 100 % (0 MB)
85 14:38:22.496129 0 MB downloaded in 0.04 s (1.43 MB/s)
86 14:38:22.496601 end: 1.3.1 http-download (duration 00:00:00) [common]
88 14:38:22.497420 end: 1.3 download-retry (duration 00:00:00) [common]
89 14:38:22.497683 start: 1.4 download-retry (timeout 00:09:59) [common]
90 14:38:22.497950 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 14:38:22.498409 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm64/defconfig/gcc-12/modules.tar.xz
92 14:38:22.498649 saving as /var/lib/lava/dispatcher/tmp/953550/tftp-deploy-18laxw67/modules/modules.tar
93 14:38:22.498854 total size: 11601668 (11 MB)
94 14:38:22.499065 Using unxz to decompress xz
95 14:38:22.539510 progress 0 % (0 MB)
96 14:38:22.607398 progress 5 % (0 MB)
97 14:38:22.684396 progress 10 % (1 MB)
98 14:38:22.784019 progress 15 % (1 MB)
99 14:38:22.875748 progress 20 % (2 MB)
100 14:38:22.956027 progress 25 % (2 MB)
101 14:38:23.032260 progress 30 % (3 MB)
102 14:38:23.106671 progress 35 % (3 MB)
103 14:38:23.185898 progress 40 % (4 MB)
104 14:38:23.264129 progress 45 % (5 MB)
105 14:38:23.348300 progress 50 % (5 MB)
106 14:38:23.425567 progress 55 % (6 MB)
107 14:38:23.510314 progress 60 % (6 MB)
108 14:38:23.591471 progress 65 % (7 MB)
109 14:38:23.668138 progress 70 % (7 MB)
110 14:38:23.750558 progress 75 % (8 MB)
111 14:38:23.834213 progress 80 % (8 MB)
112 14:38:23.910238 progress 85 % (9 MB)
113 14:38:23.993497 progress 90 % (9 MB)
114 14:38:24.072439 progress 95 % (10 MB)
115 14:38:24.150342 progress 100 % (11 MB)
116 14:38:24.161827 11 MB downloaded in 1.66 s (6.65 MB/s)
117 14:38:24.163144 end: 1.4.1 http-download (duration 00:00:02) [common]
119 14:38:24.165685 end: 1.4 download-retry (duration 00:00:02) [common]
120 14:38:24.166539 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 14:38:24.167301 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 14:38:24.168119 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 14:38:24.168887 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 14:38:24.170339 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89
125 14:38:24.171474 makedir: /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin
126 14:38:24.172511 makedir: /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/tests
127 14:38:24.173487 makedir: /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/results
128 14:38:24.174419 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-add-keys
129 14:38:24.175848 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-add-sources
130 14:38:24.177354 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-background-process-start
131 14:38:24.178794 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-background-process-stop
132 14:38:24.180688 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-common-functions
133 14:38:24.182097 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-echo-ipv4
134 14:38:24.183471 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-install-packages
135 14:38:24.185088 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-installed-packages
136 14:38:24.186447 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-os-build
137 14:38:24.187785 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-probe-channel
138 14:38:24.189159 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-probe-ip
139 14:38:24.190540 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-target-ip
140 14:38:24.191931 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-target-mac
141 14:38:24.193312 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-target-storage
142 14:38:24.194676 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-test-case
143 14:38:24.196036 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-test-event
144 14:38:24.197368 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-test-feedback
145 14:38:24.198697 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-test-raise
146 14:38:24.200235 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-test-reference
147 14:38:24.201523 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-test-runner
148 14:38:24.202736 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-test-set
149 14:38:24.203945 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-test-shell
150 14:38:24.204743 Updating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-install-packages (oe)
151 14:38:24.205503 Updating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/bin/lava-installed-packages (oe)
152 14:38:24.206113 Creating /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/environment
153 14:38:24.206650 LAVA metadata
154 14:38:24.206989 - LAVA_JOB_ID=953550
155 14:38:24.207293 - LAVA_DISPATCHER_IP=192.168.6.2
156 14:38:24.207788 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 14:38:24.209160 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 14:38:24.209596 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 14:38:24.209880 skipped lava-vland-overlay
160 14:38:24.210203 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 14:38:24.210545 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 14:38:24.210843 skipped lava-multinode-overlay
163 14:38:24.211208 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 14:38:24.211548 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 14:38:24.211871 Loading test definitions
166 14:38:24.212337 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 14:38:24.212646 Using /lava-953550 at stage 0
168 14:38:24.214179 uuid=953550_1.5.2.4.1 testdef=None
169 14:38:24.214570 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 14:38:24.214968 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 14:38:24.217271 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 14:38:24.218306 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 14:38:24.221396 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 14:38:24.222449 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 14:38:24.225299 runner path: /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/0/tests/0_dmesg test_uuid 953550_1.5.2.4.1
178 14:38:24.226040 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 14:38:24.227024 Creating lava-test-runner.conf files
181 14:38:24.227298 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/953550/lava-overlay-go30ak89/lava-953550/0 for stage 0
182 14:38:24.227763 - 0_dmesg
183 14:38:24.228228 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 14:38:24.228642 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 14:38:24.256942 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 14:38:24.257373 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 14:38:24.257640 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 14:38:24.257911 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 14:38:24.258172 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 14:38:25.166896 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 14:38:25.167356 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 14:38:25.167605 extracting modules file /var/lib/lava/dispatcher/tmp/953550/tftp-deploy-18laxw67/modules/modules.tar to /var/lib/lava/dispatcher/tmp/953550/extract-overlay-ramdisk-gipoj7sn/ramdisk
193 14:38:26.474429 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 14:38:26.474916 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 14:38:26.475194 [common] Applying overlay /var/lib/lava/dispatcher/tmp/953550/compress-overlay-nmslcuse/overlay-1.5.2.5.tar.gz to ramdisk
196 14:38:26.475407 [common] Applying overlay /var/lib/lava/dispatcher/tmp/953550/compress-overlay-nmslcuse/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/953550/extract-overlay-ramdisk-gipoj7sn/ramdisk
197 14:38:26.505162 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 14:38:26.505586 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 14:38:26.505856 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 14:38:26.506084 Converting downloaded kernel to a uImage
201 14:38:26.506391 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/953550/tftp-deploy-18laxw67/kernel/Image /var/lib/lava/dispatcher/tmp/953550/tftp-deploy-18laxw67/kernel/uImage
202 14:38:26.960445 output: Image Name:
203 14:38:26.960874 output: Created: Thu Nov 7 14:38:26 2024
204 14:38:26.961087 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 14:38:26.961294 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 14:38:26.961498 output: Load Address: 01080000
207 14:38:26.961699 output: Entry Point: 01080000
208 14:38:26.961896 output:
209 14:38:26.962230 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 14:38:26.962495 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 14:38:26.962767 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 14:38:26.963022 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 14:38:26.963281 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 14:38:26.963545 Building ramdisk /var/lib/lava/dispatcher/tmp/953550/extract-overlay-ramdisk-gipoj7sn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/953550/extract-overlay-ramdisk-gipoj7sn/ramdisk
215 14:38:29.316336 >> 181575 blocks
216 14:38:37.726116 Adding RAMdisk u-boot header.
217 14:38:37.726783 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/953550/extract-overlay-ramdisk-gipoj7sn/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/953550/extract-overlay-ramdisk-gipoj7sn/ramdisk.cpio.gz.uboot
218 14:38:38.001125 output: Image Name:
219 14:38:38.001537 output: Created: Thu Nov 7 14:38:37 2024
220 14:38:38.001747 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 14:38:38.001952 output: Data Size: 26055175 Bytes = 25444.51 KiB = 24.85 MiB
222 14:38:38.002154 output: Load Address: 00000000
223 14:38:38.002354 output: Entry Point: 00000000
224 14:38:38.002550 output:
225 14:38:38.003261 rename /var/lib/lava/dispatcher/tmp/953550/extract-overlay-ramdisk-gipoj7sn/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/953550/tftp-deploy-18laxw67/ramdisk/ramdisk.cpio.gz.uboot
226 14:38:38.003693 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 14:38:38.003974 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 14:38:38.004605 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 14:38:38.005109 No LXC device requested
230 14:38:38.005655 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 14:38:38.006213 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 14:38:38.006757 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 14:38:38.007212 Checking files for TFTP limit of 4294967296 bytes.
234 14:38:38.010170 end: 1 tftp-deploy (duration 00:00:16) [common]
235 14:38:38.010804 start: 2 uboot-action (timeout 00:05:00) [common]
236 14:38:38.011377 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 14:38:38.011920 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 14:38:38.012540 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 14:38:38.013123 Using kernel file from prepare-kernel: 953550/tftp-deploy-18laxw67/kernel/uImage
240 14:38:38.013783 substitutions:
241 14:38:38.014232 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 14:38:38.014675 - {DTB_ADDR}: 0x01070000
243 14:38:38.015115 - {DTB}: 953550/tftp-deploy-18laxw67/dtb/meson-g12b-a311d-libretech-cc.dtb
244 14:38:38.015557 - {INITRD}: 953550/tftp-deploy-18laxw67/ramdisk/ramdisk.cpio.gz.uboot
245 14:38:38.016021 - {KERNEL_ADDR}: 0x01080000
246 14:38:38.016463 - {KERNEL}: 953550/tftp-deploy-18laxw67/kernel/uImage
247 14:38:38.016899 - {LAVA_MAC}: None
248 14:38:38.017444 - {PRESEED_CONFIG}: None
249 14:38:38.017927 - {PRESEED_LOCAL}: None
250 14:38:38.018383 - {RAMDISK_ADDR}: 0x08000000
251 14:38:38.018827 - {RAMDISK}: 953550/tftp-deploy-18laxw67/ramdisk/ramdisk.cpio.gz.uboot
252 14:38:38.019269 - {ROOT_PART}: None
253 14:38:38.019703 - {ROOT}: None
254 14:38:38.020171 - {SERVER_IP}: 192.168.6.2
255 14:38:38.020613 - {TEE_ADDR}: 0x83000000
256 14:38:38.021051 - {TEE}: None
257 14:38:38.021484 Parsed boot commands:
258 14:38:38.021904 - setenv autoload no
259 14:38:38.022335 - setenv initrd_high 0xffffffff
260 14:38:38.022765 - setenv fdt_high 0xffffffff
261 14:38:38.023195 - dhcp
262 14:38:38.023624 - setenv serverip 192.168.6.2
263 14:38:38.024077 - tftpboot 0x01080000 953550/tftp-deploy-18laxw67/kernel/uImage
264 14:38:38.024513 - tftpboot 0x08000000 953550/tftp-deploy-18laxw67/ramdisk/ramdisk.cpio.gz.uboot
265 14:38:38.024944 - tftpboot 0x01070000 953550/tftp-deploy-18laxw67/dtb/meson-g12b-a311d-libretech-cc.dtb
266 14:38:38.025375 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 14:38:38.025812 - bootm 0x01080000 0x08000000 0x01070000
268 14:38:38.026378 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 14:38:38.028064 start: 2.3 connect-device (timeout 00:05:00) [common]
271 14:38:38.028574 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 14:38:38.043768 Setting prompt string to ['lava-test: # ']
273 14:38:38.045408 end: 2.3 connect-device (duration 00:00:00) [common]
274 14:38:38.046077 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 14:38:38.046715 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 14:38:38.047289 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 14:38:38.048736 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 14:38:38.086349 >> OK - accepted request
279 14:38:38.088637 Returned 0 in 0 seconds
280 14:38:38.189871 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 14:38:38.191667 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 14:38:38.192341 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 14:38:38.192902 Setting prompt string to ['Hit any key to stop autoboot']
285 14:38:38.193396 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 14:38:38.195117 Trying 192.168.56.21...
287 14:38:38.195643 Connected to conserv1.
288 14:38:38.196137 Escape character is '^]'.
289 14:38:38.196607
290 14:38:38.197070 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 14:38:38.197543
292 14:38:49.930814 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
293 14:38:49.931481 bl2_stage_init 0x81
294 14:38:49.936337 hw id: 0x0000 - pwm id 0x01
295 14:38:49.936870 bl2_stage_init 0xc1
296 14:38:49.937352 bl2_stage_init 0x02
297 14:38:49.937820
298 14:38:49.941917 L0:00000000
299 14:38:49.942425 L1:20000703
300 14:38:49.942891 L2:00008067
301 14:38:49.943347 L3:14000000
302 14:38:49.943796 B2:00402000
303 14:38:49.944680 B1:e0f83180
304 14:38:49.945151
305 14:38:49.945597 TE: 58150
306 14:38:49.946031
307 14:38:49.955906 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
308 14:38:49.956424
309 14:38:49.956863 Board ID = 1
310 14:38:49.957290 Set A53 clk to 24M
311 14:38:49.957712 Set A73 clk to 24M
312 14:38:49.961535 Set clk81 to 24M
313 14:38:49.961994 A53 clk: 1200 MHz
314 14:38:49.962419 A73 clk: 1200 MHz
315 14:38:49.967114 CLK81: 166.6M
316 14:38:49.967580 smccc: 00012aac
317 14:38:49.972701 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
318 14:38:49.973164 board id: 1
319 14:38:49.981207 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
320 14:38:49.992013 fw parse done
321 14:38:49.997934 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
322 14:38:50.040601 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
323 14:38:50.051437 PIEI prepare done
324 14:38:50.051932 fastboot data load
325 14:38:50.052418 fastboot data verify
326 14:38:50.057268 verify result: 266
327 14:38:50.062755 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
328 14:38:50.063241 LPDDR4 probe
329 14:38:50.063673 ddr clk to 1584MHz
330 14:38:50.070696 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
331 14:38:50.107073
332 14:38:50.107630 dmc_version 0001
333 14:38:50.113864 Check phy result
334 14:38:50.120525 INFO : End of CA training
335 14:38:50.121021 INFO : End of initialization
336 14:38:50.126108 INFO : Training has run successfully!
337 14:38:50.126580 Check phy result
338 14:38:50.131751 INFO : End of initialization
339 14:38:50.132262 INFO : End of read enable training
340 14:38:50.137293 INFO : End of fine write leveling
341 14:38:50.142902 INFO : End of Write leveling coarse delay
342 14:38:50.143375 INFO : Training has run successfully!
343 14:38:50.143819 Check phy result
344 14:38:50.148527 INFO : End of initialization
345 14:38:50.149001 INFO : End of read dq deskew training
346 14:38:50.154145 INFO : End of MPR read delay center optimization
347 14:38:50.159749 INFO : End of write delay center optimization
348 14:38:50.165325 INFO : End of read delay center optimization
349 14:38:50.165798 INFO : End of max read latency training
350 14:38:50.170914 INFO : Training has run successfully!
351 14:38:50.171400 1D training succeed
352 14:38:50.179118 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
353 14:38:50.227685 Check phy result
354 14:38:50.228253 INFO : End of initialization
355 14:38:50.249261 INFO : End of 2D read delay Voltage center optimization
356 14:38:50.269354 INFO : End of 2D read delay Voltage center optimization
357 14:38:50.321326 INFO : End of 2D write delay Voltage center optimization
358 14:38:50.370480 INFO : End of 2D write delay Voltage center optimization
359 14:38:50.376085 INFO : Training has run successfully!
360 14:38:50.376578
361 14:38:50.377038 channel==0
362 14:38:50.381649 RxClkDly_Margin_A0==88 ps 9
363 14:38:50.382126 TxDqDly_Margin_A0==98 ps 10
364 14:38:50.387241 RxClkDly_Margin_A1==88 ps 9
365 14:38:50.387722 TxDqDly_Margin_A1==98 ps 10
366 14:38:50.388216 TrainedVREFDQ_A0==74
367 14:38:50.392834 TrainedVREFDQ_A1==74
368 14:38:50.393321 VrefDac_Margin_A0==25
369 14:38:50.393766 DeviceVref_Margin_A0==40
370 14:38:50.398448 VrefDac_Margin_A1==25
371 14:38:50.398915 DeviceVref_Margin_A1==40
372 14:38:50.399357
373 14:38:50.399798
374 14:38:50.404085 channel==1
375 14:38:50.404581 RxClkDly_Margin_A0==98 ps 10
376 14:38:50.405028 TxDqDly_Margin_A0==88 ps 9
377 14:38:50.409772 RxClkDly_Margin_A1==88 ps 9
378 14:38:50.410266 TxDqDly_Margin_A1==88 ps 9
379 14:38:50.415349 TrainedVREFDQ_A0==77
380 14:38:50.415855 TrainedVREFDQ_A1==77
381 14:38:50.416354 VrefDac_Margin_A0==22
382 14:38:50.420926 DeviceVref_Margin_A0==37
383 14:38:50.421400 VrefDac_Margin_A1==24
384 14:38:50.426453 DeviceVref_Margin_A1==37
385 14:38:50.426921
386 14:38:50.427366 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
387 14:38:50.427814
388 14:38:50.460083 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
389 14:38:50.460654 2D training succeed
390 14:38:50.465669 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
391 14:38:50.471293 auto size-- 65535DDR cs0 size: 2048MB
392 14:38:50.471772 DDR cs1 size: 2048MB
393 14:38:50.476860 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
394 14:38:50.477331 cs0 DataBus test pass
395 14:38:50.482466 cs1 DataBus test pass
396 14:38:50.482935 cs0 AddrBus test pass
397 14:38:50.483375 cs1 AddrBus test pass
398 14:38:50.483806
399 14:38:50.488067 100bdlr_step_size ps== 420
400 14:38:50.488543 result report
401 14:38:50.493629 boot times 0Enable ddr reg access
402 14:38:50.498882 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
403 14:38:50.512384 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
404 14:38:51.084462 0.0;M3 CHK:0;cm4_sp_mode 0
405 14:38:51.085137 MVN_1=0x00000000
406 14:38:51.089861 MVN_2=0x00000000
407 14:38:51.095591 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
408 14:38:51.096140 OPS=0x10
409 14:38:51.096615 ring efuse init
410 14:38:51.097067 chipver efuse init
411 14:38:51.101185 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
412 14:38:51.106817 [0.018961 Inits done]
413 14:38:51.107290 secure task start!
414 14:38:51.107734 high task start!
415 14:38:51.111402 low task start!
416 14:38:51.111870 run into bl31
417 14:38:51.118091 NOTICE: BL31: v1.3(release):4fc40b1
418 14:38:51.127309 NOTICE: BL31: Built : 15:58:17, May 22 2019
419 14:38:51.127784 NOTICE: BL31: G12A normal boot!
420 14:38:51.151199 NOTICE: BL31: BL33 decompress pass
421 14:38:51.156911 ERROR: Error initializing runtime service opteed_fast
422 14:38:52.390488
423 14:38:52.391153
424 14:38:52.398473 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
425 14:38:52.399004
426 14:38:52.399470 Model: Libre Computer AML-A311D-CC Alta
427 14:38:52.606905 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
428 14:38:52.630324 DRAM: 2 GiB (effective 3.8 GiB)
429 14:38:52.773368 Core: 408 devices, 31 uclasses, devicetree: separate
430 14:38:52.779089 WDT: Not starting watchdog@f0d0
431 14:38:52.811173 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
432 14:38:52.823724 Loading Environment from FAT... Card did not respond to voltage select! : -110
433 14:38:52.828692 ** Bad device specification mmc 0 **
434 14:38:52.839044 Card did not respond to voltage select! : -110
435 14:38:52.846736 ** Bad device specification mmc 0 **
436 14:38:52.847206 Couldn't find partition mmc 0
437 14:38:52.855119 Card did not respond to voltage select! : -110
438 14:38:52.860637 ** Bad device specification mmc 0 **
439 14:38:52.861110 Couldn't find partition mmc 0
440 14:38:52.865624 Error: could not access storage.
441 14:38:54.131492 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
442 14:38:54.131904 bl2_stage_init 0x81
443 14:38:54.136994 hw id: 0x0000 - pwm id 0x01
444 14:38:54.137300 bl2_stage_init 0xc1
445 14:38:54.137517 bl2_stage_init 0x02
446 14:38:54.137724
447 14:38:54.142657 L0:00000000
448 14:38:54.143085 L1:20000703
449 14:38:54.143447 L2:00008067
450 14:38:54.143796 L3:14000000
451 14:38:54.144210 B2:00402000
452 14:38:54.145416 B1:e0f83180
453 14:38:54.145805
454 14:38:54.146069 TE: 58150
455 14:38:54.146292
456 14:38:54.156666 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
457 14:38:54.157182
458 14:38:54.157561 Board ID = 1
459 14:38:54.157920 Set A53 clk to 24M
460 14:38:54.158291 Set A73 clk to 24M
461 14:38:54.162125 Set clk81 to 24M
462 14:38:54.162426 A53 clk: 1200 MHz
463 14:38:54.162650 A73 clk: 1200 MHz
464 14:38:54.165734 CLK81: 166.6M
465 14:38:54.166158 smccc: 00012aac
466 14:38:54.171392 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
467 14:38:54.176874 board id: 1
468 14:38:54.182077 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
469 14:38:54.192497 fw parse done
470 14:38:54.197456 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
471 14:38:54.240458 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
472 14:38:54.252074 PIEI prepare done
473 14:38:54.252579 fastboot data load
474 14:38:54.252863 fastboot data verify
475 14:38:54.257690 verify result: 266
476 14:38:54.263238 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
477 14:38:54.263547 LPDDR4 probe
478 14:38:54.263774 ddr clk to 1584MHz
479 14:38:54.271258 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
480 14:38:54.308477
481 14:38:54.308998 dmc_version 0001
482 14:38:54.315199 Check phy result
483 14:38:54.321023 INFO : End of CA training
484 14:38:54.321321 INFO : End of initialization
485 14:38:54.326599 INFO : Training has run successfully!
486 14:38:54.327033 Check phy result
487 14:38:54.332226 INFO : End of initialization
488 14:38:54.332545 INFO : End of read enable training
489 14:38:54.337776 INFO : End of fine write leveling
490 14:38:54.343397 INFO : End of Write leveling coarse delay
491 14:38:54.343858 INFO : Training has run successfully!
492 14:38:54.344155 Check phy result
493 14:38:54.349035 INFO : End of initialization
494 14:38:54.349520 INFO : End of read dq deskew training
495 14:38:54.354782 INFO : End of MPR read delay center optimization
496 14:38:54.360276 INFO : End of write delay center optimization
497 14:38:54.365921 INFO : End of read delay center optimization
498 14:38:54.366426 INFO : End of max read latency training
499 14:38:54.371476 INFO : Training has run successfully!
500 14:38:54.371935 1D training succeed
501 14:38:54.380597 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 14:38:54.428576 Check phy result
503 14:38:54.428967 INFO : End of initialization
504 14:38:54.451400 INFO : End of 2D read delay Voltage center optimization
505 14:38:54.470039 INFO : End of 2D read delay Voltage center optimization
506 14:38:54.522020 INFO : End of 2D write delay Voltage center optimization
507 14:38:54.571229 INFO : End of 2D write delay Voltage center optimization
508 14:38:54.576752 INFO : Training has run successfully!
509 14:38:54.577343
510 14:38:54.577822 channel==0
511 14:38:54.583202 RxClkDly_Margin_A0==88 ps 9
512 14:38:54.583683 TxDqDly_Margin_A0==98 ps 10
513 14:38:54.587889 RxClkDly_Margin_A1==88 ps 9
514 14:38:54.588488 TxDqDly_Margin_A1==88 ps 9
515 14:38:54.588951 TrainedVREFDQ_A0==74
516 14:38:54.593514 TrainedVREFDQ_A1==74
517 14:38:54.594049 VrefDac_Margin_A0==25
518 14:38:54.594470 DeviceVref_Margin_A0==40
519 14:38:54.598998 VrefDac_Margin_A1==25
520 14:38:54.599467 DeviceVref_Margin_A1==40
521 14:38:54.599870
522 14:38:54.600314
523 14:38:54.600716 channel==1
524 14:38:54.604572 RxClkDly_Margin_A0==98 ps 10
525 14:38:54.605018 TxDqDly_Margin_A0==88 ps 9
526 14:38:54.610547 RxClkDly_Margin_A1==98 ps 10
527 14:38:54.611017 TxDqDly_Margin_A1==88 ps 9
528 14:38:54.615908 TrainedVREFDQ_A0==77
529 14:38:54.616403 TrainedVREFDQ_A1==77
530 14:38:54.616810 VrefDac_Margin_A0==22
531 14:38:54.621542 DeviceVref_Margin_A0==37
532 14:38:54.621992 VrefDac_Margin_A1==22
533 14:38:54.627074 DeviceVref_Margin_A1==37
534 14:38:54.627529
535 14:38:54.627940 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
536 14:38:54.628387
537 14:38:54.660763 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
538 14:38:54.661363 2D training succeed
539 14:38:54.666488 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
540 14:38:54.671963 auto size-- 65535DDR cs0 size: 2048MB
541 14:38:54.672590 DDR cs1 size: 2048MB
542 14:38:54.677534 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
543 14:38:54.678076 cs0 DataBus test pass
544 14:38:54.683173 cs1 DataBus test pass
545 14:38:54.683714 cs0 AddrBus test pass
546 14:38:54.684237 cs1 AddrBus test pass
547 14:38:54.684694
548 14:38:54.688736 100bdlr_step_size ps== 420
549 14:38:54.689275 result report
550 14:38:54.694406 boot times 0Enable ddr reg access
551 14:38:54.699520 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
552 14:38:54.712914 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
553 14:38:55.284931 0.0;M3 CHK:0;cm4_sp_mode 0
554 14:38:55.288092 MVN_1=0x00000000
555 14:38:55.290478 MVN_2=0x00000000
556 14:38:55.296215 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
557 14:38:55.296545 OPS=0x10
558 14:38:55.296755 ring efuse init
559 14:38:55.296954 chipver efuse init
560 14:38:55.301784 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
561 14:38:55.307420 [0.018961 Inits done]
562 14:38:55.307953 secure task start!
563 14:38:55.308401 high task start!
564 14:38:55.311974 low task start!
565 14:38:55.312475 run into bl31
566 14:38:55.318656 NOTICE: BL31: v1.3(release):4fc40b1
567 14:38:55.326496 NOTICE: BL31: Built : 15:58:17, May 22 2019
568 14:38:55.327023 NOTICE: BL31: G12A normal boot!
569 14:38:55.351932 NOTICE: BL31: BL33 decompress pass
570 14:38:55.357541 ERROR: Error initializing runtime service opteed_fast
571 14:38:56.590282
572 14:38:56.590698
573 14:38:56.598700 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
574 14:38:56.599014
575 14:38:56.599239 Model: Libre Computer AML-A311D-CC Alta
576 14:38:56.807142 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
577 14:38:56.830544 DRAM: 2 GiB (effective 3.8 GiB)
578 14:38:56.973544 Core: 408 devices, 31 uclasses, devicetree: separate
579 14:38:56.979390 WDT: Not starting watchdog@f0d0
580 14:38:57.011701 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
581 14:38:57.024128 Loading Environment from FAT... Card did not respond to voltage select! : -110
582 14:38:57.029116 ** Bad device specification mmc 0 **
583 14:38:57.039499 Card did not respond to voltage select! : -110
584 14:38:57.047100 ** Bad device specification mmc 0 **
585 14:38:57.047417 Couldn't find partition mmc 0
586 14:38:57.055487 Card did not respond to voltage select! : -110
587 14:38:57.060930 ** Bad device specification mmc 0 **
588 14:38:57.061231 Couldn't find partition mmc 0
589 14:38:57.066024 Error: could not access storage.
590 14:38:57.408486 Net: eth0: ethernet@ff3f0000
591 14:38:57.408904 starting USB...
592 14:38:57.660296 Bus usb@ff500000: Register 3000140 NbrPorts 3
593 14:38:57.660716 Starting the controller
594 14:38:57.667281 USB XHCI 1.10
595 14:38:59.291526 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
596 14:38:59.292169 bl2_stage_init 0x01
597 14:38:59.292460 bl2_stage_init 0x81
598 14:38:59.297038 hw id: 0x0000 - pwm id 0x01
599 14:38:59.297511 bl2_stage_init 0xc1
600 14:38:59.297772 bl2_stage_init 0x02
601 14:38:59.298022
602 14:38:59.302595 L0:00000000
603 14:38:59.302917 L1:20000703
604 14:38:59.303157 L2:00008067
605 14:38:59.303409 L3:14000000
606 14:38:59.308188 B2:00402000
607 14:38:59.308521 B1:e0f83180
608 14:38:59.308761
609 14:38:59.308990 TE: 58150
610 14:38:59.309434
611 14:38:59.313872 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
612 14:38:59.314208
613 14:38:59.314450 Board ID = 1
614 14:38:59.319487 Set A53 clk to 24M
615 14:38:59.319969 Set A73 clk to 24M
616 14:38:59.320410 Set clk81 to 24M
617 14:38:59.325051 A53 clk: 1200 MHz
618 14:38:59.325455 A73 clk: 1200 MHz
619 14:38:59.325681 CLK81: 166.6M
620 14:38:59.325907 smccc: 00012aac
621 14:38:59.330667 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
622 14:38:59.336226 board id: 1
623 14:38:59.342176 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
624 14:38:59.352780 fw parse done
625 14:38:59.358761 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
626 14:38:59.401263 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
627 14:38:59.412246 PIEI prepare done
628 14:38:59.412823 fastboot data load
629 14:38:59.413106 fastboot data verify
630 14:38:59.417813 verify result: 266
631 14:38:59.423403 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
632 14:38:59.423745 LPDDR4 probe
633 14:38:59.424013 ddr clk to 1584MHz
634 14:38:59.431358 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
635 14:38:59.468704
636 14:38:59.469133 dmc_version 0001
637 14:38:59.475357 Check phy result
638 14:38:59.481202 INFO : End of CA training
639 14:38:59.481738 INFO : End of initialization
640 14:38:59.486813 INFO : Training has run successfully!
641 14:38:59.487178 Check phy result
642 14:38:59.492411 INFO : End of initialization
643 14:38:59.492776 INFO : End of read enable training
644 14:38:59.498462 INFO : End of fine write leveling
645 14:38:59.503584 INFO : End of Write leveling coarse delay
646 14:38:59.504085 INFO : Training has run successfully!
647 14:38:59.504359 Check phy result
648 14:38:59.509167 INFO : End of initialization
649 14:38:59.509641 INFO : End of read dq deskew training
650 14:38:59.514858 INFO : End of MPR read delay center optimization
651 14:38:59.520379 INFO : End of write delay center optimization
652 14:38:59.526038 INFO : End of read delay center optimization
653 14:38:59.526637 INFO : End of max read latency training
654 14:38:59.531591 INFO : Training has run successfully!
655 14:38:59.532204 1D training succeed
656 14:38:59.540820 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
657 14:38:59.588441 Check phy result
658 14:38:59.589090 INFO : End of initialization
659 14:38:59.610121 INFO : End of 2D read delay Voltage center optimization
660 14:38:59.630299 INFO : End of 2D read delay Voltage center optimization
661 14:38:59.682062 INFO : End of 2D write delay Voltage center optimization
662 14:38:59.731262 INFO : End of 2D write delay Voltage center optimization
663 14:38:59.736775 INFO : Training has run successfully!
664 14:38:59.737374
665 14:38:59.737856 channel==0
666 14:38:59.742370 RxClkDly_Margin_A0==88 ps 9
667 14:38:59.742951 TxDqDly_Margin_A0==98 ps 10
668 14:38:59.747934 RxClkDly_Margin_A1==88 ps 9
669 14:38:59.748549 TxDqDly_Margin_A1==98 ps 10
670 14:38:59.749032 TrainedVREFDQ_A0==74
671 14:38:59.753559 TrainedVREFDQ_A1==75
672 14:38:59.754137 VrefDac_Margin_A0==25
673 14:38:59.754609 DeviceVref_Margin_A0==40
674 14:38:59.759170 VrefDac_Margin_A1==25
675 14:38:59.759733 DeviceVref_Margin_A1==39
676 14:38:59.760242
677 14:38:59.760707
678 14:38:59.764786 channel==1
679 14:38:59.765346 RxClkDly_Margin_A0==98 ps 10
680 14:38:59.765806 TxDqDly_Margin_A0==98 ps 10
681 14:38:59.770365 RxClkDly_Margin_A1==88 ps 9
682 14:38:59.770925 TxDqDly_Margin_A1==88 ps 9
683 14:38:59.775964 TrainedVREFDQ_A0==77
684 14:38:59.776561 TrainedVREFDQ_A1==77
685 14:38:59.777033 VrefDac_Margin_A0==22
686 14:38:59.781577 DeviceVref_Margin_A0==37
687 14:38:59.782138 VrefDac_Margin_A1==24
688 14:38:59.787148 DeviceVref_Margin_A1==37
689 14:38:59.787727
690 14:38:59.788290 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
691 14:38:59.788785
692 14:38:59.820888 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
693 14:38:59.821549 2D training succeed
694 14:38:59.826494 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
695 14:38:59.832099 auto size-- 65535DDR cs0 size: 2048MB
696 14:38:59.832684 DDR cs1 size: 2048MB
697 14:38:59.837673 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
698 14:38:59.838246 cs0 DataBus test pass
699 14:38:59.843266 cs1 DataBus test pass
700 14:38:59.843833 cs0 AddrBus test pass
701 14:38:59.844338 cs1 AddrBus test pass
702 14:38:59.844787
703 14:38:59.848906 100bdlr_step_size ps== 420
704 14:38:59.849482 result report
705 14:38:59.854496 boot times 0Enable ddr reg access
706 14:38:59.859823 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
707 14:38:59.873362 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
708 14:39:00.445615 0.0;M3 CHK:0;cm4_sp_mode 0
709 14:39:00.446314 MVN_1=0x00000000
710 14:39:00.450663 MVN_2=0x00000000
711 14:39:00.456410 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
712 14:39:00.456728 OPS=0x10
713 14:39:00.456948 ring efuse init
714 14:39:00.457159 chipver efuse init
715 14:39:00.464554 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
716 14:39:00.464905 [0.018961 Inits done]
717 14:39:00.472218 secure task start!
718 14:39:00.472566 high task start!
719 14:39:00.472806 low task start!
720 14:39:00.473040 run into bl31
721 14:39:00.478868 NOTICE: BL31: v1.3(release):4fc40b1
722 14:39:00.486678 NOTICE: BL31: Built : 15:58:17, May 22 2019
723 14:39:00.487038 NOTICE: BL31: G12A normal boot!
724 14:39:00.512064 NOTICE: BL31: BL33 decompress pass
725 14:39:00.517703 ERROR: Error initializing runtime service opteed_fast
726 14:39:01.750495
727 14:39:01.750926
728 14:39:01.758910 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
729 14:39:01.759254
730 14:39:01.759472 Model: Libre Computer AML-A311D-CC Alta
731 14:39:01.966386 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
732 14:39:01.990735 DRAM: 2 GiB (effective 3.8 GiB)
733 14:39:02.133712 Core: 408 devices, 31 uclasses, devicetree: separate
734 14:39:02.139580 WDT: Not starting watchdog@f0d0
735 14:39:02.171871 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
736 14:39:02.184350 Loading Environment from FAT... Card did not respond to voltage select! : -110
737 14:39:02.189337 ** Bad device specification mmc 0 **
738 14:39:02.199631 Card did not respond to voltage select! : -110
739 14:39:02.207265 ** Bad device specification mmc 0 **
740 14:39:02.207567 Couldn't find partition mmc 0
741 14:39:02.215571 Card did not respond to voltage select! : -110
742 14:39:02.221076 ** Bad device specification mmc 0 **
743 14:39:02.221369 Couldn't find partition mmc 0
744 14:39:02.226127 Error: could not access storage.
745 14:39:02.568724 Net: eth0: ethernet@ff3f0000
746 14:39:02.569149 starting USB...
747 14:39:02.820581 Bus usb@ff500000: Register 3000140 NbrPorts 3
748 14:39:02.820992 Starting the controller
749 14:39:02.827496 USB XHCI 1.10
750 14:39:04.993057 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
751 14:39:04.993508 bl2_stage_init 0x01
752 14:39:04.993750 bl2_stage_init 0x81
753 14:39:04.998712 hw id: 0x0000 - pwm id 0x01
754 14:39:04.999114 bl2_stage_init 0xc1
755 14:39:04.999336 bl2_stage_init 0x02
756 14:39:04.999550
757 14:39:05.004315 L0:00000000
758 14:39:05.004701 L1:20000703
759 14:39:05.004918 L2:00008067
760 14:39:05.005201 L3:14000000
761 14:39:05.009980 B2:00402000
762 14:39:05.010388 B1:e0f83180
763 14:39:05.010610
764 14:39:05.010904 TE: 58167
765 14:39:05.011129
766 14:39:05.015487 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
767 14:39:05.015892
768 14:39:05.016264 Board ID = 1
769 14:39:05.021051 Set A53 clk to 24M
770 14:39:05.021437 Set A73 clk to 24M
771 14:39:05.021654 Set clk81 to 24M
772 14:39:05.026704 A53 clk: 1200 MHz
773 14:39:05.027148 A73 clk: 1200 MHz
774 14:39:05.027419 CLK81: 166.6M
775 14:39:05.027651 smccc: 00012abd
776 14:39:05.032263 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
777 14:39:05.037914 board id: 1
778 14:39:05.043901 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
779 14:39:05.054495 fw parse done
780 14:39:05.060445 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
781 14:39:05.102869 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
782 14:39:05.113796 PIEI prepare done
783 14:39:05.114171 fastboot data load
784 14:39:05.114443 fastboot data verify
785 14:39:05.119841 verify result: 266
786 14:39:05.125020 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
787 14:39:05.125385 LPDDR4 probe
788 14:39:05.125589 ddr clk to 1584MHz
789 14:39:05.132515 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
790 14:39:05.170311
791 14:39:05.170753 dmc_version 0001
792 14:39:05.176955 Check phy result
793 14:39:05.182912 INFO : End of CA training
794 14:39:05.183250 INFO : End of initialization
795 14:39:05.188468 INFO : Training has run successfully!
796 14:39:05.188789 Check phy result
797 14:39:05.193994 INFO : End of initialization
798 14:39:05.194291 INFO : End of read enable training
799 14:39:05.199596 INFO : End of fine write leveling
800 14:39:05.205244 INFO : End of Write leveling coarse delay
801 14:39:05.205579 INFO : Training has run successfully!
802 14:39:05.205789 Check phy result
803 14:39:05.210818 INFO : End of initialization
804 14:39:05.211133 INFO : End of read dq deskew training
805 14:39:05.216500 INFO : End of MPR read delay center optimization
806 14:39:05.222417 INFO : End of write delay center optimization
807 14:39:05.228201 INFO : End of read delay center optimization
808 14:39:05.228817 INFO : End of max read latency training
809 14:39:05.233205 INFO : Training has run successfully!
810 14:39:05.233719 1D training succeed
811 14:39:05.242506 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
812 14:39:05.290151 Check phy result
813 14:39:05.290821 INFO : End of initialization
814 14:39:05.311768 INFO : End of 2D read delay Voltage center optimization
815 14:39:05.331774 INFO : End of 2D read delay Voltage center optimization
816 14:39:05.383825 INFO : End of 2D write delay Voltage center optimization
817 14:39:05.433125 INFO : End of 2D write delay Voltage center optimization
818 14:39:05.438412 INFO : Training has run successfully!
819 14:39:05.439032
820 14:39:05.439492 channel==0
821 14:39:05.444075 RxClkDly_Margin_A0==88 ps 9
822 14:39:05.444696 TxDqDly_Margin_A0==98 ps 10
823 14:39:05.447270 RxClkDly_Margin_A1==88 ps 9
824 14:39:05.447823 TxDqDly_Margin_A1==98 ps 10
825 14:39:05.453020 TrainedVREFDQ_A0==74
826 14:39:05.453628 TrainedVREFDQ_A1==74
827 14:39:05.458470 VrefDac_Margin_A0==25
828 14:39:05.459030 DeviceVref_Margin_A0==40
829 14:39:05.459474 VrefDac_Margin_A1==25
830 14:39:05.464187 DeviceVref_Margin_A1==40
831 14:39:05.464770
832 14:39:05.465253
833 14:39:05.465701 channel==1
834 14:39:05.466135 RxClkDly_Margin_A0==98 ps 10
835 14:39:05.467378 TxDqDly_Margin_A0==98 ps 10
836 14:39:05.473077 RxClkDly_Margin_A1==88 ps 9
837 14:39:05.473658 TxDqDly_Margin_A1==88 ps 9
838 14:39:05.474104 TrainedVREFDQ_A0==77
839 14:39:05.478668 TrainedVREFDQ_A1==77
840 14:39:05.479279 VrefDac_Margin_A0==22
841 14:39:05.484198 DeviceVref_Margin_A0==37
842 14:39:05.484773 VrefDac_Margin_A1==24
843 14:39:05.485215 DeviceVref_Margin_A1==37
844 14:39:05.485647
845 14:39:05.493205 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
846 14:39:05.493812
847 14:39:05.521710 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
848 14:39:05.522399 2D training succeed
849 14:39:05.532337 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
850 14:39:05.532947 auto size-- 65535DDR cs0 size: 2048MB
851 14:39:05.533351 DDR cs1 size: 2048MB
852 14:39:05.537856 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
853 14:39:05.538432 cs0 DataBus test pass
854 14:39:05.543452 cs1 DataBus test pass
855 14:39:05.543801 cs0 AddrBus test pass
856 14:39:05.549128 cs1 AddrBus test pass
857 14:39:05.549522
858 14:39:05.549780 100bdlr_step_size ps== 420
859 14:39:05.550028 result report
860 14:39:05.554808 boot times 0Enable ddr reg access
861 14:39:05.561305 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
862 14:39:05.573864 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
863 14:39:06.146797 0.0;M3 CHK:0;cm4_sp_mode 0
864 14:39:06.147487 MVN_1=0x00000000
865 14:39:06.152317 MVN_2=0x00000000
866 14:39:06.158132 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
867 14:39:06.158805 OPS=0x10
868 14:39:06.159429 ring efuse init
869 14:39:06.159953 chipver efuse init
870 14:39:06.163715 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
871 14:39:06.169246 [0.018961 Inits done]
872 14:39:06.169853 secure task start!
873 14:39:06.170282 high task start!
874 14:39:06.173923 low task start!
875 14:39:06.174550 run into bl31
876 14:39:06.180500 NOTICE: BL31: v1.3(release):4fc40b1
877 14:39:06.187499 NOTICE: BL31: Built : 15:58:17, May 22 2019
878 14:39:06.187972 NOTICE: BL31: G12A normal boot!
879 14:39:06.213584 NOTICE: BL31: BL33 decompress pass
880 14:39:06.219360 ERROR: Error initializing runtime service opteed_fast
881 14:39:07.452256
882 14:39:07.452982
883 14:39:07.459602 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
884 14:39:07.460213
885 14:39:07.460681 Model: Libre Computer AML-A311D-CC Alta
886 14:39:07.668764 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
887 14:39:07.692340 DRAM: 2 GiB (effective 3.8 GiB)
888 14:39:07.835333 Core: 408 devices, 31 uclasses, devicetree: separate
889 14:39:07.840226 WDT: Not starting watchdog@f0d0
890 14:39:07.873400 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
891 14:39:07.885851 Loading Environment from FAT... Card did not respond to voltage select! : -110
892 14:39:07.889883 ** Bad device specification mmc 0 **
893 14:39:07.901135 Card did not respond to voltage select! : -110
894 14:39:07.908797 ** Bad device specification mmc 0 **
895 14:39:07.909138 Couldn't find partition mmc 0
896 14:39:07.917208 Card did not respond to voltage select! : -110
897 14:39:07.922728 ** Bad device specification mmc 0 **
898 14:39:07.923235 Couldn't find partition mmc 0
899 14:39:07.927131 Error: could not access storage.
900 14:39:08.270261 Net: eth0: ethernet@ff3f0000
901 14:39:08.270668 starting USB...
902 14:39:08.522004 Bus usb@ff500000: Register 3000140 NbrPorts 3
903 14:39:08.522424 Starting the controller
904 14:39:08.528966 USB XHCI 1.10
905 14:39:10.392879 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
906 14:39:10.393299 bl2_stage_init 0x01
907 14:39:10.393521 bl2_stage_init 0x81
908 14:39:10.398455 hw id: 0x0000 - pwm id 0x01
909 14:39:10.398772 bl2_stage_init 0xc1
910 14:39:10.398990 bl2_stage_init 0x02
911 14:39:10.399195
912 14:39:10.404092 L0:00000000
913 14:39:10.404409 L1:20000703
914 14:39:10.404631 L2:00008067
915 14:39:10.404839 L3:14000000
916 14:39:10.409654 B2:00402000
917 14:39:10.409965 B1:e0f83180
918 14:39:10.410175
919 14:39:10.410391 TE: 58124
920 14:39:10.410596
921 14:39:10.415267 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
922 14:39:10.415635
923 14:39:10.415860 Board ID = 1
924 14:39:10.420841 Set A53 clk to 24M
925 14:39:10.421166 Set A73 clk to 24M
926 14:39:10.421381 Set clk81 to 24M
927 14:39:10.426486 A53 clk: 1200 MHz
928 14:39:10.426802 A73 clk: 1200 MHz
929 14:39:10.427014 CLK81: 166.6M
930 14:39:10.427217 smccc: 00012a92
931 14:39:10.432124 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
932 14:39:10.438076 board id: 1
933 14:39:10.443808 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
934 14:39:10.454050 fw parse done
935 14:39:10.460062 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
936 14:39:10.501730 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
937 14:39:10.513627 PIEI prepare done
938 14:39:10.514385 fastboot data load
939 14:39:10.514930 fastboot data verify
940 14:39:10.519205 verify result: 266
941 14:39:10.524842 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
942 14:39:10.525462 LPDDR4 probe
943 14:39:10.525976 ddr clk to 1584MHz
944 14:39:10.532781 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
945 14:39:10.570143
946 14:39:10.570830 dmc_version 0001
947 14:39:10.576707 Check phy result
948 14:39:10.582638 INFO : End of CA training
949 14:39:10.583237 INFO : End of initialization
950 14:39:10.588248 INFO : Training has run successfully!
951 14:39:10.588814 Check phy result
952 14:39:10.593763 INFO : End of initialization
953 14:39:10.594339 INFO : End of read enable training
954 14:39:10.599421 INFO : End of fine write leveling
955 14:39:10.604943 INFO : End of Write leveling coarse delay
956 14:39:10.605522 INFO : Training has run successfully!
957 14:39:10.606033 Check phy result
958 14:39:10.610574 INFO : End of initialization
959 14:39:10.611161 INFO : End of read dq deskew training
960 14:39:10.616207 INFO : End of MPR read delay center optimization
961 14:39:10.621804 INFO : End of write delay center optimization
962 14:39:10.627482 INFO : End of read delay center optimization
963 14:39:10.628167 INFO : End of max read latency training
964 14:39:10.632922 INFO : Training has run successfully!
965 14:39:10.633522 1D training succeed
966 14:39:10.641231 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
967 14:39:10.689809 Check phy result
968 14:39:10.690555 INFO : End of initialization
969 14:39:10.711563 INFO : End of 2D read delay Voltage center optimization
970 14:39:10.730937 INFO : End of 2D read delay Voltage center optimization
971 14:39:10.783790 INFO : End of 2D write delay Voltage center optimization
972 14:39:10.833286 INFO : End of 2D write delay Voltage center optimization
973 14:39:10.838750 INFO : Training has run successfully!
974 14:39:10.839346
975 14:39:10.839884 channel==0
976 14:39:10.844391 RxClkDly_Margin_A0==88 ps 9
977 14:39:10.845055 TxDqDly_Margin_A0==98 ps 10
978 14:39:10.847599 RxClkDly_Margin_A1==88 ps 9
979 14:39:10.848211 TxDqDly_Margin_A1==98 ps 10
980 14:39:10.853161 TrainedVREFDQ_A0==74
981 14:39:10.853743 TrainedVREFDQ_A1==74
982 14:39:10.858763 VrefDac_Margin_A0==25
983 14:39:10.859324 DeviceVref_Margin_A0==40
984 14:39:10.859835 VrefDac_Margin_A1==25
985 14:39:10.864373 DeviceVref_Margin_A1==40
986 14:39:10.864926
987 14:39:10.865433
988 14:39:10.865938 channel==1
989 14:39:10.866438 RxClkDly_Margin_A0==98 ps 10
990 14:39:10.867687 TxDqDly_Margin_A0==98 ps 10
991 14:39:10.873357 RxClkDly_Margin_A1==98 ps 10
992 14:39:10.873899 TxDqDly_Margin_A1==88 ps 9
993 14:39:10.878873 TrainedVREFDQ_A0==77
994 14:39:10.879387 TrainedVREFDQ_A1==77
995 14:39:10.879819 VrefDac_Margin_A0==22
996 14:39:10.884550 DeviceVref_Margin_A0==37
997 14:39:10.885289 VrefDac_Margin_A1==22
998 14:39:10.885834 DeviceVref_Margin_A1==37
999 14:39:10.886415
1000 14:39:10.890111 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1001 14:39:10.890741
1002 14:39:10.923689 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
1003 14:39:10.924482 2D training succeed
1004 14:39:10.929295 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1005 14:39:10.934927 auto size-- 65535DDR cs0 size: 2048MB
1006 14:39:10.935599 DDR cs1 size: 2048MB
1007 14:39:10.940516 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1008 14:39:10.941109 cs0 DataBus test pass
1009 14:39:10.941625 cs1 DataBus test pass
1010 14:39:10.946086 cs0 AddrBus test pass
1011 14:39:10.946679 cs1 AddrBus test pass
1012 14:39:10.947192
1013 14:39:10.951698 100bdlr_step_size ps== 420
1014 14:39:10.952380 result report
1015 14:39:10.952910 boot times 0Enable ddr reg access
1016 14:39:10.961766 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1017 14:39:10.975302 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1018 14:39:11.548972 0.0;M3 CHK:0;cm4_sp_mode 0
1019 14:39:11.549413 MVN_1=0x00000000
1020 14:39:11.554436 MVN_2=0x00000000
1021 14:39:11.560159 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1022 14:39:11.560493 OPS=0x10
1023 14:39:11.560713 ring efuse init
1024 14:39:11.560919 chipver efuse init
1025 14:39:11.565791 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1026 14:39:11.571428 [0.018960 Inits done]
1027 14:39:11.571776 secure task start!
1028 14:39:11.572027 high task start!
1029 14:39:11.575924 low task start!
1030 14:39:11.576245 run into bl31
1031 14:39:11.582630 NOTICE: BL31: v1.3(release):4fc40b1
1032 14:39:11.590405 NOTICE: BL31: Built : 15:58:17, May 22 2019
1033 14:39:11.590857 NOTICE: BL31: G12A normal boot!
1034 14:39:11.615917 NOTICE: BL31: BL33 decompress pass
1035 14:39:11.621648 ERROR: Error initializing runtime service opteed_fast
1036 14:39:12.854446
1037 14:39:12.854841
1038 14:39:12.862928 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1039 14:39:12.863343
1040 14:39:12.863675 Model: Libre Computer AML-A311D-CC Alta
1041 14:39:13.071355 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1042 14:39:13.094733 DRAM: 2 GiB (effective 3.8 GiB)
1043 14:39:13.237701 Core: 408 devices, 31 uclasses, devicetree: separate
1044 14:39:13.243508 WDT: Not starting watchdog@f0d0
1045 14:39:13.275845 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1046 14:39:13.288333 Loading Environment from FAT... Card did not respond to voltage select! : -110
1047 14:39:13.293199 ** Bad device specification mmc 0 **
1048 14:39:13.303551 Card did not respond to voltage select! : -110
1049 14:39:13.311211 ** Bad device specification mmc 0 **
1050 14:39:13.311652 Couldn't find partition mmc 0
1051 14:39:13.319531 Card did not respond to voltage select! : -110
1052 14:39:13.325038 ** Bad device specification mmc 0 **
1053 14:39:13.325468 Couldn't find partition mmc 0
1054 14:39:13.330144 Error: could not access storage.
1055 14:39:13.672554 Net: eth0: ethernet@ff3f0000
1056 14:39:13.673150 starting USB...
1057 14:39:13.924442 Bus usb@ff500000: Register 3000140 NbrPorts 3
1058 14:39:13.925052 Starting the controller
1059 14:39:13.931337 USB XHCI 1.10
1060 14:39:15.485785 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1061 14:39:15.493919 scanning usb for storage devices... 0 Storage Device(s) found
1063 14:39:15.545595 Hit any key to stop autoboot: 1
1064 14:39:15.546418 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1065 14:39:15.546862 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1066 14:39:15.547206 Setting prompt string to ['=>']
1067 14:39:15.547614 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1068 14:39:15.561670 0
1069 14:39:15.562650 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1070 14:39:15.563087 Sending with 10 millisecond of delay
1072 14:39:16.698273 => setenv autoload no
1073 14:39:16.709273 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1074 14:39:16.715602 setenv autoload no
1075 14:39:16.716562 Sending with 10 millisecond of delay
1077 14:39:18.514352 => setenv initrd_high 0xffffffff
1078 14:39:18.525042 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1079 14:39:18.525753 setenv initrd_high 0xffffffff
1080 14:39:18.526338 Sending with 10 millisecond of delay
1082 14:39:20.143529 => setenv fdt_high 0xffffffff
1083 14:39:20.154381 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1084 14:39:20.155280 setenv fdt_high 0xffffffff
1085 14:39:20.156066 Sending with 10 millisecond of delay
1087 14:39:20.448031 => dhcp
1088 14:39:20.458821 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1089 14:39:20.459712 dhcp
1090 14:39:20.460219 Speed: 1000, full duplex
1091 14:39:20.460670 BOOTP broadcast 1
1092 14:39:20.635122 DHCP client bound to address 192.168.6.27 (176 ms)
1093 14:39:20.636043 Sending with 10 millisecond of delay
1095 14:39:22.312669 => setenv serverip 192.168.6.2
1096 14:39:22.323478 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1097 14:39:22.324398 setenv serverip 192.168.6.2
1098 14:39:22.325151 Sending with 10 millisecond of delay
1100 14:39:26.049249 => tftpboot 0x01080000 953550/tftp-deploy-18laxw67/kernel/uImage
1101 14:39:26.060070 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1102 14:39:26.060980 tftpboot 0x01080000 953550/tftp-deploy-18laxw67/kernel/uImage
1103 14:39:26.061445 Speed: 1000, full duplex
1104 14:39:26.061884 Using ethernet@ff3f0000 device
1105 14:39:26.062715 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1106 14:39:26.068244 Filename '953550/tftp-deploy-18laxw67/kernel/uImage'.
1107 14:39:26.071406 Load address: 0x1080000
1108 14:39:29.043045 Loading: *################################################## 43.6 MiB
1109 14:39:29.043710 14.7 MiB/s
1110 14:39:29.044225 done
1111 14:39:29.047390 Bytes transferred = 45713984 (2b98a40 hex)
1112 14:39:29.048136 Sending with 10 millisecond of delay
1114 14:39:33.735759 => tftpboot 0x08000000 953550/tftp-deploy-18laxw67/ramdisk/ramdisk.cpio.gz.uboot
1115 14:39:33.746652 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1116 14:39:33.747608 tftpboot 0x08000000 953550/tftp-deploy-18laxw67/ramdisk/ramdisk.cpio.gz.uboot
1117 14:39:33.748116 Speed: 1000, full duplex
1118 14:39:33.748559 Using ethernet@ff3f0000 device
1119 14:39:33.749550 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1120 14:39:33.761307 Filename '953550/tftp-deploy-18laxw67/ramdisk/ramdisk.cpio.gz.uboot'.
1121 14:39:33.761862 Load address: 0x8000000
1122 14:39:40.907031 Loading: *#################T ################################ UDP wrong checksum 00000005 0000c63f
1123 14:39:45.908427 T UDP wrong checksum 00000005 0000c63f
1124 14:39:55.911304 T T UDP wrong checksum 00000005 0000c63f
1125 14:40:15.912231 T T T UDP wrong checksum 00000005 0000c63f
1126 14:40:19.912557 T UDP wrong checksum 000000ff 0000d43e
1127 14:40:19.924437 UDP wrong checksum 000000ff 00006831
1128 14:40:27.177224 T T UDP wrong checksum 000000ff 00006abc
1129 14:40:27.220419 UDP wrong checksum 000000ff 000004af
1130 14:40:30.026767 UDP wrong checksum 000000ff 000042a0
1131 14:40:30.068050 UDP wrong checksum 000000ff 0000cc92
1132 14:40:30.919572
1133 14:40:30.920276 Retry count exceeded; starting again
1135 14:40:30.921369 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1138 14:40:30.922908 end: 2.4 uboot-commands (duration 00:01:53) [common]
1140 14:40:30.924302 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1142 14:40:30.924993 end: 2 uboot-action (duration 00:01:53) [common]
1144 14:40:30.925853 Cleaning after the job
1145 14:40:30.926209 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953550/tftp-deploy-18laxw67/ramdisk
1146 14:40:30.927511 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953550/tftp-deploy-18laxw67/kernel
1147 14:40:30.954965 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953550/tftp-deploy-18laxw67/dtb
1148 14:40:30.956304 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953550/tftp-deploy-18laxw67/modules
1149 14:40:30.973596 start: 4.1 power-off (timeout 00:00:30) [common]
1150 14:40:30.974250 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1151 14:40:31.010661 >> OK - accepted request
1152 14:40:31.012662 Returned 0 in 0 seconds
1153 14:40:31.113812 end: 4.1 power-off (duration 00:00:00) [common]
1155 14:40:31.115753 start: 4.2 read-feedback (timeout 00:10:00) [common]
1156 14:40:31.116969 Listened to connection for namespace 'common' for up to 1s
1157 14:40:32.117779 Finalising connection for namespace 'common'
1158 14:40:32.118553 Disconnecting from shell: Finalise
1159 14:40:32.119088 =>
1160 14:40:32.220166 end: 4.2 read-feedback (duration 00:00:01) [common]
1161 14:40:32.220867 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/953550
1162 14:40:32.518933 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/953550
1163 14:40:32.519539 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.