Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 14:48:34.829710 lava-dispatcher, installed at version: 2024.01
2 14:48:34.830537 start: 0 validate
3 14:48:34.831017 Start time: 2024-11-07 14:48:34.830987+00:00 (UTC)
4 14:48:34.831604 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 14:48:34.832156 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 14:48:34.871051 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 14:48:34.871583 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-239-gba19e4550e25a%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 14:48:34.902846 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 14:48:34.903457 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-239-gba19e4550e25a%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 14:48:35.954881 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 14:48:35.955389 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-239-gba19e4550e25a%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 14:48:35.988734 validate duration: 1.16
14 14:48:35.989587 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 14:48:35.989914 start: 1.1 download-retry (timeout 00:10:00) [common]
16 14:48:35.990215 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 14:48:35.990787 Not decompressing ramdisk as can be used compressed.
18 14:48:35.991201 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 14:48:35.991462 saving as /var/lib/lava/dispatcher/tmp/953523/tftp-deploy-aftd19gn/ramdisk/rootfs.cpio.gz
20 14:48:35.991733 total size: 8181887 (7 MB)
21 14:48:36.031693 progress 0 % (0 MB)
22 14:48:36.042079 progress 5 % (0 MB)
23 14:48:36.052065 progress 10 % (0 MB)
24 14:48:36.061612 progress 15 % (1 MB)
25 14:48:36.066813 progress 20 % (1 MB)
26 14:48:36.072377 progress 25 % (1 MB)
27 14:48:36.077611 progress 30 % (2 MB)
28 14:48:36.083161 progress 35 % (2 MB)
29 14:48:36.088479 progress 40 % (3 MB)
30 14:48:36.094033 progress 45 % (3 MB)
31 14:48:36.099180 progress 50 % (3 MB)
32 14:48:36.104732 progress 55 % (4 MB)
33 14:48:36.109816 progress 60 % (4 MB)
34 14:48:36.115347 progress 65 % (5 MB)
35 14:48:36.120464 progress 70 % (5 MB)
36 14:48:36.125908 progress 75 % (5 MB)
37 14:48:36.131097 progress 80 % (6 MB)
38 14:48:36.136536 progress 85 % (6 MB)
39 14:48:36.141325 progress 90 % (7 MB)
40 14:48:36.146490 progress 95 % (7 MB)
41 14:48:36.151268 progress 100 % (7 MB)
42 14:48:36.151918 7 MB downloaded in 0.16 s (48.72 MB/s)
43 14:48:36.152494 end: 1.1.1 http-download (duration 00:00:00) [common]
45 14:48:36.153382 end: 1.1 download-retry (duration 00:00:00) [common]
46 14:48:36.153676 start: 1.2 download-retry (timeout 00:10:00) [common]
47 14:48:36.153952 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 14:48:36.154428 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm64/defconfig/gcc-12/kernel/Image
49 14:48:36.154702 saving as /var/lib/lava/dispatcher/tmp/953523/tftp-deploy-aftd19gn/kernel/Image
50 14:48:36.154918 total size: 45713920 (43 MB)
51 14:48:36.155131 No compression specified
52 14:48:36.193605 progress 0 % (0 MB)
53 14:48:36.221205 progress 5 % (2 MB)
54 14:48:36.248624 progress 10 % (4 MB)
55 14:48:36.276130 progress 15 % (6 MB)
56 14:48:36.303820 progress 20 % (8 MB)
57 14:48:36.331226 progress 25 % (10 MB)
58 14:48:36.358854 progress 30 % (13 MB)
59 14:48:36.386643 progress 35 % (15 MB)
60 14:48:36.414416 progress 40 % (17 MB)
61 14:48:36.442231 progress 45 % (19 MB)
62 14:48:36.469985 progress 50 % (21 MB)
63 14:48:36.497803 progress 55 % (24 MB)
64 14:48:36.525672 progress 60 % (26 MB)
65 14:48:36.555100 progress 65 % (28 MB)
66 14:48:36.585903 progress 70 % (30 MB)
67 14:48:36.613838 progress 75 % (32 MB)
68 14:48:36.641754 progress 80 % (34 MB)
69 14:48:36.669354 progress 85 % (37 MB)
70 14:48:36.697195 progress 90 % (39 MB)
71 14:48:36.724874 progress 95 % (41 MB)
72 14:48:36.751811 progress 100 % (43 MB)
73 14:48:36.752372 43 MB downloaded in 0.60 s (72.97 MB/s)
74 14:48:36.752864 end: 1.2.1 http-download (duration 00:00:01) [common]
76 14:48:36.753677 end: 1.2 download-retry (duration 00:00:01) [common]
77 14:48:36.753953 start: 1.3 download-retry (timeout 00:09:59) [common]
78 14:48:36.754217 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 14:48:36.754694 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 14:48:36.754974 saving as /var/lib/lava/dispatcher/tmp/953523/tftp-deploy-aftd19gn/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 14:48:36.755183 total size: 53209 (0 MB)
82 14:48:36.755394 No compression specified
83 14:48:36.792447 progress 61 % (0 MB)
84 14:48:36.793311 progress 100 % (0 MB)
85 14:48:36.793893 0 MB downloaded in 0.04 s (1.31 MB/s)
86 14:48:36.794376 end: 1.3.1 http-download (duration 00:00:00) [common]
88 14:48:36.795187 end: 1.3 download-retry (duration 00:00:00) [common]
89 14:48:36.795446 start: 1.4 download-retry (timeout 00:09:59) [common]
90 14:48:36.795708 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 14:48:36.796217 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm64/defconfig/gcc-12/modules.tar.xz
92 14:48:36.796526 saving as /var/lib/lava/dispatcher/tmp/953523/tftp-deploy-aftd19gn/modules/modules.tar
93 14:48:36.796742 total size: 11601668 (11 MB)
94 14:48:36.796957 Using unxz to decompress xz
95 14:48:36.840519 progress 0 % (0 MB)
96 14:48:36.913087 progress 5 % (0 MB)
97 14:48:36.989177 progress 10 % (1 MB)
98 14:48:37.088679 progress 15 % (1 MB)
99 14:48:37.181715 progress 20 % (2 MB)
100 14:48:37.262089 progress 25 % (2 MB)
101 14:48:37.337660 progress 30 % (3 MB)
102 14:48:37.412296 progress 35 % (3 MB)
103 14:48:37.489781 progress 40 % (4 MB)
104 14:48:37.566764 progress 45 % (5 MB)
105 14:48:37.651123 progress 50 % (5 MB)
106 14:48:37.728436 progress 55 % (6 MB)
107 14:48:37.815012 progress 60 % (6 MB)
108 14:48:37.897284 progress 65 % (7 MB)
109 14:48:37.975115 progress 70 % (7 MB)
110 14:48:38.057539 progress 75 % (8 MB)
111 14:48:38.141508 progress 80 % (8 MB)
112 14:48:38.217665 progress 85 % (9 MB)
113 14:48:38.300646 progress 90 % (9 MB)
114 14:48:38.378096 progress 95 % (10 MB)
115 14:48:38.455504 progress 100 % (11 MB)
116 14:48:38.466702 11 MB downloaded in 1.67 s (6.63 MB/s)
117 14:48:38.467263 end: 1.4.1 http-download (duration 00:00:02) [common]
119 14:48:38.468291 end: 1.4 download-retry (duration 00:00:02) [common]
120 14:48:38.468881 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 14:48:38.469471 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 14:48:38.470012 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 14:48:38.470559 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 14:48:38.471603 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6
125 14:48:38.472616 makedir: /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin
126 14:48:38.473337 makedir: /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/tests
127 14:48:38.474015 makedir: /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/results
128 14:48:38.474679 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-add-keys
129 14:48:38.475690 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-add-sources
130 14:48:38.476747 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-background-process-start
131 14:48:38.477758 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-background-process-stop
132 14:48:38.478813 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-common-functions
133 14:48:38.479907 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-echo-ipv4
134 14:48:38.480960 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-install-packages
135 14:48:38.481927 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-installed-packages
136 14:48:38.482876 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-os-build
137 14:48:38.483830 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-probe-channel
138 14:48:38.484839 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-probe-ip
139 14:48:38.485795 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-target-ip
140 14:48:38.486748 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-target-mac
141 14:48:38.487702 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-target-storage
142 14:48:38.488853 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-test-case
143 14:48:38.489864 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-test-event
144 14:48:38.490821 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-test-feedback
145 14:48:38.491810 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-test-raise
146 14:48:38.492846 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-test-reference
147 14:48:38.493817 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-test-runner
148 14:48:38.494785 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-test-set
149 14:48:38.495744 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-test-shell
150 14:48:38.496783 Updating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-install-packages (oe)
151 14:48:38.497825 Updating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/bin/lava-installed-packages (oe)
152 14:48:38.498717 Creating /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/environment
153 14:48:38.499482 LAVA metadata
154 14:48:38.500071 - LAVA_JOB_ID=953523
155 14:48:38.500554 - LAVA_DISPATCHER_IP=192.168.6.2
156 14:48:38.501274 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 14:48:38.503227 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 14:48:38.503870 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 14:48:38.504382 skipped lava-vland-overlay
160 14:48:38.504870 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 14:48:38.505392 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 14:48:38.505814 skipped lava-multinode-overlay
163 14:48:38.506290 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 14:48:38.506785 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 14:48:38.507254 Loading test definitions
166 14:48:38.507789 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 14:48:38.508175 Using /lava-953523 at stage 0
168 14:48:38.509406 uuid=953523_1.5.2.4.1 testdef=None
169 14:48:38.509725 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 14:48:38.509992 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 14:48:38.511886 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 14:48:38.512727 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 14:48:38.514983 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 14:48:38.515811 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 14:48:38.518022 runner path: /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/0/tests/0_dmesg test_uuid 953523_1.5.2.4.1
178 14:48:38.518585 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 14:48:38.519353 Creating lava-test-runner.conf files
181 14:48:38.519556 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/953523/lava-overlay-eq8_viv6/lava-953523/0 for stage 0
182 14:48:38.519887 - 0_dmesg
183 14:48:38.520277 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 14:48:38.520555 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 14:48:38.544421 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 14:48:38.544841 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 14:48:38.545105 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 14:48:38.545370 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 14:48:38.545632 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 14:48:39.630425 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 14:48:39.630893 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 14:48:39.631139 extracting modules file /var/lib/lava/dispatcher/tmp/953523/tftp-deploy-aftd19gn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/953523/extract-overlay-ramdisk-6uv_5w6n/ramdisk
193 14:48:40.985120 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 14:48:40.985600 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 14:48:40.985874 [common] Applying overlay /var/lib/lava/dispatcher/tmp/953523/compress-overlay-zcbpa2z4/overlay-1.5.2.5.tar.gz to ramdisk
196 14:48:40.986086 [common] Applying overlay /var/lib/lava/dispatcher/tmp/953523/compress-overlay-zcbpa2z4/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/953523/extract-overlay-ramdisk-6uv_5w6n/ramdisk
197 14:48:41.016299 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 14:48:41.016713 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 14:48:41.016980 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 14:48:41.017206 Converting downloaded kernel to a uImage
201 14:48:41.017507 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/953523/tftp-deploy-aftd19gn/kernel/Image /var/lib/lava/dispatcher/tmp/953523/tftp-deploy-aftd19gn/kernel/uImage
202 14:48:41.509922 output: Image Name:
203 14:48:41.510345 output: Created: Thu Nov 7 14:48:41 2024
204 14:48:41.510555 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 14:48:41.510761 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 14:48:41.510963 output: Load Address: 01080000
207 14:48:41.511160 output: Entry Point: 01080000
208 14:48:41.511358 output:
209 14:48:41.511693 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 14:48:41.511957 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 14:48:41.512273 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 14:48:41.512527 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 14:48:41.512785 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 14:48:41.513047 Building ramdisk /var/lib/lava/dispatcher/tmp/953523/extract-overlay-ramdisk-6uv_5w6n/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/953523/extract-overlay-ramdisk-6uv_5w6n/ramdisk
215 14:48:44.327477 >> 181575 blocks
216 14:48:52.973979 Adding RAMdisk u-boot header.
217 14:48:52.974667 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/953523/extract-overlay-ramdisk-6uv_5w6n/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/953523/extract-overlay-ramdisk-6uv_5w6n/ramdisk.cpio.gz.uboot
218 14:48:53.269888 output: Image Name:
219 14:48:53.270299 output: Created: Thu Nov 7 14:48:52 2024
220 14:48:53.270507 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 14:48:53.270709 output: Data Size: 26053385 Bytes = 25442.76 KiB = 24.85 MiB
222 14:48:53.270908 output: Load Address: 00000000
223 14:48:53.271105 output: Entry Point: 00000000
224 14:48:53.271300 output:
225 14:48:53.271880 rename /var/lib/lava/dispatcher/tmp/953523/extract-overlay-ramdisk-6uv_5w6n/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/953523/tftp-deploy-aftd19gn/ramdisk/ramdisk.cpio.gz.uboot
226 14:48:53.272552 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 14:48:53.273090 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 14:48:53.273609 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 14:48:53.274083 No LXC device requested
230 14:48:53.274574 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 14:48:53.275071 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 14:48:53.275553 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 14:48:53.275970 Checking files for TFTP limit of 4294967296 bytes.
234 14:48:53.278645 end: 1 tftp-deploy (duration 00:00:17) [common]
235 14:48:53.279201 start: 2 uboot-action (timeout 00:05:00) [common]
236 14:48:53.279715 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 14:48:53.280240 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 14:48:53.280737 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 14:48:53.281256 Using kernel file from prepare-kernel: 953523/tftp-deploy-aftd19gn/kernel/uImage
240 14:48:53.281853 substitutions:
241 14:48:53.282255 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 14:48:53.282653 - {DTB_ADDR}: 0x01070000
243 14:48:53.283045 - {DTB}: 953523/tftp-deploy-aftd19gn/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 14:48:53.283437 - {INITRD}: 953523/tftp-deploy-aftd19gn/ramdisk/ramdisk.cpio.gz.uboot
245 14:48:53.283830 - {KERNEL_ADDR}: 0x01080000
246 14:48:53.284250 - {KERNEL}: 953523/tftp-deploy-aftd19gn/kernel/uImage
247 14:48:53.284643 - {LAVA_MAC}: None
248 14:48:53.285067 - {PRESEED_CONFIG}: None
249 14:48:53.285456 - {PRESEED_LOCAL}: None
250 14:48:53.285838 - {RAMDISK_ADDR}: 0x08000000
251 14:48:53.286220 - {RAMDISK}: 953523/tftp-deploy-aftd19gn/ramdisk/ramdisk.cpio.gz.uboot
252 14:48:53.286606 - {ROOT_PART}: None
253 14:48:53.286988 - {ROOT}: None
254 14:48:53.287371 - {SERVER_IP}: 192.168.6.2
255 14:48:53.287759 - {TEE_ADDR}: 0x83000000
256 14:48:53.288177 - {TEE}: None
257 14:48:53.288567 Parsed boot commands:
258 14:48:53.288940 - setenv autoload no
259 14:48:53.289320 - setenv initrd_high 0xffffffff
260 14:48:53.289702 - setenv fdt_high 0xffffffff
261 14:48:53.290082 - dhcp
262 14:48:53.290464 - setenv serverip 192.168.6.2
263 14:48:53.290848 - tftpboot 0x01080000 953523/tftp-deploy-aftd19gn/kernel/uImage
264 14:48:53.291230 - tftpboot 0x08000000 953523/tftp-deploy-aftd19gn/ramdisk/ramdisk.cpio.gz.uboot
265 14:48:53.291613 - tftpboot 0x01070000 953523/tftp-deploy-aftd19gn/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 14:48:53.292014 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 14:48:53.292407 - bootm 0x01080000 0x08000000 0x01070000
268 14:48:53.292892 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 14:48:53.294353 start: 2.3 connect-device (timeout 00:05:00) [common]
271 14:48:53.294786 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 14:48:53.309671 Setting prompt string to ['lava-test: # ']
273 14:48:53.311154 end: 2.3 connect-device (duration 00:00:00) [common]
274 14:48:53.311742 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 14:48:53.312330 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 14:48:53.312862 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 14:48:53.313976 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 14:48:53.347941 >> OK - accepted request
279 14:48:53.350031 Returned 0 in 0 seconds
280 14:48:53.451192 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 14:48:53.452875 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 14:48:53.453449 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 14:48:53.453945 Setting prompt string to ['Hit any key to stop autoboot']
285 14:48:53.454382 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 14:48:53.455918 Trying 192.168.56.21...
287 14:48:53.456412 Connected to conserv1.
288 14:48:53.456825 Escape character is '^]'.
289 14:48:53.457240
290 14:48:53.457655 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 14:48:53.458081
292 14:49:00.669983 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 14:49:00.670620 bl2_stage_init 0x01
294 14:49:00.671050 bl2_stage_init 0x81
295 14:49:00.675458 hw id: 0x0000 - pwm id 0x01
296 14:49:00.675912 bl2_stage_init 0xc1
297 14:49:00.681042 bl2_stage_init 0x02
298 14:49:00.681483
299 14:49:00.681884 L0:00000000
300 14:49:00.682284 L1:00000703
301 14:49:00.682670 L2:00008067
302 14:49:00.683054 L3:15000000
303 14:49:00.686656 S1:00000000
304 14:49:00.687080 B2:20282000
305 14:49:00.687472 B1:a0f83180
306 14:49:00.687858
307 14:49:00.688284 TE: 70018
308 14:49:00.688674
309 14:49:00.692223 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 14:49:00.692638
311 14:49:00.697840 Board ID = 1
312 14:49:00.698263 Set cpu clk to 24M
313 14:49:00.698652 Set clk81 to 24M
314 14:49:00.703415 Use GP1_pll as DSU clk.
315 14:49:00.703824 DSU clk: 1200 Mhz
316 14:49:00.704246 CPU clk: 1200 MHz
317 14:49:00.709059 Set clk81 to 166.6M
318 14:49:00.714654 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 14:49:00.715078 board id: 1
320 14:49:00.721850 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 14:49:00.732732 fw parse done
322 14:49:00.738743 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 14:49:00.781885 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 14:49:00.793096 PIEI prepare done
325 14:49:00.793619 fastboot data load
326 14:49:00.794070 fastboot data verify
327 14:49:00.798701 verify result: 266
328 14:49:00.804349 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 14:49:00.804896 LPDDR4 probe
330 14:49:00.805385 ddr clk to 1584MHz
331 14:49:00.812257 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 14:49:00.850019
333 14:49:00.850537 dmc_version 0001
334 14:49:00.857055 Check phy result
335 14:49:00.863012 INFO : End of CA training
336 14:49:00.863526 INFO : End of initialization
337 14:49:00.868619 INFO : Training has run successfully!
338 14:49:00.869131 Check phy result
339 14:49:00.874205 INFO : End of initialization
340 14:49:00.874710 INFO : End of read enable training
341 14:49:00.877504 INFO : End of fine write leveling
342 14:49:00.883090 INFO : End of Write leveling coarse delay
343 14:49:00.888693 INFO : Training has run successfully!
344 14:49:00.889198 Check phy result
345 14:49:00.889634 INFO : End of initialization
346 14:49:00.894220 INFO : End of read dq deskew training
347 14:49:00.899821 INFO : End of MPR read delay center optimization
348 14:49:00.900373 INFO : End of write delay center optimization
349 14:49:00.905427 INFO : End of read delay center optimization
350 14:49:00.911083 INFO : End of max read latency training
351 14:49:00.911607 INFO : Training has run successfully!
352 14:49:00.916744 1D training succeed
353 14:49:00.922650 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 14:49:00.970961 Check phy result
355 14:49:00.971476 INFO : End of initialization
356 14:49:00.998261 INFO : End of 2D read delay Voltage center optimization
357 14:49:01.022549 INFO : End of 2D read delay Voltage center optimization
358 14:49:01.079343 INFO : End of 2D write delay Voltage center optimization
359 14:49:01.133489 INFO : End of 2D write delay Voltage center optimization
360 14:49:01.139232 INFO : Training has run successfully!
361 14:49:01.139760
362 14:49:01.140253 channel==0
363 14:49:01.144442 RxClkDly_Margin_A0==78 ps 8
364 14:49:01.144955 TxDqDly_Margin_A0==88 ps 9
365 14:49:01.150517 RxClkDly_Margin_A1==88 ps 9
366 14:49:01.151029 TxDqDly_Margin_A1==88 ps 9
367 14:49:01.151471 TrainedVREFDQ_A0==74
368 14:49:01.155869 TrainedVREFDQ_A1==74
369 14:49:01.156468 VrefDac_Margin_A0==24
370 14:49:01.156945 DeviceVref_Margin_A0==40
371 14:49:01.161365 VrefDac_Margin_A1==23
372 14:49:01.161882 DeviceVref_Margin_A1==40
373 14:49:01.162320
374 14:49:01.162753
375 14:49:01.163188 channel==1
376 14:49:01.166754 RxClkDly_Margin_A0==88 ps 9
377 14:49:01.167261 TxDqDly_Margin_A0==88 ps 9
378 14:49:01.172699 RxClkDly_Margin_A1==78 ps 8
379 14:49:01.173209 TxDqDly_Margin_A1==88 ps 9
380 14:49:01.177966 TrainedVREFDQ_A0==76
381 14:49:01.178481 TrainedVREFDQ_A1==75
382 14:49:01.178916 VrefDac_Margin_A0==21
383 14:49:01.183527 DeviceVref_Margin_A0==38
384 14:49:01.184072 VrefDac_Margin_A1==22
385 14:49:01.184512 DeviceVref_Margin_A1==39
386 14:49:01.189115
387 14:49:01.189626 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 14:49:01.190060
389 14:49:01.222701 soc_vref_reg_value 0x 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000062
390 14:49:01.223307 2D training succeed
391 14:49:01.228299 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 14:49:01.233972 auto size-- 65535DDR cs0 size: 2048MB
393 14:49:01.234480 DDR cs1 size: 2048MB
394 14:49:01.239517 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 14:49:01.240050 cs0 DataBus test pass
396 14:49:01.245163 cs1 DataBus test pass
397 14:49:01.245670 cs0 AddrBus test pass
398 14:49:01.246100 cs1 AddrBus test pass
399 14:49:01.246525
400 14:49:01.250745 100bdlr_step_size ps== 478
401 14:49:01.251267 result report
402 14:49:01.256307 boot times 0Enable ddr reg access
403 14:49:01.261304 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 14:49:01.275167 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 14:49:01.934487 bl2z: ptr: 05129330, size: 00001e40
406 14:49:01.942833 0.0;M3 CHK:0;cm4_sp_mode 0
407 14:49:01.943335 MVN_1=0x00000000
408 14:49:01.943769 MVN_2=0x00000000
409 14:49:01.954187 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 14:49:01.954675 OPS=0x04
411 14:49:01.955114 ring efuse init
412 14:49:01.957146 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 14:49:01.963315 [0.017354 Inits done]
414 14:49:01.963789 secure task start!
415 14:49:01.964263 high task start!
416 14:49:01.964690 low task start!
417 14:49:01.967623 run into bl31
418 14:49:01.976262 NOTICE: BL31: v1.3(release):4fc40b1
419 14:49:01.984085 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 14:49:01.984576 NOTICE: BL31: G12A normal boot!
421 14:49:01.999569 NOTICE: BL31: BL33 decompress pass
422 14:49:02.005248 ERROR: Error initializing runtime service opteed_fast
423 14:49:04.721220 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 14:49:04.721908 bl2_stage_init 0x01
425 14:49:04.722393 bl2_stage_init 0x81
426 14:49:04.726718 hw id: 0x0000 - pwm id 0x01
427 14:49:04.727250 bl2_stage_init 0xc1
428 14:49:04.731466 bl2_stage_init 0x02
429 14:49:04.732201
430 14:49:04.732690 L0:00000000
431 14:49:04.733125 L1:00000703
432 14:49:04.733552 L2:00008067
433 14:49:04.737089 L3:15000000
434 14:49:04.737575 S1:00000000
435 14:49:04.738007 B2:20282000
436 14:49:04.738437 B1:a0f83180
437 14:49:04.738860
438 14:49:04.739287 TE: 70520
439 14:49:04.739709
440 14:49:04.748213 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 14:49:04.748720
442 14:49:04.749163 Board ID = 1
443 14:49:04.749600 Set cpu clk to 24M
444 14:49:04.750031 Set clk81 to 24M
445 14:49:04.753800 Use GP1_pll as DSU clk.
446 14:49:04.754283 DSU clk: 1200 Mhz
447 14:49:04.754712 CPU clk: 1200 MHz
448 14:49:04.759364 Set clk81 to 166.6M
449 14:49:04.765049 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 14:49:04.765525 board id: 1
451 14:49:04.773097 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 14:49:04.783772 fw parse done
453 14:49:04.789699 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 14:49:04.832419 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 14:49:04.843391 PIEI prepare done
456 14:49:04.843896 fastboot data load
457 14:49:04.844378 fastboot data verify
458 14:49:04.848949 verify result: 266
459 14:49:04.854535 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 14:49:04.855029 LPDDR4 probe
461 14:49:04.855461 ddr clk to 1584MHz
462 14:49:04.862545 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 14:49:04.899851
464 14:49:04.900460 dmc_version 0001
465 14:49:04.906461 Check phy result
466 14:49:04.912414 INFO : End of CA training
467 14:49:04.912947 INFO : End of initialization
468 14:49:04.918014 INFO : Training has run successfully!
469 14:49:04.918534 Check phy result
470 14:49:04.923603 INFO : End of initialization
471 14:49:04.924157 INFO : End of read enable training
472 14:49:04.929220 INFO : End of fine write leveling
473 14:49:04.934793 INFO : End of Write leveling coarse delay
474 14:49:04.935319 INFO : Training has run successfully!
475 14:49:04.935791 Check phy result
476 14:49:04.940407 INFO : End of initialization
477 14:49:04.940919 INFO : End of read dq deskew training
478 14:49:04.945988 INFO : End of MPR read delay center optimization
479 14:49:04.951593 INFO : End of write delay center optimization
480 14:49:04.957214 INFO : End of read delay center optimization
481 14:49:04.957740 INFO : End of max read latency training
482 14:49:04.962786 INFO : Training has run successfully!
483 14:49:04.963292 1D training succeed
484 14:49:04.971931 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 14:49:05.019543 Check phy result
486 14:49:05.020100 INFO : End of initialization
487 14:49:05.041997 INFO : End of 2D read delay Voltage center optimization
488 14:49:05.061107 INFO : End of 2D read delay Voltage center optimization
489 14:49:05.112954 INFO : End of 2D write delay Voltage center optimization
490 14:49:05.162180 INFO : End of 2D write delay Voltage center optimization
491 14:49:05.167751 INFO : Training has run successfully!
492 14:49:05.168323
493 14:49:05.168782 channel==0
494 14:49:05.173384 RxClkDly_Margin_A0==88 ps 9
495 14:49:05.173886 TxDqDly_Margin_A0==98 ps 10
496 14:49:05.178915 RxClkDly_Margin_A1==78 ps 8
497 14:49:05.179412 TxDqDly_Margin_A1==88 ps 9
498 14:49:05.179862 TrainedVREFDQ_A0==74
499 14:49:05.184539 TrainedVREFDQ_A1==74
500 14:49:05.185042 VrefDac_Margin_A0==23
501 14:49:05.185491 DeviceVref_Margin_A0==40
502 14:49:05.190149 VrefDac_Margin_A1==23
503 14:49:05.190646 DeviceVref_Margin_A1==40
504 14:49:05.191098
505 14:49:05.191542
506 14:49:05.192012 channel==1
507 14:49:05.195743 RxClkDly_Margin_A0==78 ps 8
508 14:49:05.196272 TxDqDly_Margin_A0==98 ps 10
509 14:49:05.201376 RxClkDly_Margin_A1==88 ps 9
510 14:49:05.201880 TxDqDly_Margin_A1==88 ps 9
511 14:49:05.206931 TrainedVREFDQ_A0==78
512 14:49:05.207432 TrainedVREFDQ_A1==75
513 14:49:05.207881 VrefDac_Margin_A0==22
514 14:49:05.212541 DeviceVref_Margin_A0==36
515 14:49:05.213038 VrefDac_Margin_A1==22
516 14:49:05.218140 DeviceVref_Margin_A1==39
517 14:49:05.218635
518 14:49:05.219085 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 14:49:05.219527
520 14:49:05.251695 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
521 14:49:05.252284 2D training succeed
522 14:49:05.257386 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 14:49:05.262917 auto size-- 65535DDR cs0 size: 2048MB
524 14:49:05.263417 DDR cs1 size: 2048MB
525 14:49:05.268506 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 14:49:05.269012 cs0 DataBus test pass
527 14:49:05.274116 cs1 DataBus test pass
528 14:49:05.274640 cs0 AddrBus test pass
529 14:49:05.275088 cs1 AddrBus test pass
530 14:49:05.275526
531 14:49:05.279743 100bdlr_step_size ps== 478
532 14:49:05.280309 result report
533 14:49:05.285406 boot times 0Enable ddr reg access
534 14:49:05.290515 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 14:49:05.304473 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 14:49:05.959244 bl2z: ptr: 05129330, size: 00001e40
537 14:49:05.967539 0.0;M3 CHK:0;cm4_sp_mode 0
538 14:49:05.968113 MVN_1=0x00000000
539 14:49:05.968580 MVN_2=0x00000000
540 14:49:05.979019 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 14:49:05.979525 OPS=0x04
542 14:49:05.980015 ring efuse init
543 14:49:05.984651 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 14:49:05.985161 [0.017310 Inits done]
545 14:49:05.985613 secure task start!
546 14:49:05.992437 high task start!
547 14:49:05.992926 low task start!
548 14:49:05.993375 run into bl31
549 14:49:06.001043 NOTICE: BL31: v1.3(release):4fc40b1
550 14:49:06.008852 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 14:49:06.009350 NOTICE: BL31: G12A normal boot!
552 14:49:06.024427 NOTICE: BL31: BL33 decompress pass
553 14:49:06.030117 ERROR: Error initializing runtime service opteed_fast
554 14:49:07.423096 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 14:49:07.423530 bl2_stage_init 0x01
556 14:49:07.423752 bl2_stage_init 0x81
557 14:49:07.428837 hw id: 0x0000 - pwm id 0x01
558 14:49:07.429362 bl2_stage_init 0xc1
559 14:49:07.433076 bl2_stage_init 0x02
560 14:49:07.433565
561 14:49:07.434021 L0:00000000
562 14:49:07.434463 L1:00000703
563 14:49:07.434900 L2:00008067
564 14:49:07.438653 L3:15000000
565 14:49:07.439128 S1:00000000
566 14:49:07.439571 B2:20282000
567 14:49:07.440050 B1:a0f83180
568 14:49:07.440502
569 14:49:07.440946 TE: 72843
570 14:49:07.441385
571 14:49:07.449793 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 14:49:07.450281
573 14:49:07.450732 Board ID = 1
574 14:49:07.451172 Set cpu clk to 24M
575 14:49:07.451607 Set clk81 to 24M
576 14:49:07.455362 Use GP1_pll as DSU clk.
577 14:49:07.455844 DSU clk: 1200 Mhz
578 14:49:07.456333 CPU clk: 1200 MHz
579 14:49:07.460964 Set clk81 to 166.6M
580 14:49:07.466545 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 14:49:07.467031 board id: 1
582 14:49:07.475015 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 14:49:07.485877 fw parse done
584 14:49:07.491958 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 14:49:07.535020 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 14:49:07.546042 PIEI prepare done
587 14:49:07.546537 fastboot data load
588 14:49:07.546999 fastboot data verify
589 14:49:07.551655 verify result: 266
590 14:49:07.557209 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 14:49:07.557704 LPDDR4 probe
592 14:49:07.558153 ddr clk to 1584MHz
593 14:49:07.565240 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 14:49:07.602962
595 14:49:07.603471 dmc_version 0001
596 14:49:07.609997 Check phy result
597 14:49:07.615941 INFO : End of CA training
598 14:49:07.616457 INFO : End of initialization
599 14:49:07.621544 INFO : Training has run successfully!
600 14:49:07.622028 Check phy result
601 14:49:07.627139 INFO : End of initialization
602 14:49:07.627612 INFO : End of read enable training
603 14:49:07.630452 INFO : End of fine write leveling
604 14:49:07.635973 INFO : End of Write leveling coarse delay
605 14:49:07.641665 INFO : Training has run successfully!
606 14:49:07.642143 Check phy result
607 14:49:07.642588 INFO : End of initialization
608 14:49:07.647197 INFO : End of read dq deskew training
609 14:49:07.652865 INFO : End of MPR read delay center optimization
610 14:49:07.653346 INFO : End of write delay center optimization
611 14:49:07.658399 INFO : End of read delay center optimization
612 14:49:07.664032 INFO : End of max read latency training
613 14:49:07.664517 INFO : Training has run successfully!
614 14:49:07.669690 1D training succeed
615 14:49:07.675562 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 14:49:07.723865 Check phy result
617 14:49:07.724447 INFO : End of initialization
618 14:49:07.751220 INFO : End of 2D read delay Voltage center optimization
619 14:49:07.775327 INFO : End of 2D read delay Voltage center optimization
620 14:49:07.832073 INFO : End of 2D write delay Voltage center optimization
621 14:49:07.886007 INFO : End of 2D write delay Voltage center optimization
622 14:49:07.891643 INFO : Training has run successfully!
623 14:49:07.892155
624 14:49:07.892626 channel==0
625 14:49:07.897210 RxClkDly_Margin_A0==69 ps 7
626 14:49:07.897686 TxDqDly_Margin_A0==98 ps 10
627 14:49:07.902787 RxClkDly_Margin_A1==88 ps 9
628 14:49:07.903267 TxDqDly_Margin_A1==88 ps 9
629 14:49:07.903715 TrainedVREFDQ_A0==74
630 14:49:07.908356 TrainedVREFDQ_A1==74
631 14:49:07.908832 VrefDac_Margin_A0==23
632 14:49:07.909278 DeviceVref_Margin_A0==40
633 14:49:07.913992 VrefDac_Margin_A1==23
634 14:49:07.914459 DeviceVref_Margin_A1==40
635 14:49:07.914905
636 14:49:07.915345
637 14:49:07.915807 channel==1
638 14:49:07.919592 RxClkDly_Margin_A0==88 ps 9
639 14:49:07.920111 TxDqDly_Margin_A0==98 ps 10
640 14:49:07.925165 RxClkDly_Margin_A1==78 ps 8
641 14:49:07.925644 TxDqDly_Margin_A1==88 ps 9
642 14:49:07.930823 TrainedVREFDQ_A0==78
643 14:49:07.931308 TrainedVREFDQ_A1==75
644 14:49:07.931751 VrefDac_Margin_A0==22
645 14:49:07.936317 DeviceVref_Margin_A0==36
646 14:49:07.936795 VrefDac_Margin_A1==22
647 14:49:07.942009 DeviceVref_Margin_A1==39
648 14:49:07.942485
649 14:49:07.942930 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 14:49:07.943369
651 14:49:07.975440 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 14:49:07.975963 2D training succeed
653 14:49:07.981051 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 14:49:07.986675 auto size-- 65535DDR cs0 size: 2048MB
655 14:49:07.987153 DDR cs1 size: 2048MB
656 14:49:07.992250 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 14:49:07.992728 cs0 DataBus test pass
658 14:49:07.997852 cs1 DataBus test pass
659 14:49:07.998323 cs0 AddrBus test pass
660 14:49:07.998765 cs1 AddrBus test pass
661 14:49:07.999204
662 14:49:08.003435 100bdlr_step_size ps== 471
663 14:49:08.003923 result report
664 14:49:08.009067 boot times 0Enable ddr reg access
665 14:49:08.014198 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 14:49:08.028256 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 14:49:08.687084 bl2z: ptr: 05129330, size: 00001e40
668 14:49:08.696116 0.0;M3 CHK:0;cm4_sp_mode 0
669 14:49:08.696738 MVN_1=0x00000000
670 14:49:08.697208 MVN_2=0x00000000
671 14:49:08.707560 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 14:49:08.708178 OPS=0x04
673 14:49:08.708657 ring efuse init
674 14:49:08.713218 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 14:49:08.713843 [0.017355 Inits done]
676 14:49:08.714325 secure task start!
677 14:49:08.721375 high task start!
678 14:49:08.721949 low task start!
679 14:49:08.722417 run into bl31
680 14:49:08.729999 NOTICE: BL31: v1.3(release):4fc40b1
681 14:49:08.737746 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 14:49:08.738331 NOTICE: BL31: G12A normal boot!
683 14:49:08.753389 NOTICE: BL31: BL33 decompress pass
684 14:49:08.759060 ERROR: Error initializing runtime service opteed_fast
685 14:49:09.552995
686 14:49:09.553409
687 14:49:09.558441 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 14:49:09.558910
689 14:49:09.561924 Model: Libre Computer AML-S905D3-CC Solitude
690 14:49:09.708954 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 14:49:09.724302 DRAM: 2 GiB (effective 3.8 GiB)
692 14:49:09.825301 Core: 406 devices, 33 uclasses, devicetree: separate
693 14:49:09.831197 WDT: Not starting watchdog@f0d0
694 14:49:09.856245 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 14:49:09.868396 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 14:49:09.873426 ** Bad device specification mmc 0 **
697 14:49:09.883559 Card did not respond to voltage select! : -110
698 14:49:09.891152 ** Bad device specification mmc 0 **
699 14:49:09.891744 Couldn't find partition mmc 0
700 14:49:09.899494 Card did not respond to voltage select! : -110
701 14:49:09.905118 ** Bad device specification mmc 0 **
702 14:49:09.905697 Couldn't find partition mmc 0
703 14:49:09.910100 Error: could not access storage.
704 14:49:10.207400 Net: eth0: ethernet@ff3f0000
705 14:49:10.208053 starting USB...
706 14:49:10.452271 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 14:49:10.452888 Starting the controller
708 14:49:10.459091 USB XHCI 1.10
709 14:49:12.012438 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 14:49:12.020832 scanning usb for storage devices... 0 Storage Device(s) found
712 14:49:12.072553 Hit any key to stop autoboot: 1
713 14:49:12.073802 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 14:49:12.074487 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 14:49:12.075017 Setting prompt string to ['=>']
716 14:49:12.075540 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 14:49:12.086841 0
718 14:49:12.087807 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 14:49:12.189193 => setenv autoload no
721 14:49:12.190196 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 14:49:12.195736 setenv autoload no
724 14:49:12.297333 => setenv initrd_high 0xffffffff
725 14:49:12.298245 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 14:49:12.302477 setenv initrd_high 0xffffffff
728 14:49:12.404059 => setenv fdt_high 0xffffffff
729 14:49:12.405062 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 14:49:12.409390 setenv fdt_high 0xffffffff
732 14:49:12.511072 => dhcp
733 14:49:12.512134 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 14:49:12.516044 dhcp
735 14:49:13.021554 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 14:49:13.021970 Speed: 1000, full duplex
737 14:49:13.022265 BOOTP broadcast 1
738 14:49:13.034254 DHCP client bound to address 192.168.6.21 (12 ms)
740 14:49:13.135750 => setenv serverip 192.168.6.2
741 14:49:13.136411 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
742 14:49:13.140838 setenv serverip 192.168.6.2
744 14:49:13.242226 => tftpboot 0x01080000 953523/tftp-deploy-aftd19gn/kernel/uImage
745 14:49:13.242790 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
746 14:49:13.249589 tftpboot 0x01080000 953523/tftp-deploy-aftd19gn/kernel/uImage
747 14:49:13.250039 Speed: 1000, full duplex
748 14:49:13.250435 Using ethernet@ff3f0000 device
749 14:49:13.254908 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 14:49:13.260556 Filename '953523/tftp-deploy-aftd19gn/kernel/uImage'.
751 14:49:13.264467 Load address: 0x1080000
752 14:49:16.165674 Loading: *################################################## 43.6 MiB
753 14:49:16.166255 15 MiB/s
754 14:49:16.166658 done
755 14:49:16.170115 Bytes transferred = 45713984 (2b98a40 hex)
757 14:49:16.271522 => tftpboot 0x08000000 953523/tftp-deploy-aftd19gn/ramdisk/ramdisk.cpio.gz.uboot
758 14:49:16.272241 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
759 14:49:16.279008 tftpboot 0x08000000 953523/tftp-deploy-aftd19gn/ramdisk/ramdisk.cpio.gz.uboot
760 14:49:16.279455 Speed: 1000, full duplex
761 14:49:16.279846 Using ethernet@ff3f0000 device
762 14:49:16.284542 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
763 14:49:16.294293 Filename '953523/tftp-deploy-aftd19gn/ramdisk/ramdisk.cpio.gz.uboot'.
764 14:49:16.294795 Load address: 0x8000000
765 14:49:17.726958 Loading: *####################################### UDP wrong checksum 000000ff 00008544
766 14:49:17.740513 # UDP wrong checksum 000000ff 00000e37
767 14:49:18.147456 ######### UDP wrong checksum 00000005 0000a6e1
768 14:49:21.037428 UDP wrong checksum 000000ff 00003862
769 14:49:21.077762 UDP wrong checksum 000000ff 0000c854
770 14:49:23.147929 T UDP wrong checksum 00000005 0000a6e1
771 14:49:26.738106 UDP wrong checksum 000000ff 00002d70
772 14:49:26.776898 UDP wrong checksum 000000ff 000085e8
773 14:49:33.150273 T T UDP wrong checksum 00000005 0000a6e1
774 14:49:33.820293 UDP wrong checksum 00000005 00004c43
775 14:49:53.152585 T T T UDP wrong checksum 00000005 0000a6e1
776 14:50:13.158995 T T T T
777 14:50:13.159602 Retry count exceeded; starting again
779 14:50:13.161070 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
782 14:50:13.162880 end: 2.4 uboot-commands (duration 00:01:20) [common]
784 14:50:13.164341 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
786 14:50:13.165404 end: 2 uboot-action (duration 00:01:20) [common]
788 14:50:13.166972 Cleaning after the job
789 14:50:13.167513 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953523/tftp-deploy-aftd19gn/ramdisk
790 14:50:13.168655 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953523/tftp-deploy-aftd19gn/kernel
791 14:50:13.215627 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953523/tftp-deploy-aftd19gn/dtb
792 14:50:13.216418 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953523/tftp-deploy-aftd19gn/modules
793 14:50:13.236498 start: 4.1 power-off (timeout 00:00:30) [common]
794 14:50:13.237141 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
795 14:50:13.269269 >> OK - accepted request
796 14:50:13.271286 Returned 0 in 0 seconds
797 14:50:13.372030 end: 4.1 power-off (duration 00:00:00) [common]
799 14:50:13.372993 start: 4.2 read-feedback (timeout 00:10:00) [common]
800 14:50:13.373641 Listened to connection for namespace 'common' for up to 1s
801 14:50:14.374629 Finalising connection for namespace 'common'
802 14:50:14.375341 Disconnecting from shell: Finalise
803 14:50:14.375855 =>
804 14:50:14.476987 end: 4.2 read-feedback (duration 00:00:01) [common]
805 14:50:14.477628 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/953523
806 14:50:14.818622 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/953523
807 14:50:14.819235 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.