Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 19:02:44.255844 lava-dispatcher, installed at version: 2024.01
2 19:02:44.256650 start: 0 validate
3 19:02:44.257142 Start time: 2024-11-07 19:02:44.257111+00:00 (UTC)
4 19:02:44.257684 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:02:44.258230 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 19:02:44.297605 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:02:44.298150 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-239-gba19e4550e25a%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 19:02:44.326936 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:02:44.327559 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-239-gba19e4550e25a%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 19:02:44.355072 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:02:44.355564 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-239-gba19e4550e25a%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 19:02:44.396279 validate duration: 0.14
14 19:02:44.397105 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:02:44.397430 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:02:44.397718 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:02:44.398279 Not decompressing ramdisk as can be used compressed.
18 19:02:44.398710 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 19:02:44.398946 saving as /var/lib/lava/dispatcher/tmp/953554/tftp-deploy-k5dwgcpl/ramdisk/rootfs.cpio.gz
20 19:02:44.399195 total size: 47897469 (45 MB)
21 19:02:44.442494 progress 0 % (0 MB)
22 19:02:44.472705 progress 5 % (2 MB)
23 19:02:44.502184 progress 10 % (4 MB)
24 19:02:44.531494 progress 15 % (6 MB)
25 19:02:44.560720 progress 20 % (9 MB)
26 19:02:44.589769 progress 25 % (11 MB)
27 19:02:44.619094 progress 30 % (13 MB)
28 19:02:44.648736 progress 35 % (16 MB)
29 19:02:44.677852 progress 40 % (18 MB)
30 19:02:44.706852 progress 45 % (20 MB)
31 19:02:44.736341 progress 50 % (22 MB)
32 19:02:44.765338 progress 55 % (25 MB)
33 19:02:44.794826 progress 60 % (27 MB)
34 19:02:44.823841 progress 65 % (29 MB)
35 19:02:44.853242 progress 70 % (32 MB)
36 19:02:44.882272 progress 75 % (34 MB)
37 19:02:44.911316 progress 80 % (36 MB)
38 19:02:44.940773 progress 85 % (38 MB)
39 19:02:44.969800 progress 90 % (41 MB)
40 19:02:44.998674 progress 95 % (43 MB)
41 19:02:45.027372 progress 100 % (45 MB)
42 19:02:45.028159 45 MB downloaded in 0.63 s (72.63 MB/s)
43 19:02:45.028790 end: 1.1.1 http-download (duration 00:00:01) [common]
45 19:02:45.029735 end: 1.1 download-retry (duration 00:00:01) [common]
46 19:02:45.030027 start: 1.2 download-retry (timeout 00:09:59) [common]
47 19:02:45.030295 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 19:02:45.030763 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm64/defconfig/gcc-12/kernel/Image
49 19:02:45.031025 saving as /var/lib/lava/dispatcher/tmp/953554/tftp-deploy-k5dwgcpl/kernel/Image
50 19:02:45.031234 total size: 45713920 (43 MB)
51 19:02:45.031446 No compression specified
52 19:02:45.075274 progress 0 % (0 MB)
53 19:02:45.104932 progress 5 % (2 MB)
54 19:02:45.133542 progress 10 % (4 MB)
55 19:02:45.163228 progress 15 % (6 MB)
56 19:02:45.193575 progress 20 % (8 MB)
57 19:02:45.222439 progress 25 % (10 MB)
58 19:02:45.251608 progress 30 % (13 MB)
59 19:02:45.280691 progress 35 % (15 MB)
60 19:02:45.309504 progress 40 % (17 MB)
61 19:02:45.337834 progress 45 % (19 MB)
62 19:02:45.366668 progress 50 % (21 MB)
63 19:02:45.395857 progress 55 % (24 MB)
64 19:02:45.424601 progress 60 % (26 MB)
65 19:02:45.452792 progress 65 % (28 MB)
66 19:02:45.481521 progress 70 % (30 MB)
67 19:02:45.510406 progress 75 % (32 MB)
68 19:02:45.539381 progress 80 % (34 MB)
69 19:02:45.567901 progress 85 % (37 MB)
70 19:02:45.596808 progress 90 % (39 MB)
71 19:02:45.625351 progress 95 % (41 MB)
72 19:02:45.653036 progress 100 % (43 MB)
73 19:02:45.653541 43 MB downloaded in 0.62 s (70.06 MB/s)
74 19:02:45.654017 end: 1.2.1 http-download (duration 00:00:01) [common]
76 19:02:45.654853 end: 1.2 download-retry (duration 00:00:01) [common]
77 19:02:45.655128 start: 1.3 download-retry (timeout 00:09:59) [common]
78 19:02:45.655389 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 19:02:45.655857 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 19:02:45.656124 saving as /var/lib/lava/dispatcher/tmp/953554/tftp-deploy-k5dwgcpl/dtb/meson-g12b-a311d-libretech-cc.dtb
81 19:02:45.656334 total size: 54703 (0 MB)
82 19:02:45.656542 No compression specified
83 19:02:45.695783 progress 59 % (0 MB)
84 19:02:45.696645 progress 100 % (0 MB)
85 19:02:45.697190 0 MB downloaded in 0.04 s (1.28 MB/s)
86 19:02:45.697659 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:02:45.698467 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:02:45.698724 start: 1.4 download-retry (timeout 00:09:59) [common]
90 19:02:45.698983 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 19:02:45.699430 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-239-gba19e4550e25a/arm64/defconfig/gcc-12/modules.tar.xz
92 19:02:45.699664 saving as /var/lib/lava/dispatcher/tmp/953554/tftp-deploy-k5dwgcpl/modules/modules.tar
93 19:02:45.699869 total size: 11601668 (11 MB)
94 19:02:45.700116 Using unxz to decompress xz
95 19:02:45.732258 progress 0 % (0 MB)
96 19:02:45.797854 progress 5 % (0 MB)
97 19:02:45.870798 progress 10 % (1 MB)
98 19:02:45.965616 progress 15 % (1 MB)
99 19:02:46.056122 progress 20 % (2 MB)
100 19:02:46.135247 progress 25 % (2 MB)
101 19:02:46.209920 progress 30 % (3 MB)
102 19:02:46.282956 progress 35 % (3 MB)
103 19:02:46.358660 progress 40 % (4 MB)
104 19:02:46.434307 progress 45 % (5 MB)
105 19:02:46.517516 progress 50 % (5 MB)
106 19:02:46.594377 progress 55 % (6 MB)
107 19:02:46.678178 progress 60 % (6 MB)
108 19:02:46.757932 progress 65 % (7 MB)
109 19:02:46.834752 progress 70 % (7 MB)
110 19:02:46.915638 progress 75 % (8 MB)
111 19:02:46.998778 progress 80 % (8 MB)
112 19:02:47.073804 progress 85 % (9 MB)
113 19:02:47.155609 progress 90 % (9 MB)
114 19:02:47.232086 progress 95 % (10 MB)
115 19:02:47.308524 progress 100 % (11 MB)
116 19:02:47.318845 11 MB downloaded in 1.62 s (6.83 MB/s)
117 19:02:47.319430 end: 1.4.1 http-download (duration 00:00:02) [common]
119 19:02:47.320887 end: 1.4 download-retry (duration 00:00:02) [common]
120 19:02:47.321512 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 19:02:47.322088 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 19:02:47.322629 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:02:47.323180 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 19:02:47.324325 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub
125 19:02:47.325261 makedir: /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin
126 19:02:47.325956 makedir: /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/tests
127 19:02:47.326634 makedir: /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/results
128 19:02:47.327303 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-add-keys
129 19:02:47.328372 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-add-sources
130 19:02:47.329432 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-background-process-start
131 19:02:47.330501 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-background-process-stop
132 19:02:47.331589 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-common-functions
133 19:02:47.332645 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-echo-ipv4
134 19:02:47.333643 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-install-packages
135 19:02:47.334605 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-installed-packages
136 19:02:47.335558 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-os-build
137 19:02:47.336564 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-probe-channel
138 19:02:47.337585 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-probe-ip
139 19:02:47.338629 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-target-ip
140 19:02:47.339602 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-target-mac
141 19:02:47.340620 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-target-storage
142 19:02:47.341609 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-test-case
143 19:02:47.342574 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-test-event
144 19:02:47.343533 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-test-feedback
145 19:02:47.344538 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-test-raise
146 19:02:47.345551 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-test-reference
147 19:02:47.346574 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-test-runner
148 19:02:47.347549 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-test-set
149 19:02:47.348559 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-test-shell
150 19:02:47.349551 Updating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-install-packages (oe)
151 19:02:47.350607 Updating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/bin/lava-installed-packages (oe)
152 19:02:47.351498 Creating /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/environment
153 19:02:47.352297 LAVA metadata
154 19:02:47.352843 - LAVA_JOB_ID=953554
155 19:02:47.353314 - LAVA_DISPATCHER_IP=192.168.6.2
156 19:02:47.354019 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 19:02:47.355943 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 19:02:47.356639 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 19:02:47.357072 skipped lava-vland-overlay
160 19:02:47.357563 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 19:02:47.358077 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 19:02:47.358499 skipped lava-multinode-overlay
163 19:02:47.358976 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 19:02:47.359472 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 19:02:47.359944 Loading test definitions
166 19:02:47.360523 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 19:02:47.360961 Using /lava-953554 at stage 0
168 19:02:47.363087 uuid=953554_1.5.2.4.1 testdef=None
169 19:02:47.363675 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 19:02:47.364170 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 19:02:47.366005 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 19:02:47.366835 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 19:02:47.369014 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 19:02:47.369900 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 19:02:47.372003 runner path: /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/0/tests/0_igt-gpu-panfrost test_uuid 953554_1.5.2.4.1
178 19:02:47.372607 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 19:02:47.373458 Creating lava-test-runner.conf files
181 19:02:47.373668 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/953554/lava-overlay-2lncwuub/lava-953554/0 for stage 0
182 19:02:47.374006 - 0_igt-gpu-panfrost
183 19:02:47.374371 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 19:02:47.374662 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 19:02:47.398150 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 19:02:47.398556 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 19:02:47.398825 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 19:02:47.399093 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 19:02:47.399360 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 19:02:54.190037 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 19:02:54.190520 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 19:02:54.190775 extracting modules file /var/lib/lava/dispatcher/tmp/953554/tftp-deploy-k5dwgcpl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/953554/extract-overlay-ramdisk-gfaf5pxu/ramdisk
193 19:02:55.582570 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 19:02:55.583063 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 19:02:55.583343 [common] Applying overlay /var/lib/lava/dispatcher/tmp/953554/compress-overlay-ujitbs1p/overlay-1.5.2.5.tar.gz to ramdisk
196 19:02:55.583558 [common] Applying overlay /var/lib/lava/dispatcher/tmp/953554/compress-overlay-ujitbs1p/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/953554/extract-overlay-ramdisk-gfaf5pxu/ramdisk
197 19:02:55.613090 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 19:02:55.613469 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 19:02:55.613741 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 19:02:55.613966 Converting downloaded kernel to a uImage
201 19:02:55.614264 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/953554/tftp-deploy-k5dwgcpl/kernel/Image /var/lib/lava/dispatcher/tmp/953554/tftp-deploy-k5dwgcpl/kernel/uImage
202 19:02:56.104321 output: Image Name:
203 19:02:56.104744 output: Created: Thu Nov 7 19:02:55 2024
204 19:02:56.104955 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 19:02:56.105160 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 19:02:56.105363 output: Load Address: 01080000
207 19:02:56.105564 output: Entry Point: 01080000
208 19:02:56.105762 output:
209 19:02:56.106096 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 19:02:56.106359 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 19:02:56.106629 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 19:02:56.106882 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 19:02:56.107138 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 19:02:56.107390 Building ramdisk /var/lib/lava/dispatcher/tmp/953554/extract-overlay-ramdisk-gfaf5pxu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/953554/extract-overlay-ramdisk-gfaf5pxu/ramdisk
215 19:03:02.743840 >> 502380 blocks
216 19:03:23.351191 Adding RAMdisk u-boot header.
217 19:03:23.351647 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/953554/extract-overlay-ramdisk-gfaf5pxu/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/953554/extract-overlay-ramdisk-gfaf5pxu/ramdisk.cpio.gz.uboot
218 19:03:24.032959 output: Image Name:
219 19:03:24.033631 output: Created: Thu Nov 7 19:03:23 2024
220 19:03:24.034089 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 19:03:24.034537 output: Data Size: 65713101 Bytes = 64172.95 KiB = 62.67 MiB
222 19:03:24.034976 output: Load Address: 00000000
223 19:03:24.035414 output: Entry Point: 00000000
224 19:03:24.035847 output:
225 19:03:24.037045 rename /var/lib/lava/dispatcher/tmp/953554/extract-overlay-ramdisk-gfaf5pxu/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/953554/tftp-deploy-k5dwgcpl/ramdisk/ramdisk.cpio.gz.uboot
226 19:03:24.037831 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 19:03:24.038422 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 19:03:24.038996 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 19:03:24.039493 No LXC device requested
230 19:03:24.040077 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 19:03:24.040643 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 19:03:24.041184 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 19:03:24.041634 Checking files for TFTP limit of 4294967296 bytes.
234 19:03:24.044578 end: 1 tftp-deploy (duration 00:00:40) [common]
235 19:03:24.045213 start: 2 uboot-action (timeout 00:05:00) [common]
236 19:03:24.045786 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 19:03:24.046333 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 19:03:24.046882 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 19:03:24.047461 Using kernel file from prepare-kernel: 953554/tftp-deploy-k5dwgcpl/kernel/uImage
240 19:03:24.048173 substitutions:
241 19:03:24.048634 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 19:03:24.049081 - {DTB_ADDR}: 0x01070000
243 19:03:24.049522 - {DTB}: 953554/tftp-deploy-k5dwgcpl/dtb/meson-g12b-a311d-libretech-cc.dtb
244 19:03:24.049965 - {INITRD}: 953554/tftp-deploy-k5dwgcpl/ramdisk/ramdisk.cpio.gz.uboot
245 19:03:24.050401 - {KERNEL_ADDR}: 0x01080000
246 19:03:24.050836 - {KERNEL}: 953554/tftp-deploy-k5dwgcpl/kernel/uImage
247 19:03:24.051277 - {LAVA_MAC}: None
248 19:03:24.051800 - {PRESEED_CONFIG}: None
249 19:03:24.052329 - {PRESEED_LOCAL}: None
250 19:03:24.052788 - {RAMDISK_ADDR}: 0x08000000
251 19:03:24.053240 - {RAMDISK}: 953554/tftp-deploy-k5dwgcpl/ramdisk/ramdisk.cpio.gz.uboot
252 19:03:24.053683 - {ROOT_PART}: None
253 19:03:24.054113 - {ROOT}: None
254 19:03:24.054546 - {SERVER_IP}: 192.168.6.2
255 19:03:24.054981 - {TEE_ADDR}: 0x83000000
256 19:03:24.055412 - {TEE}: None
257 19:03:24.055841 Parsed boot commands:
258 19:03:24.056293 - setenv autoload no
259 19:03:24.056725 - setenv initrd_high 0xffffffff
260 19:03:24.057154 - setenv fdt_high 0xffffffff
261 19:03:24.057581 - dhcp
262 19:03:24.058011 - setenv serverip 192.168.6.2
263 19:03:24.058439 - tftpboot 0x01080000 953554/tftp-deploy-k5dwgcpl/kernel/uImage
264 19:03:24.058868 - tftpboot 0x08000000 953554/tftp-deploy-k5dwgcpl/ramdisk/ramdisk.cpio.gz.uboot
265 19:03:24.059299 - tftpboot 0x01070000 953554/tftp-deploy-k5dwgcpl/dtb/meson-g12b-a311d-libretech-cc.dtb
266 19:03:24.059729 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 19:03:24.060198 - bootm 0x01080000 0x08000000 0x01070000
268 19:03:24.060768 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 19:03:24.062407 start: 2.3 connect-device (timeout 00:05:00) [common]
271 19:03:24.062898 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 19:03:24.079699 Setting prompt string to ['lava-test: # ']
273 19:03:24.081322 end: 2.3 connect-device (duration 00:00:00) [common]
274 19:03:24.081968 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 19:03:24.082557 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 19:03:24.083111 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 19:03:24.084361 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 19:03:24.121724 >> OK - accepted request
279 19:03:24.124032 Returned 0 in 0 seconds
280 19:03:24.225144 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 19:03:24.226149 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 19:03:24.226485 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 19:03:24.226773 Setting prompt string to ['Hit any key to stop autoboot']
285 19:03:24.227030 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 19:03:24.228031 Trying 192.168.56.21...
287 19:03:24.228329 Connected to conserv1.
288 19:03:24.228561 Escape character is '^]'.
289 19:03:24.384467
290 19:03:24.384892 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 19:03:24.385176
292 19:03:35.877956 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
293 19:03:35.878676 bl2_stage_init 0x81
294 19:03:35.883493 hw id: 0x0000 - pwm id 0x01
295 19:03:35.884259 bl2_stage_init 0xc1
296 19:03:35.884748 bl2_stage_init 0x02
297 19:03:35.885201
298 19:03:35.888968 L0:00000000
299 19:03:35.889439 L1:20000703
300 19:03:35.889882 L2:00008067
301 19:03:35.890311 L3:14000000
302 19:03:35.890735 B2:00402000
303 19:03:35.891934 B1:e0f83180
304 19:03:35.892435
305 19:03:35.892869 TE: 58150
306 19:03:35.893299
307 19:03:35.902983 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
308 19:03:35.903450
309 19:03:35.903887 Board ID = 1
310 19:03:35.904358 Set A53 clk to 24M
311 19:03:35.904786 Set A73 clk to 24M
312 19:03:35.908596 Set clk81 to 24M
313 19:03:35.909066 A53 clk: 1200 MHz
314 19:03:35.909495 A73 clk: 1200 MHz
315 19:03:35.912229 CLK81: 166.6M
316 19:03:35.912684 smccc: 00012aac
317 19:03:35.917743 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
318 19:03:35.923307 board id: 1
319 19:03:35.928594 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
320 19:03:35.938967 fw parse done
321 19:03:35.944911 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
322 19:03:35.987542 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
323 19:03:35.998422 PIEI prepare done
324 19:03:35.998881 fastboot data load
325 19:03:35.999313 fastboot data verify
326 19:03:36.004029 verify result: 266
327 19:03:36.009633 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
328 19:03:36.010093 LPDDR4 probe
329 19:03:36.010521 ddr clk to 1584MHz
330 19:03:36.017661 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
331 19:03:36.055005
332 19:03:36.055523 dmc_version 0001
333 19:03:36.061537 Check phy result
334 19:03:36.067409 INFO : End of CA training
335 19:03:36.067900 INFO : End of initialization
336 19:03:36.073002 INFO : Training has run successfully!
337 19:03:36.073467 Check phy result
338 19:03:36.078594 INFO : End of initialization
339 19:03:36.079055 INFO : End of read enable training
340 19:03:36.084205 INFO : End of fine write leveling
341 19:03:36.089856 INFO : End of Write leveling coarse delay
342 19:03:36.090322 INFO : Training has run successfully!
343 19:03:36.090764 Check phy result
344 19:03:36.095392 INFO : End of initialization
345 19:03:36.095859 INFO : End of read dq deskew training
346 19:03:36.100998 INFO : End of MPR read delay center optimization
347 19:03:36.106580 INFO : End of write delay center optimization
348 19:03:36.112189 INFO : End of read delay center optimization
349 19:03:36.112651 INFO : End of max read latency training
350 19:03:36.117840 INFO : Training has run successfully!
351 19:03:36.118327 1D training succeed
352 19:03:36.127033 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
353 19:03:36.174611 Check phy result
354 19:03:36.175110 INFO : End of initialization
355 19:03:36.196311 INFO : End of 2D read delay Voltage center optimization
356 19:03:36.216603 INFO : End of 2D read delay Voltage center optimization
357 19:03:36.268597 INFO : End of 2D write delay Voltage center optimization
358 19:03:36.317986 INFO : End of 2D write delay Voltage center optimization
359 19:03:36.323580 INFO : Training has run successfully!
360 19:03:36.324114
361 19:03:36.324576 channel==0
362 19:03:36.329153 RxClkDly_Margin_A0==88 ps 9
363 19:03:36.329626 TxDqDly_Margin_A0==98 ps 10
364 19:03:36.334762 RxClkDly_Margin_A1==88 ps 9
365 19:03:36.335242 TxDqDly_Margin_A1==88 ps 9
366 19:03:36.335692 TrainedVREFDQ_A0==74
367 19:03:36.340347 TrainedVREFDQ_A1==74
368 19:03:36.340825 VrefDac_Margin_A0==25
369 19:03:36.341269 DeviceVref_Margin_A0==40
370 19:03:36.345945 VrefDac_Margin_A1==25
371 19:03:36.346405 DeviceVref_Margin_A1==40
372 19:03:36.346845
373 19:03:36.347282
374 19:03:36.347720 channel==1
375 19:03:36.351523 RxClkDly_Margin_A0==98 ps 10
376 19:03:36.352016 TxDqDly_Margin_A0==88 ps 9
377 19:03:36.357196 RxClkDly_Margin_A1==88 ps 9
378 19:03:36.357674 TxDqDly_Margin_A1==88 ps 9
379 19:03:36.362762 TrainedVREFDQ_A0==77
380 19:03:36.363233 TrainedVREFDQ_A1==77
381 19:03:36.363682 VrefDac_Margin_A0==22
382 19:03:36.368328 DeviceVref_Margin_A0==37
383 19:03:36.368794 VrefDac_Margin_A1==24
384 19:03:36.373935 DeviceVref_Margin_A1==37
385 19:03:36.374403
386 19:03:36.374849 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
387 19:03:36.375288
388 19:03:36.407844 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
389 19:03:36.408460 2D training succeed
390 19:03:36.413236 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
391 19:03:36.418837 auto size-- 65535DDR cs0 size: 2048MB
392 19:03:36.419325 DDR cs1 size: 2048MB
393 19:03:36.424350 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
394 19:03:36.424827 cs0 DataBus test pass
395 19:03:36.429924 cs1 DataBus test pass
396 19:03:36.430392 cs0 AddrBus test pass
397 19:03:36.430837 cs1 AddrBus test pass
398 19:03:36.431276
399 19:03:36.435512 100bdlr_step_size ps== 420
400 19:03:36.436021 result report
401 19:03:36.441122 boot times 0Enable ddr reg access
402 19:03:36.446342 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
403 19:03:36.459799 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
404 19:03:37.033707 0.0;M3 CHK:0;cm4_sp_mode 0
405 19:03:37.034397 MVN_1=0x00000000
406 19:03:37.038987 MVN_2=0x00000000
407 19:03:37.044711 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
408 19:03:37.045200 OPS=0x10
409 19:03:37.045660 ring efuse init
410 19:03:37.046109 chipver efuse init
411 19:03:37.050297 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
412 19:03:37.056025 [0.018961 Inits done]
413 19:03:37.056521 secure task start!
414 19:03:37.056980 high task start!
415 19:03:37.060509 low task start!
416 19:03:37.060997 run into bl31
417 19:03:37.067149 NOTICE: BL31: v1.3(release):4fc40b1
418 19:03:37.075058 NOTICE: BL31: Built : 15:58:17, May 22 2019
419 19:03:37.075538 NOTICE: BL31: G12A normal boot!
420 19:03:37.100982 NOTICE: BL31: BL33 decompress pass
421 19:03:37.106587 ERROR: Error initializing runtime service opteed_fast
422 19:03:38.339581
423 19:03:38.340323
424 19:03:38.347819 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
425 19:03:38.348368
426 19:03:38.348832 Model: Libre Computer AML-A311D-CC Alta
427 19:03:38.556543 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
428 19:03:38.579804 DRAM: 2 GiB (effective 3.8 GiB)
429 19:03:38.722731 Core: 408 devices, 31 uclasses, devicetree: separate
430 19:03:38.728566 WDT: Not starting watchdog@f0d0
431 19:03:38.760833 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
432 19:03:38.773325 Loading Environment from FAT... Card did not respond to voltage select! : -110
433 19:03:38.778297 ** Bad device specification mmc 0 **
434 19:03:38.788674 Card did not respond to voltage select! : -110
435 19:03:38.796232 ** Bad device specification mmc 0 **
436 19:03:38.796775 Couldn't find partition mmc 0
437 19:03:38.804530 Card did not respond to voltage select! : -110
438 19:03:38.809991 ** Bad device specification mmc 0 **
439 19:03:38.810479 Couldn't find partition mmc 0
440 19:03:38.815070 Error: could not access storage.
441 19:03:40.077205 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
442 19:03:40.077819 bl2_stage_init 0x01
443 19:03:40.078245 bl2_stage_init 0x81
444 19:03:40.082858 hw id: 0x0000 - pwm id 0x01
445 19:03:40.083337 bl2_stage_init 0xc1
446 19:03:40.083751 bl2_stage_init 0x02
447 19:03:40.084206
448 19:03:40.088422 L0:00000000
449 19:03:40.088881 L1:20000703
450 19:03:40.089289 L2:00008067
451 19:03:40.089686 L3:14000000
452 19:03:40.094023 B2:00402000
453 19:03:40.094480 B1:e0f83180
454 19:03:40.094887
455 19:03:40.095286 TE: 58159
456 19:03:40.095685
457 19:03:40.099601 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 19:03:40.100093
459 19:03:40.100509 Board ID = 1
460 19:03:40.105226 Set A53 clk to 24M
461 19:03:40.105687 Set A73 clk to 24M
462 19:03:40.106091 Set clk81 to 24M
463 19:03:40.110798 A53 clk: 1200 MHz
464 19:03:40.111260 A73 clk: 1200 MHz
465 19:03:40.111666 CLK81: 166.6M
466 19:03:40.112097 smccc: 00012ab4
467 19:03:40.116412 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 19:03:40.122025 board id: 1
469 19:03:40.127848 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 19:03:40.138546 fw parse done
471 19:03:40.144493 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 19:03:40.187090 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 19:03:40.198080 PIEI prepare done
474 19:03:40.198547 fastboot data load
475 19:03:40.198963 fastboot data verify
476 19:03:40.203729 verify result: 266
477 19:03:40.209304 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 19:03:40.209767 LPDDR4 probe
479 19:03:40.210172 ddr clk to 1584MHz
480 19:03:40.217349 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 19:03:40.254618
482 19:03:40.255115 dmc_version 0001
483 19:03:40.261203 Check phy result
484 19:03:40.267075 INFO : End of CA training
485 19:03:40.267531 INFO : End of initialization
486 19:03:40.272675 INFO : Training has run successfully!
487 19:03:40.273131 Check phy result
488 19:03:40.278288 INFO : End of initialization
489 19:03:40.278756 INFO : End of read enable training
490 19:03:40.281608 INFO : End of fine write leveling
491 19:03:40.287102 INFO : End of Write leveling coarse delay
492 19:03:40.292705 INFO : Training has run successfully!
493 19:03:40.293159 Check phy result
494 19:03:40.293567 INFO : End of initialization
495 19:03:40.298354 INFO : End of read dq deskew training
496 19:03:40.303889 INFO : End of MPR read delay center optimization
497 19:03:40.304387 INFO : End of write delay center optimization
498 19:03:40.309496 INFO : End of read delay center optimization
499 19:03:40.315121 INFO : End of max read latency training
500 19:03:40.315577 INFO : Training has run successfully!
501 19:03:40.320767 1D training succeed
502 19:03:40.326687 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 19:03:40.374301 Check phy result
504 19:03:40.374960 INFO : End of initialization
505 19:03:40.396152 INFO : End of 2D read delay Voltage center optimization
506 19:03:40.416955 INFO : End of 2D read delay Voltage center optimization
507 19:03:40.468486 INFO : End of 2D write delay Voltage center optimization
508 19:03:40.517791 INFO : End of 2D write delay Voltage center optimization
509 19:03:40.523394 INFO : Training has run successfully!
510 19:03:40.523887
511 19:03:40.524351 channel==0
512 19:03:40.528908 RxClkDly_Margin_A0==88 ps 9
513 19:03:40.529382 TxDqDly_Margin_A0==98 ps 10
514 19:03:40.532266 RxClkDly_Margin_A1==88 ps 9
515 19:03:40.532741 TxDqDly_Margin_A1==98 ps 10
516 19:03:40.537873 TrainedVREFDQ_A0==74
517 19:03:40.538366 TrainedVREFDQ_A1==74
518 19:03:40.538781 VrefDac_Margin_A0==25
519 19:03:40.543463 DeviceVref_Margin_A0==40
520 19:03:40.543948 VrefDac_Margin_A1==25
521 19:03:40.549064 DeviceVref_Margin_A1==40
522 19:03:40.549561
523 19:03:40.549974
524 19:03:40.550373 channel==1
525 19:03:40.550766 RxClkDly_Margin_A0==98 ps 10
526 19:03:40.554644 TxDqDly_Margin_A0==88 ps 9
527 19:03:40.555126 RxClkDly_Margin_A1==98 ps 10
528 19:03:40.560244 TxDqDly_Margin_A1==88 ps 9
529 19:03:40.560734 TrainedVREFDQ_A0==77
530 19:03:40.561143 TrainedVREFDQ_A1==77
531 19:03:40.565859 VrefDac_Margin_A0==22
532 19:03:40.566346 DeviceVref_Margin_A0==37
533 19:03:40.571435 VrefDac_Margin_A1==22
534 19:03:40.571905 DeviceVref_Margin_A1==37
535 19:03:40.572345
536 19:03:40.576971 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 19:03:40.577442
538 19:03:40.864143 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
539 19:03:40.864728 2D training succeed
540 19:03:40.865156 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 19:03:40.865565 auto size-- 65535DDR cs0 size: 2048MB
542 19:03:40.865966 DDR cs1 size: 2048MB
543 19:03:40.866360 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 19:03:40.866785 cs0 DataBus test pass
545 19:03:40.867228 cs1 DataBus test pass
546 19:03:40.867633 cs0 AddrBus test pass
547 19:03:40.868059 cs1 AddrBus test pass
548 19:03:40.868464
549 19:03:40.868870 100bdlr_step_size ps== 420
550 19:03:40.869278 result report
551 19:03:40.869670 boot times 0Enable ddr reg access
552 19:03:40.870061 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 19:03:40.870845 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 19:03:41.234017 0.0;M3 CHK:0;cm4_sp_mode 0
555 19:03:41.234843 MVN_1=0x00000000
556 19:03:41.239166 MVN_2=0x00000000
557 19:03:41.244847 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 19:03:41.245495 OPS=0x10
559 19:03:41.246064 ring efuse init
560 19:03:41.246621 chipver efuse init
561 19:03:41.250412 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 19:03:41.256272 [0.018961 Inits done]
563 19:03:41.256861 secure task start!
564 19:03:41.257369 high task start!
565 19:03:41.260657 low task start!
566 19:03:41.261230 run into bl31
567 19:03:41.267211 NOTICE: BL31: v1.3(release):4fc40b1
568 19:03:41.275125 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 19:03:41.275713 NOTICE: BL31: G12A normal boot!
570 19:03:41.300904 NOTICE: BL31: BL33 decompress pass
571 19:03:41.306563 ERROR: Error initializing runtime service opteed_fast
572 19:03:42.539643
573 19:03:42.540305
574 19:03:42.547916 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 19:03:42.548426
576 19:03:42.548830 Model: Libre Computer AML-A311D-CC Alta
577 19:03:42.756253 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 19:03:42.779618 DRAM: 2 GiB (effective 3.8 GiB)
579 19:03:42.922573 Core: 408 devices, 31 uclasses, devicetree: separate
580 19:03:42.928425 WDT: Not starting watchdog@f0d0
581 19:03:42.960794 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 19:03:42.973142 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 19:03:42.978161 ** Bad device specification mmc 0 **
584 19:03:42.988489 Card did not respond to voltage select! : -110
585 19:03:42.996209 ** Bad device specification mmc 0 **
586 19:03:42.996835 Couldn't find partition mmc 0
587 19:03:43.004510 Card did not respond to voltage select! : -110
588 19:03:43.009964 ** Bad device specification mmc 0 **
589 19:03:43.010418 Couldn't find partition mmc 0
590 19:03:43.015019 Error: could not access storage.
591 19:03:43.357577 Net: eth0: ethernet@ff3f0000
592 19:03:43.358181 starting USB...
593 19:03:43.609498 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 19:03:43.610117 Starting the controller
595 19:03:43.616437 USB XHCI 1.10
596 19:03:45.329284 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 19:03:45.329935 bl2_stage_init 0x01
598 19:03:45.331735 bl2_stage_init 0x81
599 19:03:45.334871 hw id: 0x0000 - pwm id 0x01
600 19:03:45.335416 bl2_stage_init 0xc1
601 19:03:45.335838 bl2_stage_init 0x02
602 19:03:45.336292
603 19:03:45.340465 L0:00000000
604 19:03:45.341006 L1:20000703
605 19:03:45.341427 L2:00008067
606 19:03:45.341833 L3:14000000
607 19:03:45.346042 B2:00402000
608 19:03:45.346569 B1:e0f83180
609 19:03:45.346989
610 19:03:45.347399 TE: 58124
611 19:03:45.347804
612 19:03:45.351632 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 19:03:45.352204
614 19:03:45.352633 Board ID = 1
615 19:03:45.357219 Set A53 clk to 24M
616 19:03:45.357763 Set A73 clk to 24M
617 19:03:45.358173 Set clk81 to 24M
618 19:03:45.362786 A53 clk: 1200 MHz
619 19:03:45.363314 A73 clk: 1200 MHz
620 19:03:45.363732 CLK81: 166.6M
621 19:03:45.364176 smccc: 00012a92
622 19:03:45.368417 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 19:03:45.374054 board id: 1
624 19:03:45.379093 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 19:03:45.390658 fw parse done
626 19:03:45.396548 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 19:03:45.439044 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 19:03:45.449986 PIEI prepare done
629 19:03:45.450531 fastboot data load
630 19:03:45.450952 fastboot data verify
631 19:03:45.455639 verify result: 266
632 19:03:45.461203 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 19:03:45.461750 LPDDR4 probe
634 19:03:45.462172 ddr clk to 1584MHz
635 19:03:45.469276 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 19:03:45.506421
637 19:03:45.506976 dmc_version 0001
638 19:03:45.513144 Check phy result
639 19:03:45.518974 INFO : End of CA training
640 19:03:45.519500 INFO : End of initialization
641 19:03:45.524629 INFO : Training has run successfully!
642 19:03:45.525155 Check phy result
643 19:03:45.530169 INFO : End of initialization
644 19:03:45.530677 INFO : End of read enable training
645 19:03:45.535746 INFO : End of fine write leveling
646 19:03:45.541369 INFO : End of Write leveling coarse delay
647 19:03:45.541875 INFO : Training has run successfully!
648 19:03:45.542286 Check phy result
649 19:03:45.547040 INFO : End of initialization
650 19:03:45.547539 INFO : End of read dq deskew training
651 19:03:45.552623 INFO : End of MPR read delay center optimization
652 19:03:45.558153 INFO : End of write delay center optimization
653 19:03:45.563744 INFO : End of read delay center optimization
654 19:03:45.564295 INFO : End of max read latency training
655 19:03:45.569352 INFO : Training has run successfully!
656 19:03:45.569856 1D training succeed
657 19:03:45.578434 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 19:03:45.626145 Check phy result
659 19:03:45.626701 INFO : End of initialization
660 19:03:45.647764 INFO : End of 2D read delay Voltage center optimization
661 19:03:45.667833 INFO : End of 2D read delay Voltage center optimization
662 19:03:45.719712 INFO : End of 2D write delay Voltage center optimization
663 19:03:45.768997 INFO : End of 2D write delay Voltage center optimization
664 19:03:45.774536 INFO : Training has run successfully!
665 19:03:45.775029
666 19:03:45.775443 channel==0
667 19:03:45.780236 RxClkDly_Margin_A0==88 ps 9
668 19:03:45.780734 TxDqDly_Margin_A0==98 ps 10
669 19:03:45.785717 RxClkDly_Margin_A1==88 ps 9
670 19:03:45.786236 TxDqDly_Margin_A1==88 ps 9
671 19:03:45.786671 TrainedVREFDQ_A0==74
672 19:03:45.791388 TrainedVREFDQ_A1==74
673 19:03:45.791901 VrefDac_Margin_A0==25
674 19:03:45.792361 DeviceVref_Margin_A0==40
675 19:03:45.796946 VrefDac_Margin_A1==25
676 19:03:45.797431 DeviceVref_Margin_A1==40
677 19:03:45.797842
678 19:03:45.798242
679 19:03:45.798644 channel==1
680 19:03:45.802532 RxClkDly_Margin_A0==98 ps 10
681 19:03:45.803009 TxDqDly_Margin_A0==98 ps 10
682 19:03:45.808241 RxClkDly_Margin_A1==98 ps 10
683 19:03:45.808891 TxDqDly_Margin_A1==98 ps 10
684 19:03:45.813726 TrainedVREFDQ_A0==77
685 19:03:45.814208 TrainedVREFDQ_A1==77
686 19:03:45.814623 VrefDac_Margin_A0==22
687 19:03:45.819368 DeviceVref_Margin_A0==37
688 19:03:45.819856 VrefDac_Margin_A1==22
689 19:03:45.824893 DeviceVref_Margin_A1==37
690 19:03:45.825365
691 19:03:45.825775 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 19:03:45.830503
693 19:03:45.858430 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
694 19:03:45.858958 2D training succeed
695 19:03:45.864241 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 19:03:45.869727 auto size-- 65535DDR cs0 size: 2048MB
697 19:03:45.870218 DDR cs1 size: 2048MB
698 19:03:45.875313 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 19:03:45.875792 cs0 DataBus test pass
700 19:03:45.880867 cs1 DataBus test pass
701 19:03:45.881335 cs0 AddrBus test pass
702 19:03:45.881738 cs1 AddrBus test pass
703 19:03:45.882135
704 19:03:45.886502 100bdlr_step_size ps== 420
705 19:03:45.886989 result report
706 19:03:45.892196 boot times 0Enable ddr reg access
707 19:03:45.897527 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 19:03:45.910948 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 19:03:46.482900 0.0;M3 CHK:0;cm4_sp_mode 0
710 19:03:46.483508 MVN_1=0x00000000
711 19:03:46.488457 MVN_2=0x00000000
712 19:03:46.494261 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 19:03:46.494755 OPS=0x10
714 19:03:46.495152 ring efuse init
715 19:03:46.495540 chipver efuse init
716 19:03:46.499790 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 19:03:46.505387 [0.018961 Inits done]
718 19:03:46.505844 secure task start!
719 19:03:46.506235 high task start!
720 19:03:46.509965 low task start!
721 19:03:46.510419 run into bl31
722 19:03:46.516805 NOTICE: BL31: v1.3(release):4fc40b1
723 19:03:46.524663 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 19:03:46.525344 NOTICE: BL31: G12A normal boot!
725 19:03:46.549961 NOTICE: BL31: BL33 decompress pass
726 19:03:46.554546 ERROR: Error initializing runtime service opteed_fast
727 19:03:47.788450
728 19:03:47.789035
729 19:03:47.796798 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 19:03:47.797270
731 19:03:47.797682 Model: Libre Computer AML-A311D-CC Alta
732 19:03:48.005189 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 19:03:48.028584 DRAM: 2 GiB (effective 3.8 GiB)
734 19:03:48.171698 Core: 408 devices, 31 uclasses, devicetree: separate
735 19:03:48.176780 WDT: Not starting watchdog@f0d0
736 19:03:48.209822 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 19:03:48.222244 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 19:03:48.226290 ** Bad device specification mmc 0 **
739 19:03:48.237417 Card did not respond to voltage select! : -110
740 19:03:48.245052 ** Bad device specification mmc 0 **
741 19:03:48.245559 Couldn't find partition mmc 0
742 19:03:48.253403 Card did not respond to voltage select! : -110
743 19:03:48.258872 ** Bad device specification mmc 0 **
744 19:03:48.259360 Couldn't find partition mmc 0
745 19:03:48.263924 Error: could not access storage.
746 19:03:48.606697 Net: eth0: ethernet@ff3f0000
747 19:03:48.607322 starting USB...
748 19:03:48.858262 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 19:03:48.858858 Starting the controller
750 19:03:48.865191 USB XHCI 1.10
751 19:03:51.027678 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 19:03:51.028126 bl2_stage_init 0x01
753 19:03:51.028410 bl2_stage_init 0x81
754 19:03:51.033093 hw id: 0x0000 - pwm id 0x01
755 19:03:51.033422 bl2_stage_init 0xc1
756 19:03:51.033691 bl2_stage_init 0x02
757 19:03:51.033952
758 19:03:51.038730 L0:00000000
759 19:03:51.039048 L1:20000703
760 19:03:51.039314 L2:00008067
761 19:03:51.039559 L3:14000000
762 19:03:51.044317 B2:00402000
763 19:03:51.044729 B1:e0f83180
764 19:03:51.045352
765 19:03:51.046183 TE: 58124
766 19:03:51.046568
767 19:03:51.049875 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 19:03:51.050262
769 19:03:51.050759 Board ID = 1
770 19:03:51.055528 Set A53 clk to 24M
771 19:03:51.055925 Set A73 clk to 24M
772 19:03:51.056291 Set clk81 to 24M
773 19:03:51.061076 A53 clk: 1200 MHz
774 19:03:51.061476 A73 clk: 1200 MHz
775 19:03:51.061831 CLK81: 166.6M
776 19:03:51.062213 smccc: 00012a92
777 19:03:51.066640 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 19:03:51.072259 board id: 1
779 19:03:51.078106 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 19:03:51.088740 fw parse done
781 19:03:51.094845 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 19:03:51.137377 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 19:03:51.148247 PIEI prepare done
784 19:03:51.148605 fastboot data load
785 19:03:51.148873 fastboot data verify
786 19:03:51.153881 verify result: 266
787 19:03:51.159466 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 19:03:51.159787 LPDDR4 probe
789 19:03:51.160086 ddr clk to 1584MHz
790 19:03:51.167465 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 19:03:51.204901
792 19:03:51.205263 dmc_version 0001
793 19:03:51.210679 Check phy result
794 19:03:51.217256 INFO : End of CA training
795 19:03:51.217565 INFO : End of initialization
796 19:03:51.222932 INFO : Training has run successfully!
797 19:03:51.223241 Check phy result
798 19:03:51.228568 INFO : End of initialization
799 19:03:51.228882 INFO : End of read enable training
800 19:03:51.231869 INFO : End of fine write leveling
801 19:03:51.237456 INFO : End of Write leveling coarse delay
802 19:03:51.242982 INFO : Training has run successfully!
803 19:03:51.243299 Check phy result
804 19:03:51.243559 INFO : End of initialization
805 19:03:51.248630 INFO : End of read dq deskew training
806 19:03:51.254252 INFO : End of MPR read delay center optimization
807 19:03:51.254663 INFO : End of write delay center optimization
808 19:03:51.259875 INFO : End of read delay center optimization
809 19:03:51.265488 INFO : End of max read latency training
810 19:03:51.266073 INFO : Training has run successfully!
811 19:03:51.271054 1D training succeed
812 19:03:51.276934 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 19:03:51.324491 Check phy result
814 19:03:51.324846 INFO : End of initialization
815 19:03:51.346191 INFO : End of 2D read delay Voltage center optimization
816 19:03:51.366416 INFO : End of 2D read delay Voltage center optimization
817 19:03:51.417985 INFO : End of 2D write delay Voltage center optimization
818 19:03:51.468155 INFO : End of 2D write delay Voltage center optimization
819 19:03:51.473522 INFO : Training has run successfully!
820 19:03:51.474023
821 19:03:51.474450 channel==0
822 19:03:51.479111 RxClkDly_Margin_A0==88 ps 9
823 19:03:51.479875 TxDqDly_Margin_A0==98 ps 10
824 19:03:51.484804 RxClkDly_Margin_A1==88 ps 9
825 19:03:51.485277 TxDqDly_Margin_A1==88 ps 9
826 19:03:51.485714 TrainedVREFDQ_A0==74
827 19:03:51.490355 TrainedVREFDQ_A1==74
828 19:03:51.490898 VrefDac_Margin_A0==24
829 19:03:51.491321 DeviceVref_Margin_A0==40
830 19:03:51.496007 VrefDac_Margin_A1==25
831 19:03:51.496499 DeviceVref_Margin_A1==40
832 19:03:51.496893
833 19:03:51.497246
834 19:03:51.497480 channel==1
835 19:03:51.501475 RxClkDly_Margin_A0==98 ps 10
836 19:03:51.501813 TxDqDly_Margin_A0==98 ps 10
837 19:03:51.507102 RxClkDly_Margin_A1==88 ps 9
838 19:03:51.507422 TxDqDly_Margin_A1==98 ps 10
839 19:03:51.512615 TrainedVREFDQ_A0==77
840 19:03:51.512947 TrainedVREFDQ_A1==77
841 19:03:51.513171 VrefDac_Margin_A0==22
842 19:03:51.518303 DeviceVref_Margin_A0==37
843 19:03:51.518620 VrefDac_Margin_A1==24
844 19:03:51.524001 DeviceVref_Margin_A1==37
845 19:03:51.524318
846 19:03:51.524544 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 19:03:51.524760
848 19:03:51.557506 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
849 19:03:51.557926 2D training succeed
850 19:03:51.563044 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 19:03:51.568649 auto size-- 65535DDR cs0 size: 2048MB
852 19:03:51.569003 DDR cs1 size: 2048MB
853 19:03:51.574211 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 19:03:51.574564 cs0 DataBus test pass
855 19:03:51.580011 cs1 DataBus test pass
856 19:03:51.580376 cs0 AddrBus test pass
857 19:03:51.580579 cs1 AddrBus test pass
858 19:03:51.580774
859 19:03:51.585389 100bdlr_step_size ps== 420
860 19:03:51.585649 result report
861 19:03:51.591016 boot times 0Enable ddr reg access
862 19:03:51.595462 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 19:03:51.608876 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 19:03:52.183528 0.0;M3 CHK:0;cm4_sp_mode 0
865 19:03:52.184211 MVN_1=0x00000000
866 19:03:52.189068 MVN_2=0x00000000
867 19:03:52.194844 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 19:03:52.195474 OPS=0x10
869 19:03:52.196066 ring efuse init
870 19:03:52.196601 chipver efuse init
871 19:03:52.200422 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 19:03:52.206067 [0.018961 Inits done]
873 19:03:52.206679 secure task start!
874 19:03:52.207207 high task start!
875 19:03:52.209990 low task start!
876 19:03:52.210590 run into bl31
877 19:03:52.217280 NOTICE: BL31: v1.3(release):4fc40b1
878 19:03:52.225198 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 19:03:52.225820 NOTICE: BL31: G12A normal boot!
880 19:03:52.250454 NOTICE: BL31: BL33 decompress pass
881 19:03:52.255520 ERROR: Error initializing runtime service opteed_fast
882 19:03:53.488878
883 19:03:53.489546
884 19:03:53.496534 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 19:03:53.497031
886 19:03:53.497485 Model: Libre Computer AML-A311D-CC Alta
887 19:03:53.704842 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 19:03:53.728358 DRAM: 2 GiB (effective 3.8 GiB)
889 19:03:53.872079 Core: 408 devices, 31 uclasses, devicetree: separate
890 19:03:53.877547 WDT: Not starting watchdog@f0d0
891 19:03:53.910175 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 19:03:53.922633 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 19:03:53.926827 ** Bad device specification mmc 0 **
894 19:03:53.937983 Card did not respond to voltage select! : -110
895 19:03:53.945634 ** Bad device specification mmc 0 **
896 19:03:53.946105 Couldn't find partition mmc 0
897 19:03:53.953980 Card did not respond to voltage select! : -110
898 19:03:53.959438 ** Bad device specification mmc 0 **
899 19:03:53.959911 Couldn't find partition mmc 0
900 19:03:53.963886 Error: could not access storage.
901 19:03:54.306051 Net: eth0: ethernet@ff3f0000
902 19:03:54.306687 starting USB...
903 19:03:54.558871 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 19:03:54.559277 Starting the controller
905 19:03:54.564828 USB XHCI 1.10
906 19:03:56.119860 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 19:03:56.128121 scanning usb for storage devices... 0 Storage Device(s) found
909 19:03:56.179165 Hit any key to stop autoboot: 1
910 19:03:56.179885 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 19:03:56.180279 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 19:03:56.180575 Setting prompt string to ['=>']
913 19:03:56.180862 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 19:03:56.185666 0
915 19:03:56.186314 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 19:03:56.186618 Sending with 10 millisecond of delay
918 19:03:57.321469 => setenv autoload no
919 19:03:57.332213 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
920 19:03:57.337049 setenv autoload no
921 19:03:57.337765 Sending with 10 millisecond of delay
923 19:03:59.135196 => setenv initrd_high 0xffffffff
924 19:03:59.145999 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 19:03:59.146881 setenv initrd_high 0xffffffff
926 19:03:59.147574 Sending with 10 millisecond of delay
928 19:04:00.764330 => setenv fdt_high 0xffffffff
929 19:04:00.775093 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
930 19:04:00.775902 setenv fdt_high 0xffffffff
931 19:04:00.776648 Sending with 10 millisecond of delay
933 19:04:01.068530 => dhcp
934 19:04:01.079278 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 19:04:01.080129 dhcp
936 19:04:01.080565 Speed: 1000, full duplex
937 19:04:01.080978 BOOTP broadcast 1
938 19:04:01.087223 DHCP client bound to address 192.168.6.27 (8 ms)
939 19:04:01.087941 Sending with 10 millisecond of delay
941 19:04:02.765784 => setenv serverip 192.168.6.2
942 19:04:02.776593 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
943 19:04:02.777461 setenv serverip 192.168.6.2
944 19:04:02.778215 Sending with 10 millisecond of delay
946 19:04:06.503658 => tftpboot 0x01080000 953554/tftp-deploy-k5dwgcpl/kernel/uImage
947 19:04:06.514455 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
948 19:04:06.515018 tftpboot 0x01080000 953554/tftp-deploy-k5dwgcpl/kernel/uImage
949 19:04:06.515259 Speed: 1000, full duplex
950 19:04:06.515472 Using ethernet@ff3f0000 device
951 19:04:06.516974 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
952 19:04:06.522515 Filename '953554/tftp-deploy-k5dwgcpl/kernel/uImage'.
953 19:04:06.526350 Load address: 0x1080000
954 19:04:09.451761 Loading: *################################################## 43.6 MiB
955 19:04:09.454842 14.9 MiB/s
956 19:04:09.455162 done
957 19:04:09.456007 Bytes transferred = 45713984 (2b98a40 hex)
958 19:04:09.456487 Sending with 10 millisecond of delay
960 19:04:14.142580 => tftpboot 0x08000000 953554/tftp-deploy-k5dwgcpl/ramdisk/ramdisk.cpio.gz.uboot
961 19:04:14.153379 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
962 19:04:14.154213 tftpboot 0x08000000 953554/tftp-deploy-k5dwgcpl/ramdisk/ramdisk.cpio.gz.uboot
963 19:04:14.154667 Speed: 1000, full duplex
964 19:04:14.155083 Using ethernet@ff3f0000 device
965 19:04:14.156183 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
966 19:04:14.164673 Filename '953554/tftp-deploy-k5dwgcpl/ramdisk/ramdisk.cpio.gz.uboot'.
967 19:04:14.165146 Load address: 0x8000000
968 19:04:23.831091 Loading: *#######T ########################################## UDP wrong checksum 0000000f 0000d283
969 19:04:28.831935 T UDP wrong checksum 0000000f 0000d283
970 19:04:38.835117 T T UDP wrong checksum 0000000f 0000d283
971 19:04:58.837144 T T T UDP wrong checksum 0000000f 0000d283
972 19:05:13.843180 T T T
973 19:05:13.843696 Retry count exceeded; starting again
975 19:05:13.844724 end: 2.4.3 bootloader-commands (duration 00:01:18) [common]
978 19:05:13.845860 end: 2.4 uboot-commands (duration 00:01:50) [common]
980 19:05:13.846701 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
982 19:05:13.847361 end: 2 uboot-action (duration 00:01:50) [common]
984 19:05:13.848391 Cleaning after the job
985 19:05:13.848778 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953554/tftp-deploy-k5dwgcpl/ramdisk
986 19:05:13.849761 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953554/tftp-deploy-k5dwgcpl/kernel
987 19:05:13.854269 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953554/tftp-deploy-k5dwgcpl/dtb
988 19:05:13.855046 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/953554/tftp-deploy-k5dwgcpl/modules
989 19:05:13.858733 start: 4.1 power-off (timeout 00:00:30) [common]
990 19:05:13.859399 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
991 19:05:13.893680 >> OK - accepted request
992 19:05:13.895438 Returned 0 in 0 seconds
993 19:05:13.996293 end: 4.1 power-off (duration 00:00:00) [common]
995 19:05:13.997407 start: 4.2 read-feedback (timeout 00:10:00) [common]
996 19:05:13.998168 Listened to connection for namespace 'common' for up to 1s
997 19:05:14.999070 Finalising connection for namespace 'common'
998 19:05:14.999667 Disconnecting from shell: Finalise
999 19:05:15.000029 =>
1000 19:05:15.100823 end: 4.2 read-feedback (duration 00:00:01) [common]
1001 19:05:15.101385 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/953554
1002 19:05:15.682321 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/953554
1003 19:05:15.682932 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.