Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 16:20:23.633396 lava-dispatcher, installed at version: 2024.01
2 16:20:23.634198 start: 0 validate
3 16:20:23.634669 Start time: 2024-11-07 16:20:23.634639+00:00 (UTC)
4 16:20:23.635211 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 16:20:23.635748 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 16:20:23.668037 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 16:20:23.668588 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 16:20:23.689949 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 16:20:23.690606 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 16:20:23.712574 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 16:20:23.713089 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 16:20:23.734173 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 16:20:23.734644 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 16:20:23.762161 validate duration: 0.13
16 16:20:23.763070 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:20:23.763401 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:20:23.763692 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:20:23.764288 Not decompressing ramdisk as can be used compressed.
20 16:20:23.764722 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 16:20:23.765138 saving as /var/lib/lava/dispatcher/tmp/954053/tftp-deploy-4fs1nbe5/ramdisk/initrd.cpio.gz
22 16:20:23.765434 total size: 4775763 (4 MB)
23 16:20:23.796154 progress 0 % (0 MB)
24 16:20:23.799879 progress 5 % (0 MB)
25 16:20:23.803220 progress 10 % (0 MB)
26 16:20:23.806527 progress 15 % (0 MB)
27 16:20:23.810213 progress 20 % (0 MB)
28 16:20:23.813312 progress 25 % (1 MB)
29 16:20:23.816709 progress 30 % (1 MB)
30 16:20:23.820224 progress 35 % (1 MB)
31 16:20:23.823454 progress 40 % (1 MB)
32 16:20:23.826646 progress 45 % (2 MB)
33 16:20:23.830007 progress 50 % (2 MB)
34 16:20:23.835965 progress 55 % (2 MB)
35 16:20:23.842369 progress 60 % (2 MB)
36 16:20:23.850209 progress 65 % (2 MB)
37 16:20:23.857295 progress 70 % (3 MB)
38 16:20:23.862104 progress 75 % (3 MB)
39 16:20:23.865242 progress 80 % (3 MB)
40 16:20:23.868196 progress 85 % (3 MB)
41 16:20:23.871544 progress 90 % (4 MB)
42 16:20:23.874607 progress 95 % (4 MB)
43 16:20:23.877822 progress 100 % (4 MB)
44 16:20:23.878456 4 MB downloaded in 0.11 s (40.30 MB/s)
45 16:20:23.879000 end: 1.1.1 http-download (duration 00:00:00) [common]
47 16:20:23.879905 end: 1.1 download-retry (duration 00:00:00) [common]
48 16:20:23.880200 start: 1.2 download-retry (timeout 00:10:00) [common]
49 16:20:23.880472 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 16:20:23.880982 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 16:20:23.881250 saving as /var/lib/lava/dispatcher/tmp/954053/tftp-deploy-4fs1nbe5/kernel/zImage
52 16:20:23.881460 total size: 11440640 (10 MB)
53 16:20:23.881673 No compression specified
54 16:20:23.912408 progress 0 % (0 MB)
55 16:20:23.919751 progress 5 % (0 MB)
56 16:20:23.927069 progress 10 % (1 MB)
57 16:20:23.934641 progress 15 % (1 MB)
58 16:20:23.941865 progress 20 % (2 MB)
59 16:20:23.949459 progress 25 % (2 MB)
60 16:20:23.956566 progress 30 % (3 MB)
61 16:20:23.964080 progress 35 % (3 MB)
62 16:20:23.971368 progress 40 % (4 MB)
63 16:20:23.978901 progress 45 % (4 MB)
64 16:20:23.988976 progress 50 % (5 MB)
65 16:20:24.001550 progress 55 % (6 MB)
66 16:20:24.010129 progress 60 % (6 MB)
67 16:20:24.020400 progress 65 % (7 MB)
68 16:20:24.027720 progress 70 % (7 MB)
69 16:20:24.034655 progress 75 % (8 MB)
70 16:20:24.042366 progress 80 % (8 MB)
71 16:20:24.049262 progress 85 % (9 MB)
72 16:20:24.056534 progress 90 % (9 MB)
73 16:20:24.063221 progress 95 % (10 MB)
74 16:20:24.069919 progress 100 % (10 MB)
75 16:20:24.070404 10 MB downloaded in 0.19 s (57.75 MB/s)
76 16:20:24.070863 end: 1.2.1 http-download (duration 00:00:00) [common]
78 16:20:24.071667 end: 1.2 download-retry (duration 00:00:00) [common]
79 16:20:24.071936 start: 1.3 download-retry (timeout 00:10:00) [common]
80 16:20:24.072194 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 16:20:24.072652 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 16:20:24.072891 saving as /var/lib/lava/dispatcher/tmp/954053/tftp-deploy-4fs1nbe5/dtb/am335x-boneblack.dtb
83 16:20:24.073096 total size: 70568 (0 MB)
84 16:20:24.073300 No compression specified
85 16:20:24.109564 progress 46 % (0 MB)
86 16:20:24.110436 progress 92 % (0 MB)
87 16:20:24.111073 progress 100 % (0 MB)
88 16:20:24.111437 0 MB downloaded in 0.04 s (1.76 MB/s)
89 16:20:24.111880 end: 1.3.1 http-download (duration 00:00:00) [common]
91 16:20:24.112671 end: 1.3 download-retry (duration 00:00:00) [common]
92 16:20:24.112930 start: 1.4 download-retry (timeout 00:10:00) [common]
93 16:20:24.113190 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 16:20:24.113642 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 16:20:24.113934 saving as /var/lib/lava/dispatcher/tmp/954053/tftp-deploy-4fs1nbe5/nfsrootfs/full.rootfs.tar
96 16:20:24.114140 total size: 117747780 (112 MB)
97 16:20:24.114347 Using unxz to decompress xz
98 16:20:24.141759 progress 0 % (0 MB)
99 16:20:24.870934 progress 5 % (5 MB)
100 16:20:25.631601 progress 10 % (11 MB)
101 16:20:26.408339 progress 15 % (16 MB)
102 16:20:27.167677 progress 20 % (22 MB)
103 16:20:27.982130 progress 25 % (28 MB)
104 16:20:29.019339 progress 30 % (33 MB)
105 16:20:29.828973 progress 35 % (39 MB)
106 16:20:30.159522 progress 40 % (44 MB)
107 16:20:30.511154 progress 45 % (50 MB)
108 16:20:31.167677 progress 50 % (56 MB)
109 16:20:31.978406 progress 55 % (61 MB)
110 16:20:32.712284 progress 60 % (67 MB)
111 16:20:33.434786 progress 65 % (73 MB)
112 16:20:34.194859 progress 70 % (78 MB)
113 16:20:34.954529 progress 75 % (84 MB)
114 16:20:35.685648 progress 80 % (89 MB)
115 16:20:36.395123 progress 85 % (95 MB)
116 16:20:37.187853 progress 90 % (101 MB)
117 16:20:37.975220 progress 95 % (106 MB)
118 16:20:38.797433 progress 100 % (112 MB)
119 16:20:38.810966 112 MB downloaded in 14.70 s (7.64 MB/s)
120 16:20:38.811629 end: 1.4.1 http-download (duration 00:00:15) [common]
122 16:20:38.812463 end: 1.4 download-retry (duration 00:00:15) [common]
123 16:20:38.812729 start: 1.5 download-retry (timeout 00:09:45) [common]
124 16:20:38.812989 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 16:20:38.813469 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 16:20:38.813718 saving as /var/lib/lava/dispatcher/tmp/954053/tftp-deploy-4fs1nbe5/modules/modules.tar
127 16:20:38.814133 total size: 6608492 (6 MB)
128 16:20:38.814600 Using unxz to decompress xz
129 16:20:38.851020 progress 0 % (0 MB)
130 16:20:38.885927 progress 5 % (0 MB)
131 16:20:38.928804 progress 10 % (0 MB)
132 16:20:38.979461 progress 15 % (0 MB)
133 16:20:39.025246 progress 20 % (1 MB)
134 16:20:39.073312 progress 25 % (1 MB)
135 16:20:39.118897 progress 30 % (1 MB)
136 16:20:39.161392 progress 35 % (2 MB)
137 16:20:39.205283 progress 40 % (2 MB)
138 16:20:39.289284 progress 45 % (2 MB)
139 16:20:39.352195 progress 50 % (3 MB)
140 16:20:39.417149 progress 55 % (3 MB)
141 16:20:39.489755 progress 60 % (3 MB)
142 16:20:39.549353 progress 65 % (4 MB)
143 16:20:39.609970 progress 70 % (4 MB)
144 16:20:39.668932 progress 75 % (4 MB)
145 16:20:39.723868 progress 80 % (5 MB)
146 16:20:39.785118 progress 85 % (5 MB)
147 16:20:39.842056 progress 90 % (5 MB)
148 16:20:39.900662 progress 95 % (6 MB)
149 16:20:39.960982 progress 100 % (6 MB)
150 16:20:39.980580 6 MB downloaded in 1.17 s (5.40 MB/s)
151 16:20:39.981559 end: 1.5.1 http-download (duration 00:00:01) [common]
153 16:20:39.983264 end: 1.5 download-retry (duration 00:00:01) [common]
154 16:20:39.983787 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 16:20:39.984304 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 16:20:58.312944 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/954053/extract-nfsrootfs-4aocc8c3
157 16:20:58.313559 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
158 16:20:58.313879 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
159 16:20:58.314530 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m
160 16:20:58.315004 makedir: /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin
161 16:20:58.315344 makedir: /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/tests
162 16:20:58.315677 makedir: /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/results
163 16:20:58.316016 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-add-keys
164 16:20:58.316543 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-add-sources
165 16:20:58.317068 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-background-process-start
166 16:20:58.317566 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-background-process-stop
167 16:20:58.318130 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-common-functions
168 16:20:58.318634 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-echo-ipv4
169 16:20:58.319112 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-install-packages
170 16:20:58.319584 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-installed-packages
171 16:20:58.320052 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-os-build
172 16:20:58.320529 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-probe-channel
173 16:20:58.321002 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-probe-ip
174 16:20:58.321499 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-target-ip
175 16:20:58.322016 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-target-mac
176 16:20:58.322510 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-target-storage
177 16:20:58.322997 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-test-case
178 16:20:58.323493 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-test-event
179 16:20:58.323972 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-test-feedback
180 16:20:58.324440 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-test-raise
181 16:20:58.324918 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-test-reference
182 16:20:58.325424 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-test-runner
183 16:20:58.325928 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-test-set
184 16:20:58.326412 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-test-shell
185 16:20:58.326972 Updating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-add-keys (debian)
186 16:20:58.327512 Updating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-add-sources (debian)
187 16:20:58.328023 Updating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-install-packages (debian)
188 16:20:58.328517 Updating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-installed-packages (debian)
189 16:20:58.329002 Updating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/bin/lava-os-build (debian)
190 16:20:58.329430 Creating /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/environment
191 16:20:58.329794 LAVA metadata
192 16:20:58.330074 - LAVA_JOB_ID=954053
193 16:20:58.330287 - LAVA_DISPATCHER_IP=192.168.6.3
194 16:20:58.330644 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
195 16:20:58.331575 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 16:20:58.331881 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
197 16:20:58.332085 skipped lava-vland-overlay
198 16:20:58.332324 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 16:20:58.332575 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
200 16:20:58.332775 skipped lava-multinode-overlay
201 16:20:58.333010 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 16:20:58.333255 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
203 16:20:58.333498 Loading test definitions
204 16:20:58.333768 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
205 16:20:58.334045 Using /lava-954053 at stage 0
206 16:20:58.335110 uuid=954053_1.6.2.4.1 testdef=None
207 16:20:58.335403 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 16:20:58.335662 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
209 16:20:58.337180 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 16:20:58.337983 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
212 16:20:58.339913 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 16:20:58.340723 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
215 16:20:58.342535 runner path: /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/0/tests/0_timesync-off test_uuid 954053_1.6.2.4.1
216 16:20:58.343074 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 16:20:58.343876 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
219 16:20:58.344095 Using /lava-954053 at stage 0
220 16:20:58.344443 Fetching tests from https://github.com/kernelci/test-definitions.git
221 16:20:58.344731 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/0/tests/1_kselftest-dt'
222 16:21:01.744551 Running '/usr/bin/git checkout kernelci.org
223 16:21:02.191713 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 16:21:02.193157 uuid=954053_1.6.2.4.5 testdef=None
225 16:21:02.193492 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 16:21:02.194302 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
228 16:21:02.197111 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 16:21:02.197934 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
231 16:21:02.201628 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 16:21:02.202492 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
234 16:21:02.206059 runner path: /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/0/tests/1_kselftest-dt test_uuid 954053_1.6.2.4.5
235 16:21:02.206358 BOARD='beaglebone-black'
236 16:21:02.206567 BRANCH='broonie-sound'
237 16:21:02.206764 SKIPFILE='/dev/null'
238 16:21:02.206960 SKIP_INSTALL='True'
239 16:21:02.207155 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 16:21:02.207354 TST_CASENAME=''
241 16:21:02.207548 TST_CMDFILES='dt'
242 16:21:02.208085 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 16:21:02.208863 Creating lava-test-runner.conf files
245 16:21:02.209065 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/954053/lava-overlay-9mjnc58m/lava-954053/0 for stage 0
246 16:21:02.209404 - 0_timesync-off
247 16:21:02.209637 - 1_kselftest-dt
248 16:21:02.209980 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 16:21:02.210258 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
250 16:21:25.571827 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 16:21:25.572278 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
252 16:21:25.572542 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 16:21:25.572810 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 16:21:25.573073 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
255 16:21:25.926980 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 16:21:25.927422 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
257 16:21:25.927670 extracting modules file /var/lib/lava/dispatcher/tmp/954053/tftp-deploy-4fs1nbe5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954053/extract-nfsrootfs-4aocc8c3
258 16:21:26.833685 extracting modules file /var/lib/lava/dispatcher/tmp/954053/tftp-deploy-4fs1nbe5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954053/extract-overlay-ramdisk-wecv5m8k/ramdisk
259 16:21:27.745167 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 16:21:27.745648 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
261 16:21:27.745957 [common] Applying overlay to NFS
262 16:21:27.746177 [common] Applying overlay /var/lib/lava/dispatcher/tmp/954053/compress-overlay-7360hv4d/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/954053/extract-nfsrootfs-4aocc8c3
263 16:21:30.479607 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 16:21:30.480088 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
265 16:21:30.480365 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
266 16:21:30.480672 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 16:21:30.480935 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 16:21:30.481196 start: 1.6.7 configure-preseed-file (timeout 00:08:53) [common]
269 16:21:30.481450 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 16:21:30.481707 start: 1.6.8 compress-ramdisk (timeout 00:08:53) [common]
271 16:21:30.481963 Building ramdisk /var/lib/lava/dispatcher/tmp/954053/extract-overlay-ramdisk-wecv5m8k/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/954053/extract-overlay-ramdisk-wecv5m8k/ramdisk
272 16:21:31.465691 >> 74896 blocks
273 16:21:36.090434 Adding RAMdisk u-boot header.
274 16:21:36.090884 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/954053/extract-overlay-ramdisk-wecv5m8k/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/954053/extract-overlay-ramdisk-wecv5m8k/ramdisk.cpio.gz.uboot
275 16:21:36.246796 output: Image Name:
276 16:21:36.247215 output: Created: Thu Nov 7 16:21:36 2024
277 16:21:36.247427 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 16:21:36.247630 output: Data Size: 14790161 Bytes = 14443.52 KiB = 14.10 MiB
279 16:21:36.247830 output: Load Address: 00000000
280 16:21:36.248028 output: Entry Point: 00000000
281 16:21:36.248222 output:
282 16:21:36.248799 rename /var/lib/lava/dispatcher/tmp/954053/extract-overlay-ramdisk-wecv5m8k/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/954053/tftp-deploy-4fs1nbe5/ramdisk/ramdisk.cpio.gz.uboot
283 16:21:36.249209 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 16:21:36.249499 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 16:21:36.249771 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
286 16:21:36.250275 No LXC device requested
287 16:21:36.250779 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 16:21:36.251306 start: 1.8 deploy-device-env (timeout 00:08:48) [common]
289 16:21:36.251796 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 16:21:36.252202 Checking files for TFTP limit of 4294967296 bytes.
291 16:21:36.254913 end: 1 tftp-deploy (duration 00:01:12) [common]
292 16:21:36.255477 start: 2 uboot-action (timeout 00:05:00) [common]
293 16:21:36.255997 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 16:21:36.256487 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 16:21:36.256984 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 16:21:36.257735 substitutions:
297 16:21:36.258185 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 16:21:36.258590 - {DTB_ADDR}: 0x88000000
299 16:21:36.258986 - {DTB}: 954053/tftp-deploy-4fs1nbe5/dtb/am335x-boneblack.dtb
300 16:21:36.259381 - {INITRD}: 954053/tftp-deploy-4fs1nbe5/ramdisk/ramdisk.cpio.gz.uboot
301 16:21:36.259774 - {KERNEL_ADDR}: 0x82000000
302 16:21:36.260162 - {KERNEL}: 954053/tftp-deploy-4fs1nbe5/kernel/zImage
303 16:21:36.260550 - {LAVA_MAC}: None
304 16:21:36.260979 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/954053/extract-nfsrootfs-4aocc8c3
305 16:21:36.261374 - {NFS_SERVER_IP}: 192.168.6.3
306 16:21:36.261762 - {PRESEED_CONFIG}: None
307 16:21:36.262177 - {PRESEED_LOCAL}: None
308 16:21:36.262564 - {RAMDISK_ADDR}: 0x83000000
309 16:21:36.262947 - {RAMDISK}: 954053/tftp-deploy-4fs1nbe5/ramdisk/ramdisk.cpio.gz.uboot
310 16:21:36.263335 - {ROOT_PART}: None
311 16:21:36.263715 - {ROOT}: None
312 16:21:36.264098 - {SERVER_IP}: 192.168.6.3
313 16:21:36.264476 - {TEE_ADDR}: 0x83000000
314 16:21:36.264856 - {TEE}: None
315 16:21:36.265237 Parsed boot commands:
316 16:21:36.265604 - setenv autoload no
317 16:21:36.266010 - setenv initrd_high 0xffffffff
318 16:21:36.266393 - setenv fdt_high 0xffffffff
319 16:21:36.266770 - dhcp
320 16:21:36.267147 - setenv serverip 192.168.6.3
321 16:21:36.267524 - tftp 0x82000000 954053/tftp-deploy-4fs1nbe5/kernel/zImage
322 16:21:36.267903 - tftp 0x83000000 954053/tftp-deploy-4fs1nbe5/ramdisk/ramdisk.cpio.gz.uboot
323 16:21:36.268287 - setenv initrd_size ${filesize}
324 16:21:36.268665 - tftp 0x88000000 954053/tftp-deploy-4fs1nbe5/dtb/am335x-boneblack.dtb
325 16:21:36.269044 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/954053/extract-nfsrootfs-4aocc8c3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 16:21:36.269435 - bootz 0x82000000 0x83000000 0x88000000
327 16:21:36.269935 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 16:21:36.271402 start: 2.3 connect-device (timeout 00:05:00) [common]
330 16:21:36.271813 [common] connect-device Connecting to device using 'telnet conserv3 3003'
331 16:21:36.286872 Setting prompt string to ['lava-test: # ']
332 16:21:36.288299 end: 2.3 connect-device (duration 00:00:00) [common]
333 16:21:36.288902 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 16:21:36.289453 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 16:21:36.290033 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 16:21:36.291255 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-06'
337 16:21:36.327638 >> OK - accepted request
338 16:21:36.329724 Returned 0 in 0 seconds
339 16:21:36.430869 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 16:21:36.432464 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 16:21:36.433019 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 16:21:36.433528 Setting prompt string to ['Hit any key to stop autoboot']
344 16:21:36.434028 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 16:21:36.435572 Trying 192.168.56.22...
346 16:21:36.436037 Connected to conserv3.
347 16:21:36.436450 Escape character is '^]'.
348 16:21:36.436865
349 16:21:36.437283 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 16:21:36.437692
351 16:21:45.315349
352 16:21:45.321435 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 16:21:45.321943 Trying to boot from MMC1
354 16:21:45.910711
355 16:21:45.911313
356 16:21:45.916207 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
357 16:21:45.916664
358 16:21:45.917088 CPU : AM335X-GP rev 2.0
359 16:21:45.921472 Model: TI AM335x BeagleBone Black
360 16:21:45.921936 DRAM: 512 MiB
361 16:21:49.364702
362 16:21:49.371541 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 16:21:49.372194 Trying to boot from MMC1
364 16:21:49.960282
365 16:21:49.960960
366 16:21:49.965701 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
367 16:21:49.966358
368 16:21:49.966742 CPU : AM335X-GP rev 2.0
369 16:21:49.970708 Model: TI AM335x BeagleBone Black
370 16:21:49.971149 DRAM: 512 MiB
371 16:21:52.066357
372 16:21:52.072608 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
373 16:21:52.073242 Trying to boot from MMC1
374 16:21:52.662145
375 16:21:52.662860
376 16:21:52.667815 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
377 16:21:52.668437
378 16:21:52.669011 CPU : AM335X-GP rev 2.0
379 16:21:52.672047 Model: TI AM335x BeagleBone Black
380 16:21:52.672607 DRAM: 512 MiB
381 16:21:52.752465 Core: 160 devices, 18 uclasses, devicetree: separate
382 16:21:52.766068 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 16:21:53.166479 NAND: 0 MiB
384 16:21:53.177612 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 16:21:53.251867 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 16:21:53.272886 <ethaddr> not set. Validating first E-fuse MAC
387 16:21:53.303445 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 16:21:53.361913 Hit any key to stop autoboot: 2
390 16:21:53.362778 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
391 16:21:53.363512 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
392 16:21:53.364045 Setting prompt string to ['=>']
393 16:21:53.364567 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
394 16:21:53.372011 0
395 16:21:53.373011 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 16:21:53.373562 Sending with 10 millisecond of delay
398 16:21:54.508694 => setenv autoload no
399 16:21:54.519285 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
400 16:21:54.522076 setenv autoload no
401 16:21:54.522597 Sending with 10 millisecond of delay
403 16:21:56.319837 => setenv initrd_high 0xffffffff
404 16:21:56.330393 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
405 16:21:56.330930 setenv initrd_high 0xffffffff
406 16:21:56.331426 Sending with 10 millisecond of delay
408 16:21:57.947551 => setenv fdt_high 0xffffffff
409 16:21:57.958075 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
410 16:21:57.958609 setenv fdt_high 0xffffffff
411 16:21:57.959103 Sending with 10 millisecond of delay
413 16:21:58.250552 => dhcp
414 16:21:58.261127 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
415 16:21:58.261703 dhcp
416 16:21:58.263798 link up on port 0, speed 100, full duplex
417 16:21:58.264072 BOOTP broadcast 1
418 16:21:58.515544 BOOTP broadcast 2
419 16:21:59.017651 BOOTP broadcast 3
420 16:22:00.018748 BOOTP broadcast 4
421 16:22:02.020692 BOOTP broadcast 5
422 16:22:02.103137 DHCP client bound to address 192.168.6.10 (3836 ms)
423 16:22:02.104349 Sending with 10 millisecond of delay
425 16:22:03.782347 => setenv serverip 192.168.6.3
426 16:22:03.793104 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
427 16:22:03.794018 setenv serverip 192.168.6.3
428 16:22:03.794756 Sending with 10 millisecond of delay
430 16:22:07.279028 => tftp 0x82000000 954053/tftp-deploy-4fs1nbe5/kernel/zImage
431 16:22:07.290627 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
432 16:22:07.291907 tftp 0x82000000 954053/tftp-deploy-4fs1nbe5/kernel/zImage
433 16:22:07.292543 link up on port 0, speed 100, full duplex
434 16:22:07.294642 Using ethernet@4a100000 device
435 16:22:07.300388 TFTP from server 192.168.6.3; our IP address is 192.168.6.10
436 16:22:07.300680 Filename '954053/tftp-deploy-4fs1nbe5/kernel/zImage'.
437 16:22:07.303645 Load address: 0x82000000
438 16:22:09.376067 Loading: *################################################## 10.9 MiB
439 16:22:09.376753 5.3 MiB/s
440 16:22:09.377234 done
441 16:22:09.380186 Bytes transferred = 11440640 (ae9200 hex)
442 16:22:09.380992 Sending with 10 millisecond of delay
444 16:22:13.831969 => tftp 0x83000000 954053/tftp-deploy-4fs1nbe5/ramdisk/ramdisk.cpio.gz.uboot
445 16:22:13.842806 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
446 16:22:13.843748 tftp 0x83000000 954053/tftp-deploy-4fs1nbe5/ramdisk/ramdisk.cpio.gz.uboot
447 16:22:13.844183 link up on port 0, speed 100, full duplex
448 16:22:13.847451 Using ethernet@4a100000 device
449 16:22:13.853006 TFTP from server 192.168.6.3; our IP address is 192.168.6.10
450 16:22:13.861634 Filename '954053/tftp-deploy-4fs1nbe5/ramdisk/ramdisk.cpio.gz.uboot'.
451 16:22:13.862058 Load address: 0x83000000
452 16:22:16.582652 Loading: *################################################## 14.1 MiB
453 16:22:16.583298 5.2 MiB/s
454 16:22:16.583780 done
455 16:22:16.586905 Bytes transferred = 14790225 (e1ae51 hex)
456 16:22:16.587737 Sending with 10 millisecond of delay
458 16:22:18.446219 => setenv initrd_size ${filesize}
459 16:22:18.456764 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
460 16:22:18.457288 setenv initrd_size ${filesize}
461 16:22:18.457770 Sending with 10 millisecond of delay
463 16:22:22.606151 => tftp 0x88000000 954053/tftp-deploy-4fs1nbe5/dtb/am335x-boneblack.dtb
464 16:22:22.616970 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
465 16:22:22.617868 tftp 0x88000000 954053/tftp-deploy-4fs1nbe5/dtb/am335x-boneblack.dtb
466 16:22:22.618301 link up on port 0, speed 100, full duplex
467 16:22:22.621356 Using ethernet@4a100000 device
468 16:22:22.626989 TFTP from server 192.168.6.3; our IP address is 192.168.6.10
469 16:22:22.637526 Filename '954053/tftp-deploy-4fs1nbe5/dtb/am335x-boneblack.dtb'.
470 16:22:22.638055 Load address: 0x88000000
471 16:22:22.647456 Loading: *################################################## 68.9 KiB
472 16:22:22.647881 5.2 MiB/s
473 16:22:22.656042 done
474 16:22:22.656458 Bytes transferred = 70568 (113a8 hex)
475 16:22:22.657112 Sending with 10 millisecond of delay
477 16:22:35.844052 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/954053/extract-nfsrootfs-4aocc8c3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 16:22:35.854638 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
479 16:22:35.855188 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/954053/extract-nfsrootfs-4aocc8c3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 16:22:35.855652 Sending with 10 millisecond of delay
482 16:22:38.195667 => bootz 0x82000000 0x83000000 0x88000000
483 16:22:38.206560 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 16:22:38.207256 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
485 16:22:38.208520 bootz 0x82000000 0x83000000 0x88000000
486 16:22:38.209071 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
487 16:22:38.209664 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 16:22:38.214182 Image Name:
489 16:22:38.214682 Created: 2024-11-07 16:21:36 UTC
490 16:22:38.222930 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 16:22:38.223413 Data Size: 14790161 Bytes = 14.1 MiB
492 16:22:38.231531 Load Address: 00000000
493 16:22:38.232005 Entry Point: 00000000
494 16:22:38.402739 Verifying Checksum ... OK
495 16:22:38.403419 ## Flattened Device Tree blob at 88000000
496 16:22:38.406456 Booting using the fdt blob at 0x88000000
497 16:22:38.406867 Working FDT set to 88000000
498 16:22:38.412413 Using Device Tree in place at 88000000, end 880143a7
499 16:22:38.416492 Working FDT set to 88000000
500 16:22:38.429302
501 16:22:38.429804 Starting kernel ...
502 16:22:38.430103
503 16:22:38.431266 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
504 16:22:38.431740 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
505 16:22:38.432027 Setting prompt string to ['Linux version [0-9]']
506 16:22:38.432387 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
507 16:22:38.432699 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
508 16:22:39.272863 [ 0.000000] Booting Linux on physical CPU 0x0
509 16:22:39.278834 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
510 16:22:39.279254 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 16:22:39.279557 Setting prompt string to []
512 16:22:39.279853 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 16:22:39.280230 Using line separator: #'\n'#
514 16:22:39.280501 No login prompt set.
515 16:22:39.280750 Parsing kernel messages
516 16:22:39.281266 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 16:22:39.281944 [login-action] Waiting for messages, (timeout 00:03:57)
518 16:22:39.282242 Waiting using forced prompt support (timeout 00:01:58)
519 16:22:39.295805 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j366908-arm-gcc-12-multi-v7-defconfig-fl9pj) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Nov 7 15:42:26 UTC 2024
520 16:22:39.301992 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
521 16:22:39.307370 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
522 16:22:39.318744 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
523 16:22:39.324480 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
524 16:22:39.330336 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
525 16:22:39.330711 [ 0.000000] Memory policy: Data cache writeback
526 16:22:39.336737 [ 0.000000] efi: UEFI not found.
527 16:22:39.345460 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
528 16:22:39.345791 [ 0.000000] Zone ranges:
529 16:22:39.351139 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
530 16:22:39.356839 [ 0.000000] Normal empty
531 16:22:39.362809 [ 0.000000] HighMem empty
532 16:22:39.363383 [ 0.000000] Movable zone start for each node
533 16:22:39.368396 [ 0.000000] Early memory node ranges
534 16:22:39.374074 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
535 16:22:39.381855 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
536 16:22:39.407255 [ 0.000000] CPU: All CPU(s) started in SVC mode.
537 16:22:39.412854 [ 0.000000] AM335X ES2.0 (sgx neon)
538 16:22:39.424471 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
539 16:22:39.442279 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/954053/extract-nfsrootfs-4aocc8c3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
540 16:22:39.453778 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
541 16:22:39.459577 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
542 16:22:39.465287 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
543 16:22:39.475239 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
544 16:22:39.504310 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
545 16:22:39.510506 <6>[ 0.000000] trace event string verifier disabled
546 16:22:39.511278 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
547 16:22:39.518122 <6>[ 0.000000] rcu: RCU event tracing is enabled.
548 16:22:39.523901 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
549 16:22:39.535265 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
550 16:22:39.540610 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
551 16:22:39.555277 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
552 16:22:39.572442 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
553 16:22:39.579215 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
554 16:22:39.670894 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
555 16:22:39.682238 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
556 16:22:39.689045 <6>[ 0.008334] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
557 16:22:39.701906 <6>[ 0.019138] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
558 16:22:39.709323 <6>[ 0.033927] Console: colour dummy device 80x30
559 16:22:39.715498 Matched prompt #6: WARNING:
560 16:22:39.716144 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
561 16:22:39.720888 <3>[ 0.038823] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
562 16:22:39.726699 <3>[ 0.045892] This ensures that you still see kernel messages. Please
563 16:22:39.729750 <3>[ 0.052620] update your kernel commandline.
564 16:22:39.770613 <6>[ 0.057232] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
565 16:22:39.776311 <6>[ 0.096146] CPU: Testing write buffer coherency: ok
566 16:22:39.782453 <6>[ 0.101513] CPU0: Spectre v2: using BPIALL workaround
567 16:22:39.783569 <6>[ 0.106981] pid_max: default: 32768 minimum: 301
568 16:22:39.793914 <6>[ 0.112176] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 16:22:39.800688 <6>[ 0.120005] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
570 16:22:39.807848 <6>[ 0.129359] CPU0: thread -1, cpu 0, socket -1, mpidr 0
571 16:22:39.816219 <6>[ 0.136372] Setting up static identity map for 0x80300000 - 0x803000ac
572 16:22:39.821969 <6>[ 0.145994] rcu: Hierarchical SRCU implementation.
573 16:22:39.829747 <6>[ 0.151280] rcu: Max phase no-delay instances is 1000.
574 16:22:39.838156 <6>[ 0.162384] EFI services will not be available.
575 16:22:39.843974 <6>[ 0.167665] smp: Bringing up secondary CPUs ...
576 16:22:39.849799 <6>[ 0.172713] smp: Brought up 1 node, 1 CPU
577 16:22:39.855850 <6>[ 0.177114] SMP: Total of 1 processors activated (996.14 BogoMIPS).
578 16:22:39.861573 <6>[ 0.183881] CPU: All CPU(s) started in SVC mode.
579 16:22:39.880986 <6>[ 0.189056] Memory: 406000K/522240K available (16384K kernel code, 2542K rwdata, 6784K rodata, 2048K init, 431K bss, 49048K reserved, 65536K cma-reserved, 0K highmem)
580 16:22:39.882234 <6>[ 0.205344] devtmpfs: initialized
581 16:22:39.903856 <6>[ 0.222386] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
582 16:22:39.915388 <6>[ 0.230971] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
583 16:22:39.921340 <6>[ 0.241426] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
584 16:22:39.932132 <6>[ 0.253688] pinctrl core: initialized pinctrl subsystem
585 16:22:39.941314 <6>[ 0.264310] DMI not present or invalid.
586 16:22:39.949597 <6>[ 0.270157] NET: Registered PF_NETLINK/PF_ROUTE protocol family
587 16:22:39.959025 <6>[ 0.279047] DMA: preallocated 256 KiB pool for atomic coherent allocations
588 16:22:39.974152 <6>[ 0.290570] thermal_sys: Registered thermal governor 'step_wise'
589 16:22:39.974706 <6>[ 0.290730] cpuidle: using governor menu
590 16:22:40.001990 <6>[ 0.326294] No ATAGs?
591 16:22:40.008109 <6>[ 0.328936] hw-breakpoint: debug architecture 0x4 unsupported.
592 16:22:40.018106 <6>[ 0.340965] Serial: AMBA PL011 UART driver
593 16:22:40.050974 <6>[ 0.375286] iommu: Default domain type: Translated
594 16:22:40.060024 <6>[ 0.380635] iommu: DMA domain TLB invalidation policy: strict mode
595 16:22:40.086613 <5>[ 0.410546] SCSI subsystem initialized
596 16:22:40.092516 <6>[ 0.415428] usbcore: registered new interface driver usbfs
597 16:22:40.098300 <6>[ 0.421489] usbcore: registered new interface driver hub
598 16:22:40.106887 <6>[ 0.427271] usbcore: registered new device driver usb
599 16:22:40.112698 <6>[ 0.433783] pps_core: LinuxPPS API ver. 1 registered
600 16:22:40.118584 <6>[ 0.439172] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
601 16:22:40.126272 <6>[ 0.448902] PTP clock support registered
602 16:22:40.129499 <6>[ 0.453365] EDAC MC: Ver: 3.0.0
603 16:22:40.178411 <6>[ 0.500296] scmi_core: SCMI protocol bus registered
604 16:22:40.193381 <6>[ 0.517619] vgaarb: loaded
605 16:22:40.206396 <6>[ 0.530638] clocksource: Switched to clocksource dmtimer
606 16:22:40.243004 <6>[ 0.566773] NET: Registered PF_INET protocol family
607 16:22:40.255008 <6>[ 0.572465] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
608 16:22:40.260977 <6>[ 0.581269] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
609 16:22:40.272418 <6>[ 0.590205] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
610 16:22:40.278461 <6>[ 0.598467] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
611 16:22:40.289745 <6>[ 0.606756] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
612 16:22:40.295500 <6>[ 0.614483] TCP: Hash tables configured (established 4096 bind 4096)
613 16:22:40.301648 <6>[ 0.621390] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
614 16:22:40.307434 <6>[ 0.628428] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
615 16:22:40.314858 <6>[ 0.636037] NET: Registered PF_UNIX/PF_LOCAL protocol family
616 16:22:40.391514 <6>[ 0.710516] RPC: Registered named UNIX socket transport module.
617 16:22:40.391922 <6>[ 0.716955] RPC: Registered udp transport module.
618 16:22:40.397472 <6>[ 0.722086] RPC: Registered tcp transport module.
619 16:22:40.403103 <6>[ 0.727191] RPC: Registered tcp-with-tls transport module.
620 16:22:40.416073 <6>[ 0.733115] RPC: Registered tcp NFSv4.1 backchannel transport module.
621 16:22:40.416493 <6>[ 0.740021] PCI: CLS 0 bytes, default 64
622 16:22:40.423420 <5>[ 0.745795] Initialise system trusted keyrings
623 16:22:40.444284 <6>[ 0.765843] Trying to unpack rootfs image as initramfs...
624 16:22:40.523346 <6>[ 0.841767] workingset: timestamp_bits=30 max_order=17 bucket_order=0
625 16:22:40.528042 <6>[ 0.849278] squashfs: version 4.0 (2009/01/31) Phillip Lougher
626 16:22:40.568177 <5>[ 0.892672] NFS: Registering the id_resolver key type
627 16:22:40.573844 <5>[ 0.898276] Key type id_resolver registered
628 16:22:40.579700 <5>[ 0.902952] Key type id_legacy registered
629 16:22:40.585340 <6>[ 0.907392] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
630 16:22:40.595101 <6>[ 0.914592] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
631 16:22:40.667596 <5>[ 0.992203] Key type asymmetric registered
632 16:22:40.673397 <5>[ 0.996727] Asymmetric key parser 'x509' registered
633 16:22:40.684915 <6>[ 1.002216] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
634 16:22:40.685388 <6>[ 1.010104] io scheduler mq-deadline registered
635 16:22:40.690865 <6>[ 1.015085] io scheduler kyber registered
636 16:22:40.696268 <6>[ 1.019541] io scheduler bfq registered
637 16:22:40.801605 <6>[ 1.122482] ledtrig-cpu: registered to indicate activity on CPUs
638 16:22:41.091943 <6>[ 1.412642] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
639 16:22:41.121974 <6>[ 1.446417] msm_serial: driver initialized
640 16:22:41.128037 <6>[ 1.451197] SuperH (H)SCI(F) driver initialized
641 16:22:41.133995 <6>[ 1.456547] STMicroelectronics ASC driver initialized
642 16:22:41.139169 <6>[ 1.462241] STM32 USART driver initialized
643 16:22:41.249446 <6>[ 1.573415] brd: module loaded
644 16:22:41.284481 <6>[ 1.608411] loop: module loaded
645 16:22:41.325575 <6>[ 1.649296] CAN device driver interface
646 16:22:41.332154 <6>[ 1.654560] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
647 16:22:41.337883 <6>[ 1.661574] e1000e: Intel(R) PRO/1000 Network Driver
648 16:22:41.343714 <6>[ 1.666958] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
649 16:22:41.350005 <6>[ 1.673416] igb: Intel(R) Gigabit Ethernet Network Driver
650 16:22:41.357780 <6>[ 1.679239] igb: Copyright (c) 2007-2014 Intel Corporation.
651 16:22:41.369553 <6>[ 1.688418] pegasus: Pegasus/Pegasus II USB Ethernet driver
652 16:22:41.375417 <6>[ 1.694568] usbcore: registered new interface driver pegasus
653 16:22:41.381112 <6>[ 1.700695] usbcore: registered new interface driver asix
654 16:22:41.386968 <6>[ 1.706579] usbcore: registered new interface driver ax88179_178a
655 16:22:41.392646 <6>[ 1.713171] usbcore: registered new interface driver cdc_ether
656 16:22:41.398409 <6>[ 1.719468] usbcore: registered new interface driver smsc75xx
657 16:22:41.404282 <6>[ 1.725711] usbcore: registered new interface driver smsc95xx
658 16:22:41.410078 <6>[ 1.731943] usbcore: registered new interface driver net1080
659 16:22:41.415776 <6>[ 1.738074] usbcore: registered new interface driver cdc_subset
660 16:22:41.421611 <6>[ 1.744486] usbcore: registered new interface driver zaurus
661 16:22:41.428387 <6>[ 1.750534] usbcore: registered new interface driver cdc_ncm
662 16:22:41.438343 <6>[ 1.759872] usbcore: registered new interface driver usb-storage
663 16:22:41.721229 <6>[ 2.043938] i2c_dev: i2c /dev entries driver
664 16:22:41.784704 <5>[ 2.101594] cpuidle: enable-method property 'ti,am3352' found operations
665 16:22:41.790554 <6>[ 2.110979] sdhci: Secure Digital Host Controller Interface driver
666 16:22:41.798005 <6>[ 2.117761] sdhci: Copyright(c) Pierre Ossman
667 16:22:41.805195 <6>[ 2.124207] Synopsys Designware Multimedia Card Interface Driver
668 16:22:41.810658 <6>[ 2.132134] sdhci-pltfm: SDHCI platform and OF driver helper
669 16:22:41.945584 <6>[ 2.262925] usbcore: registered new interface driver usbhid
670 16:22:41.946162 <6>[ 2.268968] usbhid: USB HID core driver
671 16:22:41.989868 <6>[ 2.311960] NET: Registered PF_INET6 protocol family
672 16:22:42.018536 <6>[ 2.343268] Segment Routing with IPv6
673 16:22:42.024394 <6>[ 2.347418] In-situ OAM (IOAM) with IPv6
674 16:22:42.031062 <6>[ 2.351933] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
675 16:22:42.036944 <6>[ 2.359202] NET: Registered PF_PACKET protocol family
676 16:22:42.042764 <6>[ 2.364765] can: controller area network core
677 16:22:42.048476 <6>[ 2.369594] NET: Registered PF_CAN protocol family
678 16:22:42.048932 <6>[ 2.374823] can: raw protocol
679 16:22:42.054329 <6>[ 2.378151] can: broadcast manager protocol
680 16:22:42.060764 <6>[ 2.382749] can: netlink gateway - max_hops=1
681 16:22:42.066980 <5>[ 2.388225] Key type dns_resolver registered
682 16:22:42.073159 <6>[ 2.393304] ThumbEE CPU extension supported.
683 16:22:42.073590 <5>[ 2.397991] Registering SWP/SWPB emulation handler
684 16:22:42.083032 <3>[ 2.403690] omap_voltage_late_init: Voltage driver support not added
685 16:22:42.280052 <5>[ 2.602152] Loading compiled-in X.509 certificates
686 16:22:42.409166 <6>[ 2.720884] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
687 16:22:42.416299 <6>[ 2.737561] pinctrl-single 44e10800.pinmux: 142 pins, size 568
688 16:22:42.442682 <3>[ 2.761257] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
689 16:22:42.652576 <3>[ 2.971078] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
690 16:22:42.849059 <6>[ 3.171878] OMAP GPIO hardware version 0.1
691 16:22:42.869629 <6>[ 3.190495] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
692 16:22:42.972809 <4>[ 3.293427] at24 2-0054: supply vcc not found, using dummy regulator
693 16:22:43.008784 <4>[ 3.329329] at24 2-0055: supply vcc not found, using dummy regulator
694 16:22:43.050581 <4>[ 3.371213] at24 2-0056: supply vcc not found, using dummy regulator
695 16:22:43.087822 <4>[ 3.408452] at24 2-0057: supply vcc not found, using dummy regulator
696 16:22:43.123360 <6>[ 3.444679] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
697 16:22:43.200071 <3>[ 3.517424] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
698 16:22:43.224630 <6>[ 3.538317] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
699 16:22:43.246565 <4>[ 3.564530] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
700 16:22:43.254370 <4>[ 3.573695] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
701 16:22:43.401034 <6>[ 3.721879] omap_rng 48310000.rng: Random Number Generator ver. 20
702 16:22:43.424539 <5>[ 3.748184] random: crng init done
703 16:22:43.455672 <6>[ 3.779695] Freeing initrd memory: 14444K
704 16:22:43.472250 <6>[ 3.791551] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
705 16:22:43.525328 <6>[ 3.843889] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
706 16:22:43.531309 <6>[ 3.854206] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
707 16:22:43.542828 <6>[ 3.861540] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
708 16:22:43.548626 <6>[ 3.868999] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
709 16:22:43.560207 <6>[ 3.877127] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
710 16:22:43.567595 <6>[ 3.888771] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:13:2b
711 16:22:43.580715 <5>[ 3.897787] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
712 16:22:43.608422 <3>[ 3.927552] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
713 16:22:43.614285 <6>[ 3.936146] edma 49000000.dma: TI EDMA DMA engine driver
714 16:22:43.685241 <3>[ 4.003630] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
715 16:22:43.700001 <6>[ 4.017964] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
716 16:22:43.712894 <3>[ 4.035089] l3-aon-clkctrl:0000:0: failed to disable
717 16:22:43.763542 <6>[ 4.082623] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
718 16:22:43.769234 <6>[ 4.092086] printk: legacy console [ttyS0] enabled
719 16:22:43.775063 <6>[ 4.092086] printk: legacy console [ttyS0] enabled
720 16:22:43.780692 <6>[ 4.102422] printk: legacy bootconsole [omap8250] disabled
721 16:22:43.786565 <6>[ 4.102422] printk: legacy bootconsole [omap8250] disabled
722 16:22:43.824259 <4>[ 4.142237] tps65217-pmic: Failed to locate of_node [id: -1]
723 16:22:43.827880 <4>[ 4.149626] tps65217-bl: Failed to locate of_node [id: -1]
724 16:22:43.844309 <6>[ 4.169230] tps65217 0-0024: TPS65217 ID 0xe version 1.2
725 16:22:43.862731 <6>[ 4.176178] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
726 16:22:43.874405 <6>[ 4.189865] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
727 16:22:43.880115 <6>[ 4.201747] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
728 16:22:43.902125 <6>[ 4.221329] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
729 16:22:43.907977 <6>[ 4.230509] sdhci-omap 48060000.mmc: Got CD GPIO
730 16:22:43.916047 <4>[ 4.235680] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
731 16:22:43.930708 <4>[ 4.249296] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
732 16:22:43.937068 <4>[ 4.257944] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
733 16:22:43.946947 <4>[ 4.266582] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
734 16:22:44.044888 <6>[ 4.366119] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
735 16:22:44.093338 <6>[ 4.412298] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
736 16:22:44.099708 <6>[ 4.420696] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
737 16:22:44.108763 <6>[ 4.429456] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
738 16:22:44.160307 <6>[ 4.482873] mmc0: new high speed SDHC card at address 0001
739 16:22:44.168804 <6>[ 4.492399] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
740 16:22:44.178193 <6>[ 4.503708] mmcblk0: p1
741 16:22:44.196627 <6>[ 4.513251] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
742 16:22:44.219001 <6>[ 4.535592] mmc1: new high speed MMC card at address 0001
743 16:22:44.219528 <6>[ 4.542734] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
744 16:22:44.228229 <6>[ 4.551090] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
745 16:22:44.235610 <6>[ 4.558174] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
746 16:22:44.243287 <6>[ 4.565257] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
747 16:22:46.283978 <6>[ 6.602520] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
748 16:22:46.507510 <5>[ 6.631509] Sending DHCP requests ., OK
749 16:22:46.518361 <6>[ 6.835967] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.10
750 16:22:46.518661 <6>[ 6.844148] IP-Config: Complete:
751 16:22:46.532722 <6>[ 6.847690] device=eth0, hwaddr=90:59:af:5b:13:2b, ipaddr=192.168.6.10, mask=255.255.255.0, gw=192.168.6.1
752 16:22:46.538396 <6>[ 6.858239] host=192.168.6.10, domain=, nis-domain=(none)
753 16:22:46.543970 <6>[ 6.864454] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
754 16:22:46.550691 <6>[ 6.864488] nameserver0=10.255.253.1
755 16:22:46.559929 <6>[ 6.877045] clk: Disabling unused clocks
756 16:22:46.560992 <6>[ 6.881808] PM: genpd: Disabling unused power domains
757 16:22:46.578948 <6>[ 6.900337] Freeing unused kernel image (initmem) memory: 2048K
758 16:22:46.586636 <6>[ 6.910089] Run /init as init process
759 16:22:46.609216 Loading, please wait...
760 16:22:46.684370 Starting systemd-udevd version 252.22-1~deb12u1
761 16:22:49.714941 <4>[ 10.032718] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
762 16:22:49.894836 <4>[ 10.213042] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
763 16:22:50.047879 <6>[ 10.372635] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
764 16:22:50.058521 <6>[ 10.378308] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
765 16:22:50.221908 <6>[ 10.544825] tda998x 0-0070: found TDA19988
766 16:22:50.268728 <6>[ 10.592087] hub 1-0:1.0: USB hub found
767 16:22:50.314169 <6>[ 10.637286] hub 1-0:1.0: 1 port detected
768 16:22:53.218017 Begin: Loading essential drivers ... done.
769 16:22:53.223550 Begin: Running /scripts/init-premount ... done.
770 16:22:53.229044 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
771 16:22:53.237001 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
772 16:22:53.243017 Device /sys/class/net/eth0 found
773 16:22:53.243535 done.
774 16:22:53.318804 Begin: Waiting up to 180 secs for any network device to become available ... done.
775 16:22:53.389941 IP-Config: eth0 hardware address 90:59:af:5b:13:2b mtu 1500 DHCP
776 16:22:53.590504 IP-Config: eth0 guessed broadcast address 192.168.6.255
777 16:22:53.595840 IP-Config: eth0 complete (dhcp from 192.168.6.1):
778 16:22:53.601295 address: 192.168.6.10 broadcast: 192.168.6.255 netmask: 255.255.255.0
779 16:22:53.610660 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
780 16:22:53.615353 rootserver: 192.168.6.1 rootpath:
781 16:22:53.615948 filename :
782 16:22:53.694020 done.
783 16:22:53.719385 Begin: Running /scripts/nfs-bottom ... done.
784 16:22:53.787445 Begin: Running /scripts/init-bottom ... done.
785 16:22:55.296705 <30>[ 15.618555] systemd[1]: System time before build time, advancing clock.
786 16:22:55.454712 <30>[ 15.750357] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
787 16:22:55.463510 <30>[ 15.787242] systemd[1]: Detected architecture arm.
788 16:22:55.477223
789 16:22:55.477538 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
790 16:22:55.477752
791 16:22:55.498537 <30>[ 15.820980] systemd[1]: Hostname set to <debian-bookworm-armhf>.
792 16:22:57.639613 <30>[ 17.960065] systemd[1]: Queued start job for default target graphical.target.
793 16:22:57.656627 <30>[ 17.975040] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
794 16:22:57.664223 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
795 16:22:57.685885 <30>[ 18.004484] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
796 16:22:57.694228 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
797 16:22:57.716418 <30>[ 18.034859] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
798 16:22:57.724777 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
799 16:22:57.744654 <30>[ 18.063459] systemd[1]: Created slice user.slice - User and Session Slice.
800 16:22:57.751324 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
801 16:22:57.779797 <30>[ 18.092826] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
802 16:22:57.785994 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
803 16:22:57.803968 <30>[ 18.122604] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
804 16:22:57.814922 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
805 16:22:57.844776 <30>[ 18.152570] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
806 16:22:57.851248 <30>[ 18.173127] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
807 16:22:57.859782 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
808 16:22:57.882912 <30>[ 18.201983] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
809 16:22:57.891348 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
810 16:22:57.913581 <30>[ 18.232344] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
811 16:22:57.922073 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
812 16:22:57.943644 <30>[ 18.262606] systemd[1]: Reached target paths.target - Path Units.
813 16:22:57.948737 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
814 16:22:57.973250 <30>[ 18.292208] systemd[1]: Reached target remote-fs.target - Remote File Systems.
815 16:22:57.980586 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
816 16:22:58.003012 <30>[ 18.321964] systemd[1]: Reached target slices.target - Slice Units.
817 16:22:58.008418 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
818 16:22:58.033385 <30>[ 18.352216] systemd[1]: Reached target swap.target - Swaps.
819 16:22:58.037361 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
820 16:22:58.064138 <30>[ 18.383258] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
821 16:22:58.076378 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
822 16:22:58.104402 <30>[ 18.423075] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
823 16:22:58.112676 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
824 16:22:58.192071 <30>[ 18.505742] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
825 16:22:58.204497 <30>[ 18.523216] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
826 16:22:58.213056 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
827 16:22:58.236450 <30>[ 18.554196] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
828 16:22:58.243812 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
829 16:22:58.266067 <30>[ 18.584612] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
830 16:22:58.274207 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
831 16:22:58.298897 <30>[ 18.616414] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
832 16:22:58.304453 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
833 16:22:58.335834 <30>[ 18.653199] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
834 16:22:58.343481 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
835 16:22:58.370536 <30>[ 18.683262] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
836 16:22:58.389108 <30>[ 18.701819] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
837 16:22:58.433549 <30>[ 18.753143] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
838 16:22:58.453712 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
839 16:22:58.490752 <30>[ 18.810196] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
840 16:22:58.512492 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
841 16:22:58.575191 <30>[ 18.893673] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
842 16:22:58.612230 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
843 16:22:58.665468 <30>[ 18.984508] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
844 16:22:58.683420 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
845 16:22:58.713673 <30>[ 19.033130] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
846 16:22:58.743590 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
847 16:22:58.784965 <30>[ 19.104964] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
848 16:22:58.811115 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
849 16:22:58.854067 <30>[ 19.172877] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
850 16:22:58.873462 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
851 16:22:58.906686 <30>[ 19.226575] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
852 16:22:58.942140 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
853 16:22:58.992906 <30>[ 19.312799] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
854 16:22:59.012446 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
855 16:22:59.041888 <28>[ 19.353916] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
856 16:22:59.050430 <28>[ 19.369355] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
857 16:22:59.094569 <30>[ 19.414932] systemd[1]: Starting systemd-journald.service - Journal Service...
858 16:22:59.111939 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
859 16:22:59.185129 <30>[ 19.504717] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
860 16:22:59.200589 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
861 16:22:59.239459 <30>[ 19.559155] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
862 16:22:59.282938 Starting [0;1;39msystemd-network-g… units from Kernel command line...
863 16:22:59.346611 <30>[ 19.665703] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
864 16:22:59.402416 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
865 16:22:59.482243 <30>[ 19.801272] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
866 16:22:59.543094 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
867 16:22:59.561138 <30>[ 19.881000] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
868 16:22:59.642969 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
869 16:22:59.654191 <30>[ 19.973920] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
870 16:22:59.693689 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
871 16:22:59.717786 <30>[ 20.036434] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
872 16:22:59.752491 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
873 16:22:59.878337 <30>[ 20.198704] systemd[1]: modprobe@configfs.service: Deactivated successfully.
874 16:22:59.913990 <30>[ 20.233173] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
875 16:22:59.942979 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
876 16:22:59.973743 <30>[ 20.294361] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
877 16:23:00.003040 <30>[ 20.322615] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
878 16:23:00.032308 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
879 16:23:00.054257 <30>[ 20.373289] systemd[1]: Started systemd-journald.service - Journal Service.
880 16:23:00.061176 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
881 16:23:00.092889 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
882 16:23:00.125480 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
883 16:23:00.154123 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
884 16:23:00.183037 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
885 16:23:00.205801 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
886 16:23:00.225511 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
887 16:23:00.245720 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
888 16:23:00.273143 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
889 16:23:00.336388 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
890 16:23:00.377458 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
891 16:23:00.446234 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
892 16:23:00.558135 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
893 16:23:00.658144 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
894 16:23:00.694464 <46>[ 21.014078] systemd-journald[163]: Received client request to flush runtime journal.
895 16:23:00.779264 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
896 16:23:00.838100 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
897 16:23:01.694567 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
898 16:23:02.023230 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
899 16:23:02.085711 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
900 16:23:02.382583 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
901 16:23:02.625536 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
902 16:23:02.645357 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
903 16:23:02.662990 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
904 16:23:02.747777 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
905 16:23:02.796335 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
906 16:23:03.663379 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
907 16:23:03.737462 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
908 16:23:04.180781 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
909 16:23:04.258120 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
910 16:23:04.334935 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
911 16:23:05.202574 <5>[ 25.522356] cfg80211: Loading compiled-in X.509 certificates for regulatory database
912 16:23:06.245326 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
913 16:23:06.696851 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
914 16:23:06.839331 <5>[ 27.161231] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
915 16:23:06.918881 <5>[ 27.239149] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
916 16:23:06.931741 <4>[ 27.251241] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
917 16:23:06.937552 <6>[ 27.260376] cfg80211: failed to load regulatory.db
918 16:23:08.359961 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
919 16:23:08.644209 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
920 16:23:09.123004 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
921 16:23:09.373457 <46>[ 29.684481] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
922 16:23:09.438561 <46>[ 29.752479] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
923 16:23:18.132311 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
924 16:23:18.159795 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
925 16:23:18.184337 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
926 16:23:18.205390 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
927 16:23:18.267418 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
928 16:23:18.332904 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
929 16:23:18.374184 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
930 16:23:18.443346 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
931 16:23:18.497239 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
932 16:23:18.532515 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
933 16:23:18.559803 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
934 16:23:18.588723 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
935 16:23:18.628739 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
936 16:23:18.660749 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
937 16:23:18.696010 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
938 16:23:18.735646 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
939 16:23:18.773695 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
940 16:23:18.798682 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
941 16:23:18.823987 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
942 16:23:18.846030 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
943 16:23:18.879310 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
944 16:23:18.903241 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
945 16:23:18.926076 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
946 16:23:18.993122 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
947 16:23:19.043887 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
948 16:23:19.136410 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
949 16:23:19.215163 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
950 16:23:19.287524 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
951 16:23:19.327811 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
952 16:23:19.370190 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
953 16:23:19.541311 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
954 16:23:19.621895 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
955 16:23:19.684073 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
956 16:23:19.702297 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
957 16:23:19.725027 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
958 16:23:19.960220 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
959 16:23:20.399507 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
960 16:23:20.455931 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
961 16:23:20.500350 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
962 16:23:20.567335 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
963 16:23:20.753933 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
964 16:23:20.882344
965 16:23:20.882961 Debian GNU/Linux 12worm-armhf login: root (automatic login)
966 16:23:20.885553
967 16:23:21.190488 Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Thu Nov 7 15:42:26 UTC 2024 armv7l
968 16:23:21.191108
969 16:23:21.195993 The programs included with the Debian GNU/Linux system are free software;
970 16:23:21.201573 the exact distribution terms for each program are described in the
971 16:23:21.207193 individual files in /usr/share/doc/*/copyright.
972 16:23:21.207644
973 16:23:21.215235 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
974 16:23:21.215747 permitted by applicable law.
975 16:23:25.835966 Unable to match end of the kernel message
977 16:23:25.837490 Setting prompt string to ['/ #']
978 16:23:25.838083 end: 2.4.4.1 login-action (duration 00:00:47) [common]
980 16:23:25.839413 end: 2.4.4 auto-login-action (duration 00:00:47) [common]
981 16:23:25.839938 start: 2.4.5 expect-shell-connection (timeout 00:03:10) [common]
982 16:23:25.840373 Setting prompt string to ['/ #']
983 16:23:25.840775 Forcing a shell prompt, looking for ['/ #']
985 16:23:25.891817 / #
986 16:23:25.892401 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
987 16:23:25.892725 Waiting using forced prompt support (timeout 00:02:30)
988 16:23:25.896976
989 16:23:25.903200 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
990 16:23:25.903646 start: 2.4.6 export-device-env (timeout 00:03:10) [common]
991 16:23:25.904006 Sending with 10 millisecond of delay
993 16:23:30.893169 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/954053/extract-nfsrootfs-4aocc8c3'
994 16:23:30.905140 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/954053/extract-nfsrootfs-4aocc8c3'
995 16:23:30.906866 Sending with 10 millisecond of delay
997 16:23:33.003947 / # export NFS_SERVER_IP='192.168.6.3'
998 16:23:33.014866 export NFS_SERVER_IP='192.168.6.3'
999 16:23:33.016757 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1000 16:23:33.017092 end: 2.4 uboot-commands (duration 00:01:57) [common]
1001 16:23:33.017407 end: 2 uboot-action (duration 00:01:57) [common]
1002 16:23:33.017746 start: 3 lava-test-retry (timeout 00:06:51) [common]
1003 16:23:33.018703 start: 3.1 lava-test-shell (timeout 00:06:51) [common]
1004 16:23:33.019094 Using namespace: common
1006 16:23:33.119920 / # #
1007 16:23:33.120808 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1008 16:23:33.124720 #
1009 16:23:33.131118 Using /lava-954053
1011 16:23:33.232269 / # export SHELL=/bin/bash
1012 16:23:33.237209 export SHELL=/bin/bash
1014 16:23:33.345773 / # . /lava-954053/environment
1015 16:23:33.351564 . /lava-954053/environment
1017 16:23:33.464513 / # /lava-954053/bin/lava-test-runner /lava-954053/0
1018 16:23:33.465404 Test shell timeout: 10s (minimum of the action and connection timeout)
1019 16:23:33.470161 /lava-954053/bin/lava-test-runner /lava-954053/0
1020 16:23:33.846397 + export TESTRUN_ID=0_timesync-off
1021 16:23:33.854409 + TESTRUN_ID=0_timesync-off
1022 16:23:33.854985 + cd /lava-954053/0/tests/0_timesync-off
1023 16:23:33.855445 ++ cat uuid
1024 16:23:33.869940 + UUID=954053_1.6.2.4.1
1025 16:23:33.870503 + set +x
1026 16:23:33.878777 <LAVA_SIGNAL_STARTRUN 0_timesync-off 954053_1.6.2.4.1>
1027 16:23:33.879323 + systemctl stop systemd-timesyncd
1028 16:23:33.880082 Received signal: <STARTRUN> 0_timesync-off 954053_1.6.2.4.1
1029 16:23:33.880569 Starting test lava.0_timesync-off (954053_1.6.2.4.1)
1030 16:23:33.881141 Skipping test definition patterns.
1031 16:23:34.178231 + set +x
1032 16:23:34.178901 <LAVA_SIGNAL_ENDRUN 0_timesync-off 954053_1.6.2.4.1>
1033 16:23:34.179636 Received signal: <ENDRUN> 0_timesync-off 954053_1.6.2.4.1
1034 16:23:34.180191 Ending use of test pattern.
1035 16:23:34.180634 Ending test lava.0_timesync-off (954053_1.6.2.4.1), duration 0.30
1037 16:23:34.345676 + export TESTRUN_ID=1_kselftest-dt
1038 16:23:34.353806 + TESTRUN_ID=1_kselftest-dt
1039 16:23:34.354438 + cd /lava-954053/0/tests/1_kselftest-dt
1040 16:23:34.354897 ++ cat uuid
1041 16:23:34.380911 + UUID=954053_1.6.2.4.5
1042 16:23:34.381475 + set +x
1043 16:23:34.386575 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 954053_1.6.2.4.5>
1044 16:23:34.387106 + cd ./automated/linux/kselftest/
1045 16:23:34.387827 Received signal: <STARTRUN> 1_kselftest-dt 954053_1.6.2.4.5
1046 16:23:34.388296 Starting test lava.1_kselftest-dt (954053_1.6.2.4.5)
1047 16:23:34.388826 Skipping test definition patterns.
1048 16:23:34.416559 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1049 16:23:34.515308 INFO: install_deps skipped
1050 16:23:35.069408 --2024-11-07 16:23:35-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1051 16:23:35.105936 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1052 16:23:35.251402 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1053 16:23:35.395531 HTTP request sent, awaiting response... 200 OK
1054 16:23:35.396166 Length: 4097112 (3.9M) [application/octet-stream]
1055 16:23:35.401199 Saving to: 'kselftest_armhf.tar.gz'
1056 16:23:35.401719
1057 16:23:37.335718
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 175KB/s
kselftest_armhf.tar 5%[> ] 218.67K 382KB/s
kselftest_armhf.tar 18%[==> ] 747.85K 875KB/s
kselftest_armhf.tar 24%[===> ] 985.07K 816KB/s
kselftest_armhf.tar 60%[===========> ] 2.35M 1.50MB/s
kselftest_armhf.tar 86%[================> ] 3.40M 1.92MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.02MB/s in 1.9s
1058 16:23:37.336486
1059 16:23:37.839539 2024-11-07 16:23:37 (2.02 MB/s) - 'kselftest_armhf.tar.gz' saved [4097112/4097112]
1060 16:23:37.839958
1061 16:23:52.479063 skiplist:
1062 16:23:52.479462 ========================================
1063 16:23:52.484681 ========================================
1064 16:23:52.587200 dt:test_unprobed_devices.sh
1065 16:23:52.620405 ============== Tests to run ===============
1066 16:23:52.628067 dt:test_unprobed_devices.sh
1067 16:23:52.632083 ===========End Tests to run ===============
1068 16:23:52.639739 shardfile-dt pass
1069 16:23:52.876407 <12>[ 73.200739] kselftest: Running tests in dt
1070 16:23:52.904521 TAP version 13
1071 16:23:52.927923 1..1
1072 16:23:52.981692 # timeout set to 45
1073 16:23:52.982070 # selftests: dt: test_unprobed_devices.sh
1074 16:23:53.749053 # TAP version 13
1075 16:24:18.602621 # 1..257
1076 16:24:18.773372 # ok 1 / # SKIP
1077 16:24:18.794212 # ok 2 /clk_mcasp0
1078 16:24:18.867028 # ok 3 /clk_mcasp0_fixed # SKIP
1079 16:24:18.937439 # ok 4 /cpus/cpu@0 # SKIP
1080 16:24:19.011578 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1081 16:24:19.034136 # ok 6 /fixedregulator0
1082 16:24:19.057439 # ok 7 /leds
1083 16:24:19.082101 # ok 8 /ocp
1084 16:24:19.109029 # ok 9 /ocp/interconnect@44c00000
1085 16:24:19.135700 # ok 10 /ocp/interconnect@44c00000/segment@0
1086 16:24:19.157716 # ok 11 /ocp/interconnect@44c00000/segment@100000
1087 16:24:19.187752 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1088 16:24:19.258591 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1089 16:24:19.275674 # ok 14 /ocp/interconnect@44c00000/segment@200000
1090 16:24:19.305795 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1091 16:24:19.413639 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1092 16:24:19.485306 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1093 16:24:19.553257 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1094 16:24:19.629880 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1095 16:24:19.710097 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1096 16:24:19.799075 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1097 16:24:19.874108 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1098 16:24:19.945768 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1099 16:24:20.018158 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1100 16:24:20.089470 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1101 16:24:20.166942 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1102 16:24:20.231502 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1103 16:24:20.301774 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1104 16:24:20.376792 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1105 16:24:20.446748 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1106 16:24:20.517759 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1107 16:24:20.588990 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1108 16:24:20.660329 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1109 16:24:20.727451 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1110 16:24:20.799570 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1111 16:24:20.870081 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1112 16:24:20.940853 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1113 16:24:21.012850 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1114 16:24:21.083977 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1115 16:24:21.156668 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1116 16:24:21.227820 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1117 16:24:21.300180 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1118 16:24:21.379064 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1119 16:24:21.449448 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1120 16:24:21.521460 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1121 16:24:21.589597 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1122 16:24:21.665468 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1123 16:24:21.736320 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1124 16:24:21.808997 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1125 16:24:21.879371 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1126 16:24:21.951380 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1127 16:24:22.018936 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1128 16:24:22.090611 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1129 16:24:22.162715 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1130 16:24:22.234756 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1131 16:24:22.304955 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1132 16:24:22.376273 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1133 16:24:22.446288 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1134 16:24:22.519243 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1135 16:24:22.592428 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1136 16:24:22.661714 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1137 16:24:22.733233 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1138 16:24:22.805651 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1139 16:24:22.877161 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1140 16:24:22.946684 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1141 16:24:23.018290 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1142 16:24:23.090409 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1143 16:24:23.167764 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1144 16:24:23.232742 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1145 16:24:23.306586 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1146 16:24:23.377798 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1147 16:24:23.456356 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1148 16:24:23.523899 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1149 16:24:23.594671 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1150 16:24:23.666561 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1151 16:24:23.738359 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1152 16:24:23.810687 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1153 16:24:23.887172 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1154 16:24:23.959725 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1155 16:24:24.031179 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1156 16:24:24.098862 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1157 16:24:24.173490 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1158 16:24:24.242639 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1159 16:24:24.314426 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1160 16:24:24.386365 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1161 16:24:24.458663 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1162 16:24:24.530279 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1163 16:24:24.600393 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1164 16:24:24.674458 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1165 16:24:24.746797 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1166 16:24:24.816431 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1167 16:24:24.889946 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1168 16:24:24.961110 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1169 16:24:25.037601 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1170 16:24:25.053826 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1171 16:24:25.078905 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1172 16:24:25.101512 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1173 16:24:25.123766 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1174 16:24:25.147391 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1175 16:24:25.171654 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1176 16:24:25.194958 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1177 16:24:25.218795 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1178 16:24:25.324159 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1179 16:24:25.348569 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1180 16:24:25.373215 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1181 16:24:25.400366 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1182 16:24:25.502876 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1183 16:24:25.578113 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1184 16:24:25.651126 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1185 16:24:25.723028 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1186 16:24:25.795068 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1187 16:24:25.866529 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1188 16:24:25.937954 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1189 16:24:26.009146 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1190 16:24:26.081308 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1191 16:24:26.156875 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1192 16:24:26.226198 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1193 16:24:26.298346 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1194 16:24:26.368937 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1195 16:24:26.442773 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1196 16:24:26.515539 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1197 16:24:26.590115 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1198 16:24:26.611677 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1199 16:24:26.686363 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1200 16:24:26.756685 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1201 16:24:26.829162 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1202 16:24:26.846859 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1203 16:24:26.919939 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1204 16:24:26.945652 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1205 16:24:27.016718 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1206 16:24:27.037782 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1207 16:24:27.059333 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1208 16:24:27.082464 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1209 16:24:27.107356 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1210 16:24:27.130352 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1211 16:24:27.154204 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1212 16:24:27.180210 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1213 16:24:27.258165 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1214 16:24:27.279603 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1215 16:24:27.304903 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1216 16:24:27.375921 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1217 16:24:27.448300 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1218 16:24:27.467884 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1219 16:24:27.570324 # not ok 144 /ocp/interconnect@47c00000
1220 16:24:27.641284 # not ok 145 /ocp/interconnect@47c00000/segment@0
1221 16:24:27.663340 # ok 146 /ocp/interconnect@48000000
1222 16:24:27.686066 # ok 147 /ocp/interconnect@48000000/segment@0
1223 16:24:27.711864 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1224 16:24:27.729696 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1225 16:24:27.753386 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1226 16:24:27.776068 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1227 16:24:27.799516 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1228 16:24:27.823229 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1229 16:24:27.847677 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1230 16:24:27.917270 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1231 16:24:27.996441 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1232 16:24:28.011205 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1233 16:24:28.038185 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1234 16:24:28.059039 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1235 16:24:28.087253 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1236 16:24:28.107683 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1237 16:24:28.130026 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1238 16:24:28.151614 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1239 16:24:28.178014 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1240 16:24:28.203382 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1241 16:24:28.223101 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1242 16:24:28.247575 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1243 16:24:28.269908 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1244 16:24:28.292632 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1245 16:24:28.316318 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1246 16:24:28.343312 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1247 16:24:28.367992 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1248 16:24:28.384540 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1249 16:24:28.414747 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1250 16:24:28.434861 # ok 175 /ocp/interconnect@48000000/segment@100000
1251 16:24:28.457245 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1252 16:24:28.480154 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1253 16:24:28.556634 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1254 16:24:28.628892 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1255 16:24:28.699607 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1256 16:24:28.771478 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1257 16:24:28.838407 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1258 16:24:28.914163 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1259 16:24:28.980601 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1260 16:24:29.055136 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1261 16:24:29.074496 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1262 16:24:29.102069 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1263 16:24:29.120481 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1264 16:24:29.144421 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1265 16:24:29.172001 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1266 16:24:29.191395 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1267 16:24:29.214674 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1268 16:24:29.243626 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1269 16:24:29.266238 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1270 16:24:29.288029 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1271 16:24:29.313728 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1272 16:24:29.338314 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1273 16:24:29.354936 # ok 198 /ocp/interconnect@48000000/segment@200000
1274 16:24:29.380054 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1275 16:24:29.452248 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1276 16:24:29.472004 # ok 201 /ocp/interconnect@48000000/segment@300000
1277 16:24:29.496280 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1278 16:24:29.520227 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1279 16:24:29.544077 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1280 16:24:29.566473 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1281 16:24:29.590210 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1282 16:24:29.617208 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1283 16:24:29.688705 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1284 16:24:29.702831 # ok 209 /ocp/interconnect@4a000000
1285 16:24:29.726408 # ok 210 /ocp/interconnect@4a000000/segment@0
1286 16:24:29.749937 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1287 16:24:29.775042 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1288 16:24:29.803656 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1289 16:24:29.825414 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1290 16:24:29.896260 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1291 16:24:29.999820 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1292 16:24:30.070963 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1293 16:24:30.175243 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1294 16:24:30.240678 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1295 16:24:30.310453 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1296 16:24:30.408999 # not ok 221 /ocp/interconnect@4b140000
1297 16:24:30.480664 # not ok 222 /ocp/interconnect@4b140000/segment@0
1298 16:24:30.556335 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1299 16:24:30.572980 # ok 224 /ocp/target-module@40300000
1300 16:24:30.600469 # ok 225 /ocp/target-module@40300000/sram@0
1301 16:24:30.668422 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1302 16:24:30.743903 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1303 16:24:30.763301 # ok 228 /ocp/target-module@47400000
1304 16:24:30.783392 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1305 16:24:30.806204 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1306 16:24:30.828452 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1307 16:24:30.854077 # ok 232 /ocp/target-module@47400000/usb@1400
1308 16:24:30.875830 # ok 233 /ocp/target-module@47400000/usb@1800
1309 16:24:30.894093 # ok 234 /ocp/target-module@47810000
1310 16:24:30.915695 # ok 235 /ocp/target-module@49000000
1311 16:24:30.943402 # ok 236 /ocp/target-module@49000000/dma@0
1312 16:24:30.964892 # ok 237 /ocp/target-module@49800000
1313 16:24:30.985139 # ok 238 /ocp/target-module@49800000/dma@0
1314 16:24:31.011107 # ok 239 /ocp/target-module@49900000
1315 16:24:31.029578 # ok 240 /ocp/target-module@49900000/dma@0
1316 16:24:31.055212 # ok 241 /ocp/target-module@49a00000
1317 16:24:31.081773 # ok 242 /ocp/target-module@49a00000/dma@0
1318 16:24:31.098224 # ok 243 /ocp/target-module@4c000000
1319 16:24:31.169744 # not ok 244 /ocp/target-module@4c000000/emif@0
1320 16:24:31.190752 # ok 245 /ocp/target-module@50000000
1321 16:24:31.214933 # ok 246 /ocp/target-module@53100000
1322 16:24:31.284646 # not ok 247 /ocp/target-module@53100000/sham@0
1323 16:24:31.310654 # ok 248 /ocp/target-module@53500000
1324 16:24:31.382428 # not ok 249 /ocp/target-module@53500000/aes@0
1325 16:24:31.399696 # ok 250 /ocp/target-module@56000000
1326 16:24:31.506109 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1327 16:24:31.574150 # ok 252 /opp-table # SKIP
1328 16:24:31.639339 # ok 253 /soc # SKIP
1329 16:24:31.660191 # ok 254 /sound
1330 16:24:31.684713 # ok 255 /target-module@4b000000
1331 16:24:31.708679 # ok 256 /target-module@4b000000/target-module@140000
1332 16:24:31.729021 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1333 16:24:31.737103 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1334 16:24:31.744951 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1335 16:24:33.857381 dt_test_unprobed_devices_sh_ skip
1336 16:24:33.862904 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1337 16:24:33.868410 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1338 16:24:33.868969 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1339 16:24:33.874036 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1340 16:24:33.879749 dt_test_unprobed_devices_sh_fixedregulator0 pass
1341 16:24:33.885217 dt_test_unprobed_devices_sh_leds pass
1342 16:24:33.885774 dt_test_unprobed_devices_sh_ocp pass
1343 16:24:33.890914 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1344 16:24:33.896324 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1345 16:24:33.902090 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1346 16:24:33.913241 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1347 16:24:33.918854 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1348 16:24:33.924467 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1349 16:24:33.935754 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1350 16:24:33.941325 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1351 16:24:33.952551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1352 16:24:33.963719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1353 16:24:33.974991 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1354 16:24:33.980719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1355 16:24:33.991823 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1356 16:24:34.002978 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1357 16:24:34.014249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1358 16:24:34.025449 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1359 16:24:34.031025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1360 16:24:34.042226 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1361 16:24:34.053326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1362 16:24:34.064570 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1363 16:24:34.075758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1364 16:24:34.081438 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1365 16:24:34.092499 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1366 16:24:34.103794 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1367 16:24:34.114909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1368 16:24:34.120485 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1369 16:24:34.131780 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1370 16:24:34.143050 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1371 16:24:34.154186 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1372 16:24:34.165356 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1373 16:24:34.170925 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1374 16:24:34.182165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1375 16:24:34.193461 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1376 16:24:34.204304 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1377 16:24:34.215737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1378 16:24:34.226725 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1379 16:24:34.237937 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1380 16:24:34.249101 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1381 16:24:34.260298 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1382 16:24:34.271521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1383 16:24:34.282707 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1384 16:24:34.293911 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1385 16:24:34.305086 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1386 16:24:34.316326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1387 16:24:34.327529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1388 16:24:34.338678 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1389 16:24:34.349910 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1390 16:24:34.361008 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1391 16:24:34.372291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1392 16:24:34.383468 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1393 16:24:34.394708 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1394 16:24:34.405998 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1395 16:24:34.417109 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1396 16:24:34.428233 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1397 16:24:34.439409 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1398 16:24:34.450653 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1399 16:24:34.456160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1400 16:24:34.467399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1401 16:24:34.478633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1402 16:24:34.489888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1403 16:24:34.501027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1404 16:24:34.512161 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1405 16:24:34.523352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1406 16:24:34.534557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1407 16:24:34.545844 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1408 16:24:34.556962 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1409 16:24:34.568142 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1410 16:24:34.579344 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1411 16:24:34.590634 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1412 16:24:34.601799 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1413 16:24:34.613103 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1414 16:24:34.624252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1415 16:24:34.635547 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1416 16:24:34.646761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1417 16:24:34.652270 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1418 16:24:34.663473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1419 16:24:34.674731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1420 16:24:34.685873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1421 16:24:34.697030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1422 16:24:34.702723 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1423 16:24:34.719401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1424 16:24:34.730680 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1425 16:24:34.736216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1426 16:24:34.753016 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1427 16:24:34.764308 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1428 16:24:34.775385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1429 16:24:34.781024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1430 16:24:34.792206 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1431 16:24:34.803385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1432 16:24:34.808990 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1433 16:24:34.820144 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1434 16:24:34.831324 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1435 16:24:34.836963 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1436 16:24:34.848159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1437 16:24:34.853733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1438 16:24:34.864923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1439 16:24:34.876115 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1440 16:24:34.887295 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1441 16:24:34.898481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1442 16:24:34.909730 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1443 16:24:34.920869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1444 16:24:34.932077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1445 16:24:34.943261 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1446 16:24:34.954556 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1447 16:24:34.965755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1448 16:24:34.976866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1449 16:24:34.988035 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1450 16:24:35.004921 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1451 16:24:35.016157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1452 16:24:35.027337 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1453 16:24:35.038574 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1454 16:24:35.049978 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1455 16:24:35.066491 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1456 16:24:35.077691 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1457 16:24:35.088875 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1458 16:24:35.100160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1459 16:24:35.105742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1460 16:24:35.116849 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1461 16:24:35.128017 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1462 16:24:35.133747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1463 16:24:35.144778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1464 16:24:35.150494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1465 16:24:35.161569 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1466 16:24:35.167367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1467 16:24:35.178441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1468 16:24:35.184098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1469 16:24:35.195256 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1470 16:24:35.200927 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1471 16:24:35.212019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1472 16:24:35.223199 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1473 16:24:35.234396 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1474 16:24:35.245603 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1475 16:24:35.256897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1476 16:24:35.262446 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1477 16:24:35.273541 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1478 16:24:35.279228 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1479 16:24:35.284777 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1480 16:24:35.290427 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1481 16:24:35.296021 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1482 16:24:35.301592 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1483 16:24:35.312743 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1484 16:24:35.318425 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1485 16:24:35.324003 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1486 16:24:35.335130 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1487 16:24:35.340826 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1488 16:24:35.351898 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1489 16:24:35.357577 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1490 16:24:35.368740 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1491 16:24:35.374366 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1492 16:24:35.385487 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1493 16:24:35.391148 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1494 16:24:35.402371 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1495 16:24:35.408044 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1496 16:24:35.419103 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1497 16:24:35.424634 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1498 16:24:35.435820 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1499 16:24:35.441521 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1500 16:24:35.447130 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1501 16:24:35.458249 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1502 16:24:35.463973 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1503 16:24:35.475055 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1504 16:24:35.480687 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1505 16:24:35.491906 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1506 16:24:35.497501 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1507 16:24:35.508583 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1508 16:24:35.514265 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1509 16:24:35.519875 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1510 16:24:35.530971 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1511 16:24:35.536643 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1512 16:24:35.547759 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1513 16:24:35.558982 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1514 16:24:35.570147 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1515 16:24:35.581217 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1516 16:24:35.592389 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1517 16:24:35.603689 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1518 16:24:35.614857 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1519 16:24:35.626143 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1520 16:24:35.631738 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1521 16:24:35.642875 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1522 16:24:35.648466 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1523 16:24:35.659648 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1524 16:24:35.665258 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1525 16:24:35.676453 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1526 16:24:35.682092 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1527 16:24:35.693188 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1528 16:24:35.698842 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1529 16:24:35.710054 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1530 16:24:35.715642 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1531 16:24:35.726857 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1532 16:24:35.732339 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1533 16:24:35.743534 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1534 16:24:35.749103 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1535 16:24:35.754803 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1536 16:24:35.765985 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1537 16:24:35.771449 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1538 16:24:35.782714 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1539 16:24:35.788290 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1540 16:24:35.799454 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1541 16:24:35.805056 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1542 16:24:35.816365 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1543 16:24:35.821898 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1544 16:24:35.827426 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1545 16:24:35.833029 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1546 16:24:35.844196 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1547 16:24:35.855393 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1548 16:24:35.861022 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1549 16:24:35.866683 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1550 16:24:35.877776 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1551 16:24:35.888933 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1552 16:24:35.900178 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1553 16:24:35.911348 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1554 16:24:35.916970 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1555 16:24:35.922696 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1556 16:24:35.928216 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1557 16:24:35.933863 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1558 16:24:35.939434 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1559 16:24:35.945026 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1560 16:24:35.956230 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1561 16:24:35.961884 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1562 16:24:35.967502 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1563 16:24:35.973077 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1564 16:24:35.978701 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1565 16:24:35.989912 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1566 16:24:35.995492 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1567 16:24:36.001079 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1568 16:24:36.006698 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1569 16:24:36.012266 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1570 16:24:36.017953 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1571 16:24:36.023490 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1572 16:24:36.029089 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1573 16:24:36.034718 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1574 16:24:36.040276 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1575 16:24:36.046392 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1576 16:24:36.051438 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1577 16:24:36.057091 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1578 16:24:36.062782 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1579 16:24:36.068330 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1580 16:24:36.073893 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1581 16:24:36.079495 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1582 16:24:36.085136 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1583 16:24:36.090822 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1584 16:24:36.096285 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1585 16:24:36.101995 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1586 16:24:36.102345 dt_test_unprobed_devices_sh_opp-table skip
1587 16:24:36.108034 dt_test_unprobed_devices_sh_soc skip
1588 16:24:36.113092 dt_test_unprobed_devices_sh_sound pass
1589 16:24:36.118929 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1590 16:24:36.124290 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1591 16:24:36.129996 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1592 16:24:36.135509 dt_test_unprobed_devices_sh fail
1593 16:24:36.135824 + ../../utils/send-to-lava.sh ./output/result.txt
1594 16:24:36.141119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1595 16:24:36.141775 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1597 16:24:36.150251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1598 16:24:36.150978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1600 16:24:36.236358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1601 16:24:36.237155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1603 16:24:36.327581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1604 16:24:36.328445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1606 16:24:36.418164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1607 16:24:36.418929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1609 16:24:36.511167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1610 16:24:36.511949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1612 16:24:36.602283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1613 16:24:36.603020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1615 16:24:36.691620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1616 16:24:36.692315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1618 16:24:36.800295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1619 16:24:36.801171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1621 16:24:36.893502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1622 16:24:36.894371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1624 16:24:36.983762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1625 16:24:36.984556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1627 16:24:37.074600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1628 16:24:37.075430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1630 16:24:37.167619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1631 16:24:37.168469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1633 16:24:37.267856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1634 16:24:37.268762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1636 16:24:37.359449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1637 16:24:37.360291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1639 16:24:37.455215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1640 16:24:37.456063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1642 16:24:37.547862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1643 16:24:37.548729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1645 16:24:37.640756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1646 16:24:37.641565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1648 16:24:37.736104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1649 16:24:37.736732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1651 16:24:37.829228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1652 16:24:37.829909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1654 16:24:37.920912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1655 16:24:37.921574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1657 16:24:38.014603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1658 16:24:38.015245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1660 16:24:38.109022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1661 16:24:38.109656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1663 16:24:38.199584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1664 16:24:38.200448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1666 16:24:38.292382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1667 16:24:38.293242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1669 16:24:38.386777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1670 16:24:38.387664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1672 16:24:38.475811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1673 16:24:38.476733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1675 16:24:38.570209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1676 16:24:38.570854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1678 16:24:38.662873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1679 16:24:38.663501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1681 16:24:38.755057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1682 16:24:38.755669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1684 16:24:38.845084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1685 16:24:38.845691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1687 16:24:38.936584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1688 16:24:38.937237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1690 16:24:39.028778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1691 16:24:39.029421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1693 16:24:39.121684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1694 16:24:39.122406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1696 16:24:39.215394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1697 16:24:39.216021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1699 16:24:39.305671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1700 16:24:39.306314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1702 16:24:39.398183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1703 16:24:39.398805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1705 16:24:39.489315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1706 16:24:39.490046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1708 16:24:39.580320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1709 16:24:39.580955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1711 16:24:39.671994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1712 16:24:39.672676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1714 16:24:39.764376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1715 16:24:39.765051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1717 16:24:39.857012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1718 16:24:39.857660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1720 16:24:39.949161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1721 16:24:39.949839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1723 16:24:40.042131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1724 16:24:40.042824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1726 16:24:40.148396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1727 16:24:40.149774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1729 16:24:40.250069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1730 16:24:40.251024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1732 16:24:40.341540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1733 16:24:40.342391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1735 16:24:40.434875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1736 16:24:40.435727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1738 16:24:40.527589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1739 16:24:40.528376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1741 16:24:40.629234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1742 16:24:40.630033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1744 16:24:40.732234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1745 16:24:40.733141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1747 16:24:40.824463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1748 16:24:40.825328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1750 16:24:40.917145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1751 16:24:40.917940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1753 16:24:41.011781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1754 16:24:41.013402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1756 16:24:41.105533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1757 16:24:41.106411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1759 16:24:41.197921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1760 16:24:41.198710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1762 16:24:41.290794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1763 16:24:41.291689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1765 16:24:41.388711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1766 16:24:41.391150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1768 16:24:41.479935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1769 16:24:41.480802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1771 16:24:41.572164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1772 16:24:41.573061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1774 16:24:41.665659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1775 16:24:41.666562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1777 16:24:41.758038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1778 16:24:41.758875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1780 16:24:41.849100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1781 16:24:41.849920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1783 16:24:41.942541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1784 16:24:41.943867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1786 16:24:42.033655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1787 16:24:42.034619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1789 16:24:42.126952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1790 16:24:42.127876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1792 16:24:42.219558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1793 16:24:42.220439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1795 16:24:42.314913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1796 16:24:42.315816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1798 16:24:42.406691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1799 16:24:42.407568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1801 16:24:42.499581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1802 16:24:42.500489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1804 16:24:42.590571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1805 16:24:42.591467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1807 16:24:42.683171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1808 16:24:42.683802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1810 16:24:42.777546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1811 16:24:42.778461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1813 16:24:42.868357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1814 16:24:42.869223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1816 16:24:42.960512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1817 16:24:42.961370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1819 16:24:43.049155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1820 16:24:43.050055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1822 16:24:43.142793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1823 16:24:43.143709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1825 16:24:43.234271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1826 16:24:43.234946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1828 16:24:43.325179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1829 16:24:43.326139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1831 16:24:43.414270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1832 16:24:43.415180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1834 16:24:43.508296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1835 16:24:43.509225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1837 16:24:43.599991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1838 16:24:43.600895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1840 16:24:43.701022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1841 16:24:43.701960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1843 16:24:43.797267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1844 16:24:43.798279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1846 16:24:43.897022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1847 16:24:43.898044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1849 16:24:43.998165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1850 16:24:43.999104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1852 16:24:44.099913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1853 16:24:44.100820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1855 16:24:44.197742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1856 16:24:44.198604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1858 16:24:44.286832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1859 16:24:44.287709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1861 16:24:44.390064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1862 16:24:44.390937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1864 16:24:44.491581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1865 16:24:44.492423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1867 16:24:44.581566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1868 16:24:44.582449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1870 16:24:44.677425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1871 16:24:44.678324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1873 16:24:44.770176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1874 16:24:44.771050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1876 16:24:44.862537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1877 16:24:44.863217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1879 16:24:44.961467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1880 16:24:44.962363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1882 16:24:45.063373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1883 16:24:45.065727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1885 16:24:45.169731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1886 16:24:45.170675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1888 16:24:45.271104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1889 16:24:45.272000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1891 16:24:45.362741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1892 16:24:45.363414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1894 16:24:45.472351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1895 16:24:45.473936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1897 16:24:45.571448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1898 16:24:45.572397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1900 16:24:45.693052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1901 16:24:45.693949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1903 16:24:45.796799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1904 16:24:45.797710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1906 16:24:45.889618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1907 16:24:45.890528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1909 16:24:45.994013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1910 16:24:45.995212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1912 16:24:46.097569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1913 16:24:46.098300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1915 16:24:46.193567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1916 16:24:46.194267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1918 16:24:46.291963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1919 16:24:46.292665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1921 16:24:46.388458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1922 16:24:46.389345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1924 16:24:46.484093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1925 16:24:46.484971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1927 16:24:46.578531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1928 16:24:46.579203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1930 16:24:46.673368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1931 16:24:46.674128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1933 16:24:46.764495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1934 16:24:46.765184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1936 16:24:46.864583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1937 16:24:46.865228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1939 16:24:46.966057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1940 16:24:46.966700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1942 16:24:47.069367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1943 16:24:47.070282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1945 16:24:47.161653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1946 16:24:47.162544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1948 16:24:47.256104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1949 16:24:47.256933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1951 16:24:47.348236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1952 16:24:47.349061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1954 16:24:47.446496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1956 16:24:47.449759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1957 16:24:47.547542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1959 16:24:47.550627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1960 16:24:47.649075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1962 16:24:47.652188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1963 16:24:47.740657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1964 16:24:47.741536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1966 16:24:47.834100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1967 16:24:47.834999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1969 16:24:47.932988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1970 16:24:47.933954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1972 16:24:48.030343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1973 16:24:48.031228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1975 16:24:48.130668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1976 16:24:48.131536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1978 16:24:48.223225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1979 16:24:48.224105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1981 16:24:48.316375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1982 16:24:48.317247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1984 16:24:48.409471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1985 16:24:48.410373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1987 16:24:48.501876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1988 16:24:48.502743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1990 16:24:48.595782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1991 16:24:48.596662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1993 16:24:48.696191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1994 16:24:48.697049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1996 16:24:48.798422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1997 16:24:48.799237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1999 16:24:48.889969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2000 16:24:48.891284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2002 16:24:48.982807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2003 16:24:48.983511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2005 16:24:49.075667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2006 16:24:49.076321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2008 16:24:49.169027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2009 16:24:49.169673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2011 16:24:49.257597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2012 16:24:49.258263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2014 16:24:49.343311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2015 16:24:49.343939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2017 16:24:49.436873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2018 16:24:49.437507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2020 16:24:49.531468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2021 16:24:49.532387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2023 16:24:49.622012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2024 16:24:49.622884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2026 16:24:49.712873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2027 16:24:49.713652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2029 16:24:49.805458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2030 16:24:49.806339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2032 16:24:49.901592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2033 16:24:49.902496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2035 16:24:50.013691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2036 16:24:50.014643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2038 16:24:50.109296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2039 16:24:50.110209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2041 16:24:50.200970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2042 16:24:50.201780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2044 16:24:50.306914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2045 16:24:50.307885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2047 16:24:50.396602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2048 16:24:50.397534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2050 16:24:50.486751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2051 16:24:50.487396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2053 16:24:50.580043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2054 16:24:50.580945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2056 16:24:50.675986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2057 16:24:50.676954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2059 16:24:50.775331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2060 16:24:50.776236 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2062 16:24:50.868801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2063 16:24:50.869785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2065 16:24:50.962039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2066 16:24:50.963169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2068 16:24:51.057313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2069 16:24:51.058261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2071 16:24:51.146647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2072 16:24:51.147447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2074 16:24:51.248479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2075 16:24:51.249190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2077 16:24:51.341309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2078 16:24:51.342044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2080 16:24:51.436234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2081 16:24:51.436960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2083 16:24:51.527055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2084 16:24:51.527676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2086 16:24:51.619913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2087 16:24:51.620864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2089 16:24:51.712374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2090 16:24:51.713249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2092 16:24:51.804923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2093 16:24:51.805958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2095 16:24:51.896699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2096 16:24:51.897574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2098 16:24:51.988814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2099 16:24:51.990073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2101 16:24:52.081390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2102 16:24:52.082526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2104 16:24:52.176022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2105 16:24:52.176964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2107 16:24:52.264746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2108 16:24:52.265770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2110 16:24:52.358324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2111 16:24:52.359219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2113 16:24:52.446362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2114 16:24:52.446965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2116 16:24:52.536422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2117 16:24:52.537015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2119 16:24:52.625419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2120 16:24:52.626316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2122 16:24:52.715925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2123 16:24:52.716837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2125 16:24:52.808616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2126 16:24:52.809549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2128 16:24:52.901439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2129 16:24:52.902385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2131 16:24:52.991865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2132 16:24:52.992786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2134 16:24:53.082277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2135 16:24:53.083208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2137 16:24:53.174344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2138 16:24:53.175267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2140 16:24:53.265637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2141 16:24:53.266603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2143 16:24:53.360690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2144 16:24:53.361626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2146 16:24:53.449733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2147 16:24:53.450672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2149 16:24:53.544895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2150 16:24:53.545634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2152 16:24:53.634116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2153 16:24:53.635585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2155 16:24:53.725755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2156 16:24:53.727313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2158 16:24:53.816822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2159 16:24:53.818413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2161 16:24:53.908079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2162 16:24:53.909546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2164 16:24:53.999756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2165 16:24:54.000747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2167 16:24:54.118181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2168 16:24:54.119477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2170 16:24:54.248843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2171 16:24:54.250068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2173 16:24:54.373496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2174 16:24:54.374232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2176 16:24:54.465025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2177 16:24:54.465867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2179 16:24:54.554529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2180 16:24:54.555787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2182 16:24:54.649167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2183 16:24:54.649802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2185 16:24:54.754689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2186 16:24:54.755623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2188 16:24:54.846360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2189 16:24:54.847247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2191 16:24:54.940048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2192 16:24:54.940934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2194 16:24:55.035094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2195 16:24:55.036044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2197 16:24:55.166156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2198 16:24:55.167093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2200 16:24:55.269414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2201 16:24:55.270385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2203 16:24:55.371645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2204 16:24:55.372563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2206 16:24:55.471449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2207 16:24:55.472097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2209 16:24:55.569624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2210 16:24:55.570599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2212 16:24:55.669621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2213 16:24:55.670553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2215 16:24:55.765075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2216 16:24:55.765685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2218 16:24:55.891198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2219 16:24:55.892458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2221 16:24:55.981433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2222 16:24:55.982581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2224 16:24:56.074122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2225 16:24:56.075219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2227 16:24:56.169067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2228 16:24:56.170384 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2230 16:24:56.265041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2231 16:24:56.265946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2233 16:24:56.358024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2234 16:24:56.358976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2236 16:24:56.449639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2237 16:24:56.450334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2239 16:24:56.550052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2240 16:24:56.550667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2242 16:24:56.643452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2243 16:24:56.644302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2245 16:24:56.735459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2246 16:24:56.736318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2248 16:24:56.826079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2249 16:24:56.826958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2251 16:24:56.918268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2252 16:24:56.919349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2254 16:24:57.020234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2255 16:24:57.021147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2257 16:24:57.109250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2258 16:24:57.110117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2260 16:24:57.201732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2261 16:24:57.202377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2263 16:24:57.292984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2264 16:24:57.293623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2266 16:24:57.412420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2267 16:24:57.413029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2269 16:24:57.514560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2270 16:24:57.515201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2272 16:24:57.609090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2273 16:24:57.609730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2275 16:24:57.715158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2277 16:24:57.718252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2278 16:24:57.808127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2279 16:24:57.809004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2281 16:24:57.902369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2282 16:24:57.902986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2284 16:24:58.002148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2285 16:24:58.002751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2287 16:24:58.104665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2288 16:24:58.105497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2290 16:24:58.206202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2291 16:24:58.207113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2293 16:24:58.350739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2294 16:24:58.351366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2296 16:24:58.441881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2297 16:24:58.442502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2299 16:24:58.534971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2300 16:24:58.535588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2302 16:24:58.627403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2303 16:24:58.628320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2305 16:24:58.717305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2306 16:24:58.718296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2308 16:24:58.808228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2309 16:24:58.809175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2311 16:24:58.897511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2312 16:24:58.898471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2314 16:24:58.991266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2315 16:24:58.992171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2317 16:24:59.083754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2318 16:24:59.084602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2320 16:24:59.171210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2321 16:24:59.172090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2323 16:24:59.264512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2324 16:24:59.265362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2326 16:24:59.355479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2327 16:24:59.356335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2329 16:24:59.446996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2330 16:24:59.447834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2332 16:24:59.542982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2333 16:24:59.543844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2335 16:24:59.654580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2336 16:24:59.655486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2338 16:24:59.743122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2339 16:24:59.743929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2341 16:24:59.834220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2342 16:24:59.835013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2344 16:24:59.927997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2345 16:24:59.928824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2347 16:25:00.039350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2348 16:25:00.040256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2350 16:25:00.150589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2351 16:25:00.151442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2353 16:25:00.251454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2354 16:25:00.252302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2356 16:25:00.379043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2357 16:25:00.379950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2359 16:25:00.481071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2360 16:25:00.481744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2362 16:25:00.592713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2363 16:25:00.593353 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2365 16:25:00.694111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2366 16:25:00.694727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2368 16:25:00.791054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2369 16:25:00.791434 + set +x
2370 16:25:00.791889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2372 16:25:00.795327 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 954053_1.6.2.4.5>
2373 16:25:00.795837 Received signal: <ENDRUN> 1_kselftest-dt 954053_1.6.2.4.5
2374 16:25:00.796121 Ending use of test pattern.
2375 16:25:00.796339 Ending test lava.1_kselftest-dt (954053_1.6.2.4.5), duration 86.41
2377 16:25:00.801688 <LAVA_TEST_RUNNER EXIT>
2378 16:25:00.802225 ok: lava_test_shell seems to have completed
2379 16:25:00.808799 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2380 16:25:00.809896 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2381 16:25:00.810247 end: 3 lava-test-retry (duration 00:01:28) [common]
2382 16:25:00.810569 start: 4 finalize (timeout 00:05:23) [common]
2383 16:25:00.810884 start: 4.1 power-off (timeout 00:00:30) [common]
2384 16:25:00.811419 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-06'
2385 16:25:00.846152 >> OK - accepted request
2386 16:25:00.847850 Returned 0 in 0 seconds
2387 16:25:00.949027 end: 4.1 power-off (duration 00:00:00) [common]
2389 16:25:00.950811 start: 4.2 read-feedback (timeout 00:05:23) [common]
2390 16:25:00.951945 Listened to connection for namespace 'common' for up to 1s
2391 16:25:00.952802 Listened to connection for namespace 'common' for up to 1s
2392 16:25:01.952744 Finalising connection for namespace 'common'
2393 16:25:01.953489 Disconnecting from shell: Finalise
2394 16:25:01.954055 / #
2395 16:25:02.055197 end: 4.2 read-feedback (duration 00:00:01) [common]
2396 16:25:02.055994 end: 4 finalize (duration 00:00:01) [common]
2397 16:25:02.056654 Cleaning after the job
2398 16:25:02.057273 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954053/tftp-deploy-4fs1nbe5/ramdisk
2399 16:25:02.066441 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954053/tftp-deploy-4fs1nbe5/kernel
2400 16:25:02.068285 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954053/tftp-deploy-4fs1nbe5/dtb
2401 16:25:02.069390 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954053/tftp-deploy-4fs1nbe5/nfsrootfs
2402 16:25:02.103837 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954053/tftp-deploy-4fs1nbe5/modules
2403 16:25:02.108077 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/954053
2404 16:25:05.328129 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/954053
2405 16:25:05.328707 Job finished correctly