Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 17:26:00.431289 lava-dispatcher, installed at version: 2024.01
2 17:26:00.432110 start: 0 validate
3 17:26:00.432604 Start time: 2024-11-07 17:26:00.432573+00:00 (UTC)
4 17:26:00.433166 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 17:26:00.433734 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 17:26:00.474065 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 17:26:00.474606 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 17:26:00.501957 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 17:26:00.502597 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 17:26:01.550866 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 17:26:01.551384 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 17:26:01.594220 validate duration: 1.16
14 17:26:01.595045 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 17:26:01.595372 start: 1.1 download-retry (timeout 00:10:00) [common]
16 17:26:01.595671 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 17:26:01.596273 Not decompressing ramdisk as can be used compressed.
18 17:26:01.596704 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 17:26:01.596944 saving as /var/lib/lava/dispatcher/tmp/954110/tftp-deploy-0gsuoaja/ramdisk/rootfs.cpio.gz
20 17:26:01.597199 total size: 8181887 (7 MB)
21 17:26:01.632669 progress 0 % (0 MB)
22 17:26:01.643830 progress 5 % (0 MB)
23 17:26:01.654009 progress 10 % (0 MB)
24 17:26:01.662697 progress 15 % (1 MB)
25 17:26:01.668371 progress 20 % (1 MB)
26 17:26:01.674105 progress 25 % (1 MB)
27 17:26:01.679351 progress 30 % (2 MB)
28 17:26:01.684985 progress 35 % (2 MB)
29 17:26:01.690440 progress 40 % (3 MB)
30 17:26:01.695958 progress 45 % (3 MB)
31 17:26:01.701151 progress 50 % (3 MB)
32 17:26:01.706669 progress 55 % (4 MB)
33 17:26:01.711797 progress 60 % (4 MB)
34 17:26:01.717345 progress 65 % (5 MB)
35 17:26:01.722467 progress 70 % (5 MB)
36 17:26:01.727962 progress 75 % (5 MB)
37 17:26:01.733286 progress 80 % (6 MB)
38 17:26:01.738815 progress 85 % (6 MB)
39 17:26:01.744081 progress 90 % (7 MB)
40 17:26:01.749207 progress 95 % (7 MB)
41 17:26:01.753901 progress 100 % (7 MB)
42 17:26:01.754567 7 MB downloaded in 0.16 s (49.59 MB/s)
43 17:26:01.755152 end: 1.1.1 http-download (duration 00:00:00) [common]
45 17:26:01.756093 end: 1.1 download-retry (duration 00:00:00) [common]
46 17:26:01.756407 start: 1.2 download-retry (timeout 00:10:00) [common]
47 17:26:01.756691 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 17:26:01.757190 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm64/defconfig/gcc-12/kernel/Image
49 17:26:01.757471 saving as /var/lib/lava/dispatcher/tmp/954110/tftp-deploy-0gsuoaja/kernel/Image
50 17:26:01.757691 total size: 45713920 (43 MB)
51 17:26:01.757911 No compression specified
52 17:26:01.790611 progress 0 % (0 MB)
53 17:26:01.819090 progress 5 % (2 MB)
54 17:26:01.847682 progress 10 % (4 MB)
55 17:26:01.876563 progress 15 % (6 MB)
56 17:26:01.907277 progress 20 % (8 MB)
57 17:26:01.935306 progress 25 % (10 MB)
58 17:26:01.963713 progress 30 % (13 MB)
59 17:26:01.991823 progress 35 % (15 MB)
60 17:26:02.020464 progress 40 % (17 MB)
61 17:26:02.048530 progress 45 % (19 MB)
62 17:26:02.076980 progress 50 % (21 MB)
63 17:26:02.105712 progress 55 % (24 MB)
64 17:26:02.134263 progress 60 % (26 MB)
65 17:26:02.162565 progress 65 % (28 MB)
66 17:26:02.191000 progress 70 % (30 MB)
67 17:26:02.219599 progress 75 % (32 MB)
68 17:26:02.248143 progress 80 % (34 MB)
69 17:26:02.276316 progress 85 % (37 MB)
70 17:26:02.305044 progress 90 % (39 MB)
71 17:26:02.333629 progress 95 % (41 MB)
72 17:26:02.360905 progress 100 % (43 MB)
73 17:26:02.361427 43 MB downloaded in 0.60 s (72.21 MB/s)
74 17:26:02.361935 end: 1.2.1 http-download (duration 00:00:01) [common]
76 17:26:02.362780 end: 1.2 download-retry (duration 00:00:01) [common]
77 17:26:02.363070 start: 1.3 download-retry (timeout 00:09:59) [common]
78 17:26:02.363350 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 17:26:02.363848 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 17:26:02.364156 saving as /var/lib/lava/dispatcher/tmp/954110/tftp-deploy-0gsuoaja/dtb/meson-g12b-a311d-libretech-cc.dtb
81 17:26:02.364375 total size: 54703 (0 MB)
82 17:26:02.364591 No compression specified
83 17:26:02.403052 progress 59 % (0 MB)
84 17:26:02.403901 progress 100 % (0 MB)
85 17:26:02.404504 0 MB downloaded in 0.04 s (1.30 MB/s)
86 17:26:02.404985 end: 1.3.1 http-download (duration 00:00:00) [common]
88 17:26:02.405823 end: 1.3 download-retry (duration 00:00:00) [common]
89 17:26:02.406100 start: 1.4 download-retry (timeout 00:09:59) [common]
90 17:26:02.406373 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 17:26:02.406854 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm64/defconfig/gcc-12/modules.tar.xz
92 17:26:02.407106 saving as /var/lib/lava/dispatcher/tmp/954110/tftp-deploy-0gsuoaja/modules/modules.tar
93 17:26:02.407320 total size: 11613380 (11 MB)
94 17:26:02.407536 Using unxz to decompress xz
95 17:26:02.449394 progress 0 % (0 MB)
96 17:26:02.516274 progress 5 % (0 MB)
97 17:26:02.593088 progress 10 % (1 MB)
98 17:26:02.692198 progress 15 % (1 MB)
99 17:26:02.783678 progress 20 % (2 MB)
100 17:26:02.864634 progress 25 % (2 MB)
101 17:26:02.940658 progress 30 % (3 MB)
102 17:26:03.020133 progress 35 % (3 MB)
103 17:26:03.093420 progress 40 % (4 MB)
104 17:26:03.170459 progress 45 % (5 MB)
105 17:26:03.256084 progress 50 % (5 MB)
106 17:26:03.334124 progress 55 % (6 MB)
107 17:26:03.420204 progress 60 % (6 MB)
108 17:26:03.501188 progress 65 % (7 MB)
109 17:26:03.583066 progress 70 % (7 MB)
110 17:26:03.662177 progress 75 % (8 MB)
111 17:26:03.746206 progress 80 % (8 MB)
112 17:26:03.826860 progress 85 % (9 MB)
113 17:26:03.906007 progress 90 % (9 MB)
114 17:26:03.984342 progress 95 % (10 MB)
115 17:26:04.061721 progress 100 % (11 MB)
116 17:26:04.074240 11 MB downloaded in 1.67 s (6.64 MB/s)
117 17:26:04.074816 end: 1.4.1 http-download (duration 00:00:02) [common]
119 17:26:04.075639 end: 1.4 download-retry (duration 00:00:02) [common]
120 17:26:04.075906 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 17:26:04.076404 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 17:26:04.076952 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 17:26:04.077504 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 17:26:04.078548 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m
125 17:26:04.079443 makedir: /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin
126 17:26:04.080153 makedir: /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/tests
127 17:26:04.080835 makedir: /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/results
128 17:26:04.081497 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-add-keys
129 17:26:04.082548 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-add-sources
130 17:26:04.083600 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-background-process-start
131 17:26:04.084654 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-background-process-stop
132 17:26:04.085702 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-common-functions
133 17:26:04.086686 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-echo-ipv4
134 17:26:04.087649 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-install-packages
135 17:26:04.088644 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-installed-packages
136 17:26:04.089599 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-os-build
137 17:26:04.090583 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-probe-channel
138 17:26:04.091567 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-probe-ip
139 17:26:04.092564 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-target-ip
140 17:26:04.093518 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-target-mac
141 17:26:04.094463 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-target-storage
142 17:26:04.095424 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-test-case
143 17:26:04.096420 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-test-event
144 17:26:04.097374 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-test-feedback
145 17:26:04.098322 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-test-raise
146 17:26:04.099260 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-test-reference
147 17:26:04.100299 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-test-runner
148 17:26:04.101269 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-test-set
149 17:26:04.102215 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-test-shell
150 17:26:04.103196 Updating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-install-packages (oe)
151 17:26:04.104253 Updating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/bin/lava-installed-packages (oe)
152 17:26:04.105147 Creating /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/environment
153 17:26:04.105908 LAVA metadata
154 17:26:04.106431 - LAVA_JOB_ID=954110
155 17:26:04.106896 - LAVA_DISPATCHER_IP=192.168.6.2
156 17:26:04.107612 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 17:26:04.109680 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 17:26:04.110315 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 17:26:04.110765 skipped lava-vland-overlay
160 17:26:04.111301 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 17:26:04.111853 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 17:26:04.112340 skipped lava-multinode-overlay
163 17:26:04.112828 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 17:26:04.113326 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 17:26:04.113797 Loading test definitions
166 17:26:04.114331 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 17:26:04.114763 Using /lava-954110 at stage 0
168 17:26:04.116967 uuid=954110_1.5.2.4.1 testdef=None
169 17:26:04.117538 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 17:26:04.118052 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 17:26:04.120770 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 17:26:04.121581 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 17:26:04.123796 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 17:26:04.124691 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 17:26:04.126850 runner path: /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/0/tests/0_dmesg test_uuid 954110_1.5.2.4.1
178 17:26:04.127397 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 17:26:04.128193 Creating lava-test-runner.conf files
181 17:26:04.128400 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/954110/lava-overlay-37i7us1m/lava-954110/0 for stage 0
182 17:26:04.128733 - 0_dmesg
183 17:26:04.129076 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 17:26:04.129352 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 17:26:04.152790 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 17:26:04.153192 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 17:26:04.153453 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 17:26:04.153718 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 17:26:04.153977 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 17:26:05.059426 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 17:26:05.059895 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 17:26:05.060194 extracting modules file /var/lib/lava/dispatcher/tmp/954110/tftp-deploy-0gsuoaja/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954110/extract-overlay-ramdisk-mdfwrvzj/ramdisk
193 17:26:06.368483 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 17:26:06.368962 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 17:26:06.369254 [common] Applying overlay /var/lib/lava/dispatcher/tmp/954110/compress-overlay-6hypkr0w/overlay-1.5.2.5.tar.gz to ramdisk
196 17:26:06.369480 [common] Applying overlay /var/lib/lava/dispatcher/tmp/954110/compress-overlay-6hypkr0w/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/954110/extract-overlay-ramdisk-mdfwrvzj/ramdisk
197 17:26:06.400093 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 17:26:06.400519 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 17:26:06.400787 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 17:26:06.401012 Converting downloaded kernel to a uImage
201 17:26:06.401319 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/954110/tftp-deploy-0gsuoaja/kernel/Image /var/lib/lava/dispatcher/tmp/954110/tftp-deploy-0gsuoaja/kernel/uImage
202 17:26:06.889704 output: Image Name:
203 17:26:06.890112 output: Created: Thu Nov 7 17:26:06 2024
204 17:26:06.890323 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 17:26:06.890526 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 17:26:06.890725 output: Load Address: 01080000
207 17:26:06.890922 output: Entry Point: 01080000
208 17:26:06.891117 output:
209 17:26:06.891449 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 17:26:06.891710 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 17:26:06.892014 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 17:26:06.892285 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 17:26:06.892542 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 17:26:06.892795 Building ramdisk /var/lib/lava/dispatcher/tmp/954110/extract-overlay-ramdisk-mdfwrvzj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/954110/extract-overlay-ramdisk-mdfwrvzj/ramdisk
215 17:26:09.257947 >> 181575 blocks
216 17:26:17.732394 Adding RAMdisk u-boot header.
217 17:26:17.732853 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/954110/extract-overlay-ramdisk-mdfwrvzj/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/954110/extract-overlay-ramdisk-mdfwrvzj/ramdisk.cpio.gz.uboot
218 17:26:18.020165 output: Image Name:
219 17:26:18.020582 output: Created: Thu Nov 7 17:26:17 2024
220 17:26:18.020790 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 17:26:18.020992 output: Data Size: 26054005 Bytes = 25443.36 KiB = 24.85 MiB
222 17:26:18.021192 output: Load Address: 00000000
223 17:26:18.021387 output: Entry Point: 00000000
224 17:26:18.021582 output:
225 17:26:18.022212 rename /var/lib/lava/dispatcher/tmp/954110/extract-overlay-ramdisk-mdfwrvzj/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/954110/tftp-deploy-0gsuoaja/ramdisk/ramdisk.cpio.gz.uboot
226 17:26:18.022631 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 17:26:18.022912 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 17:26:18.023180 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 17:26:18.023415 No LXC device requested
230 17:26:18.023667 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 17:26:18.023920 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 17:26:18.024382 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 17:26:18.024793 Checking files for TFTP limit of 4294967296 bytes.
234 17:26:18.027410 end: 1 tftp-deploy (duration 00:00:16) [common]
235 17:26:18.027976 start: 2 uboot-action (timeout 00:05:00) [common]
236 17:26:18.028538 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 17:26:18.029031 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 17:26:18.029527 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 17:26:18.030048 Using kernel file from prepare-kernel: 954110/tftp-deploy-0gsuoaja/kernel/uImage
240 17:26:18.030663 substitutions:
241 17:26:18.031068 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 17:26:18.031465 - {DTB_ADDR}: 0x01070000
243 17:26:18.031855 - {DTB}: 954110/tftp-deploy-0gsuoaja/dtb/meson-g12b-a311d-libretech-cc.dtb
244 17:26:18.032282 - {INITRD}: 954110/tftp-deploy-0gsuoaja/ramdisk/ramdisk.cpio.gz.uboot
245 17:26:18.032676 - {KERNEL_ADDR}: 0x01080000
246 17:26:18.033065 - {KERNEL}: 954110/tftp-deploy-0gsuoaja/kernel/uImage
247 17:26:18.033451 - {LAVA_MAC}: None
248 17:26:18.033874 - {PRESEED_CONFIG}: None
249 17:26:18.034260 - {PRESEED_LOCAL}: None
250 17:26:18.034645 - {RAMDISK_ADDR}: 0x08000000
251 17:26:18.035026 - {RAMDISK}: 954110/tftp-deploy-0gsuoaja/ramdisk/ramdisk.cpio.gz.uboot
252 17:26:18.035410 - {ROOT_PART}: None
253 17:26:18.035793 - {ROOT}: None
254 17:26:18.036203 - {SERVER_IP}: 192.168.6.2
255 17:26:18.036591 - {TEE_ADDR}: 0x83000000
256 17:26:18.036974 - {TEE}: None
257 17:26:18.037355 Parsed boot commands:
258 17:26:18.037726 - setenv autoload no
259 17:26:18.038106 - setenv initrd_high 0xffffffff
260 17:26:18.038484 - setenv fdt_high 0xffffffff
261 17:26:18.038861 - dhcp
262 17:26:18.039242 - setenv serverip 192.168.6.2
263 17:26:18.039619 - tftpboot 0x01080000 954110/tftp-deploy-0gsuoaja/kernel/uImage
264 17:26:18.040016 - tftpboot 0x08000000 954110/tftp-deploy-0gsuoaja/ramdisk/ramdisk.cpio.gz.uboot
265 17:26:18.040404 - tftpboot 0x01070000 954110/tftp-deploy-0gsuoaja/dtb/meson-g12b-a311d-libretech-cc.dtb
266 17:26:18.040787 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 17:26:18.041175 - bootm 0x01080000 0x08000000 0x01070000
268 17:26:18.041662 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 17:26:18.043123 start: 2.3 connect-device (timeout 00:05:00) [common]
271 17:26:18.043556 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 17:26:18.057782 Setting prompt string to ['lava-test: # ']
273 17:26:18.059229 end: 2.3 connect-device (duration 00:00:00) [common]
274 17:26:18.059813 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 17:26:18.060402 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 17:26:18.060928 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 17:26:18.062058 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 17:26:18.098958 >> OK - accepted request
279 17:26:18.100969 Returned 0 in 0 seconds
280 17:26:18.202008 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 17:26:18.203556 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 17:26:18.204150 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 17:26:18.204655 Setting prompt string to ['Hit any key to stop autoboot']
285 17:26:18.205097 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 17:26:18.206654 Trying 192.168.56.21...
287 17:26:18.207122 Connected to conserv1.
288 17:26:18.207521 Escape character is '^]'.
289 17:26:18.207938
290 17:26:18.208386 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 17:26:18.208809
292 17:26:29.650387 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 17:26:29.651018 bl2_stage_init 0x01
294 17:26:29.651453 bl2_stage_init 0x81
295 17:26:29.655895 hw id: 0x0000 - pwm id 0x01
296 17:26:29.656396 bl2_stage_init 0xc1
297 17:26:29.656804 bl2_stage_init 0x02
298 17:26:29.657197
299 17:26:29.661472 L0:00000000
300 17:26:29.661894 L1:20000703
301 17:26:29.662280 L2:00008067
302 17:26:29.662662 L3:14000000
303 17:26:29.667086 B2:00402000
304 17:26:29.667501 B1:e0f83180
305 17:26:29.667884
306 17:26:29.668301 TE: 58124
307 17:26:29.668688
308 17:26:29.672669 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 17:26:29.673084
310 17:26:29.673473 Board ID = 1
311 17:26:29.678317 Set A53 clk to 24M
312 17:26:29.678746 Set A73 clk to 24M
313 17:26:29.679130 Set clk81 to 24M
314 17:26:29.683873 A53 clk: 1200 MHz
315 17:26:29.684329 A73 clk: 1200 MHz
316 17:26:29.684719 CLK81: 166.6M
317 17:26:29.685101 smccc: 00012a92
318 17:26:29.689463 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 17:26:29.695058 board id: 1
320 17:26:29.700925 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 17:26:29.711608 fw parse done
322 17:26:29.717569 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 17:26:29.760262 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 17:26:29.771092 PIEI prepare done
325 17:26:29.771500 fastboot data load
326 17:26:29.771887 fastboot data verify
327 17:26:29.776834 verify result: 266
328 17:26:29.782410 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 17:26:29.782842 LPDDR4 probe
330 17:26:29.783247 ddr clk to 1584MHz
331 17:26:29.790343 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 17:26:29.827620
333 17:26:29.828126 dmc_version 0001
334 17:26:29.834277 Check phy result
335 17:26:29.840195 INFO : End of CA training
336 17:26:29.840661 INFO : End of initialization
337 17:26:29.845808 INFO : Training has run successfully!
338 17:26:29.846370 Check phy result
339 17:26:29.851503 INFO : End of initialization
340 17:26:29.852136 INFO : End of read enable training
341 17:26:29.857075 INFO : End of fine write leveling
342 17:26:29.862792 INFO : End of Write leveling coarse delay
343 17:26:29.863386 INFO : Training has run successfully!
344 17:26:29.863809 Check phy result
345 17:26:29.868314 INFO : End of initialization
346 17:26:29.868839 INFO : End of read dq deskew training
347 17:26:29.873816 INFO : End of MPR read delay center optimization
348 17:26:29.879475 INFO : End of write delay center optimization
349 17:26:29.885096 INFO : End of read delay center optimization
350 17:26:29.885609 INFO : End of max read latency training
351 17:26:29.890680 INFO : Training has run successfully!
352 17:26:29.891181 1D training succeed
353 17:26:29.899756 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 17:26:29.947391 Check phy result
355 17:26:29.947882 INFO : End of initialization
356 17:26:29.969127 INFO : End of 2D read delay Voltage center optimization
357 17:26:29.989439 INFO : End of 2D read delay Voltage center optimization
358 17:26:30.041477 INFO : End of 2D write delay Voltage center optimization
359 17:26:30.090823 INFO : End of 2D write delay Voltage center optimization
360 17:26:30.096300 INFO : Training has run successfully!
361 17:26:30.096608
362 17:26:30.096819 channel==0
363 17:26:30.101937 RxClkDly_Margin_A0==78 ps 8
364 17:26:30.102361 TxDqDly_Margin_A0==98 ps 10
365 17:26:30.107506 RxClkDly_Margin_A1==88 ps 9
366 17:26:30.107938 TxDqDly_Margin_A1==98 ps 10
367 17:26:30.108306 TrainedVREFDQ_A0==74
368 17:26:30.113111 TrainedVREFDQ_A1==74
369 17:26:30.113410 VrefDac_Margin_A0==25
370 17:26:30.113616 DeviceVref_Margin_A0==40
371 17:26:30.118703 VrefDac_Margin_A1==25
372 17:26:30.119140 DeviceVref_Margin_A1==40
373 17:26:30.119464
374 17:26:30.119774
375 17:26:30.124304 channel==1
376 17:26:30.124733 RxClkDly_Margin_A0==98 ps 10
377 17:26:30.124975 TxDqDly_Margin_A0==88 ps 9
378 17:26:30.129954 RxClkDly_Margin_A1==88 ps 9
379 17:26:30.130255 TxDqDly_Margin_A1==88 ps 9
380 17:26:30.135490 TrainedVREFDQ_A0==76
381 17:26:30.135918 TrainedVREFDQ_A1==77
382 17:26:30.136272 VrefDac_Margin_A0==23
383 17:26:30.141197 DeviceVref_Margin_A0==38
384 17:26:30.141508 VrefDac_Margin_A1==24
385 17:26:30.146686 DeviceVref_Margin_A1==37
386 17:26:30.146938
387 17:26:30.147154 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 17:26:30.147361
389 17:26:30.180303 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 17:26:30.180839 2D training succeed
391 17:26:30.185895 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 17:26:30.191484 auto size-- 65535DDR cs0 size: 2048MB
393 17:26:30.191918 DDR cs1 size: 2048MB
394 17:26:30.197125 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 17:26:30.197558 cs0 DataBus test pass
396 17:26:30.202729 cs1 DataBus test pass
397 17:26:30.203153 cs0 AddrBus test pass
398 17:26:30.203552 cs1 AddrBus test pass
399 17:26:30.203944
400 17:26:30.208322 100bdlr_step_size ps== 420
401 17:26:30.208783 result report
402 17:26:30.213902 boot times 0Enable ddr reg access
403 17:26:30.219163 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 17:26:30.232685 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 17:26:30.806292 0.0;M3 CHK:0;cm4_sp_mode 0
406 17:26:30.806917 MVN_1=0x00000000
407 17:26:30.811818 MVN_2=0x00000000
408 17:26:30.817506 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 17:26:30.817994 OPS=0x10
410 17:26:30.818433 ring efuse init
411 17:26:30.818849 chipver efuse init
412 17:26:30.825696 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 17:26:30.826198 [0.018961 Inits done]
414 17:26:30.833289 secure task start!
415 17:26:30.833774 high task start!
416 17:26:30.834192 low task start!
417 17:26:30.834603 run into bl31
418 17:26:30.839928 NOTICE: BL31: v1.3(release):4fc40b1
419 17:26:30.847750 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 17:26:30.848256 NOTICE: BL31: G12A normal boot!
421 17:26:30.873109 NOTICE: BL31: BL33 decompress pass
422 17:26:30.877873 ERROR: Error initializing runtime service opteed_fast
423 17:26:32.111722
424 17:26:32.112376
425 17:26:32.120186 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 17:26:32.120738
427 17:26:32.121195 Model: Libre Computer AML-A311D-CC Alta
428 17:26:32.328757 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 17:26:32.352130 DRAM: 2 GiB (effective 3.8 GiB)
430 17:26:32.495038 Core: 408 devices, 31 uclasses, devicetree: separate
431 17:26:32.501111 WDT: Not starting watchdog@f0d0
432 17:26:32.533201 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 17:26:32.545703 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 17:26:32.550632 ** Bad device specification mmc 0 **
435 17:26:32.560985 Card did not respond to voltage select! : -110
436 17:26:32.568582 ** Bad device specification mmc 0 **
437 17:26:32.568911 Couldn't find partition mmc 0
438 17:26:32.576912 Card did not respond to voltage select! : -110
439 17:26:32.582314 ** Bad device specification mmc 0 **
440 17:26:32.582576 Couldn't find partition mmc 0
441 17:26:32.587402 Error: could not access storage.
442 17:26:33.851026 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 17:26:33.851641 bl2_stage_init 0x01
444 17:26:33.852109 bl2_stage_init 0x81
445 17:26:33.856566 hw id: 0x0000 - pwm id 0x01
446 17:26:33.857008 bl2_stage_init 0xc1
447 17:26:33.857420 bl2_stage_init 0x02
448 17:26:33.857823
449 17:26:33.862169 L0:00000000
450 17:26:33.862605 L1:20000703
451 17:26:33.863011 L2:00008067
452 17:26:33.863407 L3:14000000
453 17:26:33.867757 B2:00402000
454 17:26:33.868252 B1:e0f83180
455 17:26:33.868675
456 17:26:33.869087 TE: 58167
457 17:26:33.869496
458 17:26:33.873349 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 17:26:33.873803
460 17:26:33.874213 Board ID = 1
461 17:26:33.878928 Set A53 clk to 24M
462 17:26:33.879363 Set A73 clk to 24M
463 17:26:33.879766 Set clk81 to 24M
464 17:26:33.884568 A53 clk: 1200 MHz
465 17:26:33.884999 A73 clk: 1200 MHz
466 17:26:33.885398 CLK81: 166.6M
467 17:26:33.885792 smccc: 00012abe
468 17:26:33.890147 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 17:26:33.895832 board id: 1
470 17:26:33.901619 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 17:26:33.912293 fw parse done
472 17:26:33.918267 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 17:26:33.960928 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 17:26:33.971842 PIEI prepare done
475 17:26:33.972356 fastboot data load
476 17:26:33.972777 fastboot data verify
477 17:26:33.977353 verify result: 266
478 17:26:33.982984 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 17:26:33.983427 LPDDR4 probe
480 17:26:33.983833 ddr clk to 1584MHz
481 17:26:33.991056 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 17:26:34.028268
483 17:26:34.028843 dmc_version 0001
484 17:26:34.035043 Check phy result
485 17:26:34.040771 INFO : End of CA training
486 17:26:34.041256 INFO : End of initialization
487 17:26:34.046360 INFO : Training has run successfully!
488 17:26:34.046815 Check phy result
489 17:26:34.051958 INFO : End of initialization
490 17:26:34.052437 INFO : End of read enable training
491 17:26:34.057550 INFO : End of fine write leveling
492 17:26:34.063151 INFO : End of Write leveling coarse delay
493 17:26:34.063603 INFO : Training has run successfully!
494 17:26:34.064046 Check phy result
495 17:26:34.068766 INFO : End of initialization
496 17:26:34.069227 INFO : End of read dq deskew training
497 17:26:34.074355 INFO : End of MPR read delay center optimization
498 17:26:34.080016 INFO : End of write delay center optimization
499 17:26:34.085558 INFO : End of read delay center optimization
500 17:26:34.085864 INFO : End of max read latency training
501 17:26:34.091131 INFO : Training has run successfully!
502 17:26:34.091413 1D training succeed
503 17:26:34.100338 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 17:26:34.147961 Check phy result
505 17:26:34.148332 INFO : End of initialization
506 17:26:34.169646 INFO : End of 2D read delay Voltage center optimization
507 17:26:34.189649 INFO : End of 2D read delay Voltage center optimization
508 17:26:34.244095 INFO : End of 2D write delay Voltage center optimization
509 17:26:34.290857 INFO : End of 2D write delay Voltage center optimization
510 17:26:34.296376 INFO : Training has run successfully!
511 17:26:34.296673
512 17:26:34.296909 channel==0
513 17:26:34.301989 RxClkDly_Margin_A0==78 ps 8
514 17:26:34.302259 TxDqDly_Margin_A0==98 ps 10
515 17:26:34.307570 RxClkDly_Margin_A1==88 ps 9
516 17:26:34.307845 TxDqDly_Margin_A1==98 ps 10
517 17:26:34.308102 TrainedVREFDQ_A0==74
518 17:26:34.313155 TrainedVREFDQ_A1==74
519 17:26:34.313447 VrefDac_Margin_A0==25
520 17:26:34.313677 DeviceVref_Margin_A0==40
521 17:26:34.318764 VrefDac_Margin_A1==25
522 17:26:34.319053 DeviceVref_Margin_A1==40
523 17:26:34.319270
524 17:26:34.319485
525 17:26:34.324376 channel==1
526 17:26:34.324655 RxClkDly_Margin_A0==98 ps 10
527 17:26:34.324891 TxDqDly_Margin_A0==88 ps 9
528 17:26:34.329975 RxClkDly_Margin_A1==88 ps 9
529 17:26:34.330243 TxDqDly_Margin_A1==88 ps 9
530 17:26:34.335563 TrainedVREFDQ_A0==76
531 17:26:34.335840 TrainedVREFDQ_A1==77
532 17:26:34.336095 VrefDac_Margin_A0==22
533 17:26:34.341149 DeviceVref_Margin_A0==38
534 17:26:34.341419 VrefDac_Margin_A1==24
535 17:26:34.346788 DeviceVref_Margin_A1==37
536 17:26:34.347061
537 17:26:34.347288 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 17:26:34.347505
539 17:26:34.380410 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 17:26:34.380766 2D training succeed
541 17:26:34.386033 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 17:26:34.391573 auto size-- 65535DDR cs0 size: 2048MB
543 17:26:34.391848 DDR cs1 size: 2048MB
544 17:26:34.397157 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 17:26:34.397442 cs0 DataBus test pass
546 17:26:34.402795 cs1 DataBus test pass
547 17:26:34.403097 cs0 AddrBus test pass
548 17:26:34.403350 cs1 AddrBus test pass
549 17:26:34.403574
550 17:26:34.408376 100bdlr_step_size ps== 420
551 17:26:34.408668 result report
552 17:26:34.414018 boot times 0Enable ddr reg access
553 17:26:34.419256 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 17:26:34.432734 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 17:26:35.004787 0.0;M3 CHK:0;cm4_sp_mode 0
556 17:26:35.005403 MVN_1=0x00000000
557 17:26:35.010264 MVN_2=0x00000000
558 17:26:35.016140 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 17:26:35.016746 OPS=0x10
560 17:26:35.017214 ring efuse init
561 17:26:35.017616 chipver efuse init
562 17:26:35.021697 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 17:26:35.027249 [0.018960 Inits done]
564 17:26:35.027818 secure task start!
565 17:26:35.028274 high task start!
566 17:26:35.031843 low task start!
567 17:26:35.032351 run into bl31
568 17:26:35.038449 NOTICE: BL31: v1.3(release):4fc40b1
569 17:26:35.048497 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 17:26:35.049017 NOTICE: BL31: G12A normal boot!
571 17:26:35.071615 NOTICE: BL31: BL33 decompress pass
572 17:26:35.077389 ERROR: Error initializing runtime service opteed_fast
573 17:26:36.310238
574 17:26:36.310858
575 17:26:36.318656 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 17:26:36.319140
577 17:26:36.319559 Model: Libre Computer AML-A311D-CC Alta
578 17:26:36.526931 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 17:26:36.550370 DRAM: 2 GiB (effective 3.8 GiB)
580 17:26:36.693363 Core: 408 devices, 31 uclasses, devicetree: separate
581 17:26:36.699248 WDT: Not starting watchdog@f0d0
582 17:26:36.731516 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 17:26:36.743954 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 17:26:36.748959 ** Bad device specification mmc 0 **
585 17:26:36.759379 Card did not respond to voltage select! : -110
586 17:26:36.766961 ** Bad device specification mmc 0 **
587 17:26:36.767500 Couldn't find partition mmc 0
588 17:26:36.775357 Card did not respond to voltage select! : -110
589 17:26:36.780788 ** Bad device specification mmc 0 **
590 17:26:36.781306 Couldn't find partition mmc 0
591 17:26:36.785834 Error: could not access storage.
592 17:26:37.128395 Net: eth0: ethernet@ff3f0000
593 17:26:37.129058 starting USB...
594 17:26:37.380155 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 17:26:37.380782 Starting the controller
596 17:26:37.387058 USB XHCI 1.10
597 17:26:39.100219 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 17:26:39.100902 bl2_stage_init 0x01
599 17:26:39.101377 bl2_stage_init 0x81
600 17:26:39.105637 hw id: 0x0000 - pwm id 0x01
601 17:26:39.106134 bl2_stage_init 0xc1
602 17:26:39.106591 bl2_stage_init 0x02
603 17:26:39.107042
604 17:26:39.111191 L0:00000000
605 17:26:39.111688 L1:20000703
606 17:26:39.112189 L2:00008067
607 17:26:39.112637 L3:14000000
608 17:26:39.114167 B2:00402000
609 17:26:39.114640 B1:e0f83180
610 17:26:39.115089
611 17:26:39.115537 TE: 58159
612 17:26:39.116024
613 17:26:39.125401 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 17:26:39.125936
615 17:26:39.126393 Board ID = 1
616 17:26:39.126835 Set A53 clk to 24M
617 17:26:39.127276 Set A73 clk to 24M
618 17:26:39.130858 Set clk81 to 24M
619 17:26:39.131342 A53 clk: 1200 MHz
620 17:26:39.131789 A73 clk: 1200 MHz
621 17:26:39.134485 CLK81: 166.6M
622 17:26:39.134964 smccc: 00012ab5
623 17:26:39.139838 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 17:26:39.145595 board id: 1
625 17:26:39.150682 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 17:26:39.161330 fw parse done
627 17:26:39.167197 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 17:26:39.209842 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 17:26:39.220898 PIEI prepare done
630 17:26:39.221400 fastboot data load
631 17:26:39.221860 fastboot data verify
632 17:26:39.226367 verify result: 266
633 17:26:39.232120 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 17:26:39.232619 LPDDR4 probe
635 17:26:39.233066 ddr clk to 1584MHz
636 17:26:39.240046 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 17:26:39.277269
638 17:26:39.277804 dmc_version 0001
639 17:26:39.283972 Check phy result
640 17:26:39.289801 INFO : End of CA training
641 17:26:39.290287 INFO : End of initialization
642 17:26:39.295379 INFO : Training has run successfully!
643 17:26:39.295893 Check phy result
644 17:26:39.300873 INFO : End of initialization
645 17:26:39.301353 INFO : End of read enable training
646 17:26:39.306608 INFO : End of fine write leveling
647 17:26:39.312273 INFO : End of Write leveling coarse delay
648 17:26:39.312765 INFO : Training has run successfully!
649 17:26:39.313215 Check phy result
650 17:26:39.317802 INFO : End of initialization
651 17:26:39.318280 INFO : End of read dq deskew training
652 17:26:39.323442 INFO : End of MPR read delay center optimization
653 17:26:39.328925 INFO : End of write delay center optimization
654 17:26:39.334571 INFO : End of read delay center optimization
655 17:26:39.335070 INFO : End of max read latency training
656 17:26:39.340279 INFO : Training has run successfully!
657 17:26:39.340781 1D training succeed
658 17:26:39.349511 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 17:26:39.397053 Check phy result
660 17:26:39.397622 INFO : End of initialization
661 17:26:39.419752 INFO : End of 2D read delay Voltage center optimization
662 17:26:39.441440 INFO : End of 2D read delay Voltage center optimization
663 17:26:39.491834 INFO : End of 2D write delay Voltage center optimization
664 17:26:39.541214 INFO : End of 2D write delay Voltage center optimization
665 17:26:39.546713 INFO : Training has run successfully!
666 17:26:39.547201
667 17:26:39.547658 channel==0
668 17:26:39.552318 RxClkDly_Margin_A0==88 ps 9
669 17:26:39.552802 TxDqDly_Margin_A0==98 ps 10
670 17:26:39.555584 RxClkDly_Margin_A1==88 ps 9
671 17:26:39.556085 TxDqDly_Margin_A1==98 ps 10
672 17:26:39.561117 TrainedVREFDQ_A0==74
673 17:26:39.561594 TrainedVREFDQ_A1==74
674 17:26:39.567054 VrefDac_Margin_A0==25
675 17:26:39.567561 DeviceVref_Margin_A0==40
676 17:26:39.568045 VrefDac_Margin_A1==25
677 17:26:39.572612 DeviceVref_Margin_A1==40
678 17:26:39.573144
679 17:26:39.573613
680 17:26:39.574058 channel==1
681 17:26:39.574524 RxClkDly_Margin_A0==98 ps 10
682 17:26:39.575874 TxDqDly_Margin_A0==98 ps 10
683 17:26:39.581141 RxClkDly_Margin_A1==88 ps 9
684 17:26:39.581644 TxDqDly_Margin_A1==88 ps 9
685 17:26:39.586851 TrainedVREFDQ_A0==77
686 17:26:39.587371 TrainedVREFDQ_A1==77
687 17:26:39.587829 VrefDac_Margin_A0==23
688 17:26:39.592397 DeviceVref_Margin_A0==37
689 17:26:39.592902 VrefDac_Margin_A1==24
690 17:26:39.593358 DeviceVref_Margin_A1==37
691 17:26:39.593805
692 17:26:39.601471 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 17:26:39.602006
694 17:26:39.629430 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 17:26:39.630046 2D training succeed
696 17:26:39.640640 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 17:26:39.641164 auto size-- 65535DDR cs0 size: 2048MB
698 17:26:39.641619 DDR cs1 size: 2048MB
699 17:26:39.646182 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 17:26:39.646504 cs0 DataBus test pass
701 17:26:39.651782 cs1 DataBus test pass
702 17:26:39.652135 cs0 AddrBus test pass
703 17:26:39.657379 cs1 AddrBus test pass
704 17:26:39.657688
705 17:26:39.657927 100bdlr_step_size ps== 420
706 17:26:39.658172 result report
707 17:26:39.662958 boot times 0Enable ddr reg access
708 17:26:39.669578 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 17:26:39.683048 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 17:26:40.257430 0.0;M3 CHK:0;cm4_sp_mode 0
711 17:26:40.258066 MVN_1=0x00000000
712 17:26:40.262146 MVN_2=0x00000000
713 17:26:40.267877 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 17:26:40.268450 OPS=0x10
715 17:26:40.268893 ring efuse init
716 17:26:40.269324 chipver efuse init
717 17:26:40.273478 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 17:26:40.279068 [0.018961 Inits done]
719 17:26:40.279530 secure task start!
720 17:26:40.279960 high task start!
721 17:26:40.283629 low task start!
722 17:26:40.284118 run into bl31
723 17:26:40.290322 NOTICE: BL31: v1.3(release):4fc40b1
724 17:26:40.298135 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 17:26:40.298600 NOTICE: BL31: G12A normal boot!
726 17:26:40.323528 NOTICE: BL31: BL33 decompress pass
727 17:26:40.329265 ERROR: Error initializing runtime service opteed_fast
728 17:26:41.562162
729 17:26:41.562845
730 17:26:41.570523 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 17:26:41.571062
732 17:26:41.571522 Model: Libre Computer AML-A311D-CC Alta
733 17:26:41.778009 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 17:26:41.802334 DRAM: 2 GiB (effective 3.8 GiB)
735 17:26:41.945354 Core: 408 devices, 31 uclasses, devicetree: separate
736 17:26:41.951169 WDT: Not starting watchdog@f0d0
737 17:26:41.983475 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 17:26:41.995950 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 17:26:42.000877 ** Bad device specification mmc 0 **
740 17:26:42.011234 Card did not respond to voltage select! : -110
741 17:26:42.018866 ** Bad device specification mmc 0 **
742 17:26:42.019435 Couldn't find partition mmc 0
743 17:26:42.027251 Card did not respond to voltage select! : -110
744 17:26:42.032761 ** Bad device specification mmc 0 **
745 17:26:42.033345 Couldn't find partition mmc 0
746 17:26:42.037779 Error: could not access storage.
747 17:26:42.380301 Net: eth0: ethernet@ff3f0000
748 17:26:42.380934 starting USB...
749 17:26:42.632124 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 17:26:42.632757 Starting the controller
751 17:26:42.639067 USB XHCI 1.10
752 17:26:44.800069 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 17:26:44.800729 bl2_stage_init 0x01
754 17:26:44.801202 bl2_stage_init 0x81
755 17:26:44.805463 hw id: 0x0000 - pwm id 0x01
756 17:26:44.806036 bl2_stage_init 0xc1
757 17:26:44.806532 bl2_stage_init 0x02
758 17:26:44.807017
759 17:26:44.811111 L0:00000000
760 17:26:44.811643 L1:20000703
761 17:26:44.812162 L2:00008067
762 17:26:44.812642 L3:14000000
763 17:26:44.816757 B2:00402000
764 17:26:44.817326 B1:e0f83180
765 17:26:44.817831
766 17:26:44.818322 TE: 58167
767 17:26:44.818803
768 17:26:44.822262 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 17:26:44.822809
770 17:26:44.823295 Board ID = 1
771 17:26:44.827838 Set A53 clk to 24M
772 17:26:44.828400 Set A73 clk to 24M
773 17:26:44.828885 Set clk81 to 24M
774 17:26:44.833449 A53 clk: 1200 MHz
775 17:26:44.833993 A73 clk: 1200 MHz
776 17:26:44.834473 CLK81: 166.6M
777 17:26:44.834962 smccc: 00012abd
778 17:26:44.839051 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 17:26:44.844638 board id: 1
780 17:26:44.850549 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 17:26:44.861229 fw parse done
782 17:26:44.867154 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 17:26:44.909835 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 17:26:44.920723 PIEI prepare done
785 17:26:44.921298 fastboot data load
786 17:26:44.921813 fastboot data verify
787 17:26:44.926365 verify result: 266
788 17:26:44.932072 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 17:26:44.932630 LPDDR4 probe
790 17:26:44.933112 ddr clk to 1584MHz
791 17:26:44.939860 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 17:26:44.977212
793 17:26:44.977838 dmc_version 0001
794 17:26:44.983937 Check phy result
795 17:26:44.989799 INFO : End of CA training
796 17:26:44.990414 INFO : End of initialization
797 17:26:44.995379 INFO : Training has run successfully!
798 17:26:44.995954 Check phy result
799 17:26:45.000981 INFO : End of initialization
800 17:26:45.001567 INFO : End of read enable training
801 17:26:45.006671 INFO : End of fine write leveling
802 17:26:45.012132 INFO : End of Write leveling coarse delay
803 17:26:45.012723 INFO : Training has run successfully!
804 17:26:45.013293 Check phy result
805 17:26:45.017727 INFO : End of initialization
806 17:26:45.018293 INFO : End of read dq deskew training
807 17:26:45.023340 INFO : End of MPR read delay center optimization
808 17:26:45.028889 INFO : End of write delay center optimization
809 17:26:45.034501 INFO : End of read delay center optimization
810 17:26:45.035045 INFO : End of max read latency training
811 17:26:45.040141 INFO : Training has run successfully!
812 17:26:45.040746 1D training succeed
813 17:26:45.049270 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 17:26:45.096982 Check phy result
815 17:26:45.097637 INFO : End of initialization
816 17:26:45.118608 INFO : End of 2D read delay Voltage center optimization
817 17:26:45.138846 INFO : End of 2D read delay Voltage center optimization
818 17:26:45.191791 INFO : End of 2D write delay Voltage center optimization
819 17:26:45.241349 INFO : End of 2D write delay Voltage center optimization
820 17:26:45.246807 INFO : Training has run successfully!
821 17:26:45.247322
822 17:26:45.247775 channel==0
823 17:26:45.252324 RxClkDly_Margin_A0==78 ps 8
824 17:26:45.252838 TxDqDly_Margin_A0==98 ps 10
825 17:26:45.255807 RxClkDly_Margin_A1==88 ps 9
826 17:26:45.256352 TxDqDly_Margin_A1==98 ps 10
827 17:26:45.261407 TrainedVREFDQ_A0==74
828 17:26:45.261914 TrainedVREFDQ_A1==74
829 17:26:45.262381 VrefDac_Margin_A0==25
830 17:26:45.267043 DeviceVref_Margin_A0==40
831 17:26:45.267572 VrefDac_Margin_A1==24
832 17:26:45.272667 DeviceVref_Margin_A1==40
833 17:26:45.273188
834 17:26:45.273625
835 17:26:45.274057 channel==1
836 17:26:45.274480 RxClkDly_Margin_A0==98 ps 10
837 17:26:45.276068 TxDqDly_Margin_A0==88 ps 9
838 17:26:45.281616 RxClkDly_Margin_A1==88 ps 9
839 17:26:45.282131 TxDqDly_Margin_A1==88 ps 9
840 17:26:45.282570 TrainedVREFDQ_A0==77
841 17:26:45.287265 TrainedVREFDQ_A1==77
842 17:26:45.287768 VrefDac_Margin_A0==22
843 17:26:45.292641 DeviceVref_Margin_A0==37
844 17:26:45.293134 VrefDac_Margin_A1==24
845 17:26:45.293561 DeviceVref_Margin_A1==37
846 17:26:45.293990
847 17:26:45.301863 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 17:26:45.302369
849 17:26:45.327822 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000017 00000016 00000018 00000016 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
850 17:26:45.333196 2D training succeed
851 17:26:45.338831 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 17:26:45.339357 auto size-- 65535DDR cs0 size: 2048MB
853 17:26:45.344426 DDR cs1 size: 2048MB
854 17:26:45.344938 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 17:26:45.350035 cs0 DataBus test pass
856 17:26:45.350539 cs1 DataBus test pass
857 17:26:45.355640 cs0 AddrBus test pass
858 17:26:45.356180 cs1 AddrBus test pass
859 17:26:45.356622
860 17:26:45.357062 100bdlr_step_size ps== 420
861 17:26:45.361215 result report
862 17:26:45.361710 boot times 0Enable ddr reg access
863 17:26:45.368792 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 17:26:45.382016 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 17:26:45.956634 0.0;M3 CHK:0;cm4_sp_mode 0
866 17:26:45.957298 MVN_1=0x00000000
867 17:26:45.962117 MVN_2=0x00000000
868 17:26:45.967882 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 17:26:45.968477 OPS=0x10
870 17:26:45.968949 ring efuse init
871 17:26:45.969412 chipver efuse init
872 17:26:45.973423 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 17:26:45.979087 [0.018961 Inits done]
874 17:26:45.979595 secure task start!
875 17:26:45.980079 high task start!
876 17:26:45.982793 low task start!
877 17:26:45.983300 run into bl31
878 17:26:45.990292 NOTICE: BL31: v1.3(release):4fc40b1
879 17:26:45.997086 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 17:26:45.997604 NOTICE: BL31: G12A normal boot!
881 17:26:46.023479 NOTICE: BL31: BL33 decompress pass
882 17:26:46.028173 ERROR: Error initializing runtime service opteed_fast
883 17:26:47.262009
884 17:26:47.262662
885 17:26:47.270445 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 17:26:47.271014
887 17:26:47.271518 Model: Libre Computer AML-A311D-CC Alta
888 17:26:47.479008 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 17:26:47.501409 DRAM: 2 GiB (effective 3.8 GiB)
890 17:26:47.645257 Core: 408 devices, 31 uclasses, devicetree: separate
891 17:26:47.651088 WDT: Not starting watchdog@f0d0
892 17:26:47.683348 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 17:26:47.695813 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 17:26:47.700802 ** Bad device specification mmc 0 **
895 17:26:47.711172 Card did not respond to voltage select! : -110
896 17:26:47.718802 ** Bad device specification mmc 0 **
897 17:26:47.719323 Couldn't find partition mmc 0
898 17:26:47.727096 Card did not respond to voltage select! : -110
899 17:26:47.732646 ** Bad device specification mmc 0 **
900 17:26:47.733177 Couldn't find partition mmc 0
901 17:26:47.737698 Error: could not access storage.
902 17:26:48.080389 Net: eth0: ethernet@ff3f0000
903 17:26:48.081093 starting USB...
904 17:26:48.332056 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 17:26:48.332819 Starting the controller
906 17:26:48.338988 USB XHCI 1.10
907 17:26:50.199681 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 17:26:50.200416 bl2_stage_init 0x01
909 17:26:50.200921 bl2_stage_init 0x81
910 17:26:50.205177 hw id: 0x0000 - pwm id 0x01
911 17:26:50.205743 bl2_stage_init 0xc1
912 17:26:50.206266 bl2_stage_init 0x02
913 17:26:50.206777
914 17:26:50.210725 L0:00000000
915 17:26:50.211377 L1:20000703
916 17:26:50.211949 L2:00008067
917 17:26:50.212463 L3:14000000
918 17:26:50.216288 B2:00402000
919 17:26:50.216820 B1:e0f83180
920 17:26:50.217289
921 17:26:50.217776 TE: 58159
922 17:26:50.218277
923 17:26:50.221848 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 17:26:50.222405
925 17:26:50.222874 Board ID = 1
926 17:26:50.227508 Set A53 clk to 24M
927 17:26:50.228036 Set A73 clk to 24M
928 17:26:50.228485 Set clk81 to 24M
929 17:26:50.233034 A53 clk: 1200 MHz
930 17:26:50.233527 A73 clk: 1200 MHz
931 17:26:50.233955 CLK81: 166.6M
932 17:26:50.234374 smccc: 00012ab5
933 17:26:50.238585 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 17:26:50.244249 board id: 1
935 17:26:50.250184 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 17:26:50.260713 fw parse done
937 17:26:50.266686 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 17:26:50.309345 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 17:26:50.320324 PIEI prepare done
940 17:26:50.320848 fastboot data load
941 17:26:50.321263 fastboot data verify
942 17:26:50.325936 verify result: 266
943 17:26:50.331600 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 17:26:50.332136 LPDDR4 probe
945 17:26:50.332537 ddr clk to 1584MHz
946 17:26:50.339653 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 17:26:50.376924
948 17:26:50.377480 dmc_version 0001
949 17:26:50.383571 Check phy result
950 17:26:50.389403 INFO : End of CA training
951 17:26:50.389919 INFO : End of initialization
952 17:26:50.394943 INFO : Training has run successfully!
953 17:26:50.395445 Check phy result
954 17:26:50.400657 INFO : End of initialization
955 17:26:50.401206 INFO : End of read enable training
956 17:26:50.404017 INFO : End of fine write leveling
957 17:26:50.409534 INFO : End of Write leveling coarse delay
958 17:26:50.415174 INFO : Training has run successfully!
959 17:26:50.415657 Check phy result
960 17:26:50.416089 INFO : End of initialization
961 17:26:50.420694 INFO : End of read dq deskew training
962 17:26:50.426351 INFO : End of MPR read delay center optimization
963 17:26:50.426808 INFO : End of write delay center optimization
964 17:26:50.431851 INFO : End of read delay center optimization
965 17:26:50.437510 INFO : End of max read latency training
966 17:26:50.438007 INFO : Training has run successfully!
967 17:26:50.443063 1D training succeed
968 17:26:50.448967 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 17:26:50.496500 Check phy result
970 17:26:50.496998 INFO : End of initialization
971 17:26:50.519031 INFO : End of 2D read delay Voltage center optimization
972 17:26:50.539161 INFO : End of 2D read delay Voltage center optimization
973 17:26:50.591061 INFO : End of 2D write delay Voltage center optimization
974 17:26:50.640521 INFO : End of 2D write delay Voltage center optimization
975 17:26:50.645889 INFO : Training has run successfully!
976 17:26:50.646347
977 17:26:50.646765 channel==0
978 17:26:50.651507 RxClkDly_Margin_A0==88 ps 9
979 17:26:50.651958 TxDqDly_Margin_A0==98 ps 10
980 17:26:50.654846 RxClkDly_Margin_A1==88 ps 9
981 17:26:50.655279 TxDqDly_Margin_A1==98 ps 10
982 17:26:50.660421 TrainedVREFDQ_A0==74
983 17:26:50.660869 TrainedVREFDQ_A1==76
984 17:26:50.661277 VrefDac_Margin_A0==25
985 17:26:50.666004 DeviceVref_Margin_A0==40
986 17:26:50.666438 VrefDac_Margin_A1==25
987 17:26:50.671630 DeviceVref_Margin_A1==38
988 17:26:50.672091
989 17:26:50.672503
990 17:26:50.672900 channel==1
991 17:26:50.673292 RxClkDly_Margin_A0==98 ps 10
992 17:26:50.677247 TxDqDly_Margin_A0==98 ps 10
993 17:26:50.677691 RxClkDly_Margin_A1==98 ps 10
994 17:26:50.682824 TxDqDly_Margin_A1==98 ps 10
995 17:26:50.683301 TrainedVREFDQ_A0==77
996 17:26:50.683717 TrainedVREFDQ_A1==78
997 17:26:50.688361 VrefDac_Margin_A0==22
998 17:26:50.688799 DeviceVref_Margin_A0==37
999 17:26:50.693992 VrefDac_Margin_A1==22
1000 17:26:50.694432 DeviceVref_Margin_A1==36
1001 17:26:50.694832
1002 17:26:50.699590 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 17:26:50.700136
1004 17:26:50.727523 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1005 17:26:50.733234 2D training succeed
1006 17:26:50.738686 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 17:26:50.739125 auto size-- 65535DDR cs0 size: 2048MB
1008 17:26:50.744263 DDR cs1 size: 2048MB
1009 17:26:50.744699 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 17:26:50.749895 cs0 DataBus test pass
1011 17:26:50.750346 cs1 DataBus test pass
1012 17:26:50.750754 cs0 AddrBus test pass
1013 17:26:50.755446 cs1 AddrBus test pass
1014 17:26:50.755879
1015 17:26:50.756332 100bdlr_step_size ps== 420
1016 17:26:50.756743 result report
1017 17:26:50.761139 boot times 0Enable ddr reg access
1018 17:26:50.768872 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 17:26:50.782341 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 17:26:51.354570 0.0;M3 CHK:0;cm4_sp_mode 0
1021 17:26:51.355216 MVN_1=0x00000000
1022 17:26:51.359891 MVN_2=0x00000000
1023 17:26:51.365606 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 17:26:51.366060 OPS=0x10
1025 17:26:51.366473 ring efuse init
1026 17:26:51.366876 chipver efuse init
1027 17:26:51.371233 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 17:26:51.376810 [0.018961 Inits done]
1029 17:26:51.377267 secure task start!
1030 17:26:51.377680 high task start!
1031 17:26:51.381427 low task start!
1032 17:26:51.381870 run into bl31
1033 17:26:51.388047 NOTICE: BL31: v1.3(release):4fc40b1
1034 17:26:51.395852 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 17:26:51.396325 NOTICE: BL31: G12A normal boot!
1036 17:26:51.421876 NOTICE: BL31: BL33 decompress pass
1037 17:26:51.427471 ERROR: Error initializing runtime service opteed_fast
1038 17:26:52.660522
1039 17:26:52.660941
1040 17:26:52.668845 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 17:26:52.669313
1042 17:26:52.669726 Model: Libre Computer AML-A311D-CC Alta
1043 17:26:52.877250 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 17:26:52.900648 DRAM: 2 GiB (effective 3.8 GiB)
1045 17:26:53.043731 Core: 408 devices, 31 uclasses, devicetree: separate
1046 17:26:53.049534 WDT: Not starting watchdog@f0d0
1047 17:26:53.081721 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 17:26:53.094200 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 17:26:53.099228 ** Bad device specification mmc 0 **
1050 17:26:53.109592 Card did not respond to voltage select! : -110
1051 17:26:53.117167 ** Bad device specification mmc 0 **
1052 17:26:53.117616 Couldn't find partition mmc 0
1053 17:26:53.125581 Card did not respond to voltage select! : -110
1054 17:26:53.131012 ** Bad device specification mmc 0 **
1055 17:26:53.131451 Couldn't find partition mmc 0
1056 17:26:53.136069 Error: could not access storage.
1057 17:26:53.478543 Net: eth0: ethernet@ff3f0000
1058 17:26:53.479126 starting USB...
1059 17:26:53.730408 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 17:26:53.731036 Starting the controller
1061 17:26:53.737294 USB XHCI 1.10
1062 17:26:55.291445 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 17:26:55.299618 scanning usb for storage devices... 0 Storage Device(s) found
1065 17:26:55.351263 Hit any key to stop autoboot: 1
1066 17:26:55.352164 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 17:26:55.352743 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 17:26:55.353199 Setting prompt string to ['=>']
1069 17:26:55.353660 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 17:26:55.367053 0
1071 17:26:55.367903 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 17:26:55.368451 Sending with 10 millisecond of delay
1074 17:26:56.503357 => setenv autoload no
1075 17:26:56.514172 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1076 17:26:56.516851 setenv autoload no
1077 17:26:56.517359 Sending with 10 millisecond of delay
1079 17:26:58.314371 => setenv initrd_high 0xffffffff
1080 17:26:58.325169 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 17:26:58.325996 setenv initrd_high 0xffffffff
1082 17:26:58.326690 Sending with 10 millisecond of delay
1084 17:26:59.943844 => setenv fdt_high 0xffffffff
1085 17:26:59.954904 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 17:26:59.956099 setenv fdt_high 0xffffffff
1087 17:26:59.957031 Sending with 10 millisecond of delay
1089 17:27:00.249317 => dhcp
1090 17:27:00.260313 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 17:27:00.261393 dhcp
1092 17:27:00.261985 Speed: 1000, full duplex
1093 17:27:00.262533 BOOTP broadcast 1
1094 17:27:00.268817 DHCP client bound to address 192.168.6.27 (9 ms)
1095 17:27:00.269689 Sending with 10 millisecond of delay
1097 17:27:01.947447 => setenv serverip 192.168.6.2
1098 17:27:01.958289 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 17:27:01.959189 setenv serverip 192.168.6.2
1100 17:27:01.959880 Sending with 10 millisecond of delay
1102 17:27:05.687290 => tftpboot 0x01080000 954110/tftp-deploy-0gsuoaja/kernel/uImage
1103 17:27:05.698299 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 17:27:05.699401 tftpboot 0x01080000 954110/tftp-deploy-0gsuoaja/kernel/uImage
1105 17:27:05.700098 Speed: 1000, full duplex
1106 17:27:05.700669 Using ethernet@ff3f0000 device
1107 17:27:05.701375 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 17:27:05.706503 Filename '954110/tftp-deploy-0gsuoaja/kernel/uImage'.
1109 17:27:05.710293 Load address: 0x1080000
1110 17:27:08.692139 Loading: *################################################## 43.6 MiB
1111 17:27:08.692815 14.6 MiB/s
1112 17:27:08.693295 done
1113 17:27:08.696756 Bytes transferred = 45713984 (2b98a40 hex)
1114 17:27:08.697631 Sending with 10 millisecond of delay
1116 17:27:13.386870 => tftpboot 0x08000000 954110/tftp-deploy-0gsuoaja/ramdisk/ramdisk.cpio.gz.uboot
1117 17:27:13.397722 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1118 17:27:13.398626 tftpboot 0x08000000 954110/tftp-deploy-0gsuoaja/ramdisk/ramdisk.cpio.gz.uboot
1119 17:27:13.399146 Speed: 1000, full duplex
1120 17:27:13.399625 Using ethernet@ff3f0000 device
1121 17:27:13.400997 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 17:27:13.412363 Filename '954110/tftp-deploy-0gsuoaja/ramdisk/ramdisk.cpio.gz.uboot'.
1123 17:27:13.412962 Load address: 0x8000000
1124 17:27:19.799454 Loading: *#############T ################## UDP wrong checksum 000000ff 00005bd2
1125 17:27:19.836635 # UDP wrong checksum 000000ff 0000f5c4
1126 17:27:20.715878 ################# UDP wrong checksum 00000005 0000cb20
1127 17:27:25.718558 T UDP wrong checksum 00000005 0000cb20
1128 17:27:35.720498 T T UDP wrong checksum 00000005 0000cb20
1129 17:27:55.724331 T T T T UDP wrong checksum 00000005 0000cb20
1130 17:28:09.272244 T T UDP wrong checksum 000000ff 00008430
1131 17:28:09.315446 UDP wrong checksum 000000ff 00001423
1132 17:28:10.728319
1133 17:28:10.729019 Retry count exceeded; starting again
1135 17:28:10.730613 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1138 17:28:10.732708 end: 2.4 uboot-commands (duration 00:01:53) [common]
1140 17:28:10.734249 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1142 17:28:10.735407 end: 2 uboot-action (duration 00:01:53) [common]
1144 17:28:10.737172 Cleaning after the job
1145 17:28:10.737813 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954110/tftp-deploy-0gsuoaja/ramdisk
1146 17:28:10.739381 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954110/tftp-deploy-0gsuoaja/kernel
1147 17:28:10.777315 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954110/tftp-deploy-0gsuoaja/dtb
1148 17:28:10.778364 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954110/tftp-deploy-0gsuoaja/modules
1149 17:28:10.800120 start: 4.1 power-off (timeout 00:00:30) [common]
1150 17:28:10.800866 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1151 17:28:10.840152 >> OK - accepted request
1152 17:28:10.841622 Returned 0 in 0 seconds
1153 17:28:10.942740 end: 4.1 power-off (duration 00:00:00) [common]
1155 17:28:10.943766 start: 4.2 read-feedback (timeout 00:10:00) [common]
1156 17:28:10.944532 Listened to connection for namespace 'common' for up to 1s
1157 17:28:11.944686 Finalising connection for namespace 'common'
1158 17:28:11.945509 Disconnecting from shell: Finalise
1159 17:28:11.946100 =>
1160 17:28:12.047294 end: 4.2 read-feedback (duration 00:00:01) [common]
1161 17:28:12.048167 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/954110
1162 17:28:12.353662 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/954110
1163 17:28:12.354288 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.