Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 19:42:05.694536 lava-dispatcher, installed at version: 2024.01
2 19:42:05.696219 start: 0 validate
3 19:42:05.696759 Start time: 2024-11-07 19:42:05.696725+00:00 (UTC)
4 19:42:05.697379 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:42:05.697978 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:42:05.742219 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:42:05.742812 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 19:42:05.777923 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:42:05.778994 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 19:42:05.814129 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:42:05.814666 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:42:05.846790 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 19:42:05.847318 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 19:42:05.890704 validate duration: 0.19
16 19:42:05.892330 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:42:05.892968 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:42:05.893579 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:42:05.894594 Not decompressing ramdisk as can be used compressed.
20 19:42:05.895424 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 19:42:05.895964 saving as /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/ramdisk/initrd.cpio.gz
22 19:42:05.896516 total size: 5628169 (5 MB)
23 19:42:05.939076 progress 0 % (0 MB)
24 19:42:05.946593 progress 5 % (0 MB)
25 19:42:05.954704 progress 10 % (0 MB)
26 19:42:05.961911 progress 15 % (0 MB)
27 19:42:05.969190 progress 20 % (1 MB)
28 19:42:05.973029 progress 25 % (1 MB)
29 19:42:05.977304 progress 30 % (1 MB)
30 19:42:05.981574 progress 35 % (1 MB)
31 19:42:05.985347 progress 40 % (2 MB)
32 19:42:05.989356 progress 45 % (2 MB)
33 19:42:05.993097 progress 50 % (2 MB)
34 19:42:05.997245 progress 55 % (2 MB)
35 19:42:06.001376 progress 60 % (3 MB)
36 19:42:06.005216 progress 65 % (3 MB)
37 19:42:06.009673 progress 70 % (3 MB)
38 19:42:06.013507 progress 75 % (4 MB)
39 19:42:06.017631 progress 80 % (4 MB)
40 19:42:06.021379 progress 85 % (4 MB)
41 19:42:06.025614 progress 90 % (4 MB)
42 19:42:06.029619 progress 95 % (5 MB)
43 19:42:06.033015 progress 100 % (5 MB)
44 19:42:06.033706 5 MB downloaded in 0.14 s (39.13 MB/s)
45 19:42:06.034335 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:42:06.035250 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:42:06.035549 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:42:06.035826 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:42:06.036349 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm64/defconfig/gcc-12/kernel/Image
51 19:42:06.036630 saving as /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/kernel/Image
52 19:42:06.036843 total size: 45713920 (43 MB)
53 19:42:06.037058 No compression specified
54 19:42:06.075867 progress 0 % (0 MB)
55 19:42:06.105405 progress 5 % (2 MB)
56 19:42:06.133803 progress 10 % (4 MB)
57 19:42:06.162116 progress 15 % (6 MB)
58 19:42:06.190271 progress 20 % (8 MB)
59 19:42:06.218167 progress 25 % (10 MB)
60 19:42:06.246280 progress 30 % (13 MB)
61 19:42:06.274321 progress 35 % (15 MB)
62 19:42:06.302584 progress 40 % (17 MB)
63 19:42:06.331185 progress 45 % (19 MB)
64 19:42:06.360232 progress 50 % (21 MB)
65 19:42:06.389414 progress 55 % (24 MB)
66 19:42:06.419719 progress 60 % (26 MB)
67 19:42:06.448563 progress 65 % (28 MB)
68 19:42:06.477721 progress 70 % (30 MB)
69 19:42:06.506551 progress 75 % (32 MB)
70 19:42:06.535102 progress 80 % (34 MB)
71 19:42:06.563176 progress 85 % (37 MB)
72 19:42:06.591585 progress 90 % (39 MB)
73 19:42:06.619944 progress 95 % (41 MB)
74 19:42:06.647744 progress 100 % (43 MB)
75 19:42:06.648330 43 MB downloaded in 0.61 s (71.30 MB/s)
76 19:42:06.648800 end: 1.2.1 http-download (duration 00:00:01) [common]
78 19:42:06.649617 end: 1.2 download-retry (duration 00:00:01) [common]
79 19:42:06.649895 start: 1.3 download-retry (timeout 00:09:59) [common]
80 19:42:06.650161 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 19:42:06.650616 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 19:42:06.650880 saving as /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/dtb/meson-g12b-a311d-libretech-cc.dtb
83 19:42:06.651089 total size: 54703 (0 MB)
84 19:42:06.651297 No compression specified
85 19:42:06.693375 progress 59 % (0 MB)
86 19:42:06.694213 progress 100 % (0 MB)
87 19:42:06.694759 0 MB downloaded in 0.04 s (1.19 MB/s)
88 19:42:06.695212 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:42:06.696066 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:42:06.696347 start: 1.4 download-retry (timeout 00:09:59) [common]
92 19:42:06.696614 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 19:42:06.697071 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 19:42:06.697312 saving as /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/nfsrootfs/full.rootfs.tar
95 19:42:06.697518 total size: 120894716 (115 MB)
96 19:42:06.697731 Using unxz to decompress xz
97 19:42:06.734225 progress 0 % (0 MB)
98 19:42:07.532108 progress 5 % (5 MB)
99 19:42:08.384752 progress 10 % (11 MB)
100 19:42:09.182223 progress 15 % (17 MB)
101 19:42:09.923193 progress 20 % (23 MB)
102 19:42:10.517712 progress 25 % (28 MB)
103 19:42:11.341337 progress 30 % (34 MB)
104 19:42:12.147685 progress 35 % (40 MB)
105 19:42:12.513678 progress 40 % (46 MB)
106 19:42:12.906486 progress 45 % (51 MB)
107 19:42:13.639362 progress 50 % (57 MB)
108 19:42:14.525560 progress 55 % (63 MB)
109 19:42:15.313392 progress 60 % (69 MB)
110 19:42:16.073426 progress 65 % (74 MB)
111 19:42:16.854524 progress 70 % (80 MB)
112 19:42:17.684859 progress 75 % (86 MB)
113 19:42:18.476187 progress 80 % (92 MB)
114 19:42:19.247461 progress 85 % (98 MB)
115 19:42:20.112801 progress 90 % (103 MB)
116 19:42:20.905325 progress 95 % (109 MB)
117 19:42:21.757690 progress 100 % (115 MB)
118 19:42:21.770264 115 MB downloaded in 15.07 s (7.65 MB/s)
119 19:42:21.770995 end: 1.4.1 http-download (duration 00:00:15) [common]
121 19:42:21.772849 end: 1.4 download-retry (duration 00:00:15) [common]
122 19:42:21.773436 start: 1.5 download-retry (timeout 00:09:44) [common]
123 19:42:21.774015 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 19:42:21.774890 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm64/defconfig/gcc-12/modules.tar.xz
125 19:42:21.775399 saving as /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/modules/modules.tar
126 19:42:21.775856 total size: 11613380 (11 MB)
127 19:42:21.776365 Using unxz to decompress xz
128 19:42:21.822634 progress 0 % (0 MB)
129 19:42:21.889406 progress 5 % (0 MB)
130 19:42:21.968123 progress 10 % (1 MB)
131 19:42:22.066048 progress 15 % (1 MB)
132 19:42:22.157186 progress 20 % (2 MB)
133 19:42:22.237541 progress 25 % (2 MB)
134 19:42:22.313087 progress 30 % (3 MB)
135 19:42:22.391784 progress 35 % (3 MB)
136 19:42:22.464830 progress 40 % (4 MB)
137 19:42:22.541666 progress 45 % (5 MB)
138 19:42:22.626867 progress 50 % (5 MB)
139 19:42:22.704596 progress 55 % (6 MB)
140 19:42:22.789919 progress 60 % (6 MB)
141 19:42:22.870640 progress 65 % (7 MB)
142 19:42:22.951371 progress 70 % (7 MB)
143 19:42:23.029936 progress 75 % (8 MB)
144 19:42:23.113408 progress 80 % (8 MB)
145 19:42:23.193327 progress 85 % (9 MB)
146 19:42:23.271592 progress 90 % (9 MB)
147 19:42:23.351216 progress 95 % (10 MB)
148 19:42:23.428238 progress 100 % (11 MB)
149 19:42:23.440245 11 MB downloaded in 1.66 s (6.65 MB/s)
150 19:42:23.441115 end: 1.5.1 http-download (duration 00:00:02) [common]
152 19:42:23.442755 end: 1.5 download-retry (duration 00:00:02) [common]
153 19:42:23.443279 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 19:42:23.443802 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 19:42:40.485771 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/954173/extract-nfsrootfs-s39gb2dj
156 19:42:40.486412 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 19:42:40.486723 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 19:42:40.487501 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq
159 19:42:40.488034 makedir: /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin
160 19:42:40.488392 makedir: /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/tests
161 19:42:40.488716 makedir: /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/results
162 19:42:40.489051 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-add-keys
163 19:42:40.489576 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-add-sources
164 19:42:40.490085 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-background-process-start
165 19:42:40.490590 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-background-process-stop
166 19:42:40.491126 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-common-functions
167 19:42:40.491658 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-echo-ipv4
168 19:42:40.492187 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-install-packages
169 19:42:40.492684 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-installed-packages
170 19:42:40.493161 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-os-build
171 19:42:40.493644 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-probe-channel
172 19:42:40.494132 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-probe-ip
173 19:42:40.494615 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-target-ip
174 19:42:40.495093 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-target-mac
175 19:42:40.495572 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-target-storage
176 19:42:40.496081 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-test-case
177 19:42:40.496577 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-test-event
178 19:42:40.497069 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-test-feedback
179 19:42:40.497648 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-test-raise
180 19:42:40.498222 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-test-reference
181 19:42:40.498785 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-test-runner
182 19:42:40.499334 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-test-set
183 19:42:40.499874 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-test-shell
184 19:42:40.500489 Updating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-add-keys (debian)
185 19:42:40.501112 Updating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-add-sources (debian)
186 19:42:40.501767 Updating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-install-packages (debian)
187 19:42:40.502359 Updating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-installed-packages (debian)
188 19:42:40.502953 Updating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/bin/lava-os-build (debian)
189 19:42:40.503464 Creating /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/environment
190 19:42:40.503904 LAVA metadata
191 19:42:40.504239 - LAVA_JOB_ID=954173
192 19:42:40.504484 - LAVA_DISPATCHER_IP=192.168.6.2
193 19:42:40.504898 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 19:42:40.505974 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 19:42:40.506316 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 19:42:40.506548 skipped lava-vland-overlay
197 19:42:40.506814 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 19:42:40.507098 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 19:42:40.507351 skipped lava-multinode-overlay
200 19:42:40.507626 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 19:42:40.507916 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 19:42:40.508234 Loading test definitions
203 19:42:40.508563 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 19:42:40.508823 Using /lava-954173 at stage 0
205 19:42:40.510058 uuid=954173_1.6.2.4.1 testdef=None
206 19:42:40.510428 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 19:42:40.510751 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 19:42:40.512700 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 19:42:40.513616 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 19:42:40.515875 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 19:42:40.516824 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 19:42:40.518897 runner path: /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/0/tests/0_timesync-off test_uuid 954173_1.6.2.4.1
215 19:42:40.519512 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 19:42:40.520427 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 19:42:40.520689 Using /lava-954173 at stage 0
219 19:42:40.521082 Fetching tests from https://github.com/kernelci/test-definitions.git
220 19:42:40.521409 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/0/tests/1_kselftest-dt'
221 19:42:44.181494 Running '/usr/bin/git checkout kernelci.org
222 19:42:44.347955 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 19:42:44.349539 uuid=954173_1.6.2.4.5 testdef=None
224 19:42:44.349955 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 19:42:44.350736 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 19:42:44.353908 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 19:42:44.354809 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 19:42:44.359006 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 19:42:44.359950 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 19:42:44.363837 runner path: /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/0/tests/1_kselftest-dt test_uuid 954173_1.6.2.4.5
234 19:42:44.364207 BOARD='meson-g12b-a311d-libretech-cc'
235 19:42:44.364419 BRANCH='broonie-sound'
236 19:42:44.364618 SKIPFILE='/dev/null'
237 19:42:44.364815 SKIP_INSTALL='True'
238 19:42:44.365011 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 19:42:44.365213 TST_CASENAME=''
240 19:42:44.365410 TST_CMDFILES='dt'
241 19:42:44.366059 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 19:42:44.366891 Creating lava-test-runner.conf files
244 19:42:44.367101 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/954173/lava-overlay-pr5rl5rq/lava-954173/0 for stage 0
245 19:42:44.367488 - 0_timesync-off
246 19:42:44.367746 - 1_kselftest-dt
247 19:42:44.368142 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 19:42:44.368456 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 19:43:08.271322 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 19:43:08.271871 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 19:43:08.272229 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 19:43:08.272572 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 19:43:08.272902 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 19:43:08.896068 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 19:43:08.896554 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 19:43:08.896807 extracting modules file /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954173/extract-nfsrootfs-s39gb2dj
257 19:43:10.430272 extracting modules file /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954173/extract-overlay-ramdisk-4dxtpm55/ramdisk
258 19:43:11.876839 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 19:43:11.877326 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 19:43:11.877610 [common] Applying overlay to NFS
261 19:43:11.877829 [common] Applying overlay /var/lib/lava/dispatcher/tmp/954173/compress-overlay-t6pzwgs9/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/954173/extract-nfsrootfs-s39gb2dj
262 19:43:14.880174 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 19:43:14.880786 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 19:43:14.881141 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 19:43:14.881431 Converting downloaded kernel to a uImage
266 19:43:14.881821 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/kernel/Image /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/kernel/uImage
267 19:43:15.390252 output: Image Name:
268 19:43:15.390688 output: Created: Thu Nov 7 19:43:14 2024
269 19:43:15.390905 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 19:43:15.391115 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 19:43:15.391323 output: Load Address: 01080000
272 19:43:15.391527 output: Entry Point: 01080000
273 19:43:15.391726 output:
274 19:43:15.392101 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 19:43:15.392387 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 19:43:15.392665 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 19:43:15.392924 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 19:43:15.393186 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 19:43:15.393445 Building ramdisk /var/lib/lava/dispatcher/tmp/954173/extract-overlay-ramdisk-4dxtpm55/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/954173/extract-overlay-ramdisk-4dxtpm55/ramdisk
280 19:43:17.581435 >> 166792 blocks
281 19:43:25.617234 Adding RAMdisk u-boot header.
282 19:43:25.617691 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/954173/extract-overlay-ramdisk-4dxtpm55/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/954173/extract-overlay-ramdisk-4dxtpm55/ramdisk.cpio.gz.uboot
283 19:43:25.866777 output: Image Name:
284 19:43:25.867246 output: Created: Thu Nov 7 19:43:25 2024
285 19:43:25.867695 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 19:43:25.868160 output: Data Size: 23433373 Bytes = 22884.15 KiB = 22.35 MiB
287 19:43:25.868597 output: Load Address: 00000000
288 19:43:25.869007 output: Entry Point: 00000000
289 19:43:25.869416 output:
290 19:43:25.870461 rename /var/lib/lava/dispatcher/tmp/954173/extract-overlay-ramdisk-4dxtpm55/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/ramdisk/ramdisk.cpio.gz.uboot
291 19:43:25.871188 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 19:43:25.871749 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 19:43:25.872328 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 19:43:25.872796 No LXC device requested
295 19:43:25.873314 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 19:43:25.873837 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 19:43:25.874346 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 19:43:25.874764 Checking files for TFTP limit of 4294967296 bytes.
299 19:43:25.877547 end: 1 tftp-deploy (duration 00:01:20) [common]
300 19:43:25.878145 start: 2 uboot-action (timeout 00:05:00) [common]
301 19:43:25.878688 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 19:43:25.879205 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 19:43:25.879725 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 19:43:25.880302 Using kernel file from prepare-kernel: 954173/tftp-deploy-00jfgn93/kernel/uImage
305 19:43:25.880948 substitutions:
306 19:43:25.881372 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 19:43:25.881785 - {DTB_ADDR}: 0x01070000
308 19:43:25.882194 - {DTB}: 954173/tftp-deploy-00jfgn93/dtb/meson-g12b-a311d-libretech-cc.dtb
309 19:43:25.882602 - {INITRD}: 954173/tftp-deploy-00jfgn93/ramdisk/ramdisk.cpio.gz.uboot
310 19:43:25.883006 - {KERNEL_ADDR}: 0x01080000
311 19:43:25.883403 - {KERNEL}: 954173/tftp-deploy-00jfgn93/kernel/uImage
312 19:43:25.883801 - {LAVA_MAC}: None
313 19:43:25.884274 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/954173/extract-nfsrootfs-s39gb2dj
314 19:43:25.884583 - {NFS_SERVER_IP}: 192.168.6.2
315 19:43:25.884794 - {PRESEED_CONFIG}: None
316 19:43:25.885000 - {PRESEED_LOCAL}: None
317 19:43:25.885207 - {RAMDISK_ADDR}: 0x08000000
318 19:43:25.885479 - {RAMDISK}: 954173/tftp-deploy-00jfgn93/ramdisk/ramdisk.cpio.gz.uboot
319 19:43:25.885888 - {ROOT_PART}: None
320 19:43:25.886287 - {ROOT}: None
321 19:43:25.886701 - {SERVER_IP}: 192.168.6.2
322 19:43:25.887095 - {TEE_ADDR}: 0x83000000
323 19:43:25.887485 - {TEE}: None
324 19:43:25.887876 Parsed boot commands:
325 19:43:25.888291 - setenv autoload no
326 19:43:25.888685 - setenv initrd_high 0xffffffff
327 19:43:25.889074 - setenv fdt_high 0xffffffff
328 19:43:25.889461 - dhcp
329 19:43:25.889849 - setenv serverip 192.168.6.2
330 19:43:25.890240 - tftpboot 0x01080000 954173/tftp-deploy-00jfgn93/kernel/uImage
331 19:43:25.890636 - tftpboot 0x08000000 954173/tftp-deploy-00jfgn93/ramdisk/ramdisk.cpio.gz.uboot
332 19:43:25.891031 - tftpboot 0x01070000 954173/tftp-deploy-00jfgn93/dtb/meson-g12b-a311d-libretech-cc.dtb
333 19:43:25.891423 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/954173/extract-nfsrootfs-s39gb2dj,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 19:43:25.891826 - bootm 0x01080000 0x08000000 0x01070000
335 19:43:25.892377 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 19:43:25.893891 start: 2.3 connect-device (timeout 00:05:00) [common]
338 19:43:25.894322 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 19:43:25.909472 Setting prompt string to ['lava-test: # ']
340 19:43:25.911010 end: 2.3 connect-device (duration 00:00:00) [common]
341 19:43:25.911660 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 19:43:25.912275 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 19:43:25.912643 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 19:43:25.913409 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 19:43:25.960975 >> OK - accepted request
346 19:43:25.963161 Returned 0 in 0 seconds
347 19:43:26.064189 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 19:43:26.065913 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 19:43:26.066500 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 19:43:26.067022 Setting prompt string to ['Hit any key to stop autoboot']
352 19:43:26.067496 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 19:43:26.069106 Trying 192.168.56.21...
354 19:43:26.069599 Connected to conserv1.
355 19:43:26.070025 Escape character is '^]'.
356 19:43:26.070456
357 19:43:26.070886 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 19:43:26.071322
359 19:43:37.240700 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 19:43:37.241136 bl2_stage_init 0x01
361 19:43:37.241599 bl2_stage_init 0x81
362 19:43:37.246331 hw id: 0x0000 - pwm id 0x01
363 19:43:37.246659 bl2_stage_init 0xc1
364 19:43:37.246906 bl2_stage_init 0x02
365 19:43:37.247158
366 19:43:37.251667 L0:00000000
367 19:43:37.251973 L1:20000703
368 19:43:37.252242 L2:00008067
369 19:43:37.252648 L3:14000000
370 19:43:37.257245 B2:00402000
371 19:43:37.257550 B1:e0f83180
372 19:43:37.257767
373 19:43:37.257977 TE: 58167
374 19:43:37.258186
375 19:43:37.262881 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 19:43:37.263164
377 19:43:37.263593 Board ID = 1
378 19:43:37.268439 Set A53 clk to 24M
379 19:43:37.268875 Set A73 clk to 24M
380 19:43:37.269124 Set clk81 to 24M
381 19:43:37.273984 A53 clk: 1200 MHz
382 19:43:37.274268 A73 clk: 1200 MHz
383 19:43:37.274481 CLK81: 166.6M
384 19:43:37.274687 smccc: 00012abe
385 19:43:37.279678 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 19:43:37.285226 board id: 1
387 19:43:37.291181 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 19:43:37.301958 fw parse done
389 19:43:37.307878 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 19:43:37.350582 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 19:43:37.361412 PIEI prepare done
392 19:43:37.362107 fastboot data load
393 19:43:37.362678 fastboot data verify
394 19:43:37.366939 verify result: 266
395 19:43:37.372576 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 19:43:37.373258 LPDDR4 probe
397 19:43:37.373836 ddr clk to 1584MHz
398 19:43:37.380679 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 19:43:37.417852
400 19:43:37.418259 dmc_version 0001
401 19:43:37.424495 Check phy result
402 19:43:37.430316 INFO : End of CA training
403 19:43:37.430653 INFO : End of initialization
404 19:43:37.436083 INFO : Training has run successfully!
405 19:43:37.436459 Check phy result
406 19:43:37.441547 INFO : End of initialization
407 19:43:37.441891 INFO : End of read enable training
408 19:43:37.444804 INFO : End of fine write leveling
409 19:43:37.450395 INFO : End of Write leveling coarse delay
410 19:43:37.455928 INFO : Training has run successfully!
411 19:43:37.456291 Check phy result
412 19:43:37.456527 INFO : End of initialization
413 19:43:37.461516 INFO : End of read dq deskew training
414 19:43:37.467109 INFO : End of MPR read delay center optimization
415 19:43:37.467455 INFO : End of write delay center optimization
416 19:43:37.472758 INFO : End of read delay center optimization
417 19:43:37.478316 INFO : End of max read latency training
418 19:43:37.478667 INFO : Training has run successfully!
419 19:43:37.483954 1D training succeed
420 19:43:37.489923 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 19:43:37.537570 Check phy result
422 19:43:37.537979 INFO : End of initialization
423 19:43:37.559330 INFO : End of 2D read delay Voltage center optimization
424 19:43:37.579579 INFO : End of 2D read delay Voltage center optimization
425 19:43:37.631589 INFO : End of 2D write delay Voltage center optimization
426 19:43:37.680881 INFO : End of 2D write delay Voltage center optimization
427 19:43:37.686634 INFO : Training has run successfully!
428 19:43:37.686975
429 19:43:37.687232 channel==0
430 19:43:37.692034 RxClkDly_Margin_A0==88 ps 9
431 19:43:37.692359 TxDqDly_Margin_A0==98 ps 10
432 19:43:37.697623 RxClkDly_Margin_A1==88 ps 9
433 19:43:37.697944 TxDqDly_Margin_A1==98 ps 10
434 19:43:37.698180 TrainedVREFDQ_A0==74
435 19:43:37.703260 TrainedVREFDQ_A1==74
436 19:43:37.703584 VrefDac_Margin_A0==25
437 19:43:37.703812 DeviceVref_Margin_A0==40
438 19:43:37.708864 VrefDac_Margin_A1==24
439 19:43:37.709190 DeviceVref_Margin_A1==40
440 19:43:37.709447
441 19:43:37.709671
442 19:43:37.714494 channel==1
443 19:43:37.714809 RxClkDly_Margin_A0==98 ps 10
444 19:43:37.715069 TxDqDly_Margin_A0==88 ps 9
445 19:43:37.720177 RxClkDly_Margin_A1==88 ps 9
446 19:43:37.720503 TxDqDly_Margin_A1==88 ps 9
447 19:43:37.725709 TrainedVREFDQ_A0==76
448 19:43:37.726035 TrainedVREFDQ_A1==77
449 19:43:37.726299 VrefDac_Margin_A0==22
450 19:43:37.731285 DeviceVref_Margin_A0==38
451 19:43:37.731608 VrefDac_Margin_A1==24
452 19:43:37.736920 DeviceVref_Margin_A1==37
453 19:43:37.737238
454 19:43:37.737472 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 19:43:37.737696
456 19:43:37.770370 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 19:43:37.770788 2D training succeed
458 19:43:37.775971 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 19:43:37.781689 auto size-- 65535DDR cs0 size: 2048MB
460 19:43:37.782185 DDR cs1 size: 2048MB
461 19:43:37.787247 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 19:43:37.787733 cs0 DataBus test pass
463 19:43:37.792867 cs1 DataBus test pass
464 19:43:37.793341 cs0 AddrBus test pass
465 19:43:37.793748 cs1 AddrBus test pass
466 19:43:37.794147
467 19:43:37.798462 100bdlr_step_size ps== 420
468 19:43:37.798958 result report
469 19:43:37.804072 boot times 0Enable ddr reg access
470 19:43:37.809308 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 19:43:37.822785 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 19:43:38.396482 0.0;M3 CHK:0;cm4_sp_mode 0
473 19:43:38.397074 MVN_1=0x00000000
474 19:43:38.401933 MVN_2=0x00000000
475 19:43:38.407740 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 19:43:38.408281 OPS=0x10
477 19:43:38.408698 ring efuse init
478 19:43:38.409097 chipver efuse init
479 19:43:38.413394 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 19:43:38.419066 [0.018961 Inits done]
481 19:43:38.419620 secure task start!
482 19:43:38.420078 high task start!
483 19:43:38.423637 low task start!
484 19:43:38.424157 run into bl31
485 19:43:38.430230 NOTICE: BL31: v1.3(release):4fc40b1
486 19:43:38.438006 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 19:43:38.438498 NOTICE: BL31: G12A normal boot!
488 19:43:38.463409 NOTICE: BL31: BL33 decompress pass
489 19:43:38.469060 ERROR: Error initializing runtime service opteed_fast
490 19:43:39.701870
491 19:43:39.702323
492 19:43:39.710115 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 19:43:39.710441
494 19:43:39.710672 Model: Libre Computer AML-A311D-CC Alta
495 19:43:39.917588 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 19:43:39.941904 DRAM: 2 GiB (effective 3.8 GiB)
497 19:43:40.084976 Core: 408 devices, 31 uclasses, devicetree: separate
498 19:43:40.090842 WDT: Not starting watchdog@f0d0
499 19:43:40.123107 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 19:43:40.135628 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 19:43:40.140535 ** Bad device specification mmc 0 **
502 19:43:40.150877 Card did not respond to voltage select! : -110
503 19:43:40.158505 ** Bad device specification mmc 0 **
504 19:43:40.158820 Couldn't find partition mmc 0
505 19:43:40.166850 Card did not respond to voltage select! : -110
506 19:43:40.172369 ** Bad device specification mmc 0 **
507 19:43:40.172807 Couldn't find partition mmc 0
508 19:43:40.177422 Error: could not access storage.
509 19:43:41.441042 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 19:43:41.441481 bl2_stage_init 0x01
511 19:43:41.441710 bl2_stage_init 0x81
512 19:43:41.446464 hw id: 0x0000 - pwm id 0x01
513 19:43:41.446887 bl2_stage_init 0xc1
514 19:43:41.447230 bl2_stage_init 0x02
515 19:43:41.447563
516 19:43:41.452086 L0:00000000
517 19:43:41.452379 L1:20000703
518 19:43:41.452599 L2:00008067
519 19:43:41.452807 L3:14000000
520 19:43:41.454941 B2:00402000
521 19:43:41.455339 B1:e0f83180
522 19:43:41.455672
523 19:43:41.456024 TE: 58159
524 19:43:41.456367
525 19:43:41.466032 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 19:43:41.466445
527 19:43:41.466702 Board ID = 1
528 19:43:41.466919 Set A53 clk to 24M
529 19:43:41.467129 Set A73 clk to 24M
530 19:43:41.471670 Set clk81 to 24M
531 19:43:41.472091 A53 clk: 1200 MHz
532 19:43:41.472436 A73 clk: 1200 MHz
533 19:43:41.477260 CLK81: 166.6M
534 19:43:41.477678 smccc: 00012ab4
535 19:43:41.482942 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 19:43:41.483359 board id: 1
537 19:43:41.488442 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 19:43:41.502237 fw parse done
539 19:43:41.508243 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 19:43:41.550818 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 19:43:41.561813 PIEI prepare done
542 19:43:41.562403 fastboot data load
543 19:43:41.562658 fastboot data verify
544 19:43:41.567470 verify result: 266
545 19:43:41.573160 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 19:43:41.573598 LPDDR4 probe
547 19:43:41.573824 ddr clk to 1584MHz
548 19:43:41.581038 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 19:43:41.618282
550 19:43:41.618707 dmc_version 0001
551 19:43:41.624912 Check phy result
552 19:43:41.630757 INFO : End of CA training
553 19:43:41.631076 INFO : End of initialization
554 19:43:41.636353 INFO : Training has run successfully!
555 19:43:41.636669 Check phy result
556 19:43:41.642057 INFO : End of initialization
557 19:43:41.642385 INFO : End of read enable training
558 19:43:41.647567 INFO : End of fine write leveling
559 19:43:41.653260 INFO : End of Write leveling coarse delay
560 19:43:41.653617 INFO : Training has run successfully!
561 19:43:41.653842 Check phy result
562 19:43:41.658769 INFO : End of initialization
563 19:43:41.659129 INFO : End of read dq deskew training
564 19:43:41.664404 INFO : End of MPR read delay center optimization
565 19:43:41.670067 INFO : End of write delay center optimization
566 19:43:41.675570 INFO : End of read delay center optimization
567 19:43:41.675906 INFO : End of max read latency training
568 19:43:41.681163 INFO : Training has run successfully!
569 19:43:41.681477 1D training succeed
570 19:43:41.692991 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 19:43:41.738142 Check phy result
572 19:43:41.738766 INFO : End of initialization
573 19:43:41.760702 INFO : End of 2D read delay Voltage center optimization
574 19:43:41.780949 INFO : End of 2D read delay Voltage center optimization
575 19:43:41.832964 INFO : End of 2D write delay Voltage center optimization
576 19:43:41.882289 INFO : End of 2D write delay Voltage center optimization
577 19:43:41.887867 INFO : Training has run successfully!
578 19:43:41.888390
579 19:43:41.888839 channel==0
580 19:43:41.893484 RxClkDly_Margin_A0==88 ps 9
581 19:43:41.893948 TxDqDly_Margin_A0==98 ps 10
582 19:43:41.899158 RxClkDly_Margin_A1==88 ps 9
583 19:43:41.899624 TxDqDly_Margin_A1==98 ps 10
584 19:43:41.900079 TrainedVREFDQ_A0==74
585 19:43:41.904669 TrainedVREFDQ_A1==74
586 19:43:41.905139 VrefDac_Margin_A0==24
587 19:43:41.905557 DeviceVref_Margin_A0==40
588 19:43:41.910309 VrefDac_Margin_A1==25
589 19:43:41.910780 DeviceVref_Margin_A1==40
590 19:43:41.911198
591 19:43:41.911614
592 19:43:41.915851 channel==1
593 19:43:41.916348 RxClkDly_Margin_A0==88 ps 9
594 19:43:41.916769 TxDqDly_Margin_A0==98 ps 10
595 19:43:41.921494 RxClkDly_Margin_A1==98 ps 10
596 19:43:41.921970 TxDqDly_Margin_A1==88 ps 9
597 19:43:41.927185 TrainedVREFDQ_A0==77
598 19:43:41.927652 TrainedVREFDQ_A1==77
599 19:43:41.928104 VrefDac_Margin_A0==22
600 19:43:41.932672 DeviceVref_Margin_A0==37
601 19:43:41.933133 VrefDac_Margin_A1==22
602 19:43:41.938261 DeviceVref_Margin_A1==37
603 19:43:41.938742
604 19:43:41.939160 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 19:43:41.939574
606 19:43:41.971818 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 19:43:41.972363 2D training succeed
608 19:43:41.977469 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 19:43:41.983227 auto size-- 65535DDR cs0 size: 2048MB
610 19:43:41.983697 DDR cs1 size: 2048MB
611 19:43:41.988691 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 19:43:41.989156 cs0 DataBus test pass
613 19:43:41.994288 cs1 DataBus test pass
614 19:43:41.994757 cs0 AddrBus test pass
615 19:43:41.995177 cs1 AddrBus test pass
616 19:43:41.995584
617 19:43:41.999845 100bdlr_step_size ps== 420
618 19:43:42.000348 result report
619 19:43:42.005475 boot times 0Enable ddr reg access
620 19:43:42.010844 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 19:43:42.024285 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 19:43:42.598022 0.0;M3 CHK:0;cm4_sp_mode 0
623 19:43:42.598656 MVN_1=0x00000000
624 19:43:42.603497 MVN_2=0x00000000
625 19:43:42.609367 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 19:43:42.609928 OPS=0x10
627 19:43:42.610391 ring efuse init
628 19:43:42.610838 chipver efuse init
629 19:43:42.614752 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 19:43:42.620312 [0.018960 Inits done]
631 19:43:42.620791 secure task start!
632 19:43:42.621236 high task start!
633 19:43:42.624875 low task start!
634 19:43:42.625351 run into bl31
635 19:43:42.631542 NOTICE: BL31: v1.3(release):4fc40b1
636 19:43:42.639348 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 19:43:42.639836 NOTICE: BL31: G12A normal boot!
638 19:43:42.664767 NOTICE: BL31: BL33 decompress pass
639 19:43:42.670415 ERROR: Error initializing runtime service opteed_fast
640 19:43:43.903557
641 19:43:43.904290
642 19:43:43.911860 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 19:43:43.912420
644 19:43:43.912896 Model: Libre Computer AML-A311D-CC Alta
645 19:43:44.120198 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 19:43:44.143711 DRAM: 2 GiB (effective 3.8 GiB)
647 19:43:44.286657 Core: 408 devices, 31 uclasses, devicetree: separate
648 19:43:44.292417 WDT: Not starting watchdog@f0d0
649 19:43:44.324644 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 19:43:44.337166 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 19:43:44.342135 ** Bad device specification mmc 0 **
652 19:43:44.352483 Card did not respond to voltage select! : -110
653 19:43:44.360135 ** Bad device specification mmc 0 **
654 19:43:44.360633 Couldn't find partition mmc 0
655 19:43:44.368570 Card did not respond to voltage select! : -110
656 19:43:44.373975 ** Bad device specification mmc 0 **
657 19:43:44.374470 Couldn't find partition mmc 0
658 19:43:44.379068 Error: could not access storage.
659 19:43:44.721526 Net: eth0: ethernet@ff3f0000
660 19:43:44.722150 starting USB...
661 19:43:44.973322 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 19:43:44.973864 Starting the controller
663 19:43:44.980386 USB XHCI 1.10
664 19:43:46.691206 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 19:43:46.691621 bl2_stage_init 0x01
666 19:43:46.692147 bl2_stage_init 0x81
667 19:43:46.696832 hw id: 0x0000 - pwm id 0x01
668 19:43:46.697333 bl2_stage_init 0xc1
669 19:43:46.697800 bl2_stage_init 0x02
670 19:43:46.698336
671 19:43:46.702290 L0:00000000
672 19:43:46.702786 L1:20000703
673 19:43:46.703247 L2:00008067
674 19:43:46.703695 L3:14000000
675 19:43:46.705331 B2:00402000
676 19:43:46.705833 B1:e0f83180
677 19:43:46.706296
678 19:43:46.706752 TE: 58159
679 19:43:46.707205
680 19:43:46.716464 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 19:43:46.716993
682 19:43:46.717458 Board ID = 1
683 19:43:46.717908 Set A53 clk to 24M
684 19:43:46.718357 Set A73 clk to 24M
685 19:43:46.722167 Set clk81 to 24M
686 19:43:46.722653 A53 clk: 1200 MHz
687 19:43:46.723108 A73 clk: 1200 MHz
688 19:43:46.727716 CLK81: 166.6M
689 19:43:46.728254 smccc: 00012ab5
690 19:43:46.733269 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 19:43:46.733767 board id: 1
692 19:43:46.742082 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 19:43:46.752348 fw parse done
694 19:43:46.758550 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 19:43:46.801031 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 19:43:46.811873 PIEI prepare done
697 19:43:46.812505 fastboot data load
698 19:43:46.812991 fastboot data verify
699 19:43:46.817533 verify result: 266
700 19:43:46.823092 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 19:43:46.823608 LPDDR4 probe
702 19:43:46.824103 ddr clk to 1584MHz
703 19:43:46.831102 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 19:43:46.868338
705 19:43:46.868873 dmc_version 0001
706 19:43:46.875076 Check phy result
707 19:43:46.881272 INFO : End of CA training
708 19:43:46.881967 INFO : End of initialization
709 19:43:46.886707 INFO : Training has run successfully!
710 19:43:46.887374 Check phy result
711 19:43:46.893750 INFO : End of initialization
712 19:43:46.894453 INFO : End of read enable training
713 19:43:46.897833 INFO : End of fine write leveling
714 19:43:46.903408 INFO : End of Write leveling coarse delay
715 19:43:46.903815 INFO : Training has run successfully!
716 19:43:46.904074 Check phy result
717 19:43:46.908930 INFO : End of initialization
718 19:43:46.909297 INFO : End of read dq deskew training
719 19:43:46.914766 INFO : End of MPR read delay center optimization
720 19:43:46.920174 INFO : End of write delay center optimization
721 19:43:46.925885 INFO : End of read delay center optimization
722 19:43:46.926292 INFO : End of max read latency training
723 19:43:46.931347 INFO : Training has run successfully!
724 19:43:46.931770 1D training succeed
725 19:43:46.940465 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 19:43:46.988338 Check phy result
727 19:43:46.988807 INFO : End of initialization
728 19:43:47.009990 INFO : End of 2D read delay Voltage center optimization
729 19:43:47.030134 INFO : End of 2D read delay Voltage center optimization
730 19:43:47.082140 INFO : End of 2D write delay Voltage center optimization
731 19:43:47.131523 INFO : End of 2D write delay Voltage center optimization
732 19:43:47.137078 INFO : Training has run successfully!
733 19:43:47.137536
734 19:43:47.137799 channel==0
735 19:43:47.142813 RxClkDly_Margin_A0==88 ps 9
736 19:43:47.143470 TxDqDly_Margin_A0==98 ps 10
737 19:43:47.148284 RxClkDly_Margin_A1==88 ps 9
738 19:43:47.148916 TxDqDly_Margin_A1==98 ps 10
739 19:43:47.149253 TrainedVREFDQ_A0==74
740 19:43:47.153888 TrainedVREFDQ_A1==74
741 19:43:47.154505 VrefDac_Margin_A0==25
742 19:43:47.154877 DeviceVref_Margin_A0==40
743 19:43:47.159455 VrefDac_Margin_A1==25
744 19:43:47.159880 DeviceVref_Margin_A1==40
745 19:43:47.160184
746 19:43:47.160426
747 19:43:47.165104 channel==1
748 19:43:47.165743 RxClkDly_Margin_A0==98 ps 10
749 19:43:47.166159 TxDqDly_Margin_A0==98 ps 10
750 19:43:47.170605 RxClkDly_Margin_A1==98 ps 10
751 19:43:47.171137 TxDqDly_Margin_A1==88 ps 9
752 19:43:47.176186 TrainedVREFDQ_A0==77
753 19:43:47.176786 TrainedVREFDQ_A1==77
754 19:43:47.177088 VrefDac_Margin_A0==22
755 19:43:47.181819 DeviceVref_Margin_A0==37
756 19:43:47.182205 VrefDac_Margin_A1==22
757 19:43:47.187441 DeviceVref_Margin_A1==37
758 19:43:47.188019
759 19:43:47.188436 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 19:43:47.192966
761 19:43:47.220954 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 19:43:47.221368 2D training succeed
763 19:43:47.226552 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 19:43:47.232142 auto size-- 65535DDR cs0 size: 2048MB
765 19:43:47.232605 DDR cs1 size: 2048MB
766 19:43:47.237764 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 19:43:47.238092 cs0 DataBus test pass
768 19:43:47.243359 cs1 DataBus test pass
769 19:43:47.243689 cs0 AddrBus test pass
770 19:43:47.243941 cs1 AddrBus test pass
771 19:43:47.244213
772 19:43:47.248955 100bdlr_step_size ps== 420
773 19:43:47.249423 result report
774 19:43:47.254591 boot times 0Enable ddr reg access
775 19:43:47.260012 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 19:43:47.273499 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 19:43:47.847258 0.0;M3 CHK:0;cm4_sp_mode 0
778 19:43:47.847762 MVN_1=0x00000000
779 19:43:47.852788 MVN_2=0x00000000
780 19:43:47.858508 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 19:43:47.858907 OPS=0x10
782 19:43:47.859150 ring efuse init
783 19:43:47.859399 chipver efuse init
784 19:43:47.864244 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 19:43:47.869690 [0.018961 Inits done]
786 19:43:47.870051 secure task start!
787 19:43:47.870297 high task start!
788 19:43:47.874251 low task start!
789 19:43:47.874619 run into bl31
790 19:43:47.880885 NOTICE: BL31: v1.3(release):4fc40b1
791 19:43:47.888698 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 19:43:47.889136 NOTICE: BL31: G12A normal boot!
793 19:43:47.914082 NOTICE: BL31: BL33 decompress pass
794 19:43:47.919726 ERROR: Error initializing runtime service opteed_fast
795 19:43:49.152572
796 19:43:49.153209
797 19:43:49.161044 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 19:43:49.161553
799 19:43:49.161982 Model: Libre Computer AML-A311D-CC Alta
800 19:43:49.369345 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 19:43:49.392761 DRAM: 2 GiB (effective 3.8 GiB)
802 19:43:49.535763 Core: 408 devices, 31 uclasses, devicetree: separate
803 19:43:49.541621 WDT: Not starting watchdog@f0d0
804 19:43:49.573919 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 19:43:49.586339 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 19:43:49.591306 ** Bad device specification mmc 0 **
807 19:43:49.601660 Card did not respond to voltage select! : -110
808 19:43:49.609299 ** Bad device specification mmc 0 **
809 19:43:49.609656 Couldn't find partition mmc 0
810 19:43:49.617630 Card did not respond to voltage select! : -110
811 19:43:49.623145 ** Bad device specification mmc 0 **
812 19:43:49.623499 Couldn't find partition mmc 0
813 19:43:49.628230 Error: could not access storage.
814 19:43:49.970743 Net: eth0: ethernet@ff3f0000
815 19:43:49.971433 starting USB...
816 19:43:50.222643 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 19:43:50.223324 Starting the controller
818 19:43:50.229520 USB XHCI 1.10
819 19:43:52.391249 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 19:43:52.391690 bl2_stage_init 0x01
821 19:43:52.391917 bl2_stage_init 0x81
822 19:43:52.396761 hw id: 0x0000 - pwm id 0x01
823 19:43:52.397091 bl2_stage_init 0xc1
824 19:43:52.397309 bl2_stage_init 0x02
825 19:43:52.397517
826 19:43:52.402422 L0:00000000
827 19:43:52.402931 L1:20000703
828 19:43:52.403199 L2:00008067
829 19:43:52.403415 L3:14000000
830 19:43:52.407922 B2:00402000
831 19:43:52.408420 B1:e0f83180
832 19:43:52.408788
833 19:43:52.409114 TE: 58124
834 19:43:52.409441
835 19:43:52.413860 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 19:43:52.414247
837 19:43:52.414492 Board ID = 1
838 19:43:52.419151 Set A53 clk to 24M
839 19:43:52.419518 Set A73 clk to 24M
840 19:43:52.419759 Set clk81 to 24M
841 19:43:52.424755 A53 clk: 1200 MHz
842 19:43:52.425120 A73 clk: 1200 MHz
843 19:43:52.425357 CLK81: 166.6M
844 19:43:52.425582 smccc: 00012a92
845 19:43:52.430311 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 19:43:52.435911 board id: 1
847 19:43:52.442066 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 19:43:52.452430 fw parse done
849 19:43:52.458353 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 19:43:52.500997 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 19:43:52.511847 PIEI prepare done
852 19:43:52.512226 fastboot data load
853 19:43:52.512494 fastboot data verify
854 19:43:52.517612 verify result: 266
855 19:43:52.523068 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 19:43:52.523407 LPDDR4 probe
857 19:43:52.523642 ddr clk to 1584MHz
858 19:43:52.531172 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 19:43:52.568542
860 19:43:52.569216 dmc_version 0001
861 19:43:52.575124 Check phy result
862 19:43:52.580966 INFO : End of CA training
863 19:43:52.581481 INFO : End of initialization
864 19:43:52.586650 INFO : Training has run successfully!
865 19:43:52.587152 Check phy result
866 19:43:52.592159 INFO : End of initialization
867 19:43:52.592711 INFO : End of read enable training
868 19:43:52.595491 INFO : End of fine write leveling
869 19:43:52.600952 INFO : End of Write leveling coarse delay
870 19:43:52.606634 INFO : Training has run successfully!
871 19:43:52.607155 Check phy result
872 19:43:52.607626 INFO : End of initialization
873 19:43:52.612153 INFO : End of read dq deskew training
874 19:43:52.617770 INFO : End of MPR read delay center optimization
875 19:43:52.618287 INFO : End of write delay center optimization
876 19:43:52.623432 INFO : End of read delay center optimization
877 19:43:52.628986 INFO : End of max read latency training
878 19:43:52.629497 INFO : Training has run successfully!
879 19:43:52.634683 1D training succeed
880 19:43:52.640600 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 19:43:52.688094 Check phy result
882 19:43:52.688641 INFO : End of initialization
883 19:43:52.710723 INFO : End of 2D read delay Voltage center optimization
884 19:43:52.730003 INFO : End of 2D read delay Voltage center optimization
885 19:43:52.782089 INFO : End of 2D write delay Voltage center optimization
886 19:43:52.831481 INFO : End of 2D write delay Voltage center optimization
887 19:43:52.837029 INFO : Training has run successfully!
888 19:43:52.837601
889 19:43:52.838081 channel==0
890 19:43:52.842669 RxClkDly_Margin_A0==88 ps 9
891 19:43:52.843172 TxDqDly_Margin_A0==98 ps 10
892 19:43:52.848166 RxClkDly_Margin_A1==88 ps 9
893 19:43:52.848664 TxDqDly_Margin_A1==98 ps 10
894 19:43:52.849154 TrainedVREFDQ_A0==74
895 19:43:52.853871 TrainedVREFDQ_A1==74
896 19:43:52.854418 VrefDac_Margin_A0==24
897 19:43:52.854880 DeviceVref_Margin_A0==40
898 19:43:52.859397 VrefDac_Margin_A1==24
899 19:43:52.860067 DeviceVref_Margin_A1==40
900 19:43:52.860580
901 19:43:52.861022
902 19:43:52.865016 channel==1
903 19:43:52.865617 RxClkDly_Margin_A0==88 ps 9
904 19:43:52.866077 TxDqDly_Margin_A0==88 ps 9
905 19:43:52.870709 RxClkDly_Margin_A1==88 ps 9
906 19:43:52.871250 TxDqDly_Margin_A1==88 ps 9
907 19:43:52.876211 TrainedVREFDQ_A0==77
908 19:43:52.876751 TrainedVREFDQ_A1==77
909 19:43:52.877218 VrefDac_Margin_A0==23
910 19:43:52.881779 DeviceVref_Margin_A0==37
911 19:43:52.882314 VrefDac_Margin_A1==24
912 19:43:52.887360 DeviceVref_Margin_A1==37
913 19:43:52.887890
914 19:43:52.888406 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 19:43:52.888849
916 19:43:52.920925 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
917 19:43:52.921549 2D training succeed
918 19:43:52.926605 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 19:43:52.932129 auto size-- 65535DDR cs0 size: 2048MB
920 19:43:52.932676 DDR cs1 size: 2048MB
921 19:43:52.937711 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 19:43:52.938248 cs0 DataBus test pass
923 19:43:52.943313 cs1 DataBus test pass
924 19:43:52.943832 cs0 AddrBus test pass
925 19:43:52.944338 cs1 AddrBus test pass
926 19:43:52.944774
927 19:43:52.948892 100bdlr_step_size ps== 420
928 19:43:52.949395 result report
929 19:43:52.954594 boot times 0Enable ddr reg access
930 19:43:52.959695 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 19:43:52.973223 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 19:43:53.546936 0.0;M3 CHK:0;cm4_sp_mode 0
933 19:43:53.547635 MVN_1=0x00000000
934 19:43:53.552302 MVN_2=0x00000000
935 19:43:53.558088 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 19:43:53.558616 OPS=0x10
937 19:43:53.559088 ring efuse init
938 19:43:53.559554 chipver efuse init
939 19:43:53.563700 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 19:43:53.569272 [0.018961 Inits done]
941 19:43:53.569809 secure task start!
942 19:43:53.570271 high task start!
943 19:43:53.573850 low task start!
944 19:43:53.574358 run into bl31
945 19:43:53.580591 NOTICE: BL31: v1.3(release):4fc40b1
946 19:43:53.588418 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 19:43:53.589018 NOTICE: BL31: G12A normal boot!
948 19:43:53.613823 NOTICE: BL31: BL33 decompress pass
949 19:43:53.619452 ERROR: Error initializing runtime service opteed_fast
950 19:43:54.852445
951 19:43:54.853152
952 19:43:54.860891 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 19:43:54.861424
954 19:43:54.861907 Model: Libre Computer AML-A311D-CC Alta
955 19:43:55.069284 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 19:43:55.092604 DRAM: 2 GiB (effective 3.8 GiB)
957 19:43:55.235666 Core: 408 devices, 31 uclasses, devicetree: separate
958 19:43:55.241420 WDT: Not starting watchdog@f0d0
959 19:43:55.273763 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 19:43:55.286190 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 19:43:55.291177 ** Bad device specification mmc 0 **
962 19:43:55.301537 Card did not respond to voltage select! : -110
963 19:43:55.309149 ** Bad device specification mmc 0 **
964 19:43:55.309656 Couldn't find partition mmc 0
965 19:43:55.317497 Card did not respond to voltage select! : -110
966 19:43:55.323018 ** Bad device specification mmc 0 **
967 19:43:55.323532 Couldn't find partition mmc 0
968 19:43:55.328089 Error: could not access storage.
969 19:43:55.670578 Net: eth0: ethernet@ff3f0000
970 19:43:55.671017 starting USB...
971 19:43:55.922339 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 19:43:55.922765 Starting the controller
973 19:43:55.928374 USB XHCI 1.10
974 19:43:57.790782 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 19:43:57.791368 bl2_stage_init 0x01
976 19:43:57.791616 bl2_stage_init 0x81
977 19:43:57.796298 hw id: 0x0000 - pwm id 0x01
978 19:43:57.796589 bl2_stage_init 0xc1
979 19:43:57.796801 bl2_stage_init 0x02
980 19:43:57.797004
981 19:43:57.801879 L0:00000000
982 19:43:57.802163 L1:20000703
983 19:43:57.802384 L2:00008067
984 19:43:57.802587 L3:14000000
985 19:43:57.807498 B2:00402000
986 19:43:57.807895 B1:e0f83180
987 19:43:57.808248
988 19:43:57.808561 TE: 58159
989 19:43:57.808865
990 19:43:57.813178 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 19:43:57.813457
992 19:43:57.813666 Board ID = 1
993 19:43:57.818673 Set A53 clk to 24M
994 19:43:57.818947 Set A73 clk to 24M
995 19:43:57.819155 Set clk81 to 24M
996 19:43:57.824280 A53 clk: 1200 MHz
997 19:43:57.824556 A73 clk: 1200 MHz
998 19:43:57.824763 CLK81: 166.6M
999 19:43:57.824961 smccc: 00012ab5
1000 19:43:57.829885 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 19:43:57.835484 board id: 1
1002 19:43:57.841363 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 19:43:57.852168 fw parse done
1004 19:43:57.857999 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 19:43:57.900651 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 19:43:57.911550 PIEI prepare done
1007 19:43:57.912170 fastboot data load
1008 19:43:57.912609 fastboot data verify
1009 19:43:57.917286 verify result: 266
1010 19:43:57.922765 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 19:43:57.923315 LPDDR4 probe
1012 19:43:57.923738 ddr clk to 1584MHz
1013 19:43:57.929816 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 19:43:57.968146
1015 19:43:57.968771 dmc_version 0001
1016 19:43:57.974773 Check phy result
1017 19:43:57.980637 INFO : End of CA training
1018 19:43:57.981225 INFO : End of initialization
1019 19:43:57.986319 INFO : Training has run successfully!
1020 19:43:57.986852 Check phy result
1021 19:43:57.992100 INFO : End of initialization
1022 19:43:57.992665 INFO : End of read enable training
1023 19:43:57.995167 INFO : End of fine write leveling
1024 19:43:58.000688 INFO : End of Write leveling coarse delay
1025 19:43:58.006478 INFO : Training has run successfully!
1026 19:43:58.007059 Check phy result
1027 19:43:58.007508 INFO : End of initialization
1028 19:43:58.012054 INFO : End of read dq deskew training
1029 19:43:58.017551 INFO : End of MPR read delay center optimization
1030 19:43:58.017932 INFO : End of write delay center optimization
1031 19:43:58.023046 INFO : End of read delay center optimization
1032 19:43:58.028772 INFO : End of max read latency training
1033 19:43:58.029155 INFO : Training has run successfully!
1034 19:43:58.034283 1D training succeed
1035 19:43:58.040507 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 19:43:58.088187 Check phy result
1037 19:43:58.088629 INFO : End of initialization
1038 19:43:58.109616 INFO : End of 2D read delay Voltage center optimization
1039 19:43:58.129871 INFO : End of 2D read delay Voltage center optimization
1040 19:43:58.181926 INFO : End of 2D write delay Voltage center optimization
1041 19:43:58.231503 INFO : End of 2D write delay Voltage center optimization
1042 19:43:58.236971 INFO : Training has run successfully!
1043 19:43:58.237330
1044 19:43:58.237567 channel==0
1045 19:43:58.242507 RxClkDly_Margin_A0==88 ps 9
1046 19:43:58.242870 TxDqDly_Margin_A0==98 ps 10
1047 19:43:58.245792 RxClkDly_Margin_A1==88 ps 9
1048 19:43:58.246142 TxDqDly_Margin_A1==98 ps 10
1049 19:43:58.251456 TrainedVREFDQ_A0==74
1050 19:43:58.251820 TrainedVREFDQ_A1==74
1051 19:43:58.252109 VrefDac_Margin_A0==25
1052 19:43:58.256955 DeviceVref_Margin_A0==40
1053 19:43:58.257315 VrefDac_Margin_A1==23
1054 19:43:58.262661 DeviceVref_Margin_A1==40
1055 19:43:58.263164
1056 19:43:58.263579
1057 19:43:58.263864 channel==1
1058 19:43:58.264128 RxClkDly_Margin_A0==98 ps 10
1059 19:43:58.265986 TxDqDly_Margin_A0==98 ps 10
1060 19:43:58.271614 RxClkDly_Margin_A1==88 ps 9
1061 19:43:58.271965 TxDqDly_Margin_A1==88 ps 9
1062 19:43:58.272255 TrainedVREFDQ_A0==77
1063 19:43:58.277207 TrainedVREFDQ_A1==77
1064 19:43:58.277571 VrefDac_Margin_A0==22
1065 19:43:58.282757 DeviceVref_Margin_A0==37
1066 19:43:58.283263 VrefDac_Margin_A1==24
1067 19:43:58.283682 DeviceVref_Margin_A1==37
1068 19:43:58.283999
1069 19:43:58.288390 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 19:43:58.288895
1071 19:43:58.321935 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
1072 19:43:58.322525 2D training succeed
1073 19:43:58.327495 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 19:43:58.333061 auto size-- 65535DDR cs0 size: 2048MB
1075 19:43:58.333442 DDR cs1 size: 2048MB
1076 19:43:58.338723 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 19:43:58.339095 cs0 DataBus test pass
1078 19:43:58.339557 cs1 DataBus test pass
1079 19:43:58.344289 cs0 AddrBus test pass
1080 19:43:58.344810 cs1 AddrBus test pass
1081 19:43:58.345206
1082 19:43:58.349882 100bdlr_step_size ps== 420
1083 19:43:58.350261 result report
1084 19:43:58.350513 boot times 0Enable ddr reg access
1085 19:43:58.359671 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 19:43:58.373239 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 19:43:58.946858 0.0;M3 CHK:0;cm4_sp_mode 0
1088 19:43:58.947288 MVN_1=0x00000000
1089 19:43:58.952356 MVN_2=0x00000000
1090 19:43:58.958072 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 19:43:58.958393 OPS=0x10
1092 19:43:58.958607 ring efuse init
1093 19:43:58.958828 chipver efuse init
1094 19:43:58.963664 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 19:43:58.969375 [0.018961 Inits done]
1096 19:43:58.969703 secure task start!
1097 19:43:58.969911 high task start!
1098 19:43:58.973805 low task start!
1099 19:43:58.974104 run into bl31
1100 19:43:58.980463 NOTICE: BL31: v1.3(release):4fc40b1
1101 19:43:58.988269 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 19:43:58.988580 NOTICE: BL31: G12A normal boot!
1103 19:43:59.013622 NOTICE: BL31: BL33 decompress pass
1104 19:43:59.019282 ERROR: Error initializing runtime service opteed_fast
1105 19:44:00.252227
1106 19:44:00.252865
1107 19:44:00.260722 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 19:44:00.261302
1109 19:44:00.261753 Model: Libre Computer AML-A311D-CC Alta
1110 19:44:00.469073 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 19:44:00.492731 DRAM: 2 GiB (effective 3.8 GiB)
1112 19:44:00.635432 Core: 408 devices, 31 uclasses, devicetree: separate
1113 19:44:00.641264 WDT: Not starting watchdog@f0d0
1114 19:44:00.673763 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 19:44:00.685987 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 19:44:00.690938 ** Bad device specification mmc 0 **
1117 19:44:00.701302 Card did not respond to voltage select! : -110
1118 19:44:00.708934 ** Bad device specification mmc 0 **
1119 19:44:00.709477 Couldn't find partition mmc 0
1120 19:44:00.717285 Card did not respond to voltage select! : -110
1121 19:44:00.722789 ** Bad device specification mmc 0 **
1122 19:44:00.723302 Couldn't find partition mmc 0
1123 19:44:00.728188 Error: could not access storage.
1124 19:44:01.070413 Net: eth0: ethernet@ff3f0000
1125 19:44:01.071107 starting USB...
1126 19:44:01.322268 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 19:44:01.323250 Starting the controller
1128 19:44:01.329582 USB XHCI 1.10
1129 19:44:02.885265 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 19:44:02.893700 scanning usb for storage devices... 0 Storage Device(s) found
1132 19:44:02.945037 Hit any key to stop autoboot: 1
1133 19:44:02.946024 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 19:44:02.946663 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 19:44:02.947180 Setting prompt string to ['=>']
1136 19:44:02.947720 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 19:44:02.961105 0
1138 19:44:02.962066 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 19:44:02.962607 Sending with 10 millisecond of delay
1141 19:44:04.098213 => setenv autoload no
1142 19:44:04.109105 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 19:44:04.114695 setenv autoload no
1144 19:44:04.115647 Sending with 10 millisecond of delay
1146 19:44:05.914963 => setenv initrd_high 0xffffffff
1147 19:44:05.925496 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 19:44:05.926043 setenv initrd_high 0xffffffff
1149 19:44:05.926513 Sending with 10 millisecond of delay
1151 19:44:07.542479 => setenv fdt_high 0xffffffff
1152 19:44:07.553253 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 19:44:07.553810 setenv fdt_high 0xffffffff
1154 19:44:07.554282 Sending with 10 millisecond of delay
1156 19:44:07.845823 => dhcp
1157 19:44:07.856543 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 19:44:07.857144 dhcp
1159 19:44:07.857408 Speed: 1000, full duplex
1160 19:44:07.857628 BOOTP broadcast 1
1161 19:44:07.864497 DHCP client bound to address 192.168.6.27 (8 ms)
1162 19:44:07.864995 Sending with 10 millisecond of delay
1164 19:44:09.540307 => setenv serverip 192.168.6.2
1165 19:44:09.554021 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 19:44:09.554612 setenv serverip 192.168.6.2
1167 19:44:09.555082 Sending with 10 millisecond of delay
1169 19:44:13.276327 => tftpboot 0x01080000 954173/tftp-deploy-00jfgn93/kernel/uImage
1170 19:44:13.287066 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1171 19:44:13.287602 tftpboot 0x01080000 954173/tftp-deploy-00jfgn93/kernel/uImage
1172 19:44:13.287864 Speed: 1000, full duplex
1173 19:44:13.288354 Using ethernet@ff3f0000 device
1174 19:44:13.289554 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 19:44:13.295145 Filename '954173/tftp-deploy-00jfgn93/kernel/uImage'.
1176 19:44:13.298937 Load address: 0x1080000
1177 19:44:13.632898 Loading: *##### UDP wrong checksum 000000ff 0000c24a
1178 19:44:13.682858 # UDP wrong checksum 000000ff 00004e3d
1179 19:44:16.134866 ############################################ 43.6 MiB
1180 19:44:16.135297 15.4 MiB/s
1181 19:44:16.135550 done
1182 19:44:16.139308 Bytes transferred = 45713984 (2b98a40 hex)
1183 19:44:16.140216 Sending with 10 millisecond of delay
1185 19:44:20.829459 => tftpboot 0x08000000 954173/tftp-deploy-00jfgn93/ramdisk/ramdisk.cpio.gz.uboot
1186 19:44:20.840276 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1187 19:44:20.841129 tftpboot 0x08000000 954173/tftp-deploy-00jfgn93/ramdisk/ramdisk.cpio.gz.uboot
1188 19:44:20.841586 Speed: 1000, full duplex
1189 19:44:20.842009 Using ethernet@ff3f0000 device
1190 19:44:20.842992 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1191 19:44:20.854754 Filename '954173/tftp-deploy-00jfgn93/ramdisk/ramdisk.cpio.gz.uboot'.
1192 19:44:20.855261 Load address: 0x8000000
1193 19:44:27.461053 Loading: *###################T ############################## UDP wrong checksum 00000005 00008c4a
1194 19:44:32.461323 T UDP wrong checksum 00000005 00008c4a
1195 19:44:42.472231 T T UDP wrong checksum 00000005 00008c4a
1196 19:45:00.115536 T T T UDP wrong checksum 000000ff 0000cfc6
1197 19:45:00.159432 UDP wrong checksum 000000ff 000069b9
1198 19:45:02.467250 T UDP wrong checksum 00000005 00008c4a
1199 19:45:17.471331 T T
1200 19:45:17.471967 Retry count exceeded; starting again
1202 19:45:17.473478 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1205 19:45:17.475373 end: 2.4 uboot-commands (duration 00:01:52) [common]
1207 19:45:17.476825 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1209 19:45:17.477848 end: 2 uboot-action (duration 00:01:52) [common]
1211 19:45:17.479354 Cleaning after the job
1212 19:45:17.479898 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/ramdisk
1213 19:45:17.481325 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/kernel
1214 19:45:17.509917 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/dtb
1215 19:45:17.511216 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/nfsrootfs
1216 19:45:17.556520 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954173/tftp-deploy-00jfgn93/modules
1217 19:45:17.560109 start: 4.1 power-off (timeout 00:00:30) [common]
1218 19:45:17.560697 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1219 19:45:17.592332 >> OK - accepted request
1220 19:45:17.594406 Returned 0 in 0 seconds
1221 19:45:17.695129 end: 4.1 power-off (duration 00:00:00) [common]
1223 19:45:17.696046 start: 4.2 read-feedback (timeout 00:10:00) [common]
1224 19:45:17.696687 Listened to connection for namespace 'common' for up to 1s
1225 19:45:18.696803 Finalising connection for namespace 'common'
1226 19:45:18.697343 Disconnecting from shell: Finalise
1227 19:45:18.697640 =>
1228 19:45:18.798399 end: 4.2 read-feedback (duration 00:00:01) [common]
1229 19:45:18.798924 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/954173
1230 19:45:21.708818 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/954173
1231 19:45:21.709390 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.