Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 19:25:45.396384 lava-dispatcher, installed at version: 2024.01
2 19:25:45.397269 start: 0 validate
3 19:25:45.397764 Start time: 2024-11-07 19:25:45.397733+00:00 (UTC)
4 19:25:45.398304 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:25:45.398844 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:25:45.441676 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:25:45.442213 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 19:25:45.475766 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:25:45.476429 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 19:25:45.511345 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:25:45.511898 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:25:45.554323 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 19:25:45.554874 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 19:25:45.596832 validate duration: 0.20
16 19:25:45.597685 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:25:45.598013 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:25:45.598331 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:25:45.598914 Not decompressing ramdisk as can be used compressed.
20 19:25:45.599311 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 19:25:45.599593 saving as /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/ramdisk/initrd.cpio.gz
22 19:25:45.599865 total size: 5628169 (5 MB)
23 19:25:45.634445 progress 0 % (0 MB)
24 19:25:45.642466 progress 5 % (0 MB)
25 19:25:45.647649 progress 10 % (0 MB)
26 19:25:45.651542 progress 15 % (0 MB)
27 19:25:45.655874 progress 20 % (1 MB)
28 19:25:45.659741 progress 25 % (1 MB)
29 19:25:45.663941 progress 30 % (1 MB)
30 19:25:45.668165 progress 35 % (1 MB)
31 19:25:45.671951 progress 40 % (2 MB)
32 19:25:45.676160 progress 45 % (2 MB)
33 19:25:45.680015 progress 50 % (2 MB)
34 19:25:45.684182 progress 55 % (2 MB)
35 19:25:45.688408 progress 60 % (3 MB)
36 19:25:45.692316 progress 65 % (3 MB)
37 19:25:45.696430 progress 70 % (3 MB)
38 19:25:45.700190 progress 75 % (4 MB)
39 19:25:45.704411 progress 80 % (4 MB)
40 19:25:45.708135 progress 85 % (4 MB)
41 19:25:45.712287 progress 90 % (4 MB)
42 19:25:45.716428 progress 95 % (5 MB)
43 19:25:45.719868 progress 100 % (5 MB)
44 19:25:45.720573 5 MB downloaded in 0.12 s (44.47 MB/s)
45 19:25:45.721107 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:25:45.722004 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:25:45.722305 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:25:45.722590 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:25:45.723094 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm64/defconfig/gcc-12/kernel/Image
51 19:25:45.723573 saving as /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/kernel/Image
52 19:25:45.723801 total size: 45713920 (43 MB)
53 19:25:45.724035 No compression specified
54 19:25:45.763161 progress 0 % (0 MB)
55 19:25:45.793247 progress 5 % (2 MB)
56 19:25:45.823664 progress 10 % (4 MB)
57 19:25:45.854842 progress 15 % (6 MB)
58 19:25:45.885559 progress 20 % (8 MB)
59 19:25:45.914913 progress 25 % (10 MB)
60 19:25:45.944998 progress 30 % (13 MB)
61 19:25:45.975077 progress 35 % (15 MB)
62 19:25:46.006833 progress 40 % (17 MB)
63 19:25:46.036782 progress 45 % (19 MB)
64 19:25:46.067024 progress 50 % (21 MB)
65 19:25:46.101432 progress 55 % (24 MB)
66 19:25:46.132143 progress 60 % (26 MB)
67 19:25:46.161676 progress 65 % (28 MB)
68 19:25:46.191731 progress 70 % (30 MB)
69 19:25:46.222062 progress 75 % (32 MB)
70 19:25:46.251881 progress 80 % (34 MB)
71 19:25:46.281110 progress 85 % (37 MB)
72 19:25:46.310930 progress 90 % (39 MB)
73 19:25:46.340595 progress 95 % (41 MB)
74 19:25:46.369580 progress 100 % (43 MB)
75 19:25:46.370148 43 MB downloaded in 0.65 s (67.45 MB/s)
76 19:25:46.370675 end: 1.2.1 http-download (duration 00:00:01) [common]
78 19:25:46.371583 end: 1.2 download-retry (duration 00:00:01) [common]
79 19:25:46.371891 start: 1.3 download-retry (timeout 00:09:59) [common]
80 19:25:46.372218 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 19:25:46.372745 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 19:25:46.373037 saving as /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/dtb/meson-g12b-a311d-libretech-cc.dtb
83 19:25:46.373266 total size: 54703 (0 MB)
84 19:25:46.373488 No compression specified
85 19:25:46.413173 progress 59 % (0 MB)
86 19:25:46.414026 progress 100 % (0 MB)
87 19:25:46.414578 0 MB downloaded in 0.04 s (1.26 MB/s)
88 19:25:46.415053 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:25:46.415871 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:25:46.416175 start: 1.4 download-retry (timeout 00:09:59) [common]
92 19:25:46.416440 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 19:25:46.416918 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 19:25:46.417160 saving as /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/nfsrootfs/full.rootfs.tar
95 19:25:46.417363 total size: 120894716 (115 MB)
96 19:25:46.417571 Using unxz to decompress xz
97 19:25:46.451286 progress 0 % (0 MB)
98 19:25:47.368753 progress 5 % (5 MB)
99 19:25:48.221541 progress 10 % (11 MB)
100 19:25:49.028716 progress 15 % (17 MB)
101 19:25:49.765583 progress 20 % (23 MB)
102 19:25:50.376908 progress 25 % (28 MB)
103 19:25:51.202635 progress 30 % (34 MB)
104 19:25:52.001624 progress 35 % (40 MB)
105 19:25:52.349909 progress 40 % (46 MB)
106 19:25:52.737806 progress 45 % (51 MB)
107 19:25:53.469291 progress 50 % (57 MB)
108 19:25:54.360447 progress 55 % (63 MB)
109 19:25:55.142982 progress 60 % (69 MB)
110 19:25:55.911340 progress 65 % (74 MB)
111 19:25:56.689439 progress 70 % (80 MB)
112 19:25:57.533315 progress 75 % (86 MB)
113 19:25:58.346611 progress 80 % (92 MB)
114 19:25:59.135607 progress 85 % (98 MB)
115 19:26:00.006303 progress 90 % (103 MB)
116 19:26:00.798216 progress 95 % (109 MB)
117 19:26:01.638732 progress 100 % (115 MB)
118 19:26:01.652366 115 MB downloaded in 15.23 s (7.57 MB/s)
119 19:26:01.652994 end: 1.4.1 http-download (duration 00:00:15) [common]
121 19:26:01.653818 end: 1.4 download-retry (duration 00:00:15) [common]
122 19:26:01.654085 start: 1.5 download-retry (timeout 00:09:44) [common]
123 19:26:01.654346 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 19:26:01.654888 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm64/defconfig/gcc-12/modules.tar.xz
125 19:26:01.655147 saving as /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/modules/modules.tar
126 19:26:01.655351 total size: 11613380 (11 MB)
127 19:26:01.655561 Using unxz to decompress xz
128 19:26:01.703714 progress 0 % (0 MB)
129 19:26:01.771851 progress 5 % (0 MB)
130 19:26:01.848953 progress 10 % (1 MB)
131 19:26:01.949092 progress 15 % (1 MB)
132 19:26:02.040473 progress 20 % (2 MB)
133 19:26:02.120576 progress 25 % (2 MB)
134 19:26:02.195721 progress 30 % (3 MB)
135 19:26:02.273869 progress 35 % (3 MB)
136 19:26:02.346367 progress 40 % (4 MB)
137 19:26:02.422331 progress 45 % (5 MB)
138 19:26:02.506525 progress 50 % (5 MB)
139 19:26:02.583730 progress 55 % (6 MB)
140 19:26:02.669316 progress 60 % (6 MB)
141 19:26:02.749595 progress 65 % (7 MB)
142 19:26:02.829882 progress 70 % (7 MB)
143 19:26:02.907830 progress 75 % (8 MB)
144 19:26:02.990936 progress 80 % (8 MB)
145 19:26:03.070988 progress 85 % (9 MB)
146 19:26:03.149603 progress 90 % (9 MB)
147 19:26:03.228966 progress 95 % (10 MB)
148 19:26:03.305344 progress 100 % (11 MB)
149 19:26:03.318215 11 MB downloaded in 1.66 s (6.66 MB/s)
150 19:26:03.319096 end: 1.5.1 http-download (duration 00:00:02) [common]
152 19:26:03.320742 end: 1.5 download-retry (duration 00:00:02) [common]
153 19:26:03.321278 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 19:26:03.321803 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 19:26:20.419647 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/954125/extract-nfsrootfs-yrbbeuis
156 19:26:20.420289 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 19:26:20.420582 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 19:26:20.421339 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp
159 19:26:20.421830 makedir: /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin
160 19:26:20.422170 makedir: /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/tests
161 19:26:20.422490 makedir: /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/results
162 19:26:20.422839 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-add-keys
163 19:26:20.423421 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-add-sources
164 19:26:20.423968 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-background-process-start
165 19:26:20.424544 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-background-process-stop
166 19:26:20.425081 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-common-functions
167 19:26:20.425617 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-echo-ipv4
168 19:26:20.426151 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-install-packages
169 19:26:20.426629 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-installed-packages
170 19:26:20.427098 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-os-build
171 19:26:20.427577 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-probe-channel
172 19:26:20.428069 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-probe-ip
173 19:26:20.428557 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-target-ip
174 19:26:20.429028 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-target-mac
175 19:26:20.429525 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-target-storage
176 19:26:20.430075 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-test-case
177 19:26:20.430557 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-test-event
178 19:26:20.431094 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-test-feedback
179 19:26:20.431575 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-test-raise
180 19:26:20.432066 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-test-reference
181 19:26:20.432557 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-test-runner
182 19:26:20.433038 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-test-set
183 19:26:20.433535 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-test-shell
184 19:26:20.434069 Updating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-add-keys (debian)
185 19:26:20.434607 Updating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-add-sources (debian)
186 19:26:20.435122 Updating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-install-packages (debian)
187 19:26:20.435619 Updating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-installed-packages (debian)
188 19:26:20.436128 Updating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/bin/lava-os-build (debian)
189 19:26:20.436567 Creating /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/environment
190 19:26:20.436933 LAVA metadata
191 19:26:20.437193 - LAVA_JOB_ID=954125
192 19:26:20.437411 - LAVA_DISPATCHER_IP=192.168.6.2
193 19:26:20.437775 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 19:26:20.438728 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 19:26:20.439037 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 19:26:20.439244 skipped lava-vland-overlay
197 19:26:20.439486 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 19:26:20.439740 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 19:26:20.439959 skipped lava-multinode-overlay
200 19:26:20.440224 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 19:26:20.440480 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 19:26:20.440726 Loading test definitions
203 19:26:20.441003 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 19:26:20.441225 Using /lava-954125 at stage 0
205 19:26:20.442288 uuid=954125_1.6.2.4.1 testdef=None
206 19:26:20.442587 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 19:26:20.442847 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 19:26:20.444544 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 19:26:20.445344 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 19:26:20.447339 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 19:26:20.448276 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 19:26:20.450153 runner path: /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/0/tests/0_timesync-off test_uuid 954125_1.6.2.4.1
215 19:26:20.450718 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 19:26:20.451529 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 19:26:20.451768 Using /lava-954125 at stage 0
219 19:26:20.452147 Fetching tests from https://github.com/kernelci/test-definitions.git
220 19:26:20.452448 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/0/tests/1_kselftest-rtc'
221 19:26:23.933759 Running '/usr/bin/git checkout kernelci.org
222 19:26:24.380249 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 19:26:24.381679 uuid=954125_1.6.2.4.5 testdef=None
224 19:26:24.382021 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 19:26:24.382774 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 19:26:24.385667 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 19:26:24.386488 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 19:26:24.390236 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 19:26:24.391092 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 19:26:24.394720 runner path: /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/0/tests/1_kselftest-rtc test_uuid 954125_1.6.2.4.5
234 19:26:24.395009 BOARD='meson-g12b-a311d-libretech-cc'
235 19:26:24.395218 BRANCH='broonie-sound'
236 19:26:24.395419 SKIPFILE='/dev/null'
237 19:26:24.395618 SKIP_INSTALL='True'
238 19:26:24.395816 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 19:26:24.396038 TST_CASENAME=''
240 19:26:24.396240 TST_CMDFILES='rtc'
241 19:26:24.396795 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 19:26:24.397584 Creating lava-test-runner.conf files
244 19:26:24.397788 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/954125/lava-overlay-stpkkdtp/lava-954125/0 for stage 0
245 19:26:24.398139 - 0_timesync-off
246 19:26:24.398388 - 1_kselftest-rtc
247 19:26:24.398723 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 19:26:24.399008 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 19:26:47.793977 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 19:26:47.794410 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 19:26:47.794678 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 19:26:47.794954 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 19:26:47.795222 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 19:26:48.438048 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 19:26:48.438553 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 19:26:48.438842 extracting modules file /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954125/extract-nfsrootfs-yrbbeuis
257 19:26:49.841988 extracting modules file /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954125/extract-overlay-ramdisk-l9wh_0_9/ramdisk
258 19:26:51.253805 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 19:26:51.254294 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 19:26:51.254573 [common] Applying overlay to NFS
261 19:26:51.254790 [common] Applying overlay /var/lib/lava/dispatcher/tmp/954125/compress-overlay-gd9zcf4u/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/954125/extract-nfsrootfs-yrbbeuis
262 19:26:54.041519 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 19:26:54.041998 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 19:26:54.042278 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 19:26:54.042512 Converting downloaded kernel to a uImage
266 19:26:54.042827 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/kernel/Image /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/kernel/uImage
267 19:26:54.577891 output: Image Name:
268 19:26:54.578321 output: Created: Thu Nov 7 19:26:54 2024
269 19:26:54.578534 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 19:26:54.578743 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 19:26:54.578947 output: Load Address: 01080000
272 19:26:54.579150 output: Entry Point: 01080000
273 19:26:54.579351 output:
274 19:26:54.579691 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 19:26:54.579963 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 19:26:54.580283 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 19:26:54.580548 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 19:26:54.580811 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 19:26:54.581071 Building ramdisk /var/lib/lava/dispatcher/tmp/954125/extract-overlay-ramdisk-l9wh_0_9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/954125/extract-overlay-ramdisk-l9wh_0_9/ramdisk
280 19:26:56.807344 >> 166792 blocks
281 19:27:04.880292 Adding RAMdisk u-boot header.
282 19:27:04.880736 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/954125/extract-overlay-ramdisk-l9wh_0_9/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/954125/extract-overlay-ramdisk-l9wh_0_9/ramdisk.cpio.gz.uboot
283 19:27:05.187920 output: Image Name:
284 19:27:05.188550 output: Created: Thu Nov 7 19:27:04 2024
285 19:27:05.188976 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 19:27:05.189384 output: Data Size: 23433271 Bytes = 22884.05 KiB = 22.35 MiB
287 19:27:05.189789 output: Load Address: 00000000
288 19:27:05.190187 output: Entry Point: 00000000
289 19:27:05.190591 output:
290 19:27:05.191587 rename /var/lib/lava/dispatcher/tmp/954125/extract-overlay-ramdisk-l9wh_0_9/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/ramdisk/ramdisk.cpio.gz.uboot
291 19:27:05.192350 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 19:27:05.192900 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 19:27:05.193430 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 19:27:05.193887 No LXC device requested
295 19:27:05.194388 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 19:27:05.194898 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 19:27:05.195393 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 19:27:05.195806 Checking files for TFTP limit of 4294967296 bytes.
299 19:27:05.198573 end: 1 tftp-deploy (duration 00:01:20) [common]
300 19:27:05.199159 start: 2 uboot-action (timeout 00:05:00) [common]
301 19:27:05.199682 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 19:27:05.200218 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 19:27:05.200727 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 19:27:05.201257 Using kernel file from prepare-kernel: 954125/tftp-deploy-l2_6helz/kernel/uImage
305 19:27:05.201884 substitutions:
306 19:27:05.202294 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 19:27:05.202700 - {DTB_ADDR}: 0x01070000
308 19:27:05.203103 - {DTB}: 954125/tftp-deploy-l2_6helz/dtb/meson-g12b-a311d-libretech-cc.dtb
309 19:27:05.203506 - {INITRD}: 954125/tftp-deploy-l2_6helz/ramdisk/ramdisk.cpio.gz.uboot
310 19:27:05.203904 - {KERNEL_ADDR}: 0x01080000
311 19:27:05.204332 - {KERNEL}: 954125/tftp-deploy-l2_6helz/kernel/uImage
312 19:27:05.204727 - {LAVA_MAC}: None
313 19:27:05.205161 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/954125/extract-nfsrootfs-yrbbeuis
314 19:27:05.205562 - {NFS_SERVER_IP}: 192.168.6.2
315 19:27:05.205953 - {PRESEED_CONFIG}: None
316 19:27:05.206347 - {PRESEED_LOCAL}: None
317 19:27:05.206736 - {RAMDISK_ADDR}: 0x08000000
318 19:27:05.207125 - {RAMDISK}: 954125/tftp-deploy-l2_6helz/ramdisk/ramdisk.cpio.gz.uboot
319 19:27:05.207518 - {ROOT_PART}: None
320 19:27:05.207908 - {ROOT}: None
321 19:27:05.208328 - {SERVER_IP}: 192.168.6.2
322 19:27:05.208718 - {TEE_ADDR}: 0x83000000
323 19:27:05.209104 - {TEE}: None
324 19:27:05.209491 Parsed boot commands:
325 19:27:05.209871 - setenv autoload no
326 19:27:05.210256 - setenv initrd_high 0xffffffff
327 19:27:05.210640 - setenv fdt_high 0xffffffff
328 19:27:05.211027 - dhcp
329 19:27:05.211412 - setenv serverip 192.168.6.2
330 19:27:05.211801 - tftpboot 0x01080000 954125/tftp-deploy-l2_6helz/kernel/uImage
331 19:27:05.212252 - tftpboot 0x08000000 954125/tftp-deploy-l2_6helz/ramdisk/ramdisk.cpio.gz.uboot
332 19:27:05.212649 - tftpboot 0x01070000 954125/tftp-deploy-l2_6helz/dtb/meson-g12b-a311d-libretech-cc.dtb
333 19:27:05.213046 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/954125/extract-nfsrootfs-yrbbeuis,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 19:27:05.213450 - bootm 0x01080000 0x08000000 0x01070000
335 19:27:05.213958 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 19:27:05.215441 start: 2.3 connect-device (timeout 00:05:00) [common]
338 19:27:05.215864 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 19:27:05.231141 Setting prompt string to ['lava-test: # ']
340 19:27:05.232728 end: 2.3 connect-device (duration 00:00:00) [common]
341 19:27:05.233358 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 19:27:05.233923 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 19:27:05.234463 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 19:27:05.235613 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 19:27:05.272782 >> OK - accepted request
346 19:27:05.274927 Returned 0 in 0 seconds
347 19:27:05.376039 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 19:27:05.377615 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 19:27:05.378161 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 19:27:05.378660 Setting prompt string to ['Hit any key to stop autoboot']
352 19:27:05.379105 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 19:27:05.380711 Trying 192.168.56.21...
354 19:27:05.381217 Connected to conserv1.
355 19:27:05.381622 Escape character is '^]'.
356 19:27:05.382033
357 19:27:05.382452 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 19:27:05.382880
359 19:27:17.554300 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 19:27:17.554940 bl2_stage_init 0x01
361 19:27:17.555356 bl2_stage_init 0x81
362 19:27:17.559819 hw id: 0x0000 - pwm id 0x01
363 19:27:17.560310 bl2_stage_init 0xc1
364 19:27:17.560739 bl2_stage_init 0x02
365 19:27:17.561146
366 19:27:17.565308 L0:00000000
367 19:27:17.565783 L1:20000703
368 19:27:17.566199 L2:00008067
369 19:27:17.566603 L3:14000000
370 19:27:17.568382 B2:00402000
371 19:27:17.568845 B1:e0f83180
372 19:27:17.569251
373 19:27:17.569650 TE: 58159
374 19:27:17.570041
375 19:27:17.579629 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 19:27:17.580094
377 19:27:17.580493 Board ID = 1
378 19:27:17.580876 Set A53 clk to 24M
379 19:27:17.581260 Set A73 clk to 24M
380 19:27:17.585141 Set clk81 to 24M
381 19:27:17.585580 A53 clk: 1200 MHz
382 19:27:17.585971 A73 clk: 1200 MHz
383 19:27:17.590797 CLK81: 166.6M
384 19:27:17.591513 smccc: 00012ab5
385 19:27:17.596392 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 19:27:17.597071 board id: 1
387 19:27:17.604961 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 19:27:17.615281 fw parse done
389 19:27:17.621284 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 19:27:17.663857 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 19:27:17.674805 PIEI prepare done
392 19:27:17.675360 fastboot data load
393 19:27:17.675884 fastboot data verify
394 19:27:17.680522 verify result: 266
395 19:27:17.686046 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 19:27:17.686609 LPDDR4 probe
397 19:27:17.687146 ddr clk to 1584MHz
398 19:27:17.694014 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 19:27:17.731262
400 19:27:17.731895 dmc_version 0001
401 19:27:17.737930 Check phy result
402 19:27:17.743766 INFO : End of CA training
403 19:27:17.744366 INFO : End of initialization
404 19:27:17.749573 INFO : Training has run successfully!
405 19:27:17.750106 Check phy result
406 19:27:17.755146 INFO : End of initialization
407 19:27:17.755789 INFO : End of read enable training
408 19:27:17.760638 INFO : End of fine write leveling
409 19:27:17.766212 INFO : End of Write leveling coarse delay
410 19:27:17.766812 INFO : Training has run successfully!
411 19:27:17.767349 Check phy result
412 19:27:17.771795 INFO : End of initialization
413 19:27:17.772411 INFO : End of read dq deskew training
414 19:27:17.777570 INFO : End of MPR read delay center optimization
415 19:27:17.783059 INFO : End of write delay center optimization
416 19:27:17.788664 INFO : End of read delay center optimization
417 19:27:17.789251 INFO : End of max read latency training
418 19:27:17.794243 INFO : Training has run successfully!
419 19:27:17.794813 1D training succeed
420 19:27:17.803410 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 19:27:17.851011 Check phy result
422 19:27:17.851616 INFO : End of initialization
423 19:27:17.872951 INFO : End of 2D read delay Voltage center optimization
424 19:27:17.893175 INFO : End of 2D read delay Voltage center optimization
425 19:27:17.945180 INFO : End of 2D write delay Voltage center optimization
426 19:27:17.994479 INFO : End of 2D write delay Voltage center optimization
427 19:27:18.000021 INFO : Training has run successfully!
428 19:27:18.000599
429 19:27:18.001121 channel==0
430 19:27:18.005600 RxClkDly_Margin_A0==78 ps 8
431 19:27:18.006173 TxDqDly_Margin_A0==98 ps 10
432 19:27:18.011190 RxClkDly_Margin_A1==88 ps 9
433 19:27:18.011733 TxDqDly_Margin_A1==98 ps 10
434 19:27:18.012285 TrainedVREFDQ_A0==74
435 19:27:18.016783 TrainedVREFDQ_A1==74
436 19:27:18.017333 VrefDac_Margin_A0==25
437 19:27:18.017853 DeviceVref_Margin_A0==40
438 19:27:18.022424 VrefDac_Margin_A1==25
439 19:27:18.022980 DeviceVref_Margin_A1==40
440 19:27:18.023505
441 19:27:18.024040
442 19:27:18.028058 channel==1
443 19:27:18.028632 RxClkDly_Margin_A0==98 ps 10
444 19:27:18.029147 TxDqDly_Margin_A0==98 ps 10
445 19:27:18.033651 RxClkDly_Margin_A1==98 ps 10
446 19:27:18.034223 TxDqDly_Margin_A1==88 ps 9
447 19:27:18.039174 TrainedVREFDQ_A0==77
448 19:27:18.039721 TrainedVREFDQ_A1==77
449 19:27:18.040272 VrefDac_Margin_A0==22
450 19:27:18.044843 DeviceVref_Margin_A0==37
451 19:27:18.045400 VrefDac_Margin_A1==22
452 19:27:18.050410 DeviceVref_Margin_A1==37
453 19:27:18.050947
454 19:27:18.051471 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 19:27:18.056003
456 19:27:18.084011 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 19:27:18.084653 2D training succeed
458 19:27:18.089566 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 19:27:18.095173 auto size-- 65535DDR cs0 size: 2048MB
460 19:27:18.095704 DDR cs1 size: 2048MB
461 19:27:18.100817 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 19:27:18.101363 cs0 DataBus test pass
463 19:27:18.106348 cs1 DataBus test pass
464 19:27:18.106884 cs0 AddrBus test pass
465 19:27:18.107394 cs1 AddrBus test pass
466 19:27:18.107897
467 19:27:18.112032 100bdlr_step_size ps== 420
468 19:27:18.112586 result report
469 19:27:18.117581 boot times 0Enable ddr reg access
470 19:27:18.122966 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 19:27:18.136638 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 19:27:18.710239 0.0;M3 CHK:0;cm4_sp_mode 0
473 19:27:18.711019 MVN_1=0x00000000
474 19:27:18.715634 MVN_2=0x00000000
475 19:27:18.721364 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 19:27:18.721950 OPS=0x10
477 19:27:18.722494 ring efuse init
478 19:27:18.723016 chipver efuse init
479 19:27:18.727026 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 19:27:18.732583 [0.018960 Inits done]
481 19:27:18.733162 secure task start!
482 19:27:18.733689 high task start!
483 19:27:18.737185 low task start!
484 19:27:18.737736 run into bl31
485 19:27:18.743780 NOTICE: BL31: v1.3(release):4fc40b1
486 19:27:18.751697 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 19:27:18.752304 NOTICE: BL31: G12A normal boot!
488 19:27:18.777038 NOTICE: BL31: BL33 decompress pass
489 19:27:18.782704 ERROR: Error initializing runtime service opteed_fast
490 19:27:20.015651
491 19:27:20.016455
492 19:27:20.024032 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 19:27:20.024641
494 19:27:20.025185 Model: Libre Computer AML-A311D-CC Alta
495 19:27:20.232525 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 19:27:20.255950 DRAM: 2 GiB (effective 3.8 GiB)
497 19:27:20.398944 Core: 408 devices, 31 uclasses, devicetree: separate
498 19:27:20.404649 WDT: Not starting watchdog@f0d0
499 19:27:20.436958 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 19:27:20.449418 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 19:27:20.454348 ** Bad device specification mmc 0 **
502 19:27:20.464718 Card did not respond to voltage select! : -110
503 19:27:20.472347 ** Bad device specification mmc 0 **
504 19:27:20.472904 Couldn't find partition mmc 0
505 19:27:20.480680 Card did not respond to voltage select! : -110
506 19:27:20.486250 ** Bad device specification mmc 0 **
507 19:27:20.486821 Couldn't find partition mmc 0
508 19:27:20.491311 Error: could not access storage.
509 19:27:21.754548 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 19:27:21.755220 bl2_stage_init 0x01
511 19:27:21.755658 bl2_stage_init 0x81
512 19:27:21.760028 hw id: 0x0000 - pwm id 0x01
513 19:27:21.760490 bl2_stage_init 0xc1
514 19:27:21.760910 bl2_stage_init 0x02
515 19:27:21.761317
516 19:27:21.765632 L0:00000000
517 19:27:21.766070 L1:20000703
518 19:27:21.766477 L2:00008067
519 19:27:21.766879 L3:14000000
520 19:27:21.771151 B2:00402000
521 19:27:21.771588 B1:e0f83180
522 19:27:21.772022
523 19:27:21.772434 TE: 58167
524 19:27:21.772840
525 19:27:21.776803 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 19:27:21.777241
527 19:27:21.777649 Board ID = 1
528 19:27:21.782353 Set A53 clk to 24M
529 19:27:21.782788 Set A73 clk to 24M
530 19:27:21.783195 Set clk81 to 24M
531 19:27:21.788046 A53 clk: 1200 MHz
532 19:27:21.788480 A73 clk: 1200 MHz
533 19:27:21.788882 CLK81: 166.6M
534 19:27:21.789281 smccc: 00012abe
535 19:27:21.793642 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 19:27:21.799176 board id: 1
537 19:27:21.805082 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 19:27:21.815748 fw parse done
539 19:27:21.821723 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 19:27:21.864314 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 19:27:21.875228 PIEI prepare done
542 19:27:21.875657 fastboot data load
543 19:27:21.876103 fastboot data verify
544 19:27:21.880920 verify result: 266
545 19:27:21.886550 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 19:27:21.886979 LPDDR4 probe
547 19:27:21.887385 ddr clk to 1584MHz
548 19:27:21.894482 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 19:27:21.931774
550 19:27:21.932250 dmc_version 0001
551 19:27:21.938433 Check phy result
552 19:27:21.944292 INFO : End of CA training
553 19:27:21.944724 INFO : End of initialization
554 19:27:21.949928 INFO : Training has run successfully!
555 19:27:21.950358 Check phy result
556 19:27:21.955509 INFO : End of initialization
557 19:27:21.955939 INFO : End of read enable training
558 19:27:21.961165 INFO : End of fine write leveling
559 19:27:21.966688 INFO : End of Write leveling coarse delay
560 19:27:21.967112 INFO : Training has run successfully!
561 19:27:21.967516 Check phy result
562 19:27:21.972290 INFO : End of initialization
563 19:27:21.972720 INFO : End of read dq deskew training
564 19:27:21.977881 INFO : End of MPR read delay center optimization
565 19:27:21.983459 INFO : End of write delay center optimization
566 19:27:21.989175 INFO : End of read delay center optimization
567 19:27:21.989606 INFO : End of max read latency training
568 19:27:21.994675 INFO : Training has run successfully!
569 19:27:21.995100 1D training succeed
570 19:27:22.003870 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 19:27:22.051472 Check phy result
572 19:27:22.051933 INFO : End of initialization
573 19:27:22.073278 INFO : End of 2D read delay Voltage center optimization
574 19:27:22.093441 INFO : End of 2D read delay Voltage center optimization
575 19:27:22.145468 INFO : End of 2D write delay Voltage center optimization
576 19:27:22.194811 INFO : End of 2D write delay Voltage center optimization
577 19:27:22.200415 INFO : Training has run successfully!
578 19:27:22.200854
579 19:27:22.201264 channel==0
580 19:27:22.206014 RxClkDly_Margin_A0==88 ps 9
581 19:27:22.206442 TxDqDly_Margin_A0==98 ps 10
582 19:27:22.211601 RxClkDly_Margin_A1==88 ps 9
583 19:27:22.212065 TxDqDly_Margin_A1==98 ps 10
584 19:27:22.212480 TrainedVREFDQ_A0==74
585 19:27:22.217238 TrainedVREFDQ_A1==74
586 19:27:22.217672 VrefDac_Margin_A0==25
587 19:27:22.218076 DeviceVref_Margin_A0==40
588 19:27:22.222802 VrefDac_Margin_A1==26
589 19:27:22.223229 DeviceVref_Margin_A1==40
590 19:27:22.223630
591 19:27:22.224060
592 19:27:22.228446 channel==1
593 19:27:22.228877 RxClkDly_Margin_A0==98 ps 10
594 19:27:22.229277 TxDqDly_Margin_A0==98 ps 10
595 19:27:22.233998 RxClkDly_Margin_A1==98 ps 10
596 19:27:22.234429 TxDqDly_Margin_A1==88 ps 9
597 19:27:22.239583 TrainedVREFDQ_A0==77
598 19:27:22.240041 TrainedVREFDQ_A1==77
599 19:27:22.240452 VrefDac_Margin_A0==22
600 19:27:22.245204 DeviceVref_Margin_A0==37
601 19:27:22.245623 VrefDac_Margin_A1==22
602 19:27:22.250821 DeviceVref_Margin_A1==37
603 19:27:22.251248
604 19:27:22.251654 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 19:27:22.256411
606 19:27:22.284405 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
607 19:27:22.284881 2D training succeed
608 19:27:22.289983 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 19:27:22.295609 auto size-- 65535DDR cs0 size: 2048MB
610 19:27:22.296075 DDR cs1 size: 2048MB
611 19:27:22.301182 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 19:27:22.301613 cs0 DataBus test pass
613 19:27:22.306823 cs1 DataBus test pass
614 19:27:22.307261 cs0 AddrBus test pass
615 19:27:22.307664 cs1 AddrBus test pass
616 19:27:22.308098
617 19:27:22.312396 100bdlr_step_size ps== 420
618 19:27:22.312837 result report
619 19:27:22.317992 boot times 0Enable ddr reg access
620 19:27:22.323447 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 19:27:22.336934 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 19:27:22.910974 0.0;M3 CHK:0;cm4_sp_mode 0
623 19:27:22.911586 MVN_1=0x00000000
624 19:27:22.916175 MVN_2=0x00000000
625 19:27:22.922108 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 19:27:22.922574 OPS=0x10
627 19:27:22.922986 ring efuse init
628 19:27:22.923394 chipver efuse init
629 19:27:22.927622 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 19:27:22.933154 [0.018960 Inits done]
631 19:27:22.933592 secure task start!
632 19:27:22.933981 high task start!
633 19:27:22.937786 low task start!
634 19:27:22.938232 run into bl31
635 19:27:22.944410 NOTICE: BL31: v1.3(release):4fc40b1
636 19:27:22.952250 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 19:27:22.952679 NOTICE: BL31: G12A normal boot!
638 19:27:22.977627 NOTICE: BL31: BL33 decompress pass
639 19:27:22.983277 ERROR: Error initializing runtime service opteed_fast
640 19:27:24.216263
641 19:27:24.216852
642 19:27:24.224452 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 19:27:24.224905
644 19:27:24.225320 Model: Libre Computer AML-A311D-CC Alta
645 19:27:24.435517 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 19:27:24.456392 DRAM: 2 GiB (effective 3.8 GiB)
647 19:27:24.599340 Core: 408 devices, 31 uclasses, devicetree: separate
648 19:27:24.605232 WDT: Not starting watchdog@f0d0
649 19:27:24.637427 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 19:27:24.649843 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 19:27:24.654949 ** Bad device specification mmc 0 **
652 19:27:24.665249 Card did not respond to voltage select! : -110
653 19:27:24.671964 ** Bad device specification mmc 0 **
654 19:27:24.672451 Couldn't find partition mmc 0
655 19:27:24.681224 Card did not respond to voltage select! : -110
656 19:27:24.686683 ** Bad device specification mmc 0 **
657 19:27:24.687165 Couldn't find partition mmc 0
658 19:27:24.691691 Error: could not access storage.
659 19:27:25.034456 Net: eth0: ethernet@ff3f0000
660 19:27:25.035030 starting USB...
661 19:27:25.407641 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 19:27:25.408288 Starting the controller
663 19:27:25.410749 USB XHCI 1.10
664 19:27:27.005170 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
665 19:27:27.005846 bl2_stage_init 0x81
666 19:27:27.010740 hw id: 0x0000 - pwm id 0x01
667 19:27:27.011219 bl2_stage_init 0xc1
668 19:27:27.011473 bl2_stage_init 0x02
669 19:27:27.011720
670 19:27:27.016203 L0:00000000
671 19:27:27.016659 L1:20000703
672 19:27:27.016944 L2:00008067
673 19:27:27.017220 L3:14000000
674 19:27:27.017524 B2:00402000
675 19:27:27.021874 B1:e0f83180
676 19:27:27.022260
677 19:27:27.022570 TE: 58150
678 19:27:27.022995
679 19:27:27.027360 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 19:27:27.028041
681 19:27:27.028603 Board ID = 1
682 19:27:27.033036 Set A53 clk to 24M
683 19:27:27.033653 Set A73 clk to 24M
684 19:27:27.034211 Set clk81 to 24M
685 19:27:27.038654 A53 clk: 1200 MHz
686 19:27:27.039093 A73 clk: 1200 MHz
687 19:27:27.039372 CLK81: 166.6M
688 19:27:27.039628 smccc: 00012aac
689 19:27:27.044398 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 19:27:27.049956 board id: 1
691 19:27:27.055795 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 19:27:27.066224 fw parse done
693 19:27:27.072269 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 19:27:27.114884 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 19:27:27.125797 PIEI prepare done
696 19:27:27.126431 fastboot data load
697 19:27:27.126985 fastboot data verify
698 19:27:27.131240 verify result: 266
699 19:27:27.136851 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 19:27:27.137457 LPDDR4 probe
701 19:27:27.137997 ddr clk to 1584MHz
702 19:27:27.144882 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 19:27:27.182198
704 19:27:27.182941 dmc_version 0001
705 19:27:27.188935 Check phy result
706 19:27:27.194616 INFO : End of CA training
707 19:27:27.195210 INFO : End of initialization
708 19:27:27.200291 INFO : Training has run successfully!
709 19:27:27.200884 Check phy result
710 19:27:27.205822 INFO : End of initialization
711 19:27:27.206424 INFO : End of read enable training
712 19:27:27.211476 INFO : End of fine write leveling
713 19:27:27.217107 INFO : End of Write leveling coarse delay
714 19:27:27.217697 INFO : Training has run successfully!
715 19:27:27.218221 Check phy result
716 19:27:27.222647 INFO : End of initialization
717 19:27:27.223229 INFO : End of read dq deskew training
718 19:27:27.228285 INFO : End of MPR read delay center optimization
719 19:27:27.233813 INFO : End of write delay center optimization
720 19:27:27.239501 INFO : End of read delay center optimization
721 19:27:27.240105 INFO : End of max read latency training
722 19:27:27.245109 INFO : Training has run successfully!
723 19:27:27.245682 1D training succeed
724 19:27:27.254296 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 19:27:27.301980 Check phy result
726 19:27:27.302713 INFO : End of initialization
727 19:27:27.323604 INFO : End of 2D read delay Voltage center optimization
728 19:27:27.344053 INFO : End of 2D read delay Voltage center optimization
729 19:27:27.396124 INFO : End of 2D write delay Voltage center optimization
730 19:27:27.445454 INFO : End of 2D write delay Voltage center optimization
731 19:27:27.450944 INFO : Training has run successfully!
732 19:27:27.451626
733 19:27:27.452244 channel==0
734 19:27:27.456396 RxClkDly_Margin_A0==88 ps 9
735 19:27:27.457053 TxDqDly_Margin_A0==98 ps 10
736 19:27:27.462054 RxClkDly_Margin_A1==88 ps 9
737 19:27:27.462680 TxDqDly_Margin_A1==98 ps 10
738 19:27:27.463225 TrainedVREFDQ_A0==74
739 19:27:27.467692 TrainedVREFDQ_A1==76
740 19:27:27.468393 VrefDac_Margin_A0==25
741 19:27:27.468941 DeviceVref_Margin_A0==40
742 19:27:27.473267 VrefDac_Margin_A1==25
743 19:27:27.473894 DeviceVref_Margin_A1==38
744 19:27:27.474442
745 19:27:27.475117
746 19:27:27.479040 channel==1
747 19:27:27.479810 RxClkDly_Margin_A0==98 ps 10
748 19:27:27.480415 TxDqDly_Margin_A0==88 ps 9
749 19:27:27.484425 RxClkDly_Margin_A1==98 ps 10
750 19:27:27.485054 TxDqDly_Margin_A1==88 ps 9
751 19:27:27.490775 TrainedVREFDQ_A0==77
752 19:27:27.491411 TrainedVREFDQ_A1==77
753 19:27:27.491957 VrefDac_Margin_A0==22
754 19:27:27.495674 DeviceVref_Margin_A0==37
755 19:27:27.496363 VrefDac_Margin_A1==24
756 19:27:27.502556 DeviceVref_Margin_A1==37
757 19:27:27.503210
758 19:27:27.503759 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 19:27:27.504361
760 19:27:27.534980 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
761 19:27:27.535690 2D training succeed
762 19:27:27.540496 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 19:27:27.546084 auto size-- 65535DDR cs0 size: 2048MB
764 19:27:27.546744 DDR cs1 size: 2048MB
765 19:27:27.551674 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 19:27:27.552370 cs0 DataBus test pass
767 19:27:27.557217 cs1 DataBus test pass
768 19:27:27.557860 cs0 AddrBus test pass
769 19:27:27.558410 cs1 AddrBus test pass
770 19:27:27.558945
771 19:27:27.562974 100bdlr_step_size ps== 420
772 19:27:27.563634 result report
773 19:27:27.568451 boot times 0Enable ddr reg access
774 19:27:27.573810 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 19:27:27.587284 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 19:27:28.161062 0.0;M3 CHK:0;cm4_sp_mode 0
777 19:27:28.161856 MVN_1=0x00000000
778 19:27:28.166336 MVN_2=0x00000000
779 19:27:28.172157 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 19:27:28.172833 OPS=0x10
781 19:27:28.173353 ring efuse init
782 19:27:28.173865 chipver efuse init
783 19:27:28.177811 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 19:27:28.183312 [0.018960 Inits done]
785 19:27:28.183911 secure task start!
786 19:27:28.184471 high task start!
787 19:27:28.187892 low task start!
788 19:27:28.188481 run into bl31
789 19:27:28.194560 NOTICE: BL31: v1.3(release):4fc40b1
790 19:27:28.202348 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 19:27:28.202924 NOTICE: BL31: G12A normal boot!
792 19:27:28.227757 NOTICE: BL31: BL33 decompress pass
793 19:27:28.233415 ERROR: Error initializing runtime service opteed_fast
794 19:27:29.466322
795 19:27:29.467107
796 19:27:29.474663 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 19:27:29.475288
798 19:27:29.475835 Model: Libre Computer AML-A311D-CC Alta
799 19:27:29.683188 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 19:27:29.706556 DRAM: 2 GiB (effective 3.8 GiB)
801 19:27:29.849562 Core: 408 devices, 31 uclasses, devicetree: separate
802 19:27:29.855345 WDT: Not starting watchdog@f0d0
803 19:27:29.888919 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 19:27:29.900108 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 19:27:29.905031 ** Bad device specification mmc 0 **
806 19:27:29.915304 Card did not respond to voltage select! : -110
807 19:27:29.922991 ** Bad device specification mmc 0 **
808 19:27:29.923588 Couldn't find partition mmc 0
809 19:27:29.931306 Card did not respond to voltage select! : -110
810 19:27:29.936901 ** Bad device specification mmc 0 **
811 19:27:29.937516 Couldn't find partition mmc 0
812 19:27:29.941911 Error: could not access storage.
813 19:27:30.284389 Net: eth0: ethernet@ff3f0000
814 19:27:30.285173 starting USB...
815 19:27:30.536427 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 19:27:30.537214 Starting the controller
817 19:27:30.543355 USB XHCI 1.10
818 19:27:32.705233 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 19:27:32.706060 bl2_stage_init 0x01
820 19:27:32.706637 bl2_stage_init 0x81
821 19:27:32.710702 hw id: 0x0000 - pwm id 0x01
822 19:27:32.711295 bl2_stage_init 0xc1
823 19:27:32.711838 bl2_stage_init 0x02
824 19:27:32.712447
825 19:27:32.716285 L0:00000000
826 19:27:32.716875 L1:20000703
827 19:27:32.717417 L2:00008067
828 19:27:32.717947 L3:14000000
829 19:27:32.719283 B2:00402000
830 19:27:32.719846 B1:e0f83180
831 19:27:32.720413
832 19:27:32.720947 TE: 58124
833 19:27:32.721468
834 19:27:32.730419 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 19:27:32.731012
836 19:27:32.731543 Board ID = 1
837 19:27:32.732108 Set A53 clk to 24M
838 19:27:32.732636 Set A73 clk to 24M
839 19:27:32.736163 Set clk81 to 24M
840 19:27:32.736726 A53 clk: 1200 MHz
841 19:27:32.737256 A73 clk: 1200 MHz
842 19:27:32.741697 CLK81: 166.6M
843 19:27:32.742260 smccc: 00012a92
844 19:27:32.747260 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 19:27:32.747828 board id: 1
846 19:27:32.755868 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 19:27:32.766386 fw parse done
848 19:27:32.772390 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 19:27:32.814983 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 19:27:32.825828 PIEI prepare done
851 19:27:32.826419 fastboot data load
852 19:27:32.826962 fastboot data verify
853 19:27:32.831556 verify result: 266
854 19:27:32.837074 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 19:27:32.837638 LPDDR4 probe
856 19:27:32.838177 ddr clk to 1584MHz
857 19:27:32.845004 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 19:27:32.881465
859 19:27:32.882016 dmc_version 0001
860 19:27:32.889225 Check phy result
861 19:27:32.894974 INFO : End of CA training
862 19:27:32.895468 INFO : End of initialization
863 19:27:32.900577 INFO : Training has run successfully!
864 19:27:32.901073 Check phy result
865 19:27:32.906214 INFO : End of initialization
866 19:27:32.906714 INFO : End of read enable training
867 19:27:32.909455 INFO : End of fine write leveling
868 19:27:32.915145 INFO : End of Write leveling coarse delay
869 19:27:32.920734 INFO : Training has run successfully!
870 19:27:32.921238 Check phy result
871 19:27:32.921661 INFO : End of initialization
872 19:27:32.926336 INFO : End of read dq deskew training
873 19:27:32.931935 INFO : End of MPR read delay center optimization
874 19:27:32.932463 INFO : End of write delay center optimization
875 19:27:32.937462 INFO : End of read delay center optimization
876 19:27:32.943071 INFO : End of max read latency training
877 19:27:32.943579 INFO : Training has run successfully!
878 19:27:32.948697 1D training succeed
879 19:27:32.954553 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 19:27:33.002187 Check phy result
881 19:27:33.002739 INFO : End of initialization
882 19:27:33.024054 INFO : End of 2D read delay Voltage center optimization
883 19:27:33.044370 INFO : End of 2D read delay Voltage center optimization
884 19:27:33.096374 INFO : End of 2D write delay Voltage center optimization
885 19:27:33.145576 INFO : End of 2D write delay Voltage center optimization
886 19:27:33.151146 INFO : Training has run successfully!
887 19:27:33.151648
888 19:27:33.152120 channel==0
889 19:27:33.156725 RxClkDly_Margin_A0==88 ps 9
890 19:27:33.157269 TxDqDly_Margin_A0==98 ps 10
891 19:27:33.162355 RxClkDly_Margin_A1==88 ps 9
892 19:27:33.162853 TxDqDly_Margin_A1==98 ps 10
893 19:27:33.163296 TrainedVREFDQ_A0==74
894 19:27:33.167909 TrainedVREFDQ_A1==74
895 19:27:33.168484 VrefDac_Margin_A0==25
896 19:27:33.168911 DeviceVref_Margin_A0==40
897 19:27:33.173539 VrefDac_Margin_A1==25
898 19:27:33.174062 DeviceVref_Margin_A1==40
899 19:27:33.174459
900 19:27:33.174850
901 19:27:33.179103 channel==1
902 19:27:33.179577 RxClkDly_Margin_A0==98 ps 10
903 19:27:33.179971 TxDqDly_Margin_A0==88 ps 9
904 19:27:33.184723 RxClkDly_Margin_A1==98 ps 10
905 19:27:33.185190 TxDqDly_Margin_A1==88 ps 9
906 19:27:33.190311 TrainedVREFDQ_A0==76
907 19:27:33.190799 TrainedVREFDQ_A1==77
908 19:27:33.191198 VrefDac_Margin_A0==22
909 19:27:33.195817 DeviceVref_Margin_A0==38
910 19:27:33.196308 VrefDac_Margin_A1==22
911 19:27:33.201449 DeviceVref_Margin_A1==37
912 19:27:33.201909
913 19:27:33.202303 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 19:27:33.202693
915 19:27:33.235047 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
916 19:27:33.235568 2D training succeed
917 19:27:33.240689 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 19:27:33.246249 auto size-- 65535DDR cs0 size: 2048MB
919 19:27:33.246715 DDR cs1 size: 2048MB
920 19:27:33.251852 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 19:27:33.252371 cs0 DataBus test pass
922 19:27:33.257430 cs1 DataBus test pass
923 19:27:33.257894 cs0 AddrBus test pass
924 19:27:33.258291 cs1 AddrBus test pass
925 19:27:33.258679
926 19:27:33.263082 100bdlr_step_size ps== 420
927 19:27:33.263556 result report
928 19:27:33.268687 boot times 0Enable ddr reg access
929 19:27:33.274006 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 19:27:33.287500 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 19:27:33.861338 0.0;M3 CHK:0;cm4_sp_mode 0
932 19:27:33.861987 MVN_1=0x00000000
933 19:27:33.866900 MVN_2=0x00000000
934 19:27:33.872614 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 19:27:33.873143 OPS=0x10
936 19:27:33.873581 ring efuse init
937 19:27:33.874004 chipver efuse init
938 19:27:33.878164 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 19:27:33.883818 [0.018961 Inits done]
940 19:27:33.884388 secure task start!
941 19:27:33.884813 high task start!
942 19:27:33.889114 low task start!
943 19:27:33.889604 run into bl31
944 19:27:33.895034 NOTICE: BL31: v1.3(release):4fc40b1
945 19:27:33.902774 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 19:27:33.903271 NOTICE: BL31: G12A normal boot!
947 19:27:33.928187 NOTICE: BL31: BL33 decompress pass
948 19:27:33.933859 ERROR: Error initializing runtime service opteed_fast
949 19:27:35.166886
950 19:27:35.167520
951 19:27:35.175155 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 19:27:35.175672
953 19:27:35.176156 Model: Libre Computer AML-A311D-CC Alta
954 19:27:35.383514 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 19:27:35.406998 DRAM: 2 GiB (effective 3.8 GiB)
956 19:27:35.549878 Core: 408 devices, 31 uclasses, devicetree: separate
957 19:27:35.555651 WDT: Not starting watchdog@f0d0
958 19:27:35.588056 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 19:27:35.600430 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 19:27:35.605275 ** Bad device specification mmc 0 **
961 19:27:35.615802 Card did not respond to voltage select! : -110
962 19:27:35.623306 ** Bad device specification mmc 0 **
963 19:27:35.623778 Couldn't find partition mmc 0
964 19:27:35.631760 Card did not respond to voltage select! : -110
965 19:27:35.637181 ** Bad device specification mmc 0 **
966 19:27:35.637647 Couldn't find partition mmc 0
967 19:27:35.642250 Error: could not access storage.
968 19:27:35.984689 Net: eth0: ethernet@ff3f0000
969 19:27:35.985223 starting USB...
970 19:27:36.236645 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 19:27:36.237190 Starting the controller
972 19:27:36.243516 USB XHCI 1.10
973 19:27:38.105149 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
974 19:27:38.105772 bl2_stage_init 0x01
975 19:27:38.106210 bl2_stage_init 0x81
976 19:27:38.110654 hw id: 0x0000 - pwm id 0x01
977 19:27:38.111108 bl2_stage_init 0xc1
978 19:27:38.111522 bl2_stage_init 0x02
979 19:27:38.111930
980 19:27:38.116075 L0:00000000
981 19:27:38.116528 L1:20000703
982 19:27:38.116943 L2:00008067
983 19:27:38.117347 L3:14000000
984 19:27:38.121769 B2:00402000
985 19:27:38.122214 B1:e0f83180
986 19:27:38.122624
987 19:27:38.123027 TE: 58124
988 19:27:38.123427
989 19:27:38.127345 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 19:27:38.127797
991 19:27:38.128248 Board ID = 1
992 19:27:38.132948 Set A53 clk to 24M
993 19:27:38.133392 Set A73 clk to 24M
994 19:27:38.133796 Set clk81 to 24M
995 19:27:38.138566 A53 clk: 1200 MHz
996 19:27:38.139002 A73 clk: 1200 MHz
997 19:27:38.139410 CLK81: 166.6M
998 19:27:38.139810 smccc: 00012a92
999 19:27:38.144084 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 19:27:38.149773 board id: 1
1001 19:27:38.155663 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 19:27:38.166314 fw parse done
1003 19:27:38.172325 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 19:27:38.214834 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 19:27:38.225676 PIEI prepare done
1006 19:27:38.226111 fastboot data load
1007 19:27:38.226506 fastboot data verify
1008 19:27:38.231447 verify result: 266
1009 19:27:38.236943 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 19:27:38.237377 LPDDR4 probe
1011 19:27:38.237766 ddr clk to 1584MHz
1012 19:27:38.244944 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 19:27:38.282182
1014 19:27:38.282628 dmc_version 0001
1015 19:27:38.288842 Check phy result
1016 19:27:38.294782 INFO : End of CA training
1017 19:27:38.295205 INFO : End of initialization
1018 19:27:38.300295 INFO : Training has run successfully!
1019 19:27:38.300715 Check phy result
1020 19:27:38.305918 INFO : End of initialization
1021 19:27:38.306375 INFO : End of read enable training
1022 19:27:38.311557 INFO : End of fine write leveling
1023 19:27:38.317095 INFO : End of Write leveling coarse delay
1024 19:27:38.317554 INFO : Training has run successfully!
1025 19:27:38.317969 Check phy result
1026 19:27:38.322711 INFO : End of initialization
1027 19:27:38.323150 INFO : End of read dq deskew training
1028 19:27:38.328332 INFO : End of MPR read delay center optimization
1029 19:27:38.333931 INFO : End of write delay center optimization
1030 19:27:38.339571 INFO : End of read delay center optimization
1031 19:27:38.340038 INFO : End of max read latency training
1032 19:27:38.345112 INFO : Training has run successfully!
1033 19:27:38.345551 1D training succeed
1034 19:27:38.354386 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 19:27:38.402029 Check phy result
1036 19:27:38.402528 INFO : End of initialization
1037 19:27:38.423572 INFO : End of 2D read delay Voltage center optimization
1038 19:27:38.443648 INFO : End of 2D read delay Voltage center optimization
1039 19:27:38.495591 INFO : End of 2D write delay Voltage center optimization
1040 19:27:38.544880 INFO : End of 2D write delay Voltage center optimization
1041 19:27:38.550433 INFO : Training has run successfully!
1042 19:27:38.550885
1043 19:27:38.551300 channel==0
1044 19:27:38.555955 RxClkDly_Margin_A0==88 ps 9
1045 19:27:38.556433 TxDqDly_Margin_A0==98 ps 10
1046 19:27:38.561638 RxClkDly_Margin_A1==88 ps 9
1047 19:27:38.562088 TxDqDly_Margin_A1==98 ps 10
1048 19:27:38.562501 TrainedVREFDQ_A0==74
1049 19:27:38.567236 TrainedVREFDQ_A1==74
1050 19:27:38.567697 VrefDac_Margin_A0==25
1051 19:27:38.568137 DeviceVref_Margin_A0==40
1052 19:27:38.572803 VrefDac_Margin_A1==25
1053 19:27:38.573251 DeviceVref_Margin_A1==40
1054 19:27:38.573658
1055 19:27:38.574058
1056 19:27:38.578429 channel==1
1057 19:27:38.578876 RxClkDly_Margin_A0==98 ps 10
1058 19:27:38.579281 TxDqDly_Margin_A0==88 ps 9
1059 19:27:38.584010 RxClkDly_Margin_A1==88 ps 9
1060 19:27:38.584457 TxDqDly_Margin_A1==88 ps 9
1061 19:27:38.589503 TrainedVREFDQ_A0==77
1062 19:27:38.589942 TrainedVREFDQ_A1==77
1063 19:27:38.590348 VrefDac_Margin_A0==22
1064 19:27:38.595199 DeviceVref_Margin_A0==37
1065 19:27:38.595634 VrefDac_Margin_A1==24
1066 19:27:38.600806 DeviceVref_Margin_A1==37
1067 19:27:38.601246
1068 19:27:38.601653 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 19:27:38.602053
1070 19:27:38.634432 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1071 19:27:38.634941 2D training succeed
1072 19:27:38.640023 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 19:27:38.645475 auto size-- 65535DDR cs0 size: 2048MB
1074 19:27:38.645928 DDR cs1 size: 2048MB
1075 19:27:38.651080 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 19:27:38.651525 cs0 DataBus test pass
1077 19:27:38.656666 cs1 DataBus test pass
1078 19:27:38.657107 cs0 AddrBus test pass
1079 19:27:38.657512 cs1 AddrBus test pass
1080 19:27:38.657907
1081 19:27:38.662337 100bdlr_step_size ps== 420
1082 19:27:38.662788 result report
1083 19:27:38.667863 boot times 0Enable ddr reg access
1084 19:27:38.673134 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 19:27:38.686604 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 19:27:39.258745 0.0;M3 CHK:0;cm4_sp_mode 0
1087 19:27:39.259382 MVN_1=0x00000000
1088 19:27:39.264104 MVN_2=0x00000000
1089 19:27:39.269856 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 19:27:39.270316 OPS=0x10
1091 19:27:39.270734 ring efuse init
1092 19:27:39.271139 chipver efuse init
1093 19:27:39.275425 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 19:27:39.281143 [0.018961 Inits done]
1095 19:27:39.281607 secure task start!
1096 19:27:39.282022 high task start!
1097 19:27:39.285610 low task start!
1098 19:27:39.286057 run into bl31
1099 19:27:39.292379 NOTICE: BL31: v1.3(release):4fc40b1
1100 19:27:39.300110 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 19:27:39.300562 NOTICE: BL31: G12A normal boot!
1102 19:27:39.325964 NOTICE: BL31: BL33 decompress pass
1103 19:27:39.331656 ERROR: Error initializing runtime service opteed_fast
1104 19:27:40.565032
1105 19:27:40.565671
1106 19:27:40.573041 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 19:27:40.573534
1108 19:27:40.573955 Model: Libre Computer AML-A311D-CC Alta
1109 19:27:40.781517 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 19:27:40.804849 DRAM: 2 GiB (effective 3.8 GiB)
1111 19:27:40.948034 Core: 408 devices, 31 uclasses, devicetree: separate
1112 19:27:40.953744 WDT: Not starting watchdog@f0d0
1113 19:27:40.985939 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 19:27:40.998381 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 19:27:41.003371 ** Bad device specification mmc 0 **
1116 19:27:41.013694 Card did not respond to voltage select! : -110
1117 19:27:41.021447 ** Bad device specification mmc 0 **
1118 19:27:41.021921 Couldn't find partition mmc 0
1119 19:27:41.029702 Card did not respond to voltage select! : -110
1120 19:27:41.035229 ** Bad device specification mmc 0 **
1121 19:27:41.035701 Couldn't find partition mmc 0
1122 19:27:41.040709 Error: could not access storage.
1123 19:27:41.382839 Net: eth0: ethernet@ff3f0000
1124 19:27:41.383468 starting USB...
1125 19:27:41.634522 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 19:27:41.634951 Starting the controller
1127 19:27:41.641631 USB XHCI 1.10
1128 19:27:43.197756 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 19:27:43.206071 scanning usb for storage devices... 0 Storage Device(s) found
1131 19:27:43.257677 Hit any key to stop autoboot: 1
1132 19:27:43.258551 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1133 19:27:43.259192 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1134 19:27:43.259664 Setting prompt string to ['=>']
1135 19:27:43.260198 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1136 19:27:43.273462 0
1137 19:27:43.274347 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 19:27:43.274831 Sending with 10 millisecond of delay
1140 19:27:44.409490 => setenv autoload no
1141 19:27:44.420313 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1142 19:27:44.425260 setenv autoload no
1143 19:27:44.425997 Sending with 10 millisecond of delay
1145 19:27:46.222893 => setenv initrd_high 0xffffffff
1146 19:27:46.233683 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1147 19:27:46.234518 setenv initrd_high 0xffffffff
1148 19:27:46.235224 Sending with 10 millisecond of delay
1150 19:27:47.851414 => setenv fdt_high 0xffffffff
1151 19:27:47.862229 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1152 19:27:47.863050 setenv fdt_high 0xffffffff
1153 19:27:47.863762 Sending with 10 millisecond of delay
1155 19:27:48.155590 => dhcp
1156 19:27:48.166390 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1157 19:27:48.167206 dhcp
1158 19:27:48.167662 Speed: 1000, full duplex
1159 19:27:48.168118 BOOTP broadcast 1
1160 19:27:48.179144 DHCP client bound to address 192.168.6.27 (12 ms)
1161 19:27:48.179870 Sending with 10 millisecond of delay
1163 19:27:49.856309 => setenv serverip 192.168.6.2
1164 19:27:49.870226 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1165 19:27:49.871206 setenv serverip 192.168.6.2
1166 19:27:49.871907 Sending with 10 millisecond of delay
1168 19:27:53.594669 => tftpboot 0x01080000 954125/tftp-deploy-l2_6helz/kernel/uImage
1169 19:27:53.605463 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1170 19:27:53.606274 tftpboot 0x01080000 954125/tftp-deploy-l2_6helz/kernel/uImage
1171 19:27:53.606720 Speed: 1000, full duplex
1172 19:27:53.607140 Using ethernet@ff3f0000 device
1173 19:27:53.608231 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1174 19:27:53.613748 Filename '954125/tftp-deploy-l2_6helz/kernel/uImage'.
1175 19:27:53.617605 Load address: 0x1080000
1176 19:27:56.403435 Loading: *################################################## 43.6 MiB
1177 19:27:56.404121 15.6 MiB/s
1178 19:27:56.404562 done
1179 19:27:56.407778 Bytes transferred = 45713984 (2b98a40 hex)
1180 19:27:56.408613 Sending with 10 millisecond of delay
1182 19:28:01.097818 => tftpboot 0x08000000 954125/tftp-deploy-l2_6helz/ramdisk/ramdisk.cpio.gz.uboot
1183 19:28:01.108622 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1184 19:28:01.109428 tftpboot 0x08000000 954125/tftp-deploy-l2_6helz/ramdisk/ramdisk.cpio.gz.uboot
1185 19:28:01.109874 Speed: 1000, full duplex
1186 19:28:01.110290 Using ethernet@ff3f0000 device
1187 19:28:01.111352 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1188 19:28:01.123204 Filename '954125/tftp-deploy-l2_6helz/ramdisk/ramdisk.cpio.gz.uboot'.
1189 19:28:01.123672 Load address: 0x8000000
1190 19:28:08.158459 Loading: *####################T ############################# UDP wrong checksum 00000005 000093e2
1191 19:28:13.158955 T UDP wrong checksum 00000005 000093e2
1192 19:28:23.160969 T T UDP wrong checksum 00000005 000093e2
1193 19:28:31.790738 T UDP wrong checksum 000000ff 00004b27
1194 19:28:31.988801 UDP wrong checksum 000000ff 0000db19
1195 19:28:43.165893 T T T UDP wrong checksum 00000005 000093e2
1196 19:28:58.169930 T T
1197 19:28:58.170858 Retry count exceeded; starting again
1199 19:28:58.172813 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1202 19:28:58.175319 end: 2.4 uboot-commands (duration 00:01:53) [common]
1204 19:28:58.177243 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1206 19:28:58.178593 end: 2 uboot-action (duration 00:01:53) [common]
1208 19:28:58.180592 Cleaning after the job
1209 19:28:58.181281 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/ramdisk
1210 19:28:58.182894 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/kernel
1211 19:28:58.216831 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/dtb
1212 19:28:58.218843 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/nfsrootfs
1213 19:28:58.251123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954125/tftp-deploy-l2_6helz/modules
1214 19:28:58.258212 start: 4.1 power-off (timeout 00:00:30) [common]
1215 19:28:58.258848 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1216 19:28:58.292903 >> OK - accepted request
1217 19:28:58.295131 Returned 0 in 0 seconds
1218 19:28:58.396200 end: 4.1 power-off (duration 00:00:00) [common]
1220 19:28:58.397831 start: 4.2 read-feedback (timeout 00:10:00) [common]
1221 19:28:58.399010 Listened to connection for namespace 'common' for up to 1s
1222 19:28:59.399834 Finalising connection for namespace 'common'
1223 19:28:59.400651 Disconnecting from shell: Finalise
1224 19:28:59.401152 =>
1225 19:28:59.502261 end: 4.2 read-feedback (duration 00:00:01) [common]
1226 19:28:59.503023 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/954125
1227 19:29:02.304017 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/954125
1228 19:29:02.304627 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.