Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 19:16:04.891534 lava-dispatcher, installed at version: 2024.01
2 19:16:04.892367 start: 0 validate
3 19:16:04.892844 Start time: 2024-11-07 19:16:04.892815+00:00 (UTC)
4 19:16:04.893385 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:16:04.893927 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:16:04.934300 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:16:04.934862 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 19:16:04.978118 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:16:04.978799 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 19:16:05.015148 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:16:05.015673 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:16:05.055138 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 19:16:05.055709 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-241-gd613d4c396116%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 19:16:05.098173 validate duration: 0.21
16 19:16:05.099743 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:16:05.100277 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:16:05.100640 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:16:05.101468 Not decompressing ramdisk as can be used compressed.
20 19:16:05.101966 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 19:16:05.102255 saving as /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/ramdisk/initrd.cpio.gz
22 19:16:05.102527 total size: 5628140 (5 MB)
23 19:16:05.144070 progress 0 % (0 MB)
24 19:16:05.151744 progress 5 % (0 MB)
25 19:16:05.159972 progress 10 % (0 MB)
26 19:16:05.165686 progress 15 % (0 MB)
27 19:16:05.169894 progress 20 % (1 MB)
28 19:16:05.173699 progress 25 % (1 MB)
29 19:16:05.177767 progress 30 % (1 MB)
30 19:16:05.181988 progress 35 % (1 MB)
31 19:16:05.185693 progress 40 % (2 MB)
32 19:16:05.189664 progress 45 % (2 MB)
33 19:16:05.193296 progress 50 % (2 MB)
34 19:16:05.197388 progress 55 % (2 MB)
35 19:16:05.201420 progress 60 % (3 MB)
36 19:16:05.205042 progress 65 % (3 MB)
37 19:16:05.209106 progress 70 % (3 MB)
38 19:16:05.212720 progress 75 % (4 MB)
39 19:16:05.216775 progress 80 % (4 MB)
40 19:16:05.220353 progress 85 % (4 MB)
41 19:16:05.224486 progress 90 % (4 MB)
42 19:16:05.228324 progress 95 % (5 MB)
43 19:16:05.231602 progress 100 % (5 MB)
44 19:16:05.232356 5 MB downloaded in 0.13 s (41.35 MB/s)
45 19:16:05.232932 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:16:05.233864 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:16:05.234182 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:16:05.234473 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:16:05.234986 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm64/defconfig/gcc-12/kernel/Image
51 19:16:05.235298 saving as /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/kernel/Image
52 19:16:05.235523 total size: 45713920 (43 MB)
53 19:16:05.235747 No compression specified
54 19:16:05.268829 progress 0 % (0 MB)
55 19:16:05.297967 progress 5 % (2 MB)
56 19:16:05.327240 progress 10 % (4 MB)
57 19:16:05.356064 progress 15 % (6 MB)
58 19:16:05.385529 progress 20 % (8 MB)
59 19:16:05.413987 progress 25 % (10 MB)
60 19:16:05.442872 progress 30 % (13 MB)
61 19:16:05.471659 progress 35 % (15 MB)
62 19:16:05.500420 progress 40 % (17 MB)
63 19:16:05.529267 progress 45 % (19 MB)
64 19:16:05.558182 progress 50 % (21 MB)
65 19:16:05.587293 progress 55 % (24 MB)
66 19:16:05.616259 progress 60 % (26 MB)
67 19:16:05.644960 progress 65 % (28 MB)
68 19:16:05.674426 progress 70 % (30 MB)
69 19:16:05.703083 progress 75 % (32 MB)
70 19:16:05.732547 progress 80 % (34 MB)
71 19:16:05.761306 progress 85 % (37 MB)
72 19:16:05.790223 progress 90 % (39 MB)
73 19:16:05.819345 progress 95 % (41 MB)
74 19:16:05.847478 progress 100 % (43 MB)
75 19:16:05.848022 43 MB downloaded in 0.61 s (71.18 MB/s)
76 19:16:05.848499 end: 1.2.1 http-download (duration 00:00:01) [common]
78 19:16:05.849319 end: 1.2 download-retry (duration 00:00:01) [common]
79 19:16:05.849595 start: 1.3 download-retry (timeout 00:09:59) [common]
80 19:16:05.849859 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 19:16:05.850324 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 19:16:05.850594 saving as /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/dtb/meson-g12b-a311d-libretech-cc.dtb
83 19:16:05.850803 total size: 54703 (0 MB)
84 19:16:05.851010 No compression specified
85 19:16:05.888993 progress 59 % (0 MB)
86 19:16:05.889844 progress 100 % (0 MB)
87 19:16:05.890398 0 MB downloaded in 0.04 s (1.32 MB/s)
88 19:16:05.890855 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:16:05.891664 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:16:05.891925 start: 1.4 download-retry (timeout 00:09:59) [common]
92 19:16:05.892228 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 19:16:05.892695 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 19:16:05.892934 saving as /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/nfsrootfs/full.rootfs.tar
95 19:16:05.893138 total size: 474398908 (452 MB)
96 19:16:05.893348 Using unxz to decompress xz
97 19:16:05.932082 progress 0 % (0 MB)
98 19:16:07.037580 progress 5 % (22 MB)
99 19:16:08.533854 progress 10 % (45 MB)
100 19:16:08.989660 progress 15 % (67 MB)
101 19:16:09.803539 progress 20 % (90 MB)
102 19:16:10.361915 progress 25 % (113 MB)
103 19:16:10.762330 progress 30 % (135 MB)
104 19:16:11.395167 progress 35 % (158 MB)
105 19:16:12.318472 progress 40 % (181 MB)
106 19:16:13.093411 progress 45 % (203 MB)
107 19:16:13.712134 progress 50 % (226 MB)
108 19:16:14.353013 progress 55 % (248 MB)
109 19:16:15.574669 progress 60 % (271 MB)
110 19:16:17.129206 progress 65 % (294 MB)
111 19:16:18.751910 progress 70 % (316 MB)
112 19:16:21.942236 progress 75 % (339 MB)
113 19:16:24.529340 progress 80 % (361 MB)
114 19:16:27.579816 progress 85 % (384 MB)
115 19:16:31.144507 progress 90 % (407 MB)
116 19:16:34.737632 progress 95 % (429 MB)
117 19:16:38.385022 progress 100 % (452 MB)
118 19:16:38.402106 452 MB downloaded in 32.51 s (13.92 MB/s)
119 19:16:38.402994 end: 1.4.1 http-download (duration 00:00:33) [common]
121 19:16:38.404678 end: 1.4 download-retry (duration 00:00:33) [common]
122 19:16:38.405208 start: 1.5 download-retry (timeout 00:09:27) [common]
123 19:16:38.405730 start: 1.5.1 http-download (timeout 00:09:27) [common]
124 19:16:38.406538 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-241-gd613d4c396116/arm64/defconfig/gcc-12/modules.tar.xz
125 19:16:38.407005 saving as /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/modules/modules.tar
126 19:16:38.407421 total size: 11613380 (11 MB)
127 19:16:38.407842 Using unxz to decompress xz
128 19:16:38.459385 progress 0 % (0 MB)
129 19:16:38.538701 progress 5 % (0 MB)
130 19:16:38.627451 progress 10 % (1 MB)
131 19:16:38.751018 progress 15 % (1 MB)
132 19:16:38.859346 progress 20 % (2 MB)
133 19:16:38.952147 progress 25 % (2 MB)
134 19:16:39.034375 progress 30 % (3 MB)
135 19:16:39.133834 progress 35 % (3 MB)
136 19:16:39.212307 progress 40 % (4 MB)
137 19:16:39.290535 progress 45 % (5 MB)
138 19:16:39.376657 progress 50 % (5 MB)
139 19:16:39.455472 progress 55 % (6 MB)
140 19:16:39.542176 progress 60 % (6 MB)
141 19:16:39.625323 progress 65 % (7 MB)
142 19:16:39.707906 progress 70 % (7 MB)
143 19:16:39.786975 progress 75 % (8 MB)
144 19:16:39.871611 progress 80 % (8 MB)
145 19:16:39.953251 progress 85 % (9 MB)
146 19:16:40.033149 progress 90 % (9 MB)
147 19:16:40.112022 progress 95 % (10 MB)
148 19:16:40.189604 progress 100 % (11 MB)
149 19:16:40.202523 11 MB downloaded in 1.80 s (6.17 MB/s)
150 19:16:40.203146 end: 1.5.1 http-download (duration 00:00:02) [common]
152 19:16:40.204045 end: 1.5 download-retry (duration 00:00:02) [common]
153 19:16:40.204640 start: 1.6 prepare-tftp-overlay (timeout 00:09:25) [common]
154 19:16:40.205219 start: 1.6.1 extract-nfsrootfs (timeout 00:09:25) [common]
155 19:16:56.047879 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/954124/extract-nfsrootfs-se5onpva
156 19:16:56.048508 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 19:16:56.048792 start: 1.6.2 lava-overlay (timeout 00:09:09) [common]
158 19:16:56.049516 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh
159 19:16:56.049958 makedir: /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin
160 19:16:56.050280 makedir: /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/tests
161 19:16:56.050588 makedir: /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/results
162 19:16:56.050917 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-add-keys
163 19:16:56.051436 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-add-sources
164 19:16:56.051927 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-background-process-start
165 19:16:56.052447 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-background-process-stop
166 19:16:56.053029 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-common-functions
167 19:16:56.053547 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-echo-ipv4
168 19:16:56.054031 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-install-packages
169 19:16:56.054570 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-installed-packages
170 19:16:56.055115 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-os-build
171 19:16:56.055665 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-probe-channel
172 19:16:56.056189 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-probe-ip
173 19:16:56.056665 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-target-ip
174 19:16:56.057125 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-target-mac
175 19:16:56.057588 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-target-storage
176 19:16:56.058060 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-test-case
177 19:16:56.058525 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-test-event
178 19:16:56.059016 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-test-feedback
179 19:16:56.059522 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-test-raise
180 19:16:56.060002 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-test-reference
181 19:16:56.060501 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-test-runner
182 19:16:56.060981 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-test-set
183 19:16:56.061444 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-test-shell
184 19:16:56.061941 Updating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-install-packages (oe)
185 19:16:56.062469 Updating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/bin/lava-installed-packages (oe)
186 19:16:56.062897 Creating /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/environment
187 19:16:56.063257 LAVA metadata
188 19:16:56.063517 - LAVA_JOB_ID=954124
189 19:16:56.063733 - LAVA_DISPATCHER_IP=192.168.6.2
190 19:16:56.064107 start: 1.6.2.1 ssh-authorize (timeout 00:09:09) [common]
191 19:16:56.065076 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 19:16:56.065390 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:09) [common]
193 19:16:56.065594 skipped lava-vland-overlay
194 19:16:56.065834 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 19:16:56.066087 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:09) [common]
196 19:16:56.066305 skipped lava-multinode-overlay
197 19:16:56.066547 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 19:16:56.066798 start: 1.6.2.4 test-definition (timeout 00:09:09) [common]
199 19:16:56.067047 Loading test definitions
200 19:16:56.067323 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:09) [common]
201 19:16:56.067546 Using /lava-954124 at stage 0
202 19:16:56.068706 uuid=954124_1.6.2.4.1 testdef=None
203 19:16:56.069010 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 19:16:56.069272 start: 1.6.2.4.2 test-overlay (timeout 00:09:09) [common]
205 19:16:56.070960 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 19:16:56.071746 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:09) [common]
208 19:16:56.073950 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 19:16:56.074783 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:09) [common]
211 19:16:56.076889 runner path: /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 954124_1.6.2.4.1
212 19:16:56.077427 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 19:16:56.078177 Creating lava-test-runner.conf files
215 19:16:56.078378 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/954124/lava-overlay-9it7yvfh/lava-954124/0 for stage 0
216 19:16:56.078702 - 0_v4l2-decoder-conformance-vp9
217 19:16:56.079035 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 19:16:56.079304 start: 1.6.2.5 compress-overlay (timeout 00:09:09) [common]
219 19:16:56.100352 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 19:16:56.100710 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:09) [common]
221 19:16:56.100965 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 19:16:56.101227 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 19:16:56.101487 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:09) [common]
224 19:16:56.732720 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 19:16:56.733177 start: 1.6.4 extract-modules (timeout 00:09:08) [common]
226 19:16:56.733425 extracting modules file /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954124/extract-nfsrootfs-se5onpva
227 19:16:58.069626 extracting modules file /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954124/extract-overlay-ramdisk-rls59r7r/ramdisk
228 19:16:59.448749 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 19:16:59.449239 start: 1.6.5 apply-overlay-tftp (timeout 00:09:06) [common]
230 19:16:59.449514 [common] Applying overlay to NFS
231 19:16:59.449726 [common] Applying overlay /var/lib/lava/dispatcher/tmp/954124/compress-overlay-afqzims5/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/954124/extract-nfsrootfs-se5onpva
232 19:16:59.478930 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 19:16:59.479320 start: 1.6.6 prepare-kernel (timeout 00:09:06) [common]
234 19:16:59.479588 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:06) [common]
235 19:16:59.479814 Converting downloaded kernel to a uImage
236 19:16:59.480158 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/kernel/Image /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/kernel/uImage
237 19:16:59.992607 output: Image Name:
238 19:16:59.993031 output: Created: Thu Nov 7 19:16:59 2024
239 19:16:59.993242 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 19:16:59.993447 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 19:16:59.993650 output: Load Address: 01080000
242 19:16:59.993849 output: Entry Point: 01080000
243 19:16:59.994048 output:
244 19:16:59.994383 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 19:16:59.994648 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 19:16:59.994913 start: 1.6.7 configure-preseed-file (timeout 00:09:05) [common]
247 19:16:59.995166 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 19:16:59.995422 start: 1.6.8 compress-ramdisk (timeout 00:09:05) [common]
249 19:16:59.995676 Building ramdisk /var/lib/lava/dispatcher/tmp/954124/extract-overlay-ramdisk-rls59r7r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/954124/extract-overlay-ramdisk-rls59r7r/ramdisk
250 19:17:02.156988 >> 166792 blocks
251 19:17:09.951181 Adding RAMdisk u-boot header.
252 19:17:09.951635 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/954124/extract-overlay-ramdisk-rls59r7r/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/954124/extract-overlay-ramdisk-rls59r7r/ramdisk.cpio.gz.uboot
253 19:17:10.223320 output: Image Name:
254 19:17:10.223941 output: Created: Thu Nov 7 19:17:09 2024
255 19:17:10.224426 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 19:17:10.224850 output: Data Size: 23433119 Bytes = 22883.91 KiB = 22.35 MiB
257 19:17:10.225259 output: Load Address: 00000000
258 19:17:10.225665 output: Entry Point: 00000000
259 19:17:10.226068 output:
260 19:17:10.227061 rename /var/lib/lava/dispatcher/tmp/954124/extract-overlay-ramdisk-rls59r7r/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/ramdisk/ramdisk.cpio.gz.uboot
261 19:17:10.227782 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 19:17:10.228405 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 19:17:10.228993 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:55) [common]
264 19:17:10.229465 No LXC device requested
265 19:17:10.229987 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 19:17:10.230517 start: 1.8 deploy-device-env (timeout 00:08:55) [common]
267 19:17:10.231032 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 19:17:10.231457 Checking files for TFTP limit of 4294967296 bytes.
269 19:17:10.234207 end: 1 tftp-deploy (duration 00:01:05) [common]
270 19:17:10.234811 start: 2 uboot-action (timeout 00:05:00) [common]
271 19:17:10.235352 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 19:17:10.235861 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 19:17:10.236428 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 19:17:10.236974 Using kernel file from prepare-kernel: 954124/tftp-deploy-4aercd_m/kernel/uImage
275 19:17:10.237625 substitutions:
276 19:17:10.238041 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 19:17:10.238452 - {DTB_ADDR}: 0x01070000
278 19:17:10.238854 - {DTB}: 954124/tftp-deploy-4aercd_m/dtb/meson-g12b-a311d-libretech-cc.dtb
279 19:17:10.239255 - {INITRD}: 954124/tftp-deploy-4aercd_m/ramdisk/ramdisk.cpio.gz.uboot
280 19:17:10.239657 - {KERNEL_ADDR}: 0x01080000
281 19:17:10.240079 - {KERNEL}: 954124/tftp-deploy-4aercd_m/kernel/uImage
282 19:17:10.240483 - {LAVA_MAC}: None
283 19:17:10.240921 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/954124/extract-nfsrootfs-se5onpva
284 19:17:10.241324 - {NFS_SERVER_IP}: 192.168.6.2
285 19:17:10.241719 - {PRESEED_CONFIG}: None
286 19:17:10.242113 - {PRESEED_LOCAL}: None
287 19:17:10.242505 - {RAMDISK_ADDR}: 0x08000000
288 19:17:10.242896 - {RAMDISK}: 954124/tftp-deploy-4aercd_m/ramdisk/ramdisk.cpio.gz.uboot
289 19:17:10.243286 - {ROOT_PART}: None
290 19:17:10.243675 - {ROOT}: None
291 19:17:10.244090 - {SERVER_IP}: 192.168.6.2
292 19:17:10.244493 - {TEE_ADDR}: 0x83000000
293 19:17:10.244892 - {TEE}: None
294 19:17:10.245288 Parsed boot commands:
295 19:17:10.245673 - setenv autoload no
296 19:17:10.246067 - setenv initrd_high 0xffffffff
297 19:17:10.246459 - setenv fdt_high 0xffffffff
298 19:17:10.246847 - dhcp
299 19:17:10.247237 - setenv serverip 192.168.6.2
300 19:17:10.247624 - tftpboot 0x01080000 954124/tftp-deploy-4aercd_m/kernel/uImage
301 19:17:10.248039 - tftpboot 0x08000000 954124/tftp-deploy-4aercd_m/ramdisk/ramdisk.cpio.gz.uboot
302 19:17:10.248437 - tftpboot 0x01070000 954124/tftp-deploy-4aercd_m/dtb/meson-g12b-a311d-libretech-cc.dtb
303 19:17:10.248829 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/954124/extract-nfsrootfs-se5onpva,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 19:17:10.249234 - bootm 0x01080000 0x08000000 0x01070000
305 19:17:10.249747 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 19:17:10.251241 start: 2.3 connect-device (timeout 00:05:00) [common]
308 19:17:10.251666 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 19:17:10.266719 Setting prompt string to ['lava-test: # ']
310 19:17:10.268264 end: 2.3 connect-device (duration 00:00:00) [common]
311 19:17:10.268898 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 19:17:10.269466 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 19:17:10.270012 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 19:17:10.271140 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 19:17:10.309114 >> OK - accepted request
316 19:17:10.310801 Returned 0 in 0 seconds
317 19:17:10.411900 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 19:17:10.413617 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 19:17:10.414221 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 19:17:10.414762 Setting prompt string to ['Hit any key to stop autoboot']
322 19:17:10.415250 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 19:17:10.416883 Trying 192.168.56.21...
324 19:17:10.417381 Connected to conserv1.
325 19:17:10.417813 Escape character is '^]'.
326 19:17:10.418238
327 19:17:10.418673 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 19:17:10.419090
329 19:17:22.501239 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 19:17:22.501685 bl2_stage_init 0x01
331 19:17:22.501922 bl2_stage_init 0x81
332 19:17:22.506830 hw id: 0x0000 - pwm id 0x01
333 19:17:22.507177 bl2_stage_init 0xc1
334 19:17:22.507401 bl2_stage_init 0x02
335 19:17:22.507614
336 19:17:22.512357 L0:00000000
337 19:17:22.512664 L1:20000703
338 19:17:22.512885 L2:00008067
339 19:17:22.513095 L3:14000000
340 19:17:22.515242 B2:00402000
341 19:17:22.515525 B1:e0f83180
342 19:17:22.515749
343 19:17:22.515962 TE: 58124
344 19:17:22.516225
345 19:17:22.526423 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 19:17:22.526769
347 19:17:22.526996 Board ID = 1
348 19:17:22.527210 Set A53 clk to 24M
349 19:17:22.527422 Set A73 clk to 24M
350 19:17:22.531929 Set clk81 to 24M
351 19:17:22.532257 A53 clk: 1200 MHz
352 19:17:22.532480 A73 clk: 1200 MHz
353 19:17:22.537509 CLK81: 166.6M
354 19:17:22.537819 smccc: 00012a92
355 19:17:22.543116 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 19:17:22.543415 board id: 1
357 19:17:22.551657 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 19:17:22.562293 fw parse done
359 19:17:22.568316 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 19:17:22.610958 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 19:17:22.621836 PIEI prepare done
362 19:17:22.622185 fastboot data load
363 19:17:22.622414 fastboot data verify
364 19:17:22.627653 verify result: 266
365 19:17:22.633091 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 19:17:22.633417 LPDDR4 probe
367 19:17:22.633643 ddr clk to 1584MHz
368 19:17:22.641050 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 19:17:22.678333
370 19:17:22.678690 dmc_version 0001
371 19:17:22.684973 Check phy result
372 19:17:22.690846 INFO : End of CA training
373 19:17:22.691166 INFO : End of initialization
374 19:17:22.696416 INFO : Training has run successfully!
375 19:17:22.696716 Check phy result
376 19:17:22.702029 INFO : End of initialization
377 19:17:22.702334 INFO : End of read enable training
378 19:17:22.705315 INFO : End of fine write leveling
379 19:17:22.710891 INFO : End of Write leveling coarse delay
380 19:17:22.716543 INFO : Training has run successfully!
381 19:17:22.716841 Check phy result
382 19:17:22.717064 INFO : End of initialization
383 19:17:22.722052 INFO : End of read dq deskew training
384 19:17:22.727641 INFO : End of MPR read delay center optimization
385 19:17:22.727946 INFO : End of write delay center optimization
386 19:17:22.733338 INFO : End of read delay center optimization
387 19:17:22.738881 INFO : End of max read latency training
388 19:17:22.739196 INFO : Training has run successfully!
389 19:17:22.744536 1D training succeed
390 19:17:22.750433 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 19:17:22.798030 Check phy result
392 19:17:22.798426 INFO : End of initialization
393 19:17:22.819755 INFO : End of 2D read delay Voltage center optimization
394 19:17:22.840098 INFO : End of 2D read delay Voltage center optimization
395 19:17:22.892147 INFO : End of 2D write delay Voltage center optimization
396 19:17:22.941506 INFO : End of 2D write delay Voltage center optimization
397 19:17:22.947010 INFO : Training has run successfully!
398 19:17:22.947557
399 19:17:22.948074 channel==0
400 19:17:22.952690 RxClkDly_Margin_A0==88 ps 9
401 19:17:22.953235 TxDqDly_Margin_A0==98 ps 10
402 19:17:22.956115 RxClkDly_Margin_A1==88 ps 9
403 19:17:22.956697 TxDqDly_Margin_A1==88 ps 9
404 19:17:22.961676 TrainedVREFDQ_A0==74
405 19:17:22.962166 TrainedVREFDQ_A1==74
406 19:17:22.962612 VrefDac_Margin_A0==25
407 19:17:22.967107 DeviceVref_Margin_A0==40
408 19:17:22.967582 VrefDac_Margin_A1==25
409 19:17:22.972648 DeviceVref_Margin_A1==40
410 19:17:22.973111
411 19:17:22.973550
412 19:17:22.973984 channel==1
413 19:17:22.974418 RxClkDly_Margin_A0==98 ps 10
414 19:17:22.976209 TxDqDly_Margin_A0==98 ps 10
415 19:17:22.981842 RxClkDly_Margin_A1==98 ps 10
416 19:17:22.982324 TxDqDly_Margin_A1==88 ps 9
417 19:17:22.982766 TrainedVREFDQ_A0==77
418 19:17:22.988839 TrainedVREFDQ_A1==77
419 19:17:22.989456 VrefDac_Margin_A0==22
420 19:17:22.989907 DeviceVref_Margin_A0==37
421 19:17:22.994650 VrefDac_Margin_A1==22
422 19:17:22.995148 DeviceVref_Margin_A1==37
423 19:17:22.995587
424 19:17:23.000060 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 19:17:23.000568
426 19:17:23.027538 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
427 19:17:23.033133 2D training succeed
428 19:17:23.038701 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 19:17:23.044132 auto size-- 65535DDR cs0 size: 2048MB
430 19:17:23.044627 DDR cs1 size: 2048MB
431 19:17:23.049742 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 19:17:23.050234 cs0 DataBus test pass
433 19:17:23.050676 cs1 DataBus test pass
434 19:17:23.055353 cs0 AddrBus test pass
435 19:17:23.055867 cs1 AddrBus test pass
436 19:17:23.056372
437 19:17:23.056815 100bdlr_step_size ps== 420
438 19:17:23.060935 result report
439 19:17:23.061413 boot times 0Enable ddr reg access
440 19:17:23.069892 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 19:17:23.083406 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 19:17:23.657087 0.0;M3 CHK:0;cm4_sp_mode 0
443 19:17:23.657767 MVN_1=0x00000000
444 19:17:23.662565 MVN_2=0x00000000
445 19:17:23.668296 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 19:17:23.668785 OPS=0x10
447 19:17:23.669244 ring efuse init
448 19:17:23.669693 chipver efuse init
449 19:17:23.673804 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 19:17:23.679531 [0.018960 Inits done]
451 19:17:23.679822 secure task start!
452 19:17:23.680109 high task start!
453 19:17:23.684026 low task start!
454 19:17:23.684319 run into bl31
455 19:17:23.690721 NOTICE: BL31: v1.3(release):4fc40b1
456 19:17:23.698644 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 19:17:23.699004 NOTICE: BL31: G12A normal boot!
458 19:17:23.723831 NOTICE: BL31: BL33 decompress pass
459 19:17:23.729493 ERROR: Error initializing runtime service opteed_fast
460 19:17:24.962340
461 19:17:24.962806
462 19:17:24.970877 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 19:17:24.971285
464 19:17:24.971531 Model: Libre Computer AML-A311D-CC Alta
465 19:17:25.179333 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 19:17:25.202723 DRAM: 2 GiB (effective 3.8 GiB)
467 19:17:25.345675 Core: 408 devices, 31 uclasses, devicetree: separate
468 19:17:25.351484 WDT: Not starting watchdog@f0d0
469 19:17:25.383805 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 19:17:25.396212 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 19:17:25.401243 ** Bad device specification mmc 0 **
472 19:17:25.411663 Card did not respond to voltage select! : -110
473 19:17:25.419168 ** Bad device specification mmc 0 **
474 19:17:25.419675 Couldn't find partition mmc 0
475 19:17:25.427502 Card did not respond to voltage select! : -110
476 19:17:25.432993 ** Bad device specification mmc 0 **
477 19:17:25.433475 Couldn't find partition mmc 0
478 19:17:25.438097 Error: could not access storage.
479 19:17:26.692904 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 19:17:26.693595 bl2_stage_init 0x01
481 19:17:26.694096 bl2_stage_init 0x81
482 19:17:26.698452 hw id: 0x0000 - pwm id 0x01
483 19:17:26.698974 bl2_stage_init 0xc1
484 19:17:26.699465 bl2_stage_init 0x02
485 19:17:26.699941
486 19:17:26.704062 L0:00000000
487 19:17:26.704562 L1:20000703
488 19:17:26.705041 L2:00008067
489 19:17:26.705514 L3:14000000
490 19:17:26.709625 B2:00402000
491 19:17:26.710078 B1:e0f83180
492 19:17:26.710549
493 19:17:26.711036 TE: 58124
494 19:17:26.711505
495 19:17:26.715167 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 19:17:26.715610
497 19:17:26.716116 Board ID = 1
498 19:17:26.720775 Set A53 clk to 24M
499 19:17:26.721271 Set A73 clk to 24M
500 19:17:26.721759 Set clk81 to 24M
501 19:17:26.726392 A53 clk: 1200 MHz
502 19:17:26.726895 A73 clk: 1200 MHz
503 19:17:26.727375 CLK81: 166.6M
504 19:17:26.727850 smccc: 00012a91
505 19:17:26.732039 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 19:17:26.737640 board id: 1
507 19:17:26.743474 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 19:17:26.754147 fw parse done
509 19:17:26.760165 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 19:17:26.802784 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 19:17:26.813666 PIEI prepare done
512 19:17:26.814286 fastboot data load
513 19:17:26.814780 fastboot data verify
514 19:17:26.819296 verify result: 266
515 19:17:26.824916 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 19:17:26.825477 LPDDR4 probe
517 19:17:26.825905 ddr clk to 1584MHz
518 19:17:26.832926 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 19:17:26.870282
520 19:17:26.870877 dmc_version 0001
521 19:17:26.876867 Check phy result
522 19:17:26.882775 INFO : End of CA training
523 19:17:26.883690 INFO : End of initialization
524 19:17:26.888319 INFO : Training has run successfully!
525 19:17:26.889180 Check phy result
526 19:17:26.893858 INFO : End of initialization
527 19:17:26.894805 INFO : End of read enable training
528 19:17:26.899524 INFO : End of fine write leveling
529 19:17:26.905179 INFO : End of Write leveling coarse delay
530 19:17:26.906119 INFO : Training has run successfully!
531 19:17:26.906906 Check phy result
532 19:17:26.910760 INFO : End of initialization
533 19:17:26.911656 INFO : End of read dq deskew training
534 19:17:26.916321 INFO : End of MPR read delay center optimization
535 19:17:26.921885 INFO : End of write delay center optimization
536 19:17:26.927538 INFO : End of read delay center optimization
537 19:17:26.928498 INFO : End of max read latency training
538 19:17:26.933168 INFO : Training has run successfully!
539 19:17:26.934050 1D training succeed
540 19:17:26.942296 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 19:17:26.989992 Check phy result
542 19:17:26.990674 INFO : End of initialization
543 19:17:27.011641 INFO : End of 2D read delay Voltage center optimization
544 19:17:27.031849 INFO : End of 2D read delay Voltage center optimization
545 19:17:27.083823 INFO : End of 2D write delay Voltage center optimization
546 19:17:27.133217 INFO : End of 2D write delay Voltage center optimization
547 19:17:27.138780 INFO : Training has run successfully!
548 19:17:27.139064
549 19:17:27.139325 channel==0
550 19:17:27.144367 RxClkDly_Margin_A0==88 ps 9
551 19:17:27.144669 TxDqDly_Margin_A0==98 ps 10
552 19:17:27.149961 RxClkDly_Margin_A1==88 ps 9
553 19:17:27.150276 TxDqDly_Margin_A1==98 ps 10
554 19:17:27.150511 TrainedVREFDQ_A0==74
555 19:17:27.155507 TrainedVREFDQ_A1==74
556 19:17:27.155821 VrefDac_Margin_A0==25
557 19:17:27.156107 DeviceVref_Margin_A0==40
558 19:17:27.161129 VrefDac_Margin_A1==25
559 19:17:27.161386 DeviceVref_Margin_A1==40
560 19:17:27.161650
561 19:17:27.161867
562 19:17:27.166719 channel==1
563 19:17:27.167017 RxClkDly_Margin_A0==98 ps 10
564 19:17:27.167265 TxDqDly_Margin_A0==98 ps 10
565 19:17:27.172332 RxClkDly_Margin_A1==88 ps 9
566 19:17:27.172590 TxDqDly_Margin_A1==88 ps 9
567 19:17:27.177949 TrainedVREFDQ_A0==77
568 19:17:27.178198 TrainedVREFDQ_A1==77
569 19:17:27.178412 VrefDac_Margin_A0==22
570 19:17:27.183555 DeviceVref_Margin_A0==37
571 19:17:27.183929 VrefDac_Margin_A1==24
572 19:17:27.189122 DeviceVref_Margin_A1==37
573 19:17:27.189493
574 19:17:27.189807 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 19:17:27.190093
576 19:17:27.222756 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 19:17:27.223081 2D training succeed
578 19:17:27.228377 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 19:17:27.234016 auto size-- 65535DDR cs0 size: 2048MB
580 19:17:27.234375 DDR cs1 size: 2048MB
581 19:17:27.239733 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 19:17:27.240089 cs0 DataBus test pass
583 19:17:27.245195 cs1 DataBus test pass
584 19:17:27.245484 cs0 AddrBus test pass
585 19:17:27.245706 cs1 AddrBus test pass
586 19:17:27.245921
587 19:17:27.250785 100bdlr_step_size ps== 420
588 19:17:27.251098 result report
589 19:17:27.256451 boot times 0Enable ddr reg access
590 19:17:27.261775 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 19:17:27.275277 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 19:17:27.849011 0.0;M3 CHK:0;cm4_sp_mode 0
593 19:17:27.849485 MVN_1=0x00000000
594 19:17:27.854406 MVN_2=0x00000000
595 19:17:27.860185 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 19:17:27.860478 OPS=0x10
597 19:17:27.860742 ring efuse init
598 19:17:27.861024 chipver efuse init
599 19:17:27.865754 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 19:17:27.871259 [0.018961 Inits done]
601 19:17:27.871565 secure task start!
602 19:17:27.871785 high task start!
603 19:17:27.875918 low task start!
604 19:17:27.876222 run into bl31
605 19:17:27.882539 NOTICE: BL31: v1.3(release):4fc40b1
606 19:17:27.890392 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 19:17:27.890793 NOTICE: BL31: G12A normal boot!
608 19:17:27.915724 NOTICE: BL31: BL33 decompress pass
609 19:17:27.921411 ERROR: Error initializing runtime service opteed_fast
610 19:17:29.154622
611 19:17:29.155276
612 19:17:29.162920 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 19:17:29.163475
614 19:17:29.163895 Model: Libre Computer AML-A311D-CC Alta
615 19:17:29.371522 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 19:17:29.394910 DRAM: 2 GiB (effective 3.8 GiB)
617 19:17:29.537810 Core: 408 devices, 31 uclasses, devicetree: separate
618 19:17:29.543739 WDT: Not starting watchdog@f0d0
619 19:17:29.575886 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 19:17:29.588428 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 19:17:29.593362 ** Bad device specification mmc 0 **
622 19:17:29.603649 Card did not respond to voltage select! : -110
623 19:17:29.611386 ** Bad device specification mmc 0 **
624 19:17:29.611934 Couldn't find partition mmc 0
625 19:17:29.619653 Card did not respond to voltage select! : -110
626 19:17:29.625122 ** Bad device specification mmc 0 **
627 19:17:29.625577 Couldn't find partition mmc 0
628 19:17:29.630240 Error: could not access storage.
629 19:17:29.972809 Net: eth0: ethernet@ff3f0000
630 19:17:29.973504 starting USB...
631 19:17:30.224664 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 19:17:30.225299 Starting the controller
633 19:17:30.231601 USB XHCI 1.10
634 19:17:31.941670 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 19:17:31.942118 bl2_stage_init 0x01
636 19:17:31.942357 bl2_stage_init 0x81
637 19:17:31.947237 hw id: 0x0000 - pwm id 0x01
638 19:17:31.947592 bl2_stage_init 0xc1
639 19:17:31.947810 bl2_stage_init 0x02
640 19:17:31.948044
641 19:17:31.952832 L0:00000000
642 19:17:31.953120 L1:20000703
643 19:17:31.953333 L2:00008067
644 19:17:31.953538 L3:14000000
645 19:17:31.955652 B2:00402000
646 19:17:31.955923 B1:e0f83180
647 19:17:31.956162
648 19:17:31.956373 TE: 58124
649 19:17:31.956591
650 19:17:31.966927 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 19:17:31.967289
652 19:17:31.967506 Board ID = 1
653 19:17:31.967714 Set A53 clk to 24M
654 19:17:31.967916 Set A73 clk to 24M
655 19:17:31.972529 Set clk81 to 24M
656 19:17:31.972819 A53 clk: 1200 MHz
657 19:17:31.973040 A73 clk: 1200 MHz
658 19:17:31.978118 CLK81: 166.6M
659 19:17:31.978411 smccc: 00012a91
660 19:17:31.983634 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 19:17:31.983929 board id: 1
662 19:17:31.992313 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 19:17:32.002985 fw parse done
664 19:17:32.008963 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 19:17:32.051475 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 19:17:32.062384 PIEI prepare done
667 19:17:32.062847 fastboot data load
668 19:17:32.063098 fastboot data verify
669 19:17:32.068061 verify result: 266
670 19:17:32.073621 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 19:17:32.074003 LPDDR4 probe
672 19:17:32.074225 ddr clk to 1584MHz
673 19:17:32.081609 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 19:17:32.119327
675 19:17:32.119705 dmc_version 0001
676 19:17:32.125531 Check phy result
677 19:17:32.131384 INFO : End of CA training
678 19:17:32.131656 INFO : End of initialization
679 19:17:32.136961 INFO : Training has run successfully!
680 19:17:32.137229 Check phy result
681 19:17:32.142653 INFO : End of initialization
682 19:17:32.142924 INFO : End of read enable training
683 19:17:32.145863 INFO : End of fine write leveling
684 19:17:32.151451 INFO : End of Write leveling coarse delay
685 19:17:32.157062 INFO : Training has run successfully!
686 19:17:32.157368 Check phy result
687 19:17:32.157587 INFO : End of initialization
688 19:17:32.162708 INFO : End of read dq deskew training
689 19:17:32.168288 INFO : End of MPR read delay center optimization
690 19:17:32.168597 INFO : End of write delay center optimization
691 19:17:32.173848 INFO : End of read delay center optimization
692 19:17:32.179492 INFO : End of max read latency training
693 19:17:32.179959 INFO : Training has run successfully!
694 19:17:32.185107 1D training succeed
695 19:17:32.190954 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 19:17:32.238742 Check phy result
697 19:17:32.239110 INFO : End of initialization
698 19:17:32.260354 INFO : End of 2D read delay Voltage center optimization
699 19:17:32.280614 INFO : End of 2D read delay Voltage center optimization
700 19:17:32.332651 INFO : End of 2D write delay Voltage center optimization
701 19:17:32.382073 INFO : End of 2D write delay Voltage center optimization
702 19:17:32.387758 INFO : Training has run successfully!
703 19:17:32.388067
704 19:17:32.388287 channel==0
705 19:17:32.393414 RxClkDly_Margin_A0==88 ps 9
706 19:17:32.393825 TxDqDly_Margin_A0==98 ps 10
707 19:17:32.398693 RxClkDly_Margin_A1==88 ps 9
708 19:17:32.399100 TxDqDly_Margin_A1==98 ps 10
709 19:17:32.399429 TrainedVREFDQ_A0==74
710 19:17:32.404317 TrainedVREFDQ_A1==74
711 19:17:32.404612 VrefDac_Margin_A0==25
712 19:17:32.404822 DeviceVref_Margin_A0==40
713 19:17:32.409919 VrefDac_Margin_A1==25
714 19:17:32.410334 DeviceVref_Margin_A1==40
715 19:17:32.410667
716 19:17:32.410996
717 19:17:32.415669 channel==1
718 19:17:32.416155 RxClkDly_Margin_A0==98 ps 10
719 19:17:32.416404 TxDqDly_Margin_A0==98 ps 10
720 19:17:32.421200 RxClkDly_Margin_A1==98 ps 10
721 19:17:32.421486 TxDqDly_Margin_A1==88 ps 9
722 19:17:32.426779 TrainedVREFDQ_A0==77
723 19:17:32.427181 TrainedVREFDQ_A1==77
724 19:17:32.427510 VrefDac_Margin_A0==22
725 19:17:32.432348 DeviceVref_Margin_A0==37
726 19:17:32.432646 VrefDac_Margin_A1==22
727 19:17:32.437911 DeviceVref_Margin_A1==37
728 19:17:32.438315
729 19:17:32.438660 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 19:17:32.443619
731 19:17:32.471452 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
732 19:17:32.471794 2D training succeed
733 19:17:32.477081 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 19:17:32.482642 auto size-- 65535DDR cs0 size: 2048MB
735 19:17:32.482926 DDR cs1 size: 2048MB
736 19:17:32.488295 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 19:17:32.488707 cs0 DataBus test pass
738 19:17:32.493859 cs1 DataBus test pass
739 19:17:32.494262 cs0 AddrBus test pass
740 19:17:32.494500 cs1 AddrBus test pass
741 19:17:32.494707
742 19:17:32.499478 100bdlr_step_size ps== 420
743 19:17:32.499772 result report
744 19:17:32.505094 boot times 0Enable ddr reg access
745 19:17:32.510522 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 19:17:32.524066 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 19:17:33.097617 0.0;M3 CHK:0;cm4_sp_mode 0
748 19:17:33.098044 MVN_1=0x00000000
749 19:17:33.103196 MVN_2=0x00000000
750 19:17:33.108885 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 19:17:33.109370 OPS=0x10
752 19:17:33.109787 ring efuse init
753 19:17:33.110185 chipver efuse init
754 19:17:33.114498 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 19:17:33.120095 [0.018961 Inits done]
756 19:17:33.120588 secure task start!
757 19:17:33.120991 high task start!
758 19:17:33.124683 low task start!
759 19:17:33.125135 run into bl31
760 19:17:33.131304 NOTICE: BL31: v1.3(release):4fc40b1
761 19:17:33.139233 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 19:17:33.139571 NOTICE: BL31: G12A normal boot!
763 19:17:33.164563 NOTICE: BL31: BL33 decompress pass
764 19:17:33.170273 ERROR: Error initializing runtime service opteed_fast
765 19:17:34.403221
766 19:17:34.403642
767 19:17:34.411494 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 19:17:34.411827
769 19:17:34.412082 Model: Libre Computer AML-A311D-CC Alta
770 19:17:34.619883 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 19:17:34.643283 DRAM: 2 GiB (effective 3.8 GiB)
772 19:17:34.786291 Core: 408 devices, 31 uclasses, devicetree: separate
773 19:17:34.792189 WDT: Not starting watchdog@f0d0
774 19:17:34.824407 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 19:17:34.836844 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 19:17:34.841859 ** Bad device specification mmc 0 **
777 19:17:34.852174 Card did not respond to voltage select! : -110
778 19:17:34.859814 ** Bad device specification mmc 0 **
779 19:17:34.860135 Couldn't find partition mmc 0
780 19:17:34.868176 Card did not respond to voltage select! : -110
781 19:17:34.873646 ** Bad device specification mmc 0 **
782 19:17:34.874063 Couldn't find partition mmc 0
783 19:17:34.878736 Error: could not access storage.
784 19:17:35.222312 Net: eth0: ethernet@ff3f0000
785 19:17:35.222720 starting USB...
786 19:17:35.474063 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 19:17:35.474614 Starting the controller
788 19:17:35.481064 USB XHCI 1.10
789 19:17:37.642020 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 19:17:37.642450 bl2_stage_init 0x01
791 19:17:37.642681 bl2_stage_init 0x81
792 19:17:37.647451 hw id: 0x0000 - pwm id 0x01
793 19:17:37.647795 bl2_stage_init 0xc1
794 19:17:37.648072 bl2_stage_init 0x02
795 19:17:37.648292
796 19:17:37.653037 L0:00000000
797 19:17:37.653379 L1:20000703
798 19:17:37.653612 L2:00008067
799 19:17:37.653827 L3:14000000
800 19:17:37.655958 B2:00402000
801 19:17:37.656419 B1:e0f83180
802 19:17:37.656775
803 19:17:37.657123 TE: 58124
804 19:17:37.657471
805 19:17:37.667005 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 19:17:37.667386
807 19:17:37.667613 Board ID = 1
808 19:17:37.667824 Set A53 clk to 24M
809 19:17:37.668067 Set A73 clk to 24M
810 19:17:37.672609 Set clk81 to 24M
811 19:17:37.672950 A53 clk: 1200 MHz
812 19:17:37.673174 A73 clk: 1200 MHz
813 19:17:37.676211 CLK81: 166.6M
814 19:17:37.676656 smccc: 00012a92
815 19:17:37.681774 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 19:17:37.687374 board id: 1
817 19:17:37.692480 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 19:17:37.703173 fw parse done
819 19:17:37.709122 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 19:17:37.751739 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 19:17:37.762699 PIEI prepare done
822 19:17:37.763238 fastboot data load
823 19:17:37.763679 fastboot data verify
824 19:17:37.768167 verify result: 266
825 19:17:37.773729 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 19:17:37.774229 LPDDR4 probe
827 19:17:37.774651 ddr clk to 1584MHz
828 19:17:37.781735 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 19:17:37.819025
830 19:17:37.819586 dmc_version 0001
831 19:17:37.825798 Check phy result
832 19:17:37.831615 INFO : End of CA training
833 19:17:37.832153 INFO : End of initialization
834 19:17:37.837165 INFO : Training has run successfully!
835 19:17:37.837668 Check phy result
836 19:17:37.842727 INFO : End of initialization
837 19:17:37.843218 INFO : End of read enable training
838 19:17:37.845985 INFO : End of fine write leveling
839 19:17:37.851582 INFO : End of Write leveling coarse delay
840 19:17:37.857156 INFO : Training has run successfully!
841 19:17:37.857665 Check phy result
842 19:17:37.858083 INFO : End of initialization
843 19:17:37.862771 INFO : End of read dq deskew training
844 19:17:37.866130 INFO : End of MPR read delay center optimization
845 19:17:37.871642 INFO : End of write delay center optimization
846 19:17:37.877270 INFO : End of read delay center optimization
847 19:17:37.878272 INFO : End of max read latency training
848 19:17:37.882889 INFO : Training has run successfully!
849 19:17:37.884077 1D training succeed
850 19:17:37.891181 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 19:17:37.938861 Check phy result
852 19:17:37.939936 INFO : End of initialization
853 19:17:37.960415 INFO : End of 2D read delay Voltage center optimization
854 19:17:37.980589 INFO : End of 2D read delay Voltage center optimization
855 19:17:38.032452 INFO : End of 2D write delay Voltage center optimization
856 19:17:38.081826 INFO : End of 2D write delay Voltage center optimization
857 19:17:38.087203 INFO : Training has run successfully!
858 19:17:38.088307
859 19:17:38.088765 channel==0
860 19:17:38.092698 RxClkDly_Margin_A0==88 ps 9
861 19:17:38.093768 TxDqDly_Margin_A0==98 ps 10
862 19:17:38.098642 RxClkDly_Margin_A1==88 ps 9
863 19:17:38.099709 TxDqDly_Margin_A1==98 ps 10
864 19:17:38.100227 TrainedVREFDQ_A0==74
865 19:17:38.103933 TrainedVREFDQ_A1==74
866 19:17:38.105067 VrefDac_Margin_A0==25
867 19:17:38.105514 DeviceVref_Margin_A0==40
868 19:17:38.109495 VrefDac_Margin_A1==25
869 19:17:38.110467 DeviceVref_Margin_A1==40
870 19:17:38.110897
871 19:17:38.111292
872 19:17:38.115081 channel==1
873 19:17:38.115640 RxClkDly_Margin_A0==98 ps 10
874 19:17:38.116082 TxDqDly_Margin_A0==88 ps 9
875 19:17:38.120993 RxClkDly_Margin_A1==98 ps 10
876 19:17:38.121481 TxDqDly_Margin_A1==88 ps 9
877 19:17:38.126333 TrainedVREFDQ_A0==75
878 19:17:38.127384 TrainedVREFDQ_A1==77
879 19:17:38.127788 VrefDac_Margin_A0==22
880 19:17:38.132190 DeviceVref_Margin_A0==39
881 19:17:38.132733 VrefDac_Margin_A1==24
882 19:17:38.137499 DeviceVref_Margin_A1==37
883 19:17:38.137952
884 19:17:38.138356 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 19:17:38.138753
886 19:17:38.171123 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
887 19:17:38.171661 2D training succeed
888 19:17:38.176696 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 19:17:38.182241 auto size-- 65535DDR cs0 size: 2048MB
890 19:17:38.182738 DDR cs1 size: 2048MB
891 19:17:38.187828 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 19:17:38.188330 cs0 DataBus test pass
893 19:17:38.193455 cs1 DataBus test pass
894 19:17:38.193902 cs0 AddrBus test pass
895 19:17:38.194300 cs1 AddrBus test pass
896 19:17:38.194692
897 19:17:38.199029 100bdlr_step_size ps== 420
898 19:17:38.199480 result report
899 19:17:38.204624 boot times 0Enable ddr reg access
900 19:17:38.209976 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 19:17:38.223461 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 19:17:38.795606 0.0;M3 CHK:0;cm4_sp_mode 0
903 19:17:38.796081 MVN_1=0x00000000
904 19:17:38.801002 MVN_2=0x00000000
905 19:17:38.806717 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 19:17:38.807088 OPS=0x10
907 19:17:38.807335 ring efuse init
908 19:17:38.807566 chipver efuse init
909 19:17:38.814913 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 19:17:38.815408 [0.018961 Inits done]
911 19:17:38.822543 secure task start!
912 19:17:38.823040 high task start!
913 19:17:38.823436 low task start!
914 19:17:38.823819 run into bl31
915 19:17:38.829160 NOTICE: BL31: v1.3(release):4fc40b1
916 19:17:38.836967 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 19:17:38.837325 NOTICE: BL31: G12A normal boot!
918 19:17:38.862540 NOTICE: BL31: BL33 decompress pass
919 19:17:38.868062 ERROR: Error initializing runtime service opteed_fast
920 19:17:40.101032
921 19:17:40.101679
922 19:17:40.108928 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 19:17:40.109429
924 19:17:40.109856 Model: Libre Computer AML-A311D-CC Alta
925 19:17:40.317813 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 19:17:40.341179 DRAM: 2 GiB (effective 3.8 GiB)
927 19:17:40.484184 Core: 408 devices, 31 uclasses, devicetree: separate
928 19:17:40.489993 WDT: Not starting watchdog@f0d0
929 19:17:40.522291 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 19:17:40.534759 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 19:17:40.539731 ** Bad device specification mmc 0 **
932 19:17:40.550078 Card did not respond to voltage select! : -110
933 19:17:40.557671 ** Bad device specification mmc 0 **
934 19:17:40.558022 Couldn't find partition mmc 0
935 19:17:40.565995 Card did not respond to voltage select! : -110
936 19:17:40.571665 ** Bad device specification mmc 0 **
937 19:17:40.572067 Couldn't find partition mmc 0
938 19:17:40.576527 Error: could not access storage.
939 19:17:40.920282 Net: eth0: ethernet@ff3f0000
940 19:17:40.921348 starting USB...
941 19:17:41.171914 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 19:17:41.172454 Starting the controller
943 19:17:41.178916 USB XHCI 1.10
944 19:17:43.041470 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 19:17:43.042097 bl2_stage_init 0x01
946 19:17:43.042528 bl2_stage_init 0x81
947 19:17:43.047001 hw id: 0x0000 - pwm id 0x01
948 19:17:43.047457 bl2_stage_init 0xc1
949 19:17:43.047874 bl2_stage_init 0x02
950 19:17:43.048340
951 19:17:43.052573 L0:00000000
952 19:17:43.053014 L1:20000703
953 19:17:43.053429 L2:00008067
954 19:17:43.053834 L3:14000000
955 19:17:43.058227 B2:00402000
956 19:17:43.058666 B1:e0f83180
957 19:17:43.059070
958 19:17:43.059477 TE: 58159
959 19:17:43.059885
960 19:17:43.063775 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 19:17:43.064255
962 19:17:43.064669 Board ID = 1
963 19:17:43.069371 Set A53 clk to 24M
964 19:17:43.069831 Set A73 clk to 24M
965 19:17:43.070243 Set clk81 to 24M
966 19:17:43.075004 A53 clk: 1200 MHz
967 19:17:43.075446 A73 clk: 1200 MHz
968 19:17:43.075853 CLK81: 166.6M
969 19:17:43.076289 smccc: 00012ab5
970 19:17:43.080572 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 19:17:43.086198 board id: 1
972 19:17:43.092078 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 19:17:43.102690 fw parse done
974 19:17:43.108692 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 19:17:43.151320 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 19:17:43.162235 PIEI prepare done
977 19:17:43.162670 fastboot data load
978 19:17:43.163065 fastboot data verify
979 19:17:43.167814 verify result: 266
980 19:17:43.173451 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 19:17:43.173878 LPDDR4 probe
982 19:17:43.174267 ddr clk to 1584MHz
983 19:17:43.181687 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 19:17:43.218951
985 19:17:43.219462 dmc_version 0001
986 19:17:43.225701 Check phy result
987 19:17:43.231554 INFO : End of CA training
988 19:17:43.232022 INFO : End of initialization
989 19:17:43.237023 INFO : Training has run successfully!
990 19:17:43.237456 Check phy result
991 19:17:43.242660 INFO : End of initialization
992 19:17:43.243160 INFO : End of read enable training
993 19:17:43.245851 INFO : End of fine write leveling
994 19:17:43.251238 INFO : End of Write leveling coarse delay
995 19:17:43.256912 INFO : Training has run successfully!
996 19:17:43.257359 Check phy result
997 19:17:43.257766 INFO : End of initialization
998 19:17:43.262483 INFO : End of read dq deskew training
999 19:17:43.268126 INFO : End of MPR read delay center optimization
1000 19:17:43.268569 INFO : End of write delay center optimization
1001 19:17:43.273686 INFO : End of read delay center optimization
1002 19:17:43.279187 INFO : End of max read latency training
1003 19:17:43.279634 INFO : Training has run successfully!
1004 19:17:43.284793 1D training succeed
1005 19:17:43.290933 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 19:17:43.338517 Check phy result
1007 19:17:43.339059 INFO : End of initialization
1008 19:17:43.360950 INFO : End of 2D read delay Voltage center optimization
1009 19:17:43.381036 INFO : End of 2D read delay Voltage center optimization
1010 19:17:43.432908 INFO : End of 2D write delay Voltage center optimization
1011 19:17:43.482328 INFO : End of 2D write delay Voltage center optimization
1012 19:17:43.487720 INFO : Training has run successfully!
1013 19:17:43.488218
1014 19:17:43.488641 channel==0
1015 19:17:43.493423 RxClkDly_Margin_A0==88 ps 9
1016 19:17:43.493866 TxDqDly_Margin_A0==98 ps 10
1017 19:17:43.498948 RxClkDly_Margin_A1==88 ps 9
1018 19:17:43.499280 TxDqDly_Margin_A1==98 ps 10
1019 19:17:43.499516 TrainedVREFDQ_A0==74
1020 19:17:43.504565 TrainedVREFDQ_A1==74
1021 19:17:43.504942 VrefDac_Margin_A0==24
1022 19:17:43.505172 DeviceVref_Margin_A0==40
1023 19:17:43.510114 VrefDac_Margin_A1==24
1024 19:17:43.510423 DeviceVref_Margin_A1==40
1025 19:17:43.510658
1026 19:17:43.510895
1027 19:17:43.515632 channel==1
1028 19:17:43.515935 RxClkDly_Margin_A0==98 ps 10
1029 19:17:43.516329 TxDqDly_Margin_A0==88 ps 9
1030 19:17:43.521424 RxClkDly_Margin_A1==98 ps 10
1031 19:17:43.521738 TxDqDly_Margin_A1==88 ps 9
1032 19:17:43.526932 TrainedVREFDQ_A0==77
1033 19:17:43.527249 TrainedVREFDQ_A1==77
1034 19:17:43.527475 VrefDac_Margin_A0==22
1035 19:17:43.532509 DeviceVref_Margin_A0==37
1036 19:17:43.532821 VrefDac_Margin_A1==23
1037 19:17:43.538286 DeviceVref_Margin_A1==37
1038 19:17:43.538622
1039 19:17:43.538856 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 19:17:43.539075
1041 19:17:43.571727 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
1042 19:17:43.572148 2D training succeed
1043 19:17:43.577449 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 19:17:43.582807 auto size-- 65535DDR cs0 size: 2048MB
1045 19:17:43.583128 DDR cs1 size: 2048MB
1046 19:17:43.588398 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 19:17:43.588645 cs0 DataBus test pass
1048 19:17:43.593996 cs1 DataBus test pass
1049 19:17:43.594236 cs0 AddrBus test pass
1050 19:17:43.594448 cs1 AddrBus test pass
1051 19:17:43.594653
1052 19:17:43.599554 100bdlr_step_size ps== 420
1053 19:17:43.599804 result report
1054 19:17:43.605284 boot times 0Enable ddr reg access
1055 19:17:43.610476 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 19:17:43.624000 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 19:17:44.196107 0.0;M3 CHK:0;cm4_sp_mode 0
1058 19:17:44.196747 MVN_1=0x00000000
1059 19:17:44.201502 MVN_2=0x00000000
1060 19:17:44.207339 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 19:17:44.207793 OPS=0x10
1062 19:17:44.208252 ring efuse init
1063 19:17:44.208662 chipver efuse init
1064 19:17:44.215537 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 19:17:44.216065 [0.018960 Inits done]
1066 19:17:44.223062 secure task start!
1067 19:17:44.223515 high task start!
1068 19:17:44.223922 low task start!
1069 19:17:44.224365 run into bl31
1070 19:17:44.229706 NOTICE: BL31: v1.3(release):4fc40b1
1071 19:17:44.237588 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 19:17:44.238052 NOTICE: BL31: G12A normal boot!
1073 19:17:44.262909 NOTICE: BL31: BL33 decompress pass
1074 19:17:44.268551 ERROR: Error initializing runtime service opteed_fast
1075 19:17:45.501459
1076 19:17:45.501888
1077 19:17:45.509899 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 19:17:45.510237
1079 19:17:45.510467 Model: Libre Computer AML-A311D-CC Alta
1080 19:17:45.718438 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 19:17:45.741790 DRAM: 2 GiB (effective 3.8 GiB)
1082 19:17:45.884815 Core: 408 devices, 31 uclasses, devicetree: separate
1083 19:17:45.890696 WDT: Not starting watchdog@f0d0
1084 19:17:45.922843 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 19:17:45.935372 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 19:17:45.940326 ** Bad device specification mmc 0 **
1087 19:17:45.950627 Card did not respond to voltage select! : -110
1088 19:17:45.958214 ** Bad device specification mmc 0 **
1089 19:17:45.958661 Couldn't find partition mmc 0
1090 19:17:45.966590 Card did not respond to voltage select! : -110
1091 19:17:45.972069 ** Bad device specification mmc 0 **
1092 19:17:45.972527 Couldn't find partition mmc 0
1093 19:17:45.977146 Error: could not access storage.
1094 19:17:46.319666 Net: eth0: ethernet@ff3f0000
1095 19:17:46.320288 starting USB...
1096 19:17:46.571501 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 19:17:46.571916 Starting the controller
1098 19:17:46.578313 USB XHCI 1.10
1099 19:17:48.134485 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 19:17:48.142810 scanning usb for storage devices... 0 Storage Device(s) found
1102 19:17:48.194389 Hit any key to stop autoboot: 1
1103 19:17:48.195181 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1104 19:17:48.195744 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1105 19:17:48.196244 Setting prompt string to ['=>']
1106 19:17:48.196720 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1107 19:17:48.210336 0
1108 19:17:48.211182 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 19:17:48.211651 Sending with 10 millisecond of delay
1111 19:17:49.346383 => setenv autoload no
1112 19:17:49.357213 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1113 19:17:49.362113 setenv autoload no
1114 19:17:49.362862 Sending with 10 millisecond of delay
1116 19:17:51.160780 => setenv initrd_high 0xffffffff
1117 19:17:51.171629 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1118 19:17:51.172627 setenv initrd_high 0xffffffff
1119 19:17:51.173429 Sending with 10 millisecond of delay
1121 19:17:52.791219 => setenv fdt_high 0xffffffff
1122 19:17:52.802103 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1123 19:17:52.803036 setenv fdt_high 0xffffffff
1124 19:17:52.803819 Sending with 10 millisecond of delay
1126 19:17:53.095924 => dhcp
1127 19:17:53.106805 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1128 19:17:53.107717 dhcp
1129 19:17:53.108231 Speed: 1000, full duplex
1130 19:17:53.108682 BOOTP broadcast 1
1131 19:17:53.118924 DHCP client bound to address 192.168.6.27 (12 ms)
1132 19:17:53.119687 Sending with 10 millisecond of delay
1134 19:17:54.796917 => setenv serverip 192.168.6.2
1135 19:17:54.807756 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1136 19:17:54.808702 setenv serverip 192.168.6.2
1137 19:17:54.809453 Sending with 10 millisecond of delay
1139 19:17:58.533293 => tftpboot 0x01080000 954124/tftp-deploy-4aercd_m/kernel/uImage
1140 19:17:58.544046 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 19:17:58.544603 tftpboot 0x01080000 954124/tftp-deploy-4aercd_m/kernel/uImage
1142 19:17:58.544847 Speed: 1000, full duplex
1143 19:17:58.545053 Using ethernet@ff3f0000 device
1144 19:17:58.546586 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 19:17:58.552049 Filename '954124/tftp-deploy-4aercd_m/kernel/uImage'.
1146 19:17:58.555906 Load address: 0x1080000
1147 19:18:01.352134 Loading: *################################################## 43.6 MiB
1148 19:18:01.352772 15.6 MiB/s
1149 19:18:01.353210 done
1150 19:18:01.356379 Bytes transferred = 45713984 (2b98a40 hex)
1151 19:18:01.357167 Sending with 10 millisecond of delay
1153 19:18:06.044015 => tftpboot 0x08000000 954124/tftp-deploy-4aercd_m/ramdisk/ramdisk.cpio.gz.uboot
1154 19:18:06.054598 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1155 19:18:06.055096 tftpboot 0x08000000 954124/tftp-deploy-4aercd_m/ramdisk/ramdisk.cpio.gz.uboot
1156 19:18:06.055331 Speed: 1000, full duplex
1157 19:18:06.055554 Using ethernet@ff3f0000 device
1158 19:18:06.057364 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 19:18:06.069159 Filename '954124/tftp-deploy-4aercd_m/ramdisk/ramdisk.cpio.gz.uboot'.
1160 19:18:06.069621 Load address: 0x8000000
1161 19:18:13.109593 Loading: *#####################T ############################ UDP wrong checksum 00000005 00007915
1162 19:18:18.110411 T UDP wrong checksum 00000005 00007915
1163 19:18:28.113642 T T UDP wrong checksum 00000005 00007915
1164 19:18:29.527503 UDP wrong checksum 000000ff 00001e23
1165 19:18:29.589892 UDP wrong checksum 000000ff 0000aa15
1166 19:18:45.578469 T T T UDP wrong checksum 000000ff 00006b50
1167 19:18:45.608637 UDP wrong checksum 000000ff 00000243
1168 19:18:48.117186 UDP wrong checksum 00000005 00007915
1169 19:19:03.122732 T T T
1170 19:19:03.123196 Retry count exceeded; starting again
1172 19:19:03.124243 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1175 19:19:03.125463 end: 2.4 uboot-commands (duration 00:01:53) [common]
1177 19:19:03.126181 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1179 19:19:03.126856 end: 2 uboot-action (duration 00:01:53) [common]
1181 19:19:03.127834 Cleaning after the job
1182 19:19:03.128225 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/ramdisk
1183 19:19:03.129161 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/kernel
1184 19:19:03.144090 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/dtb
1185 19:19:03.145041 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/nfsrootfs
1186 19:19:03.200113 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954124/tftp-deploy-4aercd_m/modules
1187 19:19:03.207087 start: 4.1 power-off (timeout 00:00:30) [common]
1188 19:19:03.207778 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1189 19:19:03.250186 >> OK - accepted request
1190 19:19:03.251623 Returned 0 in 0 seconds
1191 19:19:03.352576 end: 4.1 power-off (duration 00:00:00) [common]
1193 19:19:03.353709 start: 4.2 read-feedback (timeout 00:10:00) [common]
1194 19:19:03.354405 Listened to connection for namespace 'common' for up to 1s
1195 19:19:04.355327 Finalising connection for namespace 'common'
1196 19:19:04.355832 Disconnecting from shell: Finalise
1197 19:19:04.356181 =>
1198 19:19:04.457107 end: 4.2 read-feedback (duration 00:00:01) [common]
1199 19:19:04.457862 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/954124
1200 19:19:07.761467 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/954124
1201 19:19:07.762125 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.