Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:11:46.821764 lava-dispatcher, installed at version: 2024.01
2 20:11:46.822559 start: 0 validate
3 20:11:46.823051 Start time: 2024-11-07 20:11:46.823020+00:00 (UTC)
4 20:11:46.823597 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:11:46.824141 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 20:11:46.866916 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:11:46.867484 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-244-g7a812b09d88be%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 20:11:46.900939 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:11:46.901879 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-244-g7a812b09d88be%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 20:11:46.935639 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:11:46.936160 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-244-g7a812b09d88be%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 20:11:46.975714 validate duration: 0.15
14 20:11:46.976647 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:11:46.976992 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:11:46.977310 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:11:46.977908 Not decompressing ramdisk as can be used compressed.
18 20:11:46.978333 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 20:11:46.978614 saving as /var/lib/lava/dispatcher/tmp/954416/tftp-deploy-9jv0ohyk/ramdisk/rootfs.cpio.gz
20 20:11:46.978892 total size: 47897469 (45 MB)
21 20:11:47.018335 progress 0 % (0 MB)
22 20:11:47.048297 progress 5 % (2 MB)
23 20:11:47.077452 progress 10 % (4 MB)
24 20:11:47.106333 progress 15 % (6 MB)
25 20:11:47.135259 progress 20 % (9 MB)
26 20:11:47.164198 progress 25 % (11 MB)
27 20:11:47.192995 progress 30 % (13 MB)
28 20:11:47.221851 progress 35 % (16 MB)
29 20:11:47.250447 progress 40 % (18 MB)
30 20:11:47.279476 progress 45 % (20 MB)
31 20:11:47.308201 progress 50 % (22 MB)
32 20:11:47.336947 progress 55 % (25 MB)
33 20:11:47.366298 progress 60 % (27 MB)
34 20:11:47.395468 progress 65 % (29 MB)
35 20:11:47.424412 progress 70 % (32 MB)
36 20:11:47.453102 progress 75 % (34 MB)
37 20:11:47.481799 progress 80 % (36 MB)
38 20:11:47.511523 progress 85 % (38 MB)
39 20:11:47.542508 progress 90 % (41 MB)
40 20:11:47.571900 progress 95 % (43 MB)
41 20:11:47.599502 progress 100 % (45 MB)
42 20:11:47.600231 45 MB downloaded in 0.62 s (73.52 MB/s)
43 20:11:47.600777 end: 1.1.1 http-download (duration 00:00:01) [common]
45 20:11:47.601673 end: 1.1 download-retry (duration 00:00:01) [common]
46 20:11:47.601965 start: 1.2 download-retry (timeout 00:09:59) [common]
47 20:11:47.602235 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 20:11:47.602711 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-244-g7a812b09d88be/arm64/defconfig/gcc-12/kernel/Image
49 20:11:47.602969 saving as /var/lib/lava/dispatcher/tmp/954416/tftp-deploy-9jv0ohyk/kernel/Image
50 20:11:47.603177 total size: 45713920 (43 MB)
51 20:11:47.603388 No compression specified
52 20:11:47.645313 progress 0 % (0 MB)
53 20:11:47.671880 progress 5 % (2 MB)
54 20:11:47.698738 progress 10 % (4 MB)
55 20:11:47.725445 progress 15 % (6 MB)
56 20:11:47.752156 progress 20 % (8 MB)
57 20:11:47.778428 progress 25 % (10 MB)
58 20:11:47.805772 progress 30 % (13 MB)
59 20:11:47.833065 progress 35 % (15 MB)
60 20:11:47.861489 progress 40 % (17 MB)
61 20:11:47.888731 progress 45 % (19 MB)
62 20:11:47.916403 progress 50 % (21 MB)
63 20:11:47.943476 progress 55 % (24 MB)
64 20:11:47.970223 progress 60 % (26 MB)
65 20:11:47.996560 progress 65 % (28 MB)
66 20:11:48.023670 progress 70 % (30 MB)
67 20:11:48.050554 progress 75 % (32 MB)
68 20:11:48.077252 progress 80 % (34 MB)
69 20:11:48.103599 progress 85 % (37 MB)
70 20:11:48.130466 progress 90 % (39 MB)
71 20:11:48.157191 progress 95 % (41 MB)
72 20:11:48.183053 progress 100 % (43 MB)
73 20:11:48.183554 43 MB downloaded in 0.58 s (75.12 MB/s)
74 20:11:48.184067 end: 1.2.1 http-download (duration 00:00:01) [common]
76 20:11:48.184882 end: 1.2 download-retry (duration 00:00:01) [common]
77 20:11:48.185157 start: 1.3 download-retry (timeout 00:09:59) [common]
78 20:11:48.185420 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 20:11:48.185888 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-244-g7a812b09d88be/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 20:11:48.186129 saving as /var/lib/lava/dispatcher/tmp/954416/tftp-deploy-9jv0ohyk/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 20:11:48.186334 total size: 53209 (0 MB)
82 20:11:48.186541 No compression specified
83 20:11:48.227642 progress 61 % (0 MB)
84 20:11:48.228507 progress 100 % (0 MB)
85 20:11:48.229025 0 MB downloaded in 0.04 s (1.19 MB/s)
86 20:11:48.229483 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:11:48.230287 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:11:48.230548 start: 1.4 download-retry (timeout 00:09:59) [common]
90 20:11:48.230810 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 20:11:48.231264 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-244-g7a812b09d88be/arm64/defconfig/gcc-12/modules.tar.xz
92 20:11:48.231500 saving as /var/lib/lava/dispatcher/tmp/954416/tftp-deploy-9jv0ohyk/modules/modules.tar
93 20:11:48.231704 total size: 11609200 (11 MB)
94 20:11:48.231913 Using unxz to decompress xz
95 20:11:48.269934 progress 0 % (0 MB)
96 20:11:48.334972 progress 5 % (0 MB)
97 20:11:48.408256 progress 10 % (1 MB)
98 20:11:48.504526 progress 15 % (1 MB)
99 20:11:48.595439 progress 20 % (2 MB)
100 20:11:48.675131 progress 25 % (2 MB)
101 20:11:48.749750 progress 30 % (3 MB)
102 20:11:48.823082 progress 35 % (3 MB)
103 20:11:48.899228 progress 40 % (4 MB)
104 20:11:48.973584 progress 45 % (5 MB)
105 20:11:49.057304 progress 50 % (5 MB)
106 20:11:49.133646 progress 55 % (6 MB)
107 20:11:49.217592 progress 60 % (6 MB)
108 20:11:49.297322 progress 65 % (7 MB)
109 20:11:49.372921 progress 70 % (7 MB)
110 20:11:49.454974 progress 75 % (8 MB)
111 20:11:49.538189 progress 80 % (8 MB)
112 20:11:49.617800 progress 85 % (9 MB)
113 20:11:49.695697 progress 90 % (9 MB)
114 20:11:49.772487 progress 95 % (10 MB)
115 20:11:49.849270 progress 100 % (11 MB)
116 20:11:49.860651 11 MB downloaded in 1.63 s (6.80 MB/s)
117 20:11:49.861207 end: 1.4.1 http-download (duration 00:00:02) [common]
119 20:11:49.862023 end: 1.4 download-retry (duration 00:00:02) [common]
120 20:11:49.862292 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 20:11:49.862557 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 20:11:49.862807 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:11:49.863062 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 20:11:49.863652 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd
125 20:11:49.864267 makedir: /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin
126 20:11:49.864908 makedir: /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/tests
127 20:11:49.865539 makedir: /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/results
128 20:11:49.866142 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-add-keys
129 20:11:49.867054 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-add-sources
130 20:11:49.867967 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-background-process-start
131 20:11:49.868926 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-background-process-stop
132 20:11:49.869879 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-common-functions
133 20:11:49.870762 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-echo-ipv4
134 20:11:49.871630 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-install-packages
135 20:11:49.872540 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-installed-packages
136 20:11:49.873410 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-os-build
137 20:11:49.874269 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-probe-channel
138 20:11:49.875159 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-probe-ip
139 20:11:49.876056 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-target-ip
140 20:11:49.876932 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-target-mac
141 20:11:49.877794 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-target-storage
142 20:11:49.878670 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-test-case
143 20:11:49.879532 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-test-event
144 20:11:49.880422 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-test-feedback
145 20:11:49.881296 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-test-raise
146 20:11:49.882154 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-test-reference
147 20:11:49.883010 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-test-runner
148 20:11:49.883871 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-test-set
149 20:11:49.884883 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-test-shell
150 20:11:49.885773 Updating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-install-packages (oe)
151 20:11:49.886722 Updating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/bin/lava-installed-packages (oe)
152 20:11:49.887520 Creating /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/environment
153 20:11:49.888227 LAVA metadata
154 20:11:49.888708 - LAVA_JOB_ID=954416
155 20:11:49.889131 - LAVA_DISPATCHER_IP=192.168.6.2
156 20:11:49.889761 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 20:11:49.891482 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 20:11:49.892075 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 20:11:49.892490 skipped lava-vland-overlay
160 20:11:49.892972 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 20:11:49.893477 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 20:11:49.893894 skipped lava-multinode-overlay
163 20:11:49.894371 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 20:11:49.894865 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 20:11:49.895331 Loading test definitions
166 20:11:49.895867 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 20:11:49.896350 Using /lava-954416 at stage 0
168 20:11:49.898421 uuid=954416_1.5.2.4.1 testdef=None
169 20:11:49.898972 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 20:11:49.899484 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 20:11:49.901508 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 20:11:49.902300 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 20:11:49.904502 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 20:11:49.905326 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 20:11:49.907374 runner path: /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/0/tests/0_igt-gpu-panfrost test_uuid 954416_1.5.2.4.1
178 20:11:49.907907 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 20:11:49.908733 Creating lava-test-runner.conf files
181 20:11:49.908940 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/954416/lava-overlay-82c3wyvd/lava-954416/0 for stage 0
182 20:11:49.909273 - 0_igt-gpu-panfrost
183 20:11:49.909614 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 20:11:49.909891 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 20:11:49.933006 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 20:11:49.933380 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 20:11:49.933643 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 20:11:49.933907 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 20:11:49.934164 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 20:11:57.220059 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 20:11:57.220557 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 20:11:57.220846 extracting modules file /var/lib/lava/dispatcher/tmp/954416/tftp-deploy-9jv0ohyk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954416/extract-overlay-ramdisk-gw53or5n/ramdisk
193 20:11:58.655291 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 20:11:58.655769 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 20:11:58.656076 [common] Applying overlay /var/lib/lava/dispatcher/tmp/954416/compress-overlay-iws_x1f8/overlay-1.5.2.5.tar.gz to ramdisk
196 20:11:58.656294 [common] Applying overlay /var/lib/lava/dispatcher/tmp/954416/compress-overlay-iws_x1f8/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/954416/extract-overlay-ramdisk-gw53or5n/ramdisk
197 20:11:58.686818 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 20:11:58.687255 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 20:11:58.687528 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 20:11:58.687760 Converting downloaded kernel to a uImage
201 20:11:58.688091 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/954416/tftp-deploy-9jv0ohyk/kernel/Image /var/lib/lava/dispatcher/tmp/954416/tftp-deploy-9jv0ohyk/kernel/uImage
202 20:11:59.161895 output: Image Name:
203 20:11:59.162311 output: Created: Thu Nov 7 20:11:58 2024
204 20:11:59.162521 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 20:11:59.162724 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 20:11:59.162925 output: Load Address: 01080000
207 20:11:59.163125 output: Entry Point: 01080000
208 20:11:59.163323 output:
209 20:11:59.163654 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 20:11:59.163920 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 20:11:59.164235 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 20:11:59.164492 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 20:11:59.164747 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 20:11:59.165012 Building ramdisk /var/lib/lava/dispatcher/tmp/954416/extract-overlay-ramdisk-gw53or5n/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/954416/extract-overlay-ramdisk-gw53or5n/ramdisk
215 20:12:05.724809 >> 502380 blocks
216 20:12:27.346435 Adding RAMdisk u-boot header.
217 20:12:27.346873 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/954416/extract-overlay-ramdisk-gw53or5n/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/954416/extract-overlay-ramdisk-gw53or5n/ramdisk.cpio.gz.uboot
218 20:12:28.022725 output: Image Name:
219 20:12:28.023171 output: Created: Thu Nov 7 20:12:27 2024
220 20:12:28.023413 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 20:12:28.023650 output: Data Size: 65714771 Bytes = 64174.58 KiB = 62.67 MiB
222 20:12:28.024139 output: Load Address: 00000000
223 20:12:28.024604 output: Entry Point: 00000000
224 20:12:28.025071 output:
225 20:12:28.026119 rename /var/lib/lava/dispatcher/tmp/954416/extract-overlay-ramdisk-gw53or5n/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/954416/tftp-deploy-9jv0ohyk/ramdisk/ramdisk.cpio.gz.uboot
226 20:12:28.026909 end: 1.5.8 compress-ramdisk (duration 00:00:29) [common]
227 20:12:28.027522 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 20:12:28.028151 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 20:12:28.028670 No LXC device requested
230 20:12:28.029273 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 20:12:28.029902 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 20:12:28.030530 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 20:12:28.031028 Checking files for TFTP limit of 4294967296 bytes.
234 20:12:28.034018 end: 1 tftp-deploy (duration 00:00:41) [common]
235 20:12:28.034663 start: 2 uboot-action (timeout 00:05:00) [common]
236 20:12:28.035250 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 20:12:28.035808 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 20:12:28.036433 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 20:12:28.037021 Using kernel file from prepare-kernel: 954416/tftp-deploy-9jv0ohyk/kernel/uImage
240 20:12:28.037698 substitutions:
241 20:12:28.038151 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 20:12:28.038599 - {DTB_ADDR}: 0x01070000
243 20:12:28.039038 - {DTB}: 954416/tftp-deploy-9jv0ohyk/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 20:12:28.039479 - {INITRD}: 954416/tftp-deploy-9jv0ohyk/ramdisk/ramdisk.cpio.gz.uboot
245 20:12:28.039917 - {KERNEL_ADDR}: 0x01080000
246 20:12:28.040413 - {KERNEL}: 954416/tftp-deploy-9jv0ohyk/kernel/uImage
247 20:12:28.040857 - {LAVA_MAC}: None
248 20:12:28.041340 - {PRESEED_CONFIG}: None
249 20:12:28.041783 - {PRESEED_LOCAL}: None
250 20:12:28.042219 - {RAMDISK_ADDR}: 0x08000000
251 20:12:28.042653 - {RAMDISK}: 954416/tftp-deploy-9jv0ohyk/ramdisk/ramdisk.cpio.gz.uboot
252 20:12:28.043091 - {ROOT_PART}: None
253 20:12:28.043523 - {ROOT}: None
254 20:12:28.043958 - {SERVER_IP}: 192.168.6.2
255 20:12:28.044434 - {TEE_ADDR}: 0x83000000
256 20:12:28.044771 - {TEE}: None
257 20:12:28.044982 Parsed boot commands:
258 20:12:28.045179 - setenv autoload no
259 20:12:28.045378 - setenv initrd_high 0xffffffff
260 20:12:28.045576 - setenv fdt_high 0xffffffff
261 20:12:28.046036 - dhcp
262 20:12:28.046473 - setenv serverip 192.168.6.2
263 20:12:28.046925 - tftpboot 0x01080000 954416/tftp-deploy-9jv0ohyk/kernel/uImage
264 20:12:28.047361 - tftpboot 0x08000000 954416/tftp-deploy-9jv0ohyk/ramdisk/ramdisk.cpio.gz.uboot
265 20:12:28.047797 - tftpboot 0x01070000 954416/tftp-deploy-9jv0ohyk/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 20:12:28.048259 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 20:12:28.048705 - bootm 0x01080000 0x08000000 0x01070000
268 20:12:28.049272 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 20:12:28.050913 start: 2.3 connect-device (timeout 00:05:00) [common]
271 20:12:28.051410 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 20:12:28.066652 Setting prompt string to ['lava-test: # ']
273 20:12:28.068275 end: 2.3 connect-device (duration 00:00:00) [common]
274 20:12:28.068956 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 20:12:28.069569 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 20:12:28.070139 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 20:12:28.071377 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 20:12:28.109310 >> OK - accepted request
279 20:12:28.111513 Returned 0 in 0 seconds
280 20:12:28.212813 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 20:12:28.214623 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 20:12:28.215262 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 20:12:28.215826 Setting prompt string to ['Hit any key to stop autoboot']
285 20:12:28.216428 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 20:12:28.218180 Trying 192.168.56.21...
287 20:12:28.218699 Connected to conserv1.
288 20:12:28.219157 Escape character is '^]'.
289 20:12:28.219623
290 20:12:28.220134 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 20:12:28.220625
292 20:12:35.558418 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 20:12:35.558873 bl2_stage_init 0x01
294 20:12:35.559121 bl2_stage_init 0x81
295 20:12:35.563943 hw id: 0x0000 - pwm id 0x01
296 20:12:35.564312 bl2_stage_init 0xc1
297 20:12:35.569413 bl2_stage_init 0x02
298 20:12:35.569789
299 20:12:35.570010 L0:00000000
300 20:12:35.570222 L1:00000703
301 20:12:35.570434 L2:00008067
302 20:12:35.570636 L3:15000000
303 20:12:35.574881 S1:00000000
304 20:12:35.575123 B2:20282000
305 20:12:35.575331 B1:a0f83180
306 20:12:35.575534
307 20:12:35.575736 TE: 71022
308 20:12:35.575939
309 20:12:35.580447 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 20:12:35.580681
311 20:12:35.586047 Board ID = 1
312 20:12:35.586279 Set cpu clk to 24M
313 20:12:35.586486 Set clk81 to 24M
314 20:12:35.591636 Use GP1_pll as DSU clk.
315 20:12:35.591867 DSU clk: 1200 Mhz
316 20:12:35.592094 CPU clk: 1200 MHz
317 20:12:35.597187 Set clk81 to 166.6M
318 20:12:35.602905 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 20:12:35.603141 board id: 1
320 20:12:35.610230 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 20:12:35.620849 fw parse done
322 20:12:35.626828 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 20:12:35.669497 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 20:12:35.680408 PIEI prepare done
325 20:12:35.680922 fastboot data load
326 20:12:35.681382 fastboot data verify
327 20:12:35.685987 verify result: 266
328 20:12:35.691566 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 20:12:35.692109 LPDDR4 probe
330 20:12:35.692570 ddr clk to 1584MHz
331 20:12:35.699558 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 20:12:35.736864
333 20:12:35.737396 dmc_version 0001
334 20:12:35.743515 Check phy result
335 20:12:35.749413 INFO : End of CA training
336 20:12:35.749923 INFO : End of initialization
337 20:12:35.754984 INFO : Training has run successfully!
338 20:12:35.755475 Check phy result
339 20:12:35.761044 INFO : End of initialization
340 20:12:35.761562 INFO : End of read enable training
341 20:12:35.766325 INFO : End of fine write leveling
342 20:12:35.771931 INFO : End of Write leveling coarse delay
343 20:12:35.772465 INFO : Training has run successfully!
344 20:12:35.772910 Check phy result
345 20:12:35.777435 INFO : End of initialization
346 20:12:35.777933 INFO : End of read dq deskew training
347 20:12:35.783087 INFO : End of MPR read delay center optimization
348 20:12:35.788650 INFO : End of write delay center optimization
349 20:12:35.794234 INFO : End of read delay center optimization
350 20:12:35.794732 INFO : End of max read latency training
351 20:12:35.799901 INFO : Training has run successfully!
352 20:12:35.800436 1D training succeed
353 20:12:35.809104 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 20:12:35.856664 Check phy result
355 20:12:35.857175 INFO : End of initialization
356 20:12:35.878963 INFO : End of 2D read delay Voltage center optimization
357 20:12:35.898141 INFO : End of 2D read delay Voltage center optimization
358 20:12:35.950011 INFO : End of 2D write delay Voltage center optimization
359 20:12:35.999205 INFO : End of 2D write delay Voltage center optimization
360 20:12:36.004675 INFO : Training has run successfully!
361 20:12:36.005173
362 20:12:36.005621 channel==0
363 20:12:36.010231 RxClkDly_Margin_A0==78 ps 8
364 20:12:36.010704 TxDqDly_Margin_A0==98 ps 10
365 20:12:36.015848 RxClkDly_Margin_A1==88 ps 9
366 20:12:36.016367 TxDqDly_Margin_A1==88 ps 9
367 20:12:36.016819 TrainedVREFDQ_A0==75
368 20:12:36.021528 TrainedVREFDQ_A1==74
369 20:12:36.022005 VrefDac_Margin_A0==24
370 20:12:36.022443 DeviceVref_Margin_A0==39
371 20:12:36.027127 VrefDac_Margin_A1==23
372 20:12:36.027611 DeviceVref_Margin_A1==40
373 20:12:36.028088
374 20:12:36.028558
375 20:12:36.029044 channel==1
376 20:12:36.032735 RxClkDly_Margin_A0==78 ps 8
377 20:12:36.033319 TxDqDly_Margin_A0==98 ps 10
378 20:12:36.038291 RxClkDly_Margin_A1==78 ps 8
379 20:12:36.038841 TxDqDly_Margin_A1==88 ps 9
380 20:12:36.043917 TrainedVREFDQ_A0==78
381 20:12:36.044491 TrainedVREFDQ_A1==75
382 20:12:36.044974 VrefDac_Margin_A0==22
383 20:12:36.049458 DeviceVref_Margin_A0==36
384 20:12:36.049982 VrefDac_Margin_A1==22
385 20:12:36.055102 DeviceVref_Margin_A1==39
386 20:12:36.055618
387 20:12:36.056131 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 20:12:36.056597
389 20:12:36.088681 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
390 20:12:36.089362 2D training succeed
391 20:12:36.094293 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 20:12:36.099917 auto size-- 65535DDR cs0 size: 2048MB
393 20:12:36.100460 DDR cs1 size: 2048MB
394 20:12:36.105454 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 20:12:36.105945 cs0 DataBus test pass
396 20:12:36.111101 cs1 DataBus test pass
397 20:12:36.111584 cs0 AddrBus test pass
398 20:12:36.112060 cs1 AddrBus test pass
399 20:12:36.112502
400 20:12:36.116683 100bdlr_step_size ps== 478
401 20:12:36.117178 result report
402 20:12:36.122294 boot times 0Enable ddr reg access
403 20:12:36.127462 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 20:12:36.141321 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 20:12:36.796317 bl2z: ptr: 05129330, size: 00001e40
406 20:12:36.804023 0.0;M3 CHK:0;cm4_sp_mode 0
407 20:12:36.804575 MVN_1=0x00000000
408 20:12:36.805033 MVN_2=0x00000000
409 20:12:36.815490 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 20:12:36.816029 OPS=0x04
411 20:12:36.816496 ring efuse init
412 20:12:36.821148 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 20:12:36.821645 [0.017310 Inits done]
414 20:12:36.822093 secure task start!
415 20:12:36.828418 high task start!
416 20:12:36.828903 low task start!
417 20:12:36.829349 run into bl31
418 20:12:36.837029 NOTICE: BL31: v1.3(release):4fc40b1
419 20:12:36.844878 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 20:12:36.845372 NOTICE: BL31: G12A normal boot!
421 20:12:36.860412 NOTICE: BL31: BL33 decompress pass
422 20:12:36.866140 ERROR: Error initializing runtime service opteed_fast
423 20:12:38.110614 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 20:12:38.111043 bl2_stage_init 0x01
425 20:12:38.111289 bl2_stage_init 0x81
426 20:12:38.116016 hw id: 0x0000 - pwm id 0x01
427 20:12:38.116339 bl2_stage_init 0xc1
428 20:12:38.121593 bl2_stage_init 0x02
429 20:12:38.122051
430 20:12:38.122429 L0:00000000
431 20:12:38.122799 L1:00000703
432 20:12:38.123061 L2:00008067
433 20:12:38.123288 L3:15000000
434 20:12:38.127287 S1:00000000
435 20:12:38.127590 B2:20282000
436 20:12:38.127827 B1:a0f83180
437 20:12:38.128090
438 20:12:38.128327 TE: 72939
439 20:12:38.128567
440 20:12:38.132767 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 20:12:38.133214
442 20:12:38.138485 Board ID = 1
443 20:12:38.138807 Set cpu clk to 24M
444 20:12:38.139039 Set clk81 to 24M
445 20:12:38.144019 Use GP1_pll as DSU clk.
446 20:12:38.144511 DSU clk: 1200 Mhz
447 20:12:38.144898 CPU clk: 1200 MHz
448 20:12:38.149606 Set clk81 to 166.6M
449 20:12:38.155215 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 20:12:38.155549 board id: 1
451 20:12:38.162405 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 20:12:38.173372 fw parse done
453 20:12:38.179277 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 20:12:38.222386 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 20:12:38.233595 PIEI prepare done
456 20:12:38.234784 fastboot data load
457 20:12:38.235290 fastboot data verify
458 20:12:38.239175 verify result: 266
459 20:12:38.246096 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 20:12:38.246604 LPDDR4 probe
461 20:12:38.247001 ddr clk to 1584MHz
462 20:12:39.607179 Load SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 20:12:39.607815 bl2_stage_init 0x01
464 20:12:39.608299 bl2_stage_init 0x81
465 20:12:39.612717 hw id: 0x0000 - pwm id 0x01
466 20:12:39.613277 bl2_stage_init 0xc1
467 20:12:39.618342 bl2_stage_init 0x02
468 20:12:39.618866
469 20:12:39.619342 L0:00000000
470 20:12:39.619777 L1:00000703
471 20:12:39.620231 L2:00008067
472 20:12:39.620636 L3:15000000
473 20:12:39.623784 S1:00000000
474 20:12:39.624271 B2:20282000
475 20:12:39.624694 B1:a0f83180
476 20:12:39.625106
477 20:12:39.625505 TE: 68631
478 20:12:39.625918
479 20:12:39.629449 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 20:12:39.629945
481 20:12:39.634998 Board ID = 1
482 20:12:39.635499 Set cpu clk to 24M
483 20:12:39.635936 Set clk81 to 24M
484 20:12:39.640700 Use GP1_pll as DSU clk.
485 20:12:39.641206 DSU clk: 1200 Mhz
486 20:12:39.641630 CPU clk: 1200 MHz
487 20:12:39.646220 Set clk81 to 166.6M
488 20:12:39.651826 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 20:12:39.652355 board id: 1
490 20:12:39.659070 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 20:12:39.669958 fw parse done
492 20:12:39.675915 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 20:12:39.719009 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 20:12:39.730262 PIEI prepare done
495 20:12:39.730808 fastboot data load
496 20:12:39.731222 fastboot data verify
497 20:12:39.735846 verify result: 266
498 20:12:39.741441 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 20:12:39.741962 LPDDR4 probe
500 20:12:39.742388 ddr clk to 1584MHz
501 20:12:39.749354 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 20:12:39.787176
503 20:12:39.787784 dmc_version 0001
504 20:12:39.794148 Check phy result
505 20:12:39.800188 INFO : End of CA training
506 20:12:39.800719 INFO : End of initialization
507 20:12:39.805794 INFO : Training has run successfully!
508 20:12:39.806280 Check phy result
509 20:12:39.811346 INFO : End of initialization
510 20:12:39.811907 INFO : End of read enable training
511 20:12:39.816957 INFO : End of fine write leveling
512 20:12:39.822523 INFO : End of Write leveling coarse delay
513 20:12:39.823032 INFO : Training has run successfully!
514 20:12:39.823445 Check phy result
515 20:12:39.828172 INFO : End of initialization
516 20:12:39.828704 INFO : End of read dq deskew training
517 20:12:39.833801 INFO : End of MPR read delay center optimization
518 20:12:39.839360 INFO : End of write delay center optimization
519 20:12:39.844947 INFO : End of read delay center optimization
520 20:12:39.845466 INFO : End of max read latency training
521 20:12:39.850521 INFO : Training has run successfully!
522 20:12:39.851047 1D training succeed
523 20:12:39.859747 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 20:12:39.908067 Check phy result
525 20:12:39.908509 INFO : End of initialization
526 20:12:39.935459 INFO : End of 2D read delay Voltage center optimization
527 20:12:39.959637 INFO : End of 2D read delay Voltage center optimization
528 20:12:40.016377 INFO : End of 2D write delay Voltage center optimization
529 20:12:40.070405 INFO : End of 2D write delay Voltage center optimization
530 20:12:40.075897 INFO : Training has run successfully!
531 20:12:40.076457
532 20:12:40.076913 channel==0
533 20:12:40.081390 RxClkDly_Margin_A0==78 ps 8
534 20:12:40.081860 TxDqDly_Margin_A0==98 ps 10
535 20:12:40.084677 RxClkDly_Margin_A1==88 ps 9
536 20:12:40.085157 TxDqDly_Margin_A1==88 ps 9
537 20:12:40.090225 TrainedVREFDQ_A0==74
538 20:12:40.090742 TrainedVREFDQ_A1==74
539 20:12:40.091171 VrefDac_Margin_A0==24
540 20:12:40.095840 DeviceVref_Margin_A0==40
541 20:12:40.096354 VrefDac_Margin_A1==23
542 20:12:40.101435 DeviceVref_Margin_A1==40
543 20:12:40.101932
544 20:12:40.102349
545 20:12:40.102755 channel==1
546 20:12:40.103150 RxClkDly_Margin_A0==78 ps 8
547 20:12:40.107000 TxDqDly_Margin_A0==98 ps 10
548 20:12:40.107443 RxClkDly_Margin_A1==78 ps 8
549 20:12:40.112675 TxDqDly_Margin_A1==88 ps 9
550 20:12:40.113164 TrainedVREFDQ_A0==78
551 20:12:40.113584 TrainedVREFDQ_A1==75
552 20:12:40.118238 VrefDac_Margin_A0==22
553 20:12:40.118739 DeviceVref_Margin_A0==36
554 20:12:40.123852 VrefDac_Margin_A1==22
555 20:12:40.124373 DeviceVref_Margin_A1==38
556 20:12:40.124800
557 20:12:40.129404 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 20:12:40.129880
559 20:12:40.157512 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
560 20:12:40.163066 2D training succeed
561 20:12:40.168683 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 20:12:40.169494 auto size-- 65535DDR cs0 size: 2048MB
563 20:12:40.174277 DDR cs1 size: 2048MB
564 20:12:40.175089 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 20:12:40.179893 cs0 DataBus test pass
566 20:12:40.180538 cs1 DataBus test pass
567 20:12:40.180965 cs0 AddrBus test pass
568 20:12:40.185446 cs1 AddrBus test pass
569 20:12:40.186018
570 20:12:40.186751 100bdlr_step_size ps== 478
571 20:12:40.187337 result report
572 20:12:40.191122 boot times 0Enable ddr reg access
573 20:12:40.198544 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 20:12:40.212626 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 20:12:40.871922 bl2z: ptr: 05129330, size: 00001e40
576 20:12:40.878304 0.0;M3 CHK:0;cm4_sp_mode 0
577 20:12:40.878661 MVN_1=0x00000000
578 20:12:40.878899 MVN_2=0x00000000
579 20:12:40.889919 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 20:12:40.890304 OPS=0x04
581 20:12:40.890540 ring efuse init
582 20:12:40.892793 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 20:12:40.898848 [0.017354 Inits done]
584 20:12:40.899214 secure task start!
585 20:12:40.899436 high task start!
586 20:12:40.899658 low task start!
587 20:12:40.903033 run into bl31
588 20:12:40.911722 NOTICE: BL31: v1.3(release):4fc40b1
589 20:12:40.919635 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 20:12:40.920162 NOTICE: BL31: G12A normal boot!
591 20:12:40.935215 NOTICE: BL31: BL33 decompress pass
592 20:12:40.940828 ERROR: Error initializing runtime service opteed_fast
593 20:12:42.307811 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 20:12:42.308283 bl2_stage_init 0x01
595 20:12:42.308502 bl2_stage_init 0x81
596 20:12:42.313464 hw id: 0x0000 - pwm id 0x01
597 20:12:42.314735 bl2_stage_init 0xc1
598 20:12:42.316961 bl2_stage_init 0x02
599 20:12:42.317334
600 20:12:42.317548 L0:00000000
601 20:12:42.317755 L1:00000703
602 20:12:42.322356 L2:00008067
603 20:12:42.322783 L3:15000000
604 20:12:42.322998 S1:00000000
605 20:12:42.323202 B2:20282000
606 20:12:42.323403 B1:a0f83180
607 20:12:42.323603
608 20:12:42.328106 TE: 70316
609 20:12:42.328523
610 20:12:42.333719 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 20:12:42.334184
612 20:12:42.334455 Board ID = 1
613 20:12:42.334707 Set cpu clk to 24M
614 20:12:42.339221 Set clk81 to 24M
615 20:12:42.339664 Use GP1_pll as DSU clk.
616 20:12:42.339912 DSU clk: 1200 Mhz
617 20:12:42.344750 CPU clk: 1200 MHz
618 20:12:42.345197 Set clk81 to 166.6M
619 20:12:42.350304 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 20:12:42.350747 board id: 1
621 20:12:42.359833 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 20:12:42.370603 fw parse done
623 20:12:42.376624 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 20:12:42.419561 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 20:12:42.430032 PIEI prepare done
626 20:12:42.430454 fastboot data load
627 20:12:42.430681 fastboot data verify
628 20:12:42.435588 verify result: 266
629 20:12:42.441234 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 20:12:42.441709 LPDDR4 probe
631 20:12:42.442051 ddr clk to 1584MHz
632 20:12:42.451546 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 20:12:42.486528
634 20:12:42.487163 dmc_version 0001
635 20:12:42.493324 Check phy result
636 20:12:42.500640 INFO : End of CA training
637 20:12:42.501275 INFO : End of initialization
638 20:12:42.504762 INFO : Training has run successfully!
639 20:12:42.505302 Check phy result
640 20:12:42.510477 INFO : End of initialization
641 20:12:42.510896 INFO : End of read enable training
642 20:12:42.515806 INFO : End of fine write leveling
643 20:12:42.521394 INFO : End of Write leveling coarse delay
644 20:12:42.521845 INFO : Training has run successfully!
645 20:12:42.522117 Check phy result
646 20:12:42.526974 INFO : End of initialization
647 20:12:42.527368 INFO : End of read dq deskew training
648 20:12:42.532501 INFO : End of MPR read delay center optimization
649 20:12:42.538240 INFO : End of write delay center optimization
650 20:12:42.543704 INFO : End of read delay center optimization
651 20:12:42.544108 INFO : End of max read latency training
652 20:12:42.549304 INFO : Training has run successfully!
653 20:12:42.549663 1D training succeed
654 20:12:42.558442 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 20:12:42.606234 Check phy result
656 20:12:42.606722 INFO : End of initialization
657 20:12:42.628564 INFO : End of 2D read delay Voltage center optimization
658 20:12:42.647791 INFO : End of 2D read delay Voltage center optimization
659 20:12:42.699735 INFO : End of 2D write delay Voltage center optimization
660 20:12:42.748930 INFO : End of 2D write delay Voltage center optimization
661 20:12:42.754434 INFO : Training has run successfully!
662 20:12:42.755080
663 20:12:42.755642 channel==0
664 20:12:42.760047 RxClkDly_Margin_A0==69 ps 7
665 20:12:42.760696 TxDqDly_Margin_A0==98 ps 10
666 20:12:42.765493 RxClkDly_Margin_A1==88 ps 9
667 20:12:42.765801 TxDqDly_Margin_A1==88 ps 9
668 20:12:42.766030 TrainedVREFDQ_A0==74
669 20:12:42.770999 TrainedVREFDQ_A1==75
670 20:12:42.771295 VrefDac_Margin_A0==23
671 20:12:42.771500 DeviceVref_Margin_A0==40
672 20:12:42.776690 VrefDac_Margin_A1==23
673 20:12:42.777012 DeviceVref_Margin_A1==39
674 20:12:42.777227
675 20:12:42.777431
676 20:12:42.777630 channel==1
677 20:12:42.782285 RxClkDly_Margin_A0==78 ps 8
678 20:12:42.782588 TxDqDly_Margin_A0==98 ps 10
679 20:12:42.787824 RxClkDly_Margin_A1==78 ps 8
680 20:12:42.788136 TxDqDly_Margin_A1==88 ps 9
681 20:12:42.793415 TrainedVREFDQ_A0==78
682 20:12:42.793748 TrainedVREFDQ_A1==77
683 20:12:42.793958 VrefDac_Margin_A0==22
684 20:12:42.798973 DeviceVref_Margin_A0==36
685 20:12:42.799261 VrefDac_Margin_A1==22
686 20:12:42.804637 DeviceVref_Margin_A1==37
687 20:12:42.804940
688 20:12:42.805147 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 20:12:42.805349
690 20:12:42.838372 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
691 20:12:42.838768 2D training succeed
692 20:12:42.844015 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 20:12:42.849347 auto size-- 65535DDR cs0 size: 2048MB
694 20:12:42.849642 DDR cs1 size: 2048MB
695 20:12:42.854956 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 20:12:42.855252 cs0 DataBus test pass
697 20:12:42.860676 cs1 DataBus test pass
698 20:12:42.860997 cs0 AddrBus test pass
699 20:12:42.861227 cs1 AddrBus test pass
700 20:12:42.861437
701 20:12:42.866326 100bdlr_step_size ps== 478
702 20:12:42.866627 result report
703 20:12:42.871816 boot times 0Enable ddr reg access
704 20:12:42.876967 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 20:12:42.890721 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 20:12:43.545676 bl2z: ptr: 05129330, size: 00001e40
707 20:12:43.553594 0.0;M3 CHK:0;cm4_sp_mode 0
708 20:12:43.553954 MVN_1=0x00000000
709 20:12:43.554165 MVN_2=0x00000000
710 20:12:43.564973 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 20:12:43.565340 OPS=0x04
712 20:12:43.565556 ring efuse init
713 20:12:43.570842 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 20:12:43.571179 [0.017320 Inits done]
715 20:12:43.571389 secure task start!
716 20:12:43.577945 high task start!
717 20:12:43.578270 low task start!
718 20:12:43.578482 run into bl31
719 20:12:43.586551 NOTICE: BL31: v1.3(release):4fc40b1
720 20:12:43.594399 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 20:12:43.594719 NOTICE: BL31: G12A normal boot!
722 20:12:43.609839 NOTICE: BL31: BL33 decompress pass
723 20:12:43.615513 ERROR: Error initializing runtime service opteed_fast
724 20:12:44.409693
725 20:12:44.410111
726 20:12:44.415144 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 20:12:44.415479
728 20:12:44.418594 Model: Libre Computer AML-S905D3-CC Solitude
729 20:12:44.565505 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 20:12:44.580693 DRAM: 2 GiB (effective 3.8 GiB)
731 20:12:44.681741 Core: 406 devices, 33 uclasses, devicetree: separate
732 20:12:44.687633 WDT: Not starting watchdog@f0d0
733 20:12:44.712733 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 20:12:44.724950 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 20:12:44.729901 ** Bad device specification mmc 0 **
736 20:12:44.739963 Card did not respond to voltage select! : -110
737 20:12:44.747625 ** Bad device specification mmc 0 **
738 20:12:44.747935 Couldn't find partition mmc 0
739 20:12:44.755932 Card did not respond to voltage select! : -110
740 20:12:44.761318 ** Bad device specification mmc 0 **
741 20:12:44.761615 Couldn't find partition mmc 0
742 20:12:44.766478 Error: could not access storage.
743 20:12:45.063073 Net: eth0: ethernet@ff3f0000
744 20:12:45.063715 starting USB...
745 20:12:45.307684 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 20:12:45.308305 Starting the controller
747 20:12:45.314637 USB XHCI 1.10
748 20:12:46.870560 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 20:12:46.878841 scanning usb for storage devices... 0 Storage Device(s) found
751 20:12:46.930595 Hit any key to stop autoboot: 1
752 20:12:46.931276 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 20:12:46.931626 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 20:12:46.931897 Setting prompt string to ['=>']
755 20:12:46.932198 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 20:12:46.944878 0
757 20:12:46.945561 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 20:12:47.046392 => setenv autoload no
760 20:12:47.047107 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 20:12:47.051786 setenv autoload no
763 20:12:47.152985 => setenv initrd_high 0xffffffff
764 20:12:47.153539 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 20:12:47.158013 setenv initrd_high 0xffffffff
767 20:12:47.259031 => setenv fdt_high 0xffffffff
768 20:12:47.259570 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 20:12:47.264196 setenv fdt_high 0xffffffff
771 20:12:47.365252 => dhcp
772 20:12:47.365795 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 20:12:47.370190 dhcp
774 20:12:48.025826 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 20:12:48.026452 Speed: 1000, full duplex
776 20:12:48.026859 BOOTP broadcast 1
777 20:12:48.273967 BOOTP broadcast 2
778 20:12:48.286887 DHCP client bound to address 192.168.6.21 (260 ms)
780 20:12:48.388571 => setenv serverip 192.168.6.2
781 20:12:48.389519 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
782 20:12:48.393980 setenv serverip 192.168.6.2
784 20:12:48.495761 => tftpboot 0x01080000 954416/tftp-deploy-9jv0ohyk/kernel/uImage
785 20:12:48.496818 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
786 20:12:48.504019 tftpboot 0x01080000 954416/tftp-deploy-9jv0ohyk/kernel/uImage
787 20:12:48.504694 Speed: 1000, full duplex
788 20:12:48.505219 Using ethernet@ff3f0000 device
789 20:12:48.509292 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
790 20:12:48.515253 Filename '954416/tftp-deploy-9jv0ohyk/kernel/uImage'.
791 20:12:48.518430 Load address: 0x1080000
792 20:12:51.398137 Loading: *################################################## 43.6 MiB
793 20:12:51.398771 15.1 MiB/s
794 20:12:51.399200 done
795 20:12:51.402643 Bytes transferred = 45713984 (2b98a40 hex)
797 20:12:51.504151 => tftpboot 0x08000000 954416/tftp-deploy-9jv0ohyk/ramdisk/ramdisk.cpio.gz.uboot
798 20:12:51.504894 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
799 20:12:51.512727 tftpboot 0x08000000 954416/tftp-deploy-9jv0ohyk/ramdisk/ramdisk.cpio.gz.uboot
800 20:12:51.513282 Speed: 1000, full duplex
801 20:12:51.513690 Using ethernet@ff3f0000 device
802 20:12:51.518281 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
803 20:12:51.527960 Filename '954416/tftp-deploy-9jv0ohyk/ramdisk/ramdisk.cpio.gz.uboot'.
804 20:12:51.528560 Load address: 0x8000000
805 20:12:56.867578 Loading: *######################### UDP wrong checksum 000000ff 00000ffb
806 20:12:56.909700 UDP wrong checksum 000000ff 0000a9ed
807 20:13:00.766243 T ######################## UDP wrong checksum 0000000f 000095a2
808 20:13:05.766815 T UDP wrong checksum 0000000f 000095a2
809 20:13:15.768557 T T UDP wrong checksum 0000000f 000095a2
810 20:13:34.238656 T T T UDP wrong checksum 000000ff 000060e7
811 20:13:34.280630 UDP wrong checksum 000000ff 0000f1d9
812 20:13:35.772381 T UDP wrong checksum 0000000f 000095a2
813 20:13:50.776647 T T
814 20:13:50.777283 Retry count exceeded; starting again
816 20:13:50.778714 end: 2.4.3 bootloader-commands (duration 00:01:04) [common]
819 20:13:50.780612 end: 2.4 uboot-commands (duration 00:01:23) [common]
821 20:13:50.781982 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
823 20:13:50.783027 end: 2 uboot-action (duration 00:01:23) [common]
825 20:13:50.784569 Cleaning after the job
826 20:13:50.785105 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954416/tftp-deploy-9jv0ohyk/ramdisk
827 20:13:50.786222 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954416/tftp-deploy-9jv0ohyk/kernel
828 20:13:50.793473 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954416/tftp-deploy-9jv0ohyk/dtb
829 20:13:50.794567 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954416/tftp-deploy-9jv0ohyk/modules
830 20:13:50.805635 start: 4.1 power-off (timeout 00:00:30) [common]
831 20:13:50.806653 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
832 20:13:50.842163 >> OK - accepted request
833 20:13:50.844338 Returned 0 in 0 seconds
834 20:13:50.945190 end: 4.1 power-off (duration 00:00:00) [common]
836 20:13:50.946840 start: 4.2 read-feedback (timeout 00:10:00) [common]
837 20:13:50.947933 Listened to connection for namespace 'common' for up to 1s
838 20:13:51.947894 Finalising connection for namespace 'common'
839 20:13:51.948661 Disconnecting from shell: Finalise
840 20:13:51.949186 =>
841 20:13:52.050177 end: 4.2 read-feedback (duration 00:00:01) [common]
842 20:13:52.050790 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/954416
843 20:13:52.717036 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/954416
844 20:13:52.717660 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.