Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 6
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 20:11:26.785137 lava-dispatcher, installed at version: 2024.01
2 20:11:26.785928 start: 0 validate
3 20:11:26.786404 Start time: 2024-11-07 20:11:26.786375+00:00 (UTC)
4 20:11:26.786929 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:11:26.787480 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 20:11:26.835341 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:11:26.835879 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-244-g7a812b09d88be%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 20:11:26.869037 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:11:26.869650 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-244-g7a812b09d88be%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:11:26.904189 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:11:26.904664 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:11:26.939964 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 20:11:26.940482 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-244-g7a812b09d88be%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 20:11:26.984021 validate duration: 0.20
16 20:11:26.985516 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:11:26.986127 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:11:26.986731 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:11:26.987674 Not decompressing ramdisk as can be used compressed.
20 20:11:26.988494 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 20:11:26.989018 saving as /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/ramdisk/initrd.cpio.gz
22 20:11:26.989520 total size: 5628169 (5 MB)
23 20:11:27.036635 progress 0 % (0 MB)
24 20:11:27.045432 progress 5 % (0 MB)
25 20:11:27.054543 progress 10 % (0 MB)
26 20:11:27.062795 progress 15 % (0 MB)
27 20:11:27.069625 progress 20 % (1 MB)
28 20:11:27.073465 progress 25 % (1 MB)
29 20:11:27.077585 progress 30 % (1 MB)
30 20:11:27.081782 progress 35 % (1 MB)
31 20:11:27.085512 progress 40 % (2 MB)
32 20:11:27.089606 progress 45 % (2 MB)
33 20:11:27.093391 progress 50 % (2 MB)
34 20:11:27.097478 progress 55 % (2 MB)
35 20:11:27.101584 progress 60 % (3 MB)
36 20:11:27.105299 progress 65 % (3 MB)
37 20:11:27.109495 progress 70 % (3 MB)
38 20:11:27.113164 progress 75 % (4 MB)
39 20:11:27.117266 progress 80 % (4 MB)
40 20:11:27.120969 progress 85 % (4 MB)
41 20:11:27.125086 progress 90 % (4 MB)
42 20:11:27.129062 progress 95 % (5 MB)
43 20:11:27.132368 progress 100 % (5 MB)
44 20:11:27.133042 5 MB downloaded in 0.14 s (37.40 MB/s)
45 20:11:27.133601 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:11:27.134532 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:11:27.134852 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:11:27.135148 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:11:27.135635 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-244-g7a812b09d88be/arm64/defconfig/gcc-12/kernel/Image
51 20:11:27.135920 saving as /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/kernel/Image
52 20:11:27.136183 total size: 45713920 (43 MB)
53 20:11:27.136409 No compression specified
54 20:11:27.175446 progress 0 % (0 MB)
55 20:11:27.204520 progress 5 % (2 MB)
56 20:11:27.233722 progress 10 % (4 MB)
57 20:11:27.262374 progress 15 % (6 MB)
58 20:11:27.291877 progress 20 % (8 MB)
59 20:11:27.320073 progress 25 % (10 MB)
60 20:11:27.348866 progress 30 % (13 MB)
61 20:11:27.377913 progress 35 % (15 MB)
62 20:11:27.407089 progress 40 % (17 MB)
63 20:11:27.435793 progress 45 % (19 MB)
64 20:11:27.464618 progress 50 % (21 MB)
65 20:11:27.493746 progress 55 % (24 MB)
66 20:11:27.522664 progress 60 % (26 MB)
67 20:11:27.551165 progress 65 % (28 MB)
68 20:11:27.580472 progress 70 % (30 MB)
69 20:11:27.609414 progress 75 % (32 MB)
70 20:11:27.638099 progress 80 % (34 MB)
71 20:11:27.666528 progress 85 % (37 MB)
72 20:11:27.695534 progress 90 % (39 MB)
73 20:11:27.724638 progress 95 % (41 MB)
74 20:11:27.752915 progress 100 % (43 MB)
75 20:11:27.753461 43 MB downloaded in 0.62 s (70.63 MB/s)
76 20:11:27.753944 end: 1.2.1 http-download (duration 00:00:01) [common]
78 20:11:27.754757 end: 1.2 download-retry (duration 00:00:01) [common]
79 20:11:27.755033 start: 1.3 download-retry (timeout 00:09:59) [common]
80 20:11:27.755300 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 20:11:27.755765 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-244-g7a812b09d88be/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 20:11:27.756058 saving as /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/dtb/meson-g12b-a311d-libretech-cc.dtb
83 20:11:27.756272 total size: 54703 (0 MB)
84 20:11:27.756479 No compression specified
85 20:11:27.798638 progress 59 % (0 MB)
86 20:11:27.799484 progress 100 % (0 MB)
87 20:11:27.800058 0 MB downloaded in 0.04 s (1.19 MB/s)
88 20:11:27.800529 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:11:27.801345 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:11:27.801605 start: 1.4 download-retry (timeout 00:09:59) [common]
92 20:11:27.801868 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 20:11:27.802314 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 20:11:27.802556 saving as /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/nfsrootfs/full.rootfs.tar
95 20:11:27.802762 total size: 120894716 (115 MB)
96 20:11:27.802970 Using unxz to decompress xz
97 20:11:27.844356 progress 0 % (0 MB)
98 20:11:28.641173 progress 5 % (5 MB)
99 20:11:29.468685 progress 10 % (11 MB)
100 20:11:30.260357 progress 15 % (17 MB)
101 20:11:30.991851 progress 20 % (23 MB)
102 20:11:31.582879 progress 25 % (28 MB)
103 20:11:32.411631 progress 30 % (34 MB)
104 20:11:33.197321 progress 35 % (40 MB)
105 20:11:33.543364 progress 40 % (46 MB)
106 20:11:33.922665 progress 45 % (51 MB)
107 20:11:34.647413 progress 50 % (57 MB)
108 20:11:35.538937 progress 55 % (63 MB)
109 20:11:36.328256 progress 60 % (69 MB)
110 20:11:37.162153 progress 65 % (74 MB)
111 20:11:38.082891 progress 70 % (80 MB)
112 20:11:39.055640 progress 75 % (86 MB)
113 20:11:39.984185 progress 80 % (92 MB)
114 20:11:40.882723 progress 85 % (98 MB)
115 20:11:41.885480 progress 90 % (103 MB)
116 20:11:42.797731 progress 95 % (109 MB)
117 20:11:43.772808 progress 100 % (115 MB)
118 20:11:43.787485 115 MB downloaded in 15.98 s (7.21 MB/s)
119 20:11:43.788442 end: 1.4.1 http-download (duration 00:00:16) [common]
121 20:11:43.790000 end: 1.4 download-retry (duration 00:00:16) [common]
122 20:11:43.790504 start: 1.5 download-retry (timeout 00:09:43) [common]
123 20:11:43.791000 start: 1.5.1 http-download (timeout 00:09:43) [common]
124 20:11:43.791765 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-244-g7a812b09d88be/arm64/defconfig/gcc-12/modules.tar.xz
125 20:11:43.792244 saving as /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/modules/modules.tar
126 20:11:43.792641 total size: 11609200 (11 MB)
127 20:11:43.793047 Using unxz to decompress xz
128 20:11:43.841803 progress 0 % (0 MB)
129 20:11:43.907698 progress 5 % (0 MB)
130 20:11:43.980917 progress 10 % (1 MB)
131 20:11:44.075597 progress 15 % (1 MB)
132 20:11:44.166415 progress 20 % (2 MB)
133 20:11:44.246034 progress 25 % (2 MB)
134 20:11:44.321167 progress 30 % (3 MB)
135 20:11:44.394471 progress 35 % (3 MB)
136 20:11:44.472222 progress 40 % (4 MB)
137 20:11:44.547589 progress 45 % (5 MB)
138 20:11:44.635417 progress 50 % (5 MB)
139 20:11:44.711899 progress 55 % (6 MB)
140 20:11:44.798285 progress 60 % (6 MB)
141 20:11:44.878436 progress 65 % (7 MB)
142 20:11:44.957245 progress 70 % (7 MB)
143 20:11:45.041370 progress 75 % (8 MB)
144 20:11:45.125486 progress 80 % (8 MB)
145 20:11:45.205806 progress 85 % (9 MB)
146 20:11:45.285525 progress 90 % (9 MB)
147 20:11:45.362939 progress 95 % (10 MB)
148 20:11:45.439909 progress 100 % (11 MB)
149 20:11:45.451111 11 MB downloaded in 1.66 s (6.68 MB/s)
150 20:11:45.451711 end: 1.5.1 http-download (duration 00:00:02) [common]
152 20:11:45.453151 end: 1.5 download-retry (duration 00:00:02) [common]
153 20:11:45.453674 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 20:11:45.454190 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 20:12:01.930458 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/954419/extract-nfsrootfs-ftsfeezm
156 20:12:01.931072 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 20:12:01.931357 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 20:12:01.932101 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf
159 20:12:01.932568 makedir: /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin
160 20:12:01.932895 makedir: /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/tests
161 20:12:01.933204 makedir: /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/results
162 20:12:01.933528 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-add-keys
163 20:12:01.934045 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-add-sources
164 20:12:01.934545 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-background-process-start
165 20:12:01.935035 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-background-process-stop
166 20:12:01.935606 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-common-functions
167 20:12:01.936169 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-echo-ipv4
168 20:12:01.936670 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-install-packages
169 20:12:01.937145 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-installed-packages
170 20:12:01.937677 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-os-build
171 20:12:01.938153 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-probe-channel
172 20:12:01.938625 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-probe-ip
173 20:12:01.939090 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-target-ip
174 20:12:01.939592 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-target-mac
175 20:12:01.940146 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-target-storage
176 20:12:01.940647 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-test-case
177 20:12:01.941121 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-test-event
178 20:12:01.941585 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-test-feedback
179 20:12:01.942047 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-test-raise
180 20:12:01.942507 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-test-reference
181 20:12:01.942975 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-test-runner
182 20:12:01.943475 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-test-set
183 20:12:01.943967 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-test-shell
184 20:12:01.944504 Updating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-add-keys (debian)
185 20:12:01.945027 Updating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-add-sources (debian)
186 20:12:01.945528 Updating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-install-packages (debian)
187 20:12:01.946021 Updating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-installed-packages (debian)
188 20:12:01.946506 Updating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/bin/lava-os-build (debian)
189 20:12:01.946932 Creating /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/environment
190 20:12:01.947290 LAVA metadata
191 20:12:01.947544 - LAVA_JOB_ID=954419
192 20:12:01.947756 - LAVA_DISPATCHER_IP=192.168.6.2
193 20:12:01.948130 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 20:12:01.949079 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 20:12:01.949386 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 20:12:01.949591 skipped lava-vland-overlay
197 20:12:01.949828 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 20:12:01.950079 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 20:12:01.950292 skipped lava-multinode-overlay
200 20:12:01.950530 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 20:12:01.950776 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 20:12:01.951018 Loading test definitions
203 20:12:01.951289 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 20:12:01.951505 Using /lava-954419 at stage 0
205 20:12:01.952612 uuid=954419_1.6.2.4.1 testdef=None
206 20:12:01.952917 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 20:12:01.953176 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 20:12:01.954692 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 20:12:01.955465 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 20:12:01.957401 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 20:12:01.958214 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 20:12:01.960031 runner path: /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/0/tests/0_timesync-off test_uuid 954419_1.6.2.4.1
215 20:12:01.960571 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 20:12:01.961367 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 20:12:01.961586 Using /lava-954419 at stage 0
219 20:12:01.961930 Fetching tests from https://github.com/kernelci/test-definitions.git
220 20:12:01.962211 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/0/tests/1_kselftest-alsa'
221 20:12:10.803835 Running '/usr/bin/git checkout kernelci.org
222 20:12:11.251909 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 20:12:11.253384 uuid=954419_1.6.2.4.5 testdef=None
224 20:12:11.253726 end: 1.6.2.4.5 git-repo-action (duration 00:00:09) [common]
226 20:12:11.254466 start: 1.6.2.4.6 test-overlay (timeout 00:09:16) [common]
227 20:12:11.257312 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 20:12:11.258130 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:16) [common]
230 20:12:11.261877 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 20:12:11.262727 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:16) [common]
233 20:12:11.266302 runner path: /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/0/tests/1_kselftest-alsa test_uuid 954419_1.6.2.4.5
234 20:12:11.266591 BOARD='meson-g12b-a311d-libretech-cc'
235 20:12:11.266797 BRANCH='broonie-sound'
236 20:12:11.266992 SKIPFILE='/dev/null'
237 20:12:11.267189 SKIP_INSTALL='True'
238 20:12:11.267382 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-244-g7a812b09d88be/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 20:12:11.267580 TST_CASENAME=''
240 20:12:11.267772 TST_CMDFILES='alsa'
241 20:12:11.268344 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 20:12:11.269131 Creating lava-test-runner.conf files
244 20:12:11.269334 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/954419/lava-overlay-01rr_6hf/lava-954419/0 for stage 0
245 20:12:11.269694 - 0_timesync-off
246 20:12:11.269946 - 1_kselftest-alsa
247 20:12:11.270283 end: 1.6.2.4 test-definition (duration 00:00:09) [common]
248 20:12:11.270564 start: 1.6.2.5 compress-overlay (timeout 00:09:16) [common]
249 20:12:34.767919 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 20:12:34.768399 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:52) [common]
251 20:12:34.768699 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 20:12:34.769011 end: 1.6.2 lava-overlay (duration 00:00:33) [common]
253 20:12:34.769307 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:52) [common]
254 20:12:35.394232 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 20:12:35.394726 start: 1.6.4 extract-modules (timeout 00:08:52) [common]
256 20:12:35.395001 extracting modules file /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954419/extract-nfsrootfs-ftsfeezm
257 20:12:36.786433 extracting modules file /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954419/extract-overlay-ramdisk-ts04u07k/ramdisk
258 20:12:38.330129 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 20:12:38.330605 start: 1.6.5 apply-overlay-tftp (timeout 00:08:49) [common]
260 20:12:38.330881 [common] Applying overlay to NFS
261 20:12:38.331094 [common] Applying overlay /var/lib/lava/dispatcher/tmp/954419/compress-overlay-s6mphksg/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/954419/extract-nfsrootfs-ftsfeezm
262 20:12:41.085209 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 20:12:41.085707 start: 1.6.6 prepare-kernel (timeout 00:08:46) [common]
264 20:12:41.086038 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:46) [common]
265 20:12:41.086303 Converting downloaded kernel to a uImage
266 20:12:41.086632 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/kernel/Image /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/kernel/uImage
267 20:12:41.767829 output: Image Name:
268 20:12:41.768355 output: Created: Thu Nov 7 20:12:41 2024
269 20:12:41.768616 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 20:12:41.768896 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 20:12:41.769153 output: Load Address: 01080000
272 20:12:41.769376 output: Entry Point: 01080000
273 20:12:41.769653 output:
274 20:12:41.770129 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 20:12:41.770460 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 20:12:41.771050 start: 1.6.7 configure-preseed-file (timeout 00:08:45) [common]
277 20:12:41.771521 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 20:12:41.771881 start: 1.6.8 compress-ramdisk (timeout 00:08:45) [common]
279 20:12:41.772263 Building ramdisk /var/lib/lava/dispatcher/tmp/954419/extract-overlay-ramdisk-ts04u07k/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/954419/extract-overlay-ramdisk-ts04u07k/ramdisk
280 20:12:44.093219 >> 166792 blocks
281 20:12:52.126650 Adding RAMdisk u-boot header.
282 20:12:52.127333 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/954419/extract-overlay-ramdisk-ts04u07k/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/954419/extract-overlay-ramdisk-ts04u07k/ramdisk.cpio.gz.uboot
283 20:12:52.374534 output: Image Name:
284 20:12:52.374964 output: Created: Thu Nov 7 20:12:52 2024
285 20:12:52.375426 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 20:12:52.375886 output: Data Size: 23433556 Bytes = 22884.33 KiB = 22.35 MiB
287 20:12:52.376567 output: Load Address: 00000000
288 20:12:52.377027 output: Entry Point: 00000000
289 20:12:52.377448 output:
290 20:12:52.378376 rename /var/lib/lava/dispatcher/tmp/954419/extract-overlay-ramdisk-ts04u07k/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/ramdisk/ramdisk.cpio.gz.uboot
291 20:12:52.379099 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 20:12:52.379665 end: 1.6 prepare-tftp-overlay (duration 00:01:07) [common]
293 20:12:52.380288 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:35) [common]
294 20:12:52.380760 No LXC device requested
295 20:12:52.381281 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 20:12:52.381806 start: 1.8 deploy-device-env (timeout 00:08:35) [common]
297 20:12:52.382317 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 20:12:52.382745 Checking files for TFTP limit of 4294967296 bytes.
299 20:12:52.385506 end: 1 tftp-deploy (duration 00:01:25) [common]
300 20:12:52.386129 start: 2 uboot-action (timeout 00:05:00) [common]
301 20:12:52.386694 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 20:12:52.387220 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 20:12:52.387742 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 20:12:52.388330 Using kernel file from prepare-kernel: 954419/tftp-deploy-ri2_i088/kernel/uImage
305 20:12:52.388990 substitutions:
306 20:12:52.389420 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 20:12:52.389838 - {DTB_ADDR}: 0x01070000
308 20:12:52.390251 - {DTB}: 954419/tftp-deploy-ri2_i088/dtb/meson-g12b-a311d-libretech-cc.dtb
309 20:12:52.390668 - {INITRD}: 954419/tftp-deploy-ri2_i088/ramdisk/ramdisk.cpio.gz.uboot
310 20:12:52.391075 - {KERNEL_ADDR}: 0x01080000
311 20:12:52.391482 - {KERNEL}: 954419/tftp-deploy-ri2_i088/kernel/uImage
312 20:12:52.391887 - {LAVA_MAC}: None
313 20:12:52.392368 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/954419/extract-nfsrootfs-ftsfeezm
314 20:12:52.392785 - {NFS_SERVER_IP}: 192.168.6.2
315 20:12:52.393188 - {PRESEED_CONFIG}: None
316 20:12:52.393591 - {PRESEED_LOCAL}: None
317 20:12:52.393995 - {RAMDISK_ADDR}: 0x08000000
318 20:12:52.394389 - {RAMDISK}: 954419/tftp-deploy-ri2_i088/ramdisk/ramdisk.cpio.gz.uboot
319 20:12:52.394786 - {ROOT_PART}: None
320 20:12:52.395182 - {ROOT}: None
321 20:12:52.395574 - {SERVER_IP}: 192.168.6.2
322 20:12:52.395967 - {TEE_ADDR}: 0x83000000
323 20:12:52.396396 - {TEE}: None
324 20:12:52.396789 Parsed boot commands:
325 20:12:52.397171 - setenv autoload no
326 20:12:52.397561 - setenv initrd_high 0xffffffff
327 20:12:52.397947 - setenv fdt_high 0xffffffff
328 20:12:52.398333 - dhcp
329 20:12:52.398719 - setenv serverip 192.168.6.2
330 20:12:52.399110 - tftpboot 0x01080000 954419/tftp-deploy-ri2_i088/kernel/uImage
331 20:12:52.399506 - tftpboot 0x08000000 954419/tftp-deploy-ri2_i088/ramdisk/ramdisk.cpio.gz.uboot
332 20:12:52.399897 - tftpboot 0x01070000 954419/tftp-deploy-ri2_i088/dtb/meson-g12b-a311d-libretech-cc.dtb
333 20:12:52.400332 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/954419/extract-nfsrootfs-ftsfeezm,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 20:12:52.400746 - bootm 0x01080000 0x08000000 0x01070000
335 20:12:52.401263 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 20:12:52.402782 start: 2.3 connect-device (timeout 00:05:00) [common]
338 20:12:52.403217 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 20:12:52.418596 Setting prompt string to ['lava-test: # ']
340 20:12:52.420205 end: 2.3 connect-device (duration 00:00:00) [common]
341 20:12:52.420878 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 20:12:52.421808 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 20:12:52.422463 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 20:12:52.423698 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 20:12:52.461195 >> OK - accepted request
346 20:12:52.462989 Returned 0 in 0 seconds
347 20:12:52.564061 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 20:12:52.565152 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 20:12:52.565501 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 20:12:52.565811 Setting prompt string to ['Hit any key to stop autoboot']
352 20:12:52.566076 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 20:12:52.567041 Trying 192.168.56.21...
354 20:12:52.567340 Connected to conserv1.
355 20:12:52.567571 Escape character is '^]'.
356 20:12:52.567801
357 20:12:52.568056 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 20:12:52.568299
359 20:13:03.771540 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 20:13:03.772274 bl2_stage_init 0x01
361 20:13:03.772741 bl2_stage_init 0x81
362 20:13:03.777291 hw id: 0x0000 - pwm id 0x01
363 20:13:03.777849 bl2_stage_init 0xc1
364 20:13:03.778273 bl2_stage_init 0x02
365 20:13:03.778686
366 20:13:03.782740 L0:00000000
367 20:13:03.783233 L1:20000703
368 20:13:03.783646 L2:00008067
369 20:13:03.784091 L3:14000000
370 20:13:03.785422 B2:00402000
371 20:13:03.785881 B1:e0f83180
372 20:13:03.786278
373 20:13:03.786675 TE: 58124
374 20:13:03.787066
375 20:13:03.796423 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 20:13:03.796947
377 20:13:03.797350 Board ID = 1
378 20:13:03.797740 Set A53 clk to 24M
379 20:13:03.798129 Set A73 clk to 24M
380 20:13:03.802029 Set clk81 to 24M
381 20:13:03.802502 A53 clk: 1200 MHz
382 20:13:03.802893 A73 clk: 1200 MHz
383 20:13:03.807868 CLK81: 166.6M
384 20:13:03.808374 smccc: 00012a92
385 20:13:03.813441 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 20:13:03.813925 board id: 1
387 20:13:03.818900 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 20:13:03.832560 fw parse done
389 20:13:03.838465 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 20:13:03.881145 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 20:13:03.892028 PIEI prepare done
392 20:13:03.892640 fastboot data load
393 20:13:03.893124 fastboot data verify
394 20:13:03.897837 verify result: 266
395 20:13:03.903342 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 20:13:03.903972 LPDDR4 probe
397 20:13:03.904528 ddr clk to 1584MHz
398 20:13:03.911364 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 20:13:03.948633
400 20:13:03.949041 dmc_version 0001
401 20:13:03.954759 Check phy result
402 20:13:03.961144 INFO : End of CA training
403 20:13:03.961468 INFO : End of initialization
404 20:13:03.966579 INFO : Training has run successfully!
405 20:13:03.966896 Check phy result
406 20:13:03.972219 INFO : End of initialization
407 20:13:03.972528 INFO : End of read enable training
408 20:13:03.977763 INFO : End of fine write leveling
409 20:13:03.983426 INFO : End of Write leveling coarse delay
410 20:13:03.983786 INFO : Training has run successfully!
411 20:13:03.984085 Check phy result
412 20:13:03.988974 INFO : End of initialization
413 20:13:03.989470 INFO : End of read dq deskew training
414 20:13:03.994524 INFO : End of MPR read delay center optimization
415 20:13:04.000619 INFO : End of write delay center optimization
416 20:13:04.005736 INFO : End of read delay center optimization
417 20:13:04.006215 INFO : End of max read latency training
418 20:13:04.011386 INFO : Training has run successfully!
419 20:13:04.011888 1D training succeed
420 20:13:04.020554 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 20:13:04.068245 Check phy result
422 20:13:04.068840 INFO : End of initialization
423 20:13:04.089902 INFO : End of 2D read delay Voltage center optimization
424 20:13:04.110212 INFO : End of 2D read delay Voltage center optimization
425 20:13:04.162228 INFO : End of 2D write delay Voltage center optimization
426 20:13:04.211560 INFO : End of 2D write delay Voltage center optimization
427 20:13:04.217232 INFO : Training has run successfully!
428 20:13:04.217739
429 20:13:04.218186 channel==0
430 20:13:04.222691 RxClkDly_Margin_A0==88 ps 9
431 20:13:04.223176 TxDqDly_Margin_A0==98 ps 10
432 20:13:04.228263 RxClkDly_Margin_A1==88 ps 9
433 20:13:04.228739 TxDqDly_Margin_A1==98 ps 10
434 20:13:04.229179 TrainedVREFDQ_A0==74
435 20:13:04.233958 TrainedVREFDQ_A1==74
436 20:13:04.234443 VrefDac_Margin_A0==25
437 20:13:04.234883 DeviceVref_Margin_A0==40
438 20:13:04.239477 VrefDac_Margin_A1==25
439 20:13:04.239950 DeviceVref_Margin_A1==40
440 20:13:04.240422
441 20:13:04.240857
442 20:13:04.245222 channel==1
443 20:13:04.245694 RxClkDly_Margin_A0==98 ps 10
444 20:13:04.246131 TxDqDly_Margin_A0==98 ps 10
445 20:13:04.250662 RxClkDly_Margin_A1==98 ps 10
446 20:13:04.251145 TxDqDly_Margin_A1==88 ps 9
447 20:13:04.256303 TrainedVREFDQ_A0==77
448 20:13:04.256780 TrainedVREFDQ_A1==77
449 20:13:04.257216 VrefDac_Margin_A0==22
450 20:13:04.261948 DeviceVref_Margin_A0==37
451 20:13:04.262440 VrefDac_Margin_A1==22
452 20:13:04.267475 DeviceVref_Margin_A1==37
453 20:13:04.267945
454 20:13:04.268421 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 20:13:04.273194
456 20:13:04.301207 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 20:13:04.301819 2D training succeed
458 20:13:04.306713 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 20:13:04.312549 auto size-- 65535DDR cs0 size: 2048MB
460 20:13:04.313158 DDR cs1 size: 2048MB
461 20:13:04.318213 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 20:13:04.318822 cs0 DataBus test pass
463 20:13:04.323670 cs1 DataBus test pass
464 20:13:04.324304 cs0 AddrBus test pass
465 20:13:04.324756 cs1 AddrBus test pass
466 20:13:04.325176
467 20:13:04.329405 100bdlr_step_size ps== 420
468 20:13:04.330023 result report
469 20:13:04.334842 boot times 0Enable ddr reg access
470 20:13:04.340340 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 20:13:04.353718 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 20:13:04.926762 0.0;M3 CHK:0;cm4_sp_mode 0
473 20:13:04.927430 MVN_1=0x00000000
474 20:13:04.932209 MVN_2=0x00000000
475 20:13:04.937965 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 20:13:04.938536 OPS=0x10
477 20:13:04.938972 ring efuse init
478 20:13:04.939387 chipver efuse init
479 20:13:04.943542 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 20:13:04.948986 [0.018961 Inits done]
481 20:13:04.949356 secure task start!
482 20:13:04.949613 high task start!
483 20:13:04.954331 low task start!
484 20:13:04.955123 run into bl31
485 20:13:04.960360 NOTICE: BL31: v1.3(release):4fc40b1
486 20:13:04.968195 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 20:13:04.968767 NOTICE: BL31: G12A normal boot!
488 20:13:04.993594 NOTICE: BL31: BL33 decompress pass
489 20:13:04.999282 ERROR: Error initializing runtime service opteed_fast
490 20:13:06.232135
491 20:13:06.232816
492 20:13:06.240388 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 20:13:06.240904
494 20:13:06.241371 Model: Libre Computer AML-A311D-CC Alta
495 20:13:06.448821 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 20:13:06.472239 DRAM: 2 GiB (effective 3.8 GiB)
497 20:13:06.615259 Core: 408 devices, 31 uclasses, devicetree: separate
498 20:13:06.621003 WDT: Not starting watchdog@f0d0
499 20:13:06.653267 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 20:13:06.665728 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 20:13:06.670687 ** Bad device specification mmc 0 **
502 20:13:06.681049 Card did not respond to voltage select! : -110
503 20:13:06.688702 ** Bad device specification mmc 0 **
504 20:13:06.689001 Couldn't find partition mmc 0
505 20:13:06.697032 Card did not respond to voltage select! : -110
506 20:13:06.702572 ** Bad device specification mmc 0 **
507 20:13:06.702848 Couldn't find partition mmc 0
508 20:13:06.707620 Error: could not access storage.
509 20:13:07.971667 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
510 20:13:07.972330 bl2_stage_init 0x81
511 20:13:07.977171 hw id: 0x0000 - pwm id 0x01
512 20:13:07.977634 bl2_stage_init 0xc1
513 20:13:07.978200 bl2_stage_init 0x02
514 20:13:07.978977
515 20:13:07.982722 L0:00000000
516 20:13:07.983106 L1:20000703
517 20:13:07.983451 L2:00008067
518 20:13:07.983767 L3:14000000
519 20:13:07.984160 B2:00402000
520 20:13:07.988303 B1:e0f83180
521 20:13:07.988615
522 20:13:07.988864 TE: 58150
523 20:13:07.989098
524 20:13:07.993948 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 20:13:07.994344
526 20:13:07.994669 Board ID = 1
527 20:13:07.999525 Set A53 clk to 24M
528 20:13:07.999915 Set A73 clk to 24M
529 20:13:08.000443 Set clk81 to 24M
530 20:13:08.005207 A53 clk: 1200 MHz
531 20:13:08.006109 A73 clk: 1200 MHz
532 20:13:08.006963 CLK81: 166.6M
533 20:13:08.007795 smccc: 00012aac
534 20:13:08.010837 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 20:13:08.016408 board id: 1
536 20:13:08.022189 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 20:13:08.032894 fw parse done
538 20:13:08.038792 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 20:13:08.081391 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 20:13:08.092281 PIEI prepare done
541 20:13:08.092593 fastboot data load
542 20:13:08.092837 fastboot data verify
543 20:13:08.097833 verify result: 266
544 20:13:08.103462 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 20:13:08.103744 LPDDR4 probe
546 20:13:08.103976 ddr clk to 1584MHz
547 20:13:08.111517 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 20:13:08.148851
549 20:13:08.149215 dmc_version 0001
550 20:13:08.155382 Check phy result
551 20:13:08.161260 INFO : End of CA training
552 20:13:08.161550 INFO : End of initialization
553 20:13:08.166861 INFO : Training has run successfully!
554 20:13:08.167142 Check phy result
555 20:13:08.172506 INFO : End of initialization
556 20:13:08.172796 INFO : End of read enable training
557 20:13:08.175757 INFO : End of fine write leveling
558 20:13:08.181372 INFO : End of Write leveling coarse delay
559 20:13:08.186975 INFO : Training has run successfully!
560 20:13:08.187267 Check phy result
561 20:13:08.187493 INFO : End of initialization
562 20:13:08.192753 INFO : End of read dq deskew training
563 20:13:08.198201 INFO : End of MPR read delay center optimization
564 20:13:08.198492 INFO : End of write delay center optimization
565 20:13:08.203790 INFO : End of read delay center optimization
566 20:13:08.209385 INFO : End of max read latency training
567 20:13:08.209678 INFO : Training has run successfully!
568 20:13:08.214982 1D training succeed
569 20:13:08.220878 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 20:13:08.268443 Check phy result
571 20:13:08.268784 INFO : End of initialization
572 20:13:08.290140 INFO : End of 2D read delay Voltage center optimization
573 20:13:08.310387 INFO : End of 2D read delay Voltage center optimization
574 20:13:08.362413 INFO : End of 2D write delay Voltage center optimization
575 20:13:08.411866 INFO : End of 2D write delay Voltage center optimization
576 20:13:08.417261 INFO : Training has run successfully!
577 20:13:08.417794
578 20:13:08.418205 channel==0
579 20:13:08.422913 RxClkDly_Margin_A0==88 ps 9
580 20:13:08.423446 TxDqDly_Margin_A0==98 ps 10
581 20:13:08.428497 RxClkDly_Margin_A1==88 ps 9
582 20:13:08.428855 TxDqDly_Margin_A1==98 ps 10
583 20:13:08.429148 TrainedVREFDQ_A0==74
584 20:13:08.434093 TrainedVREFDQ_A1==74
585 20:13:08.434427 VrefDac_Margin_A0==25
586 20:13:08.434714 DeviceVref_Margin_A0==40
587 20:13:08.439732 VrefDac_Margin_A1==25
588 20:13:08.440079 DeviceVref_Margin_A1==40
589 20:13:08.440369
590 20:13:08.440652
591 20:13:08.445333 channel==1
592 20:13:08.445810 RxClkDly_Margin_A0==98 ps 10
593 20:13:08.446212 TxDqDly_Margin_A0==98 ps 10
594 20:13:08.450847 RxClkDly_Margin_A1==98 ps 10
595 20:13:08.451318 TxDqDly_Margin_A1==88 ps 9
596 20:13:08.456536 TrainedVREFDQ_A0==77
597 20:13:08.457005 TrainedVREFDQ_A1==77
598 20:13:08.457445 VrefDac_Margin_A0==22
599 20:13:08.462111 DeviceVref_Margin_A0==37
600 20:13:08.462585 VrefDac_Margin_A1==22
601 20:13:08.467746 DeviceVref_Margin_A1==37
602 20:13:08.468229
603 20:13:08.468624 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 20:13:08.473255
605 20:13:08.501331 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
606 20:13:08.501736 2D training succeed
607 20:13:08.506871 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 20:13:08.512474 auto size-- 65535DDR cs0 size: 2048MB
609 20:13:08.512828 DDR cs1 size: 2048MB
610 20:13:08.518124 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 20:13:08.518454 cs0 DataBus test pass
612 20:13:08.523823 cs1 DataBus test pass
613 20:13:08.524210 cs0 AddrBus test pass
614 20:13:08.524444 cs1 AddrBus test pass
615 20:13:08.524658
616 20:13:08.529376 100bdlr_step_size ps== 420
617 20:13:08.529723 result report
618 20:13:08.534972 boot times 0Enable ddr reg access
619 20:13:08.540485 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 20:13:08.553906 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 20:13:09.127931 0.0;M3 CHK:0;cm4_sp_mode 0
622 20:13:09.128675 MVN_1=0x00000000
623 20:13:09.133333 MVN_2=0x00000000
624 20:13:09.139078 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 20:13:09.139688 OPS=0x10
626 20:13:09.140231 ring efuse init
627 20:13:09.140729 chipver efuse init
628 20:13:09.144582 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 20:13:09.150178 [0.018961 Inits done]
630 20:13:09.150687 secure task start!
631 20:13:09.151125 high task start!
632 20:13:09.154701 low task start!
633 20:13:09.155215 run into bl31
634 20:13:09.161449 NOTICE: BL31: v1.3(release):4fc40b1
635 20:13:09.169271 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 20:13:09.169759 NOTICE: BL31: G12A normal boot!
637 20:13:09.194518 NOTICE: BL31: BL33 decompress pass
638 20:13:09.200195 ERROR: Error initializing runtime service opteed_fast
639 20:13:10.433391
640 20:13:10.434081
641 20:13:10.441573 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 20:13:10.442108
643 20:13:10.442580 Model: Libre Computer AML-A311D-CC Alta
644 20:13:10.650020 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 20:13:10.673339 DRAM: 2 GiB (effective 3.8 GiB)
646 20:13:10.816394 Core: 408 devices, 31 uclasses, devicetree: separate
647 20:13:10.822333 WDT: Not starting watchdog@f0d0
648 20:13:10.854617 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 20:13:10.866908 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 20:13:10.871974 ** Bad device specification mmc 0 **
651 20:13:10.882421 Card did not respond to voltage select! : -110
652 20:13:10.889861 ** Bad device specification mmc 0 **
653 20:13:10.890363 Couldn't find partition mmc 0
654 20:13:10.898340 Card did not respond to voltage select! : -110
655 20:13:10.903715 ** Bad device specification mmc 0 **
656 20:13:10.904272 Couldn't find partition mmc 0
657 20:13:10.908770 Error: could not access storage.
658 20:13:11.251609 Net: eth0: ethernet@ff3f0000
659 20:13:11.252359 starting USB...
660 20:13:11.503247 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 20:13:11.503900 Starting the controller
662 20:13:11.510101 USB XHCI 1.10
663 20:13:13.221931 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
664 20:13:13.222605 bl2_stage_init 0x01
665 20:13:13.223074 bl2_stage_init 0x81
666 20:13:13.227503 hw id: 0x0000 - pwm id 0x01
667 20:13:13.228053 bl2_stage_init 0xc1
668 20:13:13.228519 bl2_stage_init 0x02
669 20:13:13.228967
670 20:13:13.233063 L0:00000000
671 20:13:13.233540 L1:20000703
672 20:13:13.233986 L2:00008067
673 20:13:13.234430 L3:14000000
674 20:13:13.238769 B2:00402000
675 20:13:13.239247 B1:e0f83180
676 20:13:13.239698
677 20:13:13.240182 TE: 58167
678 20:13:13.240634
679 20:13:13.246914 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 20:13:13.247401
681 20:13:13.247851 Board ID = 1
682 20:13:13.249294 Set A53 clk to 24M
683 20:13:13.249769 Set A73 clk to 24M
684 20:13:13.250214 Set clk81 to 24M
685 20:13:13.255012 A53 clk: 1200 MHz
686 20:13:13.255492 A73 clk: 1200 MHz
687 20:13:13.255941 CLK81: 166.6M
688 20:13:13.256425 smccc: 00012abe
689 20:13:13.266205 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 20:13:13.266696 board id: 1
691 20:13:13.272499 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 20:13:13.283121 fw parse done
693 20:13:13.289089 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 20:13:13.331575 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 20:13:13.342447 PIEI prepare done
696 20:13:13.342931 fastboot data load
697 20:13:13.343381 fastboot data verify
698 20:13:13.348085 verify result: 266
699 20:13:13.353625 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 20:13:13.354105 LPDDR4 probe
701 20:13:13.354553 ddr clk to 1584MHz
702 20:13:13.361613 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 20:13:13.398955
704 20:13:13.399501 dmc_version 0001
705 20:13:13.405592 Check phy result
706 20:13:13.411444 INFO : End of CA training
707 20:13:13.411932 INFO : End of initialization
708 20:13:13.417087 INFO : Training has run successfully!
709 20:13:13.417586 Check phy result
710 20:13:13.422709 INFO : End of initialization
711 20:13:13.423196 INFO : End of read enable training
712 20:13:13.425980 INFO : End of fine write leveling
713 20:13:13.431518 INFO : End of Write leveling coarse delay
714 20:13:13.437078 INFO : Training has run successfully!
715 20:13:13.437557 Check phy result
716 20:13:13.438003 INFO : End of initialization
717 20:13:13.442681 INFO : End of read dq deskew training
718 20:13:13.448456 INFO : End of MPR read delay center optimization
719 20:13:13.448989 INFO : End of write delay center optimization
720 20:13:13.453873 INFO : End of read delay center optimization
721 20:13:13.459553 INFO : End of max read latency training
722 20:13:13.460103 INFO : Training has run successfully!
723 20:13:13.465164 1D training succeed
724 20:13:13.471037 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 20:13:13.518705 Check phy result
726 20:13:13.519221 INFO : End of initialization
727 20:13:13.541170 INFO : End of 2D read delay Voltage center optimization
728 20:13:13.561253 INFO : End of 2D read delay Voltage center optimization
729 20:13:13.613156 INFO : End of 2D write delay Voltage center optimization
730 20:13:13.662404 INFO : End of 2D write delay Voltage center optimization
731 20:13:13.667916 INFO : Training has run successfully!
732 20:13:13.668440
733 20:13:13.668898 channel==0
734 20:13:13.673524 RxClkDly_Margin_A0==88 ps 9
735 20:13:13.674003 TxDqDly_Margin_A0==98 ps 10
736 20:13:13.679122 RxClkDly_Margin_A1==88 ps 9
737 20:13:13.679597 TxDqDly_Margin_A1==98 ps 10
738 20:13:13.680082 TrainedVREFDQ_A0==74
739 20:13:13.684693 TrainedVREFDQ_A1==74
740 20:13:13.685168 VrefDac_Margin_A0==24
741 20:13:13.685613 DeviceVref_Margin_A0==40
742 20:13:13.690434 VrefDac_Margin_A1==25
743 20:13:13.690902 DeviceVref_Margin_A1==40
744 20:13:13.691341
745 20:13:13.691784
746 20:13:13.695881 channel==1
747 20:13:13.696401 RxClkDly_Margin_A0==88 ps 9
748 20:13:13.696850 TxDqDly_Margin_A0==98 ps 10
749 20:13:13.701460 RxClkDly_Margin_A1==98 ps 10
750 20:13:13.701940 TxDqDly_Margin_A1==88 ps 9
751 20:13:13.707095 TrainedVREFDQ_A0==77
752 20:13:13.707572 TrainedVREFDQ_A1==77
753 20:13:13.708053 VrefDac_Margin_A0==22
754 20:13:13.712645 DeviceVref_Margin_A0==37
755 20:13:13.713114 VrefDac_Margin_A1==22
756 20:13:13.718452 DeviceVref_Margin_A1==37
757 20:13:13.718949
758 20:13:13.719402 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 20:13:13.719848
760 20:13:13.751876 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
761 20:13:13.752436 2D training succeed
762 20:13:13.757518 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 20:13:13.763079 auto size-- 65535DDR cs0 size: 2048MB
764 20:13:13.763552 DDR cs1 size: 2048MB
765 20:13:13.768719 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 20:13:13.769200 cs0 DataBus test pass
767 20:13:13.774288 cs1 DataBus test pass
768 20:13:13.774756 cs0 AddrBus test pass
769 20:13:13.775197 cs1 AddrBus test pass
770 20:13:13.775629
771 20:13:13.779870 100bdlr_step_size ps== 420
772 20:13:13.780441 result report
773 20:13:13.785512 boot times 0Enable ddr reg access
774 20:13:13.790833 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 20:13:13.804301 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 20:13:14.376528 0.0;M3 CHK:0;cm4_sp_mode 0
777 20:13:14.377190 MVN_1=0x00000000
778 20:13:14.381907 MVN_2=0x00000000
779 20:13:14.387792 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 20:13:14.388392 OPS=0x10
781 20:13:14.388832 ring efuse init
782 20:13:14.389263 chipver efuse init
783 20:13:14.393248 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 20:13:14.398794 [0.018961 Inits done]
785 20:13:14.399260 secure task start!
786 20:13:14.399690 high task start!
787 20:13:14.403428 low task start!
788 20:13:14.403893 run into bl31
789 20:13:14.410112 NOTICE: BL31: v1.3(release):4fc40b1
790 20:13:14.417929 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 20:13:14.418417 NOTICE: BL31: G12A normal boot!
792 20:13:14.443376 NOTICE: BL31: BL33 decompress pass
793 20:13:14.448974 ERROR: Error initializing runtime service opteed_fast
794 20:13:15.682020
795 20:13:15.682680
796 20:13:15.690207 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 20:13:15.690689
798 20:13:15.691125 Model: Libre Computer AML-A311D-CC Alta
799 20:13:15.898728 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 20:13:15.922047 DRAM: 2 GiB (effective 3.8 GiB)
801 20:13:16.065098 Core: 408 devices, 31 uclasses, devicetree: separate
802 20:13:16.070871 WDT: Not starting watchdog@f0d0
803 20:13:16.103165 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 20:13:16.115615 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 20:13:16.120655 ** Bad device specification mmc 0 **
806 20:13:16.130937 Card did not respond to voltage select! : -110
807 20:13:16.138651 ** Bad device specification mmc 0 **
808 20:13:16.139126 Couldn't find partition mmc 0
809 20:13:16.146919 Card did not respond to voltage select! : -110
810 20:13:16.152449 ** Bad device specification mmc 0 **
811 20:13:16.152921 Couldn't find partition mmc 0
812 20:13:16.157507 Error: could not access storage.
813 20:13:16.500086 Net: eth0: ethernet@ff3f0000
814 20:13:16.500710 starting USB...
815 20:13:16.751833 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 20:13:16.752449 Starting the controller
817 20:13:16.758749 USB XHCI 1.10
818 20:13:18.922042 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 20:13:18.922666 bl2_stage_init 0x01
820 20:13:18.923130 bl2_stage_init 0x81
821 20:13:18.928023 hw id: 0x0000 - pwm id 0x01
822 20:13:18.928512 bl2_stage_init 0xc1
823 20:13:18.928965 bl2_stage_init 0x02
824 20:13:18.929413
825 20:13:18.933125 L0:00000000
826 20:13:18.933607 L1:20000703
827 20:13:18.934053 L2:00008067
828 20:13:18.934489 L3:14000000
829 20:13:18.936162 B2:00402000
830 20:13:18.936633 B1:e0f83180
831 20:13:18.937078
832 20:13:18.937515 TE: 58150
833 20:13:18.937952
834 20:13:18.947370 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 20:13:18.947858
836 20:13:18.948351 Board ID = 1
837 20:13:18.948793 Set A53 clk to 24M
838 20:13:18.949232 Set A73 clk to 24M
839 20:13:18.952923 Set clk81 to 24M
840 20:13:18.953396 A53 clk: 1200 MHz
841 20:13:18.953844 A73 clk: 1200 MHz
842 20:13:18.956549 CLK81: 166.6M
843 20:13:18.957028 smccc: 00012aac
844 20:13:18.961987 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 20:13:18.967667 board id: 1
846 20:13:18.972609 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 20:13:18.983104 fw parse done
848 20:13:18.989072 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 20:13:19.031725 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 20:13:19.042562 PIEI prepare done
851 20:13:19.043036 fastboot data load
852 20:13:19.043493 fastboot data verify
853 20:13:19.048208 verify result: 266
854 20:13:19.053695 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 20:13:19.054172 LPDDR4 probe
856 20:13:19.054618 ddr clk to 1584MHz
857 20:13:19.061743 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 20:13:19.099058
859 20:13:19.099576 dmc_version 0001
860 20:13:19.105629 Check phy result
861 20:13:19.111598 INFO : End of CA training
862 20:13:19.112098 INFO : End of initialization
863 20:13:19.117252 INFO : Training has run successfully!
864 20:13:19.117726 Check phy result
865 20:13:19.122777 INFO : End of initialization
866 20:13:19.123248 INFO : End of read enable training
867 20:13:19.126033 INFO : End of fine write leveling
868 20:13:19.131585 INFO : End of Write leveling coarse delay
869 20:13:19.137279 INFO : Training has run successfully!
870 20:13:19.137751 Check phy result
871 20:13:19.138200 INFO : End of initialization
872 20:13:19.142843 INFO : End of read dq deskew training
873 20:13:19.148415 INFO : End of MPR read delay center optimization
874 20:13:19.148886 INFO : End of write delay center optimization
875 20:13:19.153988 INFO : End of read delay center optimization
876 20:13:19.159636 INFO : End of max read latency training
877 20:13:19.160142 INFO : Training has run successfully!
878 20:13:19.165294 1D training succeed
879 20:13:19.171162 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 20:13:19.218722 Check phy result
881 20:13:19.219208 INFO : End of initialization
882 20:13:19.240336 INFO : End of 2D read delay Voltage center optimization
883 20:13:19.260415 INFO : End of 2D read delay Voltage center optimization
884 20:13:19.312498 INFO : End of 2D write delay Voltage center optimization
885 20:13:19.361726 INFO : End of 2D write delay Voltage center optimization
886 20:13:19.367276 INFO : Training has run successfully!
887 20:13:19.367746
888 20:13:19.368254 channel==0
889 20:13:19.372715 RxClkDly_Margin_A0==88 ps 9
890 20:13:19.373206 TxDqDly_Margin_A0==98 ps 10
891 20:13:19.376092 RxClkDly_Margin_A1==88 ps 9
892 20:13:19.376565 TxDqDly_Margin_A1==98 ps 10
893 20:13:19.381692 TrainedVREFDQ_A0==74
894 20:13:19.382012 TrainedVREFDQ_A1==75
895 20:13:19.382245 VrefDac_Margin_A0==25
896 20:13:19.387363 DeviceVref_Margin_A0==40
897 20:13:19.387665 VrefDac_Margin_A1==25
898 20:13:19.392952 DeviceVref_Margin_A1==39
899 20:13:19.393246
900 20:13:19.393462
901 20:13:19.393670 channel==1
902 20:13:19.393871 RxClkDly_Margin_A0==98 ps 10
903 20:13:19.398582 TxDqDly_Margin_A0==98 ps 10
904 20:13:19.398877 RxClkDly_Margin_A1==98 ps 10
905 20:13:19.404144 TxDqDly_Margin_A1==88 ps 9
906 20:13:19.404449 TrainedVREFDQ_A0==77
907 20:13:19.404671 TrainedVREFDQ_A1==77
908 20:13:19.409678 VrefDac_Margin_A0==22
909 20:13:19.409983 DeviceVref_Margin_A0==37
910 20:13:19.415334 VrefDac_Margin_A1==24
911 20:13:19.415672 DeviceVref_Margin_A1==37
912 20:13:19.415896
913 20:13:19.420898 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 20:13:19.421232
915 20:13:19.448861 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
916 20:13:19.454440 2D training succeed
917 20:13:19.460089 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 20:13:19.460410 auto size-- 65535DDR cs0 size: 2048MB
919 20:13:19.465677 DDR cs1 size: 2048MB
920 20:13:19.465992 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 20:13:19.471309 cs0 DataBus test pass
922 20:13:19.471619 cs1 DataBus test pass
923 20:13:19.471830 cs0 AddrBus test pass
924 20:13:19.476869 cs1 AddrBus test pass
925 20:13:19.477211
926 20:13:19.477426 100bdlr_step_size ps== 420
927 20:13:19.477634 result report
928 20:13:19.482478 boot times 0Enable ddr reg access
929 20:13:19.490232 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 20:13:19.503669 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 20:13:20.075783 0.0;M3 CHK:0;cm4_sp_mode 0
932 20:13:20.076245 MVN_1=0x00000000
933 20:13:20.081261 MVN_2=0x00000000
934 20:13:20.087058 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 20:13:20.087478 OPS=0x10
936 20:13:20.087844 ring efuse init
937 20:13:20.088132 chipver efuse init
938 20:13:20.095245 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 20:13:20.095580 [0.018961 Inits done]
940 20:13:20.102848 secure task start!
941 20:13:20.103160 high task start!
942 20:13:20.103369 low task start!
943 20:13:20.103582 run into bl31
944 20:13:20.109828 NOTICE: BL31: v1.3(release):4fc40b1
945 20:13:20.117387 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 20:13:20.117708 NOTICE: BL31: G12A normal boot!
947 20:13:20.143062 NOTICE: BL31: BL33 decompress pass
948 20:13:20.148792 ERROR: Error initializing runtime service opteed_fast
949 20:13:21.381980
950 20:13:21.382411
951 20:13:21.390247 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 20:13:21.390683
953 20:13:21.391016 Model: Libre Computer AML-A311D-CC Alta
954 20:13:21.598649 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 20:13:21.622084 DRAM: 2 GiB (effective 3.8 GiB)
956 20:13:21.764885 Core: 408 devices, 31 uclasses, devicetree: separate
957 20:13:21.770835 WDT: Not starting watchdog@f0d0
958 20:13:21.803121 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 20:13:21.815471 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 20:13:21.820487 ** Bad device specification mmc 0 **
961 20:13:21.830835 Card did not respond to voltage select! : -110
962 20:13:21.838564 ** Bad device specification mmc 0 **
963 20:13:21.838855 Couldn't find partition mmc 0
964 20:13:21.846787 Card did not respond to voltage select! : -110
965 20:13:21.852439 ** Bad device specification mmc 0 **
966 20:13:21.852736 Couldn't find partition mmc 0
967 20:13:21.857474 Error: could not access storage.
968 20:13:22.199957 Net: eth0: ethernet@ff3f0000
969 20:13:22.200406 starting USB...
970 20:13:22.451692 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 20:13:22.452320 Starting the controller
972 20:13:22.458741 USB XHCI 1.10
973 20:13:24.321846 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
974 20:13:24.322268 bl2_stage_init 0x01
975 20:13:24.322484 bl2_stage_init 0x81
976 20:13:24.327395 hw id: 0x0000 - pwm id 0x01
977 20:13:24.327684 bl2_stage_init 0xc1
978 20:13:24.327895 bl2_stage_init 0x02
979 20:13:24.328168
980 20:13:24.333071 L0:00000000
981 20:13:24.333449 L1:20000703
982 20:13:24.333765 L2:00008067
983 20:13:24.334078 L3:14000000
984 20:13:24.338644 B2:00402000
985 20:13:24.338917 B1:e0f83180
986 20:13:24.339126
987 20:13:24.339331 TE: 58159
988 20:13:24.339533
989 20:13:24.344257 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 20:13:24.344632
991 20:13:24.344949 Board ID = 1
992 20:13:24.349790 Set A53 clk to 24M
993 20:13:24.350164 Set A73 clk to 24M
994 20:13:24.350484 Set clk81 to 24M
995 20:13:24.355482 A53 clk: 1200 MHz
996 20:13:24.355859 A73 clk: 1200 MHz
997 20:13:24.356208 CLK81: 166.6M
998 20:13:24.356514 smccc: 00012ab5
999 20:13:24.361112 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 20:13:24.366597 board id: 1
1001 20:13:24.372496 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 20:13:24.383198 fw parse done
1003 20:13:24.389200 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 20:13:24.431718 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 20:13:24.442568 PIEI prepare done
1006 20:13:24.443066 fastboot data load
1007 20:13:24.443480 fastboot data verify
1008 20:13:24.448286 verify result: 266
1009 20:13:24.453735 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 20:13:24.454236 LPDDR4 probe
1011 20:13:24.454652 ddr clk to 1584MHz
1012 20:13:24.461709 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 20:13:24.499221
1014 20:13:24.499779 dmc_version 0001
1015 20:13:24.505644 Check phy result
1016 20:13:24.511722 INFO : End of CA training
1017 20:13:24.512316 INFO : End of initialization
1018 20:13:24.517189 INFO : Training has run successfully!
1019 20:13:24.517708 Check phy result
1020 20:13:24.522859 INFO : End of initialization
1021 20:13:24.523503 INFO : End of read enable training
1022 20:13:24.526051 INFO : End of fine write leveling
1023 20:13:24.531654 INFO : End of Write leveling coarse delay
1024 20:13:24.537197 INFO : Training has run successfully!
1025 20:13:24.537860 Check phy result
1026 20:13:24.538406 INFO : End of initialization
1027 20:13:24.542762 INFO : End of read dq deskew training
1028 20:13:24.548455 INFO : End of MPR read delay center optimization
1029 20:13:24.549121 INFO : End of write delay center optimization
1030 20:13:24.553977 INFO : End of read delay center optimization
1031 20:13:24.559631 INFO : End of max read latency training
1032 20:13:24.560251 INFO : Training has run successfully!
1033 20:13:24.565233 1D training succeed
1034 20:13:24.571104 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 20:13:24.618877 Check phy result
1036 20:13:24.619533 INFO : End of initialization
1037 20:13:24.641206 INFO : End of 2D read delay Voltage center optimization
1038 20:13:24.661307 INFO : End of 2D read delay Voltage center optimization
1039 20:13:24.713195 INFO : End of 2D write delay Voltage center optimization
1040 20:13:24.762562 INFO : End of 2D write delay Voltage center optimization
1041 20:13:24.768181 INFO : Training has run successfully!
1042 20:13:24.768742
1043 20:13:24.769245 channel==0
1044 20:13:24.773744 RxClkDly_Margin_A0==88 ps 9
1045 20:13:24.774507 TxDqDly_Margin_A0==98 ps 10
1046 20:13:24.779342 RxClkDly_Margin_A1==88 ps 9
1047 20:13:24.779878 TxDqDly_Margin_A1==98 ps 10
1048 20:13:24.780437 TrainedVREFDQ_A0==74
1049 20:13:24.784918 TrainedVREFDQ_A1==74
1050 20:13:24.785682 VrefDac_Margin_A0==24
1051 20:13:24.786457 DeviceVref_Margin_A0==40
1052 20:13:24.790402 VrefDac_Margin_A1==24
1053 20:13:24.790944 DeviceVref_Margin_A1==40
1054 20:13:24.791439
1055 20:13:24.791917
1056 20:13:24.796137 channel==1
1057 20:13:24.796482 RxClkDly_Margin_A0==88 ps 9
1058 20:13:24.796714 TxDqDly_Margin_A0==88 ps 9
1059 20:13:24.801672 RxClkDly_Margin_A1==98 ps 10
1060 20:13:24.801992 TxDqDly_Margin_A1==88 ps 9
1061 20:13:24.807296 TrainedVREFDQ_A0==77
1062 20:13:24.807616 TrainedVREFDQ_A1==77
1063 20:13:24.807842 VrefDac_Margin_A0==22
1064 20:13:24.812868 DeviceVref_Margin_A0==37
1065 20:13:24.813184 VrefDac_Margin_A1==22
1066 20:13:24.818469 DeviceVref_Margin_A1==37
1067 20:13:24.818792
1068 20:13:24.819019 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 20:13:24.819233
1070 20:13:24.852128 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1071 20:13:24.852672 2D training succeed
1072 20:13:24.857611 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 20:13:24.863283 auto size-- 65535DDR cs0 size: 2048MB
1074 20:13:24.863760 DDR cs1 size: 2048MB
1075 20:13:24.868863 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 20:13:24.869332 cs0 DataBus test pass
1077 20:13:24.874474 cs1 DataBus test pass
1078 20:13:24.874945 cs0 AddrBus test pass
1079 20:13:24.875337 cs1 AddrBus test pass
1080 20:13:24.875725
1081 20:13:24.880139 100bdlr_step_size ps== 420
1082 20:13:24.880615 result report
1083 20:13:24.885693 boot times 0Enable ddr reg access
1084 20:13:24.890924 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 20:13:24.904293 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 20:13:25.476288 0.0;M3 CHK:0;cm4_sp_mode 0
1087 20:13:25.476707 MVN_1=0x00000000
1088 20:13:25.481856 MVN_2=0x00000000
1089 20:13:25.487513 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 20:13:25.487816 OPS=0x10
1091 20:13:25.488092 ring efuse init
1092 20:13:25.488327 chipver efuse init
1093 20:13:25.495723 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 20:13:25.496068 [0.018961 Inits done]
1095 20:13:25.503324 secure task start!
1096 20:13:25.503656 high task start!
1097 20:13:25.503880 low task start!
1098 20:13:25.504127 run into bl31
1099 20:13:25.510087 NOTICE: BL31: v1.3(release):4fc40b1
1100 20:13:25.517758 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 20:13:25.518100 NOTICE: BL31: G12A normal boot!
1102 20:13:25.543182 NOTICE: BL31: BL33 decompress pass
1103 20:13:25.548908 ERROR: Error initializing runtime service opteed_fast
1104 20:13:26.781655
1105 20:13:26.782078
1106 20:13:26.790023 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 20:13:26.790329
1108 20:13:26.790552 Model: Libre Computer AML-A311D-CC Alta
1109 20:13:26.998453 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 20:13:27.023230 DRAM: 2 GiB (effective 3.8 GiB)
1111 20:13:27.164950 Core: 408 devices, 31 uclasses, devicetree: separate
1112 20:13:27.170683 WDT: Not starting watchdog@f0d0
1113 20:13:27.203009 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 20:13:27.215473 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 20:13:27.220361 ** Bad device specification mmc 0 **
1116 20:13:27.230705 Card did not respond to voltage select! : -110
1117 20:13:27.238444 ** Bad device specification mmc 0 **
1118 20:13:27.239018 Couldn't find partition mmc 0
1119 20:13:27.246722 Card did not respond to voltage select! : -110
1120 20:13:27.252313 ** Bad device specification mmc 0 **
1121 20:13:27.252876 Couldn't find partition mmc 0
1122 20:13:27.257344 Error: could not access storage.
1123 20:13:27.599847 Net: eth0: ethernet@ff3f0000
1124 20:13:27.600584 starting USB...
1125 20:13:27.851651 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 20:13:27.852332 Starting the controller
1127 20:13:27.858529 USB XHCI 1.10
1128 20:13:29.412955 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 20:13:29.421136 scanning usb for storage devices... 0 Storage Device(s) found
1131 20:13:29.473135 Hit any key to stop autoboot: 1
1132 20:13:29.474074 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1133 20:13:29.474705 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1134 20:13:29.475231 Setting prompt string to ['=>']
1135 20:13:29.475752 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1136 20:13:29.488992 0
1137 20:13:29.489998 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 20:13:29.490551 Sending with 10 millisecond of delay
1140 20:13:30.626569 => setenv autoload no
1141 20:13:30.637478 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1142 20:13:30.642979 setenv autoload no
1143 20:13:30.643803 Sending with 10 millisecond of delay
1145 20:13:32.441651 => setenv initrd_high 0xffffffff
1146 20:13:32.452508 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1147 20:13:32.453403 setenv initrd_high 0xffffffff
1148 20:13:32.454163 Sending with 10 millisecond of delay
1150 20:13:34.070632 => setenv fdt_high 0xffffffff
1151 20:13:34.081479 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1152 20:13:34.082352 setenv fdt_high 0xffffffff
1153 20:13:34.083112 Sending with 10 millisecond of delay
1155 20:13:34.375071 => dhcp
1156 20:13:34.385963 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1157 20:13:34.386927 dhcp
1158 20:13:34.387413 Speed: 1000, full duplex
1159 20:13:34.387874 BOOTP broadcast 1
1160 20:13:34.394235 DHCP client bound to address 192.168.6.27 (8 ms)
1161 20:13:34.394981 Sending with 10 millisecond of delay
1163 20:13:36.071858 => setenv serverip 192.168.6.2
1164 20:13:36.083096 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1165 20:13:36.084328 setenv serverip 192.168.6.2
1166 20:13:36.085202 Sending with 10 millisecond of delay
1168 20:13:39.811380 => tftpboot 0x01080000 954419/tftp-deploy-ri2_i088/kernel/uImage
1169 20:13:39.822423 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1170 20:13:39.823528 tftpboot 0x01080000 954419/tftp-deploy-ri2_i088/kernel/uImage
1171 20:13:39.824173 Speed: 1000, full duplex
1172 20:13:39.824746 Using ethernet@ff3f0000 device
1173 20:13:39.825436 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1174 20:13:39.830939 Filename '954419/tftp-deploy-ri2_i088/kernel/uImage'.
1175 20:13:39.834562 Load address: 0x1080000
1176 20:13:42.810911 Loading: *################################################## 43.6 MiB
1177 20:13:42.811543 14.6 MiB/s
1178 20:13:42.811975 done
1179 20:13:42.815398 Bytes transferred = 45713984 (2b98a40 hex)
1180 20:13:42.816183 Sending with 10 millisecond of delay
1182 20:13:47.502626 => tftpboot 0x08000000 954419/tftp-deploy-ri2_i088/ramdisk/ramdisk.cpio.gz.uboot
1183 20:13:47.513440 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1184 20:13:47.514294 tftpboot 0x08000000 954419/tftp-deploy-ri2_i088/ramdisk/ramdisk.cpio.gz.uboot
1185 20:13:47.514742 Speed: 1000, full duplex
1186 20:13:47.515163 Using ethernet@ff3f0000 device
1187 20:13:47.516417 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1188 20:13:47.528244 Filename '954419/tftp-deploy-ri2_i088/ramdisk/ramdisk.cpio.gz.uboot'.
1189 20:13:47.528766 Load address: 0x8000000
1190 20:13:54.097826 Loading: *###################T ############################# UDP wrong checksum 000000ff 00009842
1191 20:13:54.131756 ## 22.3 MiB
1192 20:13:54.132315 3.4 MiB/s
1193 20:13:54.132746 done
1194 20:13:54.135339 Bytes transferred = 23433620 (1659194 hex)
1195 20:13:54.136141 Sending with 10 millisecond of delay
1197 20:13:59.303926 => tftpboot 0x01070000 954419/tftp-deploy-ri2_i088/dtb/meson-g12b-a311d-libretech-cc.dtb
1198 20:13:59.314730 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:53)
1199 20:13:59.315546 tftpboot 0x01070000 954419/tftp-deploy-ri2_i088/dtb/meson-g12b-a311d-libretech-cc.dtb
1200 20:13:59.316024 Speed: 1000, full duplex
1201 20:13:59.316447 Using ethernet@ff3f0000 device
1202 20:13:59.319953 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1203 20:13:59.327336 Filename '954419/tftp-deploy-ri2_i088/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1204 20:13:59.338673 Load address: 0x1070000
1205 20:13:59.350117 Loading: *################################################## 53.4 KiB
1206 20:13:59.350584 3.1 MiB/s
1207 20:13:59.351002 done
1208 20:13:59.354539 Bytes transferred = 54703 (d5af hex)
1209 20:13:59.355275 Sending with 10 millisecond of delay
1211 20:14:12.650836 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/954419/extract-nfsrootfs-ftsfeezm,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1212 20:14:12.661652 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:40)
1213 20:14:12.662523 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/954419/extract-nfsrootfs-ftsfeezm,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1214 20:14:12.663224 Sending with 10 millisecond of delay
1216 20:14:15.001912 => bootm 0x01080000 0x08000000 0x01070000
1217 20:14:15.012694 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1218 20:14:15.013303 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:37)
1219 20:14:15.014351 bootm 0x01080000 0x08000000 0x01070000
1220 20:14:15.014816 ## Booting kernel from Legacy Image at 01080000 ...
1221 20:14:15.025469 Image Name:
1222 20:14:15.026018 Image Type: AArch64 Linux Kernel Image (uncompressed)
1223 20:14:15.027084 Data Size: 45713920 Bytes = 43.6 MiB
1224 20:14:15.027757 Load Address: 01080000
1225 20:14:15.028268 Entry Point: 01080000
1226 20:14:15.223850 Verifying Checksum ... OK
1227 20:14:15.224459 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1228 20:14:15.229283 Image Name:
1229 20:14:15.234791 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1230 20:14:15.235242 Data Size: 23433556 Bytes = 22.3 MiB
1231 20:14:15.237275 Load Address: 00000000
1232 20:14:15.244358 Entry Point: 00000000
1233 20:14:15.342840 Verifying Checksum ... OK
1234 20:14:15.343326 ## Flattened Device Tree blob at 01070000
1235 20:14:15.348030 Booting using the fdt blob at 0x1070000
1236 20:14:15.348491 Working FDT set to 1070000
1237 20:14:15.353230 Loading Kernel Image
1238 20:14:15.503670 Loading Ramdisk to 7e9a6000, end 7ffff154 ... OK
1239 20:14:15.512088 Loading Device Tree to 000000007e995000, end 000000007e9a55ae ... OK
1240 20:14:15.512645 Working FDT set to 7e995000
1241 20:14:15.512910
1242 20:14:15.513530 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1243 20:14:15.513899 start: 2.4.4 auto-login-action (timeout 00:03:37) [common]
1244 20:14:15.514185 Setting prompt string to ['Linux version [0-9]']
1245 20:14:15.514438 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1246 20:14:15.514693 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1247 20:14:15.515538 Starting kernel ...
1248 20:14:15.515849
1249 20:14:15.552293 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1250 20:14:15.553116 start: 2.4.4.1 login-action (timeout 00:03:37) [common]
1251 20:14:15.553451 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1252 20:14:15.553712 Setting prompt string to []
1253 20:14:15.553976 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1254 20:14:15.554228 Using line separator: #'\n'#
1255 20:14:15.554445 No login prompt set.
1256 20:14:15.554698 Parsing kernel messages
1257 20:14:15.554916 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1258 20:14:15.555354 [login-action] Waiting for messages, (timeout 00:03:37)
1259 20:14:15.555612 Waiting using forced prompt support (timeout 00:01:48)
1260 20:14:15.568845 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j366965-arm64-gcc-12-defconfig-9tvfv) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Nov 7 16:41:56 UTC 2024
1261 20:14:15.574361 [ 0.000000] KASLR disabled due to lack of seed
1262 20:14:15.579843 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1263 20:14:15.585346 [ 0.000000] efi: UEFI not found.
1264 20:14:15.590796 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1265 20:14:15.596270 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1266 20:14:15.607259 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1267 20:14:15.618303 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1268 20:14:15.623946 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1269 20:14:15.635017 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1270 20:14:15.646048 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1271 20:14:15.651625 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1272 20:14:15.657131 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1273 20:14:15.662647 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1274 20:14:15.663111 [ 0.000000] Zone ranges:
1275 20:14:15.668178 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1276 20:14:15.673671 [ 0.000000] DMA32 empty
1277 20:14:15.674151 [ 0.000000] Normal empty
1278 20:14:15.679226 [ 0.000000] Movable zone start for each node
1279 20:14:15.684677 [ 0.000000] Early memory node ranges
1280 20:14:15.690217 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1281 20:14:15.695725 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1282 20:14:15.701253 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1283 20:14:15.706832 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1284 20:14:15.734097 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1285 20:14:15.739652 [ 0.000000] psci: probing for conduit method from DT.
1286 20:14:15.740154 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1287 20:14:15.745192 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1288 20:14:15.750711 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1289 20:14:15.756240 [ 0.000000] psci: SMC Calling Convention v1.1
1290 20:14:15.761731 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1291 20:14:15.767267 [ 0.000000] Detected VIPT I-cache on CPU0
1292 20:14:15.772841 [ 0.000000] CPU features: detected: ARM erratum 845719
1293 20:14:15.778293 [ 0.000000] alternatives: applying boot alternatives
1294 20:14:15.794777 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/954419/extract-nfsrootfs-ftsfeezm,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1295 20:14:15.805847 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1296 20:14:15.811416 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1297 20:14:15.816975 <6>[ 0.000000] Fallback order for Node 0: 0
1298 20:14:15.822482 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1299 20:14:15.828002 <6>[ 0.000000] Policy zone: DMA
1300 20:14:15.833491 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1301 20:14:15.839018 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1302 20:14:15.844536 <6>[ 0.000000] software IO TLB: area num 8.
1303 20:14:15.853521 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1304 20:14:15.900047 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1305 20:14:15.905590 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1306 20:14:15.911136 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1307 20:14:15.916629 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1308 20:14:15.922131 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1309 20:14:15.927665 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1310 20:14:15.933177 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1311 20:14:15.938700 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1312 20:14:15.949706 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1313 20:14:15.960735 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1314 20:14:15.966306 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1315 20:14:15.971879 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1316 20:14:15.972376 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1317 20:14:15.981651 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1318 20:14:15.994308 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1319 20:14:16.005347 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1320 20:14:16.010913 <6>[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1321 20:14:16.016433 <6>[ 0.008793] Console: colour dummy device 80x25
1322 20:14:16.027504 <6>[ 0.012935] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1323 20:14:16.033006 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1324 20:14:16.038434 <6>[ 0.028188] LSM: initializing lsm=capability
1325 20:14:16.043955 <6>[ 0.032726] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1326 20:14:16.049452 <6>[ 0.040210] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1327 20:14:16.054984 <6>[ 0.052298] rcu: Hierarchical SRCU implementation.
1328 20:14:16.060495 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1329 20:14:16.071561 <6>[ 0.058886] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1330 20:14:16.080002 <6>[ 0.071568] EFI services will not be available.
1331 20:14:16.080528 <6>[ 0.075225] smp: Bringing up secondary CPUs ...
1332 20:14:16.096259 <6>[ 0.077135] Detected VIPT I-cache on CPU1
1333 20:14:16.101806 <6>[ 0.077255] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1334 20:14:16.107269 <6>[ 0.078583] CPU features: detected: Spectre-v2
1335 20:14:16.116256 <6>[ 0.078598] CPU features: detected: Spectre-v4
1336 20:14:16.116767 <6>[ 0.078603] CPU features: detected: Spectre-BHB
1337 20:14:16.121822 <6>[ 0.078609] CPU features: detected: ARM erratum 858921
1338 20:14:16.127312 <6>[ 0.078617] Detected VIPT I-cache on CPU2
1339 20:14:16.136444 <6>[ 0.078689] arch_timer: Enabling local workaround for ARM erratum 858921
1340 20:14:16.141955 <6>[ 0.078706] arch_timer: CPU2: Trapping CNTVCT access
1341 20:14:16.147466 <6>[ 0.078716] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1342 20:14:16.153000 <6>[ 0.083575] Detected VIPT I-cache on CPU3
1343 20:14:16.158555 <6>[ 0.083621] arch_timer: Enabling local workaround for ARM erratum 858921
1344 20:14:16.164078 <6>[ 0.083630] arch_timer: CPU3: Trapping CNTVCT access
1345 20:14:16.169631 <6>[ 0.083638] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1346 20:14:16.175068 <6>[ 0.087609] Detected VIPT I-cache on CPU4
1347 20:14:16.180620 <6>[ 0.087656] arch_timer: Enabling local workaround for ARM erratum 858921
1348 20:14:16.186140 <6>[ 0.087666] arch_timer: CPU4: Trapping CNTVCT access
1349 20:14:16.191647 <6>[ 0.087673] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1350 20:14:16.197167 <6>[ 0.095639] Detected VIPT I-cache on CPU5
1351 20:14:16.202691 <6>[ 0.095686] arch_timer: Enabling local workaround for ARM erratum 858921
1352 20:14:16.208226 <6>[ 0.095696] arch_timer: CPU5: Trapping CNTVCT access
1353 20:14:16.213762 <6>[ 0.095703] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1354 20:14:16.219240 <6>[ 0.095823] smp: Brought up 1 node, 6 CPUs
1355 20:14:16.224840 <6>[ 0.217052] SMP: Total of 6 processors activated.
1356 20:14:16.230312 <6>[ 0.221955] CPU: All CPU(s) started at EL2
1357 20:14:16.235817 <6>[ 0.226297] CPU features: detected: 32-bit EL0 Support
1358 20:14:16.241327 <6>[ 0.231613] CPU features: detected: 32-bit EL1 Support
1359 20:14:16.246861 <6>[ 0.236962] CPU features: detected: CRC32 instructions
1360 20:14:16.252385 <6>[ 0.242363] alternatives: applying system-wide alternatives
1361 20:14:16.263407 <6>[ 0.249545] Memory: 3557432K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187800K reserved, 262144K cma-reserved)
1362 20:14:16.270335 <6>[ 0.263894] devtmpfs: initialized
1363 20:14:16.281364 <6>[ 0.273083] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1364 20:14:16.286892 <6>[ 0.277440] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1365 20:14:16.292415 <6>[ 0.288236] 21392 pages in range for non-PLT usage
1366 20:14:16.297927 <6>[ 0.288246] 512912 pages in range for PLT usage
1367 20:14:16.303465 <6>[ 0.289791] pinctrl core: initialized pinctrl subsystem
1368 20:14:16.308994 <6>[ 0.301881] DMI not present or invalid.
1369 20:14:16.314498 <6>[ 0.306157] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1370 20:14:16.320760 <6>[ 0.310902] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1371 20:14:16.331080 <6>[ 0.317674] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1372 20:14:16.336566 <6>[ 0.325778] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1373 20:14:16.342107 <6>[ 0.333271] audit: initializing netlink subsys (disabled)
1374 20:14:16.347677 <5>[ 0.338997] audit: type=2000 audit(0.260:1): state=initialized audit_enabled=0 res=1
1375 20:14:16.358608 <6>[ 0.340411] thermal_sys: Registered thermal governor 'step_wise'
1376 20:14:16.364212 <6>[ 0.346776] thermal_sys: Registered thermal governor 'power_allocator'
1377 20:14:16.369689 <6>[ 0.353037] cpuidle: using governor menu
1378 20:14:16.375206 <6>[ 0.364076] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1379 20:14:16.380737 <6>[ 0.370952] ASID allocator initialised with 65536 entries
1380 20:14:16.383395 <6>[ 0.378427] Serial: AMBA PL011 UART driver
1381 20:14:16.394281 <6>[ 0.389033] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1382 20:14:16.410538 <6>[ 0.404524] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1383 20:14:16.419501 <6>[ 0.407181] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1384 20:14:16.424970 <6>[ 0.420347] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1385 20:14:16.436011 <6>[ 0.423567] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1386 20:14:16.441520 <6>[ 0.431993] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1387 20:14:16.452568 <6>[ 0.439611] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1388 20:14:16.458095 <6>[ 0.453205] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1389 20:14:16.463627 <6>[ 0.455431] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1390 20:14:16.474645 <6>[ 0.461912] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1391 20:14:16.480191 <6>[ 0.468891] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1392 20:14:16.485665 <6>[ 0.475359] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1393 20:14:16.491181 <6>[ 0.482343] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1394 20:14:16.496698 <6>[ 0.488813] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1395 20:14:16.507773 <6>[ 0.495798] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1396 20:14:16.508329 <6>[ 0.503822] ACPI: Interpreter disabled.
1397 20:14:16.513274 <6>[ 0.509297] iommu: Default domain type: Translated
1398 20:14:16.518865 <6>[ 0.511332] iommu: DMA domain TLB invalidation policy: strict mode
1399 20:14:16.524302 <5>[ 0.518079] SCSI subsystem initialized
1400 20:14:16.529856 <6>[ 0.521951] usbcore: registered new interface driver usbfs
1401 20:14:16.535377 <6>[ 0.527393] usbcore: registered new interface driver hub
1402 20:14:16.540892 <6>[ 0.532906] usbcore: registered new device driver usb
1403 20:14:16.546413 <6>[ 0.539171] pps_core: LinuxPPS API ver. 1 registered
1404 20:14:16.557435 <6>[ 0.543326] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1405 20:14:16.557954 <6>[ 0.552645] PTP clock support registered
1406 20:14:16.562937 <6>[ 0.556884] EDAC MC: Ver: 3.0.0
1407 20:14:16.568509 <6>[ 0.560542] scmi_core: SCMI protocol bus registered
1408 20:14:16.574080 <6>[ 0.566141] FPGA manager framework
1409 20:14:16.579424 <6>[ 0.568908] Advanced Linux Sound Architecture Driver Initialized.
1410 20:14:16.579913 <6>[ 0.575867] vgaarb: loaded
1411 20:14:16.584947 <6>[ 0.578398] clocksource: Switched to clocksource arch_sys_counter
1412 20:14:16.590499 <5>[ 0.584553] VFS: Disk quotas dquot_6.6.0
1413 20:14:16.596015 <6>[ 0.588540] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1414 20:14:16.601566 <6>[ 0.595750] pnp: PnP ACPI: disabled
1415 20:14:16.607185 <6>[ 0.604305] NET: Registered PF_INET protocol family
1416 20:14:16.612653 <6>[ 0.604568] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1417 20:14:16.623697 <6>[ 0.614733] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1418 20:14:16.629201 <6>[ 0.620742] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1419 20:14:16.640258 <6>[ 0.628638] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1420 20:14:16.645755 <6>[ 0.636876] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1421 20:14:16.656839 <6>[ 0.644674] TCP: Hash tables configured (established 32768 bind 32768)
1422 20:14:16.662360 <6>[ 0.651150] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1423 20:14:16.667899 <6>[ 0.657995] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1424 20:14:16.673367 <6>[ 0.665418] NET: Registered PF_UNIX/PF_LOCAL protocol family
1425 20:14:16.678925 <6>[ 0.671502] RPC: Registered named UNIX socket transport module.
1426 20:14:16.684400 <6>[ 0.677283] RPC: Registered udp transport module.
1427 20:14:16.689924 <6>[ 0.682188] RPC: Registered tcp transport module.
1428 20:14:16.695440 <6>[ 0.687103] RPC: Registered tcp-with-tls transport module.
1429 20:14:16.700970 <6>[ 0.692796] RPC: Registered tcp NFSv4.1 backchannel transport module.
1430 20:14:16.706477 <6>[ 0.699444] PCI: CLS 0 bytes, default 64
1431 20:14:16.712044 <6>[ 0.703764] Unpacking initramfs...
1432 20:14:16.717527 <6>[ 0.709967] kvm [1]: nv: 554 coarse grained trap handlers
1433 20:14:16.723097 <6>[ 0.713130] kvm [1]: IPA Size Limit: 40 bits
1434 20:14:16.723582 <6>[ 0.718733] kvm [1]: vgic interrupt IRQ9
1435 20:14:16.728547 <6>[ 0.721455] kvm [1]: Hyp nVHE mode initialized successfully
1436 20:14:16.734081 <5>[ 0.728678] Initialise system trusted keyrings
1437 20:14:16.739599 <6>[ 0.732104] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1438 20:14:16.745141 <6>[ 0.738753] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1439 20:14:16.750652 <5>[ 0.744840] NFS: Registering the id_resolver key type
1440 20:14:16.756219 <5>[ 0.749831] Key type id_resolver registered
1441 20:14:16.761682 <5>[ 0.754208] Key type id_legacy registered
1442 20:14:16.767218 <6>[ 0.758445] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1443 20:14:16.778206 <6>[ 0.765335] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1444 20:14:16.782161 <6>[ 0.773140] 9p: Installing v9fs 9p2000 file system support
1445 20:14:16.820227 <5>[ 0.819791] Key type asymmetric registered
1446 20:14:16.825744 <5>[ 0.819837] Asymmetric key parser 'x509' registered
1447 20:14:16.836834 <6>[ 0.823709] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1448 20:14:16.837337 <6>[ 0.831226] io scheduler mq-deadline registered
1449 20:14:16.842308 <6>[ 0.835969] io scheduler kyber registered
1450 20:14:16.847802 <6>[ 0.840226] io scheduler bfq registered
1451 20:14:16.854116 <6>[ 0.848157] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1452 20:14:16.870173 <6>[ 0.866434] ledtrig-cpu: registered to indicate activity on CPUs
1453 20:14:16.902252 <6>[ 0.897790] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1454 20:14:16.922642 <6>[ 0.911009] Serial: 8250/16550 driver, 4 ports,<6>[ 0.915688] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1455 20:14:16.928213 <6>[ 0.925318] printk: legacy console [ttyAML0] enabled
1456 20:14:16.933735 <6>[ 0.925318] printk: legacy console [ttyAML0] enabled
1457 20:14:16.939291 <6>[ 0.930111] printk: legacy bootconsole [meson0] disabled
1458 20:14:16.944844 <6>[ 0.930111] printk: legacy bootconsole [meson0] disabled
1459 20:14:16.950386 <6>[ 0.943233] msm_serial: driver initialized
1460 20:14:16.955934 <6>[ 0.946070] SuperH (H)SCI(F) driver initialized
1461 20:14:16.956456 <6>[ 0.950609] STM32 USART driver initialized
1462 20:14:16.963476 <5>[ 0.956765] random: crng init done
1463 20:14:16.970522 <6>[ 0.965892] loop: module loaded
1464 20:14:16.971013 <6>[ 0.967187] megasas: 07.727.03.00-rc1
1465 20:14:16.976087 <6>[ 0.974658] tun: Universal TUN/TAP device driver, 1.6
1466 20:14:16.981624 <6>[ 0.975882] thunder_xcv, ver 1.0
1467 20:14:16.987231 <6>[ 0.977819] thunder_bgx, ver 1.0
1468 20:14:16.987722 <6>[ 0.981305] nicpf, ver 1.0
1469 20:14:16.992688 <6>[ 0.985865] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1470 20:14:16.998245 <6>[ 0.991676] hns3: Copyright (c) 2017 Huawei Corporation.
1471 20:14:17.003814 <6>[ 0.997260] hclge is initializing
1472 20:14:17.009318 <6>[ 1.000801] e1000: Intel(R) PRO/1000 Network Driver
1473 20:14:17.015003 <6>[ 1.005883] e1000: Copyright (c) 1999-2006 Intel Corporation.
1474 20:14:17.020539 <6>[ 1.011904] e1000e: Intel(R) PRO/1000 Network Driver
1475 20:14:17.026072 <6>[ 1.017066] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1476 20:14:17.031623 <6>[ 1.023244] igb: Intel(R) Gigabit Ethernet Network Driver
1477 20:14:17.037061 <6>[ 1.028849] igb: Copyright (c) 2007-2014 Intel Corporation.
1478 20:14:17.042580 <6>[ 1.034687] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1479 20:14:17.048190 <6>[ 1.041158] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1480 20:14:17.053666 <6>[ 1.047909] sky2: driver version 1.30
1481 20:14:17.059197 <6>[ 1.052987] VFIO - User Level meta-driver version: 0.3
1482 20:14:17.064792 <6>[ 1.060533] usbcore: registered new interface driver usb-storage
1483 20:14:17.069906 <6>[ 1.066752] i2c_dev: i2c /dev entries driver
1484 20:14:17.083742 <6>[ 1.077777] sdhci: Secure Digital Host Controller Interface driver
1485 20:14:17.084322 <6>[ 1.078610] sdhci: Copyright(c) Pierre Ossman
1486 20:14:17.092815 <6>[ 1.084312] Synopsys Designware Multimedia Card Interface Driver
1487 20:14:17.098301 <6>[ 1.090846] sdhci-pltfm: SDHCI platform and OF driver helper
1488 20:14:17.103832 <6>[ 1.098483] meson-sm: secure-monitor enabled
1489 20:14:17.109323 <6>[ 1.101102] usbcore: registered new interface driver usbhid
1490 20:14:17.113251 <6>[ 1.105639] usbhid: USB HID core driver
1491 20:14:17.120950 <6>[ 1.120428] NET: Registered PF_PACKET protocol family
1492 20:14:17.126422 <6>[ 1.120516] 9pnet: Installing 9P2000 support
1493 20:14:17.133727 <5>[ 1.124676] Key type dns_resolver registered
1494 20:14:17.139236 <6>[ 1.136441] registered taskstats version 1
1495 20:14:17.144823 <5>[ 1.136589] Loading compiled-in X.509 certificates
1496 20:14:17.147357 <6>[ 1.145240] Demotion targets for Node 0: null
1497 20:14:17.189309 <6>[ 1.188777] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1498 20:14:17.194795 <6>[ 1.188822] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1499 20:14:17.205858 <4>[ 1.199046] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1500 20:14:17.211410 <4>[ 1.201558] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1501 20:14:17.217012 <6>[ 1.209161] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1502 20:14:17.222628 <6>[ 1.218373] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1503 20:14:17.233663 <6>[ 1.221885] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1504 20:14:17.244755 <6>[ 1.229859] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1505 20:14:17.250391 <6>[ 1.239383] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1506 20:14:17.255880 <6>[ 1.245592] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1507 20:14:17.261448 <6>[ 1.251231] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1508 20:14:17.266963 <6>[ 1.259115] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1509 20:14:17.272513 <6>[ 1.266357] hub 1-0:1.0: USB hub found
1510 20:14:17.278070 <6>[ 1.269880] hub 1-0:1.0: 2 ports detected
1511 20:14:17.283633 <6>[ 1.275955] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1512 20:14:17.289148 <6>[ 1.282830] hub 2-0:1.0: USB hub found
1513 20:14:17.293253 <6>[ 1.286424] hub 2-0:1.0: 1 port detected
1514 20:14:17.313276 <6>[ 1.311000] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1515 20:14:17.329979 <6>[ 1.326147] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1516 20:14:17.366383 <6>[ 1.362186] Trying to probe devices needed for running init ...
1517 20:14:17.523291 <6>[ 1.518440] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1518 20:14:17.667746 <6>[ 1.661705] mmc0: new ultra high speed SDR104 SDXC card at address e624
1519 20:14:17.673901 <6>[ 1.663639] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1520 20:14:17.674382 <6>[ 1.669336] mmcblk0: p1
1521 20:14:17.682199 <6>[ 1.679934] Freeing initrd memory: 22884K
1522 20:14:17.714726 <6>[ 1.714197] hub 1-1:1.0: USB hub found
1523 20:14:17.720517 <6>[ 1.714517] hub 1-1:1.0: 4 ports detected
1524 20:14:17.779316 <6>[ 1.774541] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1525 20:14:17.827428 <6>[ 1.826857] hub 2-1:1.0: USB hub found
1526 20:14:17.833241 <6>[ 1.827685] hub 2-1:1.0: 4 ports detected
1527 20:14:29.647165 <6>[ 13.646462] clk: Disabling unused clocks
1528 20:14:29.652632 <6>[ 13.646630] PM: genpd: Disabling unused power domains
1529 20:14:29.661231 <6>[ 13.650322] ALSA device list:
1530 20:14:29.661708 <6>[ 13.653532] No soundcards found.
1531 20:14:29.667337 <6>[ 13.665845] Freeing unused kernel memory: 10432K
1532 20:14:29.672796 <6>[ 13.665948] Run /init as init process
1533 20:14:29.678996 Loading, please wait...
1534 20:14:29.716277 Starting systemd-udevd version 252.22-1~deb12u1
1535 20:14:30.188406 <6>[ 14.185454] mc: Linux media interface: v0.10
1536 20:14:30.202753 <6>[ 14.198667] videodev: Linux video capture interface: v2.00
1537 20:14:30.216637 <6>[ 14.210509] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1538 20:14:30.222214 <6>[ 14.213283] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1539 20:14:30.227735 <6>[ 14.218229] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1540 20:14:30.233359 <6>[ 14.224551] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1541 20:14:30.244399 <4>[ 14.235303] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1542 20:14:30.249961 <6>[ 14.236043] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1543 20:14:30.255502 <6>[ 14.239454] meson-vrtc ff8000a8.rtc: registered as rtc0
1544 20:14:30.261087 <6>[ 14.246455] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1545 20:14:30.266723 <6>[ 14.246468] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1546 20:14:30.277705 <6>[ 14.253002] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1547 20:14:30.283224 <6>[ 14.257358] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1548 20:14:30.288689 <6>[ 14.257366] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1549 20:14:30.299794 <6>[ 14.257372] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1550 20:14:30.305337 <6>[ 14.257378] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1551 20:14:30.310892 <6>[ 14.301677] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1552 20:14:30.316424 <6>[ 14.306792] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1553 20:14:30.321977 <3>[ 14.310520] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1554 20:14:30.333020 <6>[ 14.312841] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1555 20:14:30.338597 <6>[ 14.314410] panfrost ffe40000.gpu: clock rate = 24000000
1556 20:14:30.344173 <3>[ 14.314468] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1557 20:14:30.355201 <6>[ 14.315871] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1558 20:14:30.360860 <6>[ 14.315883] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1559 20:14:30.377393 <6>[ 14.315891] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1560 20:14:30.382995 <6>[ 14.315899] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1561 20:14:30.394024 <4>[ 14.341744] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1562 20:14:30.399630 <6>[ 14.353708] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1563 20:14:30.405193 <6>[ 14.373450] Registered IR keymap rc-empty
1564 20:14:30.410747 <6>[ 14.381326] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1565 20:14:30.416284 <6>[ 14.390613] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1566 20:14:30.421875 <6>[ 14.397495] usbcore: registered new device driver onboard-usb-dev
1567 20:14:30.432853 <6>[ 14.399991] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1568 20:14:30.443948 <6>[ 14.418506] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1569 20:14:30.444458 <6>[ 14.420808] rc rc0: sw decoder init
1570 20:14:30.449564 <6>[ 14.430796] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1571 20:14:30.460590 <6>[ 14.431837] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1572 20:14:30.471690 <6>[ 14.433736] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1573 20:14:30.477250 <3>[ 14.433871] meson-drm ff900000.vpu: DSI transceiver device is disabled
1574 20:14:30.482831 <6>[ 14.434780] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1575 20:14:30.488457 <6>[ 14.438599] meson-ir ff808000.ir: receiver initialized
1576 20:14:30.668231 <6>[ 14.643211] Console: switching to colour frame buffer device 128x48
1577 20:14:30.675352 <6>[ 14.663100] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1578 20:14:30.686506 <6>[ 14.677604] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1579 20:14:30.930737 <6>[ 14.930135] hub 1-1:1.0: USB hub found
1580 20:14:30.936213 <6>[ 14.930459] hub 1-1:1.0: 4 ports detected
1581 20:14:30.942651 <6>[ 14.935986] onboard-usb-dev 1-1: USB disconnect, device number 2
1582 20:14:31.070072 Begin: Loading essential drivers ... done.
1583 20:14:31.075552 Begin: Running /scripts/init-premount ... done.
1584 20:14:31.081068 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1585 20:14:31.094748 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1586 20:14:31.095230 Device /sys/class/net/end0 found
1587 20:14:31.095649 done.
1588 20:14:31.108159 Begin: Waiting up to 180 secs for any network device to become available ... done.
1589 20:14:31.149049 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1590 20:14:31.154675 <6>[ 15.146706] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1591 20:14:31.227261 <6>[ 15.218575] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=30)
1592 20:14:31.240722 <6>[ 15.234721] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1593 20:14:31.246321 <6>[ 15.236922] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1594 20:14:31.255583 <6>[ 15.244471] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1595 20:14:31.287101 <6>[ 15.282173] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1596 20:14:31.423189 <6>[ 15.418434] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1597 20:14:31.602971 <6>[ 15.602309] hub 1-1:1.0: USB hub found
1598 20:14:31.608628 <6>[ 15.602620] hub 1-1:1.0: 4 ports detected
1599 20:14:32.119138 <4>[ 16.118432] rc rc0: two consecutive events of type space
1600 20:14:32.754469 IP-Config: no response after 2 secs - giving up
1601 20:14:32.802715 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1602 20:14:34.333999 <6>[ 18.327292] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1603 20:14:34.912849 IP-Config: end0 guessed broadcast address 192.168.6.255
1604 20:14:34.918396 IP-Config: end0 complete (dhcp from 192.168.6.1):
1605 20:14:34.923830 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1606 20:14:34.934961 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1607 20:14:34.935457 rootserver: 192.168.6.1 rootpath:
1608 20:14:34.937446 filename :
1609 20:14:35.075695 done.
1610 20:14:35.086053 Begin: Running /scripts/nfs-bottom ... done.
1611 20:14:35.108794 Begin: Running /scripts/init-bottom ... done.
1612 20:14:35.448354 <30>[ 19.443389] systemd[1]: System time before build time, advancing clock.
1613 20:14:35.498854 <6>[ 19.498142] NET: Registered PF_INET6 protocol family
1614 20:14:35.504162 <6>[ 19.499947] Segment Routing with IPv6
1615 20:14:35.508851 <6>[ 19.501647] In-situ OAM (IOAM) with IPv6
1616 20:14:35.587466 <30>[ 19.555952] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1617 20:14:35.591036 <30>[ 19.583336] systemd[1]: Detected architecture arm64.
1618 20:14:35.591542
1619 20:14:35.596973 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1620 20:14:35.597473
1621 20:14:35.611428 <30>[ 19.608163] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1622 20:14:36.408766 <30>[ 20.403417] systemd[1]: Queued start job for default target graphical.target.
1623 20:14:36.438943 <30>[ 20.433023] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1624 20:14:36.447377 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1625 20:14:36.458454 <30>[ 20.451419] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1626 20:14:36.465703 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1627 20:14:36.477435 <30>[ 20.471512] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1628 20:14:36.486446 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1629 20:14:36.497560 <30>[ 20.491163] systemd[1]: Created slice user.slice - User and Session Slice.
1630 20:14:36.504006 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1631 20:14:36.517697 <30>[ 20.506689] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1632 20:14:36.523650 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1633 20:14:36.534688 <30>[ 20.526627] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1634 20:14:36.546800 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1635 20:14:36.563403 <30>[ 20.546588] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1636 20:14:36.569018 <30>[ 20.560650] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1637 20:14:36.582080 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1638 20:14:36.587625 <30>[ 20.582494] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1639 20:14:36.596607 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1640 20:14:36.612510 <30>[ 20.606522] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1641 20:14:36.620958 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1642 20:14:36.632522 <30>[ 20.626548] systemd[1]: Reached target paths.target - Path Units.
1643 20:14:36.640953 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1644 20:14:36.646616 <30>[ 20.642511] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1645 20:14:36.658259 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1646 20:14:36.663855 <30>[ 20.658495] systemd[1]: Reached target slices.target - Slice Units.
1647 20:14:36.672020 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1648 20:14:36.677503 <30>[ 20.674503] systemd[1]: Reached target swap.target - Swaps.
1649 20:14:36.684587 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1650 20:14:36.696556 <30>[ 20.690521] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1651 20:14:36.705430 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1652 20:14:36.720754 <30>[ 20.714705] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1653 20:14:36.729968 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1654 20:14:36.742208 <30>[ 20.736185] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1655 20:14:36.751013 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1656 20:14:36.762020 <30>[ 20.756002] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1657 20:14:36.775097 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1658 20:14:36.780661 <30>[ 20.775324] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1659 20:14:36.788749 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1660 20:14:36.806306 <30>[ 20.800231] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1661 20:14:36.815419 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1662 20:14:36.827522 <30>[ 20.821467] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1663 20:14:36.833098 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1664 20:14:36.845225 <30>[ 20.839174] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1665 20:14:36.853760 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1666 20:14:36.908790 <30>[ 20.902754] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1667 20:14:36.915451 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1668 20:14:36.929281 <30>[ 20.923250] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1669 20:14:36.936856 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1670 20:14:36.951040 <30>[ 20.944961] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1671 20:14:36.957490 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1672 20:14:36.978906 <30>[ 20.966739] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1673 20:14:37.016924 <30>[ 21.010797] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1674 20:14:37.025531 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1675 20:14:37.043418 <30>[ 21.037397] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1676 20:14:37.051366 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1677 20:14:37.067612 <30>[ 21.061619] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1678 20:14:37.075255 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1679 20:14:37.092604 <6>[ 21.086571] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1680 20:14:37.103736 <30>[ 21.088035] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1681 20:14:37.108633 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1682 20:14:37.125638 <30>[ 21.119560] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1683 20:14:37.133943 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1684 20:14:37.149575 <30>[ 21.143578] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1685 20:14:37.156835 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1686 20:14:37.171456 <30>[ 21.165419] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1687 20:14:37.180965 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel<6>[ 21.175064] fuse: init (API version 7.41)
1688 20:14:37.181494 Module loop...
1689 20:14:37.201169 <30>[ 21.195118] systemd[1]: Starting systemd-journald.service - Journal Service...
1690 20:14:37.207575 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1691 20:14:37.227118 <30>[ 21.221066] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1692 20:14:37.233738 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1693 20:14:37.253506 <30>[ 21.247472] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1694 20:14:37.262546 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1695 20:14:37.277247 <30>[ 21.271251] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1696 20:14:37.285094 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1697 20:14:37.301451 <30>[ 21.295354] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1698 20:14:37.309465 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1699 20:14:37.328778 <30>[ 21.322740] systemd[1]: Started systemd-journald.service - Journal Service.
1700 20:14:37.335671 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1701 20:14:37.347823 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1702 20:14:37.365422 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1703 20:14:37.381741 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1704 20:14:37.398374 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1705 20:14:37.409625 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1706 20:14:37.421707 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1707 20:14:37.436726 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1708 20:14:37.449753 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1709 20:14:37.464607 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1710 20:14:37.481583 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1711 20:14:37.497503 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1712 20:14:37.513451 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1713 20:14:37.528562 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1714 20:14:37.545883 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1715 20:14:37.591206 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1716 20:14:37.602376 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1717 20:14:37.616234 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1718 20:14:37.633393 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1719 20:14:37.649546 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1720 20:14:37.656930 <46>[ 21.649437] systemd-journald[229]: Received client request to flush runtime journal.
1721 20:14:37.680749 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1722 20:14:37.704919 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1723 20:14:37.711356 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1724 20:14:37.729077 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1725 20:14:37.745615 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1726 20:14:37.761720 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1727 20:14:37.888402 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1728 20:14:37.933816 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1729 20:14:37.953664 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1730 20:14:38.020801 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1731 20:14:38.029206 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1732 20:14:38.044284 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1733 20:14:38.080245 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1734 20:14:38.094660 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1735 20:14:38.315671 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1736 20:14:38.362879 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1737 20:14:38.370292 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1738 20:14:38.414236 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1739 20:14:38.464629 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1740 20:14:38.482233 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1741 20:14:38.541515 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1742 20:14:38.548705 <5>[ 22.543782] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1743 20:14:38.590219 <5>[ 22.584356] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1744 20:14:38.595870 <5>[ 22.585052] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1745 20:14:38.601530 <4>[ 22.594383] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1746 20:14:38.609598 <6>[ 22.600970] cfg80211: failed to load regulatory.db
1747 20:14:38.654604 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1748 20:14:38.665696 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1749 20:14:38.678249 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1750 20:14:38.684639 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1751 20:14:38.697134 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1752 20:14:38.723975 <46>[ 22.706845] systemd-journald[229]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1753 20:14:38.735101 <46>[ 22.719356] systemd-journald[229]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1754 20:14:38.745207 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1755 20:14:38.765287 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1756 20:14:38.861313 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1757 20:14:38.878194 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1758 20:14:38.892787 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1759 20:14:38.933475 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1760 20:14:38.944721 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1761 20:14:38.960583 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1762 20:14:38.967118 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1763 20:14:38.975658 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1764 20:14:39.039672 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1765 20:14:39.055346 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1766 20:14:39.077703 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1767 20:14:39.090562 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1768 20:14:39.137169 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1769 20:14:39.153797 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1770 20:14:39.168918 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1771 20:14:39.175422 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1772 20:14:39.220755 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1773 20:14:39.236977 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1774 20:14:39.256900 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1775 20:14:39.264495 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1776 20:14:39.273352 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1777 20:14:39.292730 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1778 20:14:39.299459 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1779 20:14:39.308836 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1780 20:14:39.329414 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1781 20:14:39.335923 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1782 20:14:39.389546 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1783 20:14:39.437073 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1784 20:14:39.500964
1785 20:14:39.501377 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1786 20:14:39.501617
1787 20:14:39.508225 debian-bookworm-arm64 login: root (automatic login)
1788 20:14:39.508580
1789 20:14:39.685591 Linux debian-bookworm-arm64 6.12.0-rc2 #1 SMP PREEMPT Thu Nov 7 16:41:56 UTC 2024 aarch64
1790 20:14:39.686235
1791 20:14:39.691120 The programs included with the Debian GNU/Linux system are free software;
1792 20:14:39.700161 the exact distribution terms for each program are described in the
1793 20:14:39.701084 individual files in /usr/share/doc/*/copyright.
1794 20:14:39.701836
1795 20:14:39.705703 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1796 20:14:39.710914 permitted by applicable law.
1797 20:14:40.376235 Matched prompt #10: / #
1799 20:14:40.377756 Setting prompt string to ['/ #']
1800 20:14:40.378307 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1802 20:14:40.379672 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1803 20:14:40.380250 start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
1804 20:14:40.380694 Setting prompt string to ['/ #']
1805 20:14:40.381104 Forcing a shell prompt, looking for ['/ #']
1807 20:14:40.432121 / #
1808 20:14:40.432883 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1809 20:14:40.433354 Waiting using forced prompt support (timeout 00:02:30)
1810 20:14:40.438988
1811 20:14:40.439878 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1812 20:14:40.440521 start: 2.4.6 export-device-env (timeout 00:03:12) [common]
1813 20:14:40.440998 Sending with 10 millisecond of delay
1815 20:14:45.428918 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/954419/extract-nfsrootfs-ftsfeezm'
1816 20:14:45.439906 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/954419/extract-nfsrootfs-ftsfeezm'
1817 20:14:45.440737 Sending with 10 millisecond of delay
1819 20:14:47.539695 / # export NFS_SERVER_IP='192.168.6.2'
1820 20:14:47.550724 export NFS_SERVER_IP='192.168.6.2'
1821 20:14:47.551633 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1822 20:14:47.552280 end: 2.4 uboot-commands (duration 00:01:55) [common]
1823 20:14:47.552895 end: 2 uboot-action (duration 00:01:55) [common]
1824 20:14:47.553496 start: 3 lava-test-retry (timeout 00:06:39) [common]
1825 20:14:47.554103 start: 3.1 lava-test-shell (timeout 00:06:39) [common]
1826 20:14:47.554781 Using namespace: common
1828 20:14:47.656106 / # #
1829 20:14:47.656876 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1830 20:14:47.662167 #
1831 20:14:47.662919 Using /lava-954419
1833 20:14:47.764101 / # export SHELL=/bin/bash
1834 20:14:47.770139 export SHELL=/bin/bash
1836 20:14:47.871672 / # . /lava-954419/environment
1837 20:14:47.880329 . /lava-954419/environment
1839 20:14:47.982926 / # /lava-954419/bin/lava-test-runner /lava-954419/0
1840 20:14:47.984340 Test shell timeout: 10s (minimum of the action and connection timeout)
1841 20:14:47.988593 /lava-954419/bin/lava-test-runner /lava-954419/0
1842 20:14:48.191343 + export TESTRUN_ID=0_timesync-off
1843 20:14:48.199510 + TESTRUN_ID=0_timesync-off
1844 20:14:48.200099 + cd /lava-954419/0/tests/0_timesync-off
1845 20:14:48.200595 ++ cat uuid
1846 20:14:48.204878 + UUID=954419_1.6.2.4.1
1847 20:14:48.205380 + set +x
1848 20:14:48.212853 <LAVA_SIGNAL_STARTRUN 0_timesync-off 954419_1.6.2.4.1>
1849 20:14:48.213313 + systemctl stop systemd-timesyncd
1850 20:14:48.214075 Received signal: <STARTRUN> 0_timesync-off 954419_1.6.2.4.1
1851 20:14:48.214523 Starting test lava.0_timesync-off (954419_1.6.2.4.1)
1852 20:14:48.215103 Skipping test definition patterns.
1853 20:14:48.272995 + set +x
1854 20:14:48.273540 <LAVA_SIGNAL_ENDRUN 0_timesync-off 954419_1.6.2.4.1>
1855 20:14:48.274213 Received signal: <ENDRUN> 0_timesync-off 954419_1.6.2.4.1
1856 20:14:48.274700 Ending use of test pattern.
1857 20:14:48.275099 Ending test lava.0_timesync-off (954419_1.6.2.4.1), duration 0.06
1859 20:14:48.347032 + export TESTRUN_ID=1_kselftest-alsa
1860 20:14:48.355493 + TESTRUN_ID=1_kselftest-alsa
1861 20:14:48.355969 + cd /lava-954419/0/tests/1_kselftest-alsa
1862 20:14:48.356488 ++ cat uuid
1863 20:14:48.361100 + UUID=954419_1.6.2.4.5
1864 20:14:48.361597 + set +x
1865 20:14:48.366623 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 954419_1.6.2.4.5>
1866 20:14:48.367130 + cd ./automated/linux/kselftest/
1867 20:14:48.367930 Received signal: <STARTRUN> 1_kselftest-alsa 954419_1.6.2.4.5
1868 20:14:48.368448 Starting test lava.1_kselftest-alsa (954419_1.6.2.4.5)
1869 20:14:48.368957 Skipping test definition patterns.
1870 20:14:48.397249 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-244-g7a812b09d88be/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1871 20:14:48.430071 INFO: install_deps skipped
1872 20:14:48.558994 --2024-11-07 20:14:48-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-244-g7a812b09d88be/arm64/defconfig/gcc-12/kselftest.tar.xz
1873 20:14:48.820114 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1874 20:14:48.964488 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1875 20:14:49.114235 HTTP request sent, awaiting response... 200 OK
1876 20:14:49.114758 Length: 6925292 (6.6M) [application/octet-stream]
1877 20:14:49.119620 Saving to: 'kselftest_armhf.tar.gz'
1878 20:14:49.120095
1879 20:14:50.570331
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 47.54K 167KB/s
kselftest_armhf.tar 3%[ ] 216.29K 379KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.02MB/s
kselftest_armhf.tar 53%[=========> ] 3.51M 3.07MB/s
kselftest_armhf.tar 95%[==================> ] 6.33M 4.38MB/s
kselftest_armhf.tar 100%[===================>] 6.60M 4.57MB/s in 1.4s
1880 20:14:50.571031
1881 20:14:50.650506 2024-11-07 20:14:50 (4.57 MB/s) - 'kselftest_armhf.tar.gz' saved [6925292/6925292]
1882 20:14:50.651133
1883 20:14:59.889063 skiplist:
1884 20:14:59.889687 ========================================
1885 20:14:59.894618 ========================================
1886 20:14:59.935565 alsa:mixer-test
1887 20:14:59.936172 alsa:pcm-test
1888 20:14:59.936590 alsa:test-pcmtest-driver
1889 20:14:59.939711 alsa:utimer-test
1890 20:14:59.952653 ============== Tests to run ===============
1891 20:14:59.953120 alsa:mixer-test
1892 20:14:59.958172 alsa:pcm-test
1893 20:14:59.958648 alsa:test-pcmtest-driver
1894 20:14:59.959050 alsa:utimer-test
1895 20:14:59.966520 ===========End Tests to run ===============
1896 20:14:59.967023 shardfile-alsa pass
1897 20:15:00.069246 <12>[ 44.066512] kselftest: Running tests in alsa
1898 20:15:00.075783 TAP version 13
1899 20:15:00.088246 1..4
1900 20:15:00.109476 # timeout set to 45
1901 20:15:00.109976 # selftests: alsa: mixer-test
1902 20:15:00.275902 # TAP version 13
1903 20:15:00.276565 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1904 20:15:00.281227 # 1..427
1905 20:15:00.281698 # ok 1 get_value.LCALTA.60
1906 20:15:00.282105 # # LCALTA.60 TDMOUT_A SRC SEL
1907 20:15:00.286940 # ok 2 name.LCALTA.60
1908 20:15:00.287419 # ok 3 write_default.LCALTA.60
1909 20:15:00.290391 # ok 4 write_valid.LCALTA.60
1910 20:15:00.295961 # ok 5 write_invalid.LCALTA.60
1911 20:15:00.296446 # ok 6 event_missing.LCALTA.60
1912 20:15:00.301484 # ok 7 event_spurious.LCALTA.60
1913 20:15:00.301913 # ok 8 get_value.LCALTA.59
1914 20:15:00.306984 # # LCALTA.59 TDMOUT_B SRC SEL
1915 20:15:00.307415 # ok 9 name.LCALTA.59
1916 20:15:00.312515 # ok 10 write_default.LCALTA.59
1917 20:15:00.313058 # ok 11 write_valid.LCALTA.59
1918 20:15:00.318158 # ok 12 write_invalid.LCALTA.59
1919 20:15:00.318796 # ok 13 event_missing.LCALTA.59
1920 20:15:00.323659 # ok 14 event_spurious.LCALTA.59
1921 20:15:00.324230 # ok 15 get_value.LCALTA.58
1922 20:15:00.329173 # # LCALTA.58 TDMOUT_C SRC SEL
1923 20:15:00.329734 # ok 16 name.LCALTA.58
1924 20:15:00.330220 # ok 17 write_default.LCALTA.58
1925 20:15:00.334694 # ok 18 write_valid.LCALTA.58
1926 20:15:00.335309 # ok 19 write_invalid.LCALTA.58
1927 20:15:00.340262 # ok 20 event_missing.LCALTA.58
1928 20:15:00.340859 # ok 21 event_spurious.LCALTA.58
1929 20:15:00.345769 # ok 22 get_value.LCALTA.57
1930 20:15:00.346328 # # LCALTA.57 TDMIN_A SRC SEL
1931 20:15:00.351384 # ok 23 name.LCALTA.57
1932 20:15:00.351927 # ok 24 write_default.LCALTA.57
1933 20:15:00.356954 # ok 25 write_valid.LCALTA.57
1934 20:15:00.357517 # ok 26 write_invalid.LCALTA.57
1935 20:15:00.362440 # ok 27 event_missing.LCALTA.57
1936 20:15:00.362911 # ok 28 event_spurious.LCALTA.57
1937 20:15:00.368038 # ok 29 get_value.LCALTA.56
1938 20:15:00.368484 # # LCALTA.56 TDMIN_B SRC SEL
1939 20:15:00.373480 # ok 30 name.LCALTA.56
1940 20:15:00.384547 # ok 31 wr<3>[ 44.369187] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1941 20:15:00.385107 ite_default.LCALTA.56
1942 20:15:00.390050 # ok 32 write_valid.LCALTA.56
1943 20:15:00.390478 # ok 33 write_invalid.LCALTA.56
1944 20:15:00.395596 # ok 34 event_missing.LCALTA.56
1945 20:15:00.396053 # ok 35 event_spurious.LCALTA.56
1946 20:15:00.401164 # ok 36 get_value.LCALTA.55
1947 20:15:00.401667 # # LCALTA.55 TDMIN_C SRC SEL
1948 20:15:00.406723 # ok 37 name.LCALTA.55
1949 20:15:00.407167 # ok 38 write_default.LCALTA.55
1950 20:15:00.412259 # ok 39 write_valid.LCALTA.55
1951 20:15:00.412707 # ok 40 write_invalid.LCALTA.55
1952 20:15:00.417883 # ok 41 event_missing.LCALTA.55
1953 20:15:00.418325 # ok 42 event_spurious.LCALTA.55
1954 20:15:00.423349 # ok 43 get_value.LCALTA.54
1955 20:15:00.423772 # # LCALTA.54 ACODEC Left DAC Sel
1956 20:15:00.428890 # ok 44 name.LCALTA.54
1957 20:15:00.429338 # ok 45 write_default.LCALTA.54
1958 20:15:00.434430 # ok 46 write_valid.LCALTA.54
1959 20:15:00.434856 # ok 47 write_invalid.LCALTA.54
1960 20:15:00.440012 # ok 48 event_missing.LCALTA.54
1961 20:15:00.440465 # ok 49 event_spurious.LCALTA.54
1962 20:15:00.445530 # ok 50 get_value.LCALTA.53
1963 20:15:00.445983 # # LCALTA.53 ACODEC Right DAC Sel
1964 20:15:00.451065 # ok 51 name.LCALTA.53
1965 20:15:00.451489 # ok 52 write_default.LCALTA.53
1966 20:15:00.456607 # ok 53 write_valid.LCALTA.53
1967 20:15:00.457031 # ok 54 write_invalid.LCALTA.53
1968 20:15:00.462154 # ok 55 event_missing.LCALTA.53
1969 20:15:00.462575 # ok 56 event_spurious.LCALTA.53
1970 20:15:00.467736 # ok 57 get_value.LCALTA.52
1971 20:15:00.468288 # # LCALTA.52 TOACODEC OUT EN Switch
1972 20:15:00.473264 # ok 58 name.LCALTA.52
1973 20:15:00.473709 # ok 59 write_default.LCALTA.52
1974 20:15:00.478895 # ok 60 write_valid.LCALTA.52
1975 20:15:00.479423 # ok 61 write_invalid.LCALTA.52
1976 20:15:00.484335 # ok 62 event_missing.LCALTA.52
1977 20:15:00.484827 # ok 63 event_spurious.LCALTA.52
1978 20:15:00.489925 # ok 64 get_value.LCALTA.51
1979 20:15:00.490480 # # LCALTA.51 TOACODEC SRC
1980 20:15:00.490963 # ok 65 name.LCALTA.51
1981 20:15:00.495451 # ok 66 write_default.LCALTA.51
1982 20:15:00.495947 # ok 67 write_valid.LCALTA.51
1983 20:15:00.501072 # ok 68 write_invalid.LCALTA.51
1984 20:15:00.501707 # ok 69 event_missing.LCALTA.51
1985 20:15:00.506571 # ok 70 event_spurious.LCALTA.51
1986 20:15:00.507050 # ok 71 get_value.LCALTA.50
1987 20:15:00.512082 # # LCALTA.50 TOHDMITX SPDIF SRC
1988 20:15:00.512535 # ok 72 name.LCALTA.50
1989 20:15:00.517666 # ok 73 write_default.LCALTA.50
1990 20:15:00.518126 # ok 74 write_valid.LCALTA.50
1991 20:15:00.523202 # ok 75 write_invalid.LCALTA.50
1992 20:15:00.523638 # ok 76 event_missing.LCALTA.50
1993 20:15:00.528743 # ok 77 event_spurious.LCALTA.50
1994 20:15:00.529271 # ok 78 get_value.LCALTA.49
1995 20:15:00.534304 # # LCALTA.49 TOHDMITX Switch
1996 20:15:00.534831 # ok 79 name.LCALTA.49
1997 20:15:00.539955 # ok 80 write_default.LCALTA.49
1998 20:15:00.540562 # ok 81 write_valid.LCALTA.49
1999 20:15:00.545377 # ok 82 write_invalid.LCALTA.49
2000 20:15:00.545833 # ok 83 event_missing.LCALTA.49
2001 20:15:00.550937 # ok 84 event_spurious.LCALTA.49
2002 20:15:00.551456 # ok 85 get_value.LCALTA.48
2003 20:15:00.556486 # # LCALTA.48 TOHDMITX I2S SRC
2004 20:15:00.557027 # ok 86 name.LCALTA.48
2005 20:15:00.562021 # ok 87 write_default.LCALTA.48
2006 20:15:00.562501 # ok 88 write_valid.LCALTA.48
2007 20:15:00.567592 # ok 89 write_invalid.LCALTA.48
2008 20:15:00.568181 # ok 90 event_missing.LCALTA.48
2009 20:15:00.573106 # ok 91 event_spurious.LCALTA.48
2010 20:15:00.573563 # ok 92 get_value.LCALTA.47
2011 20:15:00.578657 # # LCALTA.47 TODDR_C SRC SEL
2012 20:15:00.579199 # ok 93 name.LCALTA.47
2013 20:15:00.579689 # ok 94 write_default.LCALTA.47
2014 20:15:00.584192 # ok 95 write_valid.LCALTA.47
2015 20:15:00.584632 # ok 96 write_invalid.LCALTA.47
2016 20:15:00.589760 # ok 97 event_missing.LCALTA.47
2017 20:15:00.595271 # ok 98 event_spurious.LCALTA.47
2018 20:15:00.595710 # ok 99 get_value.LCALTA.46
2019 20:15:00.596153 # # LCALTA.46 TODDR_B SRC SEL
2020 20:15:00.600882 # ok 100 name.LCALTA.46
2021 20:15:00.601361 # ok 101 write_default.LCALTA.46
2022 20:15:00.606355 # ok 102 write_valid.LCALTA.46
2023 20:15:00.606818 # ok 103 write_invalid.LCALTA.46
2024 20:15:00.611926 # ok 104 event_missing.LCALTA.46
2025 20:15:00.617482 # ok 105 event_spurious.LCALTA.46
2026 20:15:00.617911 # ok 106 get_value.LCALTA.45
2027 20:15:00.618305 # # LCALTA.45 TODDR_A SRC SEL
2028 20:15:00.623012 # ok 107 name.LCALTA.45
2029 20:15:00.623438 # ok 108 write_default.LCALTA.45
2030 20:15:00.628589 # ok 109 write_valid.LCALTA.45
2031 20:15:00.629058 # ok 110 write_invalid.LCALTA.45
2032 20:15:00.634107 # ok 111 event_missing.LCALTA.45
2033 20:15:00.634534 # ok 112 event_spurious.LCALTA.45
2034 20:15:00.639659 # ok 113 get_value.LCALTA.44
2035 20:15:00.640118 # # LCALTA.44 FRDDR_C SINK 3 SEL
2036 20:15:00.645195 # ok 114 name.LCALTA.44
2037 20:15:00.645644 # ok 115 write_default.LCALTA.44
2038 20:15:00.650816 # ok 116 write_valid.LCALTA.44
2039 20:15:00.651363 # ok 117 write_invalid.LCALTA.44
2040 20:15:00.656324 # ok 118 event_missing.LCALTA.44
2041 20:15:00.661877 # ok 119 event_spurious.LCALTA.44
2042 20:15:00.662318 # ok 120 get_value.LCALTA.43
2043 20:15:00.667376 # # LCALTA.43 FRDDR_C SINK 2 SEL
2044 20:15:00.667805 # ok 121 name.LCALTA.43
2045 20:15:00.668239 # ok 122 write_default.LCALTA.43
2046 20:15:00.672948 # ok 123 write_valid.LCALTA.43
2047 20:15:00.673380 # ok 124 write_invalid.LCALTA.43
2048 20:15:00.678446 # ok 125 event_missing.LCALTA.43
2049 20:15:00.684052 # ok 126 event_spurious.LCALTA.43
2050 20:15:00.684487 # ok 127 get_value.LCALTA.42
2051 20:15:00.689579 # # LCALTA.42 FRDDR_C SINK 1 SEL
2052 20:15:00.690008 # ok 128 name.LCALTA.42
2053 20:15:00.690400 # ok 129 write_default.LCALTA.42
2054 20:15:00.695112 # ok 130 write_valid.LCALTA.42
2055 20:15:00.700683 # ok 131 write_invalid.LCALTA.42
2056 20:15:00.701151 # ok 132 event_missing.LCALTA.42
2057 20:15:00.706228 # ok 133 event_spurious.LCALTA.42
2058 20:15:00.706683 # ok 134 get_value.LCALTA.41
2059 20:15:00.711790 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
2060 20:15:00.712299 # ok 135 name.LCALTA.41
2061 20:15:00.717347 # ok 136 write_default.LCALTA.41
2062 20:15:00.717806 # ok 137 write_valid.LCALTA.41
2063 20:15:00.722922 # ok 138 write_invalid.LCALTA.41
2064 20:15:00.723380 # ok 139 event_missing.LCALTA.41
2065 20:15:00.728444 # ok 140 event_spurious.LCALTA.41
2066 20:15:00.728894 # ok 141 get_value.LCALTA.40
2067 20:15:00.733958 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
2068 20:15:00.734385 # ok 142 name.LCALTA.40
2069 20:15:00.739484 # ok 143 write_default.LCALTA.40
2070 20:15:00.739898 # ok 144 write_valid.LCALTA.40
2071 20:15:00.745056 # ok 145 write_invalid.LCALTA.40
2072 20:15:00.745475 # ok 146 event_missing.LCALTA.40
2073 20:15:00.750593 # ok 147 event_spurious.LCALTA.40
2074 20:15:00.751007 # ok 148 get_value.LCALTA.39
2075 20:15:00.756150 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
2076 20:15:00.756566 # ok 149 name.LCALTA.39
2077 20:15:00.761679 # ok 150 write_default.LCALTA.39
2078 20:15:00.762096 # ok 151 write_valid.LCALTA.39
2079 20:15:00.767226 # ok 152 write_invalid.LCALTA.39
2080 20:15:00.767647 # ok 153 event_missing.LCALTA.39
2081 20:15:00.772776 # ok 154 event_spurious.LCALTA.39
2082 20:15:00.773197 # ok 155 get_value.LCALTA.38
2083 20:15:00.778298 # # LCALTA.38 FRDDR_B SINK 3 SEL
2084 20:15:00.778737 # ok 156 name.LCALTA.38
2085 20:15:00.783883 # ok 157 write_default.LCALTA.38
2086 20:15:00.784332 # ok 158 write_valid.LCALTA.38
2087 20:15:00.789396 # ok 159 write_invalid.LCALTA.38
2088 20:15:00.789815 # ok 160 event_missing.LCALTA.38
2089 20:15:00.794971 # ok 161 event_spurious.LCALTA.38
2090 20:15:00.795403 # ok 162 get_value.LCALTA.37
2091 20:15:00.800512 # # LCALTA.37 FRDDR_B SINK 2 SEL
2092 20:15:00.800924 # ok 163 name.LCALTA.37
2093 20:15:00.806062 # ok 164 write_default.LCALTA.37
2094 20:15:00.806484 # ok 165 write_valid.LCALTA.37
2095 20:15:00.811612 # ok 166 write_invalid.LCALTA.37
2096 20:15:00.812076 # ok 167 event_missing.LCALTA.37
2097 20:15:00.817143 # ok 168 event_spurious.LCALTA.37
2098 20:15:00.817569 # ok 169 get_value.LCALTA.36
2099 20:15:00.822670 # # LCALTA.36 FRDDR_B SINK 1 SEL
2100 20:15:00.823120 # ok 170 name.LCALTA.36
2101 20:15:00.828223 # ok 171 write_default.LCALTA.36
2102 20:15:00.828656 # ok 172 write_valid.LCALTA.36
2103 20:15:00.833765 # ok 173 write_invalid.LCALTA.36
2104 20:15:00.834204 # ok 174 event_missing.LCALTA.36
2105 20:15:00.839290 # ok 175 event_spurious.LCALTA.36
2106 20:15:00.839707 # ok 176 get_value.LCALTA.35
2107 20:15:00.844895 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
2108 20:15:00.845351 # ok 177 name.LCALTA.35
2109 20:15:00.850453 # ok 178 write_default.LCALTA.35
2110 20:15:00.855953 # ok 179 write_valid.LCALTA.35
2111 20:15:00.856450 # ok 180 write_invalid.LCALTA.35
2112 20:15:00.861519 # ok 181 event_missing.LCALTA.35
2113 20:15:00.861951 # ok 182 event_spurious.LCALTA.35
2114 20:15:00.867075 # ok 183 get_value.LCALTA.34
2115 20:15:00.867510 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
2116 20:15:00.872624 # ok 184 name.LCALTA.34
2117 20:15:00.873049 # ok 185 write_default.LCALTA.34
2118 20:15:00.878194 # ok 186 write_valid.LCALTA.34
2119 20:15:00.878656 # ok 187 write_invalid.LCALTA.34
2120 20:15:00.883748 # ok 188 event_missing.LCALTA.34
2121 20:15:00.884214 # ok 189 event_spurious.LCALTA.34
2122 20:15:00.889281 # ok 190 get_value.LCALTA.33
2123 20:15:00.889712 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
2124 20:15:00.894797 # ok 191 name.LCALTA.33
2125 20:15:00.895215 # ok 192 write_default.LCALTA.33
2126 20:15:00.900354 # ok 193 write_valid.LCALTA.33
2127 20:15:00.900821 # ok 194 write_invalid.LCALTA.33
2128 20:15:00.905873 # ok 195 event_missing.LCALTA.33
2129 20:15:00.906315 # ok 196 event_spurious.LCALTA.33
2130 20:15:00.911418 # ok 197 get_value.LCALTA.32
2131 20:15:00.911874 # # LCALTA.32 FRDDR_A SINK 3 SEL
2132 20:15:00.917017 # ok 198 name.LCALTA.32
2133 20:15:00.917469 # ok 199 write_default.LCALTA.32
2134 20:15:00.922542 # ok 200 write_valid.LCALTA.32
2135 20:15:00.922974 # ok 201 write_invalid.LCALTA.32
2136 20:15:00.928111 # ok 202 event_missing.LCALTA.32
2137 20:15:00.928546 # ok 203 event_spurious.LCALTA.32
2138 20:15:00.933648 # ok 204 get_value.LCALTA.31
2139 20:15:00.934079 # # LCALTA.31 FRDDR_A SINK 2 SEL
2140 20:15:00.939237 # ok 205 name.LCALTA.31
2141 20:15:00.939664 # ok 206 write_default.LCALTA.31
2142 20:15:00.944717 # ok 207 write_valid.LCALTA.31
2143 20:15:00.945150 # ok 208 write_invalid.LCALTA.31
2144 20:15:00.950346 # ok 209 event_missing.LCALTA.31
2145 20:15:00.950878 # ok 210 event_spurious.LCALTA.31
2146 20:15:00.955819 # ok 211 get_value.LCALTA.30
2147 20:15:00.956286 # # LCALTA.30 FRDDR_A SINK 1 SEL
2148 20:15:00.961380 # ok 212 name.LCALTA.30
2149 20:15:00.961813 # ok 213 write_default.LCALTA.30
2150 20:15:00.966951 # ok 214 write_valid.LCALTA.30
2151 20:15:00.967378 # ok 215 write_invalid.LCALTA.30
2152 20:15:00.972483 # ok 216 event_missing.LCALTA.30
2153 20:15:00.972910 # ok 217 event_spurious.LCALTA.30
2154 20:15:00.978020 # ok 218 get_value.LCALTA.29
2155 20:15:00.983576 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2156 20:15:00.984063 # ok 219 name.LCALTA.29
2157 20:15:00.984464 # ok 220 write_default.LCALTA.29
2158 20:15:00.989135 # ok 221 write_valid.LCALTA.29
2159 20:15:00.989596 # ok 222 write_invalid.LCALTA.29
2160 20:15:00.994672 # ok 223 event_missing.LCALTA.29
2161 20:15:01.000189 # ok 224 event_spurious.LCALTA.29
2162 20:15:01.000619 # ok 225 get_value.LCALTA.28
2163 20:15:01.005743 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2164 20:15:01.006203 # ok 226 name.LCALTA.28
2165 20:15:01.011270 # ok 227 write_default.LCALTA.28
2166 20:15:01.011737 # ok 228 write_valid.LCALTA.28
2167 20:15:01.016928 # ok 229 write_invalid.LCALTA.28
2168 20:15:01.017456 # ok 230 event_missing.LCALTA.28
2169 20:15:01.022434 # ok 231 event_spurious.LCALTA.28
2170 20:15:01.022904 # ok 232 get_value.LCALTA.27
2171 20:15:01.027970 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2172 20:15:01.028435 # ok 233 name.LCALTA.27
2173 20:15:01.033451 # ok 234 write_default.LCALTA.27
2174 20:15:01.033880 # ok 235 write_valid.LCALTA.27
2175 20:15:01.038986 # ok 236 write_invalid.LCALTA.27
2176 20:15:01.039408 # ok 237 event_missing.LCALTA.27
2177 20:15:01.044560 # ok 238 event_spurious.LCALTA.27
2178 20:15:01.045024 # ok 239 get_value.LCALTA.26
2179 20:15:01.050125 # # LCALTA.26 ELD
2180 20:15:01.050565 # ok 240 name.LCALTA.26
2181 20:15:01.050959 # # ELD is not writeable
2182 20:15:01.055631 # ok 241 # SKIP write_default.LCALTA.26
2183 20:15:01.056085 # # ELD is not writeable
2184 20:15:01.061194 # ok 242 # SKIP write_valid.LCALTA.26
2185 20:15:01.061655 # # ELD is not writeable
2186 20:15:01.066758 # ok 243 # SKIP write_invalid.LCALTA.26
2187 20:15:01.072308 # ok 244 event_missing.LCALTA.26
2188 20:15:01.072774 # ok 245 event_spurious.LCALTA.26
2189 20:15:01.077815 # ok 246 get_value.LCALTA.25
2190 20:15:01.078261 # # LCALTA.25 IEC958 Playback Default
2191 20:15:01.083351 # ok 247 name.LCALTA.25
2192 20:15:01.083777 # ok 248 write_default.LCALTA.25
2193 20:15:01.088910 # ok 249 # SKIP write_valid.LCALTA.25
2194 20:15:01.089344 # ok 250 # SKIP write_invalid.LCALTA.25
2195 20:15:01.094456 # ok 251 event_missing.LCALTA.25
2196 20:15:01.094878 # ok 252 event_spurious.LCALTA.25
2197 20:15:01.100053 # ok 253 get_value.LCALTA.24
2198 20:15:01.100521 # # LCALTA.24 IEC958 Playback Mask
2199 20:15:01.105557 # ok 254 name.LCALTA.24
2200 20:15:01.111157 # # IEC958 Playback Mask is not writeable
2201 20:15:01.111626 # ok 255 # SKIP write_default.LCALTA.24
2202 20:15:01.116671 # # IEC958 Playback Mask is not writeable
2203 20:15:01.117105 # ok 256 # SKIP write_valid.LCALTA.24
2204 20:15:01.122221 # # IEC958 Playback Mask is not writeable
2205 20:15:01.127771 # ok 257 # SKIP write_invalid.LCALTA.24
2206 20:15:01.128238 # ok 258 event_missing.LCALTA.24
2207 20:15:01.133325 # ok 259 event_spurious.LCALTA.24
2208 20:15:01.133782 # ok 260 get_value.LCALTA.23
2209 20:15:01.138864 # # LCALTA.23 Playback Channel Map
2210 20:15:01.139321 # ok 261 name.LCALTA.23
2211 20:15:01.144400 # # Playback Channel Map is not writeable
2212 20:15:01.149938 # ok 262 # SKIP write_default.LCALTA.23
2213 20:15:01.150365 # # Playback Channel Map is not writeable
2214 20:15:01.155515 # ok 263 # SKIP write_valid.LCALTA.23
2215 20:15:01.161058 # # Playback Channel Map is not writeable
2216 20:15:01.161496 # ok 264 # SKIP write_invalid.LCALTA.23
2217 20:15:01.166595 # ok 265 event_missing.LCALTA.23
2218 20:15:01.167024 # ok 266 event_spurious.LCALTA.23
2219 20:15:01.172173 # ok 267 get_value.LCALTA.22
2220 20:15:01.172598 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2221 20:15:01.177696 # ok 268 name.LCALTA.22
2222 20:15:01.178116 # ok 269 write_default.LCALTA.22
2223 20:15:01.183238 # ok 270 write_valid.LCALTA.22
2224 20:15:01.183663 # ok 271 write_invalid.LCALTA.22
2225 20:15:01.188780 # ok 272 event_missing.LCALTA.22
2226 20:15:01.189208 # ok 273 event_spurious.LCALTA.22
2227 20:15:01.194324 # ok 274 get_value.LCALTA.21
2228 20:15:01.194744 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2229 20:15:01.199862 # ok 275 name.LCALTA.21
2230 20:15:01.200315 # ok 276 write_default.LCALTA.21
2231 20:15:01.205422 # ok 277 write_valid.LCALTA.21
2232 20:15:01.205843 # ok 278 write_invalid.LCALTA.21
2233 20:15:01.210952 # ok 279 event_missing.LCALTA.21
2234 20:15:01.216512 # ok 280 event_spurious.LCALTA.21
2235 20:15:01.216933 # ok 281 get_value.LCALTA.20
2236 20:15:01.222074 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2237 20:15:01.222497 # ok 282 name.LCALTA.20
2238 20:15:01.222892 # ok 283 write_default.LCALTA.20
2239 20:15:01.227609 # ok 284 write_valid.LCALTA.20
2240 20:15:01.233174 # ok 285 write_invalid.LCALTA.20
2241 20:15:01.233639 # ok 286 event_missing.LCALTA.20
2242 20:15:01.238717 # ok 287 event_spurious.LCALTA.20
2243 20:15:01.239171 # ok 288 get_value.LCALTA.19
2244 20:15:01.244246 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2245 20:15:01.244669 # ok 289 name.LCALTA.19
2246 20:15:01.249792 # ok 290 write_default.LCALTA.19
2247 20:15:01.250214 # ok 291 write_valid.LCALTA.19
2248 20:15:01.255348 # ok 292 write_invalid.LCALTA.19
2249 20:15:01.255804 # ok 293 event_missing.LCALTA.19
2250 20:15:01.260919 # ok 294 event_spurious.LCALTA.19
2251 20:15:01.261403 # ok 295 get_value.LCALTA.18
2252 20:15:01.266431 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2253 20:15:01.266869 # ok 296 name.LCALTA.18
2254 20:15:01.272059 # ok 297 write_default.LCALTA.18
2255 20:15:01.272490 # ok 298 write_valid.LCALTA.18
2256 20:15:01.277539 # ok 299 write_invalid.LCALTA.18
2257 20:15:01.277962 # ok 300 event_missing.LCALTA.18
2258 20:15:01.283068 # ok 301 event_spurious.LCALTA.18
2259 20:15:01.283487 # ok 302 get_value.LCALTA.17
2260 20:15:01.288616 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2261 20:15:01.289039 # ok 303 name.LCALTA.17
2262 20:15:01.294188 # ok 304 write_default.LCALTA.17
2263 20:15:01.294615 # ok 305 write_valid.LCALTA.17
2264 20:15:01.299734 # ok 306 write_invalid.LCALTA.17
2265 20:15:01.300191 # ok 307 event_missing.LCALTA.17
2266 20:15:01.305262 # ok 308 event_spurious.LCALTA.17
2267 20:15:01.305681 # ok 309 get_value.LCALTA.16
2268 20:15:01.310810 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2269 20:15:01.311240 # ok 310 name.LCALTA.16
2270 20:15:01.316355 # ok 311 write_default.LCALTA.16
2271 20:15:01.316788 # ok 312 write_valid.LCALTA.16
2272 20:15:01.321991 # ok 313 write_invalid.LCALTA.16
2273 20:15:01.327455 # ok 314 event_missing.LCALTA.16
2274 20:15:01.327879 # ok 315 event_spurious.LCALTA.16
2275 20:15:01.333023 # ok 316 get_value.LCALTA.15
2276 20:15:01.333445 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2277 20:15:01.338551 # ok 317 name.LCALTA.15
2278 20:15:01.338972 # ok 318 write_default.LCALTA.15
2279 20:15:01.344124 # ok 319 write_valid.LCALTA.15
2280 20:15:01.344547 # ok 320 write_invalid.LCALTA.15
2281 20:15:01.349738 # ok 321 event_missing.LCALTA.15
2282 20:15:01.350310 # ok 322 event_spurious.LCALTA.15
2283 20:15:01.355217 # ok 323 get_value.LCALTA.14
2284 20:15:01.355690 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2285 20:15:01.360755 # ok 324 name.LCALTA.14
2286 20:15:01.361233 # ok 325 write_default.LCALTA.14
2287 20:15:01.366303 # ok 326 write_valid.LCALTA.14
2288 20:15:01.366791 # ok 327 write_invalid.LCALTA.14
2289 20:15:01.371860 # ok 328 event_missing.LCALTA.14
2290 20:15:01.372375 # ok 329 event_spurious.LCALTA.14
2291 20:15:01.377382 # ok 330 get_value.LCALTA.13
2292 20:15:01.377815 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2293 20:15:01.383021 # ok 331 name.LCALTA.13
2294 20:15:01.383456 # ok 332 write_default.LCALTA.13
2295 20:15:01.388488 # ok 333 write_valid.LCALTA.13
2296 20:15:01.388994 # ok 334 write_invalid.LCALTA.13
2297 20:15:01.394036 # ok 335 event_missing.LCALTA.13
2298 20:15:01.394506 # ok 336 event_spurious.LCALTA.13
2299 20:15:01.399713 # ok 337 get_value.LCALTA.12
2300 20:15:01.400290 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2301 20:15:01.405148 # ok 338 name.LCALTA.12
2302 20:15:01.405680 # ok 339 write_default.LCALTA.12
2303 20:15:01.410681 # ok 340 write_valid.LCALTA.12
2304 20:15:01.411193 # ok 341 write_invalid.LCALTA.12
2305 20:15:01.416294 # ok 342 event_missing.LCALTA.12
2306 20:15:01.421744 # ok 343 event_spurious.LCALTA.12
2307 20:15:01.422180 # ok 344 get_value.LCALTA.11
2308 20:15:01.427288 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2309 20:15:01.427731 # ok 345 name.LCALTA.11
2310 20:15:01.428196 # ok 346 write_default.LCALTA.11
2311 20:15:01.432878 # ok 347 write_valid.LCALTA.11
2312 20:15:01.438391 # ok 348 write_invalid.LCALTA.11
2313 20:15:01.438830 # ok 349 event_missing.LCALTA.11
2314 20:15:01.444066 # ok 350 event_spurious.LCALTA.11
2315 20:15:01.444558 # ok 351 get_value.LCALTA.10
2316 20:15:01.449525 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2317 20:15:01.450025 # ok 352 name.LCALTA.10
2318 20:15:01.455067 # ok 353 write_default.LCALTA.10
2319 20:15:01.455534 # ok 354 write_valid.LCALTA.10
2320 20:15:01.460583 # ok 355 write_invalid.LCALTA.10
2321 20:15:01.461023 # ok 356 event_missing.LCALTA.10
2322 20:15:01.466129 # ok 357 event_spurious.LCALTA.10
2323 20:15:01.466560 # ok 358 get_value.LCALTA.9
2324 20:15:01.471658 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2325 20:15:01.472114 # ok 359 name.LCALTA.9
2326 20:15:01.477199 # ok 360 write_default.LCALTA.9
2327 20:15:01.477616 # ok 361 write_valid.LCALTA.9
2328 20:15:01.482739 # ok 362 write_invalid.LCALTA.9
2329 20:15:01.483155 # ok 363 event_missing.LCALTA.9
2330 20:15:01.488310 # ok 364 event_spurious.LCALTA.9
2331 20:15:01.488740 # ok 365 get_value.LCALTA.8
2332 20:15:01.493884 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2333 20:15:01.494340 # ok 366 name.LCALTA.8
2334 20:15:01.499405 # ok 367 write_default.LCALTA.8
2335 20:15:01.499834 # ok 368 write_valid.LCALTA.8
2336 20:15:01.505040 # ok 369 write_invalid.LCALTA.8
2337 20:15:01.505495 # ok 370 event_missing.LCALTA.8
2338 20:15:01.510524 # ok 371 event_spurious.LCALTA.8
2339 20:15:01.510966 # ok 372 get_value.LCALTA.7
2340 20:15:01.516071 # # LCALTA.7 ACODEC Unmute Ramp Switch
2341 20:15:01.516515 # ok 373 name.LCALTA.7
2342 20:15:01.521576 # ok 374 write_default.LCALTA.7
2343 20:15:01.522004 # ok 375 write_valid.LCALTA.7
2344 20:15:01.527131 # ok 376 write_invalid.LCALTA.7
2345 20:15:01.527573 # ok 377 event_missing.LCALTA.7
2346 20:15:01.532710 # ok 378 event_spurious.LCALTA.7
2347 20:15:01.533167 # ok 379 get_value.LCALTA.6
2348 20:15:01.538241 # # LCALTA.6 ACODEC Mute Ramp Switch
2349 20:15:01.538701 # ok 380 name.LCALTA.6
2350 20:15:01.543775 # ok 381 write_default.LCALTA.6
2351 20:15:01.544300 # ok 382 write_valid.LCALTA.6
2352 20:15:01.549360 # ok 383 write_invalid.LCALTA.6
2353 20:15:01.549856 # ok 384 event_missing.LCALTA.6
2354 20:15:01.554882 # ok 385 event_spurious.LCALTA.6
2355 20:15:01.555314 # ok 386 get_value.LCALTA.5
2356 20:15:01.560419 # # LCALTA.5 ACODEC Volume Ramp Switch
2357 20:15:01.560847 # ok 387 name.LCALTA.5
2358 20:15:01.566069 # ok 388 write_default.LCALTA.5
2359 20:15:01.566507 # ok 389 write_valid.LCALTA.5
2360 20:15:01.571532 # ok 390 write_invalid.LCALTA.5
2361 20:15:01.571960 # ok 391 event_missing.LCALTA.5
2362 20:15:01.577050 # ok 392 event_spurious.LCALTA.5
2363 20:15:01.577465 # ok 393 get_value.LCALTA.4
2364 20:15:01.582589 # # LCALTA.4 ACODEC Ramp Rate
2365 20:15:01.583002 # ok 394 name.LCALTA.4
2366 20:15:01.583395 # ok 395 write_default.LCALTA.4
2367 20:15:01.588171 # ok 396 write_valid.LCALTA.4
2368 20:15:01.588600 # ok 397 write_invalid.LCALTA.4
2369 20:15:01.593682 # ok 398 event_missing.LCALTA.4
2370 20:15:01.599239 # ok 399 event_spurious.LCALTA.4
2371 20:15:01.599657 # ok 400 get_value.LCALTA.3
2372 20:15:01.604775 # # LCALTA.3 ACODEC Playback Volume
2373 20:15:01.605196 # ok 401 name.LCALTA.3
2374 20:15:01.605588 # ok 402 write_default.LCALTA.3
2375 20:15:01.610340 # ok 403 write_valid.LCALTA.3
2376 20:15:01.610770 # ok 404 write_invalid.LCALTA.3
2377 20:15:01.615888 # ok 405 event_missing.LCALTA.3
2378 20:15:01.616339 # ok 406 event_spurious.LCALTA.3
2379 20:15:01.621429 # ok 407 get_value.LCALTA.2
2380 20:15:01.627048 # # LCALTA.2 ACODEC Playback Switch
2381 20:15:01.627470 # ok 408 name.LCALTA.2
2382 20:15:01.627862 # ok 409 write_default.LCALTA.2
2383 20:15:01.632525 # ok 410 write_valid.LCALTA.2
2384 20:15:01.632945 # ok 411 write_invalid.LCALTA.2
2385 20:15:01.638065 # ok 412 event_missing.LCALTA.2
2386 20:15:01.638490 # ok 413 event_spurious.LCALTA.2
2387 20:15:01.643607 # ok 414 get_value.LCALTA.1
2388 20:15:01.649164 # # LCALTA.1 ACODEC Playback Channel Mode
2389 20:15:01.649590 # ok 415 name.LCALTA.1
2390 20:15:01.649986 # ok 416 write_default.LCALTA.1
2391 20:15:01.654711 # ok 417 write_valid.LCALTA.1
2392 20:15:01.655133 # ok 418 write_invalid.LCALTA.1
2393 20:15:01.660263 # ok 419 event_missing.LCALTA.1
2394 20:15:01.665833 # ok 420 event_spurious.LCALTA.1
2395 20:15:01.666318 # ok 421 get_value.LCALTA.0
2396 20:15:01.671372 # # LCALTA.0 TOACODEC Lane Select
2397 20:15:01.671839 # ok 422 name.LCALTA.0
2398 20:15:01.672272 # ok 423 write_default.LCALTA.0
2399 20:15:01.676912 # ok 424 write_valid.LCALTA.0
2400 20:15:01.677344 # ok 425 write_invalid.LCALTA.0
2401 20:15:01.682429 # ok 426 event_missing.LCALTA.0
2402 20:15:01.682855 # ok 427 event_spurious.LCALTA.0
2403 20:15:01.688059 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2404 20:15:01.693538 ok 1 selftests: alsa: mixer-test
2405 20:15:01.693967 # timeout set to 45
2406 20:15:01.699083 # selftests: alsa: pcm-test
2407 20:15:01.699508 # TAP version 13
2408 20:15:01.704647 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2409 20:15:01.705074 # # LCALTA.0 - fe.dai-link-0 (*)
2410 20:15:01.710174 # # LCALTA.0 - fe.dai-link-1 (*)
2411 20:15:01.710606 # # LCALTA.0 - fe.dai-link-2 (*)
2412 20:15:01.715718 # # LCALTA.0 - fe.dai-link-3 (*)
2413 20:15:01.716173 # # LCALTA.0 - fe.dai-link-4 (*)
2414 20:15:01.721256 # # LCALTA.0 - fe.dai-link-5 (*)
2415 20:15:01.721681 # 1..42
2416 20:15:01.726811 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2417 20:15:01.732403 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2418 20:15:01.732877 # # snd_pcm_hw_params: Invalid argument
2419 20:15:01.737927 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2420 20:15:01.743480 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2421 20:15:01.749076 # # snd_pcm_hw_params: Invalid argument
2422 20:15:01.754554 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2423 20:15:01.760118 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2424 20:15:01.760540 # # snd_pcm_hw_params: Invalid argument
2425 20:15:01.765639 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2426 20:15:01.771173 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2427 20:15:01.776737 # # snd_pcm_hw_params: Invalid argument
2428 20:15:01.782286 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2429 20:15:01.782712 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2430 20:15:01.787824 # # snd_pcm_hw_params: Invalid argument
2431 20:15:01.793371 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2432 20:15:01.798940 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2433 20:15:01.804464 # # snd_pcm_hw_params: Invalid argument
2434 20:15:01.810046 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2435 20:15:01.810470 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2436 20:15:01.816080 # # snd_pcm_hw_params: Invalid argument
2437 20:15:01.821301 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2438 20:15:01.832325 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2439 20:15:01.832971 # # snd_pcm_hw_params: Invalid argument
2440 20:15:01.833400 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2441 20:15:01.837949 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2442 20:15:01.843535 # # snd_pcm_hw_params: Invalid argument
2443 20:15:01.850556 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2444 20:15:01.854699 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2445 20:15:01.855378 # # snd_pcm_hw_params: Invalid argument
2446 20:15:01.860230 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2447 20:15:01.865703 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2448 20:15:01.871349 # # snd_pcm_hw_params: Invalid argument
2449 20:15:01.876790 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2450 20:15:01.882353 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2451 20:15:01.882835 # # snd_pcm_hw_params: Invalid argument
2452 20:15:01.887918 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2453 20:15:01.893423 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2454 20:15:01.898960 # # snd_pcm_hw_params: Invalid argument
2455 20:15:01.904598 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2456 20:15:01.910955 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2457 20:15:01.911552 # # snd_pcm_hw_params: Invalid argument
2458 20:15:01.915701 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2459 20:15:01.921025 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2460 20:15:01.926625 # # snd_pcm_hw_params: Invalid argument
2461 20:15:01.932236 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2462 20:15:01.932896 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2463 20:15:01.937819 # # snd_pcm_hw_params: Invalid argument
2464 20:15:01.943284 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2465 20:15:01.948795 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2466 20:15:01.954526 # # snd_pcm_hw_params: Invalid argument
2467 20:15:01.959923 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2468 20:15:01.960474 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2469 20:15:01.965429 # # snd_pcm_hw_params: Invalid argument
2470 20:15:01.970944 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2471 20:15:01.976553 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2472 20:15:01.977084 # # snd_pcm_hw_params: Invalid argument
2473 20:15:01.987763 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2474 20:15:01.988682 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2475 20:15:01.993256 # # snd_pcm_hw_params: Invalid argument
2476 20:15:01.998858 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2477 20:15:02.004374 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2478 20:15:02.004883 # # snd_pcm_hw_params: Invalid argument
2479 20:15:02.009956 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2480 20:15:02.015465 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2481 20:15:02.020935 # # snd_pcm_hw_params: Invalid argument
2482 20:15:02.026486 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2483 20:15:02.032051 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2484 20:15:02.032536 # # snd_pcm_hw_params: Invalid argument
2485 20:15:02.037554 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2486 20:15:02.043080 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2487 20:15:02.048637 # # snd_pcm_hw_params: Invalid argument
2488 20:15:02.054179 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2489 20:15:02.059726 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2490 20:15:02.060234 # # snd_pcm_hw_params: Invalid argument
2491 20:15:02.065258 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2492 20:15:02.070779 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2493 20:15:02.076509 # # snd_pcm_hw_params: Invalid argument
2494 20:15:02.082010 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2495 20:15:02.087569 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2496 20:15:02.088440 # # snd_pcm_hw_params: Invalid argument
2497 20:15:02.093020 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2498 20:15:02.098739 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2499 20:15:02.104216 # # snd_pcm_hw_params: Invalid argument
2500 20:15:02.109987 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2501 20:15:02.115337 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2502 20:15:02.116289 # # snd_pcm_hw_params: Invalid argument
2503 20:15:02.120886 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2504 20:15:02.126279 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2505 20:15:02.131844 # # snd_pcm_hw_params: Invalid argument
2506 20:15:02.137470 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2507 20:15:02.143045 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2508 20:15:02.143796 # # snd_pcm_hw_params: Invalid argument
2509 20:15:02.148594 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2510 20:15:02.154124 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2511 20:15:02.159593 # # snd_pcm_hw_params: Invalid argument
2512 20:15:02.165091 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2513 20:15:02.170661 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2514 20:15:02.171169 # # snd_pcm_hw_params: Invalid argument
2515 20:15:02.176278 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2516 20:15:02.181770 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2517 20:15:02.187295 # # snd_pcm_hw_params: Invalid argument
2518 20:15:02.192826 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2519 20:15:02.198392 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2520 20:15:02.198857 # # snd_pcm_hw_params: Invalid argument
2521 20:15:02.203954 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2522 20:15:02.209437 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2523 20:15:02.215016 # # snd_pcm_hw_params: Invalid argument
2524 20:15:02.220821 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2525 20:15:02.221565 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2526 20:15:02.226243 # # snd_pcm_hw_params: Invalid argument
2527 20:15:02.231749 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2528 20:15:02.237307 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2529 20:15:02.242886 # # snd_pcm_hw_params: Invalid argument
2530 20:15:02.248409 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2531 20:15:02.249168 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2532 20:15:02.253940 # # snd_pcm_hw_params: Invalid argument
2533 20:15:02.259546 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2534 20:15:02.265052 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2535 20:15:02.270796 # # snd_pcm_hw_params: Invalid argument
2536 20:15:02.276214 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2537 20:15:02.277079 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2538 20:15:02.281743 # # snd_pcm_hw_params: Invalid argument
2539 20:15:02.287260 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2540 20:15:02.292847 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2541 20:15:02.298352 # # snd_pcm_hw_params: Invalid argument
2542 20:15:02.303905 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2543 20:15:02.304773 ok 2 selftests: alsa: pcm-test
2544 20:15:02.305509 # timeout set to 45
2545 20:15:02.309428 # selftests: alsa: test-pcmtest-driver
2546 20:15:02.310278 # TAP version 13
2547 20:15:02.310927 # 1..5
2548 20:15:02.314969 # # Starting 5 tests from 1 test cases.
2549 20:15:02.320544 # # RUN pcmtest.playback ...
2550 20:15:02.326079 # # SKIP Can't read patterns. Probably, module isn't loaded
2551 20:15:02.326887 # # OK pcmtest.playback
2552 20:15:02.337014 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2553 20:15:02.337516 # # RUN pcmtest.capture ...
2554 20:15:02.342687 # # SKIP Can't read patterns. Probably, module isn't loaded
2555 20:15:02.348337 # # OK pcmtest.capture
2556 20:15:02.353836 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2557 20:15:02.359508 # # RUN pcmtest.ni_capture ...
2558 20:15:02.364869 # # SKIP Can't read patterns. Probably, module isn't loaded
2559 20:15:02.370615 # # OK pcmtest.ni_capture
2560 20:15:02.375967 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2561 20:15:02.381475 # # RUN pcmtest.ni_playback ...
2562 20:15:02.387182 # # SKIP Can't read patterns. Probably, module isn't loaded
2563 20:15:02.388048 # # OK pcmtest.ni_playback
2564 20:15:02.398028 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2565 20:15:02.398536 # # RUN pcmtest.reset_ioctl ...
2566 20:15:02.403636 # # SKIP Can't read patterns. Probably, module isn't loaded
2567 20:15:02.409168 # # OK pcmtest.reset_ioctl
2568 20:15:02.414889 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2569 20:15:02.420300 # # PASSED: 5 / 5 tests passed.
2570 20:15:02.425798 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2571 20:15:02.431344 ok 3 selftests: alsa: test-pcmtest-driver
2572 20:15:02.431837 # timeout set to 45
2573 20:15:02.432279 # selftests: alsa: utimer-test
2574 20:15:02.436940 # TAP version 13
2575 20:15:02.437430 # 1..2
2576 20:15:02.437841 # # Starting 2 tests from 2 test cases.
2577 20:15:02.442550 # # RUN global.wrong_timers_test ...
2578 20:15:02.448006 # # OK global.wrong_timers_test
2579 20:15:02.448504 # ok 1 global.wrong_timers_test
2580 20:15:02.453539 # # RUN timer_f.utimer ...
2581 20:15:02.464678 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2582 20:15:02.470387 # # utimer: Test terminated by assertion
2583 20:15:02.471233 # # FAIL timer_f.utimer
2584 20:15:02.471876 # not ok 2 timer_f.utimer
2585 20:15:02.475820 # # FAILED: 1 / 2 tests passed.
2586 20:15:02.481468 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2587 20:15:02.485294 not ok 4 selftests: alsa: utimer-test # exit=1
2588 20:15:03.097573 alsa_mixer-test_get_value_LCALTA_60 pass
2589 20:15:03.102811 alsa_mixer-test_name_LCALTA_60 pass
2590 20:15:03.103329 alsa_mixer-test_write_default_LCALTA_60 pass
2591 20:15:03.108414 alsa_mixer-test_write_valid_LCALTA_60 pass
2592 20:15:03.113944 alsa_mixer-test_write_invalid_LCALTA_60 pass
2593 20:15:03.119481 alsa_mixer-test_event_missing_LCALTA_60 pass
2594 20:15:03.119967 alsa_mixer-test_event_spurious_LCALTA_60 pass
2595 20:15:03.125016 alsa_mixer-test_get_value_LCALTA_59 pass
2596 20:15:03.130576 alsa_mixer-test_name_LCALTA_59 pass
2597 20:15:03.131073 alsa_mixer-test_write_default_LCALTA_59 pass
2598 20:15:03.136115 alsa_mixer-test_write_valid_LCALTA_59 pass
2599 20:15:03.141666 alsa_mixer-test_write_invalid_LCALTA_59 pass
2600 20:15:03.142156 alsa_mixer-test_event_missing_LCALTA_59 pass
2601 20:15:03.147206 alsa_mixer-test_event_spurious_LCALTA_59 pass
2602 20:15:03.152752 alsa_mixer-test_get_value_LCALTA_58 pass
2603 20:15:03.153250 alsa_mixer-test_name_LCALTA_58 pass
2604 20:15:03.158343 alsa_mixer-test_write_default_LCALTA_58 pass
2605 20:15:03.163852 alsa_mixer-test_write_valid_LCALTA_58 pass
2606 20:15:03.164379 alsa_mixer-test_write_invalid_LCALTA_58 pass
2607 20:15:03.169398 alsa_mixer-test_event_missing_LCALTA_58 pass
2608 20:15:03.174958 alsa_mixer-test_event_spurious_LCALTA_58 pass
2609 20:15:03.180487 alsa_mixer-test_get_value_LCALTA_57 pass
2610 20:15:03.181014 alsa_mixer-test_name_LCALTA_57 pass
2611 20:15:03.186057 alsa_mixer-test_write_default_LCALTA_57 pass
2612 20:15:03.191598 alsa_mixer-test_write_valid_LCALTA_57 pass
2613 20:15:03.192130 alsa_mixer-test_write_invalid_LCALTA_57 pass
2614 20:15:03.197121 alsa_mixer-test_event_missing_LCALTA_57 pass
2615 20:15:03.202678 alsa_mixer-test_event_spurious_LCALTA_57 pass
2616 20:15:03.203175 alsa_mixer-test_get_value_LCALTA_56 pass
2617 20:15:03.208259 alsa_mixer-test_name_LCALTA_56 pass
2618 20:15:03.213774 alsa_mixer-test_write_default_LCALTA_56 pass
2619 20:15:03.214274 alsa_mixer-test_write_valid_LCALTA_56 pass
2620 20:15:03.219344 alsa_mixer-test_write_invalid_LCALTA_56 pass
2621 20:15:03.224872 alsa_mixer-test_event_missing_LCALTA_56 pass
2622 20:15:03.230452 alsa_mixer-test_event_spurious_LCALTA_56 pass
2623 20:15:03.230960 alsa_mixer-test_get_value_LCALTA_55 pass
2624 20:15:03.236028 alsa_mixer-test_name_LCALTA_55 pass
2625 20:15:03.241542 alsa_mixer-test_write_default_LCALTA_55 pass
2626 20:15:03.242055 alsa_mixer-test_write_valid_LCALTA_55 pass
2627 20:15:03.247087 alsa_mixer-test_write_invalid_LCALTA_55 pass
2628 20:15:03.252631 alsa_mixer-test_event_missing_LCALTA_55 pass
2629 20:15:03.253136 alsa_mixer-test_event_spurious_LCALTA_55 pass
2630 20:15:03.258165 alsa_mixer-test_get_value_LCALTA_54 pass
2631 20:15:03.263723 alsa_mixer-test_name_LCALTA_54 pass
2632 20:15:03.264258 alsa_mixer-test_write_default_LCALTA_54 pass
2633 20:15:03.269268 alsa_mixer-test_write_valid_LCALTA_54 pass
2634 20:15:03.274810 alsa_mixer-test_write_invalid_LCALTA_54 pass
2635 20:15:03.275319 alsa_mixer-test_event_missing_LCALTA_54 pass
2636 20:15:03.280385 alsa_mixer-test_event_spurious_LCALTA_54 pass
2637 20:15:03.285891 alsa_mixer-test_get_value_LCALTA_53 pass
2638 20:15:03.286388 alsa_mixer-test_name_LCALTA_53 pass
2639 20:15:03.291464 alsa_mixer-test_write_default_LCALTA_53 pass
2640 20:15:03.297101 alsa_mixer-test_write_valid_LCALTA_53 pass
2641 20:15:03.302604 alsa_mixer-test_write_invalid_LCALTA_53 pass
2642 20:15:03.303155 alsa_mixer-test_event_missing_LCALTA_53 pass
2643 20:15:03.308105 alsa_mixer-test_event_spurious_LCALTA_53 pass
2644 20:15:03.313643 alsa_mixer-test_get_value_LCALTA_52 pass
2645 20:15:03.314161 alsa_mixer-test_name_LCALTA_52 pass
2646 20:15:03.319178 alsa_mixer-test_write_default_LCALTA_52 pass
2647 20:15:03.324703 alsa_mixer-test_write_valid_LCALTA_52 pass
2648 20:15:03.325195 alsa_mixer-test_write_invalid_LCALTA_52 pass
2649 20:15:03.330265 alsa_mixer-test_event_missing_LCALTA_52 pass
2650 20:15:03.335854 alsa_mixer-test_event_spurious_LCALTA_52 pass
2651 20:15:03.336411 alsa_mixer-test_get_value_LCALTA_51 pass
2652 20:15:03.341399 alsa_mixer-test_name_LCALTA_51 pass
2653 20:15:03.346911 alsa_mixer-test_write_default_LCALTA_51 pass
2654 20:15:03.347402 alsa_mixer-test_write_valid_LCALTA_51 pass
2655 20:15:03.352440 alsa_mixer-test_write_invalid_LCALTA_51 pass
2656 20:15:03.358009 alsa_mixer-test_event_missing_LCALTA_51 pass
2657 20:15:03.363547 alsa_mixer-test_event_spurious_LCALTA_51 pass
2658 20:15:03.364063 alsa_mixer-test_get_value_LCALTA_50 pass
2659 20:15:03.369090 alsa_mixer-test_name_LCALTA_50 pass
2660 20:15:03.374630 alsa_mixer-test_write_default_LCALTA_50 pass
2661 20:15:03.375123 alsa_mixer-test_write_valid_LCALTA_50 pass
2662 20:15:03.380237 alsa_mixer-test_write_invalid_LCALTA_50 pass
2663 20:15:03.385786 alsa_mixer-test_event_missing_LCALTA_50 pass
2664 20:15:03.386302 alsa_mixer-test_event_spurious_LCALTA_50 pass
2665 20:15:03.391295 alsa_mixer-test_get_value_LCALTA_49 pass
2666 20:15:03.396833 alsa_mixer-test_name_LCALTA_49 pass
2667 20:15:03.397327 alsa_mixer-test_write_default_LCALTA_49 pass
2668 20:15:03.402391 alsa_mixer-test_write_valid_LCALTA_49 pass
2669 20:15:03.407899 alsa_mixer-test_write_invalid_LCALTA_49 pass
2670 20:15:03.413498 alsa_mixer-test_event_missing_LCALTA_49 pass
2671 20:15:03.414003 alsa_mixer-test_event_spurious_LCALTA_49 pass
2672 20:15:03.419042 alsa_mixer-test_get_value_LCALTA_48 pass
2673 20:15:03.419545 alsa_mixer-test_name_LCALTA_48 pass
2674 20:15:03.424568 alsa_mixer-test_write_default_LCALTA_48 pass
2675 20:15:03.430118 alsa_mixer-test_write_valid_LCALTA_48 pass
2676 20:15:03.435654 alsa_mixer-test_write_invalid_LCALTA_48 pass
2677 20:15:03.436179 alsa_mixer-test_event_missing_LCALTA_48 pass
2678 20:15:03.441214 alsa_mixer-test_event_spurious_LCALTA_48 pass
2679 20:15:03.446767 alsa_mixer-test_get_value_LCALTA_47 pass
2680 20:15:03.447264 alsa_mixer-test_name_LCALTA_47 pass
2681 20:15:03.452328 alsa_mixer-test_write_default_LCALTA_47 pass
2682 20:15:03.457858 alsa_mixer-test_write_valid_LCALTA_47 pass
2683 20:15:03.458382 alsa_mixer-test_write_invalid_LCALTA_47 pass
2684 20:15:03.463393 alsa_mixer-test_event_missing_LCALTA_47 pass
2685 20:15:03.468930 alsa_mixer-test_event_spurious_LCALTA_47 pass
2686 20:15:03.474476 alsa_mixer-test_get_value_LCALTA_46 pass
2687 20:15:03.474974 alsa_mixer-test_name_LCALTA_46 pass
2688 20:15:03.480050 alsa_mixer-test_write_default_LCALTA_46 pass
2689 20:15:03.485587 alsa_mixer-test_write_valid_LCALTA_46 pass
2690 20:15:03.486136 alsa_mixer-test_write_invalid_LCALTA_46 pass
2691 20:15:03.491181 alsa_mixer-test_event_missing_LCALTA_46 pass
2692 20:15:03.496731 alsa_mixer-test_event_spurious_LCALTA_46 pass
2693 20:15:03.497285 alsa_mixer-test_get_value_LCALTA_45 pass
2694 20:15:03.502222 alsa_mixer-test_name_LCALTA_45 pass
2695 20:15:03.507761 alsa_mixer-test_write_default_LCALTA_45 pass
2696 20:15:03.508312 alsa_mixer-test_write_valid_LCALTA_45 pass
2697 20:15:03.513330 alsa_mixer-test_write_invalid_LCALTA_45 pass
2698 20:15:03.518896 alsa_mixer-test_event_missing_LCALTA_45 pass
2699 20:15:03.519424 alsa_mixer-test_event_spurious_LCALTA_45 pass
2700 20:15:03.524420 alsa_mixer-test_get_value_LCALTA_44 pass
2701 20:15:03.530027 alsa_mixer-test_name_LCALTA_44 pass
2702 20:15:03.530566 alsa_mixer-test_write_default_LCALTA_44 pass
2703 20:15:03.535494 alsa_mixer-test_write_valid_LCALTA_44 pass
2704 20:15:03.541055 alsa_mixer-test_write_invalid_LCALTA_44 pass
2705 20:15:03.546608 alsa_mixer-test_event_missing_LCALTA_44 pass
2706 20:15:03.547144 alsa_mixer-test_event_spurious_LCALTA_44 pass
2707 20:15:03.552223 alsa_mixer-test_get_value_LCALTA_43 pass
2708 20:15:03.557719 alsa_mixer-test_name_LCALTA_43 pass
2709 20:15:03.558240 alsa_mixer-test_write_default_LCALTA_43 pass
2710 20:15:03.563254 alsa_mixer-test_write_valid_LCALTA_43 pass
2711 20:15:03.568856 alsa_mixer-test_write_invalid_LCALTA_43 pass
2712 20:15:03.569449 alsa_mixer-test_event_missing_LCALTA_43 pass
2713 20:15:03.574324 alsa_mixer-test_event_spurious_LCALTA_43 pass
2714 20:15:03.579882 alsa_mixer-test_get_value_LCALTA_42 pass
2715 20:15:03.580432 alsa_mixer-test_name_LCALTA_42 pass
2716 20:15:03.585404 alsa_mixer-test_write_default_LCALTA_42 pass
2717 20:15:03.590950 alsa_mixer-test_write_valid_LCALTA_42 pass
2718 20:15:03.591462 alsa_mixer-test_write_invalid_LCALTA_42 pass
2719 20:15:03.596481 alsa_mixer-test_event_missing_LCALTA_42 pass
2720 20:15:03.602047 alsa_mixer-test_event_spurious_LCALTA_42 pass
2721 20:15:03.607613 alsa_mixer-test_get_value_LCALTA_41 pass
2722 20:15:03.608172 alsa_mixer-test_name_LCALTA_41 pass
2723 20:15:03.613201 alsa_mixer-test_write_default_LCALTA_41 pass
2724 20:15:03.618703 alsa_mixer-test_write_valid_LCALTA_41 pass
2725 20:15:03.619251 alsa_mixer-test_write_invalid_LCALTA_41 pass
2726 20:15:03.624265 alsa_mixer-test_event_missing_LCALTA_41 pass
2727 20:15:03.629788 alsa_mixer-test_event_spurious_LCALTA_41 pass
2728 20:15:03.630292 alsa_mixer-test_get_value_LCALTA_40 pass
2729 20:15:03.635315 alsa_mixer-test_name_LCALTA_40 pass
2730 20:15:03.640858 alsa_mixer-test_write_default_LCALTA_40 pass
2731 20:15:03.641370 alsa_mixer-test_write_valid_LCALTA_40 pass
2732 20:15:03.646408 alsa_mixer-test_write_invalid_LCALTA_40 pass
2733 20:15:03.651971 alsa_mixer-test_event_missing_LCALTA_40 pass
2734 20:15:03.657563 alsa_mixer-test_event_spurious_LCALTA_40 pass
2735 20:15:03.658146 alsa_mixer-test_get_value_LCALTA_39 pass
2736 20:15:03.663079 alsa_mixer-test_name_LCALTA_39 pass
2737 20:15:03.668624 alsa_mixer-test_write_default_LCALTA_39 pass
2738 20:15:03.669120 alsa_mixer-test_write_valid_LCALTA_39 pass
2739 20:15:03.674168 alsa_mixer-test_write_invalid_LCALTA_39 pass
2740 20:15:03.679690 alsa_mixer-test_event_missing_LCALTA_39 pass
2741 20:15:03.680213 alsa_mixer-test_event_spurious_LCALTA_39 pass
2742 20:15:03.685248 alsa_mixer-test_get_value_LCALTA_38 pass
2743 20:15:03.690792 alsa_mixer-test_name_LCALTA_38 pass
2744 20:15:03.691271 alsa_mixer-test_write_default_LCALTA_38 pass
2745 20:15:03.696431 alsa_mixer-test_write_valid_LCALTA_38 pass
2746 20:15:03.701892 alsa_mixer-test_write_invalid_LCALTA_38 pass
2747 20:15:03.702371 alsa_mixer-test_event_missing_LCALTA_38 pass
2748 20:15:03.707428 alsa_mixer-test_event_spurious_LCALTA_38 pass
2749 20:15:03.712960 alsa_mixer-test_get_value_LCALTA_37 pass
2750 20:15:03.713439 alsa_mixer-test_name_LCALTA_37 pass
2751 20:15:03.718528 alsa_mixer-test_write_default_LCALTA_37 pass
2752 20:15:03.724092 alsa_mixer-test_write_valid_LCALTA_37 pass
2753 20:15:03.729632 alsa_mixer-test_write_invalid_LCALTA_37 pass
2754 20:15:03.730112 alsa_mixer-test_event_missing_LCALTA_37 pass
2755 20:15:03.735207 alsa_mixer-test_event_spurious_LCALTA_37 pass
2756 20:15:03.740737 alsa_mixer-test_get_value_LCALTA_36 pass
2757 20:15:03.741216 alsa_mixer-test_name_LCALTA_36 pass
2758 20:15:03.746268 alsa_mixer-test_write_default_LCALTA_36 pass
2759 20:15:03.751822 alsa_mixer-test_write_valid_LCALTA_36 pass
2760 20:15:03.752340 alsa_mixer-test_write_invalid_LCALTA_36 pass
2761 20:15:03.757384 alsa_mixer-test_event_missing_LCALTA_36 pass
2762 20:15:03.762912 alsa_mixer-test_event_spurious_LCALTA_36 pass
2763 20:15:03.763389 alsa_mixer-test_get_value_LCALTA_35 pass
2764 20:15:03.768476 alsa_mixer-test_name_LCALTA_35 pass
2765 20:15:03.774011 alsa_mixer-test_write_default_LCALTA_35 pass
2766 20:15:03.774503 alsa_mixer-test_write_valid_LCALTA_35 pass
2767 20:15:03.779623 alsa_mixer-test_write_invalid_LCALTA_35 pass
2768 20:15:03.785111 alsa_mixer-test_event_missing_LCALTA_35 pass
2769 20:15:03.790674 alsa_mixer-test_event_spurious_LCALTA_35 pass
2770 20:15:03.791175 alsa_mixer-test_get_value_LCALTA_34 pass
2771 20:15:03.796260 alsa_mixer-test_name_LCALTA_34 pass
2772 20:15:03.801728 alsa_mixer-test_write_default_LCALTA_34 pass
2773 20:15:03.802217 alsa_mixer-test_write_valid_LCALTA_34 pass
2774 20:15:03.807286 alsa_mixer-test_write_invalid_LCALTA_34 pass
2775 20:15:03.812821 alsa_mixer-test_event_missing_LCALTA_34 pass
2776 20:15:03.813298 alsa_mixer-test_event_spurious_LCALTA_34 pass
2777 20:15:03.818372 alsa_mixer-test_get_value_LCALTA_33 pass
2778 20:15:03.823923 alsa_mixer-test_name_LCALTA_33 pass
2779 20:15:03.824430 alsa_mixer-test_write_default_LCALTA_33 pass
2780 20:15:03.829509 alsa_mixer-test_write_valid_LCALTA_33 pass
2781 20:15:03.835020 alsa_mixer-test_write_invalid_LCALTA_33 pass
2782 20:15:03.840557 alsa_mixer-test_event_missing_LCALTA_33 pass
2783 20:15:03.841037 alsa_mixer-test_event_spurious_LCALTA_33 pass
2784 20:15:03.846079 alsa_mixer-test_get_value_LCALTA_32 pass
2785 20:15:03.846554 alsa_mixer-test_name_LCALTA_32 pass
2786 20:15:03.851641 alsa_mixer-test_write_default_LCALTA_32 pass
2787 20:15:03.857176 alsa_mixer-test_write_valid_LCALTA_32 pass
2788 20:15:03.862724 alsa_mixer-test_write_invalid_LCALTA_32 pass
2789 20:15:03.863198 alsa_mixer-test_event_missing_LCALTA_32 pass
2790 20:15:03.868291 alsa_mixer-test_event_spurious_LCALTA_32 pass
2791 20:15:03.873836 alsa_mixer-test_get_value_LCALTA_31 pass
2792 20:15:03.874321 alsa_mixer-test_name_LCALTA_31 pass
2793 20:15:03.879434 alsa_mixer-test_write_default_LCALTA_31 pass
2794 20:15:03.884920 alsa_mixer-test_write_valid_LCALTA_31 pass
2795 20:15:03.885395 alsa_mixer-test_write_invalid_LCALTA_31 pass
2796 20:15:03.890488 alsa_mixer-test_event_missing_LCALTA_31 pass
2797 20:15:03.896036 alsa_mixer-test_event_spurious_LCALTA_31 pass
2798 20:15:03.901594 alsa_mixer-test_get_value_LCALTA_30 pass
2799 20:15:03.902081 alsa_mixer-test_name_LCALTA_30 pass
2800 20:15:03.907125 alsa_mixer-test_write_default_LCALTA_30 pass
2801 20:15:03.912681 alsa_mixer-test_write_valid_LCALTA_30 pass
2802 20:15:03.913162 alsa_mixer-test_write_invalid_LCALTA_30 pass
2803 20:15:03.918209 alsa_mixer-test_event_missing_LCALTA_30 pass
2804 20:15:03.923752 alsa_mixer-test_event_spurious_LCALTA_30 pass
2805 20:15:03.924262 alsa_mixer-test_get_value_LCALTA_29 pass
2806 20:15:03.929332 alsa_mixer-test_name_LCALTA_29 pass
2807 20:15:03.934860 alsa_mixer-test_write_default_LCALTA_29 pass
2808 20:15:03.935336 alsa_mixer-test_write_valid_LCALTA_29 pass
2809 20:15:03.940491 alsa_mixer-test_write_invalid_LCALTA_29 pass
2810 20:15:03.945951 alsa_mixer-test_event_missing_LCALTA_29 pass
2811 20:15:03.946425 alsa_mixer-test_event_spurious_LCALTA_29 pass
2812 20:15:03.951507 alsa_mixer-test_get_value_LCALTA_28 pass
2813 20:15:03.957064 alsa_mixer-test_name_LCALTA_28 pass
2814 20:15:03.957563 alsa_mixer-test_write_default_LCALTA_28 pass
2815 20:15:03.962612 alsa_mixer-test_write_valid_LCALTA_28 pass
2816 20:15:03.968165 alsa_mixer-test_write_invalid_LCALTA_28 pass
2817 20:15:03.973673 alsa_mixer-test_event_missing_LCALTA_28 pass
2818 20:15:03.974149 alsa_mixer-test_event_spurious_LCALTA_28 pass
2819 20:15:03.979228 alsa_mixer-test_get_value_LCALTA_27 pass
2820 20:15:03.984779 alsa_mixer-test_name_LCALTA_27 pass
2821 20:15:03.985252 alsa_mixer-test_write_default_LCALTA_27 pass
2822 20:15:03.990343 alsa_mixer-test_write_valid_LCALTA_27 pass
2823 20:15:03.995853 alsa_mixer-test_write_invalid_LCALTA_27 pass
2824 20:15:03.996356 alsa_mixer-test_event_missing_LCALTA_27 pass
2825 20:15:04.001503 alsa_mixer-test_event_spurious_LCALTA_27 pass
2826 20:15:04.006960 alsa_mixer-test_get_value_LCALTA_26 pass
2827 20:15:04.007436 alsa_mixer-test_name_LCALTA_26 pass
2828 20:15:04.012515 alsa_mixer-test_write_default_LCALTA_26 skip
2829 20:15:04.018033 alsa_mixer-test_write_valid_LCALTA_26 skip
2830 20:15:04.018506 alsa_mixer-test_write_invalid_LCALTA_26 skip
2831 20:15:04.023673 alsa_mixer-test_event_missing_LCALTA_26 pass
2832 20:15:04.029216 alsa_mixer-test_event_spurious_LCALTA_26 pass
2833 20:15:04.034774 alsa_mixer-test_get_value_LCALTA_25 pass
2834 20:15:04.035307 alsa_mixer-test_name_LCALTA_25 pass
2835 20:15:04.040269 alsa_mixer-test_write_default_LCALTA_25 pass
2836 20:15:04.045781 alsa_mixer-test_write_valid_LCALTA_25 skip
2837 20:15:04.046254 alsa_mixer-test_write_invalid_LCALTA_25 skip
2838 20:15:04.051337 alsa_mixer-test_event_missing_LCALTA_25 pass
2839 20:15:04.056878 alsa_mixer-test_event_spurious_LCALTA_25 pass
2840 20:15:04.057381 alsa_mixer-test_get_value_LCALTA_24 pass
2841 20:15:04.062487 alsa_mixer-test_name_LCALTA_24 pass
2842 20:15:04.067957 alsa_mixer-test_write_default_LCALTA_24 skip
2843 20:15:04.068524 alsa_mixer-test_write_valid_LCALTA_24 skip
2844 20:15:04.073532 alsa_mixer-test_write_invalid_LCALTA_24 skip
2845 20:15:04.079039 alsa_mixer-test_event_missing_LCALTA_24 pass
2846 20:15:04.084587 alsa_mixer-test_event_spurious_LCALTA_24 pass
2847 20:15:04.085067 alsa_mixer-test_get_value_LCALTA_23 pass
2848 20:15:04.090131 alsa_mixer-test_name_LCALTA_23 pass
2849 20:15:04.095711 alsa_mixer-test_write_default_LCALTA_23 skip
2850 20:15:04.096230 alsa_mixer-test_write_valid_LCALTA_23 skip
2851 20:15:04.101246 alsa_mixer-test_write_invalid_LCALTA_23 skip
2852 20:15:04.106802 alsa_mixer-test_event_missing_LCALTA_23 pass
2853 20:15:04.107291 alsa_mixer-test_event_spurious_LCALTA_23 pass
2854 20:15:04.112387 alsa_mixer-test_get_value_LCALTA_22 pass
2855 20:15:04.117898 alsa_mixer-test_name_LCALTA_22 pass
2856 20:15:04.118380 alsa_mixer-test_write_default_LCALTA_22 pass
2857 20:15:04.123505 alsa_mixer-test_write_valid_LCALTA_22 pass
2858 20:15:04.128998 alsa_mixer-test_write_invalid_LCALTA_22 pass
2859 20:15:04.129481 alsa_mixer-test_event_missing_LCALTA_22 pass
2860 20:15:04.134562 alsa_mixer-test_event_spurious_LCALTA_22 pass
2861 20:15:04.140124 alsa_mixer-test_get_value_LCALTA_21 pass
2862 20:15:04.140614 alsa_mixer-test_name_LCALTA_21 pass
2863 20:15:04.145651 alsa_mixer-test_write_default_LCALTA_21 pass
2864 20:15:04.151188 alsa_mixer-test_write_valid_LCALTA_21 pass
2865 20:15:04.156750 alsa_mixer-test_write_invalid_LCALTA_21 pass
2866 20:15:04.157240 alsa_mixer-test_event_missing_LCALTA_21 pass
2867 20:15:04.162318 alsa_mixer-test_event_spurious_LCALTA_21 pass
2868 20:15:04.167851 alsa_mixer-test_get_value_LCALTA_20 pass
2869 20:15:04.168399 alsa_mixer-test_name_LCALTA_20 pass
2870 20:15:04.173397 alsa_mixer-test_write_default_LCALTA_20 pass
2871 20:15:04.178927 alsa_mixer-test_write_valid_LCALTA_20 pass
2872 20:15:04.179406 alsa_mixer-test_write_invalid_LCALTA_20 pass
2873 20:15:04.184548 alsa_mixer-test_event_missing_LCALTA_20 pass
2874 20:15:04.190001 alsa_mixer-test_event_spurious_LCALTA_20 pass
2875 20:15:04.190485 alsa_mixer-test_get_value_LCALTA_19 pass
2876 20:15:04.195570 alsa_mixer-test_name_LCALTA_19 pass
2877 20:15:04.201115 alsa_mixer-test_write_default_LCALTA_19 pass
2878 20:15:04.201603 alsa_mixer-test_write_valid_LCALTA_19 pass
2879 20:15:04.206649 alsa_mixer-test_write_invalid_LCALTA_19 pass
2880 20:15:04.212237 alsa_mixer-test_event_missing_LCALTA_19 pass
2881 20:15:04.217753 alsa_mixer-test_event_spurious_LCALTA_19 pass
2882 20:15:04.218236 alsa_mixer-test_get_value_LCALTA_18 pass
2883 20:15:04.223274 alsa_mixer-test_name_LCALTA_18 pass
2884 20:15:04.228837 alsa_mixer-test_write_default_LCALTA_18 pass
2885 20:15:04.229324 alsa_mixer-test_write_valid_LCALTA_18 pass
2886 20:15:04.234422 alsa_mixer-test_write_invalid_LCALTA_18 pass
2887 20:15:04.239946 alsa_mixer-test_event_missing_LCALTA_18 pass
2888 20:15:04.240461 alsa_mixer-test_event_spurious_LCALTA_18 pass
2889 20:15:04.245555 alsa_mixer-test_get_value_LCALTA_17 pass
2890 20:15:04.251070 alsa_mixer-test_name_LCALTA_17 pass
2891 20:15:04.251587 alsa_mixer-test_write_default_LCALTA_17 pass
2892 20:15:04.256589 alsa_mixer-test_write_valid_LCALTA_17 pass
2893 20:15:04.262113 alsa_mixer-test_write_invalid_LCALTA_17 pass
2894 20:15:04.267664 alsa_mixer-test_event_missing_LCALTA_17 pass
2895 20:15:04.268181 alsa_mixer-test_event_spurious_LCALTA_17 pass
2896 20:15:04.273229 alsa_mixer-test_get_value_LCALTA_16 pass
2897 20:15:04.273711 alsa_mixer-test_name_LCALTA_16 pass
2898 20:15:04.278743 alsa_mixer-test_write_default_LCALTA_16 pass
2899 20:15:04.284291 alsa_mixer-test_write_valid_LCALTA_16 pass
2900 20:15:04.289834 alsa_mixer-test_write_invalid_LCALTA_16 pass
2901 20:15:04.290321 alsa_mixer-test_event_missing_LCALTA_16 pass
2902 20:15:04.295395 alsa_mixer-test_event_spurious_LCALTA_16 pass
2903 20:15:04.300973 alsa_mixer-test_get_value_LCALTA_15 pass
2904 20:15:04.301473 alsa_mixer-test_name_LCALTA_15 pass
2905 20:15:04.306532 alsa_mixer-test_write_default_LCALTA_15 pass
2906 20:15:04.312067 alsa_mixer-test_write_valid_LCALTA_15 pass
2907 20:15:04.312552 alsa_mixer-test_write_invalid_LCALTA_15 pass
2908 20:15:04.317599 alsa_mixer-test_event_missing_LCALTA_15 pass
2909 20:15:04.323133 alsa_mixer-test_event_spurious_LCALTA_15 pass
2910 20:15:04.328679 alsa_mixer-test_get_value_LCALTA_14 pass
2911 20:15:04.329159 alsa_mixer-test_name_LCALTA_14 pass
2912 20:15:04.334228 alsa_mixer-test_write_default_LCALTA_14 pass
2913 20:15:04.339789 alsa_mixer-test_write_valid_LCALTA_14 pass
2914 20:15:04.340305 alsa_mixer-test_write_invalid_LCALTA_14 pass
2915 20:15:04.345310 alsa_mixer-test_event_missing_LCALTA_14 pass
2916 20:15:04.350867 alsa_mixer-test_event_spurious_LCALTA_14 pass
2917 20:15:04.351346 alsa_mixer-test_get_value_LCALTA_13 pass
2918 20:15:04.356404 alsa_mixer-test_name_LCALTA_13 pass
2919 20:15:04.361953 alsa_mixer-test_write_default_LCALTA_13 pass
2920 20:15:04.362446 alsa_mixer-test_write_valid_LCALTA_13 pass
2921 20:15:04.367538 alsa_mixer-test_write_invalid_LCALTA_13 pass
2922 20:15:04.373057 alsa_mixer-test_event_missing_LCALTA_13 pass
2923 20:15:04.373565 alsa_mixer-test_event_spurious_LCALTA_13 pass
2924 20:15:04.378624 alsa_mixer-test_get_value_LCALTA_12 pass
2925 20:15:04.384222 alsa_mixer-test_name_LCALTA_12 pass
2926 20:15:04.384726 alsa_mixer-test_write_default_LCALTA_12 pass
2927 20:15:04.389677 alsa_mixer-test_write_valid_LCALTA_12 pass
2928 20:15:04.395231 alsa_mixer-test_write_invalid_LCALTA_12 pass
2929 20:15:04.400796 alsa_mixer-test_event_missing_LCALTA_12 pass
2930 20:15:04.401285 alsa_mixer-test_event_spurious_LCALTA_12 pass
2931 20:15:04.406339 alsa_mixer-test_get_value_LCALTA_11 pass
2932 20:15:04.411900 alsa_mixer-test_name_LCALTA_11 pass
2933 20:15:04.412449 alsa_mixer-test_write_default_LCALTA_11 pass
2934 20:15:04.417432 alsa_mixer-test_write_valid_LCALTA_11 pass
2935 20:15:04.422974 alsa_mixer-test_write_invalid_LCALTA_11 pass
2936 20:15:04.423460 alsa_mixer-test_event_missing_LCALTA_11 pass
2937 20:15:04.428547 alsa_mixer-test_event_spurious_LCALTA_11 pass
2938 20:15:04.434045 alsa_mixer-test_get_value_LCALTA_10 pass
2939 20:15:04.434527 alsa_mixer-test_name_LCALTA_10 pass
2940 20:15:04.439614 alsa_mixer-test_write_default_LCALTA_10 pass
2941 20:15:04.445185 alsa_mixer-test_write_valid_LCALTA_10 pass
2942 20:15:04.445697 alsa_mixer-test_write_invalid_LCALTA_10 pass
2943 20:15:04.450725 alsa_mixer-test_event_missing_LCALTA_10 pass
2944 20:15:04.456283 alsa_mixer-test_event_spurious_LCALTA_10 pass
2945 20:15:04.461779 alsa_mixer-test_get_value_LCALTA_9 pass
2946 20:15:04.462255 alsa_mixer-test_name_LCALTA_9 pass
2947 20:15:04.467346 alsa_mixer-test_write_default_LCALTA_9 pass
2948 20:15:04.472906 alsa_mixer-test_write_valid_LCALTA_9 pass
2949 20:15:04.473390 alsa_mixer-test_write_invalid_LCALTA_9 pass
2950 20:15:04.478441 alsa_mixer-test_event_missing_LCALTA_9 pass
2951 20:15:04.484014 alsa_mixer-test_event_spurious_LCALTA_9 pass
2952 20:15:04.484502 alsa_mixer-test_get_value_LCALTA_8 pass
2953 20:15:04.489548 alsa_mixer-test_name_LCALTA_8 pass
2954 20:15:04.495088 alsa_mixer-test_write_default_LCALTA_8 pass
2955 20:15:04.495575 alsa_mixer-test_write_valid_LCALTA_8 pass
2956 20:15:04.500636 alsa_mixer-test_write_invalid_LCALTA_8 pass
2957 20:15:04.506191 alsa_mixer-test_event_missing_LCALTA_8 pass
2958 20:15:04.506682 alsa_mixer-test_event_spurious_LCALTA_8 pass
2959 20:15:04.511729 alsa_mixer-test_get_value_LCALTA_7 pass
2960 20:15:04.517265 alsa_mixer-test_name_LCALTA_7 pass
2961 20:15:04.517749 alsa_mixer-test_write_default_LCALTA_7 pass
2962 20:15:04.522830 alsa_mixer-test_write_valid_LCALTA_7 pass
2963 20:15:04.528380 alsa_mixer-test_write_invalid_LCALTA_7 pass
2964 20:15:04.528875 alsa_mixer-test_event_missing_LCALTA_7 pass
2965 20:15:04.533953 alsa_mixer-test_event_spurious_LCALTA_7 pass
2966 20:15:04.539478 alsa_mixer-test_get_value_LCALTA_6 pass
2967 20:15:04.539973 alsa_mixer-test_name_LCALTA_6 pass
2968 20:15:04.545002 alsa_mixer-test_write_default_LCALTA_6 pass
2969 20:15:04.550591 alsa_mixer-test_write_valid_LCALTA_6 pass
2970 20:15:04.551086 alsa_mixer-test_write_invalid_LCALTA_6 pass
2971 20:15:04.556116 alsa_mixer-test_event_missing_LCALTA_6 pass
2972 20:15:04.561658 alsa_mixer-test_event_spurious_LCALTA_6 pass
2973 20:15:04.562148 alsa_mixer-test_get_value_LCALTA_5 pass
2974 20:15:04.567200 alsa_mixer-test_name_LCALTA_5 pass
2975 20:15:04.572770 alsa_mixer-test_write_default_LCALTA_5 pass
2976 20:15:04.573281 alsa_mixer-test_write_valid_LCALTA_5 pass
2977 20:15:04.578319 alsa_mixer-test_write_invalid_LCALTA_5 pass
2978 20:15:04.583855 alsa_mixer-test_event_missing_LCALTA_5 pass
2979 20:15:04.584392 alsa_mixer-test_event_spurious_LCALTA_5 pass
2980 20:15:04.589382 alsa_mixer-test_get_value_LCALTA_4 pass
2981 20:15:04.594935 alsa_mixer-test_name_LCALTA_4 pass
2982 20:15:04.595416 alsa_mixer-test_write_default_LCALTA_4 pass
2983 20:15:04.600486 alsa_mixer-test_write_valid_LCALTA_4 pass
2984 20:15:04.606026 alsa_mixer-test_write_invalid_LCALTA_4 pass
2985 20:15:04.606519 alsa_mixer-test_event_missing_LCALTA_4 pass
2986 20:15:04.611593 alsa_mixer-test_event_spurious_LCALTA_4 pass
2987 20:15:04.617126 alsa_mixer-test_get_value_LCALTA_3 pass
2988 20:15:04.617613 alsa_mixer-test_name_LCALTA_3 pass
2989 20:15:04.622702 alsa_mixer-test_write_default_LCALTA_3 pass
2990 20:15:04.628266 alsa_mixer-test_write_valid_LCALTA_3 pass
2991 20:15:04.628764 alsa_mixer-test_write_invalid_LCALTA_3 pass
2992 20:15:04.633765 alsa_mixer-test_event_missing_LCALTA_3 pass
2993 20:15:04.639289 alsa_mixer-test_event_spurious_LCALTA_3 pass
2994 20:15:04.639776 alsa_mixer-test_get_value_LCALTA_2 pass
2995 20:15:04.644846 alsa_mixer-test_name_LCALTA_2 pass
2996 20:15:04.650391 alsa_mixer-test_write_default_LCALTA_2 pass
2997 20:15:04.650872 alsa_mixer-test_write_valid_LCALTA_2 pass
2998 20:15:04.655967 alsa_mixer-test_write_invalid_LCALTA_2 pass
2999 20:15:04.661503 alsa_mixer-test_event_missing_LCALTA_2 pass
3000 20:15:04.667053 alsa_mixer-test_event_spurious_LCALTA_2 pass
3001 20:15:04.667553 alsa_mixer-test_get_value_LCALTA_1 pass
3002 20:15:04.672589 alsa_mixer-test_name_LCALTA_1 pass
3003 20:15:04.673073 alsa_mixer-test_write_default_LCALTA_1 pass
3004 20:15:04.678128 alsa_mixer-test_write_valid_LCALTA_1 pass
3005 20:15:04.683661 alsa_mixer-test_write_invalid_LCALTA_1 pass
3006 20:15:04.689206 alsa_mixer-test_event_missing_LCALTA_1 pass
3007 20:15:04.689685 alsa_mixer-test_event_spurious_LCALTA_1 pass
3008 20:15:04.694767 alsa_mixer-test_get_value_LCALTA_0 pass
3009 20:15:04.695238 alsa_mixer-test_name_LCALTA_0 pass
3010 20:15:04.700308 alsa_mixer-test_write_default_LCALTA_0 pass
3011 20:15:04.705830 alsa_mixer-test_write_valid_LCALTA_0 pass
3012 20:15:04.711388 alsa_mixer-test_write_invalid_LCALTA_0 pass
3013 20:15:04.711861 alsa_mixer-test_event_missing_LCALTA_0 pass
3014 20:15:04.716932 alsa_mixer-test_event_spurious_LCALTA_0 pass
3015 20:15:04.717407 alsa_mixer-test pass
3016 20:15:04.722481 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
3017 20:15:04.728036 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
3018 20:15:04.733595 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
3019 20:15:04.739141 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
3020 20:15:04.739623 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
3021 20:15:04.744682 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
3022 20:15:04.750229 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
3023 20:15:04.755790 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
3024 20:15:04.761333 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
3025 20:15:04.766863 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
3026 20:15:04.767359 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
3027 20:15:04.772424 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
3028 20:15:04.777969 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
3029 20:15:04.783512 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
3030 20:15:04.789060 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
3031 20:15:04.794605 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
3032 20:15:04.795109 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
3033 20:15:04.800212 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
3034 20:15:04.805731 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
3035 20:15:04.811241 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
3036 20:15:04.816780 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
3037 20:15:04.822335 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
3038 20:15:04.822813 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
3039 20:15:04.827887 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
3040 20:15:04.833434 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
3041 20:15:04.838961 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
3042 20:15:04.844530 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
3043 20:15:04.850068 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
3044 20:15:04.850547 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
3045 20:15:04.855598 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
3046 20:15:04.861156 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
3047 20:15:04.866711 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
3048 20:15:04.872267 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
3049 20:15:04.877799 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
3050 20:15:04.883340 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
3051 20:15:04.883812 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
3052 20:15:04.888893 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
3053 20:15:04.894447 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
3054 20:15:04.900004 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
3055 20:15:04.905636 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
3056 20:15:04.911091 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
3057 20:15:04.911576 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
3058 20:15:04.916676 alsa_pcm-test pass
3059 20:15:04.922174 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3060 20:15:04.933215 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3061 20:15:04.938824 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3062 20:15:04.949856 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3063 20:15:04.955468 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3064 20:15:04.961144 alsa_test-pcmtest-driver pass
3065 20:15:04.966632 alsa_utimer-test_global_wrong_timers_test pass
3066 20:15:04.967118 alsa_utimer-test_timer_f_utimer fail
3067 20:15:04.972125 alsa_utimer-test fail
3068 20:15:04.972627 + ../../utils/send-to-lava.sh ./output/result.txt
3069 20:15:04.977630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
3070 20:15:04.978580 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
3072 20:15:04.988704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
3073 20:15:04.989450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
3075 20:15:04.994470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
3076 20:15:04.995169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
3078 20:15:05.025539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
3079 20:15:05.026382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
3081 20:15:05.072657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
3082 20:15:05.073473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
3084 20:15:05.134663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
3085 20:15:05.135450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
3087 20:15:05.185018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
3088 20:15:05.185751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
3090 20:15:05.233063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
3091 20:15:05.233794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
3093 20:15:05.285609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
3094 20:15:05.286375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
3096 20:15:05.336231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
3097 20:15:05.337025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
3099 20:15:05.380910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
3100 20:15:05.381659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
3102 20:15:05.430403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
3103 20:15:05.431253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
3105 20:15:05.477719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
3106 20:15:05.478488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
3108 20:15:05.526679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
3109 20:15:05.527491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
3111 20:15:05.580785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
3112 20:15:05.581556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
3114 20:15:05.629118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
3115 20:15:05.629873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
3117 20:15:05.681707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
3118 20:15:05.682475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
3120 20:15:05.733974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
3121 20:15:05.734745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
3123 20:15:05.784898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
3124 20:15:05.785657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
3126 20:15:05.838287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
3127 20:15:05.839049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
3129 20:15:05.889175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
3130 20:15:05.889928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
3132 20:15:05.945084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
3133 20:15:05.945869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
3135 20:15:05.999057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
3136 20:15:05.999819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
3138 20:15:06.050325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
3139 20:15:06.051170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
3141 20:15:06.110824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
3142 20:15:06.111657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
3144 20:15:06.163319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3145 20:15:06.164145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3147 20:15:06.211040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3148 20:15:06.211873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3150 20:15:06.253837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3151 20:15:06.254623 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3153 20:15:06.302629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3154 20:15:06.303588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3156 20:15:06.354282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3157 20:15:06.355141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3159 20:15:06.396558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3160 20:15:06.397413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3162 20:15:06.448486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3163 20:15:06.449388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3165 20:15:06.505961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3166 20:15:06.506809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3168 20:15:06.556038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3169 20:15:06.556943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3171 20:15:06.605729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3172 20:15:06.606628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3174 20:15:06.657140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3175 20:15:06.658010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3177 20:15:06.702015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3178 20:15:06.702820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3180 20:15:06.753328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3181 20:15:06.754159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3183 20:15:06.804052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3184 20:15:06.804851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3186 20:15:06.848061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3187 20:15:06.848847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3189 20:15:06.897078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3190 20:15:06.897874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3192 20:15:06.952535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3193 20:15:06.953383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3195 20:15:07.007084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3196 20:15:07.007774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3198 20:15:07.063532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3199 20:15:07.064922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3201 20:15:07.111817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3202 20:15:07.113360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3204 20:15:07.166194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3205 20:15:07.167060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3207 20:15:07.222533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3208 20:15:07.223335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3210 20:15:07.271760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3211 20:15:07.272663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3213 20:15:07.322547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3214 20:15:07.323426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3216 20:15:07.378872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3217 20:15:07.379737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3219 20:15:07.441751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3220 20:15:07.442668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3222 20:15:07.491169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3223 20:15:07.492072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3225 20:15:07.538582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3226 20:15:07.539715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3228 20:15:07.595757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3229 20:15:07.596717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3231 20:15:07.645797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3232 20:15:07.646976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3234 20:15:07.696642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3235 20:15:07.697501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3237 20:15:07.740574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3238 20:15:07.741426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3240 20:15:07.785542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3241 20:15:07.786498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3243 20:15:07.830917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3244 20:15:07.831733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3246 20:15:07.876666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3247 20:15:07.877538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3249 20:15:07.936879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3250 20:15:07.937784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3252 20:15:07.988748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3253 20:15:07.989582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3255 20:15:08.040050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3256 20:15:08.040889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3258 20:15:08.092085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3259 20:15:08.092888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3261 20:15:08.135613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3262 20:15:08.136479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3264 20:15:08.182414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3265 20:15:08.183316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3267 20:15:08.233978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3268 20:15:08.234842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3270 20:15:08.287932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3271 20:15:08.288832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3273 20:15:08.340802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3274 20:15:08.341675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3276 20:15:08.392493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3277 20:15:08.393520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3279 20:15:08.447127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3280 20:15:08.448032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3282 20:15:08.493521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3283 20:15:08.494387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3285 20:15:08.544041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3286 20:15:08.544895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3288 20:15:08.589751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3289 20:15:08.590595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3291 20:15:08.639157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3292 20:15:08.640046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3294 20:15:08.699309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3295 20:15:08.700148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3297 20:15:08.756341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3298 20:15:08.757179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3300 20:15:08.808590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3301 20:15:08.809426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3303 20:15:08.860342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3304 20:15:08.861214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3306 20:15:08.904755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3307 20:15:08.905376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3309 20:15:08.954551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3310 20:15:08.955401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3312 20:15:09.007064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3313 20:15:09.007892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3315 20:15:09.052879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3316 20:15:09.053750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3318 20:15:09.171839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3319 20:15:09.172639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3321 20:15:09.232697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3322 20:15:09.233299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3324 20:15:09.282300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3325 20:15:09.283150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3327 20:15:09.325862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3328 20:15:09.326788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3330 20:15:09.381181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3331 20:15:09.381906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3333 20:15:09.429356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3334 20:15:09.429971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3336 20:15:09.481353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3337 20:15:09.481936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3339 20:15:09.525619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3340 20:15:09.526252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3342 20:15:09.576691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3343 20:15:09.577293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3345 20:15:09.624782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3346 20:15:09.625419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3348 20:15:09.676699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3349 20:15:09.677280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3351 20:15:09.729656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3352 20:15:09.730262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3354 20:15:09.778856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3355 20:15:09.779509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3357 20:15:09.829700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3358 20:15:09.830324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3360 20:15:09.883786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3361 20:15:09.884421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3363 20:15:09.937002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3364 20:15:09.937632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3366 20:15:09.988482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3367 20:15:09.989104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3369 20:15:10.041122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3370 20:15:10.041750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3372 20:15:10.093776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3373 20:15:10.094397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3375 20:15:10.145693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3376 20:15:10.146286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3378 20:15:10.202573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3379 20:15:10.203256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3381 20:15:10.255623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3382 20:15:10.256237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3384 20:15:10.301742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3385 20:15:10.302370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3387 20:15:10.356449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3388 20:15:10.357087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3390 20:15:10.405755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3391 20:15:10.406356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3393 20:15:10.466906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3394 20:15:10.467536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3396 20:15:10.516714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3397 20:15:10.517296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3399 20:15:10.573001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3400 20:15:10.573667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3402 20:15:10.628354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3403 20:15:10.629251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3405 20:15:10.684238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3406 20:15:10.685303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3408 20:15:10.744684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3409 20:15:10.745787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3411 20:15:10.789466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3412 20:15:10.790388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3414 20:15:10.836810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3415 20:15:10.837719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3417 20:15:10.886312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3418 20:15:10.887404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3420 20:15:10.948859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3421 20:15:10.949705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3423 20:15:10.997837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3424 20:15:10.998855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3426 20:15:11.049640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3427 20:15:11.050526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3429 20:15:11.109997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3430 20:15:11.110830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3432 20:15:11.159873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3433 20:15:11.160805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3435 20:15:11.205511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3436 20:15:11.206357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3438 20:15:11.259351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3439 20:15:11.260205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3441 20:15:11.319237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3442 20:15:11.320428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3444 20:15:11.388176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3445 20:15:11.389125 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3447 20:15:11.450179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3448 20:15:11.451388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3450 20:15:11.503342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3451 20:15:11.504208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3453 20:15:11.553937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3454 20:15:11.554816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3456 20:15:11.611274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3457 20:15:11.612090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3459 20:15:11.666976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3460 20:15:11.667809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3462 20:15:11.722399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3463 20:15:11.723217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3465 20:15:11.775753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3466 20:15:11.776362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3468 20:15:11.825917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3469 20:15:11.826830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3471 20:15:11.877048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3472 20:15:11.877864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3474 20:15:11.934155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3475 20:15:11.935039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3477 20:15:11.993513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3478 20:15:11.994397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3480 20:15:12.041201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3481 20:15:12.042027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3483 20:15:12.101434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3484 20:15:12.102315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3486 20:15:12.151645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3487 20:15:12.152494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3489 20:15:12.199019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3490 20:15:12.199840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3492 20:15:12.256661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3493 20:15:12.257484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3495 20:15:12.299841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3496 20:15:12.300715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3498 20:15:12.352868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3499 20:15:12.353677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3501 20:15:12.402615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3502 20:15:12.403434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3504 20:15:12.458004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3505 20:15:12.458804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3507 20:15:12.514324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3508 20:15:12.515150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3510 20:15:12.579025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3511 20:15:12.579896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3513 20:15:12.642676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3514 20:15:12.643554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3516 20:15:12.687092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3517 20:15:12.687915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3519 20:15:12.739418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3520 20:15:12.740218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3522 20:15:12.783630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3523 20:15:12.784502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3525 20:15:12.835649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3526 20:15:12.836490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3528 20:15:12.884859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3529 20:15:12.885650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3531 20:15:12.937057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3532 20:15:12.937906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3534 20:15:12.988054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3535 20:15:12.988871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3537 20:15:13.035752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3538 20:15:13.036594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3540 20:15:13.085091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3541 20:15:13.085897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3543 20:15:13.136560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3544 20:15:13.137436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3546 20:15:13.186396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3547 20:15:13.187200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3549 20:15:13.240746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3550 20:15:13.241579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3552 20:15:13.293153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3553 20:15:13.293962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3555 20:15:13.346230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3556 20:15:13.346970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3558 20:15:13.406107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3559 20:15:13.406863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3561 20:15:13.457632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3562 20:15:13.458388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3564 20:15:13.509607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3565 20:15:13.510414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3567 20:15:13.564854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3568 20:15:13.565633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3570 20:15:13.615043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3571 20:15:13.615789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3573 20:15:13.664963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3574 20:15:13.665721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3576 20:15:13.722212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3577 20:15:13.723001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3579 20:15:13.771529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3580 20:15:13.772318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3582 20:15:13.822597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3583 20:15:13.823393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3585 20:15:13.873257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3586 20:15:13.874013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3588 20:15:13.926012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3589 20:15:13.926785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3591 20:15:13.973703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3592 20:15:13.974469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3594 20:15:14.030713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3595 20:15:14.031692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3597 20:15:14.084394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3598 20:15:14.085264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3600 20:15:14.134012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3601 20:15:14.134864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3603 20:15:14.184397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3604 20:15:14.185209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3606 20:15:14.234044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3607 20:15:14.234990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3609 20:15:14.289316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3610 20:15:14.290139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3612 20:15:14.339108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3613 20:15:14.339912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3615 20:15:14.400057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3616 20:15:14.400842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3618 20:15:14.452487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3619 20:15:14.453301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3621 20:15:14.504189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3622 20:15:14.505007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3624 20:15:14.562581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3625 20:15:14.563664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3627 20:15:14.614363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3628 20:15:14.615307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3630 20:15:14.670951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3631 20:15:14.671852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3633 20:15:14.723449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3634 20:15:14.724588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3636 20:15:14.785046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3637 20:15:14.785931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3639 20:15:14.828768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3640 20:15:14.829699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3642 20:15:14.877996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3643 20:15:14.878929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3645 20:15:14.925034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3646 20:15:14.925963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3648 20:15:14.981739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3649 20:15:14.982578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3651 20:15:15.034693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3652 20:15:15.035543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3654 20:15:15.080540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3655 20:15:15.081397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3657 20:15:15.130154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3658 20:15:15.130986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3660 20:15:15.179150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3661 20:15:15.179927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3663 20:15:15.223892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3664 20:15:15.224722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3666 20:15:15.275904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3667 20:15:15.276727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3669 20:15:15.331232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3670 20:15:15.332091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3672 20:15:15.375232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3673 20:15:15.376080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3675 20:15:15.429382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3676 20:15:15.430260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3678 20:15:15.477611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3679 20:15:15.478446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3681 20:15:15.529427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3682 20:15:15.530240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3684 20:15:15.581153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3685 20:15:15.581816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3687 20:15:15.640396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3688 20:15:15.641419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3690 20:15:15.688150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3691 20:15:15.689059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3693 20:15:15.742642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3694 20:15:15.743562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3696 20:15:15.792728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3697 20:15:15.793380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3699 20:15:15.846033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3700 20:15:15.846978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3702 20:15:15.901202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3703 20:15:15.902102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3705 20:15:15.948955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3706 20:15:15.950069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3708 20:15:16.005835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3709 20:15:16.006736 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3711 20:15:16.056331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3712 20:15:16.057255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3714 20:15:16.105131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3715 20:15:16.106020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3717 20:15:16.153847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3718 20:15:16.154796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3720 20:15:16.211651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3721 20:15:16.212607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3723 20:15:16.260671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3724 20:15:16.261553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3726 20:15:16.303762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3727 20:15:16.304816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3729 20:15:16.362463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3730 20:15:16.363436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3732 20:15:16.415956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3733 20:15:16.416927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3735 20:15:16.468368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3736 20:15:16.469304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3738 20:15:16.524314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3739 20:15:16.525348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3741 20:15:16.577091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3742 20:15:16.577741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3744 20:15:16.625975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3745 20:15:16.626622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3747 20:15:16.684283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3748 20:15:16.684939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3750 20:15:16.743522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3751 20:15:16.744141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3753 20:15:16.793234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3754 20:15:16.794134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3756 20:15:16.846576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3757 20:15:16.847442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3759 20:15:16.892921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3760 20:15:16.893756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3762 20:15:16.940215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3763 20:15:16.941076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3765 20:15:16.995791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3766 20:15:16.996631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3768 20:15:17.044198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3769 20:15:17.045103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3771 20:15:17.094373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3772 20:15:17.095188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3774 20:15:17.148120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3775 20:15:17.148997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3777 20:15:17.199239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3778 20:15:17.200084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3780 20:15:17.250239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3781 20:15:17.251094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3783 20:15:17.296901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3784 20:15:17.297737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3786 20:15:17.344082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3787 20:15:17.344928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3789 20:15:17.396572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3790 20:15:17.397377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3792 20:15:17.450731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3793 20:15:17.451621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3795 20:15:17.502672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3796 20:15:17.503467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3798 20:15:17.557163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3799 20:15:17.558040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3801 20:15:17.603474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3802 20:15:17.604304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3804 20:15:17.646210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3805 20:15:17.647059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3807 20:15:17.695377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3808 20:15:17.696165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3810 20:15:17.747197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3811 20:15:17.748093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3813 20:15:17.793792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3814 20:15:17.794616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3816 20:15:17.842794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3817 20:15:17.843587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3819 20:15:17.893792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3820 20:15:17.894674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3822 20:15:17.942924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3823 20:15:17.943730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3825 20:15:17.995819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3826 20:15:17.996739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3828 20:15:18.044634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3829 20:15:18.045538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3831 20:15:18.095207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3832 20:15:18.096096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3834 20:15:18.155439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3835 20:15:18.156332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3837 20:15:18.207965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3838 20:15:18.208822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3840 20:15:18.261200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3841 20:15:18.262068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3843 20:15:18.319670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3844 20:15:18.320509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3846 20:15:18.369294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3847 20:15:18.370170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3849 20:15:18.419841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3850 20:15:18.420761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3852 20:15:18.481328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3853 20:15:18.482420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3855 20:15:18.530774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3856 20:15:18.531747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3858 20:15:18.579089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3859 20:15:18.581361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3861 20:15:18.631232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3862 20:15:18.632108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3864 20:15:18.680819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3865 20:15:18.681710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3867 20:15:18.736440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3868 20:15:18.737538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3870 20:15:18.779977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3871 20:15:18.780880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3873 20:15:18.825374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3874 20:15:18.826296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3876 20:15:18.879893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3877 20:15:18.880864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3879 20:15:18.935216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3880 20:15:18.936116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3882 20:15:18.983877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3883 20:15:18.984716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3885 20:15:19.037656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3886 20:15:19.038307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3888 20:15:19.090390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3889 20:15:19.091241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3891 20:15:19.135517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3892 20:15:19.136151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3894 20:15:19.189000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3895 20:15:19.189645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3897 20:15:19.240394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3898 20:15:19.241057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3900 20:15:19.293046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3901 20:15:19.293894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3903 20:15:19.346201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3904 20:15:19.347186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3906 20:15:19.398496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3907 20:15:19.399185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3909 20:15:19.452465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3910 20:15:19.453820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3912 20:15:19.499299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3913 20:15:19.499957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3915 20:15:19.551558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3916 20:15:19.552245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3918 20:15:19.606343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3919 20:15:19.606976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3921 20:15:19.652298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3922 20:15:19.653142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3924 20:15:19.701776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3925 20:15:19.702641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3927 20:15:19.751233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3928 20:15:19.752106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3930 20:15:19.802924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3931 20:15:19.803741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3933 20:15:19.850367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3934 20:15:19.851222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3936 20:15:19.902951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3937 20:15:19.903797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3939 20:15:19.953361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3940 20:15:19.954187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3942 20:15:20.006008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3943 20:15:20.006864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3945 20:15:20.058152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3946 20:15:20.059010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3948 20:15:20.108816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3949 20:15:20.109689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3951 20:15:20.164971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3952 20:15:20.165816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3954 20:15:20.221899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3955 20:15:20.222697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3957 20:15:20.270659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3958 20:15:20.271479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3960 20:15:20.330618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3961 20:15:20.331447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3963 20:15:20.375524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3964 20:15:20.376417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3966 20:15:20.433121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3967 20:15:20.434008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3969 20:15:20.488226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3970 20:15:20.489141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3972 20:15:20.532548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3973 20:15:20.533400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3975 20:15:20.589308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3976 20:15:20.590112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3978 20:15:20.652081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3979 20:15:20.652906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3981 20:15:20.702191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3982 20:15:20.703034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3984 20:15:20.757772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3985 20:15:20.758672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3987 20:15:20.819382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3988 20:15:20.820295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3990 20:15:20.873124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3991 20:15:20.873959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3993 20:15:20.928531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3994 20:15:20.929356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3996 20:15:20.979359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3997 20:15:20.980177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3999 20:15:21.032579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
4000 20:15:21.033447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
4002 20:15:21.086317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
4003 20:15:21.087196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
4005 20:15:21.142680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
4006 20:15:21.143589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
4008 20:15:21.190134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
4009 20:15:21.190987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
4011 20:15:21.244444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
4012 20:15:21.245244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
4014 20:15:21.291117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
4015 20:15:21.291891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
4017 20:15:21.342828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
4018 20:15:21.343739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
4020 20:15:21.394067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
4021 20:15:21.394957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
4023 20:15:21.442429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
4024 20:15:21.443331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
4026 20:15:21.490222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
4027 20:15:21.491139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
4029 20:15:21.545953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
4030 20:15:21.546812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
4032 20:15:21.591948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
4033 20:15:21.592824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
4035 20:15:21.647840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
4036 20:15:21.648732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
4038 20:15:21.699356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
4039 20:15:21.700159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
4041 20:15:21.747377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
4042 20:15:21.748155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
4044 20:15:21.800849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
4045 20:15:21.801671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
4047 20:15:21.855612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
4048 20:15:21.856536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
4050 20:15:21.907246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
4051 20:15:21.908274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
4053 20:15:21.954964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
4054 20:15:21.955817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
4056 20:15:22.004485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
4057 20:15:22.005409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
4059 20:15:22.055032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
4060 20:15:22.056042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
4062 20:15:22.098537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
4063 20:15:22.099359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
4065 20:15:22.148608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
4066 20:15:22.149463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
4068 20:15:22.209659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
4069 20:15:22.210474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
4071 20:15:22.259411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
4072 20:15:22.260298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
4074 20:15:22.305490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
4075 20:15:22.306285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
4077 20:15:22.350926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
4078 20:15:22.351684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
4080 20:15:22.397165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
4081 20:15:22.398148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
4083 20:15:22.446272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
4084 20:15:22.446929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
4086 20:15:22.492938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
4087 20:15:22.493882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
4089 20:15:22.542894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
4090 20:15:22.543922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
4092 20:15:22.592422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
4093 20:15:22.593025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
4095 20:15:22.637961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
4096 20:15:22.638887 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
4098 20:15:22.693389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
4099 20:15:22.694078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
4101 20:15:22.753441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
4102 20:15:22.754305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
4104 20:15:22.797641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
4105 20:15:22.798456 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
4107 20:15:22.851589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
4108 20:15:22.852459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
4110 20:15:22.904447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
4111 20:15:22.905269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
4113 20:15:22.957789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
4114 20:15:22.958687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
4116 20:15:23.012554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
4117 20:15:23.013393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
4119 20:15:23.057914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
4120 20:15:23.058759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
4122 20:15:23.108260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
4123 20:15:23.109087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
4125 20:15:23.165147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
4126 20:15:23.166142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
4128 20:15:23.214522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
4129 20:15:23.215405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
4131 20:15:23.261673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
4132 20:15:23.262282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
4134 20:15:23.308800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
4135 20:15:23.309662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
4137 20:15:23.363154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
4138 20:15:23.364113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
4140 20:15:23.415087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
4141 20:15:23.416045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
4143 20:15:23.476163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
4144 20:15:23.477127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4146 20:15:23.530378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4147 20:15:23.531258 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4149 20:15:23.589584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4150 20:15:23.590492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4152 20:15:23.633951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4153 20:15:23.634567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4155 20:15:23.687906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4156 20:15:23.688599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4158 20:15:23.738253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4159 20:15:23.739251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4161 20:15:23.788800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4162 20:15:23.789672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4164 20:15:23.832674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4165 20:15:23.833553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4167 20:15:23.885439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4168 20:15:23.886327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4170 20:15:23.933162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4171 20:15:23.934036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4173 20:15:23.983040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4174 20:15:23.983867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4176 20:15:24.031749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4177 20:15:24.032619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4179 20:15:24.080477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4180 20:15:24.081260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4182 20:15:24.123832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4183 20:15:24.124533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4185 20:15:24.167720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4186 20:15:24.168401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4188 20:15:24.219598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4189 20:15:24.220245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4191 20:15:24.274280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4192 20:15:24.274922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4194 20:15:24.324936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4195 20:15:24.325573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4197 20:15:24.375480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4198 20:15:24.376113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4200 20:15:24.431318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4201 20:15:24.431928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4203 20:15:24.481190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4204 20:15:24.482068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4206 20:15:24.533689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4207 20:15:24.534527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4209 20:15:24.578353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4210 20:15:24.579139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4212 20:15:24.628760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4213 20:15:24.629549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4215 20:15:24.677770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4216 20:15:24.678551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4218 20:15:24.724680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4219 20:15:24.725341 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4221 20:15:24.776620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4222 20:15:24.777235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4224 20:15:24.833393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4225 20:15:24.834103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4227 20:15:24.886452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4228 20:15:24.887106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4230 20:15:24.938228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4231 20:15:24.938853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4233 20:15:24.991380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4234 20:15:24.992052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4236 20:15:25.045575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4237 20:15:25.046242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4239 20:15:25.094513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4240 20:15:25.095182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4242 20:15:25.149269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4243 20:15:25.149909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4245 20:15:25.205785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4246 20:15:25.206624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4248 20:15:25.264049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4249 20:15:25.264820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4251 20:15:25.327051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4252 20:15:25.327823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4254 20:15:25.380251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4255 20:15:25.381030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4257 20:15:25.434959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4258 20:15:25.435719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4260 20:15:25.493741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4261 20:15:25.494502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4263 20:15:25.547956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4264 20:15:25.548776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4266 20:15:25.600910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4267 20:15:25.601698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4269 20:15:25.651209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4270 20:15:25.651965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4272 20:15:25.705040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4273 20:15:25.705865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4275 20:15:25.752240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4276 20:15:25.753020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4278 20:15:25.808099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4279 20:15:25.808874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4281 20:15:25.861922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4282 20:15:25.862670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4284 20:15:25.909775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4285 20:15:25.910536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4287 20:15:25.966830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4288 20:15:25.967642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4290 20:15:26.030330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4291 20:15:26.031097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4293 20:15:26.082942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4294 20:15:26.083709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4296 20:15:26.136656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4297 20:15:26.137416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4299 20:15:26.186266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4300 20:15:26.187028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4302 20:15:26.238249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4303 20:15:26.238991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4305 20:15:26.289387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4306 20:15:26.290163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4308 20:15:26.339705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4309 20:15:26.340541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4311 20:15:26.393709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4312 20:15:26.394500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4314 20:15:26.443367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4315 20:15:26.444132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4317 20:15:26.501590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4318 20:15:26.502376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4320 20:15:26.549027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4321 20:15:26.549797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4323 20:15:26.597732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4324 20:15:26.598499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4326 20:15:26.649359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4327 20:15:26.650096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4329 20:15:26.704827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4330 20:15:26.705575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4332 20:15:26.751958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4333 20:15:26.752736 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4335 20:15:26.797964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4336 20:15:26.798705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4338 20:15:26.850300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4339 20:15:26.851028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4341 20:15:26.902824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4342 20:15:26.903653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4344 20:15:26.967649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4345 20:15:26.968576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4347 20:15:27.024846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4348 20:15:27.025678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4350 20:15:27.077517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4351 20:15:27.078310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4353 20:15:27.124830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4355 20:15:27.127791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4356 20:15:27.181127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4357 20:15:27.181892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4359 20:15:27.231863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4360 20:15:27.232686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4362 20:15:27.276113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4363 20:15:27.276911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4365 20:15:27.325316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4366 20:15:27.326117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4368 20:15:27.380303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4369 20:15:27.381270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4371 20:15:27.435867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4372 20:15:27.438838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4374 20:15:27.486384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4375 20:15:27.487257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4377 20:15:27.539663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4378 20:15:27.540601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4380 20:15:27.587154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4381 20:15:27.588339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4383 20:15:27.640572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4384 20:15:27.641965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4386 20:15:27.684625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4387 20:15:27.685290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4389 20:15:27.742259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4390 20:15:27.742907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4392 20:15:27.790911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4393 20:15:27.792202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4395 20:15:27.845662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4396 20:15:27.846521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4398 20:15:27.904763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4399 20:15:27.906092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4401 20:15:27.955151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4402 20:15:27.956043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4404 20:15:28.017552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4405 20:15:28.018538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4407 20:15:28.079431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4408 20:15:28.080420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4410 20:15:28.138642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4411 20:15:28.139527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4413 20:15:28.193894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4414 20:15:28.194790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4416 20:15:28.245010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4417 20:15:28.245681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4419 20:15:28.300161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4420 20:15:28.301102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4422 20:15:28.349030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4423 20:15:28.349934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4425 20:15:28.402970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4426 20:15:28.403846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4428 20:15:28.452843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4429 20:15:28.453731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4431 20:15:28.501578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4432 20:15:28.502707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4434 20:15:28.549389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4435 20:15:28.550617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4437 20:15:28.598181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4438 20:15:28.598858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4440 20:15:28.655415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4441 20:15:28.656410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4443 20:15:28.712764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4444 20:15:28.713690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4446 20:15:28.769795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4447 20:15:28.770687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4449 20:15:28.825700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4450 20:15:28.826698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4452 20:15:28.877906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4453 20:15:28.878840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4455 20:15:28.929269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4456 20:15:28.929968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4458 20:15:28.997813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4459 20:15:28.998471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4461 20:15:29.041377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4462 20:15:29.042260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4464 20:15:29.095623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4465 20:15:29.096799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4467 20:15:29.148697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4468 20:15:29.149732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4470 20:15:29.193726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4471 20:15:29.194657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4473 20:15:29.244844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4474 20:15:29.245854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4476 20:15:29.297593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4477 20:15:29.298542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4479 20:15:29.346805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4480 20:15:29.347728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4482 20:15:29.399394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4483 20:15:29.400348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4485 20:15:29.459044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4486 20:15:29.460021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4488 20:15:29.507336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4489 20:15:29.508311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4491 20:15:29.558783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4492 20:15:29.559717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4494 20:15:29.609729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4495 20:15:29.610635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4497 20:15:29.658374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4498 20:15:29.659282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4500 20:15:29.705989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4501 20:15:29.706906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4503 20:15:29.757784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4504 20:15:29.758787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4506 20:15:29.806926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4507 20:15:29.807856 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4509 20:15:29.851069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4511 20:15:29.856257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4512 20:15:29.856848 + set +x
4513 20:15:29.861832 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 954419_1.6.2.4.5>
4514 20:15:29.862460 <LAVA_TEST_RUNNER EXIT>
4515 20:15:29.863390 Received signal: <ENDRUN> 1_kselftest-alsa 954419_1.6.2.4.5
4516 20:15:29.864073 Ending use of test pattern.
4517 20:15:29.864644 Ending test lava.1_kselftest-alsa (954419_1.6.2.4.5), duration 41.50
4519 20:15:29.866604 ok: lava_test_shell seems to have completed
4520 20:15:29.895847 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4521 20:15:29.898049 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4522 20:15:29.898806 end: 3 lava-test-retry (duration 00:00:42) [common]
4523 20:15:29.899522 start: 4 finalize (timeout 00:05:57) [common]
4524 20:15:29.900311 start: 4.1 power-off (timeout 00:00:30) [common]
4525 20:15:29.901597 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4526 20:15:29.936693 >> OK - accepted request
4527 20:15:29.938814 Returned 0 in 0 seconds
4528 20:15:30.040348 end: 4.1 power-off (duration 00:00:00) [common]
4530 20:15:30.042554 start: 4.2 read-feedback (timeout 00:05:57) [common]
4531 20:15:30.043953 Listened to connection for namespace 'common' for up to 1s
4532 20:15:31.044650 Finalising connection for namespace 'common'
4533 20:15:31.045418 Disconnecting from shell: Finalise
4534 20:15:31.046008 / #
4535 20:15:31.147184 end: 4.2 read-feedback (duration 00:00:01) [common]
4536 20:15:31.148051 end: 4 finalize (duration 00:00:01) [common]
4537 20:15:31.148950 Cleaning after the job
4538 20:15:31.149658 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/ramdisk
4539 20:15:31.163879 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/kernel
4540 20:15:31.214610 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/dtb
4541 20:15:31.215502 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/nfsrootfs
4542 20:15:31.245547 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954419/tftp-deploy-ri2_i088/modules
4543 20:15:31.252424 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/954419
4544 20:15:35.522155 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/954419
4545 20:15:35.522746 Job finished correctly