Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 20:50:53.600664 lava-dispatcher, installed at version: 2024.01
2 20:50:53.601452 start: 0 validate
3 20:50:53.601953 Start time: 2024-11-07 20:50:53.601922+00:00 (UTC)
4 20:50:53.602511 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 20:50:53.603056 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 20:50:53.637328 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 20:50:53.637974 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 20:50:53.661972 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 20:50:53.662620 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 20:50:53.689093 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 20:50:53.689825 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 20:50:53.714575 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 20:50:53.715258 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 20:50:53.746358 validate duration: 0.14
16 20:50:53.747303 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:50:53.747641 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:50:53.747945 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:50:53.748531 Not decompressing ramdisk as can be used compressed.
20 20:50:53.748968 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 20:50:53.749255 saving as /var/lib/lava/dispatcher/tmp/955456/tftp-deploy-lfqq7hzz/ramdisk/initrd.cpio.gz
22 20:50:53.749528 total size: 4775763 (4 MB)
23 20:50:53.780987 progress 0 % (0 MB)
24 20:50:53.785688 progress 5 % (0 MB)
25 20:50:53.789896 progress 10 % (0 MB)
26 20:50:53.794041 progress 15 % (0 MB)
27 20:50:53.798699 progress 20 % (0 MB)
28 20:50:53.802792 progress 25 % (1 MB)
29 20:50:53.806851 progress 30 % (1 MB)
30 20:50:53.811485 progress 35 % (1 MB)
31 20:50:53.815660 progress 40 % (1 MB)
32 20:50:53.819957 progress 45 % (2 MB)
33 20:50:53.824085 progress 50 % (2 MB)
34 20:50:53.828558 progress 55 % (2 MB)
35 20:50:53.831920 progress 60 % (2 MB)
36 20:50:53.835198 progress 65 % (2 MB)
37 20:50:53.838901 progress 70 % (3 MB)
38 20:50:53.842342 progress 75 % (3 MB)
39 20:50:53.845664 progress 80 % (3 MB)
40 20:50:53.848873 progress 85 % (3 MB)
41 20:50:53.852536 progress 90 % (4 MB)
42 20:50:53.855945 progress 95 % (4 MB)
43 20:50:53.859534 progress 100 % (4 MB)
44 20:50:53.860261 4 MB downloaded in 0.11 s (41.14 MB/s)
45 20:50:53.860907 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:50:53.861940 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:50:53.862298 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:50:53.862646 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:50:53.863195 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 20:50:53.863501 saving as /var/lib/lava/dispatcher/tmp/955456/tftp-deploy-lfqq7hzz/kernel/zImage
52 20:50:53.863753 total size: 11440640 (10 MB)
53 20:50:53.864008 No compression specified
54 20:50:53.896594 progress 0 % (0 MB)
55 20:50:53.906393 progress 5 % (0 MB)
56 20:50:53.915580 progress 10 % (1 MB)
57 20:50:53.923486 progress 15 % (1 MB)
58 20:50:53.930787 progress 20 % (2 MB)
59 20:50:53.938847 progress 25 % (2 MB)
60 20:50:53.945901 progress 30 % (3 MB)
61 20:50:53.953243 progress 35 % (3 MB)
62 20:50:53.961063 progress 40 % (4 MB)
63 20:50:53.970411 progress 45 % (4 MB)
64 20:50:53.979263 progress 50 % (5 MB)
65 20:50:53.988693 progress 55 % (6 MB)
66 20:50:53.997504 progress 60 % (6 MB)
67 20:50:54.006284 progress 65 % (7 MB)
68 20:50:54.013671 progress 70 % (7 MB)
69 20:50:54.020694 progress 75 % (8 MB)
70 20:50:54.028129 progress 80 % (8 MB)
71 20:50:54.035289 progress 85 % (9 MB)
72 20:50:54.042881 progress 90 % (9 MB)
73 20:50:54.049882 progress 95 % (10 MB)
74 20:50:54.056937 progress 100 % (10 MB)
75 20:50:54.057417 10 MB downloaded in 0.19 s (56.34 MB/s)
76 20:50:54.057900 end: 1.2.1 http-download (duration 00:00:00) [common]
78 20:50:54.058723 end: 1.2 download-retry (duration 00:00:00) [common]
79 20:50:54.058995 start: 1.3 download-retry (timeout 00:10:00) [common]
80 20:50:54.059256 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 20:50:54.059718 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 20:50:54.059957 saving as /var/lib/lava/dispatcher/tmp/955456/tftp-deploy-lfqq7hzz/dtb/am335x-boneblack.dtb
83 20:50:54.060161 total size: 70568 (0 MB)
84 20:50:54.060368 No compression specified
85 20:50:54.099481 progress 46 % (0 MB)
86 20:50:54.100305 progress 92 % (0 MB)
87 20:50:54.100966 progress 100 % (0 MB)
88 20:50:54.101336 0 MB downloaded in 0.04 s (1.63 MB/s)
89 20:50:54.101780 end: 1.3.1 http-download (duration 00:00:00) [common]
91 20:50:54.102623 end: 1.3 download-retry (duration 00:00:00) [common]
92 20:50:54.102887 start: 1.4 download-retry (timeout 00:10:00) [common]
93 20:50:54.103149 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 20:50:54.103608 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 20:50:54.103847 saving as /var/lib/lava/dispatcher/tmp/955456/tftp-deploy-lfqq7hzz/nfsrootfs/full.rootfs.tar
96 20:50:54.104049 total size: 117747780 (112 MB)
97 20:50:54.104259 Using unxz to decompress xz
98 20:50:54.134648 progress 0 % (0 MB)
99 20:50:54.862473 progress 5 % (5 MB)
100 20:50:55.605794 progress 10 % (11 MB)
101 20:50:56.373954 progress 15 % (16 MB)
102 20:50:57.084273 progress 20 % (22 MB)
103 20:50:57.657253 progress 25 % (28 MB)
104 20:50:58.477975 progress 30 % (33 MB)
105 20:50:59.312278 progress 35 % (39 MB)
106 20:50:59.674208 progress 40 % (44 MB)
107 20:51:00.053762 progress 45 % (50 MB)
108 20:51:00.733405 progress 50 % (56 MB)
109 20:51:01.533833 progress 55 % (61 MB)
110 20:51:02.249233 progress 60 % (67 MB)
111 20:51:02.954381 progress 65 % (73 MB)
112 20:51:03.702913 progress 70 % (78 MB)
113 20:51:04.449682 progress 75 % (84 MB)
114 20:51:05.190680 progress 80 % (89 MB)
115 20:51:05.896226 progress 85 % (95 MB)
116 20:51:06.688071 progress 90 % (101 MB)
117 20:51:07.441914 progress 95 % (106 MB)
118 20:51:08.244330 progress 100 % (112 MB)
119 20:51:08.256561 112 MB downloaded in 14.15 s (7.93 MB/s)
120 20:51:08.257503 end: 1.4.1 http-download (duration 00:00:14) [common]
122 20:51:08.259373 end: 1.4 download-retry (duration 00:00:14) [common]
123 20:51:08.259960 start: 1.5 download-retry (timeout 00:09:45) [common]
124 20:51:08.260540 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 20:51:08.261452 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 20:51:08.262002 saving as /var/lib/lava/dispatcher/tmp/955456/tftp-deploy-lfqq7hzz/modules/modules.tar
127 20:51:08.262467 total size: 6608112 (6 MB)
128 20:51:08.262940 Using unxz to decompress xz
129 20:51:08.306864 progress 0 % (0 MB)
130 20:51:08.341735 progress 5 % (0 MB)
131 20:51:08.388201 progress 10 % (0 MB)
132 20:51:08.431265 progress 15 % (0 MB)
133 20:51:08.475063 progress 20 % (1 MB)
134 20:51:08.522269 progress 25 % (1 MB)
135 20:51:08.566043 progress 30 % (1 MB)
136 20:51:08.608159 progress 35 % (2 MB)
137 20:51:08.651593 progress 40 % (2 MB)
138 20:51:08.698282 progress 45 % (2 MB)
139 20:51:08.751577 progress 50 % (3 MB)
140 20:51:08.803877 progress 55 % (3 MB)
141 20:51:08.859285 progress 60 % (3 MB)
142 20:51:08.916463 progress 65 % (4 MB)
143 20:51:08.969747 progress 70 % (4 MB)
144 20:51:09.027112 progress 75 % (4 MB)
145 20:51:09.080375 progress 80 % (5 MB)
146 20:51:09.132652 progress 85 % (5 MB)
147 20:51:09.185714 progress 90 % (5 MB)
148 20:51:09.238806 progress 95 % (6 MB)
149 20:51:09.293227 progress 100 % (6 MB)
150 20:51:09.309246 6 MB downloaded in 1.05 s (6.02 MB/s)
151 20:51:09.309885 end: 1.5.1 http-download (duration 00:00:01) [common]
153 20:51:09.311510 end: 1.5 download-retry (duration 00:00:01) [common]
154 20:51:09.312031 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 20:51:09.312542 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 20:51:26.292034 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/955456/extract-nfsrootfs-svlvjh47
157 20:51:26.292649 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 20:51:26.292937 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 20:51:26.293549 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao
160 20:51:26.294002 makedir: /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin
161 20:51:26.294336 makedir: /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/tests
162 20:51:26.294655 makedir: /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/results
163 20:51:26.294993 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-add-keys
164 20:51:26.295524 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-add-sources
165 20:51:26.296058 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-background-process-start
166 20:51:26.296573 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-background-process-stop
167 20:51:26.297113 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-common-functions
168 20:51:26.297619 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-echo-ipv4
169 20:51:26.298149 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-install-packages
170 20:51:26.298634 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-installed-packages
171 20:51:26.299115 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-os-build
172 20:51:26.299595 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-probe-channel
173 20:51:26.300079 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-probe-ip
174 20:51:26.300592 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-target-ip
175 20:51:26.301108 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-target-mac
176 20:51:26.301595 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-target-storage
177 20:51:26.302151 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-test-case
178 20:51:26.302671 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-test-event
179 20:51:26.303161 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-test-feedback
180 20:51:26.303643 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-test-raise
181 20:51:26.304207 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-test-reference
182 20:51:26.304732 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-test-runner
183 20:51:26.305250 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-test-set
184 20:51:26.305776 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-test-shell
185 20:51:26.306324 Updating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-add-keys (debian)
186 20:51:26.306872 Updating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-add-sources (debian)
187 20:51:26.307387 Updating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-install-packages (debian)
188 20:51:26.307891 Updating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-installed-packages (debian)
189 20:51:26.308386 Updating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/bin/lava-os-build (debian)
190 20:51:26.308821 Creating /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/environment
191 20:51:26.309193 LAVA metadata
192 20:51:26.309454 - LAVA_JOB_ID=955456
193 20:51:26.309667 - LAVA_DISPATCHER_IP=192.168.6.3
194 20:51:26.310070 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 20:51:26.311031 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 20:51:26.311344 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 20:51:26.311548 skipped lava-vland-overlay
198 20:51:26.311786 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 20:51:26.312039 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 20:51:26.312241 skipped lava-multinode-overlay
201 20:51:26.312476 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 20:51:26.312722 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 20:51:26.312969 Loading test definitions
204 20:51:26.313243 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 20:51:26.313478 Using /lava-955456 at stage 0
206 20:51:26.314595 uuid=955456_1.6.2.4.1 testdef=None
207 20:51:26.314902 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 20:51:26.315167 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 20:51:26.316716 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 20:51:26.317494 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 20:51:26.319474 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 20:51:26.320298 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 20:51:26.322109 runner path: /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/0/tests/0_timesync-off test_uuid 955456_1.6.2.4.1
216 20:51:26.322676 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 20:51:26.323487 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 20:51:26.323709 Using /lava-955456 at stage 0
220 20:51:26.324062 Fetching tests from https://github.com/kernelci/test-definitions.git
221 20:51:26.324355 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/0/tests/1_kselftest-dt'
222 20:51:29.676313 Running '/usr/bin/git checkout kernelci.org
223 20:51:30.229094 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 20:51:30.230613 uuid=955456_1.6.2.4.5 testdef=None
225 20:51:30.230970 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 20:51:30.231710 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 20:51:30.235073 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 20:51:30.238231 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 20:51:30.242714 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 20:51:30.244968 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 20:51:30.250117 runner path: /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/0/tests/1_kselftest-dt test_uuid 955456_1.6.2.4.5
235 20:51:30.250497 BOARD='beaglebone-black'
236 20:51:30.250712 BRANCH='broonie-sound'
237 20:51:30.250925 SKIPFILE='/dev/null'
238 20:51:30.251123 SKIP_INSTALL='True'
239 20:51:30.251320 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 20:51:30.251522 TST_CASENAME=''
241 20:51:30.251715 TST_CMDFILES='dt'
242 20:51:30.252345 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 20:51:30.253232 Creating lava-test-runner.conf files
245 20:51:30.253456 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/955456/lava-overlay-qfsb6bao/lava-955456/0 for stage 0
246 20:51:30.253870 - 0_timesync-off
247 20:51:30.254165 - 1_kselftest-dt
248 20:51:30.254536 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 20:51:30.254839 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 20:51:53.632160 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 20:51:53.632577 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 20:51:53.632842 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 20:51:53.633112 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 20:51:53.633375 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 20:51:54.012015 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 20:51:54.012509 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 20:51:54.012763 extracting modules file /var/lib/lava/dispatcher/tmp/955456/tftp-deploy-lfqq7hzz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955456/extract-nfsrootfs-svlvjh47
258 20:51:54.911886 extracting modules file /var/lib/lava/dispatcher/tmp/955456/tftp-deploy-lfqq7hzz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955456/extract-overlay-ramdisk-vqltf2z3/ramdisk
259 20:51:55.877335 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 20:51:55.877827 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 20:51:55.878114 [common] Applying overlay to NFS
262 20:51:55.878330 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955456/compress-overlay-nov7xbzy/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/955456/extract-nfsrootfs-svlvjh47
263 20:51:58.613560 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 20:51:58.614051 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 20:51:58.614328 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 20:51:58.614630 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 20:51:58.614888 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 20:51:58.615149 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 20:51:58.615399 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 20:51:58.615654 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 20:51:58.615880 Building ramdisk /var/lib/lava/dispatcher/tmp/955456/extract-overlay-ramdisk-vqltf2z3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/955456/extract-overlay-ramdisk-vqltf2z3/ramdisk
272 20:51:59.605366 >> 74896 blocks
273 20:52:04.160604 Adding RAMdisk u-boot header.
274 20:52:04.161267 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/955456/extract-overlay-ramdisk-vqltf2z3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/955456/extract-overlay-ramdisk-vqltf2z3/ramdisk.cpio.gz.uboot
275 20:52:04.318516 output: Image Name:
276 20:52:04.318944 output: Created: Thu Nov 7 20:52:04 2024
277 20:52:04.319154 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 20:52:04.319359 output: Data Size: 14788371 Bytes = 14441.77 KiB = 14.10 MiB
279 20:52:04.319562 output: Load Address: 00000000
280 20:52:04.319759 output: Entry Point: 00000000
281 20:52:04.319955 output:
282 20:52:04.320554 rename /var/lib/lava/dispatcher/tmp/955456/extract-overlay-ramdisk-vqltf2z3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/955456/tftp-deploy-lfqq7hzz/ramdisk/ramdisk.cpio.gz.uboot
283 20:52:04.320970 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 20:52:04.321251 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 20:52:04.321523 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 20:52:04.321766 No LXC device requested
287 20:52:04.322370 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 20:52:04.322959 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 20:52:04.323507 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 20:52:04.323963 Checking files for TFTP limit of 4294967296 bytes.
291 20:52:04.326911 end: 1 tftp-deploy (duration 00:01:11) [common]
292 20:52:04.327540 start: 2 uboot-action (timeout 00:05:00) [common]
293 20:52:04.328117 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 20:52:04.328663 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 20:52:04.329210 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 20:52:04.330057 substitutions:
297 20:52:04.330532 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 20:52:04.330980 - {DTB_ADDR}: 0x88000000
299 20:52:04.331416 - {DTB}: 955456/tftp-deploy-lfqq7hzz/dtb/am335x-boneblack.dtb
300 20:52:04.331854 - {INITRD}: 955456/tftp-deploy-lfqq7hzz/ramdisk/ramdisk.cpio.gz.uboot
301 20:52:04.332288 - {KERNEL_ADDR}: 0x82000000
302 20:52:04.332719 - {KERNEL}: 955456/tftp-deploy-lfqq7hzz/kernel/zImage
303 20:52:04.333149 - {LAVA_MAC}: None
304 20:52:04.333625 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/955456/extract-nfsrootfs-svlvjh47
305 20:52:04.334104 - {NFS_SERVER_IP}: 192.168.6.3
306 20:52:04.334539 - {PRESEED_CONFIG}: None
307 20:52:04.334968 - {PRESEED_LOCAL}: None
308 20:52:04.335394 - {RAMDISK_ADDR}: 0x83000000
309 20:52:04.335822 - {RAMDISK}: 955456/tftp-deploy-lfqq7hzz/ramdisk/ramdisk.cpio.gz.uboot
310 20:52:04.336253 - {ROOT_PART}: None
311 20:52:04.336675 - {ROOT}: None
312 20:52:04.337096 - {SERVER_IP}: 192.168.6.3
313 20:52:04.337515 - {TEE_ADDR}: 0x83000000
314 20:52:04.337969 - {TEE}: None
315 20:52:04.338412 Parsed boot commands:
316 20:52:04.338826 - setenv autoload no
317 20:52:04.339247 - setenv initrd_high 0xffffffff
318 20:52:04.339667 - setenv fdt_high 0xffffffff
319 20:52:04.340084 - dhcp
320 20:52:04.340501 - setenv serverip 192.168.6.3
321 20:52:04.340922 - tftp 0x82000000 955456/tftp-deploy-lfqq7hzz/kernel/zImage
322 20:52:04.341347 - tftp 0x83000000 955456/tftp-deploy-lfqq7hzz/ramdisk/ramdisk.cpio.gz.uboot
323 20:52:04.341770 - setenv initrd_size ${filesize}
324 20:52:04.342226 - tftp 0x88000000 955456/tftp-deploy-lfqq7hzz/dtb/am335x-boneblack.dtb
325 20:52:04.342653 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/955456/extract-nfsrootfs-svlvjh47,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 20:52:04.343090 - bootz 0x82000000 0x83000000 0x88000000
327 20:52:04.343635 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 20:52:04.345252 start: 2.3 connect-device (timeout 00:05:00) [common]
330 20:52:04.345710 [common] connect-device Connecting to device using 'telnet conserv3 3000'
331 20:52:04.361346 Setting prompt string to ['lava-test: # ']
332 20:52:04.362988 end: 2.3 connect-device (duration 00:00:00) [common]
333 20:52:04.363673 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 20:52:04.364362 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 20:52:04.365143 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 20:52:04.366522 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
337 20:52:04.404247 >> OK - accepted request
338 20:52:04.406185 Returned 0 in 0 seconds
339 20:52:04.507328 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 20:52:04.508362 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 20:52:04.508706 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 20:52:04.509010 Setting prompt string to ['Hit any key to stop autoboot']
344 20:52:04.509272 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 20:52:04.510240 Trying 192.168.56.22...
346 20:52:04.510548 Connected to conserv3.
347 20:52:04.510789 Escape character is '^]'.
348 20:52:04.511043
349 20:52:04.511300 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 20:52:04.511540
351 20:52:12.763427
352 20:52:12.770576 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
353 20:52:12.771218 Trying to boot from MMC1
354 20:52:13.356485
355 20:52:13.357307
356 20:52:13.361846 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
357 20:52:13.362463
358 20:52:13.362952 CPU : AM335X-GP rev 2.0
359 20:52:13.367455 Model: TI AM335x BeagleBone Black
360 20:52:13.368117 DRAM: 512 MiB
361 20:52:16.816502
362 20:52:16.823297 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
363 20:52:16.823905 Trying to boot from MMC1
364 20:52:17.409700
365 20:52:17.410147
366 20:52:17.414796 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
367 20:52:17.415045
368 20:52:17.415255 CPU : AM335X-GP rev 2.0
369 20:52:17.420145 Model: TI AM335x BeagleBone Black
370 20:52:17.420395 DRAM: 512 MiB
371 20:52:19.511961
372 20:52:19.518814 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
373 20:52:19.519339 Trying to boot from MMC1
374 20:52:20.105104
375 20:52:20.105518
376 20:52:20.110525 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
377 20:52:20.110932
378 20:52:20.111276 CPU : AM335X-GP rev 2.0
379 20:52:20.115670 Model: TI AM335x BeagleBone Black
380 20:52:20.115964 DRAM: 512 MiB
381 20:52:20.200338 Core: 160 devices, 18 uclasses, devicetree: separate
382 20:52:20.214071 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 20:52:20.614888 NAND: 0 MiB
384 20:52:20.624743 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 20:52:20.699418 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 20:52:20.720781 <ethaddr> not set. Validating first E-fuse MAC
387 20:52:20.750436 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 20:52:20.808756 Hit any key to stop autoboot: 2
390 20:52:20.809440 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
391 20:52:20.809788 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
392 20:52:20.810095 Setting prompt string to ['=>']
393 20:52:20.810370 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
394 20:52:20.818213 0
395 20:52:20.818846 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 20:52:20.819147 Sending with 10 millisecond of delay
398 20:52:21.953707 => setenv autoload no
399 20:52:21.964576 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
400 20:52:21.969485 setenv autoload no
401 20:52:21.970228 Sending with 10 millisecond of delay
403 20:52:23.767243 => setenv initrd_high 0xffffffff
404 20:52:23.777993 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
405 20:52:23.778840 setenv initrd_high 0xffffffff
406 20:52:23.779538 Sending with 10 millisecond of delay
408 20:52:25.395628 => setenv fdt_high 0xffffffff
409 20:52:25.406393 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
410 20:52:25.407221 setenv fdt_high 0xffffffff
411 20:52:25.407918 Sending with 10 millisecond of delay
413 20:52:25.699680 => dhcp
414 20:52:25.710426 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
415 20:52:25.711261 dhcp
416 20:52:25.711696 link up on port 0, speed 100, full duplex
417 20:52:25.712105 BOOTP broadcast 1
418 20:52:25.965010 BOOTP broadcast 2
419 20:52:26.466964 BOOTP broadcast 3
420 20:52:27.469052 BOOTP broadcast 4
421 20:52:29.470930 BOOTP broadcast 5
422 20:52:29.720350 DHCP client bound to address 192.168.6.23 (4004 ms)
423 20:52:29.721219 Sending with 10 millisecond of delay
425 20:52:31.398524 => setenv serverip 192.168.6.3
426 20:52:31.409366 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
427 20:52:31.410445 setenv serverip 192.168.6.3
428 20:52:31.411217 Sending with 10 millisecond of delay
430 20:52:34.893634 => tftp 0x82000000 955456/tftp-deploy-lfqq7hzz/kernel/zImage
431 20:52:34.904471 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
432 20:52:34.905348 tftp 0x82000000 955456/tftp-deploy-lfqq7hzz/kernel/zImage
433 20:52:34.905773 link up on port 0, speed 100, full duplex
434 20:52:34.909848 Using ethernet@4a100000 device
435 20:52:34.915069 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
436 20:52:34.915493 Filename '955456/tftp-deploy-lfqq7hzz/kernel/zImage'.
437 20:52:34.922212 Load address: 0x82000000
438 20:52:37.022924 Loading: *################################################## 10.9 MiB
439 20:52:37.023321 5.2 MiB/s
440 20:52:37.023536 done
441 20:52:37.027206 Bytes transferred = 11440640 (ae9200 hex)
442 20:52:37.028326 Sending with 10 millisecond of delay
444 20:52:41.476337 => tftp 0x83000000 955456/tftp-deploy-lfqq7hzz/ramdisk/ramdisk.cpio.gz.uboot
445 20:52:41.486908 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
446 20:52:41.487483 tftp 0x83000000 955456/tftp-deploy-lfqq7hzz/ramdisk/ramdisk.cpio.gz.uboot
447 20:52:41.487747 link up on port 0, speed 100, full duplex
448 20:52:41.491597 Using ethernet@4a100000 device
449 20:52:41.497208 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
450 20:52:41.505983 Filename '955456/tftp-deploy-lfqq7hzz/ramdisk/ramdisk.cpio.gz.uboot'.
451 20:52:41.506374 Load address: 0x83000000
452 20:52:44.242389 Loading: *################################################## 14.1 MiB
453 20:52:44.242788 5.2 MiB/s
454 20:52:44.242997 done
455 20:52:44.246221 Bytes transferred = 14788435 (e1a753 hex)
456 20:52:44.246777 Sending with 10 millisecond of delay
458 20:52:46.110792 => setenv initrd_size ${filesize}
459 20:52:46.121340 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
460 20:52:46.121886 setenv initrd_size ${filesize}
461 20:52:46.122369 Sending with 10 millisecond of delay
463 20:52:50.268728 => tftp 0x88000000 955456/tftp-deploy-lfqq7hzz/dtb/am335x-boneblack.dtb
464 20:52:50.279494 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
465 20:52:50.421068 tftp 0x88000000 955456/tftp-deploy-lfqq7hzz/dtb/am335x-boneblack.dtb
466 20:52:50.421673 link up on port 0, speed 100, full duplex
467 20:52:50.426437 Using ethernet@4a100000 device
468 20:52:50.431985 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
469 20:52:50.442157 Filename '955456/tftp-deploy-lfqq7hzz/dtb/am335x-boneblack.dtb'.
470 20:52:50.442611 Load address: 0x88000000
471 20:52:50.453152 Loading: *################################################## 68.9 KiB
472 20:52:50.453612 4.8 MiB/s
473 20:52:50.461900 done
474 20:52:50.462351 Bytes transferred = 70568 (113a8 hex)
475 20:52:50.463032 Sending with 10 millisecond of delay
477 20:53:03.646873 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/955456/extract-nfsrootfs-svlvjh47,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 20:53:03.657763 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
479 20:53:03.658770 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/955456/extract-nfsrootfs-svlvjh47,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 20:53:03.659539 Sending with 10 millisecond of delay
482 20:53:05.999058 => bootz 0x82000000 0x83000000 0x88000000
483 20:53:06.009915 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 20:53:06.010558 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
485 20:53:06.011652 bootz 0x82000000 0x83000000 0x88000000
486 20:53:06.012190 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
487 20:53:06.012766 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 20:53:06.017632 Image Name:
489 20:53:06.018216 Created: 2024-11-07 20:52:04 UTC
490 20:53:06.026611 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 20:53:06.027193 Data Size: 14788371 Bytes = 14.1 MiB
492 20:53:06.034945 Load Address: 00000000
493 20:53:06.035526 Entry Point: 00000000
494 20:53:06.203203 Verifying Checksum ... OK
495 20:53:06.203843 ## Flattened Device Tree blob at 88000000
496 20:53:06.209634 Booting using the fdt blob at 0x88000000
497 20:53:06.210242 Working FDT set to 88000000
498 20:53:06.215283 Using Device Tree in place at 88000000, end 880143a7
499 20:53:06.219043 Working FDT set to 88000000
500 20:53:06.232360
501 20:53:06.232901 Starting kernel ...
502 20:53:06.233366
503 20:53:06.234366 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
504 20:53:06.235077 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
505 20:53:06.235641 Setting prompt string to ['Linux version [0-9]']
506 20:53:06.236188 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
507 20:53:06.236749 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
508 20:53:07.075876 [ 0.000000] Booting Linux on physical CPU 0x0
509 20:53:07.081968 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
510 20:53:07.082589 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 20:53:07.083113 Setting prompt string to []
512 20:53:07.083658 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 20:53:07.084166 Using line separator: #'\n'#
514 20:53:07.084621 No login prompt set.
515 20:53:07.085102 Parsing kernel messages
516 20:53:07.085545 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 20:53:07.086456 [login-action] Waiting for messages, (timeout 00:03:57)
518 20:53:07.086948 Waiting using forced prompt support (timeout 00:01:59)
519 20:53:07.095627 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j367288-arm-gcc-12-multi-v7-defconfig-kk5n8) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Nov 7 20:15:18 UTC 2024
520 20:53:07.106905 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
521 20:53:07.112713 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
522 20:53:07.118524 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
523 20:53:07.124161 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
524 20:53:07.129923 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
525 20:53:07.136641 [ 0.000000] Memory policy: Data cache writeback
526 20:53:07.137147 [ 0.000000] efi: UEFI not found.
527 20:53:07.144249 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
528 20:53:07.150750 [ 0.000000] Zone ranges:
529 20:53:07.156480 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
530 20:53:07.162158 [ 0.000000] Normal empty
531 20:53:07.162728 [ 0.000000] HighMem empty
532 20:53:07.167960 [ 0.000000] Movable zone start for each node
533 20:53:07.168507 [ 0.000000] Early memory node ranges
534 20:53:07.179385 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
535 20:53:07.184182 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
536 20:53:07.210134 [ 0.000000] CPU: All CPU(s) started in SVC mode.
537 20:53:07.215523 [ 0.000000] AM335X ES2.0 (sgx neon)
538 20:53:07.227350 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
539 20:53:07.245032 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/955456/extract-nfsrootfs-svlvjh47,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
540 20:53:07.256600 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
541 20:53:07.262327 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
542 20:53:07.268070 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
543 20:53:07.277872 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
544 20:53:07.307104 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
545 20:53:07.313051 <6>[ 0.000000] trace event string verifier disabled
546 20:53:07.313614 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
547 20:53:07.318800 <6>[ 0.000000] rcu: RCU event tracing is enabled.
548 20:53:07.330181 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
549 20:53:07.335973 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
550 20:53:07.343326 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
551 20:53:07.357311 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
552 20:53:07.375219 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
553 20:53:07.381556 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
554 20:53:07.473652 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
555 20:53:07.485131 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
556 20:53:07.491912 <6>[ 0.008334] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
557 20:53:07.503973 <6>[ 0.019138] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
558 20:53:07.512263 <6>[ 0.033924] Console: colour dummy device 80x30
559 20:53:07.518443 Matched prompt #6: WARNING:
560 20:53:07.519054 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
561 20:53:07.523798 <3>[ 0.038826] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
562 20:53:07.526632 <3>[ 0.045896] This ensures that you still see kernel messages. Please
563 20:53:07.532703 <3>[ 0.052621] update your kernel commandline.
564 20:53:07.573400 <6>[ 0.057237] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
565 20:53:07.579216 <6>[ 0.096142] CPU: Testing write buffer coherency: ok
566 20:53:07.585147 <6>[ 0.101509] CPU0: Spectre v2: using BPIALL workaround
567 20:53:07.585702 <6>[ 0.106974] pid_max: default: 32768 minimum: 301
568 20:53:07.596573 <6>[ 0.112165] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 20:53:07.603532 <6>[ 0.119989] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
570 20:53:07.609870 <6>[ 0.129342] CPU0: thread -1, cpu 0, socket -1, mpidr 0
571 20:53:07.681257 <6>[ 0.199521] Setting up static identity map for 0x80300000 - 0x803000ac
572 20:53:07.687482 <6>[ 0.209117] rcu: Hierarchical SRCU implementation.
573 20:53:07.695389 <6>[ 0.214407] rcu: Max phase no-delay instances is 1000.
574 20:53:07.704105 <6>[ 0.225415] EFI services will not be available.
575 20:53:07.709912 <6>[ 0.230780] smp: Bringing up secondary CPUs ...
576 20:53:07.715682 <6>[ 0.235753] smp: Brought up 1 node, 1 CPU
577 20:53:07.721448 <6>[ 0.240229] SMP: Total of 1 processors activated (996.14 BogoMIPS).
578 20:53:07.727358 <6>[ 0.246946] CPU: All CPU(s) started in SVC mode.
579 20:53:07.747326 <6>[ 0.252140] Memory: 406000K/522240K available (16384K kernel code, 2542K rwdata, 6784K rodata, 2048K init, 431K bss, 49048K reserved, 65536K cma-reserved, 0K highmem)
580 20:53:07.747913 <6>[ 0.268412] devtmpfs: initialized
581 20:53:07.769883 <6>[ 0.285460] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
582 20:53:07.781360 <6>[ 0.294054] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
583 20:53:07.786808 <6>[ 0.304496] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
584 20:53:07.798012 <6>[ 0.316768] pinctrl core: initialized pinctrl subsystem
585 20:53:07.807273 <6>[ 0.327400] DMI not present or invalid.
586 20:53:07.814269 <6>[ 0.333242] NET: Registered PF_NETLINK/PF_ROUTE protocol family
587 20:53:07.824615 <6>[ 0.342204] DMA: preallocated 256 KiB pool for atomic coherent allocations
588 20:53:07.839274 <6>[ 0.353618] thermal_sys: Registered thermal governor 'step_wise'
589 20:53:07.839849 <6>[ 0.353792] cpuidle: using governor menu
590 20:53:07.867822 <6>[ 0.389499] No ATAGs?
591 20:53:07.873227 <6>[ 0.392143] hw-breakpoint: debug architecture 0x4 unsupported.
592 20:53:07.883330 <6>[ 0.404044] Serial: AMBA PL011 UART driver
593 20:53:07.913700 <6>[ 0.435229] iommu: Default domain type: Translated
594 20:53:07.922593 <6>[ 0.440579] iommu: DMA domain TLB invalidation policy: strict mode
595 20:53:07.949380 <5>[ 0.470650] SCSI subsystem initialized
596 20:53:07.964010 <6>[ 0.480062] usbcore: registered new interface driver usbfs
597 20:53:07.970966 <6>[ 0.486021] usbcore: registered new interface driver hub
598 20:53:07.971520 <6>[ 0.491850] usbcore: registered new device driver usb
599 20:53:07.976800 <6>[ 0.498336] pps_core: LinuxPPS API ver. 1 registered
600 20:53:07.988164 <6>[ 0.503780] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
601 20:53:07.996937 <6>[ 0.513484] PTP clock support registered
602 20:53:07.997490 <6>[ 0.517930] EDAC MC: Ver: 3.0.0
603 20:53:08.043878 <6>[ 0.563397] scmi_core: SCMI protocol bus registered
604 20:53:08.068870 <6>[ 0.589869] vgaarb: loaded
605 20:53:08.074237 <6>[ 0.593642] clocksource: Switched to clocksource dmtimer
606 20:53:08.099228 <6>[ 0.620550] NET: Registered PF_INET protocol family
607 20:53:08.111763 <6>[ 0.626253] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
608 20:53:08.117600 <6>[ 0.635090] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
609 20:53:08.129013 <6>[ 0.644021] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
610 20:53:08.134842 <6>[ 0.652263] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
611 20:53:08.146323 <6>[ 0.660558] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
612 20:53:08.152256 <6>[ 0.668277] TCP: Hash tables configured (established 4096 bind 4096)
613 20:53:08.158051 <6>[ 0.675200] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
614 20:53:08.163966 <6>[ 0.682211] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
615 20:53:08.170552 <6>[ 0.689826] NET: Registered PF_UNIX/PF_LOCAL protocol family
616 20:53:08.257440 <6>[ 0.773453] RPC: Registered named UNIX socket transport module.
617 20:53:08.258076 <6>[ 0.779886] RPC: Registered udp transport module.
618 20:53:08.263252 <6>[ 0.785012] RPC: Registered tcp transport module.
619 20:53:08.269000 <6>[ 0.790117] RPC: Registered tcp-with-tls transport module.
620 20:53:08.281945 <6>[ 0.796039] RPC: Registered tcp NFSv4.1 backchannel transport module.
621 20:53:08.282580 <6>[ 0.802947] PCI: CLS 0 bytes, default 64
622 20:53:08.289166 <5>[ 0.808721] Initialise system trusted keyrings
623 20:53:08.309606 <6>[ 0.828828] Trying to unpack rootfs image as initramfs...
624 20:53:08.389222 <6>[ 0.904635] workingset: timestamp_bits=30 max_order=17 bucket_order=0
625 20:53:08.393565 <6>[ 0.912149] squashfs: version 4.0 (2009/01/31) Phillip Lougher
626 20:53:08.432656 <5>[ 0.954426] NFS: Registering the id_resolver key type
627 20:53:08.438624 <5>[ 0.960019] Key type id_resolver registered
628 20:53:08.444289 <5>[ 0.964708] Key type id_legacy registered
629 20:53:08.450094 <6>[ 0.969149] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
630 20:53:08.459617 <6>[ 0.976356] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
631 20:53:08.528799 <5>[ 1.050436] Key type asymmetric registered
632 20:53:08.534615 <5>[ 1.055011] Asymmetric key parser 'x509' registered
633 20:53:08.546137 <6>[ 1.060439] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
634 20:53:08.546764 <6>[ 1.068360] io scheduler mq-deadline registered
635 20:53:08.551957 <6>[ 1.073292] io scheduler kyber registered
636 20:53:08.557143 <6>[ 1.077781] io scheduler bfq registered
637 20:53:08.676200 <6>[ 1.194811] ledtrig-cpu: registered to indicate activity on CPUs
638 20:53:08.979534 <6>[ 1.497391] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
639 20:53:09.005291 <6>[ 1.526748] msm_serial: driver initialized
640 20:53:09.011396 <6>[ 1.531533] SuperH (H)SCI(F) driver initialized
641 20:53:09.017259 <6>[ 1.536850] STMicroelectronics ASC driver initialized
642 20:53:09.022084 <6>[ 1.542454] STM32 USART driver initialized
643 20:53:09.153091 <6>[ 1.674404] brd: module loaded
644 20:53:09.184271 <6>[ 1.705588] loop: module loaded
645 20:53:09.220393 <6>[ 1.741115] CAN device driver interface
646 20:53:09.226904 <6>[ 1.746365] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
647 20:53:09.232742 <6>[ 1.753264] e1000e: Intel(R) PRO/1000 Network Driver
648 20:53:09.239409 <6>[ 1.758726] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
649 20:53:09.245289 <6>[ 1.765177] igb: Intel(R) Gigabit Ethernet Network Driver
650 20:53:09.251927 <6>[ 1.771001] igb: Copyright (c) 2007-2014 Intel Corporation.
651 20:53:09.264172 <6>[ 1.780154] pegasus: Pegasus/Pegasus II USB Ethernet driver
652 20:53:09.270059 <6>[ 1.786309] usbcore: registered new interface driver pegasus
653 20:53:09.272803 <6>[ 1.792436] usbcore: registered new interface driver asix
654 20:53:09.278569 <6>[ 1.798319] usbcore: registered new interface driver ax88179_178a
655 20:53:09.284286 <6>[ 1.804908] usbcore: registered new interface driver cdc_ether
656 20:53:09.290108 <6>[ 1.811202] usbcore: registered new interface driver smsc75xx
657 20:53:09.298570 <6>[ 1.817441] usbcore: registered new interface driver smsc95xx
658 20:53:09.304428 <6>[ 1.823680] usbcore: registered new interface driver net1080
659 20:53:09.310191 <6>[ 1.829806] usbcore: registered new interface driver cdc_subset
660 20:53:09.318724 <6>[ 1.836213] usbcore: registered new interface driver zaurus
661 20:53:09.323403 <6>[ 1.842258] usbcore: registered new interface driver cdc_ncm
662 20:53:09.333162 <6>[ 1.851654] usbcore: registered new interface driver usb-storage
663 20:53:09.619491 <6>[ 2.139258] i2c_dev: i2c /dev entries driver
664 20:53:09.666077 <5>[ 2.179934] cpuidle: enable-method property 'ti,am3352' found operations
665 20:53:09.671958 <6>[ 2.189576] sdhci: Secure Digital Host Controller Interface driver
666 20:53:09.679370 <6>[ 2.196373] sdhci: Copyright(c) Pierre Ossman
667 20:53:09.686589 <6>[ 2.202785] Synopsys Designware Multimedia Card Interface Driver
668 20:53:09.691253 <6>[ 2.210710] sdhci-pltfm: SDHCI platform and OF driver helper
669 20:53:09.820026 <6>[ 2.335141] usbcore: registered new interface driver usbhid
670 20:53:09.820713 <6>[ 2.341184] usbhid: USB HID core driver
671 20:53:09.863945 <6>[ 2.384020] NET: Registered PF_INET6 protocol family
672 20:53:09.893711 <6>[ 2.415589] Segment Routing with IPv6
673 20:53:09.899586 <6>[ 2.419737] In-situ OAM (IOAM) with IPv6
674 20:53:09.906216 <6>[ 2.424273] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
675 20:53:09.913712 <6>[ 2.431496] NET: Registered PF_PACKET protocol family
676 20:53:09.919567 <6>[ 2.437058] can: controller area network core
677 20:53:09.920059 <6>[ 2.441891] NET: Registered PF_CAN protocol family
678 20:53:09.925456 <6>[ 2.447121] can: raw protocol
679 20:53:09.931138 <6>[ 2.450449] can: broadcast manager protocol
680 20:53:09.938051 <6>[ 2.455056] can: netlink gateway - max_hops=1
681 20:53:09.938680 <5>[ 2.460540] Key type dns_resolver registered
682 20:53:09.943789 <6>[ 2.465616] ThumbEE CPU extension supported.
683 20:53:09.950078 <5>[ 2.470308] Registering SWP/SWPB emulation handler
684 20:53:09.957603 <3>[ 2.475995] omap_voltage_late_init: Voltage driver support not added
685 20:53:10.154208 <5>[ 2.674459] Loading compiled-in X.509 certificates
686 20:53:10.284294 <6>[ 2.793098] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
687 20:53:10.291340 <6>[ 2.809759] pinctrl-single 44e10800.pinmux: 142 pins, size 568
688 20:53:10.316886 <3>[ 2.833466] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
689 20:53:10.516820 <3>[ 3.033243] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
690 20:53:10.713250 <6>[ 3.234058] OMAP GPIO hardware version 0.1
691 20:53:10.733908 <6>[ 3.252669] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
692 20:53:10.827137 <4>[ 3.345802] at24 2-0054: supply vcc not found, using dummy regulator
693 20:53:10.873216 <4>[ 3.391831] at24 2-0055: supply vcc not found, using dummy regulator
694 20:53:10.911889 <4>[ 3.430374] at24 2-0056: supply vcc not found, using dummy regulator
695 20:53:10.952130 <4>[ 3.470376] at24 2-0057: supply vcc not found, using dummy regulator
696 20:53:10.989541 <6>[ 3.508840] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
697 20:53:11.064566 <3>[ 3.579676] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
698 20:53:11.088845 <6>[ 3.600530] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
699 20:53:11.109289 <4>[ 3.626735] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
700 20:53:11.127308 <4>[ 3.644029] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
701 20:53:11.255820 <6>[ 3.774143] omap_rng 48310000.rng: Random Number Generator ver. 20
702 20:53:11.279606 <5>[ 3.800447] random: crng init done
703 20:53:11.319327 <6>[ 3.840870] Freeing initrd memory: 14444K
704 20:53:11.329123 <6>[ 3.845667] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
705 20:53:11.380461 <6>[ 3.896075] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
706 20:53:11.386239 <6>[ 3.906397] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
707 20:53:11.398054 <6>[ 3.913733] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
708 20:53:11.403793 <6>[ 3.921180] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
709 20:53:11.415307 <6>[ 3.929307] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
710 20:53:11.422708 <6>[ 3.940939] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
711 20:53:11.435860 <5>[ 3.949967] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
712 20:53:11.463585 <3>[ 3.979722] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
713 20:53:11.468683 <6>[ 3.988315] edma 49000000.dma: TI EDMA DMA engine driver
714 20:53:11.540558 <3>[ 4.055868] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
715 20:53:11.555142 <6>[ 4.070208] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
716 20:53:11.568131 <3>[ 4.087328] l3-aon-clkctrl:0000:0: failed to disable
717 20:53:11.618695 <6>[ 4.134777] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
718 20:53:11.624358 <6>[ 4.144242] printk: legacy console [ttyS0] enabled
719 20:53:11.630075 <6>[ 4.144242] printk: legacy console [ttyS0] enabled
720 20:53:11.635732 <6>[ 4.154581] printk: legacy bootconsole [omap8250] disabled
721 20:53:11.641565 <6>[ 4.154581] printk: legacy bootconsole [omap8250] disabled
722 20:53:11.679349 <4>[ 4.194412] tps65217-pmic: Failed to locate of_node [id: -1]
723 20:53:11.682147 <4>[ 4.201797] tps65217-bl: Failed to locate of_node [id: -1]
724 20:53:11.699500 <6>[ 4.221436] tps65217 0-0024: TPS65217 ID 0xe version 1.2
725 20:53:11.718708 <6>[ 4.228391] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
726 20:53:11.729375 <6>[ 4.242082] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
727 20:53:11.735116 <6>[ 4.253962] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
728 20:53:11.757069 <6>[ 4.273537] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
729 20:53:11.763051 <6>[ 4.282739] sdhci-omap 48060000.mmc: Got CD GPIO
730 20:53:11.771162 <4>[ 4.287915] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
731 20:53:11.785642 <4>[ 4.301535] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
732 20:53:11.792107 <4>[ 4.310170] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
733 20:53:11.801983 <4>[ 4.318826] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
734 20:53:11.925469 <6>[ 4.442892] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
735 20:53:11.971266 <6>[ 4.486462] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
736 20:53:11.977761 <6>[ 4.495839] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
737 20:53:11.986909 <6>[ 4.504797] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
738 20:53:12.040352 <6>[ 4.552951] mmc0: new high speed SDHC card at address 0001
739 20:53:12.040726 <6>[ 4.560341] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
740 20:53:12.046903 <6>[ 4.568745] mmcblk0: p1
741 20:53:12.069145 <6>[ 4.582979] mmc1: new high speed MMC card at address 0001
742 20:53:12.069464 <6>[ 4.590062] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
743 20:53:12.081829 <6>[ 4.597877] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
744 20:53:12.088229 <6>[ 4.609192] mmcblk1:
745 20:53:12.091029 <6>[ 4.612551] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
746 20:53:12.100531 <6>[ 4.620004] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
747 20:53:12.115197 <6>[ 4.633365] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
748 20:53:14.238558 <6>[ 6.754671] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
749 20:53:14.341874 <5>[ 6.783663] Sending DHCP requests ., OK
750 20:53:14.353207 <6>[ 6.868091] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.23
751 20:53:14.353616 <6>[ 6.876288] IP-Config: Complete:
752 20:53:14.364552 <6>[ 6.879827] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.6.23, mask=255.255.255.0, gw=192.168.6.1
753 20:53:14.370233 <6>[ 6.890349] host=192.168.6.23, domain=, nis-domain=(none)
754 20:53:14.382596 <6>[ 6.896560] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
755 20:53:14.383033 <6>[ 6.896593] nameserver0=10.255.253.1
756 20:53:14.388920 <6>[ 6.909143] clk: Disabling unused clocks
757 20:53:14.396697 <6>[ 6.913944] PM: genpd: Disabling unused power domains
758 20:53:14.414330 <6>[ 6.932837] Freeing unused kernel image (initmem) memory: 2048K
759 20:53:14.421725 <6>[ 6.942527] Run /init as init process
760 20:53:14.446443 Loading, please wait...
761 20:53:14.520769 Starting systemd-udevd version 252.22-1~deb12u1
762 20:53:17.603009 <4>[ 10.117638] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
763 20:53:17.750695 <4>[ 10.265293] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
764 20:53:17.930740 <6>[ 10.452903] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
765 20:53:17.941663 <6>[ 10.458783] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
766 20:53:18.150856 <6>[ 10.671323] hub 1-0:1.0: USB hub found
767 20:53:18.185650 <6>[ 10.706012] hub 1-0:1.0: 1 port detected
768 20:53:18.297531 <6>[ 10.817754] tda998x 0-0070: found TDA19988
769 20:53:21.106667 Begin: Loading essential drivers ... done.
770 20:53:21.112165 Begin: Running /scripts/init-premount ... done.
771 20:53:21.117675 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
772 20:53:21.127870 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
773 20:53:21.136916 Device /sys/class/net/eth0 found
774 20:53:21.137437 done.
775 20:53:21.195271 Begin: Waiting up to 180 secs for any network device to become available ... done.
776 20:53:21.274959 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
777 20:53:21.357515 IP-Config: eth0 guessed broadcast address 192.168.6.255
778 20:53:21.362917 IP-Config: eth0 complete (dhcp from 192.168.6.1):
779 20:53:21.368549 address: 192.168.6.23 broadcast: 192.168.6.255 netmask: 255.255.255.0
780 20:53:21.377578 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
781 20:53:21.383362 rootserver: 192.168.6.1 rootpath:
782 20:53:21.384156 filename :
783 20:53:21.473756 done.
784 20:53:21.496828 Begin: Running /scripts/nfs-bottom ... done.
785 20:53:21.540714 Begin: Running /scripts/init-bottom ... done.
786 20:53:22.919617 <30>[ 15.437421] systemd[1]: System time before build time, advancing clock.
787 20:53:23.193400 <30>[ 15.684994] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
788 20:53:23.202289 <30>[ 15.722050] systemd[1]: Detected architecture arm.
789 20:53:23.217487
790 20:53:23.218220 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
791 20:53:23.218814
792 20:53:23.245437 <30>[ 15.763958] systemd[1]: Hostname set to <debian-bookworm-armhf>.
793 20:53:25.372749 <30>[ 17.890203] systemd[1]: Queued start job for default target graphical.target.
794 20:53:25.389668 <30>[ 17.905216] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
795 20:53:25.397354 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
796 20:53:25.421129 <30>[ 17.936675] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
797 20:53:25.429497 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
798 20:53:25.451863 <30>[ 17.966556] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
799 20:53:25.459337 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
800 20:53:25.492395 <30>[ 18.007361] systemd[1]: Created slice user.slice - User and Session Slice.
801 20:53:25.499173 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
802 20:53:25.524667 <30>[ 18.034907] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
803 20:53:25.530725 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
804 20:53:25.548795 <30>[ 18.064735] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
805 20:53:25.557840 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
806 20:53:25.589733 <30>[ 18.094686] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
807 20:53:25.596269 <30>[ 18.115243] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
808 20:53:25.604738 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
809 20:53:25.627980 <30>[ 18.144185] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
810 20:53:25.636295 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
811 20:53:25.658634 <30>[ 18.174563] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
812 20:53:25.667166 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
813 20:53:25.690457 <30>[ 18.205772] systemd[1]: Reached target paths.target - Path Units.
814 20:53:25.695516 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
815 20:53:25.718117 <30>[ 18.234251] systemd[1]: Reached target remote-fs.target - Remote File Systems.
816 20:53:25.725476 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
817 20:53:25.747994 <30>[ 18.264131] systemd[1]: Reached target slices.target - Slice Units.
818 20:53:25.753476 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
819 20:53:25.778518 <30>[ 18.294470] systemd[1]: Reached target swap.target - Swaps.
820 20:53:25.782554 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
821 20:53:25.809397 <30>[ 18.325572] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
822 20:53:25.821565 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
823 20:53:25.849364 <30>[ 18.365128] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
824 20:53:25.857610 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
825 20:53:25.935044 <30>[ 18.446101] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
826 20:53:25.947787 <30>[ 18.463486] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
827 20:53:25.956245 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
828 20:53:25.980416 <30>[ 18.497866] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
829 20:53:25.992892 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
830 20:53:26.022186 <30>[ 18.536821] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
831 20:53:26.029305 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
832 20:53:26.064901 <30>[ 18.581443] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
833 20:53:26.078159 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
834 20:53:26.100057 <30>[ 18.615668] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
835 20:53:26.108664 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
836 20:53:26.135600 <30>[ 18.645411] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
837 20:53:26.152133 <30>[ 18.662067] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
838 20:53:26.203911 <30>[ 18.720725] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
839 20:53:26.228482 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
840 20:53:26.280155 <30>[ 18.796811] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
841 20:53:26.307334 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
842 20:53:26.409371 <30>[ 18.925056] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
843 20:53:26.437090 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
844 20:53:26.490424 <30>[ 19.006708] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
845 20:53:26.508611 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
846 20:53:26.548372 <30>[ 19.065037] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
847 20:53:26.577177 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
848 20:53:26.629890 <30>[ 19.147099] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
849 20:53:26.658192 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
850 20:53:26.710555 <30>[ 19.226488] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
851 20:53:26.739020 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
852 20:53:26.788580 <30>[ 19.305546] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
853 20:53:26.808365 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
854 20:53:26.868224 <30>[ 19.385267] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
855 20:53:26.896376 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
856 20:53:26.926589 <28>[ 19.437565] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
857 20:53:26.935144 <28>[ 19.451305] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
858 20:53:26.978563 <30>[ 19.494758] systemd[1]: Starting systemd-journald.service - Journal Service...
859 20:53:26.984975 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
860 20:53:27.022108 <30>[ 19.538859] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
861 20:53:27.047882 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
862 20:53:27.099922 <30>[ 19.616937] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
863 20:53:27.148634 Starting [0;1;39msystemd-network-g… units from Kernel command line...
864 20:53:27.221548 <30>[ 19.737014] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
865 20:53:27.270909 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
866 20:53:27.350093 <30>[ 19.866323] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
867 20:53:27.409491 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
868 20:53:27.469987 <30>[ 19.987080] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
869 20:53:27.508044 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
870 20:53:27.528300 <30>[ 20.045291] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
871 20:53:27.563792 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
872 20:53:27.592538 <30>[ 20.108523] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
873 20:53:27.620479 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
874 20:53:27.790494 <30>[ 20.308161] systemd[1]: modprobe@configfs.service: Deactivated successfully.
875 20:53:27.818717 <30>[ 20.335299] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
876 20:53:27.846907 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
877 20:53:27.868663 <30>[ 20.386529] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
878 20:53:27.908631 <30>[ 20.425518] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
879 20:53:27.937989 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
880 20:53:27.960140 <30>[ 20.475555] systemd[1]: Started systemd-journald.service - Journal Service.
881 20:53:27.967058 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
882 20:53:28.007864 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
883 20:53:28.040471 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
884 20:53:28.070131 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
885 20:53:28.092796 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
886 20:53:28.128014 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
887 20:53:28.160329 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
888 20:53:28.180477 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
889 20:53:28.212275 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
890 20:53:28.271221 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
891 20:53:28.310076 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
892 20:53:28.371888 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
893 20:53:28.474202 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
894 20:53:28.600106 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
895 20:53:28.656917 <46>[ 21.174909] systemd-journald[163]: Received client request to flush runtime journal.
896 20:53:28.750483 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
897 20:53:28.801244 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
898 20:53:29.630747 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
899 20:53:29.967593 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
900 20:53:30.027927 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
901 20:53:30.356961 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
902 20:53:30.580113 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
903 20:53:30.600116 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
904 20:53:30.627816 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
905 20:53:30.711633 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
906 20:53:30.763320 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
907 20:53:31.649600 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
908 20:53:31.714666 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
909 20:53:32.109862 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
910 20:53:32.242985 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
911 20:53:32.321501 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
912 20:53:34.417038 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
913 20:53:34.659316 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
914 20:53:34.789149 <5>[ 27.306421] cfg80211: Loading compiled-in X.509 certificates for regulatory database
915 20:53:35.540975 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
916 20:53:36.309316 <5>[ 28.828771] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
917 20:53:36.342290 <5>[ 28.856680] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
918 20:53:36.348117 <4>[ 28.867074] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
919 20:53:36.356143 <6>[ 28.876226] cfg80211: failed to load regulatory.db
920 20:53:37.081997 <46>[ 29.590116] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
921 20:53:37.109332 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
922 20:53:37.263764 <46>[ 29.774023] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
923 20:53:37.451335 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
924 20:53:45.923454 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
925 20:53:45.948299 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
926 20:53:45.972538 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
927 20:53:46.005318 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
928 20:53:46.068292 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
929 20:53:46.119402 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
930 20:53:46.180761 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
931 20:53:46.222466 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
932 20:53:46.277851 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
933 20:53:46.311122 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
934 20:53:46.348509 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
935 20:53:46.373467 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
936 20:53:46.402745 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
937 20:53:46.449732 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
938 20:53:46.498890 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
939 20:53:46.520317 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
940 20:53:46.548340 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
941 20:53:46.574589 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
942 20:53:46.603058 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
943 20:53:46.628078 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
944 20:53:46.659806 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
945 20:53:46.676722 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
946 20:53:46.700553 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
947 20:53:46.777951 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
948 20:53:46.830098 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
949 20:53:46.926137 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
950 20:53:47.012262 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
951 20:53:47.079530 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
952 20:53:47.113703 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
953 20:53:47.127177 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
954 20:53:47.376113 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
955 20:53:47.389907 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
956 20:53:47.508652 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
957 20:53:47.570682 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
958 20:53:47.597799 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
959 20:53:47.715065 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
960 20:53:48.068293 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
961 20:53:48.117097 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
962 20:53:48.142748 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
963 20:53:48.221797 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
964 20:53:48.398114 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
965 20:53:48.528815
966 20:53:48.533224 Debian GNU/Linux 12 debian-bookwworm-armhf login: root (automatic login)
967 20:53:48.533769
968 20:53:48.824703 Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Thu Nov 7 20:15:18 UTC 2024 armv7l
969 20:53:48.825295
970 20:53:48.830650 The programs included with the Debian GNU/Linux system are free software;
971 20:53:48.833868 the exact distribution terms for each program are described in the
972 20:53:48.839473 individual files in /usr/share/doc/*/copyright.
973 20:53:48.840015
974 20:53:48.845742 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
975 20:53:48.849692 permitted by applicable law.
976 20:53:53.460042 Unable to match end of the kernel message
978 20:53:53.461783 Setting prompt string to ['/ #']
979 20:53:53.462483 end: 2.4.4.1 login-action (duration 00:00:46) [common]
981 20:53:53.464030 end: 2.4.4 auto-login-action (duration 00:00:47) [common]
982 20:53:53.464664 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
983 20:53:53.465217 Setting prompt string to ['/ #']
984 20:53:53.465851 Forcing a shell prompt, looking for ['/ #']
986 20:53:53.516984 / #
987 20:53:53.517678 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
988 20:53:53.518301 Waiting using forced prompt support (timeout 00:02:30)
989 20:53:53.521609
990 20:53:53.529096 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
991 20:53:53.529740 start: 2.4.6 export-device-env (timeout 00:03:11) [common]
992 20:53:53.530323 Sending with 10 millisecond of delay
994 20:53:58.519294 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/955456/extract-nfsrootfs-svlvjh47'
995 20:53:58.530325 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/955456/extract-nfsrootfs-svlvjh47'
996 20:53:58.531992 Sending with 10 millisecond of delay
998 20:54:00.630126 / # export NFS_SERVER_IP='192.168.6.3'
999 20:54:00.641134 export NFS_SERVER_IP='192.168.6.3'
1000 20:54:00.642127 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1001 20:54:00.642783 end: 2.4 uboot-commands (duration 00:01:56) [common]
1002 20:54:00.643422 end: 2 uboot-action (duration 00:01:56) [common]
1003 20:54:00.644047 start: 3 lava-test-retry (timeout 00:06:53) [common]
1004 20:54:00.644690 start: 3.1 lava-test-shell (timeout 00:06:53) [common]
1005 20:54:00.645212 Using namespace: common
1007 20:54:00.746515 / # #
1008 20:54:00.747185 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1009 20:54:00.750880 #
1010 20:54:00.757977 Using /lava-955456
1012 20:54:00.859211 / # export SHELL=/bin/bash
1013 20:54:00.863541 export SHELL=/bin/bash
1015 20:54:00.971188 / # . /lava-955456/environment
1016 20:54:00.975813 . /lava-955456/environment
1018 20:54:01.089452 / # /lava-955456/bin/lava-test-runner /lava-955456/0
1019 20:54:01.090563 Test shell timeout: 10s (minimum of the action and connection timeout)
1020 20:54:01.094292 /lava-955456/bin/lava-test-runner /lava-955456/0
1021 20:54:01.480608 + export TESTRUN_ID=0_timesync-off
1022 20:54:01.488685 + TESTRUN_ID=0_timesync-off
1023 20:54:01.489317 + cd /lava-955456/0/tests/0_timesync-off
1024 20:54:01.489887 ++ cat uuid
1025 20:54:01.504879 + UUID=955456_1.6.2.4.1
1026 20:54:01.505508 + set +x
1027 20:54:01.513528 <LAVA_SIGNAL_STARTRUN 0_timesync-off 955456_1.6.2.4.1>
1028 20:54:01.514176 + systemctl stop systemd-timesyncd
1029 20:54:01.515016 Received signal: <STARTRUN> 0_timesync-off 955456_1.6.2.4.1
1030 20:54:01.515617 Starting test lava.0_timesync-off (955456_1.6.2.4.1)
1031 20:54:01.516250 Skipping test definition patterns.
1032 20:54:01.799186 + set +x
1033 20:54:01.799865 <LAVA_SIGNAL_ENDRUN 0_timesync-off 955456_1.6.2.4.1>
1034 20:54:01.800626 Received signal: <ENDRUN> 0_timesync-off 955456_1.6.2.4.1
1035 20:54:01.801194 Ending use of test pattern.
1036 20:54:01.801663 Ending test lava.0_timesync-off (955456_1.6.2.4.1), duration 0.29
1038 20:54:01.963218 + export TESTRUN_ID=1_kselftest-dt
1039 20:54:01.971182 + TESTRUN_ID=1_kselftest-dt
1040 20:54:01.971774 + cd /lava-955456/0/tests/1_kselftest-dt
1041 20:54:01.972287 ++ cat uuid
1042 20:54:01.987453 + UUID=955456_1.6.2.4.5
1043 20:54:01.988054 + set +x
1044 20:54:01.992978 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 955456_1.6.2.4.5>
1045 20:54:01.993558 + cd ./automated/linux/kselftest/
1046 20:54:01.994356 Received signal: <STARTRUN> 1_kselftest-dt 955456_1.6.2.4.5
1047 20:54:01.994843 Starting test lava.1_kselftest-dt (955456_1.6.2.4.5)
1048 20:54:01.995456 Skipping test definition patterns.
1049 20:54:02.022916 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1050 20:54:02.169584 INFO: install_deps skipped
1051 20:54:02.808473 --2024-11-07 20:54:02-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1052 20:54:03.077098 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1053 20:54:03.222046 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1054 20:54:03.368489 HTTP request sent, awaiting response... 200 OK
1055 20:54:03.368873 Length: 4099068 (3.9M) [application/octet-stream]
1056 20:54:03.374068 Saving to: 'kselftest_armhf.tar.gz'
1057 20:54:03.374628
1058 20:54:05.436414
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 175KB/s
kselftest_armhf.tar 5%[> ] 216.29K 379KB/s
kselftest_armhf.tar 19%[==> ] 777.39K 778KB/s
kselftest_armhf.tar 53%[=========> ] 2.09M 1.63MB/s
kselftest_armhf.tar 66%[============> ] 2.62M 1.76MB/s
kselftest_armhf.tar 76%[==============> ] 3.00M 1.75MB/s
kselftest_armhf.tar 84%[===============> ] 3.32M 1.72MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 1.90MB/s in 2.1s
1059 20:54:05.437148
1060 20:54:06.057050 2024-11-07 20:54:05 (1.90 MB/s) - 'kselftest_armhf.tar.gz' saved [4099068/4099068]
1061 20:54:06.057706
1062 20:54:20.321877 skiplist:
1063 20:54:20.322298 ========================================
1064 20:54:20.327505 ========================================
1065 20:54:20.427548 dt:test_unprobed_devices.sh
1066 20:54:20.463023 ============== Tests to run ===============
1067 20:54:20.470810 dt:test_unprobed_devices.sh
1068 20:54:20.474751 ===========End Tests to run ===============
1069 20:54:20.485422 shardfile-dt pass
1070 20:54:20.718405 <12>[ 73.240604] kselftest: Running tests in dt
1071 20:54:20.745913 TAP version 13
1072 20:54:20.769835 1..1
1073 20:54:20.822997 # timeout set to 45
1074 20:54:20.823501 # selftests: dt: test_unprobed_devices.sh
1075 20:54:21.563940 # TAP version 13
1076 20:54:46.535684 # 1..257
1077 20:54:46.707904 # ok 1 / # SKIP
1078 20:54:46.730111 # ok 2 /clk_mcasp0
1079 20:54:46.804866 # ok 3 /clk_mcasp0_fixed # SKIP
1080 20:54:46.869050 # ok 4 /cpus/cpu@0 # SKIP
1081 20:54:46.940092 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1082 20:54:46.964355 # ok 6 /fixedregulator0
1083 20:54:46.984491 # ok 7 /leds
1084 20:54:47.000636 # ok 8 /ocp
1085 20:54:47.025112 # ok 9 /ocp/interconnect@44c00000
1086 20:54:47.050141 # ok 10 /ocp/interconnect@44c00000/segment@0
1087 20:54:47.071574 # ok 11 /ocp/interconnect@44c00000/segment@100000
1088 20:54:47.095777 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1089 20:54:47.171246 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1090 20:54:47.190624 # ok 14 /ocp/interconnect@44c00000/segment@200000
1091 20:54:47.211490 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1092 20:54:47.315159 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1093 20:54:47.385903 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1094 20:54:47.457225 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1095 20:54:47.528183 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1096 20:54:47.599235 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1097 20:54:47.670086 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1098 20:54:47.741142 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1099 20:54:47.812533 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1100 20:54:47.884862 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1101 20:54:47.955752 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1102 20:54:48.030235 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1103 20:54:48.102197 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1104 20:54:48.173262 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1105 20:54:48.244717 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1106 20:54:48.310785 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1107 20:54:48.383023 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1108 20:54:48.454645 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1109 20:54:48.524473 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1110 20:54:48.599530 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1111 20:54:48.667205 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1112 20:54:48.738136 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1113 20:54:48.809862 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1114 20:54:48.881505 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1115 20:54:48.952675 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1116 20:54:49.024411 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1117 20:54:49.099482 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1118 20:54:49.172395 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1119 20:54:49.244162 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1120 20:54:49.315798 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1121 20:54:49.385231 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1122 20:54:49.456820 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1123 20:54:49.532016 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1124 20:54:49.603678 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1125 20:54:49.675714 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1126 20:54:49.743435 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1127 20:54:49.815335 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1128 20:54:49.890985 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1129 20:54:49.962950 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1130 20:54:50.035579 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1131 20:54:50.105492 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1132 20:54:50.173916 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1133 20:54:50.245050 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1134 20:54:50.315877 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1135 20:54:50.387313 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1136 20:54:50.459461 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1137 20:54:50.530878 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1138 20:54:50.602137 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1139 20:54:50.673890 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1140 20:54:50.750486 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1141 20:54:50.820752 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1142 20:54:50.893504 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1143 20:54:50.965743 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1144 20:54:51.033309 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1145 20:54:51.104377 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1146 20:54:51.180884 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1147 20:54:51.252847 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1148 20:54:51.325221 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1149 20:54:51.395328 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1150 20:54:51.470973 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1151 20:54:51.542244 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1152 20:54:51.613653 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1153 20:54:51.685531 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1154 20:54:51.752443 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1155 20:54:51.824377 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1156 20:54:51.900539 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1157 20:54:51.973124 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1158 20:54:52.040039 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1159 20:54:52.110257 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1160 20:54:52.181384 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1161 20:54:52.252702 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1162 20:54:52.323973 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1163 20:54:52.399830 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1164 20:54:52.467724 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1165 20:54:52.546526 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1166 20:54:52.614586 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1167 20:54:52.684456 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1168 20:54:52.756059 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1169 20:54:52.829366 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1170 20:54:52.901665 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1171 20:54:52.922161 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1172 20:54:52.946222 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1173 20:54:52.970117 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1174 20:54:52.993890 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1175 20:54:53.017627 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1176 20:54:53.041433 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1177 20:54:53.065545 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1178 20:54:53.087548 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1179 20:54:53.191463 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1180 20:54:53.216491 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1181 20:54:53.240267 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1182 20:54:53.266087 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1183 20:54:53.373484 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1184 20:54:53.446545 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1185 20:54:53.514629 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1186 20:54:53.587587 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1187 20:54:53.659720 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1188 20:54:53.731994 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1189 20:54:53.803404 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1190 20:54:53.874942 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1191 20:54:53.947146 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1192 20:54:54.019261 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1193 20:54:54.090795 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1194 20:54:54.162314 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1195 20:54:54.232514 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1196 20:54:54.306246 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1197 20:54:54.383420 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1198 20:54:54.454824 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1199 20:54:54.480868 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1200 20:54:54.551902 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1201 20:54:54.620563 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1202 20:54:54.692916 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1203 20:54:54.713752 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1204 20:54:54.781185 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1205 20:54:54.805130 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1206 20:54:54.876330 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1207 20:54:54.901876 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1208 20:54:54.923363 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1209 20:54:54.946102 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1210 20:54:54.970330 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1211 20:54:54.997616 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1212 20:54:55.022459 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1213 20:54:55.044153 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1214 20:54:55.117269 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1215 20:54:55.143552 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1216 20:54:55.167826 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1217 20:54:55.235297 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1218 20:54:55.310923 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1219 20:54:55.331926 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1220 20:54:55.427596 # not ok 144 /ocp/interconnect@47c00000
1221 20:54:55.499194 # not ok 145 /ocp/interconnect@47c00000/segment@0
1222 20:54:55.524792 # ok 146 /ocp/interconnect@48000000
1223 20:54:55.547958 # ok 147 /ocp/interconnect@48000000/segment@0
1224 20:54:55.568453 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1225 20:54:55.596636 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1226 20:54:55.619779 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1227 20:54:55.641853 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1228 20:54:55.662399 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1229 20:54:55.686530 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1230 20:54:55.708927 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1231 20:54:55.782578 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1232 20:54:55.854105 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1233 20:54:55.880194 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1234 20:54:55.902419 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1235 20:54:55.922495 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1236 20:54:55.946820 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1237 20:54:55.971718 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1238 20:54:55.994297 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1239 20:54:56.016612 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1240 20:54:56.040658 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1241 20:54:56.063470 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1242 20:54:56.091815 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1243 20:54:56.111763 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1244 20:54:56.138409 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1245 20:54:56.161647 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1246 20:54:56.182199 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1247 20:54:56.208252 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1248 20:54:56.232468 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1249 20:54:56.251653 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1250 20:54:56.279561 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1251 20:54:56.300142 # ok 175 /ocp/interconnect@48000000/segment@100000
1252 20:54:56.320502 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1253 20:54:56.349042 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1254 20:54:56.421833 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1255 20:54:56.495046 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1256 20:54:56.564180 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1257 20:54:56.634654 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1258 20:54:56.706717 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1259 20:54:56.775844 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1260 20:54:56.847071 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1261 20:54:56.919932 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1262 20:54:56.939408 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1263 20:54:56.962598 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1264 20:54:56.986120 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1265 20:54:57.011884 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1266 20:54:57.032676 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1267 20:54:57.057173 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1268 20:54:57.079393 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1269 20:54:57.108676 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1270 20:54:57.131506 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1271 20:54:57.152002 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1272 20:54:57.175234 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1273 20:54:57.202461 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1274 20:54:57.224783 # ok 198 /ocp/interconnect@48000000/segment@200000
1275 20:54:57.249540 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1276 20:54:57.322311 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1277 20:54:57.340217 # ok 201 /ocp/interconnect@48000000/segment@300000
1278 20:54:57.368201 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1279 20:54:57.391578 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1280 20:54:57.412546 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1281 20:54:57.438762 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1282 20:54:57.461787 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1283 20:54:57.485451 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1284 20:54:57.551991 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1285 20:54:57.570456 # ok 209 /ocp/interconnect@4a000000
1286 20:54:57.598832 # ok 210 /ocp/interconnect@4a000000/segment@0
1287 20:54:57.621559 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1288 20:54:57.648423 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1289 20:54:57.673302 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1290 20:54:57.690713 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1291 20:54:57.762370 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1292 20:54:57.866979 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1293 20:54:57.938944 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1294 20:54:58.041281 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1295 20:54:58.111154 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1296 20:54:58.181188 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1297 20:54:58.279660 # not ok 221 /ocp/interconnect@4b140000
1298 20:54:58.350705 # not ok 222 /ocp/interconnect@4b140000/segment@0
1299 20:54:58.426124 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1300 20:54:58.443155 # ok 224 /ocp/target-module@40300000
1301 20:54:58.469591 # ok 225 /ocp/target-module@40300000/sram@0
1302 20:54:58.541216 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1303 20:54:58.616790 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1304 20:54:58.632244 # ok 228 /ocp/target-module@47400000
1305 20:54:58.656874 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1306 20:54:58.678934 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1307 20:54:58.701850 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1308 20:54:58.728240 # ok 232 /ocp/target-module@47400000/usb@1400
1309 20:54:58.749750 # ok 233 /ocp/target-module@47400000/usb@1800
1310 20:54:58.768066 # ok 234 /ocp/target-module@47810000
1311 20:54:58.790580 # ok 235 /ocp/target-module@49000000
1312 20:54:58.813582 # ok 236 /ocp/target-module@49000000/dma@0
1313 20:54:58.839151 # ok 237 /ocp/target-module@49800000
1314 20:54:58.865168 # ok 238 /ocp/target-module@49800000/dma@0
1315 20:54:58.880878 # ok 239 /ocp/target-module@49900000
1316 20:54:58.904351 # ok 240 /ocp/target-module@49900000/dma@0
1317 20:54:58.928944 # ok 241 /ocp/target-module@49a00000
1318 20:54:58.952181 # ok 242 /ocp/target-module@49a00000/dma@0
1319 20:54:58.971977 # ok 243 /ocp/target-module@4c000000
1320 20:54:59.044269 # not ok 244 /ocp/target-module@4c000000/emif@0
1321 20:54:59.068765 # ok 245 /ocp/target-module@50000000
1322 20:54:59.088883 # ok 246 /ocp/target-module@53100000
1323 20:54:59.158868 # not ok 247 /ocp/target-module@53100000/sham@0
1324 20:54:59.180785 # ok 248 /ocp/target-module@53500000
1325 20:54:59.256537 # not ok 249 /ocp/target-module@53500000/aes@0
1326 20:54:59.277894 # ok 250 /ocp/target-module@56000000
1327 20:54:59.377736 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1328 20:54:59.448172 # ok 252 /opp-table # SKIP
1329 20:54:59.517971 # ok 253 /soc # SKIP
1330 20:54:59.543454 # ok 254 /sound
1331 20:54:59.562071 # ok 255 /target-module@4b000000
1332 20:54:59.590531 # ok 256 /target-module@4b000000/target-module@140000
1333 20:54:59.608626 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1334 20:54:59.617235 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1335 20:54:59.625240 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1336 20:55:01.795912 dt_test_unprobed_devices_sh_ skip
1337 20:55:01.801412 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1338 20:55:01.806992 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1339 20:55:01.807492 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1340 20:55:01.815956 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1341 20:55:01.816393 dt_test_unprobed_devices_sh_fixedregulator0 pass
1342 20:55:01.821392 dt_test_unprobed_devices_sh_leds pass
1343 20:55:01.827056 dt_test_unprobed_devices_sh_ocp pass
1344 20:55:01.830660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1345 20:55:01.836098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1346 20:55:01.841651 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1347 20:55:01.852975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1348 20:55:01.858616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1349 20:55:01.864072 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1350 20:55:01.875207 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1351 20:55:01.880911 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1352 20:55:01.892093 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1353 20:55:01.903354 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1354 20:55:01.908956 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1355 20:55:01.920091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1356 20:55:01.931276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1357 20:55:01.942525 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1358 20:55:01.953716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1359 20:55:01.959284 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1360 20:55:01.970452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1361 20:55:01.981732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1362 20:55:01.992835 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1363 20:55:02.004024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1364 20:55:02.009668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1365 20:55:02.020797 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1366 20:55:02.032008 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1367 20:55:02.043244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1368 20:55:02.048842 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1369 20:55:02.060005 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1370 20:55:02.071208 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1371 20:55:02.082382 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1372 20:55:02.087993 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1373 20:55:02.099188 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1374 20:55:02.110429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1375 20:55:02.121695 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1376 20:55:02.132962 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1377 20:55:02.144125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1378 20:55:02.155270 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1379 20:55:02.166461 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1380 20:55:02.177672 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1381 20:55:02.188903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1382 20:55:02.200005 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1383 20:55:02.211247 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1384 20:55:02.222406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1385 20:55:02.233641 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1386 20:55:02.244879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1387 20:55:02.256024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1388 20:55:02.267213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1389 20:55:02.278445 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1390 20:55:02.289724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1391 20:55:02.300978 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1392 20:55:02.312102 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1393 20:55:02.323320 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1394 20:55:02.334531 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1395 20:55:02.345778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1396 20:55:02.356972 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1397 20:55:02.368165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1398 20:55:02.373833 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1399 20:55:02.384968 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1400 20:55:02.396161 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1401 20:55:02.407358 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1402 20:55:02.418538 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1403 20:55:02.429742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1404 20:55:02.441007 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1405 20:55:02.452186 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1406 20:55:02.463421 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1407 20:55:02.474785 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1408 20:55:02.485725 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1409 20:55:02.496940 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1410 20:55:02.508086 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1411 20:55:02.519256 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1412 20:55:02.530517 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1413 20:55:02.541637 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1414 20:55:02.552883 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1415 20:55:02.564046 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1416 20:55:02.569664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1417 20:55:02.580829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1418 20:55:02.592165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1419 20:55:02.603328 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1420 20:55:02.614537 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1421 20:55:02.625733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1422 20:55:02.631321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1423 20:55:02.642518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1424 20:55:02.653626 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1425 20:55:02.664777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1426 20:55:02.675947 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1427 20:55:02.687146 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1428 20:55:02.698327 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1429 20:55:02.715120 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1430 20:55:02.720735 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1431 20:55:02.731903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1432 20:55:02.743080 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1433 20:55:02.748699 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1434 20:55:02.759881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1435 20:55:02.771095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1436 20:55:02.776705 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1437 20:55:02.787870 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1438 20:55:02.793487 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1439 20:55:02.804660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1440 20:55:02.815853 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1441 20:55:02.827099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1442 20:55:02.832656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1443 20:55:02.843870 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1444 20:55:02.860640 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1445 20:55:02.871821 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1446 20:55:02.883086 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1447 20:55:02.894283 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1448 20:55:02.905472 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1449 20:55:02.916658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1450 20:55:02.927848 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1451 20:55:02.939046 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1452 20:55:02.955858 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1453 20:55:02.967039 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1454 20:55:02.978352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1455 20:55:02.989530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1456 20:55:03.006316 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1457 20:55:03.017511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1458 20:55:03.028758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1459 20:55:03.039893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1460 20:55:03.045498 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1461 20:55:03.056755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1462 20:55:03.062289 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1463 20:55:03.073486 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1464 20:55:03.079078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1465 20:55:03.090246 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1466 20:55:03.095868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1467 20:55:03.107055 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1468 20:55:03.112652 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1469 20:55:03.123825 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1470 20:55:03.135038 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1471 20:55:03.140633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1472 20:55:03.151822 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1473 20:55:03.162997 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1474 20:55:03.174216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1475 20:55:03.185398 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1476 20:55:03.191021 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1477 20:55:03.202175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1478 20:55:03.213395 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1479 20:55:03.219010 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1480 20:55:03.224596 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1481 20:55:03.230182 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1482 20:55:03.235819 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1483 20:55:03.241389 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1484 20:55:03.246977 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1485 20:55:03.258166 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1486 20:55:03.263767 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1487 20:55:03.274938 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1488 20:55:03.280558 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1489 20:55:03.291777 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1490 20:55:03.297345 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1491 20:55:03.308504 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1492 20:55:03.314118 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1493 20:55:03.325198 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1494 20:55:03.330794 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1495 20:55:03.336399 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1496 20:55:03.347573 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1497 20:55:03.353301 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1498 20:55:03.364505 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1499 20:55:03.370097 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1500 20:55:03.381277 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1501 20:55:03.386869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1502 20:55:03.398086 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1503 20:55:03.403673 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1504 20:55:03.414857 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1505 20:55:03.420458 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1506 20:55:03.426049 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1507 20:55:03.437225 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1508 20:55:03.442860 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1509 20:55:03.454051 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1510 20:55:03.459570 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1511 20:55:03.470837 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1512 20:55:03.476400 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1513 20:55:03.487624 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1514 20:55:03.498788 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1515 20:55:03.510031 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1516 20:55:03.521191 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1517 20:55:03.532404 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1518 20:55:03.543562 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1519 20:55:03.554823 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1520 20:55:03.565982 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1521 20:55:03.571561 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1522 20:55:03.582815 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1523 20:55:03.588357 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1524 20:55:03.599554 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1525 20:55:03.605123 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1526 20:55:03.616338 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1527 20:55:03.621969 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1528 20:55:03.633139 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1529 20:55:03.638751 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1530 20:55:03.649927 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1531 20:55:03.655530 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1532 20:55:03.666720 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1533 20:55:03.672333 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1534 20:55:03.677899 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1535 20:55:03.689098 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1536 20:55:03.694722 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1537 20:55:03.705916 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1538 20:55:03.711489 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1539 20:55:03.722672 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1540 20:55:03.728286 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1541 20:55:03.739479 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1542 20:55:03.745054 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1543 20:55:03.756239 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1544 20:55:03.761860 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1545 20:55:03.767438 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1546 20:55:03.773025 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1547 20:55:03.784217 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1548 20:55:03.789865 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1549 20:55:03.801009 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1550 20:55:03.806614 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1551 20:55:03.817901 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1552 20:55:03.828944 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1553 20:55:03.840160 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1554 20:55:03.845806 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1555 20:55:03.856891 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1556 20:55:03.862501 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1557 20:55:03.868133 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1558 20:55:03.873742 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1559 20:55:03.879317 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1560 20:55:03.884915 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1561 20:55:03.896115 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1562 20:55:03.901740 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1563 20:55:03.907350 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1564 20:55:03.912948 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1565 20:55:03.918535 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1566 20:55:03.924121 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1567 20:55:03.929735 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1568 20:55:03.940970 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1569 20:55:03.946573 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1570 20:55:03.947061 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1571 20:55:03.957836 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1572 20:55:03.958392 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1573 20:55:03.968994 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1574 20:55:03.969502 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1575 20:55:03.980193 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1576 20:55:03.980805 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1577 20:55:03.991398 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1578 20:55:03.991983 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1579 20:55:04.002631 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1580 20:55:04.008212 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1581 20:55:04.008713 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1582 20:55:04.019423 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1583 20:55:04.020051 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1584 20:55:04.030681 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1585 20:55:04.031281 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1586 20:55:04.041896 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1587 20:55:04.042388 dt_test_unprobed_devices_sh_opp-table skip
1588 20:55:04.047493 dt_test_unprobed_devices_sh_soc skip
1589 20:55:04.047967 dt_test_unprobed_devices_sh_sound pass
1590 20:55:04.053312 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1591 20:55:04.064496 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1592 20:55:04.070112 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1593 20:55:04.070649 dt_test_unprobed_devices_sh fail
1594 20:55:04.075658 + ../../utils/send-to-lava.sh ./output/result.txt
1595 20:55:04.081267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1596 20:55:04.082174 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1598 20:55:04.089317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1599 20:55:04.090100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1601 20:55:04.179206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1602 20:55:04.180018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1604 20:55:04.271398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1605 20:55:04.272183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1607 20:55:04.364345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1608 20:55:04.365222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1610 20:55:04.457714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1611 20:55:04.458577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1613 20:55:04.547568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1614 20:55:04.548447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1616 20:55:04.638444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1617 20:55:04.639303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1619 20:55:04.729852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1620 20:55:04.730740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1622 20:55:04.824859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1623 20:55:04.825720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1625 20:55:04.916908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1626 20:55:04.917736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1628 20:55:05.009507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1629 20:55:05.010383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1631 20:55:05.103358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1632 20:55:05.104244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1634 20:55:05.196942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1635 20:55:05.197791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1637 20:55:05.287618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1638 20:55:05.288444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1640 20:55:05.380608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1641 20:55:05.381441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1643 20:55:05.473864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1644 20:55:05.474735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1646 20:55:05.567081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1647 20:55:05.567942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1649 20:55:05.661140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1650 20:55:05.661962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1652 20:55:05.752617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1653 20:55:05.753451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1655 20:55:05.845119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1656 20:55:05.845957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1658 20:55:05.939325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1659 20:55:05.940153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1661 20:55:06.032576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1662 20:55:06.033433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1664 20:55:06.122751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1665 20:55:06.123568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1667 20:55:06.214817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1668 20:55:06.215638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1670 20:55:06.315589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1671 20:55:06.316412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1673 20:55:06.410518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1674 20:55:06.411438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1676 20:55:06.503147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1677 20:55:06.504062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1679 20:55:06.596131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1680 20:55:06.597024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1682 20:55:06.697439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1683 20:55:06.698362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1685 20:55:06.797792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1686 20:55:06.798698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1688 20:55:06.891700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1689 20:55:06.892602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1691 20:55:06.985185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1692 20:55:06.985986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1694 20:55:07.079696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1695 20:55:07.080581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1697 20:55:07.171484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1698 20:55:07.172355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1700 20:55:07.264647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1701 20:55:07.265495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1703 20:55:07.356334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1704 20:55:07.357244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1706 20:55:07.450062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1707 20:55:07.450920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1709 20:55:07.543108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1710 20:55:07.544045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1712 20:55:07.635427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1713 20:55:07.636251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1715 20:55:07.732037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1716 20:55:07.732933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1718 20:55:07.823041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1719 20:55:07.823840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1721 20:55:07.917080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1722 20:55:07.917914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1724 20:55:08.008744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1725 20:55:08.009567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1727 20:55:08.101288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1728 20:55:08.102132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1730 20:55:08.193356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1731 20:55:08.194022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1733 20:55:08.284723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1734 20:55:08.285833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1736 20:55:08.379203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1737 20:55:08.380334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1739 20:55:08.471932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1740 20:55:08.473034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1742 20:55:08.564840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1743 20:55:08.565942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1745 20:55:08.658032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1746 20:55:08.659148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1748 20:55:08.751617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1749 20:55:08.752660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1751 20:55:08.845339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1752 20:55:08.846469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1754 20:55:08.939059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1755 20:55:08.940137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1757 20:55:09.033878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1758 20:55:09.035020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1760 20:55:09.125466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1761 20:55:09.126568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1763 20:55:09.220303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1764 20:55:09.221367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1766 20:55:09.314637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1767 20:55:09.315683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1769 20:55:09.413230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1770 20:55:09.414356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1772 20:55:09.515062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1773 20:55:09.516004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1775 20:55:09.614411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1776 20:55:09.615263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1778 20:55:09.717262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1779 20:55:09.718162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1781 20:55:09.820808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1782 20:55:09.821640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1784 20:55:09.922073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1785 20:55:09.922909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1787 20:55:10.018998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1788 20:55:10.019900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1790 20:55:10.120646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1791 20:55:10.121540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1793 20:55:10.214394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1794 20:55:10.215238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1796 20:55:10.307064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1797 20:55:10.307900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1799 20:55:10.398188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1800 20:55:10.399033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1802 20:55:10.490768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1803 20:55:10.491646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1805 20:55:10.584573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1806 20:55:10.585407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1808 20:55:10.677373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1809 20:55:10.678238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1811 20:55:10.771560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1812 20:55:10.772394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1814 20:55:10.864175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1815 20:55:10.864998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1817 20:55:10.955992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1818 20:55:10.956821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1820 20:55:11.050202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1821 20:55:11.051042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1823 20:55:11.143820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1824 20:55:11.144629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1826 20:55:11.236826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1827 20:55:11.237658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1829 20:55:11.329650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1830 20:55:11.330503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1832 20:55:11.423317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1833 20:55:11.424150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1835 20:55:11.515301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1836 20:55:11.516184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1838 20:55:11.607651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1839 20:55:11.608480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1841 20:55:11.701238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1842 20:55:11.702118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1844 20:55:11.793741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1845 20:55:11.794602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1847 20:55:11.887346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1848 20:55:11.888182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1850 20:55:11.981472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1851 20:55:11.982360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1853 20:55:12.075653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1854 20:55:12.076515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1856 20:55:12.177477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1857 20:55:12.178045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1859 20:55:12.278269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1860 20:55:12.279091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1862 20:55:12.373925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1863 20:55:12.374771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1865 20:55:12.466638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1866 20:55:12.467478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1868 20:55:12.558088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1869 20:55:12.558912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1871 20:55:12.662537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1872 20:55:12.663341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1874 20:55:12.763142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1875 20:55:12.763966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1877 20:55:12.864974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1878 20:55:12.865654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1880 20:55:12.952948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1881 20:55:12.953996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1883 20:55:13.045150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1884 20:55:13.046007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1886 20:55:13.138872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1887 20:55:13.139710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1889 20:55:13.232346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1890 20:55:13.233139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1892 20:55:13.321650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1893 20:55:13.322528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1895 20:55:13.413877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1896 20:55:13.414751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1898 20:55:13.505845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1899 20:55:13.506723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1901 20:55:13.600154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1902 20:55:13.600949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1904 20:55:13.691261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1905 20:55:13.692072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1907 20:55:13.783220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1908 20:55:13.784021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1910 20:55:13.884871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1911 20:55:13.885633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1913 20:55:13.985717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1914 20:55:13.986514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1916 20:55:14.078113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1917 20:55:14.078995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1919 20:55:14.169420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1920 20:55:14.170321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1922 20:55:14.262649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1923 20:55:14.263763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1925 20:55:14.354172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1926 20:55:14.355038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1928 20:55:14.445084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1929 20:55:14.445973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1931 20:55:14.537102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1932 20:55:14.537997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1934 20:55:14.631329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1935 20:55:14.632183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1937 20:55:14.723808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1938 20:55:14.724648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1940 20:55:14.815195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1941 20:55:14.816037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1943 20:55:14.907421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1944 20:55:14.908265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1946 20:55:14.999039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1947 20:55:14.999891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1949 20:55:15.090332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1950 20:55:15.091136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1952 20:55:15.181934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1953 20:55:15.182782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1955 20:55:15.274073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1957 20:55:15.277204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1958 20:55:15.367209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1960 20:55:15.370352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1961 20:55:15.460450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1963 20:55:15.463490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1964 20:55:15.558221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1965 20:55:15.559109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1967 20:55:15.650570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1968 20:55:15.651866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1970 20:55:15.740818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1971 20:55:15.741678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1973 20:55:15.831185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1974 20:55:15.832039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1976 20:55:15.917603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1977 20:55:15.918471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1979 20:55:16.010564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1980 20:55:16.011414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1982 20:55:16.101335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1983 20:55:16.102285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1985 20:55:16.194551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1986 20:55:16.195428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1988 20:55:16.287929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1989 20:55:16.288784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1991 20:55:16.380482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1992 20:55:16.381358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1994 20:55:16.470588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1995 20:55:16.471488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1997 20:55:16.564023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1998 20:55:16.564964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2000 20:55:16.656458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2001 20:55:16.657306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2003 20:55:16.750749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2004 20:55:16.751593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2006 20:55:16.845863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2007 20:55:16.846791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2009 20:55:16.940969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2010 20:55:16.941861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2012 20:55:17.033213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2013 20:55:17.033794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2015 20:55:17.125419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2016 20:55:17.126286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2018 20:55:17.221043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2019 20:55:17.221916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2021 20:55:17.313439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2022 20:55:17.314324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2024 20:55:17.404301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2025 20:55:17.405311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2027 20:55:17.493644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2028 20:55:17.494346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2030 20:55:17.588632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2031 20:55:17.589543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2033 20:55:17.682430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2034 20:55:17.683283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2036 20:55:17.776303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2037 20:55:17.777142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2039 20:55:17.870706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2040 20:55:17.871716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2042 20:55:17.960803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2043 20:55:17.961660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2045 20:55:18.054080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2046 20:55:18.055002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2048 20:55:18.147069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2049 20:55:18.147932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2051 20:55:18.240984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2052 20:55:18.241966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2054 20:55:18.333276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2055 20:55:18.334472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2057 20:55:18.425045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2058 20:55:18.425939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2060 20:55:18.517264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2061 20:55:18.517889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2063 20:55:18.610616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2064 20:55:18.611473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2066 20:55:18.700628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2067 20:55:18.701463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2069 20:55:18.787402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2070 20:55:18.788234 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2072 20:55:18.878028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2073 20:55:18.878857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2075 20:55:18.970766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2076 20:55:18.971604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2078 20:55:19.062331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2079 20:55:19.063258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2081 20:55:19.154558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2082 20:55:19.155422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2084 20:55:19.248677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2085 20:55:19.249525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2087 20:55:19.342025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2088 20:55:19.342894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2090 20:55:19.434054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2091 20:55:19.434911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2093 20:55:19.526828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2094 20:55:19.527437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2096 20:55:19.621490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2097 20:55:19.622360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2099 20:55:19.713961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2100 20:55:19.714822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2102 20:55:19.806704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2103 20:55:19.807566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2105 20:55:19.899818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2106 20:55:19.900740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2108 20:55:19.989419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2109 20:55:19.990283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2111 20:55:20.081572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2112 20:55:20.082531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2114 20:55:20.172178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2115 20:55:20.173159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2117 20:55:20.265427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2118 20:55:20.266334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2120 20:55:20.354323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2121 20:55:20.355198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2123 20:55:20.447905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2124 20:55:20.448547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2126 20:55:20.540304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2127 20:55:20.540924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2129 20:55:20.633726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2130 20:55:20.634614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2132 20:55:20.727068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2133 20:55:20.727952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2135 20:55:20.818118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2136 20:55:20.818959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2138 20:55:20.912079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2139 20:55:20.912911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2141 20:55:21.005405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2142 20:55:21.006271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2144 20:55:21.099257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2145 20:55:21.100149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2147 20:55:21.191108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2148 20:55:21.191951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2150 20:55:21.284336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2151 20:55:21.285225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2153 20:55:21.374079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2154 20:55:21.374969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2156 20:55:21.465994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2157 20:55:21.466634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2159 20:55:21.557596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2160 20:55:21.558515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2162 20:55:21.649968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2163 20:55:21.650792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2165 20:55:21.740318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2166 20:55:21.741125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2168 20:55:21.833628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2169 20:55:21.834463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2171 20:55:21.928653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2172 20:55:21.929470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2174 20:55:22.020970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2175 20:55:22.021878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2177 20:55:22.112663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2178 20:55:22.113393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2180 20:55:22.204487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2181 20:55:22.205254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2183 20:55:22.299494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2184 20:55:22.300324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2186 20:55:22.390852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2187 20:55:22.391677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2189 20:55:22.480154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2190 20:55:22.480813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2192 20:55:22.574455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2193 20:55:22.575348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2195 20:55:22.667629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2196 20:55:22.668447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2198 20:55:22.757961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2199 20:55:22.758783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2201 20:55:22.850669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2202 20:55:22.851474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2204 20:55:22.938153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2205 20:55:22.939931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2207 20:55:23.031761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2208 20:55:23.032448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2210 20:55:23.123121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2211 20:55:23.123969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2213 20:55:23.217140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2214 20:55:23.217955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2216 20:55:23.308785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2217 20:55:23.309657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2219 20:55:23.402890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2220 20:55:23.404732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2222 20:55:23.496328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2223 20:55:23.497407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2225 20:55:23.588489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2226 20:55:23.589040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2228 20:55:23.683054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2229 20:55:23.683925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2231 20:55:23.777234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2232 20:55:23.778122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2234 20:55:23.871499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2235 20:55:23.872410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2237 20:55:23.961217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2238 20:55:23.962147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2240 20:55:24.054041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2241 20:55:24.055148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2243 20:55:24.147173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2244 20:55:24.148092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2246 20:55:24.242561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2247 20:55:24.243474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2249 20:55:24.332852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2250 20:55:24.333731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2252 20:55:24.424812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2253 20:55:24.425695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2255 20:55:24.517449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2256 20:55:24.518370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2258 20:55:24.602628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2259 20:55:24.603501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2261 20:55:24.694163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2262 20:55:24.695009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2264 20:55:24.785861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2265 20:55:24.786694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2267 20:55:24.876605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2268 20:55:24.877436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2270 20:55:24.967220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2271 20:55:24.968048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2273 20:55:25.059930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2274 20:55:25.060788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2276 20:55:25.150303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2278 20:55:25.153469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2279 20:55:25.243072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2280 20:55:25.243917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2282 20:55:25.334432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2283 20:55:25.335278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2285 20:55:25.426736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2286 20:55:25.427626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2288 20:55:25.517592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2289 20:55:25.518466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2291 20:55:25.606053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2292 20:55:25.606898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2294 20:55:25.698319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2295 20:55:25.699188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2297 20:55:25.790268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2298 20:55:25.791132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2300 20:55:25.882534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2301 20:55:25.883372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2303 20:55:25.976254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2304 20:55:25.977104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2306 20:55:26.068554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2307 20:55:26.069479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2309 20:55:26.162240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2310 20:55:26.163167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2312 20:55:26.253602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2313 20:55:26.254568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2315 20:55:26.356043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2316 20:55:26.356951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2318 20:55:26.456454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2319 20:55:26.457352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2321 20:55:26.558195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2322 20:55:26.559103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2324 20:55:26.650959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2325 20:55:26.651654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2327 20:55:26.742672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2328 20:55:26.743602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2330 20:55:26.834222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2331 20:55:26.835086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2333 20:55:26.926767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2334 20:55:26.927597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2336 20:55:27.018751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2337 20:55:27.019592 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2339 20:55:27.110199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2340 20:55:27.111056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2342 20:55:27.204599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2343 20:55:27.205477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2345 20:55:27.296172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2346 20:55:27.296989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2348 20:55:27.389929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2349 20:55:27.390761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2351 20:55:27.480466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2352 20:55:27.481383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2354 20:55:27.573916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2355 20:55:27.574730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2357 20:55:27.666285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2358 20:55:27.667097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2360 20:55:27.758290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2361 20:55:27.759141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2363 20:55:27.851557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2364 20:55:27.852416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2366 20:55:27.943458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2367 20:55:27.944318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2369 20:55:28.042154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2370 20:55:28.042760 + set +x
2371 20:55:28.043486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2373 20:55:28.046424 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 955456_1.6.2.4.5>
2374 20:55:28.047204 Received signal: <ENDRUN> 1_kselftest-dt 955456_1.6.2.4.5
2375 20:55:28.047701 Ending use of test pattern.
2376 20:55:28.048150 Ending test lava.1_kselftest-dt (955456_1.6.2.4.5), duration 86.05
2378 20:55:28.055902 <LAVA_TEST_RUNNER EXIT>
2379 20:55:28.056667 ok: lava_test_shell seems to have completed
2380 20:55:28.071045 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2381 20:55:28.073147 end: 3.1 lava-test-shell (duration 00:01:27) [common]
2382 20:55:28.073778 end: 3 lava-test-retry (duration 00:01:27) [common]
2383 20:55:28.074432 start: 4 finalize (timeout 00:05:26) [common]
2384 20:55:28.075048 start: 4.1 power-off (timeout 00:00:30) [common]
2385 20:55:28.076115 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2386 20:55:28.112482 >> OK - accepted request
2387 20:55:28.114431 Returned 0 in 0 seconds
2388 20:55:28.215449 end: 4.1 power-off (duration 00:00:00) [common]
2390 20:55:28.217318 start: 4.2 read-feedback (timeout 00:05:26) [common]
2391 20:55:28.218587 Listened to connection for namespace 'common' for up to 1s
2392 20:55:28.219528 Listened to connection for namespace 'common' for up to 1s
2393 20:55:29.219329 Finalising connection for namespace 'common'
2394 20:55:29.220124 Disconnecting from shell: Finalise
2395 20:55:29.220707 / #
2396 20:55:29.321968 end: 4.2 read-feedback (duration 00:00:01) [common]
2397 20:55:29.322843 end: 4 finalize (duration 00:00:01) [common]
2398 20:55:29.323567 Cleaning after the job
2399 20:55:29.324236 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955456/tftp-deploy-lfqq7hzz/ramdisk
2400 20:55:29.334340 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955456/tftp-deploy-lfqq7hzz/kernel
2401 20:55:29.342743 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955456/tftp-deploy-lfqq7hzz/dtb
2402 20:55:29.344172 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955456/tftp-deploy-lfqq7hzz/nfsrootfs
2403 20:55:29.510704 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955456/tftp-deploy-lfqq7hzz/modules
2404 20:55:29.521210 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/955456
2405 20:55:32.576763 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/955456
2406 20:55:32.577427 Job finished correctly