Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:35:07.756264 lava-dispatcher, installed at version: 2024.01
2 20:35:07.757030 start: 0 validate
3 20:35:07.757512 Start time: 2024-11-07 20:35:07.757483+00:00 (UTC)
4 20:35:07.758040 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:35:07.758584 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 20:35:07.800886 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:35:07.801418 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 20:35:07.835061 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:35:07.836089 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:35:08.889497 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:35:08.889998 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 20:35:08.934877 validate duration: 1.18
14 20:35:08.936361 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:35:08.936710 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:35:08.937018 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:35:08.937970 Not decompressing ramdisk as can be used compressed.
18 20:35:08.938719 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 20:35:08.939174 saving as /var/lib/lava/dispatcher/tmp/955482/tftp-deploy-7l5_8f_g/ramdisk/rootfs.cpio.gz
20 20:35:08.939653 total size: 8181887 (7 MB)
21 20:35:08.980750 progress 0 % (0 MB)
22 20:35:08.993589 progress 5 % (0 MB)
23 20:35:09.005428 progress 10 % (0 MB)
24 20:35:09.017489 progress 15 % (1 MB)
25 20:35:09.026138 progress 20 % (1 MB)
26 20:35:09.032018 progress 25 % (1 MB)
27 20:35:09.037315 progress 30 % (2 MB)
28 20:35:09.043352 progress 35 % (2 MB)
29 20:35:09.048717 progress 40 % (3 MB)
30 20:35:09.054144 progress 45 % (3 MB)
31 20:35:09.059520 progress 50 % (3 MB)
32 20:35:09.065212 progress 55 % (4 MB)
33 20:35:09.070540 progress 60 % (4 MB)
34 20:35:09.076291 progress 65 % (5 MB)
35 20:35:09.081765 progress 70 % (5 MB)
36 20:35:09.087307 progress 75 % (5 MB)
37 20:35:09.092672 progress 80 % (6 MB)
38 20:35:09.098337 progress 85 % (6 MB)
39 20:35:09.103293 progress 90 % (7 MB)
40 20:35:09.108641 progress 95 % (7 MB)
41 20:35:09.113661 progress 100 % (7 MB)
42 20:35:09.114305 7 MB downloaded in 0.17 s (44.68 MB/s)
43 20:35:09.114902 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:35:09.115799 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:35:09.116173 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:35:09.116483 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:35:09.116996 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/kernel/Image
49 20:35:09.117296 saving as /var/lib/lava/dispatcher/tmp/955482/tftp-deploy-7l5_8f_g/kernel/Image
50 20:35:09.117545 total size: 45713920 (43 MB)
51 20:35:09.117787 No compression specified
52 20:35:09.156415 progress 0 % (0 MB)
53 20:35:09.184773 progress 5 % (2 MB)
54 20:35:09.213037 progress 10 % (4 MB)
55 20:35:09.240836 progress 15 % (6 MB)
56 20:35:09.268202 progress 20 % (8 MB)
57 20:35:09.295443 progress 25 % (10 MB)
58 20:35:09.323265 progress 30 % (13 MB)
59 20:35:09.351076 progress 35 % (15 MB)
60 20:35:09.379146 progress 40 % (17 MB)
61 20:35:09.405975 progress 45 % (19 MB)
62 20:35:09.433686 progress 50 % (21 MB)
63 20:35:09.460808 progress 55 % (24 MB)
64 20:35:09.488822 progress 60 % (26 MB)
65 20:35:09.516041 progress 65 % (28 MB)
66 20:35:09.544816 progress 70 % (30 MB)
67 20:35:09.572024 progress 75 % (32 MB)
68 20:35:09.599525 progress 80 % (34 MB)
69 20:35:09.629835 progress 85 % (37 MB)
70 20:35:09.657926 progress 90 % (39 MB)
71 20:35:09.685851 progress 95 % (41 MB)
72 20:35:09.713181 progress 100 % (43 MB)
73 20:35:09.713679 43 MB downloaded in 0.60 s (73.13 MB/s)
74 20:35:09.714153 end: 1.2.1 http-download (duration 00:00:01) [common]
76 20:35:09.714962 end: 1.2 download-retry (duration 00:00:01) [common]
77 20:35:09.715232 start: 1.3 download-retry (timeout 00:09:59) [common]
78 20:35:09.715491 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 20:35:09.715949 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 20:35:09.716241 saving as /var/lib/lava/dispatcher/tmp/955482/tftp-deploy-7l5_8f_g/dtb/meson-g12b-a311d-libretech-cc.dtb
81 20:35:09.716451 total size: 54703 (0 MB)
82 20:35:09.716662 No compression specified
83 20:35:09.758805 progress 59 % (0 MB)
84 20:35:09.759623 progress 100 % (0 MB)
85 20:35:09.760185 0 MB downloaded in 0.04 s (1.19 MB/s)
86 20:35:09.760647 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:35:09.761455 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:35:09.761713 start: 1.4 download-retry (timeout 00:09:59) [common]
90 20:35:09.761973 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 20:35:09.762421 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/modules.tar.xz
92 20:35:09.762655 saving as /var/lib/lava/dispatcher/tmp/955482/tftp-deploy-7l5_8f_g/modules/modules.tar
93 20:35:09.762859 total size: 11624536 (11 MB)
94 20:35:09.763068 Using unxz to decompress xz
95 20:35:09.804691 progress 0 % (0 MB)
96 20:35:09.869959 progress 5 % (0 MB)
97 20:35:09.945584 progress 10 % (1 MB)
98 20:35:10.043904 progress 15 % (1 MB)
99 20:35:10.134334 progress 20 % (2 MB)
100 20:35:10.214908 progress 25 % (2 MB)
101 20:35:10.290315 progress 30 % (3 MB)
102 20:35:10.368505 progress 35 % (3 MB)
103 20:35:10.441850 progress 40 % (4 MB)
104 20:35:10.517298 progress 45 % (5 MB)
105 20:35:10.602751 progress 50 % (5 MB)
106 20:35:10.685805 progress 55 % (6 MB)
107 20:35:10.768331 progress 60 % (6 MB)
108 20:35:10.848873 progress 65 % (7 MB)
109 20:35:10.929935 progress 70 % (7 MB)
110 20:35:11.011856 progress 75 % (8 MB)
111 20:35:11.091076 progress 80 % (8 MB)
112 20:35:11.171812 progress 85 % (9 MB)
113 20:35:11.254703 progress 90 % (10 MB)
114 20:35:11.331655 progress 95 % (10 MB)
115 20:35:11.405051 progress 100 % (11 MB)
116 20:35:11.419278 11 MB downloaded in 1.66 s (6.69 MB/s)
117 20:35:11.419866 end: 1.4.1 http-download (duration 00:00:02) [common]
119 20:35:11.421908 end: 1.4 download-retry (duration 00:00:02) [common]
120 20:35:11.422555 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 20:35:11.423197 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 20:35:11.423743 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:35:11.424418 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 20:35:11.425473 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg
125 20:35:11.426504 makedir: /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin
126 20:35:11.427216 makedir: /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/tests
127 20:35:11.427888 makedir: /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/results
128 20:35:11.428596 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-add-keys
129 20:35:11.429724 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-add-sources
130 20:35:11.430809 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-background-process-start
131 20:35:11.431898 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-background-process-stop
132 20:35:11.433188 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-common-functions
133 20:35:11.434253 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-echo-ipv4
134 20:35:11.435311 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-install-packages
135 20:35:11.436309 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-installed-packages
136 20:35:11.437516 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-os-build
137 20:35:11.438512 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-probe-channel
138 20:35:11.439464 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-probe-ip
139 20:35:11.440483 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-target-ip
140 20:35:11.441589 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-target-mac
141 20:35:11.442648 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-target-storage
142 20:35:11.443739 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-test-case
143 20:35:11.445042 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-test-event
144 20:35:11.446040 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-test-feedback
145 20:35:11.447177 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-test-raise
146 20:35:11.448289 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-test-reference
147 20:35:11.449440 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-test-runner
148 20:35:11.450483 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-test-set
149 20:35:11.451536 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-test-shell
150 20:35:11.452598 Updating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-install-packages (oe)
151 20:35:11.453622 Updating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/bin/lava-installed-packages (oe)
152 20:35:11.454606 Creating /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/environment
153 20:35:11.455480 LAVA metadata
154 20:35:11.456097 - LAVA_JOB_ID=955482
155 20:35:11.456535 - LAVA_DISPATCHER_IP=192.168.6.2
156 20:35:11.457212 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 20:35:11.459180 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 20:35:11.459838 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 20:35:11.460286 skipped lava-vland-overlay
160 20:35:11.460843 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 20:35:11.461391 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 20:35:11.461900 skipped lava-multinode-overlay
163 20:35:11.462388 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 20:35:11.462886 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 20:35:11.463354 Loading test definitions
166 20:35:11.463894 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 20:35:11.464233 Using /lava-955482 at stage 0
168 20:35:11.465476 uuid=955482_1.5.2.4.1 testdef=None
169 20:35:11.465785 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 20:35:11.466051 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 20:35:11.467970 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 20:35:11.468867 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 20:35:11.471324 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 20:35:11.472275 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 20:35:11.474497 runner path: /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/0/tests/0_dmesg test_uuid 955482_1.5.2.4.1
178 20:35:11.475059 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 20:35:11.475818 Creating lava-test-runner.conf files
181 20:35:11.476053 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/955482/lava-overlay-wjfwk1gg/lava-955482/0 for stage 0
182 20:35:11.476397 - 0_dmesg
183 20:35:11.476737 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 20:35:11.477007 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 20:35:11.501742 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 20:35:11.502193 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 20:35:11.502460 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 20:35:11.502728 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 20:35:11.502990 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 20:35:12.415418 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 20:35:12.415869 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 20:35:12.416169 extracting modules file /var/lib/lava/dispatcher/tmp/955482/tftp-deploy-7l5_8f_g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955482/extract-overlay-ramdisk-d9w2f9h1/ramdisk
193 20:35:13.720619 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 20:35:13.721080 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 20:35:13.721372 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955482/compress-overlay-ozcnd4s5/overlay-1.5.2.5.tar.gz to ramdisk
196 20:35:13.721601 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955482/compress-overlay-ozcnd4s5/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/955482/extract-overlay-ramdisk-d9w2f9h1/ramdisk
197 20:35:13.752985 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 20:35:13.753412 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 20:35:13.753727 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 20:35:13.753979 Converting downloaded kernel to a uImage
201 20:35:13.754314 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/955482/tftp-deploy-7l5_8f_g/kernel/Image /var/lib/lava/dispatcher/tmp/955482/tftp-deploy-7l5_8f_g/kernel/uImage
202 20:35:14.224275 output: Image Name:
203 20:35:14.224903 output: Created: Thu Nov 7 20:35:13 2024
204 20:35:14.225317 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 20:35:14.225722 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 20:35:14.226121 output: Load Address: 01080000
207 20:35:14.226513 output: Entry Point: 01080000
208 20:35:14.226902 output:
209 20:35:14.227487 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 20:35:14.228064 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 20:35:14.228355 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 20:35:14.228614 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 20:35:14.228871 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 20:35:14.229136 Building ramdisk /var/lib/lava/dispatcher/tmp/955482/extract-overlay-ramdisk-d9w2f9h1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/955482/extract-overlay-ramdisk-d9w2f9h1/ramdisk
215 20:35:16.623459 >> 181575 blocks
216 20:35:25.308909 Adding RAMdisk u-boot header.
217 20:35:25.309588 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/955482/extract-overlay-ramdisk-d9w2f9h1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/955482/extract-overlay-ramdisk-d9w2f9h1/ramdisk.cpio.gz.uboot
218 20:35:25.586639 output: Image Name:
219 20:35:25.587071 output: Created: Thu Nov 7 20:35:25 2024
220 20:35:25.587279 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 20:35:25.587486 output: Data Size: 26054233 Bytes = 25443.59 KiB = 24.85 MiB
222 20:35:25.587689 output: Load Address: 00000000
223 20:35:25.587891 output: Entry Point: 00000000
224 20:35:25.588248 output:
225 20:35:25.589396 rename /var/lib/lava/dispatcher/tmp/955482/extract-overlay-ramdisk-d9w2f9h1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/955482/tftp-deploy-7l5_8f_g/ramdisk/ramdisk.cpio.gz.uboot
226 20:35:25.590189 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 20:35:25.590783 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 20:35:25.591360 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 20:35:25.591859 No LXC device requested
230 20:35:25.592455 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 20:35:25.593017 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 20:35:25.593558 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 20:35:25.594009 Checking files for TFTP limit of 4294967296 bytes.
234 20:35:25.597009 end: 1 tftp-deploy (duration 00:00:17) [common]
235 20:35:25.597675 start: 2 uboot-action (timeout 00:05:00) [common]
236 20:35:25.598257 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 20:35:25.598807 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 20:35:25.599359 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 20:35:25.599956 Using kernel file from prepare-kernel: 955482/tftp-deploy-7l5_8f_g/kernel/uImage
240 20:35:25.600701 substitutions:
241 20:35:25.601162 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 20:35:25.601609 - {DTB_ADDR}: 0x01070000
243 20:35:25.602047 - {DTB}: 955482/tftp-deploy-7l5_8f_g/dtb/meson-g12b-a311d-libretech-cc.dtb
244 20:35:25.602490 - {INITRD}: 955482/tftp-deploy-7l5_8f_g/ramdisk/ramdisk.cpio.gz.uboot
245 20:35:25.602927 - {KERNEL_ADDR}: 0x01080000
246 20:35:25.603359 - {KERNEL}: 955482/tftp-deploy-7l5_8f_g/kernel/uImage
247 20:35:25.603796 - {LAVA_MAC}: None
248 20:35:25.604310 - {PRESEED_CONFIG}: None
249 20:35:25.604752 - {PRESEED_LOCAL}: None
250 20:35:25.605188 - {RAMDISK_ADDR}: 0x08000000
251 20:35:25.605613 - {RAMDISK}: 955482/tftp-deploy-7l5_8f_g/ramdisk/ramdisk.cpio.gz.uboot
252 20:35:25.606049 - {ROOT_PART}: None
253 20:35:25.606480 - {ROOT}: None
254 20:35:25.606912 - {SERVER_IP}: 192.168.6.2
255 20:35:25.607349 - {TEE_ADDR}: 0x83000000
256 20:35:25.607781 - {TEE}: None
257 20:35:25.608243 Parsed boot commands:
258 20:35:25.608665 - setenv autoload no
259 20:35:25.609095 - setenv initrd_high 0xffffffff
260 20:35:25.609523 - setenv fdt_high 0xffffffff
261 20:35:25.609948 - dhcp
262 20:35:25.610375 - setenv serverip 192.168.6.2
263 20:35:25.610805 - tftpboot 0x01080000 955482/tftp-deploy-7l5_8f_g/kernel/uImage
264 20:35:25.611235 - tftpboot 0x08000000 955482/tftp-deploy-7l5_8f_g/ramdisk/ramdisk.cpio.gz.uboot
265 20:35:25.611662 - tftpboot 0x01070000 955482/tftp-deploy-7l5_8f_g/dtb/meson-g12b-a311d-libretech-cc.dtb
266 20:35:25.612115 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 20:35:25.612562 - bootm 0x01080000 0x08000000 0x01070000
268 20:35:25.613128 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 20:35:25.614780 start: 2.3 connect-device (timeout 00:05:00) [common]
271 20:35:25.615273 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 20:35:25.630778 Setting prompt string to ['lava-test: # ']
273 20:35:25.632475 end: 2.3 connect-device (duration 00:00:00) [common]
274 20:35:25.633143 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 20:35:25.633735 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 20:35:25.634317 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 20:35:25.635600 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 20:35:25.674083 >> OK - accepted request
279 20:35:25.676238 Returned 0 in 0 seconds
280 20:35:25.777204 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 20:35:25.779005 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 20:35:25.779634 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 20:35:25.780241 Setting prompt string to ['Hit any key to stop autoboot']
285 20:35:25.780741 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 20:35:25.782477 Trying 192.168.56.21...
287 20:35:25.782990 Connected to conserv1.
288 20:35:25.783436 Escape character is '^]'.
289 20:35:25.783893
290 20:35:25.784394 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 20:35:25.784868
292 20:35:36.939637 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 20:35:36.940373 bl2_stage_init 0x01
294 20:35:36.940855 bl2_stage_init 0x81
295 20:35:36.945188 hw id: 0x0000 - pwm id 0x01
296 20:35:36.945697 bl2_stage_init 0xc1
297 20:35:36.946149 bl2_stage_init 0x02
298 20:35:36.946600
299 20:35:36.950883 L0:00000000
300 20:35:36.951360 L1:20000703
301 20:35:36.951794 L2:00008067
302 20:35:36.952260 L3:14000000
303 20:35:36.956468 B2:00402000
304 20:35:36.956931 B1:e0f83180
305 20:35:36.957361
306 20:35:36.957791 TE: 58124
307 20:35:36.958219
308 20:35:36.962217 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 20:35:36.962681
310 20:35:36.963115 Board ID = 1
311 20:35:36.967529 Set A53 clk to 24M
312 20:35:36.968022 Set A73 clk to 24M
313 20:35:36.968455 Set clk81 to 24M
314 20:35:36.973134 A53 clk: 1200 MHz
315 20:35:36.973589 A73 clk: 1200 MHz
316 20:35:36.974015 CLK81: 166.6M
317 20:35:36.974441 smccc: 00012a92
318 20:35:36.978719 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 20:35:36.984352 board id: 1
320 20:35:36.990217 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 20:35:37.000855 fw parse done
322 20:35:37.006859 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 20:35:37.049507 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 20:35:37.060359 PIEI prepare done
325 20:35:37.060830 fastboot data load
326 20:35:37.061263 fastboot data verify
327 20:35:37.066073 verify result: 266
328 20:35:37.071624 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 20:35:37.072141 LPDDR4 probe
330 20:35:37.072581 ddr clk to 1584MHz
331 20:35:37.079609 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 20:35:37.116861
333 20:35:37.117358 dmc_version 0001
334 20:35:37.123530 Check phy result
335 20:35:37.129387 INFO : End of CA training
336 20:35:37.129857 INFO : End of initialization
337 20:35:37.135014 INFO : Training has run successfully!
338 20:35:37.135469 Check phy result
339 20:35:37.140602 INFO : End of initialization
340 20:35:37.141071 INFO : End of read enable training
341 20:35:37.146203 INFO : End of fine write leveling
342 20:35:37.151787 INFO : End of Write leveling coarse delay
343 20:35:37.152282 INFO : Training has run successfully!
344 20:35:37.152716 Check phy result
345 20:35:37.157392 INFO : End of initialization
346 20:35:37.157853 INFO : End of read dq deskew training
347 20:35:37.163027 INFO : End of MPR read delay center optimization
348 20:35:37.168599 INFO : End of write delay center optimization
349 20:35:37.174203 INFO : End of read delay center optimization
350 20:35:37.174663 INFO : End of max read latency training
351 20:35:37.179787 INFO : Training has run successfully!
352 20:35:37.180289 1D training succeed
353 20:35:37.189022 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 20:35:37.236598 Check phy result
355 20:35:37.237074 INFO : End of initialization
356 20:35:37.258426 INFO : End of 2D read delay Voltage center optimization
357 20:35:37.278381 INFO : End of 2D read delay Voltage center optimization
358 20:35:37.330352 INFO : End of 2D write delay Voltage center optimization
359 20:35:37.379519 INFO : End of 2D write delay Voltage center optimization
360 20:35:37.385121 INFO : Training has run successfully!
361 20:35:37.385625
362 20:35:37.386068 channel==0
363 20:35:37.390675 RxClkDly_Margin_A0==88 ps 9
364 20:35:37.391154 TxDqDly_Margin_A0==98 ps 10
365 20:35:37.396273 RxClkDly_Margin_A1==88 ps 9
366 20:35:37.396745 TxDqDly_Margin_A1==98 ps 10
367 20:35:37.397188 TrainedVREFDQ_A0==74
368 20:35:37.401842 TrainedVREFDQ_A1==74
369 20:35:37.402317 VrefDac_Margin_A0==25
370 20:35:37.402765 DeviceVref_Margin_A0==40
371 20:35:37.407407 VrefDac_Margin_A1==25
372 20:35:37.407864 DeviceVref_Margin_A1==40
373 20:35:37.408331
374 20:35:37.408765
375 20:35:37.413040 channel==1
376 20:35:37.413502 RxClkDly_Margin_A0==88 ps 9
377 20:35:37.413937 TxDqDly_Margin_A0==98 ps 10
378 20:35:37.418708 RxClkDly_Margin_A1==98 ps 10
379 20:35:37.419233 TxDqDly_Margin_A1==88 ps 9
380 20:35:37.424266 TrainedVREFDQ_A0==77
381 20:35:37.424742 TrainedVREFDQ_A1==77
382 20:35:37.425180 VrefDac_Margin_A0==22
383 20:35:37.429885 DeviceVref_Margin_A0==37
384 20:35:37.430372 VrefDac_Margin_A1==22
385 20:35:37.435386 DeviceVref_Margin_A1==37
386 20:35:37.435855
387 20:35:37.436330 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 20:35:37.436763
389 20:35:37.469108 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 20:35:37.469730 2D training succeed
391 20:35:37.474705 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 20:35:37.480265 auto size-- 65535DDR cs0 size: 2048MB
393 20:35:37.480806 DDR cs1 size: 2048MB
394 20:35:37.485766 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 20:35:37.486259 cs0 DataBus test pass
396 20:35:37.491340 cs1 DataBus test pass
397 20:35:37.491807 cs0 AddrBus test pass
398 20:35:37.492288 cs1 AddrBus test pass
399 20:35:37.492720
400 20:35:37.496950 100bdlr_step_size ps== 420
401 20:35:37.497429 result report
402 20:35:37.502607 boot times 0Enable ddr reg access
403 20:35:37.507789 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 20:35:37.521440 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 20:35:38.093514 0.0;M3 CHK:0;cm4_sp_mode 0
406 20:35:38.094192 MVN_1=0x00000000
407 20:35:38.098879 MVN_2=0x00000000
408 20:35:38.104595 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 20:35:38.105075 OPS=0x10
410 20:35:38.105520 ring efuse init
411 20:35:38.105954 chipver efuse init
412 20:35:38.110301 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 20:35:38.115883 [0.018960 Inits done]
414 20:35:38.116429 secure task start!
415 20:35:38.116873 high task start!
416 20:35:38.120409 low task start!
417 20:35:38.120867 run into bl31
418 20:35:38.127030 NOTICE: BL31: v1.3(release):4fc40b1
419 20:35:38.134830 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 20:35:38.135308 NOTICE: BL31: G12A normal boot!
421 20:35:38.160201 NOTICE: BL31: BL33 decompress pass
422 20:35:38.165896 ERROR: Error initializing runtime service opteed_fast
423 20:35:39.398855
424 20:35:39.399518
425 20:35:39.407232 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 20:35:39.407852
427 20:35:39.408500 Model: Libre Computer AML-A311D-CC Alta
428 20:35:39.615725 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 20:35:39.639022 DRAM: 2 GiB (effective 3.8 GiB)
430 20:35:39.782032 Core: 408 devices, 31 uclasses, devicetree: separate
431 20:35:39.787878 WDT: Not starting watchdog@f0d0
432 20:35:39.820218 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 20:35:39.832594 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 20:35:39.837575 ** Bad device specification mmc 0 **
435 20:35:39.847909 Card did not respond to voltage select! : -110
436 20:35:39.855557 ** Bad device specification mmc 0 **
437 20:35:39.856071 Couldn't find partition mmc 0
438 20:35:39.863916 Card did not respond to voltage select! : -110
439 20:35:39.869430 ** Bad device specification mmc 0 **
440 20:35:39.869908 Couldn't find partition mmc 0
441 20:35:39.874701 Error: could not access storage.
442 20:35:41.140149 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 20:35:41.140826 bl2_stage_init 0x01
444 20:35:41.141320 bl2_stage_init 0x81
445 20:35:41.145680 hw id: 0x0000 - pwm id 0x01
446 20:35:41.146176 bl2_stage_init 0xc1
447 20:35:41.146627 bl2_stage_init 0x02
448 20:35:41.147075
449 20:35:41.151193 L0:00000000
450 20:35:41.151680 L1:20000703
451 20:35:41.152163 L2:00008067
452 20:35:41.152607 L3:14000000
453 20:35:41.156784 B2:00402000
454 20:35:41.157261 B1:e0f83180
455 20:35:41.157705
456 20:35:41.158147 TE: 58167
457 20:35:41.158591
458 20:35:41.162438 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 20:35:41.162939
460 20:35:41.163392 Board ID = 1
461 20:35:41.168015 Set A53 clk to 24M
462 20:35:41.168497 Set A73 clk to 24M
463 20:35:41.168940 Set clk81 to 24M
464 20:35:41.173722 A53 clk: 1200 MHz
465 20:35:41.174208 A73 clk: 1200 MHz
466 20:35:41.174653 CLK81: 166.6M
467 20:35:41.175090 smccc: 00012abe
468 20:35:41.179165 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 20:35:41.184806 board id: 1
470 20:35:41.190735 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 20:35:41.201400 fw parse done
472 20:35:41.207491 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 20:35:41.249981 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 20:35:41.260828 PIEI prepare done
475 20:35:41.261342 fastboot data load
476 20:35:41.261796 fastboot data verify
477 20:35:41.266432 verify result: 266
478 20:35:41.272061 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 20:35:41.272545 LPDDR4 probe
480 20:35:41.272993 ddr clk to 1584MHz
481 20:35:41.280068 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 20:35:41.317270
483 20:35:41.317812 dmc_version 0001
484 20:35:41.323924 Check phy result
485 20:35:41.329813 INFO : End of CA training
486 20:35:41.330289 INFO : End of initialization
487 20:35:41.335398 INFO : Training has run successfully!
488 20:35:41.335870 Check phy result
489 20:35:41.341016 INFO : End of initialization
490 20:35:41.341519 INFO : End of read enable training
491 20:35:41.346684 INFO : End of fine write leveling
492 20:35:41.352209 INFO : End of Write leveling coarse delay
493 20:35:41.352675 INFO : Training has run successfully!
494 20:35:41.353120 Check phy result
495 20:35:41.357793 INFO : End of initialization
496 20:35:41.358260 INFO : End of read dq deskew training
497 20:35:41.363428 INFO : End of MPR read delay center optimization
498 20:35:41.368981 INFO : End of write delay center optimization
499 20:35:41.374761 INFO : End of read delay center optimization
500 20:35:41.375250 INFO : End of max read latency training
501 20:35:41.380281 INFO : Training has run successfully!
502 20:35:41.380771 1D training succeed
503 20:35:41.389487 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 20:35:41.437148 Check phy result
505 20:35:41.437812 INFO : End of initialization
506 20:35:41.458944 INFO : End of 2D read delay Voltage center optimization
507 20:35:41.479125 INFO : End of 2D read delay Voltage center optimization
508 20:35:41.531189 INFO : End of 2D write delay Voltage center optimization
509 20:35:41.580575 INFO : End of 2D write delay Voltage center optimization
510 20:35:41.586090 INFO : Training has run successfully!
511 20:35:41.586645
512 20:35:41.587131 channel==0
513 20:35:41.591738 RxClkDly_Margin_A0==88 ps 9
514 20:35:41.592338 TxDqDly_Margin_A0==98 ps 10
515 20:35:41.597280 RxClkDly_Margin_A1==88 ps 9
516 20:35:41.597822 TxDqDly_Margin_A1==98 ps 10
517 20:35:41.598300 TrainedVREFDQ_A0==74
518 20:35:41.602910 TrainedVREFDQ_A1==74
519 20:35:41.603489 VrefDac_Margin_A0==25
520 20:35:41.603975 DeviceVref_Margin_A0==40
521 20:35:41.608480 VrefDac_Margin_A1==25
522 20:35:41.609046 DeviceVref_Margin_A1==40
523 20:35:41.609521
524 20:35:41.609989
525 20:35:41.614094 channel==1
526 20:35:41.614667 RxClkDly_Margin_A0==98 ps 10
527 20:35:41.615152 TxDqDly_Margin_A0==98 ps 10
528 20:35:41.619749 RxClkDly_Margin_A1==98 ps 10
529 20:35:41.620357 TxDqDly_Margin_A1==98 ps 10
530 20:35:41.625294 TrainedVREFDQ_A0==77
531 20:35:41.625842 TrainedVREFDQ_A1==77
532 20:35:41.626325 VrefDac_Margin_A0==22
533 20:35:41.630906 DeviceVref_Margin_A0==37
534 20:35:41.631447 VrefDac_Margin_A1==22
535 20:35:41.636440 DeviceVref_Margin_A1==37
536 20:35:41.636970
537 20:35:41.637436 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 20:35:41.642071
539 20:35:41.670066 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
540 20:35:41.670711 2D training succeed
541 20:35:41.675842 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 20:35:41.681273 auto size-- 65535DDR cs0 size: 2048MB
543 20:35:41.681851 DDR cs1 size: 2048MB
544 20:35:41.686856 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 20:35:41.687609 cs0 DataBus test pass
546 20:35:41.692475 cs1 DataBus test pass
547 20:35:41.693211 cs0 AddrBus test pass
548 20:35:41.693713 cs1 AddrBus test pass
549 20:35:41.694160
550 20:35:41.698085 100bdlr_step_size ps== 420
551 20:35:41.698651 result report
552 20:35:41.703625 boot times 0Enable ddr reg access
553 20:35:41.709174 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 20:35:41.722644 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 20:35:42.296559 0.0;M3 CHK:0;cm4_sp_mode 0
556 20:35:42.297686 MVN_1=0x00000000
557 20:35:42.302001 MVN_2=0x00000000
558 20:35:42.307771 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 20:35:42.309000 OPS=0x10
560 20:35:42.309956 ring efuse init
561 20:35:42.310961 chipver efuse init
562 20:35:42.313147 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 20:35:42.319034 [0.018961 Inits done]
564 20:35:42.320163 secure task start!
565 20:35:42.321012 high task start!
566 20:35:42.323344 low task start!
567 20:35:42.323879 run into bl31
568 20:35:42.329969 NOTICE: BL31: v1.3(release):4fc40b1
569 20:35:42.338004 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 20:35:42.338891 NOTICE: BL31: G12A normal boot!
571 20:35:42.363266 NOTICE: BL31: BL33 decompress pass
572 20:35:42.368773 ERROR: Error initializing runtime service opteed_fast
573 20:35:43.601842
574 20:35:43.602518
575 20:35:43.610368 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 20:35:43.610884
577 20:35:43.611350 Model: Libre Computer AML-A311D-CC Alta
578 20:35:43.818730 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 20:35:43.842180 DRAM: 2 GiB (effective 3.8 GiB)
580 20:35:43.984986 Core: 408 devices, 31 uclasses, devicetree: separate
581 20:35:43.990891 WDT: Not starting watchdog@f0d0
582 20:35:44.023185 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 20:35:44.035505 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 20:35:44.040492 ** Bad device specification mmc 0 **
585 20:35:44.050871 Card did not respond to voltage select! : -110
586 20:35:44.058571 ** Bad device specification mmc 0 **
587 20:35:44.059177 Couldn't find partition mmc 0
588 20:35:44.066866 Card did not respond to voltage select! : -110
589 20:35:44.072371 ** Bad device specification mmc 0 **
590 20:35:44.072884 Couldn't find partition mmc 0
591 20:35:44.077392 Error: could not access storage.
592 20:35:44.420090 Net: eth0: ethernet@ff3f0000
593 20:35:44.420753 starting USB...
594 20:35:44.671808 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 20:35:44.672479 Starting the controller
596 20:35:44.678798 USB XHCI 1.10
597 20:35:46.390277 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 20:35:46.390964 bl2_stage_init 0x01
599 20:35:46.391433 bl2_stage_init 0x81
600 20:35:46.395712 hw id: 0x0000 - pwm id 0x01
601 20:35:46.396266 bl2_stage_init 0xc1
602 20:35:46.396726 bl2_stage_init 0x02
603 20:35:46.397173
604 20:35:46.401281 L0:00000000
605 20:35:46.401794 L1:20000703
606 20:35:46.402248 L2:00008067
607 20:35:46.402693 L3:14000000
608 20:35:46.406825 B2:00402000
609 20:35:46.407332 B1:e0f83180
610 20:35:46.407779
611 20:35:46.408269 TE: 58167
612 20:35:46.408720
613 20:35:46.412645 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 20:35:46.413220
615 20:35:46.413702 Board ID = 1
616 20:35:46.418266 Set A53 clk to 24M
617 20:35:46.418891 Set A73 clk to 24M
618 20:35:46.419364 Set clk81 to 24M
619 20:35:46.423602 A53 clk: 1200 MHz
620 20:35:46.424155 A73 clk: 1200 MHz
621 20:35:46.424614 CLK81: 166.6M
622 20:35:46.425055 smccc: 00012abd
623 20:35:46.429234 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 20:35:46.434819 board id: 1
625 20:35:46.440886 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 20:35:46.451339 fw parse done
627 20:35:46.457301 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 20:35:46.501180 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 20:35:46.510824 PIEI prepare done
630 20:35:46.511396 fastboot data load
631 20:35:46.511868 fastboot data verify
632 20:35:46.516621 verify result: 266
633 20:35:46.522062 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 20:35:46.522586 LPDDR4 probe
635 20:35:46.523033 ddr clk to 1584MHz
636 20:35:46.530093 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 20:35:46.567393
638 20:35:46.568114 dmc_version 0001
639 20:35:46.573965 Check phy result
640 20:35:46.579922 INFO : End of CA training
641 20:35:46.580473 INFO : End of initialization
642 20:35:46.585514 INFO : Training has run successfully!
643 20:35:46.586023 Check phy result
644 20:35:46.591099 INFO : End of initialization
645 20:35:46.591669 INFO : End of read enable training
646 20:35:46.594330 INFO : End of fine write leveling
647 20:35:46.599927 INFO : End of Write leveling coarse delay
648 20:35:46.605582 INFO : Training has run successfully!
649 20:35:46.606096 Check phy result
650 20:35:46.606548 INFO : End of initialization
651 20:35:46.611115 INFO : End of read dq deskew training
652 20:35:46.616670 INFO : End of MPR read delay center optimization
653 20:35:46.617176 INFO : End of write delay center optimization
654 20:35:46.622310 INFO : End of read delay center optimization
655 20:35:46.627884 INFO : End of max read latency training
656 20:35:46.628528 INFO : Training has run successfully!
657 20:35:46.633599 1D training succeed
658 20:35:46.639539 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 20:35:46.687021 Check phy result
660 20:35:46.687572 INFO : End of initialization
661 20:35:46.708792 INFO : End of 2D read delay Voltage center optimization
662 20:35:46.728991 INFO : End of 2D read delay Voltage center optimization
663 20:35:46.781072 INFO : End of 2D write delay Voltage center optimization
664 20:35:46.830475 INFO : End of 2D write delay Voltage center optimization
665 20:35:46.835941 INFO : Training has run successfully!
666 20:35:46.836489
667 20:35:46.836949 channel==0
668 20:35:46.841658 RxClkDly_Margin_A0==88 ps 9
669 20:35:46.842163 TxDqDly_Margin_A0==98 ps 10
670 20:35:46.844887 RxClkDly_Margin_A1==88 ps 9
671 20:35:46.845382 TxDqDly_Margin_A1==98 ps 10
672 20:35:46.850502 TrainedVREFDQ_A0==74
673 20:35:46.851023 TrainedVREFDQ_A1==74
674 20:35:46.856102 VrefDac_Margin_A0==25
675 20:35:46.856633 DeviceVref_Margin_A0==40
676 20:35:46.857083 VrefDac_Margin_A1==25
677 20:35:46.861675 DeviceVref_Margin_A1==40
678 20:35:46.862174
679 20:35:46.862626
680 20:35:46.863071 channel==1
681 20:35:46.863512 RxClkDly_Margin_A0==88 ps 9
682 20:35:46.867263 TxDqDly_Margin_A0==98 ps 10
683 20:35:46.867772 RxClkDly_Margin_A1==98 ps 10
684 20:35:46.872841 TxDqDly_Margin_A1==98 ps 10
685 20:35:46.873353 TrainedVREFDQ_A0==77
686 20:35:46.873810 TrainedVREFDQ_A1==78
687 20:35:46.878427 VrefDac_Margin_A0==22
688 20:35:46.878927 DeviceVref_Margin_A0==37
689 20:35:46.884047 VrefDac_Margin_A1==24
690 20:35:46.884553 DeviceVref_Margin_A1==36
691 20:35:46.885006
692 20:35:46.889638 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 20:35:46.890155
694 20:35:46.917555 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000017 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
695 20:35:46.923158 2D training succeed
696 20:35:46.928770 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 20:35:46.929283 auto size-- 65535DDR cs0 size: 2048MB
698 20:35:46.934344 DDR cs1 size: 2048MB
699 20:35:46.934843 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 20:35:46.939945 cs0 DataBus test pass
701 20:35:46.940480 cs1 DataBus test pass
702 20:35:46.940930 cs0 AddrBus test pass
703 20:35:46.945595 cs1 AddrBus test pass
704 20:35:46.946092
705 20:35:46.946539 100bdlr_step_size ps== 420
706 20:35:46.946998 result report
707 20:35:46.951167 boot times 0Enable ddr reg access
708 20:35:46.958950 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 20:35:46.972438 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 20:35:47.546344 0.0;M3 CHK:0;cm4_sp_mode 0
711 20:35:47.547020 MVN_1=0x00000000
712 20:35:47.551796 MVN_2=0x00000000
713 20:35:47.557612 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 20:35:47.558185 OPS=0x10
715 20:35:47.558633 ring efuse init
716 20:35:47.559068 chipver efuse init
717 20:35:47.565915 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 20:35:47.566514 [0.018960 Inits done]
719 20:35:47.566966 secure task start!
720 20:35:47.573401 high task start!
721 20:35:47.573927 low task start!
722 20:35:47.574367 run into bl31
723 20:35:47.579910 NOTICE: BL31: v1.3(release):4fc40b1
724 20:35:47.587938 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 20:35:47.588478 NOTICE: BL31: G12A normal boot!
726 20:35:47.613118 NOTICE: BL31: BL33 decompress pass
727 20:35:47.618843 ERROR: Error initializing runtime service opteed_fast
728 20:35:48.851751
729 20:35:48.852469
730 20:35:48.860238 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 20:35:48.860782
732 20:35:48.861245 Model: Libre Computer AML-A311D-CC Alta
733 20:35:49.068537 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 20:35:49.092116 DRAM: 2 GiB (effective 3.8 GiB)
735 20:35:49.234995 Core: 408 devices, 31 uclasses, devicetree: separate
736 20:35:49.240767 WDT: Not starting watchdog@f0d0
737 20:35:49.272910 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 20:35:49.285384 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 20:35:49.290404 ** Bad device specification mmc 0 **
740 20:35:49.300846 Card did not respond to voltage select! : -110
741 20:35:49.307502 ** Bad device specification mmc 0 **
742 20:35:49.308055 Couldn't find partition mmc 0
743 20:35:49.316694 Card did not respond to voltage select! : -110
744 20:35:49.322265 ** Bad device specification mmc 0 **
745 20:35:49.322783 Couldn't find partition mmc 0
746 20:35:49.326406 Error: could not access storage.
747 20:35:49.669840 Net: eth0: ethernet@ff3f0000
748 20:35:49.670591 starting USB...
749 20:35:49.921618 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 20:35:49.922268 Starting the controller
751 20:35:49.927575 USB XHCI 1.10
752 20:35:52.090400 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 20:35:52.091040 bl2_stage_init 0x01
754 20:35:52.091506 bl2_stage_init 0x81
755 20:35:52.095891 hw id: 0x0000 - pwm id 0x01
756 20:35:52.096476 bl2_stage_init 0xc1
757 20:35:52.096946 bl2_stage_init 0x02
758 20:35:52.097399
759 20:35:52.101512 L0:00000000
760 20:35:52.102082 L1:20000703
761 20:35:52.102640 L2:00008067
762 20:35:52.103159 L3:14000000
763 20:35:52.104538 B2:00402000
764 20:35:52.105126 B1:e0f83180
765 20:35:52.105610
766 20:35:52.106063 TE: 58159
767 20:35:52.106507
768 20:35:52.115446 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 20:35:52.115959
770 20:35:52.116451 Board ID = 1
771 20:35:52.116893 Set A53 clk to 24M
772 20:35:52.117329 Set A73 clk to 24M
773 20:35:52.121088 Set clk81 to 24M
774 20:35:52.121588 A53 clk: 1200 MHz
775 20:35:52.122056 A73 clk: 1200 MHz
776 20:35:52.126689 CLK81: 166.6M
777 20:35:52.127198 smccc: 00012ab5
778 20:35:52.132247 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 20:35:52.132756 board id: 1
780 20:35:52.140902 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 20:35:52.151555 fw parse done
782 20:35:52.157498 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 20:35:52.200192 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 20:35:52.211060 PIEI prepare done
785 20:35:52.211564 fastboot data load
786 20:35:52.212059 fastboot data verify
787 20:35:52.216712 verify result: 266
788 20:35:52.222317 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 20:35:52.222818 LPDDR4 probe
790 20:35:52.223268 ddr clk to 1584MHz
791 20:35:52.230314 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 20:35:52.267686
793 20:35:52.268378 dmc_version 0001
794 20:35:52.274323 Check phy result
795 20:35:52.280090 INFO : End of CA training
796 20:35:52.280591 INFO : End of initialization
797 20:35:52.285684 INFO : Training has run successfully!
798 20:35:52.286182 Check phy result
799 20:35:52.291350 INFO : End of initialization
800 20:35:52.291847 INFO : End of read enable training
801 20:35:52.296870 INFO : End of fine write leveling
802 20:35:52.302485 INFO : End of Write leveling coarse delay
803 20:35:52.302988 INFO : Training has run successfully!
804 20:35:52.303439 Check phy result
805 20:35:52.308120 INFO : End of initialization
806 20:35:52.308617 INFO : End of read dq deskew training
807 20:35:52.313702 INFO : End of MPR read delay center optimization
808 20:35:52.319322 INFO : End of write delay center optimization
809 20:35:52.324871 INFO : End of read delay center optimization
810 20:35:52.325371 INFO : End of max read latency training
811 20:35:52.330502 INFO : Training has run successfully!
812 20:35:52.331016 1D training succeed
813 20:35:52.339623 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 20:35:52.387296 Check phy result
815 20:35:52.387829 INFO : End of initialization
816 20:35:52.408929 INFO : End of 2D read delay Voltage center optimization
817 20:35:52.429147 INFO : End of 2D read delay Voltage center optimization
818 20:35:52.480975 INFO : End of 2D write delay Voltage center optimization
819 20:35:52.530294 INFO : End of 2D write delay Voltage center optimization
820 20:35:52.535826 INFO : Training has run successfully!
821 20:35:52.536421
822 20:35:52.536883 channel==0
823 20:35:52.541488 RxClkDly_Margin_A0==88 ps 9
824 20:35:52.542005 TxDqDly_Margin_A0==98 ps 10
825 20:35:52.544632 RxClkDly_Margin_A1==88 ps 9
826 20:35:52.545145 TxDqDly_Margin_A1==98 ps 10
827 20:35:52.550266 TrainedVREFDQ_A0==74
828 20:35:52.550782 TrainedVREFDQ_A1==74
829 20:35:52.555896 VrefDac_Margin_A0==25
830 20:35:52.556471 DeviceVref_Margin_A0==40
831 20:35:52.556923 VrefDac_Margin_A1==25
832 20:35:52.561495 DeviceVref_Margin_A1==40
833 20:35:52.562018
834 20:35:52.562451
835 20:35:52.562879 channel==1
836 20:35:52.563304 RxClkDly_Margin_A0==98 ps 10
837 20:35:52.566950 TxDqDly_Margin_A0==88 ps 9
838 20:35:52.567465 RxClkDly_Margin_A1==88 ps 9
839 20:35:52.572581 TxDqDly_Margin_A1==88 ps 9
840 20:35:52.573101 TrainedVREFDQ_A0==77
841 20:35:52.573537 TrainedVREFDQ_A1==77
842 20:35:52.578207 VrefDac_Margin_A0==22
843 20:35:52.578692 DeviceVref_Margin_A0==37
844 20:35:52.583783 VrefDac_Margin_A1==24
845 20:35:52.584297 DeviceVref_Margin_A1==37
846 20:35:52.584727
847 20:35:52.589468 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 20:35:52.589961
849 20:35:52.617486 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
850 20:35:52.622956 2D training succeed
851 20:35:52.628447 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 20:35:52.628941 auto size-- 65535DDR cs0 size: 2048MB
853 20:35:52.634065 DDR cs1 size: 2048MB
854 20:35:52.634553 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 20:35:52.639640 cs0 DataBus test pass
856 20:35:52.640167 cs1 DataBus test pass
857 20:35:52.640601 cs0 AddrBus test pass
858 20:35:52.645313 cs1 AddrBus test pass
859 20:35:52.645798
860 20:35:52.646231 100bdlr_step_size ps== 420
861 20:35:52.646668 result report
862 20:35:52.650852 boot times 0Enable ddr reg access
863 20:35:52.658501 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 20:35:52.671896 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 20:35:53.243866 0.0;M3 CHK:0;cm4_sp_mode 0
866 20:35:53.244562 MVN_1=0x00000000
867 20:35:53.249386 MVN_2=0x00000000
868 20:35:53.255202 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 20:35:53.255704 OPS=0x10
870 20:35:53.256197 ring efuse init
871 20:35:53.256641 chipver efuse init
872 20:35:53.260740 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 20:35:53.266360 [0.018961 Inits done]
874 20:35:53.266853 secure task start!
875 20:35:53.267297 high task start!
876 20:35:53.270908 low task start!
877 20:35:53.271402 run into bl31
878 20:35:53.277574 NOTICE: BL31: v1.3(release):4fc40b1
879 20:35:53.285399 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 20:35:53.285901 NOTICE: BL31: G12A normal boot!
881 20:35:53.310983 NOTICE: BL31: BL33 decompress pass
882 20:35:53.316631 ERROR: Error initializing runtime service opteed_fast
883 20:35:54.549347
884 20:35:54.550018
885 20:35:54.557778 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 20:35:54.558324
887 20:35:54.558783 Model: Libre Computer AML-A311D-CC Alta
888 20:35:54.766190 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 20:35:54.789600 DRAM: 2 GiB (effective 3.8 GiB)
890 20:35:54.932637 Core: 408 devices, 31 uclasses, devicetree: separate
891 20:35:54.938453 WDT: Not starting watchdog@f0d0
892 20:35:54.970745 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 20:35:54.983151 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 20:35:54.988169 ** Bad device specification mmc 0 **
895 20:35:54.998546 Card did not respond to voltage select! : -110
896 20:35:55.006150 ** Bad device specification mmc 0 **
897 20:35:55.006670 Couldn't find partition mmc 0
898 20:35:55.014642 Card did not respond to voltage select! : -110
899 20:35:55.020135 ** Bad device specification mmc 0 **
900 20:35:55.020786 Couldn't find partition mmc 0
901 20:35:55.024649 Error: could not access storage.
902 20:35:55.367548 Net: eth0: ethernet@ff3f0000
903 20:35:55.368241 starting USB...
904 20:35:55.619355 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 20:35:55.620068 Starting the controller
906 20:35:55.625700 USB XHCI 1.10
907 20:35:57.180322 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 20:35:57.188687 scanning usb for storage devices... 0 Storage Device(s) found
910 20:35:57.239746 Hit any key to stop autoboot: 1
911 20:35:57.240620 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
912 20:35:57.241004 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
913 20:35:57.241287 Setting prompt string to ['=>']
914 20:35:57.241588 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
915 20:35:57.246120 0
916 20:35:57.246733 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 20:35:57.247059 Sending with 10 millisecond of delay
919 20:35:58.381571 => setenv autoload no
920 20:35:58.393297 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
921 20:35:58.398274 setenv autoload no
922 20:35:58.399014 Sending with 10 millisecond of delay
924 20:36:00.196363 => setenv initrd_high 0xffffffff
925 20:36:00.207124 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
926 20:36:00.208027 setenv initrd_high 0xffffffff
927 20:36:00.208767 Sending with 10 millisecond of delay
929 20:36:01.825482 => setenv fdt_high 0xffffffff
930 20:36:01.836272 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
931 20:36:01.837075 setenv fdt_high 0xffffffff
932 20:36:01.837786 Sending with 10 millisecond of delay
934 20:36:02.129585 => dhcp
935 20:36:02.140155 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
936 20:36:02.140726 dhcp
937 20:36:02.140982 Speed: 1000, full duplex
938 20:36:02.141218 BOOTP broadcast 1
939 20:36:02.147876 DHCP client bound to address 192.168.6.27 (8 ms)
940 20:36:02.148602 Sending with 10 millisecond of delay
942 20:36:03.825257 => setenv serverip 192.168.6.2
943 20:36:03.836093 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
944 20:36:03.837005 setenv serverip 192.168.6.2
945 20:36:03.837690 Sending with 10 millisecond of delay
947 20:36:07.563621 => tftpboot 0x01080000 955482/tftp-deploy-7l5_8f_g/kernel/uImage
948 20:36:07.574472 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
949 20:36:07.575370 tftpboot 0x01080000 955482/tftp-deploy-7l5_8f_g/kernel/uImage
950 20:36:07.575842 Speed: 1000, full duplex
951 20:36:07.576311 Using ethernet@ff3f0000 device
952 20:36:07.577189 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
953 20:36:07.582686 Filename '955482/tftp-deploy-7l5_8f_g/kernel/uImage'.
954 20:36:07.586668 Load address: 0x1080000
955 20:36:10.518983 Loading: *################################################## 43.6 MiB
956 20:36:10.519659 14.9 MiB/s
957 20:36:10.520343 done
958 20:36:10.523562 Bytes transferred = 45713984 (2b98a40 hex)
959 20:36:10.524462 Sending with 10 millisecond of delay
961 20:36:15.213717 => tftpboot 0x08000000 955482/tftp-deploy-7l5_8f_g/ramdisk/ramdisk.cpio.gz.uboot
962 20:36:15.224582 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
963 20:36:15.225504 tftpboot 0x08000000 955482/tftp-deploy-7l5_8f_g/ramdisk/ramdisk.cpio.gz.uboot
964 20:36:15.225991 Speed: 1000, full duplex
965 20:36:15.226451 Using ethernet@ff3f0000 device
966 20:36:15.227539 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
967 20:36:15.236056 Filename '955482/tftp-deploy-7l5_8f_g/ramdisk/ramdisk.cpio.gz.uboot'.
968 20:36:15.236656 Load address: 0x8000000
969 20:36:21.907260 Loading: *#############T #################################### UDP wrong checksum 00000005 0000f978
970 20:36:26.908387 T UDP wrong checksum 00000005 0000f978
971 20:36:35.634158 T UDP wrong checksum 000000ff 0000c703
972 20:36:35.694853 UDP wrong checksum 000000ff 000052f6
973 20:36:35.704154 UDP wrong checksum 000000ff 0000eeb8
974 20:36:35.744716 UDP wrong checksum 000000ff 000073ab
975 20:36:36.911254 T UDP wrong checksum 00000005 0000f978
976 20:36:55.876045 T T T UDP wrong checksum 000000ff 0000c32f
977 20:36:55.951375 UDP wrong checksum 000000ff 00005e22
978 20:36:56.912981 UDP wrong checksum 00000005 0000f978
979 20:37:11.919706 T T T
980 20:37:11.920414 Retry count exceeded; starting again
982 20:37:11.922051 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
985 20:37:11.924181 end: 2.4 uboot-commands (duration 00:01:46) [common]
987 20:37:11.925776 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
989 20:37:11.926900 end: 2 uboot-action (duration 00:01:46) [common]
991 20:37:11.928603 Cleaning after the job
992 20:37:11.929201 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955482/tftp-deploy-7l5_8f_g/ramdisk
993 20:37:11.930410 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955482/tftp-deploy-7l5_8f_g/kernel
994 20:37:11.950498 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955482/tftp-deploy-7l5_8f_g/dtb
995 20:37:11.951732 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955482/tftp-deploy-7l5_8f_g/modules
996 20:37:11.961783 start: 4.1 power-off (timeout 00:00:30) [common]
997 20:37:11.962900 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
998 20:37:11.999109 >> OK - accepted request
999 20:37:12.001475 Returned 0 in 0 seconds
1000 20:37:12.102652 end: 4.1 power-off (duration 00:00:00) [common]
1002 20:37:12.104520 start: 4.2 read-feedback (timeout 00:10:00) [common]
1003 20:37:12.105747 Listened to connection for namespace 'common' for up to 1s
1004 20:37:13.106526 Finalising connection for namespace 'common'
1005 20:37:13.107331 Disconnecting from shell: Finalise
1006 20:37:13.107901 =>
1007 20:37:13.209113 end: 4.2 read-feedback (duration 00:00:01) [common]
1008 20:37:13.209909 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/955482
1009 20:37:13.508435 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/955482
1010 20:37:13.509047 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.