Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:36:07.788683 lava-dispatcher, installed at version: 2024.01
2 20:36:07.789471 start: 0 validate
3 20:36:07.789936 Start time: 2024-11-07 20:36:07.789906+00:00 (UTC)
4 20:36:07.790485 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:36:07.791003 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 20:36:07.838857 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:36:07.839409 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 20:36:07.865689 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:36:07.866320 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 20:36:08.913936 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:36:08.914438 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 20:36:08.958824 validate duration: 1.17
14 20:36:08.960397 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:36:08.961031 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:36:08.961631 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:36:08.962622 Not decompressing ramdisk as can be used compressed.
18 20:36:08.963373 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 20:36:08.963894 saving as /var/lib/lava/dispatcher/tmp/955534/tftp-deploy-cmi0ouuc/ramdisk/rootfs.cpio.gz
20 20:36:08.964454 total size: 8181887 (7 MB)
21 20:36:09.002683 progress 0 % (0 MB)
22 20:36:09.014302 progress 5 % (0 MB)
23 20:36:09.025494 progress 10 % (0 MB)
24 20:36:09.036988 progress 15 % (1 MB)
25 20:36:09.043573 progress 20 % (1 MB)
26 20:36:09.049225 progress 25 % (1 MB)
27 20:36:09.054380 progress 30 % (2 MB)
28 20:36:09.059950 progress 35 % (2 MB)
29 20:36:09.065147 progress 40 % (3 MB)
30 20:36:09.070662 progress 45 % (3 MB)
31 20:36:09.075745 progress 50 % (3 MB)
32 20:36:09.081218 progress 55 % (4 MB)
33 20:36:09.086354 progress 60 % (4 MB)
34 20:36:09.091791 progress 65 % (5 MB)
35 20:36:09.096939 progress 70 % (5 MB)
36 20:36:09.102468 progress 75 % (5 MB)
37 20:36:09.107564 progress 80 % (6 MB)
38 20:36:09.113073 progress 85 % (6 MB)
39 20:36:09.118249 progress 90 % (7 MB)
40 20:36:09.123728 progress 95 % (7 MB)
41 20:36:09.128467 progress 100 % (7 MB)
42 20:36:09.129107 7 MB downloaded in 0.16 s (47.39 MB/s)
43 20:36:09.129652 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:36:09.130532 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:36:09.130822 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:36:09.131091 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:36:09.131565 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/kernel/Image
49 20:36:09.131831 saving as /var/lib/lava/dispatcher/tmp/955534/tftp-deploy-cmi0ouuc/kernel/Image
50 20:36:09.132065 total size: 45713920 (43 MB)
51 20:36:09.132276 No compression specified
52 20:36:09.172409 progress 0 % (0 MB)
53 20:36:09.200422 progress 5 % (2 MB)
54 20:36:09.228126 progress 10 % (4 MB)
55 20:36:09.256153 progress 15 % (6 MB)
56 20:36:09.284160 progress 20 % (8 MB)
57 20:36:09.312284 progress 25 % (10 MB)
58 20:36:09.340476 progress 30 % (13 MB)
59 20:36:09.368907 progress 35 % (15 MB)
60 20:36:09.397243 progress 40 % (17 MB)
61 20:36:09.425001 progress 45 % (19 MB)
62 20:36:09.453404 progress 50 % (21 MB)
63 20:36:09.481696 progress 55 % (24 MB)
64 20:36:09.509999 progress 60 % (26 MB)
65 20:36:09.537972 progress 65 % (28 MB)
66 20:36:09.566348 progress 70 % (30 MB)
67 20:36:09.594810 progress 75 % (32 MB)
68 20:36:09.622613 progress 80 % (34 MB)
69 20:36:09.650314 progress 85 % (37 MB)
70 20:36:09.678519 progress 90 % (39 MB)
71 20:36:09.706225 progress 95 % (41 MB)
72 20:36:09.733842 progress 100 % (43 MB)
73 20:36:09.734375 43 MB downloaded in 0.60 s (72.38 MB/s)
74 20:36:09.734856 end: 1.2.1 http-download (duration 00:00:01) [common]
76 20:36:09.735667 end: 1.2 download-retry (duration 00:00:01) [common]
77 20:36:09.735937 start: 1.3 download-retry (timeout 00:09:59) [common]
78 20:36:09.736234 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 20:36:09.736704 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 20:36:09.736983 saving as /var/lib/lava/dispatcher/tmp/955534/tftp-deploy-cmi0ouuc/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 20:36:09.737191 total size: 53209 (0 MB)
82 20:36:09.737400 No compression specified
83 20:36:09.772482 progress 61 % (0 MB)
84 20:36:09.773403 progress 100 % (0 MB)
85 20:36:09.773958 0 MB downloaded in 0.04 s (1.38 MB/s)
86 20:36:09.774410 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:36:09.775215 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:36:09.775473 start: 1.4 download-retry (timeout 00:09:59) [common]
90 20:36:09.775733 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 20:36:09.776205 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/modules.tar.xz
92 20:36:09.776454 saving as /var/lib/lava/dispatcher/tmp/955534/tftp-deploy-cmi0ouuc/modules/modules.tar
93 20:36:09.776656 total size: 11624536 (11 MB)
94 20:36:09.776864 Using unxz to decompress xz
95 20:36:09.810471 progress 0 % (0 MB)
96 20:36:09.883373 progress 5 % (0 MB)
97 20:36:09.960700 progress 10 % (1 MB)
98 20:36:10.059138 progress 15 % (1 MB)
99 20:36:10.149712 progress 20 % (2 MB)
100 20:36:10.230571 progress 25 % (2 MB)
101 20:36:10.305988 progress 30 % (3 MB)
102 20:36:10.385408 progress 35 % (3 MB)
103 20:36:10.458399 progress 40 % (4 MB)
104 20:36:10.534111 progress 45 % (5 MB)
105 20:36:10.620043 progress 50 % (5 MB)
106 20:36:10.702925 progress 55 % (6 MB)
107 20:36:10.783355 progress 60 % (6 MB)
108 20:36:10.868322 progress 65 % (7 MB)
109 20:36:10.949792 progress 70 % (7 MB)
110 20:36:11.031968 progress 75 % (8 MB)
111 20:36:11.111054 progress 80 % (8 MB)
112 20:36:11.193624 progress 85 % (9 MB)
113 20:36:11.275739 progress 90 % (10 MB)
114 20:36:11.351973 progress 95 % (10 MB)
115 20:36:11.424725 progress 100 % (11 MB)
116 20:36:11.438297 11 MB downloaded in 1.66 s (6.67 MB/s)
117 20:36:11.439287 end: 1.4.1 http-download (duration 00:00:02) [common]
119 20:36:11.440769 end: 1.4 download-retry (duration 00:00:02) [common]
120 20:36:11.441073 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 20:36:11.441348 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 20:36:11.441605 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:36:11.442085 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 20:36:11.443179 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9
125 20:36:11.444181 makedir: /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin
126 20:36:11.444962 makedir: /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/tests
127 20:36:11.445688 makedir: /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/results
128 20:36:11.446401 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-add-keys
129 20:36:11.447597 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-add-sources
130 20:36:11.448723 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-background-process-start
131 20:36:11.449823 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-background-process-stop
132 20:36:11.450954 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-common-functions
133 20:36:11.452030 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-echo-ipv4
134 20:36:11.453078 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-install-packages
135 20:36:11.454111 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-installed-packages
136 20:36:11.455132 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-os-build
137 20:36:11.456195 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-probe-channel
138 20:36:11.457243 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-probe-ip
139 20:36:11.458284 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-target-ip
140 20:36:11.459329 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-target-mac
141 20:36:11.460392 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-target-storage
142 20:36:11.461425 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-test-case
143 20:36:11.462418 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-test-event
144 20:36:11.463396 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-test-feedback
145 20:36:11.464417 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-test-raise
146 20:36:11.465407 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-test-reference
147 20:36:11.466389 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-test-runner
148 20:36:11.467368 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-test-set
149 20:36:11.468377 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-test-shell
150 20:36:11.469379 Updating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-install-packages (oe)
151 20:36:11.470453 Updating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/bin/lava-installed-packages (oe)
152 20:36:11.471361 Creating /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/environment
153 20:36:11.472164 LAVA metadata
154 20:36:11.472705 - LAVA_JOB_ID=955534
155 20:36:11.473181 - LAVA_DISPATCHER_IP=192.168.6.2
156 20:36:11.473897 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 20:36:11.475844 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 20:36:11.476530 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 20:36:11.476995 skipped lava-vland-overlay
160 20:36:11.477535 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 20:36:11.478095 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 20:36:11.478564 skipped lava-multinode-overlay
163 20:36:11.479097 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 20:36:11.479650 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 20:36:11.480256 Loading test definitions
166 20:36:11.480818 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 20:36:11.481262 Using /lava-955534 at stage 0
168 20:36:11.483493 uuid=955534_1.5.2.4.1 testdef=None
169 20:36:11.484095 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 20:36:11.484628 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 20:36:11.487976 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 20:36:11.488847 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 20:36:11.491127 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 20:36:11.491967 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 20:36:11.494223 runner path: /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/0/tests/0_dmesg test_uuid 955534_1.5.2.4.1
178 20:36:11.494801 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 20:36:11.495584 Creating lava-test-runner.conf files
181 20:36:11.495791 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/955534/lava-overlay-rmrcl6k9/lava-955534/0 for stage 0
182 20:36:11.496159 - 0_dmesg
183 20:36:11.496527 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 20:36:11.496817 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 20:36:11.521134 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 20:36:11.521560 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 20:36:11.521836 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 20:36:11.522109 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 20:36:11.522382 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 20:36:12.437459 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 20:36:12.437952 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 20:36:12.438205 extracting modules file /var/lib/lava/dispatcher/tmp/955534/tftp-deploy-cmi0ouuc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955534/extract-overlay-ramdisk-j63t3hxf/ramdisk
193 20:36:13.756399 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 20:36:13.756884 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 20:36:13.757157 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955534/compress-overlay-c5bogtrr/overlay-1.5.2.5.tar.gz to ramdisk
196 20:36:13.757368 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955534/compress-overlay-c5bogtrr/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/955534/extract-overlay-ramdisk-j63t3hxf/ramdisk
197 20:36:13.787262 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 20:36:13.787661 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 20:36:13.787930 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 20:36:13.788182 Converting downloaded kernel to a uImage
201 20:36:13.788484 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/955534/tftp-deploy-cmi0ouuc/kernel/Image /var/lib/lava/dispatcher/tmp/955534/tftp-deploy-cmi0ouuc/kernel/uImage
202 20:36:14.322230 output: Image Name:
203 20:36:14.322648 output: Created: Thu Nov 7 20:36:13 2024
204 20:36:14.322855 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 20:36:14.323058 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 20:36:14.323260 output: Load Address: 01080000
207 20:36:14.323457 output: Entry Point: 01080000
208 20:36:14.323652 output:
209 20:36:14.324017 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 20:36:14.324304 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 20:36:14.324574 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 20:36:14.324827 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 20:36:14.325080 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 20:36:14.325343 Building ramdisk /var/lib/lava/dispatcher/tmp/955534/extract-overlay-ramdisk-j63t3hxf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/955534/extract-overlay-ramdisk-j63t3hxf/ramdisk
215 20:36:16.732714 >> 181575 blocks
216 20:36:25.148840 Adding RAMdisk u-boot header.
217 20:36:25.149547 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/955534/extract-overlay-ramdisk-j63t3hxf/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/955534/extract-overlay-ramdisk-j63t3hxf/ramdisk.cpio.gz.uboot
218 20:36:25.441115 output: Image Name:
219 20:36:25.441734 output: Created: Thu Nov 7 20:36:25 2024
220 20:36:25.442156 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 20:36:25.442565 output: Data Size: 26053551 Bytes = 25442.92 KiB = 24.85 MiB
222 20:36:25.442966 output: Load Address: 00000000
223 20:36:25.443363 output: Entry Point: 00000000
224 20:36:25.443754 output:
225 20:36:25.445258 rename /var/lib/lava/dispatcher/tmp/955534/extract-overlay-ramdisk-j63t3hxf/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/955534/tftp-deploy-cmi0ouuc/ramdisk/ramdisk.cpio.gz.uboot
226 20:36:25.445980 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 20:36:25.446532 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 20:36:25.447058 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 20:36:25.447523 No LXC device requested
230 20:36:25.448063 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 20:36:25.448596 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 20:36:25.449096 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 20:36:25.449521 Checking files for TFTP limit of 4294967296 bytes.
234 20:36:25.452173 end: 1 tftp-deploy (duration 00:00:16) [common]
235 20:36:25.452747 start: 2 uboot-action (timeout 00:05:00) [common]
236 20:36:25.453279 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 20:36:25.453810 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 20:36:25.454311 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 20:36:25.454835 Using kernel file from prepare-kernel: 955534/tftp-deploy-cmi0ouuc/kernel/uImage
240 20:36:25.455435 substitutions:
241 20:36:25.455840 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 20:36:25.456264 - {DTB_ADDR}: 0x01070000
243 20:36:25.456656 - {DTB}: 955534/tftp-deploy-cmi0ouuc/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 20:36:25.457047 - {INITRD}: 955534/tftp-deploy-cmi0ouuc/ramdisk/ramdisk.cpio.gz.uboot
245 20:36:25.457437 - {KERNEL_ADDR}: 0x01080000
246 20:36:25.457825 - {KERNEL}: 955534/tftp-deploy-cmi0ouuc/kernel/uImage
247 20:36:25.458210 - {LAVA_MAC}: None
248 20:36:25.458633 - {PRESEED_CONFIG}: None
249 20:36:25.459022 - {PRESEED_LOCAL}: None
250 20:36:25.459407 - {RAMDISK_ADDR}: 0x08000000
251 20:36:25.459787 - {RAMDISK}: 955534/tftp-deploy-cmi0ouuc/ramdisk/ramdisk.cpio.gz.uboot
252 20:36:25.460207 - {ROOT_PART}: None
253 20:36:25.460595 - {ROOT}: None
254 20:36:25.460979 - {SERVER_IP}: 192.168.6.2
255 20:36:25.461366 - {TEE_ADDR}: 0x83000000
256 20:36:25.461753 - {TEE}: None
257 20:36:25.462135 Parsed boot commands:
258 20:36:25.462507 - setenv autoload no
259 20:36:25.462885 - setenv initrd_high 0xffffffff
260 20:36:25.463264 - setenv fdt_high 0xffffffff
261 20:36:25.463643 - dhcp
262 20:36:25.464048 - setenv serverip 192.168.6.2
263 20:36:25.464433 - tftpboot 0x01080000 955534/tftp-deploy-cmi0ouuc/kernel/uImage
264 20:36:25.464817 - tftpboot 0x08000000 955534/tftp-deploy-cmi0ouuc/ramdisk/ramdisk.cpio.gz.uboot
265 20:36:25.465205 - tftpboot 0x01070000 955534/tftp-deploy-cmi0ouuc/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 20:36:25.465587 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 20:36:25.465976 - bootm 0x01080000 0x08000000 0x01070000
268 20:36:25.466457 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 20:36:25.467921 start: 2.3 connect-device (timeout 00:05:00) [common]
271 20:36:25.468388 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 20:36:25.483699 Setting prompt string to ['lava-test: # ']
273 20:36:25.485219 end: 2.3 connect-device (duration 00:00:00) [common]
274 20:36:25.485811 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 20:36:25.486353 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 20:36:25.486989 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 20:36:25.488187 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 20:36:25.525234 >> OK - accepted request
279 20:36:25.527158 Returned 0 in 0 seconds
280 20:36:25.628285 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 20:36:25.629873 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 20:36:25.630456 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 20:36:25.630962 Setting prompt string to ['Hit any key to stop autoboot']
285 20:36:25.631395 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 20:36:25.632996 Trying 192.168.56.21...
287 20:36:25.633474 Connected to conserv1.
288 20:36:25.633887 Escape character is '^]'.
289 20:36:25.634304
290 20:36:25.634737 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 20:36:25.635184
292 20:36:33.283667 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 20:36:33.284405 bl2_stage_init 0x01
294 20:36:33.284849 bl2_stage_init 0x81
295 20:36:33.289031 hw id: 0x0000 - pwm id 0x01
296 20:36:33.289494 bl2_stage_init 0xc1
297 20:36:33.294676 bl2_stage_init 0x02
298 20:36:33.295125
299 20:36:33.295524 L0:00000000
300 20:36:33.295924 L1:00000703
301 20:36:33.296350 L2:00008067
302 20:36:33.296735 L3:15000000
303 20:36:33.300183 S1:00000000
304 20:36:33.300605 B2:20282000
305 20:36:33.300994 B1:a0f83180
306 20:36:33.301379
307 20:36:33.301769 TE: 67946
308 20:36:33.302160
309 20:36:33.305899 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 20:36:33.306329
311 20:36:33.311343 Board ID = 1
312 20:36:33.311816 Set cpu clk to 24M
313 20:36:33.312245 Set clk81 to 24M
314 20:36:33.317057 Use GP1_pll as DSU clk.
315 20:36:33.317530 DSU clk: 1200 Mhz
316 20:36:33.317923 CPU clk: 1200 MHz
317 20:36:33.322582 Set clk81 to 166.6M
318 20:36:33.328201 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 20:36:33.328672 board id: 1
320 20:36:33.335477 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 20:36:33.346398 fw parse done
322 20:36:33.352322 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 20:36:33.395349 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 20:36:33.406537 PIEI prepare done
325 20:36:33.407045 fastboot data load
326 20:36:33.407452 fastboot data verify
327 20:36:33.412025 verify result: 266
328 20:36:33.417697 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 20:36:33.418198 LPDDR4 probe
330 20:36:33.418614 ddr clk to 1584MHz
331 20:36:33.425570 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 20:36:33.463597
333 20:36:33.464223 dmc_version 0001
334 20:36:33.470487 Check phy result
335 20:36:33.476568 INFO : End of CA training
336 20:36:33.477062 INFO : End of initialization
337 20:36:33.482052 INFO : Training has run successfully!
338 20:36:33.482540 Check phy result
339 20:36:33.487696 INFO : End of initialization
340 20:36:33.488202 INFO : End of read enable training
341 20:36:33.491042 INFO : End of fine write leveling
342 20:36:33.496566 INFO : End of Write leveling coarse delay
343 20:36:33.502139 INFO : Training has run successfully!
344 20:36:33.502623 Check phy result
345 20:36:33.503036 INFO : End of initialization
346 20:36:33.507700 INFO : End of read dq deskew training
347 20:36:33.513319 INFO : End of MPR read delay center optimization
348 20:36:33.513802 INFO : End of write delay center optimization
349 20:36:33.518962 INFO : End of read delay center optimization
350 20:36:33.524516 INFO : End of max read latency training
351 20:36:33.525011 INFO : Training has run successfully!
352 20:36:33.530190 1D training succeed
353 20:36:33.536075 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 20:36:33.584463 Check phy result
355 20:36:33.585005 INFO : End of initialization
356 20:36:33.611883 INFO : End of 2D read delay Voltage center optimization
357 20:36:33.635955 INFO : End of 2D read delay Voltage center optimization
358 20:36:33.692733 INFO : End of 2D write delay Voltage center optimization
359 20:36:33.746656 INFO : End of 2D write delay Voltage center optimization
360 20:36:33.752175 INFO : Training has run successfully!
361 20:36:33.752703
362 20:36:33.753124 channel==0
363 20:36:33.757727 RxClkDly_Margin_A0==78 ps 8
364 20:36:33.758237 TxDqDly_Margin_A0==98 ps 10
365 20:36:33.761138 RxClkDly_Margin_A1==88 ps 9
366 20:36:33.761619 TxDqDly_Margin_A1==98 ps 10
367 20:36:33.766793 TrainedVREFDQ_A0==74
368 20:36:33.767304 TrainedVREFDQ_A1==74
369 20:36:33.767704 VrefDac_Margin_A0==23
370 20:36:33.772899 DeviceVref_Margin_A0==40
371 20:36:33.773415 VrefDac_Margin_A1==23
372 20:36:33.778551 DeviceVref_Margin_A1==40
373 20:36:33.779089
374 20:36:33.779517
375 20:36:33.779928 channel==1
376 20:36:33.780373 RxClkDly_Margin_A0==78 ps 8
377 20:36:33.784152 TxDqDly_Margin_A0==98 ps 10
378 20:36:33.784680 RxClkDly_Margin_A1==78 ps 8
379 20:36:33.789675 TxDqDly_Margin_A1==88 ps 9
380 20:36:33.790203 TrainedVREFDQ_A0==78
381 20:36:33.790627 TrainedVREFDQ_A1==75
382 20:36:33.795526 VrefDac_Margin_A0==22
383 20:36:33.796081 DeviceVref_Margin_A0==36
384 20:36:33.796516 VrefDac_Margin_A1==22
385 20:36:33.800953 DeviceVref_Margin_A1==39
386 20:36:33.801479
387 20:36:33.806515 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 20:36:33.807041
389 20:36:33.834587 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000014 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
390 20:36:33.835190 2D training succeed
391 20:36:33.845705 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 20:36:33.846260 auto size-- 65535DDR cs0 size: 2048MB
393 20:36:33.851343 DDR cs1 size: 2048MB
394 20:36:33.851874 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 20:36:33.856977 cs0 DataBus test pass
396 20:36:33.857508 cs1 DataBus test pass
397 20:36:33.857928 cs0 AddrBus test pass
398 20:36:33.862558 cs1 AddrBus test pass
399 20:36:33.863105
400 20:36:33.863534 100bdlr_step_size ps== 485
401 20:36:33.863956 result report
402 20:36:33.868175 boot times 0Enable ddr reg access
403 20:36:33.875067 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 20:36:33.888842 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 20:36:34.548445 bl2z: ptr: 05129330, size: 00001e40
406 20:36:34.556273 0.0;M3 CHK:0;cm4_sp_mode 0
407 20:36:34.556822 MVN_1=0x00000000
408 20:36:34.557240 MVN_2=0x00000000
409 20:36:34.567738 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 20:36:34.568322 OPS=0x04
411 20:36:34.568743 ring efuse init
412 20:36:34.570809 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 20:36:34.577233 [0.017354 Inits done]
414 20:36:34.577782 secure task start!
415 20:36:34.578200 high task start!
416 20:36:34.578603 low task start!
417 20:36:34.581513 run into bl31
418 20:36:34.590261 NOTICE: BL31: v1.3(release):4fc40b1
419 20:36:34.597961 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 20:36:34.598508 NOTICE: BL31: G12A normal boot!
421 20:36:34.613393 NOTICE: BL31: BL33 decompress pass
422 20:36:34.619056 ERROR: Error initializing runtime service opteed_fast
423 20:36:35.834556 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 20:36:35.835015 bl2_stage_init 0x01
425 20:36:35.835232 bl2_stage_init 0x81
426 20:36:35.840315 hw id: 0x0000 - pwm id 0x01
427 20:36:35.840849 bl2_stage_init 0xc1
428 20:36:35.845732 bl2_stage_init 0x02
429 20:36:35.846174
430 20:36:35.846574 L0:00000000
431 20:36:35.846965 L1:00000703
432 20:36:35.847352 L2:00008067
433 20:36:35.847735 L3:15000000
434 20:36:35.851302 S1:00000000
435 20:36:35.851719 B2:20282000
436 20:36:35.852151 B1:a0f83180
437 20:36:35.852541
438 20:36:35.852926 TE: 68979
439 20:36:35.853309
440 20:36:35.857000 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 20:36:35.857429
442 20:36:35.862549 Board ID = 1
443 20:36:35.862977 Set cpu clk to 24M
444 20:36:35.863364 Set clk81 to 24M
445 20:36:35.868226 Use GP1_pll as DSU clk.
446 20:36:35.868652 DSU clk: 1200 Mhz
447 20:36:35.869035 CPU clk: 1200 MHz
448 20:36:35.873749 Set clk81 to 166.6M
449 20:36:35.879352 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 20:36:35.879777 board id: 1
451 20:36:35.886919 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 20:36:35.897468 fw parse done
453 20:36:35.903649 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 20:36:35.946474 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 20:36:35.957667 PIEI prepare done
456 20:36:35.958104 fastboot data load
457 20:36:35.958502 fastboot data verify
458 20:36:35.963249 verify result: 266
459 20:36:35.968817 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 20:36:35.969253 LPDDR4 probe
461 20:36:35.969645 ddr clk to 1584MHz
462 20:36:37.337813 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd000 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 20:36:37.338479 bl2_stage_init 0x01
464 20:36:37.338954 bl2_stage_init 0x81
465 20:36:37.343664 hw id: 0x0000 - pwm id 0x01
466 20:36:37.344280 bl2_stage_init 0xc1
467 20:36:37.347717 bl2_stage_init 0x02
468 20:36:37.348236
469 20:36:37.348694 L0:00000000
470 20:36:37.349140 L1:00000703
471 20:36:37.349583 L2:00008067
472 20:36:37.353258 L3:15000000
473 20:36:37.353762 S1:00000000
474 20:36:37.354209 B2:20282000
475 20:36:37.354650 B1:a0f83180
476 20:36:37.355087
477 20:36:37.355527 TE: 71202
478 20:36:37.359210
479 20:36:37.364530 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 20:36:37.365018
481 20:36:37.365466 Board ID = 1
482 20:36:37.365907 Set cpu clk to 24M
483 20:36:37.370100 Set clk81 to 24M
484 20:36:37.370583 Use GP1_pll as DSU clk.
485 20:36:37.371030 DSU clk: 1200 Mhz
486 20:36:37.371473 CPU clk: 1200 MHz
487 20:36:37.375606 Set clk81 to 166.6M
488 20:36:37.381156 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 20:36:37.381643 board id: 1
490 20:36:37.389761 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 20:36:37.400656 fw parse done
492 20:36:37.406615 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 20:36:37.449787 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 20:36:37.460922 PIEI prepare done
495 20:36:37.461431 fastboot data load
496 20:36:37.461888 fastboot data verify
497 20:36:37.466578 verify result: 266
498 20:36:37.472133 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 20:36:37.472655 LPDDR4 probe
500 20:36:37.473108 ddr clk to 1584MHz
501 20:36:37.480086 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 20:36:37.517943
503 20:36:37.518460 dmc_version 0001
504 20:36:37.524924 Check phy result
505 20:36:37.530916 INFO : End of CA training
506 20:36:37.531407 INFO : End of initialization
507 20:36:37.536600 INFO : Training has run successfully!
508 20:36:37.537115 Check phy result
509 20:36:37.542120 INFO : End of initialization
510 20:36:37.542689 INFO : End of read enable training
511 20:36:37.547774 INFO : End of fine write leveling
512 20:36:37.553328 INFO : End of Write leveling coarse delay
513 20:36:37.553871 INFO : Training has run successfully!
514 20:36:37.554342 Check phy result
515 20:36:37.562852 INFO : End of initialization
516 20:36:37.563701 INFO : End of read dq deskew training
517 20:36:37.568220 INFO : End of MPR read delay center optimization
518 20:36:37.570902 INFO : End of write delay center optimization
519 20:36:37.575690 INFO : End of read delay center optimization
520 20:36:37.576087 INFO : End of max read latency training
521 20:36:37.581262 INFO : Training has run successfully!
522 20:36:37.581618 1D training succeed
523 20:36:37.590470 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 20:36:37.638729 Check phy result
525 20:36:37.639152 INFO : End of initialization
526 20:36:37.666135 INFO : End of 2D read delay Voltage center optimization
527 20:36:37.690252 INFO : End of 2D read delay Voltage center optimization
528 20:36:37.747141 INFO : End of 2D write delay Voltage center optimization
529 20:36:37.801128 INFO : End of 2D write delay Voltage center optimization
530 20:36:37.806673 INFO : Training has run successfully!
531 20:36:37.807006
532 20:36:37.807226 channel==0
533 20:36:37.812234 RxClkDly_Margin_A0==78 ps 8
534 20:36:37.812579 TxDqDly_Margin_A0==88 ps 9
535 20:36:37.817801 RxClkDly_Margin_A1==88 ps 9
536 20:36:37.818117 TxDqDly_Margin_A1==88 ps 9
537 20:36:37.818327 TrainedVREFDQ_A0==74
538 20:36:37.823376 TrainedVREFDQ_A1==74
539 20:36:37.823684 VrefDac_Margin_A0==23
540 20:36:37.823903 DeviceVref_Margin_A0==40
541 20:36:37.828857 VrefDac_Margin_A1==23
542 20:36:37.829173 DeviceVref_Margin_A1==40
543 20:36:37.829388
544 20:36:37.829606
545 20:36:37.829821 channel==1
546 20:36:37.834533 RxClkDly_Margin_A0==78 ps 8
547 20:36:37.834849 TxDqDly_Margin_A0==98 ps 10
548 20:36:37.840154 RxClkDly_Margin_A1==78 ps 8
549 20:36:37.840466 TxDqDly_Margin_A1==78 ps 8
550 20:36:37.845726 TrainedVREFDQ_A0==78
551 20:36:37.846050 TrainedVREFDQ_A1==75
552 20:36:37.846279 VrefDac_Margin_A0==22
553 20:36:37.851318 DeviceVref_Margin_A0==36
554 20:36:37.851633 VrefDac_Margin_A1==22
555 20:36:37.851854 DeviceVref_Margin_A1==39
556 20:36:37.856902
557 20:36:37.857223 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 20:36:37.857440
559 20:36:37.890541 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000019 00000015 00000017 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
560 20:36:37.890932 2D training succeed
561 20:36:37.896208 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 20:36:37.901784 auto size-- 65535DDR cs0 size: 2048MB
563 20:36:37.902106 DDR cs1 size: 2048MB
564 20:36:37.907308 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 20:36:37.907624 cs0 DataBus test pass
566 20:36:37.912949 cs1 DataBus test pass
567 20:36:37.913522 cs0 AddrBus test pass
568 20:36:37.913981 cs1 AddrBus test pass
569 20:36:37.914434
570 20:36:37.918565 100bdlr_step_size ps== 471
571 20:36:37.919086 result report
572 20:36:37.924136 boot times 0Enable ddr reg access
573 20:36:37.929299 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 20:36:37.943008 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 20:36:38.602373 bl2z: ptr: 05129330, size: 00001e40
576 20:36:38.608861 0.0;M3 CHK:0;cm4_sp_mode 0
577 20:36:38.609433 MVN_1=0x00000000
578 20:36:38.609894 MVN_2=0x00000000
579 20:36:38.620333 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 20:36:38.620871 OPS=0x04
581 20:36:38.621327 ring efuse init
582 20:36:38.623244 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 20:36:38.629335 [0.017354 Inits done]
584 20:36:38.629926 secure task start!
585 20:36:38.630400 high task start!
586 20:36:38.630857 low task start!
587 20:36:38.633615 run into bl31
588 20:36:38.642237 NOTICE: BL31: v1.3(release):4fc40b1
589 20:36:38.650054 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 20:36:38.650599 NOTICE: BL31: G12A normal boot!
591 20:36:38.665669 NOTICE: BL31: BL33 decompress pass
592 20:36:38.671407 ERROR: Error initializing runtime service opteed_fast
593 20:36:39.884636 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 20:36:39.885162 bl2_stage_init 0x01
595 20:36:39.885534 bl2_stage_init 0x81
596 20:36:39.890065 hw id: 0x0000 - pwm id 0x01
597 20:36:39.890366 bl2_stage_init 0xc1
598 20:36:39.895720 bl2_stage_init 0x02
599 20:36:39.896156
600 20:36:39.896482 L0:00000000
601 20:36:39.896808 L1:00000703
602 20:36:39.897099 L2:00008067
603 20:36:39.897379 L3:15000000
604 20:36:39.901815 S1:00000000
605 20:36:39.902191 B2:20282000
606 20:36:39.902490 B1:a0f83180
607 20:36:39.902808
608 20:36:39.903099 TE: 68194
609 20:36:39.903390
610 20:36:39.907409 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 20:36:39.907715
612 20:36:39.912977 Board ID = 1
613 20:36:39.913276 Set cpu clk to 24M
614 20:36:39.913482 Set clk81 to 24M
615 20:36:39.918856 Use GP1_pll as DSU clk.
616 20:36:39.919693 DSU clk: 1200 Mhz
617 20:36:39.920519 CPU clk: 1200 MHz
618 20:36:39.921240 Set clk81 to 166.6M
619 20:36:39.929891 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 20:36:39.930749 board id: 1
621 20:36:39.936591 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 20:36:39.947295 fw parse done
623 20:36:39.953211 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 20:36:39.995879 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 20:36:40.007042 PIEI prepare done
626 20:36:40.007803 fastboot data load
627 20:36:40.008531 fastboot data verify
628 20:36:40.012514 verify result: 266
629 20:36:40.018091 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 20:36:40.018889 LPDDR4 probe
631 20:36:40.019517 ddr clk to 1584MHz
632 20:36:40.026146 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 20:36:40.063261
634 20:36:40.063623 dmc_version 0001
635 20:36:40.069961 Check phy result
636 20:36:40.075930 INFO : End of CA training
637 20:36:40.076820 INFO : End of initialization
638 20:36:40.081542 INFO : Training has run successfully!
639 20:36:40.082285 Check phy result
640 20:36:40.087135 INFO : End of initialization
641 20:36:40.087938 INFO : End of read enable training
642 20:36:40.092775 INFO : End of fine write leveling
643 20:36:40.098361 INFO : End of Write leveling coarse delay
644 20:36:40.099156 INFO : Training has run successfully!
645 20:36:40.099769 Check phy result
646 20:36:40.103877 INFO : End of initialization
647 20:36:40.104623 INFO : End of read dq deskew training
648 20:36:40.109408 INFO : End of MPR read delay center optimization
649 20:36:40.115041 INFO : End of write delay center optimization
650 20:36:40.120671 INFO : End of read delay center optimization
651 20:36:40.121461 INFO : End of max read latency training
652 20:36:40.126275 INFO : Training has run successfully!
653 20:36:40.127055 1D training succeed
654 20:36:40.135427 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 20:36:40.183127 Check phy result
656 20:36:40.183801 INFO : End of initialization
657 20:36:40.205362 INFO : End of 2D read delay Voltage center optimization
658 20:36:40.224610 INFO : End of 2D read delay Voltage center optimization
659 20:36:40.276453 INFO : End of 2D write delay Voltage center optimization
660 20:36:40.325684 INFO : End of 2D write delay Voltage center optimization
661 20:36:40.331253 INFO : Training has run successfully!
662 20:36:40.332090
663 20:36:40.332811 channel==0
664 20:36:40.336808 RxClkDly_Margin_A0==78 ps 8
665 20:36:40.337579 TxDqDly_Margin_A0==98 ps 10
666 20:36:40.342387 RxClkDly_Margin_A1==88 ps 9
667 20:36:40.343147 TxDqDly_Margin_A1==88 ps 9
668 20:36:40.343857 TrainedVREFDQ_A0==74
669 20:36:40.347940 TrainedVREFDQ_A1==74
670 20:36:40.348787 VrefDac_Margin_A0==23
671 20:36:40.349453 DeviceVref_Margin_A0==40
672 20:36:40.353566 VrefDac_Margin_A1==23
673 20:36:40.354307 DeviceVref_Margin_A1==40
674 20:36:40.355018
675 20:36:40.355723
676 20:36:40.356435 channel==1
677 20:36:40.359194 RxClkDly_Margin_A0==88 ps 9
678 20:36:40.359909 TxDqDly_Margin_A0==98 ps 10
679 20:36:40.364802 RxClkDly_Margin_A1==88 ps 9
680 20:36:40.365538 TxDqDly_Margin_A1==88 ps 9
681 20:36:40.373143 TrainedVREFDQ_A0==75
682 20:36:40.373918 TrainedVREFDQ_A1==77
683 20:36:40.374626 VrefDac_Margin_A0==23
684 20:36:40.376054 DeviceVref_Margin_A0==39
685 20:36:40.376798 VrefDac_Margin_A1==21
686 20:36:40.381723 DeviceVref_Margin_A1==37
687 20:36:40.382488
688 20:36:40.383202 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 20:36:40.383859
690 20:36:40.415493 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000018 00000019 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
691 20:36:40.416407 2D training succeed
692 20:36:40.420858 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 20:36:40.426323 auto size-- 65535DDR cs0 size: 2048MB
694 20:36:40.426662 DDR cs1 size: 2048MB
695 20:36:40.431962 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 20:36:40.432532 cs0 DataBus test pass
697 20:36:40.437552 cs1 DataBus test pass
698 20:36:40.438080 cs0 AddrBus test pass
699 20:36:40.438506 cs1 AddrBus test pass
700 20:36:40.438905
701 20:36:40.443107 100bdlr_step_size ps== 478
702 20:36:40.443620 result report
703 20:36:40.448842 boot times 0Enable ddr reg access
704 20:36:40.453913 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 20:36:40.467766 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 20:36:41.124267 bl2z: ptr: 05129330, size: 00001e40
707 20:36:41.130957 0.0;M3 CHK:0;cm4_sp_mode 0
708 20:36:41.131339 MVN_1=0x00000000
709 20:36:41.131601 MVN_2=0x00000000
710 20:36:41.142311 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 20:36:41.142732 OPS=0x04
712 20:36:41.142997 ring efuse init
713 20:36:41.147927 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 20:36:41.148316 [0.017319 Inits done]
715 20:36:41.148587 secure task start!
716 20:36:41.155846 high task start!
717 20:36:41.156238 low task start!
718 20:36:41.156505 run into bl31
719 20:36:41.164477 NOTICE: BL31: v1.3(release):4fc40b1
720 20:36:41.172343 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 20:36:41.172711 NOTICE: BL31: G12A normal boot!
722 20:36:41.187807 NOTICE: BL31: BL33 decompress pass
723 20:36:41.193539 ERROR: Error initializing runtime service opteed_fast
724 20:36:41.988991
725 20:36:41.989754
726 20:36:41.994296 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 20:36:41.994880
728 20:36:41.997749 Model: Libre Computer AML-S905D3-CC Solitude
729 20:36:42.144883 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 20:36:42.160241 DRAM: 2 GiB (effective 3.8 GiB)
731 20:36:42.261201 Core: 406 devices, 33 uclasses, devicetree: separate
732 20:36:42.267099 WDT: Not starting watchdog@f0d0
733 20:36:42.292210 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 20:36:42.304395 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 20:36:42.309354 ** Bad device specification mmc 0 **
736 20:36:42.319433 Card did not respond to voltage select! : -110
737 20:36:42.327137 ** Bad device specification mmc 0 **
738 20:36:42.327632 Couldn't find partition mmc 0
739 20:36:42.335412 Card did not respond to voltage select! : -110
740 20:36:42.340939 ** Bad device specification mmc 0 **
741 20:36:42.341469 Couldn't find partition mmc 0
742 20:36:42.345996 Error: could not access storage.
743 20:36:42.642401 Net: eth0: ethernet@ff3f0000
744 20:36:42.642981 starting USB...
745 20:36:42.887129 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 20:36:42.887705 Starting the controller
747 20:36:42.894009 USB XHCI 1.10
748 20:36:44.448710 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 20:36:44.456819 scanning usb for storage devices... 0 Storage Device(s) found
751 20:36:44.508296 Hit any key to stop autoboot: 1
752 20:36:44.509411 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 20:36:44.510059 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 20:36:44.510543 Setting prompt string to ['=>']
755 20:36:44.511032 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 20:36:44.522895 0
757 20:36:44.523839 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 20:36:44.625135 => setenv autoload no
760 20:36:44.625866 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 20:36:44.632014 setenv autoload no
763 20:36:44.733766 => setenv initrd_high 0xffffffff
764 20:36:44.734581 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 20:36:44.739351 setenv initrd_high 0xffffffff
767 20:36:44.841049 => setenv fdt_high 0xffffffff
768 20:36:44.841836 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 20:36:44.846462 setenv fdt_high 0xffffffff
771 20:36:44.948162 => dhcp
772 20:36:44.948960 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 20:36:44.952305 dhcp
774 20:36:45.508885 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
775 20:36:45.509688 Speed: 1000, full duplex
776 20:36:45.510227 BOOTP broadcast 1
777 20:36:45.757006 BOOTP broadcast 2
778 20:36:45.768585 DHCP client bound to address 192.168.6.21 (259 ms)
780 20:36:45.870268 => setenv serverip 192.168.6.2
781 20:36:45.871083 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
782 20:36:45.875697 setenv serverip 192.168.6.2
784 20:36:45.977452 => tftpboot 0x01080000 955534/tftp-deploy-cmi0ouuc/kernel/uImage
785 20:36:45.978299 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
786 20:36:45.985015 tftpboot 0x01080000 955534/tftp-deploy-cmi0ouuc/kernel/uImage
787 20:36:45.985617 Speed: 1000, full duplex
788 20:36:45.986143 Using ethernet@ff3f0000 device
789 20:36:45.990601 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
790 20:36:45.996180 Filename '955534/tftp-deploy-cmi0ouuc/kernel/uImage'.
791 20:36:45.999924 Load address: 0x1080000
792 20:36:49.030542 Loading: *################################################## 43.6 MiB
793 20:36:49.031170 14.4 MiB/s
794 20:36:49.031574 done
795 20:36:49.034935 Bytes transferred = 45713984 (2b98a40 hex)
797 20:36:49.136429 => tftpboot 0x08000000 955534/tftp-deploy-cmi0ouuc/ramdisk/ramdisk.cpio.gz.uboot
798 20:36:49.137194 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
799 20:36:49.144287 tftpboot 0x08000000 955534/tftp-deploy-cmi0ouuc/ramdisk/ramdisk.cpio.gz.uboot
800 20:36:49.144755 Speed: 1000, full duplex
801 20:36:49.145151 Using ethernet@ff3f0000 device
802 20:36:49.149661 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
803 20:36:49.159558 Filename '955534/tftp-deploy-cmi0ouuc/ramdisk/ramdisk.cpio.gz.uboot'.
804 20:36:49.160262 Load address: 0x8000000
805 20:36:50.826139 Loading: *################################################# UDP wrong checksum 00000005 000092db
806 20:36:55.827029 T UDP wrong checksum 00000005 000092db
807 20:36:55.877859 UDP wrong checksum 000000ff 0000c32f
808 20:36:55.954362 UDP wrong checksum 000000ff 00005e22
809 20:37:05.829043 T T UDP wrong checksum 00000005 000092db
810 20:37:25.833078 T T T T UDP wrong checksum 00000005 000092db
811 20:37:33.258237 T UDP wrong checksum 000000ff 0000fdd3
812 20:37:33.280712 UDP wrong checksum 000000ff 000091c6
813 20:37:37.611105 T UDP wrong checksum 000000ff 0000cf7c
814 20:37:37.650932 UDP wrong checksum 000000ff 00005f6f
815 20:37:38.631400 UDP wrong checksum 000000ff 0000d9bf
816 20:37:38.642715 UDP wrong checksum 000000ff 00006eb2
817 20:37:45.837801 T
818 20:37:45.838440 Retry count exceeded; starting again
820 20:37:45.839837 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
823 20:37:45.841700 end: 2.4 uboot-commands (duration 00:01:20) [common]
825 20:37:45.843030 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
827 20:37:45.844109 end: 2 uboot-action (duration 00:01:20) [common]
829 20:37:45.845677 Cleaning after the job
830 20:37:45.846253 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955534/tftp-deploy-cmi0ouuc/ramdisk
831 20:37:45.847424 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955534/tftp-deploy-cmi0ouuc/kernel
832 20:37:45.891176 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955534/tftp-deploy-cmi0ouuc/dtb
833 20:37:45.892023 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955534/tftp-deploy-cmi0ouuc/modules
834 20:37:45.912453 start: 4.1 power-off (timeout 00:00:30) [common]
835 20:37:45.913128 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
836 20:37:45.946983 >> OK - accepted request
837 20:37:45.949164 Returned 0 in 0 seconds
838 20:37:46.050264 end: 4.1 power-off (duration 00:00:00) [common]
840 20:37:46.051254 start: 4.2 read-feedback (timeout 00:10:00) [common]
841 20:37:46.051920 Listened to connection for namespace 'common' for up to 1s
842 20:37:47.052656 Finalising connection for namespace 'common'
843 20:37:47.053370 Disconnecting from shell: Finalise
844 20:37:47.053885 =>
845 20:37:47.154917 end: 4.2 read-feedback (duration 00:00:01) [common]
846 20:37:47.155573 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/955534
847 20:37:47.524166 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/955534
848 20:37:47.524775 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.