Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:39:52.398132 lava-dispatcher, installed at version: 2024.01
2 22:39:52.398933 start: 0 validate
3 22:39:52.399425 Start time: 2024-11-07 22:39:52.399394+00:00 (UTC)
4 22:39:52.400005 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:39:52.400544 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 22:39:52.443273 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:39:52.443860 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 22:39:52.475120 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:39:52.475784 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 22:39:52.510628 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:39:52.511156 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 22:39:52.550527 validate duration: 0.15
14 22:39:52.551583 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:39:52.552003 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:39:52.552403 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:39:52.553119 Not decompressing ramdisk as can be used compressed.
18 22:39:52.553640 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 22:39:52.553964 saving as /var/lib/lava/dispatcher/tmp/955478/tftp-deploy-02je9_co/ramdisk/rootfs.cpio.gz
20 22:39:52.554294 total size: 47897469 (45 MB)
21 22:39:52.589327 progress 0 % (0 MB)
22 22:39:52.620604 progress 5 % (2 MB)
23 22:39:52.651172 progress 10 % (4 MB)
24 22:39:52.681419 progress 15 % (6 MB)
25 22:39:52.711714 progress 20 % (9 MB)
26 22:39:52.741716 progress 25 % (11 MB)
27 22:39:52.772154 progress 30 % (13 MB)
28 22:39:52.802346 progress 35 % (16 MB)
29 22:39:52.832525 progress 40 % (18 MB)
30 22:39:52.862524 progress 45 % (20 MB)
31 22:39:52.892564 progress 50 % (22 MB)
32 22:39:52.922941 progress 55 % (25 MB)
33 22:39:52.953415 progress 60 % (27 MB)
34 22:39:52.983599 progress 65 % (29 MB)
35 22:39:53.013827 progress 70 % (32 MB)
36 22:39:53.043944 progress 75 % (34 MB)
37 22:39:53.073956 progress 80 % (36 MB)
38 22:39:53.103997 progress 85 % (38 MB)
39 22:39:53.134314 progress 90 % (41 MB)
40 22:39:53.163944 progress 95 % (43 MB)
41 22:39:53.192565 progress 100 % (45 MB)
42 22:39:53.193283 45 MB downloaded in 0.64 s (71.49 MB/s)
43 22:39:53.193824 end: 1.1.1 http-download (duration 00:00:01) [common]
45 22:39:53.194699 end: 1.1 download-retry (duration 00:00:01) [common]
46 22:39:53.194985 start: 1.2 download-retry (timeout 00:09:59) [common]
47 22:39:53.195250 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 22:39:53.195716 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/kernel/Image
49 22:39:53.195969 saving as /var/lib/lava/dispatcher/tmp/955478/tftp-deploy-02je9_co/kernel/Image
50 22:39:53.196203 total size: 45713920 (43 MB)
51 22:39:53.196411 No compression specified
52 22:39:53.242452 progress 0 % (0 MB)
53 22:39:53.271179 progress 5 % (2 MB)
54 22:39:53.300619 progress 10 % (4 MB)
55 22:39:53.329524 progress 15 % (6 MB)
56 22:39:53.358168 progress 20 % (8 MB)
57 22:39:53.386864 progress 25 % (10 MB)
58 22:39:53.424628 progress 30 % (13 MB)
59 22:39:53.456798 progress 35 % (15 MB)
60 22:39:53.485587 progress 40 % (17 MB)
61 22:39:53.514407 progress 45 % (19 MB)
62 22:39:53.543711 progress 50 % (21 MB)
63 22:39:53.572803 progress 55 % (24 MB)
64 22:39:53.601521 progress 60 % (26 MB)
65 22:39:53.629478 progress 65 % (28 MB)
66 22:39:53.658388 progress 70 % (30 MB)
67 22:39:53.686990 progress 75 % (32 MB)
68 22:39:53.715734 progress 80 % (34 MB)
69 22:39:53.744112 progress 85 % (37 MB)
70 22:39:53.772459 progress 90 % (39 MB)
71 22:39:53.800858 progress 95 % (41 MB)
72 22:39:53.828255 progress 100 % (43 MB)
73 22:39:53.828764 43 MB downloaded in 0.63 s (68.92 MB/s)
74 22:39:53.829246 end: 1.2.1 http-download (duration 00:00:01) [common]
76 22:39:53.830064 end: 1.2 download-retry (duration 00:00:01) [common]
77 22:39:53.830344 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:39:53.830609 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:39:53.831086 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 22:39:53.831330 saving as /var/lib/lava/dispatcher/tmp/955478/tftp-deploy-02je9_co/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 22:39:53.831539 total size: 53209 (0 MB)
82 22:39:53.831751 No compression specified
83 22:39:53.868828 progress 61 % (0 MB)
84 22:39:53.869664 progress 100 % (0 MB)
85 22:39:53.870218 0 MB downloaded in 0.04 s (1.31 MB/s)
86 22:39:53.870702 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:39:53.871538 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:39:53.871811 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:39:53.872112 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:39:53.872583 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/modules.tar.xz
92 22:39:53.872831 saving as /var/lib/lava/dispatcher/tmp/955478/tftp-deploy-02je9_co/modules/modules.tar
93 22:39:53.873045 total size: 11624536 (11 MB)
94 22:39:53.873263 Using unxz to decompress xz
95 22:39:53.908119 progress 0 % (0 MB)
96 22:39:53.975700 progress 5 % (0 MB)
97 22:39:54.052739 progress 10 % (1 MB)
98 22:39:54.154191 progress 15 % (1 MB)
99 22:39:54.247924 progress 20 % (2 MB)
100 22:39:54.334002 progress 25 % (2 MB)
101 22:39:54.414174 progress 30 % (3 MB)
102 22:39:54.496448 progress 35 % (3 MB)
103 22:39:54.571487 progress 40 % (4 MB)
104 22:39:54.647120 progress 45 % (5 MB)
105 22:39:54.731934 progress 50 % (5 MB)
106 22:39:54.813897 progress 55 % (6 MB)
107 22:39:54.894542 progress 60 % (6 MB)
108 22:39:54.975102 progress 65 % (7 MB)
109 22:39:55.064358 progress 70 % (7 MB)
110 22:39:55.146447 progress 75 % (8 MB)
111 22:39:55.225322 progress 80 % (8 MB)
112 22:39:55.307801 progress 85 % (9 MB)
113 22:39:55.392363 progress 90 % (10 MB)
114 22:39:55.471029 progress 95 % (10 MB)
115 22:39:55.545807 progress 100 % (11 MB)
116 22:39:55.560674 11 MB downloaded in 1.69 s (6.57 MB/s)
117 22:39:55.561343 end: 1.4.1 http-download (duration 00:00:02) [common]
119 22:39:55.562182 end: 1.4 download-retry (duration 00:00:02) [common]
120 22:39:55.562453 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 22:39:55.562721 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 22:39:55.562968 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:39:55.563223 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 22:39:55.563814 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj
125 22:39:55.564523 makedir: /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin
126 22:39:55.565222 makedir: /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/tests
127 22:39:55.565855 makedir: /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/results
128 22:39:55.566481 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-add-keys
129 22:39:55.567427 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-add-sources
130 22:39:55.568387 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-background-process-start
131 22:39:55.569324 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-background-process-stop
132 22:39:55.570548 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-common-functions
133 22:39:55.571445 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-echo-ipv4
134 22:39:55.572383 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-install-packages
135 22:39:55.573277 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-installed-packages
136 22:39:55.574170 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-os-build
137 22:39:55.575044 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-probe-channel
138 22:39:55.575913 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-probe-ip
139 22:39:55.576823 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-target-ip
140 22:39:55.577695 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-target-mac
141 22:39:55.578551 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-target-storage
142 22:39:55.579429 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-test-case
143 22:39:55.580324 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-test-event
144 22:39:55.581185 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-test-feedback
145 22:39:55.582052 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-test-raise
146 22:39:55.582943 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-test-reference
147 22:39:55.583845 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-test-runner
148 22:39:55.584762 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-test-set
149 22:39:55.585639 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-test-shell
150 22:39:55.586516 Updating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-install-packages (oe)
151 22:39:55.587454 Updating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/bin/lava-installed-packages (oe)
152 22:39:55.588276 Creating /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/environment
153 22:39:55.588966 LAVA metadata
154 22:39:55.589437 - LAVA_JOB_ID=955478
155 22:39:55.589863 - LAVA_DISPATCHER_IP=192.168.6.2
156 22:39:55.590514 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 22:39:55.592267 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 22:39:55.592840 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 22:39:55.593249 skipped lava-vland-overlay
160 22:39:55.593732 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 22:39:55.594232 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 22:39:55.594653 skipped lava-multinode-overlay
163 22:39:55.595132 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 22:39:55.595625 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 22:39:55.596117 Loading test definitions
166 22:39:55.596662 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 22:39:55.597094 Using /lava-955478 at stage 0
168 22:39:55.599348 uuid=955478_1.5.2.4.1 testdef=None
169 22:39:55.599941 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 22:39:55.600345 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 22:39:55.602121 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 22:39:55.602930 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 22:39:55.605203 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 22:39:55.606087 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 22:39:55.608264 runner path: /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/0/tests/0_igt-gpu-panfrost test_uuid 955478_1.5.2.4.1
178 22:39:55.608880 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 22:39:55.609709 Creating lava-test-runner.conf files
181 22:39:55.609918 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/955478/lava-overlay-les_c2aj/lava-955478/0 for stage 0
182 22:39:55.610267 - 0_igt-gpu-panfrost
183 22:39:55.610647 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 22:39:55.610936 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 22:39:55.640100 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 22:39:55.640639 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 22:39:55.640971 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 22:39:55.641307 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 22:39:55.641632 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 22:40:02.615339 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 22:40:02.616150 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 22:40:02.616791 extracting modules file /var/lib/lava/dispatcher/tmp/955478/tftp-deploy-02je9_co/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955478/extract-overlay-ramdisk-n0gm3m8o/ramdisk
193 22:40:04.367940 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 22:40:04.368564 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 22:40:04.368923 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955478/compress-overlay-x4nlm8tn/overlay-1.5.2.5.tar.gz to ramdisk
196 22:40:04.369185 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955478/compress-overlay-x4nlm8tn/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/955478/extract-overlay-ramdisk-n0gm3m8o/ramdisk
197 22:40:04.407688 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 22:40:04.408276 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 22:40:04.408636 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 22:40:04.408935 Converting downloaded kernel to a uImage
201 22:40:04.409317 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/955478/tftp-deploy-02je9_co/kernel/Image /var/lib/lava/dispatcher/tmp/955478/tftp-deploy-02je9_co/kernel/uImage
202 22:40:04.899469 output: Image Name:
203 22:40:04.899904 output: Created: Thu Nov 7 22:40:04 2024
204 22:40:04.900169 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 22:40:04.900413 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 22:40:04.900653 output: Load Address: 01080000
207 22:40:04.900897 output: Entry Point: 01080000
208 22:40:04.901130 output:
209 22:40:04.901515 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 22:40:04.901845 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 22:40:04.902171 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 22:40:04.902455 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 22:40:04.902730 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 22:40:04.903014 Building ramdisk /var/lib/lava/dispatcher/tmp/955478/extract-overlay-ramdisk-n0gm3m8o/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/955478/extract-overlay-ramdisk-n0gm3m8o/ramdisk
215 22:40:11.584087 >> 502380 blocks
216 22:40:32.277898 Adding RAMdisk u-boot header.
217 22:40:32.278352 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/955478/extract-overlay-ramdisk-n0gm3m8o/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/955478/extract-overlay-ramdisk-n0gm3m8o/ramdisk.cpio.gz.uboot
218 22:40:32.957774 output: Image Name:
219 22:40:32.958202 output: Created: Thu Nov 7 22:40:32 2024
220 22:40:32.958411 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 22:40:32.958615 output: Data Size: 65714715 Bytes = 64174.53 KiB = 62.67 MiB
222 22:40:32.958815 output: Load Address: 00000000
223 22:40:32.959014 output: Entry Point: 00000000
224 22:40:32.959210 output:
225 22:40:32.959853 rename /var/lib/lava/dispatcher/tmp/955478/extract-overlay-ramdisk-n0gm3m8o/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/955478/tftp-deploy-02je9_co/ramdisk/ramdisk.cpio.gz.uboot
226 22:40:32.960597 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 22:40:32.961215 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 22:40:32.961792 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 22:40:32.962303 No LXC device requested
230 22:40:32.962848 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 22:40:32.963400 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 22:40:32.963942 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 22:40:32.964431 Checking files for TFTP limit of 4294967296 bytes.
234 22:40:32.967326 end: 1 tftp-deploy (duration 00:00:40) [common]
235 22:40:32.967940 start: 2 uboot-action (timeout 00:05:00) [common]
236 22:40:32.968548 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 22:40:32.969091 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 22:40:32.969654 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 22:40:32.970222 Using kernel file from prepare-kernel: 955478/tftp-deploy-02je9_co/kernel/uImage
240 22:40:32.970877 substitutions:
241 22:40:32.971319 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 22:40:32.971761 - {DTB_ADDR}: 0x01070000
243 22:40:32.972236 - {DTB}: 955478/tftp-deploy-02je9_co/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 22:40:32.972675 - {INITRD}: 955478/tftp-deploy-02je9_co/ramdisk/ramdisk.cpio.gz.uboot
245 22:40:32.973110 - {KERNEL_ADDR}: 0x01080000
246 22:40:32.973537 - {KERNEL}: 955478/tftp-deploy-02je9_co/kernel/uImage
247 22:40:32.973969 - {LAVA_MAC}: None
248 22:40:32.974441 - {PRESEED_CONFIG}: None
249 22:40:32.974874 - {PRESEED_LOCAL}: None
250 22:40:32.975301 - {RAMDISK_ADDR}: 0x08000000
251 22:40:32.975727 - {RAMDISK}: 955478/tftp-deploy-02je9_co/ramdisk/ramdisk.cpio.gz.uboot
252 22:40:32.976200 - {ROOT_PART}: None
253 22:40:32.976627 - {ROOT}: None
254 22:40:32.977058 - {SERVER_IP}: 192.168.6.2
255 22:40:32.977491 - {TEE_ADDR}: 0x83000000
256 22:40:32.977916 - {TEE}: None
257 22:40:32.978344 Parsed boot commands:
258 22:40:32.978756 - setenv autoload no
259 22:40:32.979179 - setenv initrd_high 0xffffffff
260 22:40:32.979603 - setenv fdt_high 0xffffffff
261 22:40:32.980047 - dhcp
262 22:40:32.980479 - setenv serverip 192.168.6.2
263 22:40:32.980903 - tftpboot 0x01080000 955478/tftp-deploy-02je9_co/kernel/uImage
264 22:40:32.981332 - tftpboot 0x08000000 955478/tftp-deploy-02je9_co/ramdisk/ramdisk.cpio.gz.uboot
265 22:40:32.981759 - tftpboot 0x01070000 955478/tftp-deploy-02je9_co/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 22:40:32.982185 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 22:40:32.982616 - bootm 0x01080000 0x08000000 0x01070000
268 22:40:32.983151 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 22:40:32.984790 start: 2.3 connect-device (timeout 00:05:00) [common]
271 22:40:32.985272 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 22:40:33.000448 Setting prompt string to ['lava-test: # ']
273 22:40:33.002033 end: 2.3 connect-device (duration 00:00:00) [common]
274 22:40:33.002681 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 22:40:33.003363 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 22:40:33.004009 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 22:40:33.005321 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 22:40:33.043545 >> OK - accepted request
279 22:40:33.045605 Returned 0 in 0 seconds
280 22:40:33.146783 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 22:40:33.148550 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 22:40:33.149168 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 22:40:33.149716 Setting prompt string to ['Hit any key to stop autoboot']
285 22:40:33.150214 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 22:40:33.151901 Trying 192.168.56.21...
287 22:40:33.152462 Connected to conserv1.
288 22:40:33.152911 Escape character is '^]'.
289 22:40:33.153368
290 22:40:33.153834 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 22:40:33.154307
292 22:40:41.260092 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 22:40:41.260544 bl2_stage_init 0x01
294 22:40:41.260795 bl2_stage_init 0x81
295 22:40:41.265493 hw id: 0x0000 - pwm id 0x01
296 22:40:41.265816 bl2_stage_init 0xc1
297 22:40:41.270998 bl2_stage_init 0x02
298 22:40:41.271307
299 22:40:41.271545 L0:00000000
300 22:40:41.271759 L1:00000703
301 22:40:41.271974 L2:00008067
302 22:40:41.272222 L3:15000000
303 22:40:41.276727 S1:00000000
304 22:40:41.277038 B2:20282000
305 22:40:41.277274 B1:a0f83180
306 22:40:41.277484
307 22:40:41.277690 TE: 68113
308 22:40:41.277896
309 22:40:41.282264 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 22:40:41.282552
311 22:40:41.287754 Board ID = 1
312 22:40:41.288069 Set cpu clk to 24M
313 22:40:41.288303 Set clk81 to 24M
314 22:40:41.293333 Use GP1_pll as DSU clk.
315 22:40:41.293619 DSU clk: 1200 Mhz
316 22:40:41.293849 CPU clk: 1200 MHz
317 22:40:41.298958 Set clk81 to 166.6M
318 22:40:41.304612 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 22:40:41.304941 board id: 1
320 22:40:41.311663 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 22:40:41.322575 fw parse done
322 22:40:41.328524 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 22:40:41.371809 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 22:40:41.383631 PIEI prepare done
325 22:40:41.383999 fastboot data load
326 22:40:41.384230 fastboot data verify
327 22:40:41.390833 verify result: 266
328 22:40:41.396253 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 22:40:41.396561 LPDDR4 probe
330 22:40:41.396794 ddr clk to 1584MHz
331 22:40:41.402415 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 22:40:41.439853
333 22:40:41.440290 dmc_version 0001
334 22:40:41.446902 Check phy result
335 22:40:41.452750 INFO : End of CA training
336 22:40:41.453075 INFO : End of initialization
337 22:40:41.458375 INFO : Training has run successfully!
338 22:40:41.458692 Check phy result
339 22:40:41.463957 INFO : End of initialization
340 22:40:41.464292 INFO : End of read enable training
341 22:40:41.467224 INFO : End of fine write leveling
342 22:40:41.472856 INFO : End of Write leveling coarse delay
343 22:40:41.478489 INFO : Training has run successfully!
344 22:40:41.478801 Check phy result
345 22:40:41.479017 INFO : End of initialization
346 22:40:41.484100 INFO : End of read dq deskew training
347 22:40:41.487385 INFO : End of MPR read delay center optimization
348 22:40:41.493020 INFO : End of write delay center optimization
349 22:40:41.498601 INFO : End of read delay center optimization
350 22:40:41.498926 INFO : End of max read latency training
351 22:40:41.504241 INFO : Training has run successfully!
352 22:40:41.504570 1D training succeed
353 22:40:41.512378 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 22:40:41.560720 Check phy result
355 22:40:41.561123 INFO : End of initialization
356 22:40:41.588111 INFO : End of 2D read delay Voltage center optimization
357 22:40:41.612313 INFO : End of 2D read delay Voltage center optimization
358 22:40:41.667957 INFO : End of 2D write delay Voltage center optimization
359 22:40:41.723023 INFO : End of 2D write delay Voltage center optimization
360 22:40:41.728548 INFO : Training has run successfully!
361 22:40:41.728890
362 22:40:41.729115 channel==0
363 22:40:41.734170 RxClkDly_Margin_A0==69 ps 7
364 22:40:41.734545 TxDqDly_Margin_A0==98 ps 10
365 22:40:41.737435 RxClkDly_Margin_A1==88 ps 9
366 22:40:41.737684 TxDqDly_Margin_A1==98 ps 10
367 22:40:41.743016 TrainedVREFDQ_A0==74
368 22:40:41.743385 TrainedVREFDQ_A1==75
369 22:40:41.748517 VrefDac_Margin_A0==24
370 22:40:41.748867 DeviceVref_Margin_A0==40
371 22:40:41.749107 VrefDac_Margin_A1==23
372 22:40:41.754110 DeviceVref_Margin_A1==39
373 22:40:41.754514
374 22:40:41.754756
375 22:40:41.754979 channel==1
376 22:40:41.755206 RxClkDly_Margin_A0==78 ps 8
377 22:40:41.759827 TxDqDly_Margin_A0==98 ps 10
378 22:40:41.760245 RxClkDly_Margin_A1==78 ps 8
379 22:40:41.765391 TxDqDly_Margin_A1==88 ps 9
380 22:40:41.765760 TrainedVREFDQ_A0==78
381 22:40:41.765993 TrainedVREFDQ_A1==75
382 22:40:41.770911 VrefDac_Margin_A0==22
383 22:40:41.771270 DeviceVref_Margin_A0==36
384 22:40:41.776457 VrefDac_Margin_A1==22
385 22:40:41.776758 DeviceVref_Margin_A1==39
386 22:40:41.776980
387 22:40:41.782051 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 22:40:41.782369
389 22:40:41.809986 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 22:40:41.815563 2D training succeed
391 22:40:41.821186 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 22:40:41.821475 auto size-- 65535DDR cs0 size: 2048MB
393 22:40:41.826797 DDR cs1 size: 2048MB
394 22:40:41.827086 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 22:40:41.832426 cs0 DataBus test pass
396 22:40:41.832731 cs1 DataBus test pass
397 22:40:41.832956 cs0 AddrBus test pass
398 22:40:41.838131 cs1 AddrBus test pass
399 22:40:41.838435
400 22:40:41.838671 100bdlr_step_size ps== 471
401 22:40:41.838904 result report
402 22:40:41.843574 boot times 0Enable ddr reg access
403 22:40:41.851301 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 22:40:41.864885 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 22:40:42.525802 bl2z: ptr: 05129330, size: 00001e40
406 22:40:42.534677 0.0;M3 CHK:0;cm4_sp_mode 0
407 22:40:42.535044 MVN_1=0x00000000
408 22:40:42.535269 MVN_2=0x00000000
409 22:40:42.546158 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 22:40:42.546505 OPS=0x04
411 22:40:42.546745 ring efuse init
412 22:40:42.551753 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 22:40:42.552080 [0.017355 Inits done]
414 22:40:42.552304 secure task start!
415 22:40:42.559743 high task start!
416 22:40:42.560112 low task start!
417 22:40:42.560330 run into bl31
418 22:40:42.568403 NOTICE: BL31: v1.3(release):4fc40b1
419 22:40:42.576138 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 22:40:42.576434 NOTICE: BL31: G12A normal boot!
421 22:40:42.591663 NOTICE: BL31: BL33 decompress pass
422 22:40:42.599177 ERROR: Error initializing runtime service opteed_fast
423 22:40:43.809039 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 22:40:43.809435 bl2_stage_init 0x01
425 22:40:43.809649 bl2_stage_init 0x81
426 22:40:43.814652 hw id: 0x0000 - pwm id 0x01
427 22:40:43.815191 bl2_stage_init 0xc1
428 22:40:43.819882 bl2_stage_init 0x02
429 22:40:43.820357
430 22:40:43.820754 L0:00000000
431 22:40:43.821142 L1:00000703
432 22:40:43.821523 L2:00008067
433 22:40:43.821905 L3:15000000
434 22:40:43.825464 S1:00000000
435 22:40:43.825881 B2:20282000
436 22:40:43.826270 B1:a0f83180
437 22:40:43.826650
438 22:40:43.827035 TE: 68480
439 22:40:43.827418
440 22:40:43.831036 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 22:40:43.836660
442 22:40:43.837079 Board ID = 1
443 22:40:43.837465 Set cpu clk to 24M
444 22:40:43.837846 Set clk81 to 24M
445 22:40:43.842328 Use GP1_pll as DSU clk.
446 22:40:43.842767 DSU clk: 1200 Mhz
447 22:40:43.843153 CPU clk: 1200 MHz
448 22:40:43.847874 Set clk81 to 166.6M
449 22:40:43.853496 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 22:40:43.853919 board id: 1
451 22:40:43.861002 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 22:40:43.871656 fw parse done
453 22:40:43.877633 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 22:40:43.920349 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 22:40:43.931217 PIEI prepare done
456 22:40:43.931664 fastboot data load
457 22:40:43.932096 fastboot data verify
458 22:40:43.936808 verify result: 266
459 22:40:43.942446 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 22:40:43.942873 LPDDR4 probe
461 22:40:43.943260 ddr clk to 1584MHz
462 22:40:45.310739 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 22:40:45.311389 bl2_stage_init 0x01
464 22:40:45.311817 bl2_stage_init 0x81
465 22:40:45.316141 hw id: 0x0000 - pwm id 0x01
466 22:40:45.316592 bl2_stage_init 0xc1
467 22:40:45.321286 bl2_stage_init 0x02
468 22:40:45.321721
469 22:40:45.322128 L0:00000000
470 22:40:45.322526 L1:00000703
471 22:40:45.322928 L2:00008067
472 22:40:45.326879 L3:15000000
473 22:40:45.327352 S1:00000000
474 22:40:45.327756 B2:20282000
475 22:40:45.328187 B1:a0f83180
476 22:40:45.328587
477 22:40:45.328985 TE: 70314
478 22:40:45.329378
479 22:40:45.332467 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 22:40:45.338035
481 22:40:45.338469 Board ID = 1
482 22:40:45.338872 Set cpu clk to 24M
483 22:40:45.339268 Set clk81 to 24M
484 22:40:45.343653 Use GP1_pll as DSU clk.
485 22:40:45.344102 DSU clk: 1200 Mhz
486 22:40:45.344507 CPU clk: 1200 MHz
487 22:40:45.349271 Set clk81 to 166.6M
488 22:40:45.354877 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 22:40:45.355318 board id: 1
490 22:40:45.362499 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 22:40:45.373192 fw parse done
492 22:40:45.379138 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 22:40:45.421783 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 22:40:45.433131 PIEI prepare done
495 22:40:45.433602 fastboot data load
496 22:40:45.434013 fastboot data verify
497 22:40:45.438366 verify result: 266
498 22:40:45.443972 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 22:40:45.444459 LPDDR4 probe
500 22:40:45.444867 ddr clk to 1584MHz
501 22:40:45.452078 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 22:40:45.489192
503 22:40:45.489885 dmc_version 0001
504 22:40:45.495821 Check phy result
505 22:40:45.501746 INFO : End of CA training
506 22:40:45.502099 INFO : End of initialization
507 22:40:45.507339 INFO : Training has run successfully!
508 22:40:45.507725 Check phy result
509 22:40:45.512933 INFO : End of initialization
510 22:40:45.513280 INFO : End of read enable training
511 22:40:45.518510 INFO : End of fine write leveling
512 22:40:45.524171 INFO : End of Write leveling coarse delay
513 22:40:45.524529 INFO : Training has run successfully!
514 22:40:45.524812 Check phy result
515 22:40:45.529763 INFO : End of initialization
516 22:40:45.530107 INFO : End of read dq deskew training
517 22:40:45.535337 INFO : End of MPR read delay center optimization
518 22:40:45.540952 INFO : End of write delay center optimization
519 22:40:45.546565 INFO : End of read delay center optimization
520 22:40:45.546911 INFO : End of max read latency training
521 22:40:45.552158 INFO : Training has run successfully!
522 22:40:45.552523 1D training succeed
523 22:40:45.561319 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 22:40:45.608900 Check phy result
525 22:40:45.609301 INFO : End of initialization
526 22:40:45.631273 INFO : End of 2D read delay Voltage center optimization
527 22:40:45.650591 INFO : End of 2D read delay Voltage center optimization
528 22:40:45.702451 INFO : End of 2D write delay Voltage center optimization
529 22:40:45.751538 INFO : End of 2D write delay Voltage center optimization
530 22:40:45.757091 INFO : Training has run successfully!
531 22:40:45.757427
532 22:40:45.757686 channel==0
533 22:40:45.762694 RxClkDly_Margin_A0==88 ps 9
534 22:40:45.763010 TxDqDly_Margin_A0==88 ps 9
535 22:40:45.768244 RxClkDly_Margin_A1==88 ps 9
536 22:40:45.768575 TxDqDly_Margin_A1==88 ps 9
537 22:40:45.768818 TrainedVREFDQ_A0==74
538 22:40:45.773851 TrainedVREFDQ_A1==74
539 22:40:45.774159 VrefDac_Margin_A0==22
540 22:40:45.774531 DeviceVref_Margin_A0==40
541 22:40:45.779608 VrefDac_Margin_A1==22
542 22:40:45.780177 DeviceVref_Margin_A1==40
543 22:40:45.780646
544 22:40:45.781096
545 22:40:45.781539 channel==1
546 22:40:45.785204 RxClkDly_Margin_A0==78 ps 8
547 22:40:45.785735 TxDqDly_Margin_A0==98 ps 10
548 22:40:45.790879 RxClkDly_Margin_A1==88 ps 9
549 22:40:45.791421 TxDqDly_Margin_A1==88 ps 9
550 22:40:45.796522 TrainedVREFDQ_A0==75
551 22:40:45.797101 TrainedVREFDQ_A1==78
552 22:40:45.797582 VrefDac_Margin_A0==22
553 22:40:45.802028 DeviceVref_Margin_A0==39
554 22:40:45.802571 VrefDac_Margin_A1==22
555 22:40:45.803026 DeviceVref_Margin_A1==36
556 22:40:45.807578
557 22:40:45.808173 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 22:40:45.808669
559 22:40:45.841145 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000016 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
560 22:40:45.841757 2D training succeed
561 22:40:45.846861 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 22:40:45.852368 auto size-- 65535DDR cs0 size: 2048MB
563 22:40:45.852919 DDR cs1 size: 2048MB
564 22:40:45.858069 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 22:40:45.858652 cs0 DataBus test pass
566 22:40:45.863625 cs1 DataBus test pass
567 22:40:45.864193 cs0 AddrBus test pass
568 22:40:45.864659 cs1 AddrBus test pass
569 22:40:45.865104
570 22:40:45.869206 100bdlr_step_size ps== 478
571 22:40:45.869748 result report
572 22:40:45.874882 boot times 0Enable ddr reg access
573 22:40:45.879930 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 22:40:45.893694 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 22:40:46.548987 bl2z: ptr: 05129330, size: 00001e40
576 22:40:46.556372 0.0;M3 CHK:0;cm4_sp_mode 0
577 22:40:46.557015 MVN_1=0x00000000
578 22:40:46.557522 MVN_2=0x00000000
579 22:40:46.568055 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 22:40:46.568414 OPS=0x04
581 22:40:46.568645 ring efuse init
582 22:40:46.570771 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 22:40:46.576655 [0.017319 Inits done]
584 22:40:46.577081 secure task start!
585 22:40:46.577415 high task start!
586 22:40:46.577731 low task start!
587 22:40:46.580672 run into bl31
588 22:40:46.589335 NOTICE: BL31: v1.3(release):4fc40b1
589 22:40:46.597146 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 22:40:46.597429 NOTICE: BL31: G12A normal boot!
591 22:40:46.612766 NOTICE: BL31: BL33 decompress pass
592 22:40:46.618470 ERROR: Error initializing runtime service opteed_fast
593 22:40:47.862895 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 22:40:47.863578 bl2_stage_init 0x01
595 22:40:47.864115 bl2_stage_init 0x81
596 22:40:47.868443 hw id: 0x0000 - pwm id 0x01
597 22:40:47.868985 bl2_stage_init 0xc1
598 22:40:47.874131 bl2_stage_init 0x02
599 22:40:47.874659
600 22:40:47.875138 L0:00000000
601 22:40:47.875604 L1:00000703
602 22:40:47.876109 L2:00008067
603 22:40:47.876581 L3:15000000
604 22:40:47.879686 S1:00000000
605 22:40:47.880246 B2:20282000
606 22:40:47.880728 B1:a0f83180
607 22:40:47.881188
608 22:40:47.881651 TE: 70952
609 22:40:47.882111
610 22:40:47.885293 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 22:40:47.885822
612 22:40:47.891147 Board ID = 1
613 22:40:47.891684 Set cpu clk to 24M
614 22:40:47.892208 Set clk81 to 24M
615 22:40:47.896441 Use GP1_pll as DSU clk.
616 22:40:47.896975 DSU clk: 1200 Mhz
617 22:40:47.897445 CPU clk: 1200 MHz
618 22:40:47.902143 Set clk81 to 166.6M
619 22:40:47.907653 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 22:40:47.908220 board id: 1
621 22:40:47.915049 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 22:40:47.925650 fw parse done
623 22:40:47.931617 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 22:40:47.974717 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 22:40:47.985980 PIEI prepare done
626 22:40:47.986511 fastboot data load
627 22:40:47.986962 fastboot data verify
628 22:40:47.991493 verify result: 266
629 22:40:47.997196 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 22:40:47.997715 LPDDR4 probe
631 22:40:47.998160 ddr clk to 1584MHz
632 22:40:48.005122 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 22:40:48.043062
634 22:40:48.043967 dmc_version 0001
635 22:40:48.049939 Check phy result
636 22:40:48.056052 INFO : End of CA training
637 22:40:48.056900 INFO : End of initialization
638 22:40:48.061696 INFO : Training has run successfully!
639 22:40:48.062460 Check phy result
640 22:40:48.067172 INFO : End of initialization
641 22:40:48.067930 INFO : End of read enable training
642 22:40:48.070490 INFO : End of fine write leveling
643 22:40:48.076082 INFO : End of Write leveling coarse delay
644 22:40:48.081671 INFO : Training has run successfully!
645 22:40:48.082422 Check phy result
646 22:40:48.083073 INFO : End of initialization
647 22:40:48.087391 INFO : End of read dq deskew training
648 22:40:48.092895 INFO : End of MPR read delay center optimization
649 22:40:48.093638 INFO : End of write delay center optimization
650 22:40:48.098478 INFO : End of read delay center optimization
651 22:40:48.104129 INFO : End of max read latency training
652 22:40:48.104877 INFO : Training has run successfully!
653 22:40:48.109696 1D training succeed
654 22:40:48.115770 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 22:40:48.163810 Check phy result
656 22:40:48.164715 INFO : End of initialization
657 22:40:48.191253 INFO : End of 2D read delay Voltage center optimization
658 22:40:48.215423 INFO : End of 2D read delay Voltage center optimization
659 22:40:48.272154 INFO : End of 2D write delay Voltage center optimization
660 22:40:48.325975 INFO : End of 2D write delay Voltage center optimization
661 22:40:48.331598 INFO : Training has run successfully!
662 22:40:48.332414
663 22:40:48.333123 channel==0
664 22:40:48.337134 RxClkDly_Margin_A0==78 ps 8
665 22:40:48.337885 TxDqDly_Margin_A0==98 ps 10
666 22:40:48.342822 RxClkDly_Margin_A1==88 ps 9
667 22:40:48.343561 TxDqDly_Margin_A1==98 ps 10
668 22:40:48.344316 TrainedVREFDQ_A0==74
669 22:40:48.348369 TrainedVREFDQ_A1==75
670 22:40:48.349055 VrefDac_Margin_A0==23
671 22:40:48.349749 DeviceVref_Margin_A0==40
672 22:40:48.353834 VrefDac_Margin_A1==23
673 22:40:48.354562 DeviceVref_Margin_A1==39
674 22:40:48.355253
675 22:40:48.355896
676 22:40:48.359416 channel==1
677 22:40:48.359920 RxClkDly_Margin_A0==88 ps 9
678 22:40:48.360410 TxDqDly_Margin_A0==98 ps 10
679 22:40:48.365010 RxClkDly_Margin_A1==78 ps 8
680 22:40:48.365500 TxDqDly_Margin_A1==88 ps 9
681 22:40:48.370618 TrainedVREFDQ_A0==78
682 22:40:48.371102 TrainedVREFDQ_A1==75
683 22:40:48.371557 VrefDac_Margin_A0==22
684 22:40:48.376234 DeviceVref_Margin_A0==36
685 22:40:48.376761 VrefDac_Margin_A1==22
686 22:40:48.381795 DeviceVref_Margin_A1==39
687 22:40:48.382297
688 22:40:48.382761 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 22:40:48.383214
690 22:40:48.415420 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
691 22:40:48.416096 2D training succeed
692 22:40:48.420962 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 22:40:48.426613 auto size-- 65535DDR cs0 size: 2048MB
694 22:40:48.427131 DDR cs1 size: 2048MB
695 22:40:48.432200 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 22:40:48.432742 cs0 DataBus test pass
697 22:40:48.437774 cs1 DataBus test pass
698 22:40:48.438284 cs0 AddrBus test pass
699 22:40:48.438738 cs1 AddrBus test pass
700 22:40:48.439182
701 22:40:48.443384 100bdlr_step_size ps== 485
702 22:40:48.443905 result report
703 22:40:48.448963 boot times 0Enable ddr reg access
704 22:40:48.454253 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 22:40:48.468196 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 22:40:49.127762 bl2z: ptr: 05129330, size: 00001e40
707 22:40:49.135423 0.0;M3 CHK:0;cm4_sp_mode 0
708 22:40:49.136031 MVN_1=0x00000000
709 22:40:49.136478 MVN_2=0x00000000
710 22:40:49.146907 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 22:40:49.147484 OPS=0x04
712 22:40:49.147924 ring efuse init
713 22:40:49.152454 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 22:40:49.152950 [0.017354 Inits done]
715 22:40:49.153381 secure task start!
716 22:40:49.158782 high task start!
717 22:40:49.159278 low task start!
718 22:40:49.159709 run into bl31
719 22:40:49.168339 NOTICE: BL31: v1.3(release):4fc40b1
720 22:40:49.176158 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 22:40:49.176640 NOTICE: BL31: G12A normal boot!
722 22:40:49.191727 NOTICE: BL31: BL33 decompress pass
723 22:40:49.197397 ERROR: Error initializing runtime service opteed_fast
724 22:40:49.992771
725 22:40:49.993432
726 22:40:49.998173 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 22:40:49.998677
728 22:40:50.000745 Model: Libre Computer AML-S905D3-CC Solitude
729 22:40:50.148700 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 22:40:50.164091 DRAM: 2 GiB (effective 3.8 GiB)
731 22:40:50.264985 Core: 406 devices, 33 uclasses, devicetree: separate
732 22:40:50.270856 WDT: Not starting watchdog@f0d0
733 22:40:50.295938 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 22:40:50.308165 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 22:40:50.313192 ** Bad device specification mmc 0 **
736 22:40:50.323187 Card did not respond to voltage select! : -110
737 22:40:50.330831 ** Bad device specification mmc 0 **
738 22:40:50.331319 Couldn't find partition mmc 0
739 22:40:50.339160 Card did not respond to voltage select! : -110
740 22:40:50.344667 ** Bad device specification mmc 0 **
741 22:40:50.345137 Couldn't find partition mmc 0
742 22:40:50.349742 Error: could not access storage.
743 22:40:50.646210 Net: eth0: ethernet@ff3f0000
744 22:40:50.646849 starting USB...
745 22:40:50.890886 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 22:40:50.891488 Starting the controller
747 22:40:50.897813 USB XHCI 1.10
748 22:40:52.452146 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 22:40:52.460372 scanning usb for storage devices... 0 Storage Device(s) found
751 22:40:52.511957 Hit any key to stop autoboot: 1
752 22:40:52.512916 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 22:40:52.513565 start: 2.4.3 bootloader-commands (timeout 00:04:40) [common]
754 22:40:52.514100 Setting prompt string to ['=>']
755 22:40:52.514623 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:40)
756 22:40:52.526444 0
757 22:40:52.527394 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 22:40:52.628694 => setenv autoload no
760 22:40:52.629398 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
761 22:40:52.634646 setenv autoload no
763 22:40:52.736188 => setenv initrd_high 0xffffffff
764 22:40:52.736975 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
765 22:40:52.741291 setenv initrd_high 0xffffffff
767 22:40:52.842861 => setenv fdt_high 0xffffffff
768 22:40:52.843683 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
769 22:40:52.847941 setenv fdt_high 0xffffffff
771 22:40:52.949553 => dhcp
772 22:40:52.950321 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
773 22:40:52.954366 dhcp
774 22:40:53.710207 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 22:40:53.710845 Speed: 1000, full duplex
776 22:40:53.711292 BOOTP broadcast 1
777 22:40:53.958639 BOOTP broadcast 2
778 22:40:53.971320 DHCP client bound to address 192.168.6.21 (260 ms)
780 22:40:54.072826 => setenv serverip 192.168.6.2
781 22:40:54.073481 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
782 22:40:54.077927 setenv serverip 192.168.6.2
784 22:40:54.179433 => tftpboot 0x01080000 955478/tftp-deploy-02je9_co/kernel/uImage
785 22:40:54.180232 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
786 22:40:54.186761 tftpboot 0x01080000 955478/tftp-deploy-02je9_co/kernel/uImage
787 22:40:54.187249 Speed: 1000, full duplex
788 22:40:54.187687 Using ethernet@ff3f0000 device
789 22:40:54.192388 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
790 22:40:54.198142 Filename '955478/tftp-deploy-02je9_co/kernel/uImage'.
791 22:40:54.201707 Load address: 0x1080000
792 22:40:55.567782 Loading: *######################## UDP wrong checksum 000000ff 0000eaf4
793 22:40:55.616850 # UDP wrong checksum 000000ff 000085e7
794 22:40:57.019351 ######################### 43.6 MiB
795 22:40:57.020044 15.5 MiB/s
796 22:40:57.020502 done
797 22:40:57.023721 Bytes transferred = 45713984 (2b98a40 hex)
799 22:40:57.125301 => tftpboot 0x08000000 955478/tftp-deploy-02je9_co/ramdisk/ramdisk.cpio.gz.uboot
800 22:40:57.125958 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
801 22:40:57.132577 tftpboot 0x08000000 955478/tftp-deploy-02je9_co/ramdisk/ramdisk.cpio.gz.uboot
802 22:40:57.133057 Speed: 1000, full duplex
803 22:40:57.133498 Using ethernet@ff3f0000 device
804 22:40:57.138129 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
805 22:40:57.147956 Filename '955478/tftp-deploy-02je9_co/ramdisk/ramdisk.cpio.gz.uboot'.
806 22:40:57.148468 Load address: 0x8000000
807 22:41:04.388148 Loading: *##########################T # UDP wrong checksum 000000ff 0000627b
808 22:41:04.418701 UDP wrong checksum 000000ff 000046ab
809 22:41:04.429171 UDP wrong checksum 000000ff 0000fb6d
810 22:41:04.456569 UDP wrong checksum 000000ff 0000e29d
811 22:41:06.606703 ###################### UDP wrong checksum 0000000f 0000d34c
812 22:41:11.608073 T UDP wrong checksum 0000000f 0000d34c
813 22:41:20.820915 T UDP wrong checksum 000000ff 00002a0a
814 22:41:20.831109 UDP wrong checksum 000000ff 0000bdfc
815 22:41:21.609897 T UDP wrong checksum 0000000f 0000d34c
816 22:41:26.310107 UDP wrong checksum 000000ff 000039b8
817 22:41:26.360063 UDP wrong checksum 000000ff 0000c4aa
818 22:41:41.612547 T T T UDP wrong checksum 0000000f 0000d34c
819 22:41:49.333428 T T UDP wrong checksum 000000ff 00007700
820 22:41:49.349842 UDP wrong checksum 000000ff 00000df3
821 22:41:56.617629 T
822 22:41:56.618303 Retry count exceeded; starting again
824 22:41:56.619824 end: 2.4.3 bootloader-commands (duration 00:01:04) [common]
827 22:41:56.621858 end: 2.4 uboot-commands (duration 00:01:24) [common]
829 22:41:56.623365 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
831 22:41:56.624525 end: 2 uboot-action (duration 00:01:24) [common]
833 22:41:56.626236 Cleaning after the job
834 22:41:56.626841 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955478/tftp-deploy-02je9_co/ramdisk
835 22:41:56.628251 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955478/tftp-deploy-02je9_co/kernel
836 22:41:56.659932 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955478/tftp-deploy-02je9_co/dtb
837 22:41:56.661507 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955478/tftp-deploy-02je9_co/modules
838 22:41:56.668308 start: 4.1 power-off (timeout 00:00:30) [common]
839 22:41:56.669349 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
840 22:41:56.707643 >> OK - accepted request
841 22:41:56.709951 Returned 0 in 0 seconds
842 22:41:56.811179 end: 4.1 power-off (duration 00:00:00) [common]
844 22:41:56.813061 start: 4.2 read-feedback (timeout 00:10:00) [common]
845 22:41:56.814288 Listened to connection for namespace 'common' for up to 1s
846 22:41:57.814623 Finalising connection for namespace 'common'
847 22:41:57.815415 Disconnecting from shell: Finalise
848 22:41:57.816031 =>
849 22:41:57.917172 end: 4.2 read-feedback (duration 00:00:01) [common]
850 22:41:57.917930 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/955478
851 22:41:58.605361 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/955478
852 22:41:58.606009 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.