Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:22:51.795273 lava-dispatcher, installed at version: 2024.01
2 22:22:51.796155 start: 0 validate
3 22:22:51.796608 Start time: 2024-11-07 22:22:51.796578+00:00 (UTC)
4 22:22:51.797110 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:22:51.797636 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:22:51.840504 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:22:51.841190 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 22:22:51.874271 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:22:51.875515 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 22:22:51.910012 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:22:51.910578 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:22:51.944507 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 22:22:51.945030 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 22:22:51.985857 validate duration: 0.19
16 22:22:51.986824 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:22:51.987214 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:22:51.987609 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:22:51.988255 Not decompressing ramdisk as can be used compressed.
20 22:22:51.988766 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 22:22:51.989100 saving as /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/ramdisk/initrd.cpio.gz
22 22:22:51.989417 total size: 5628169 (5 MB)
23 22:22:52.033805 progress 0 % (0 MB)
24 22:22:52.038096 progress 5 % (0 MB)
25 22:22:52.042392 progress 10 % (0 MB)
26 22:22:52.046253 progress 15 % (0 MB)
27 22:22:52.050412 progress 20 % (1 MB)
28 22:22:52.054601 progress 25 % (1 MB)
29 22:22:52.059525 progress 30 % (1 MB)
30 22:22:52.064101 progress 35 % (1 MB)
31 22:22:52.068121 progress 40 % (2 MB)
32 22:22:52.072878 progress 45 % (2 MB)
33 22:22:52.076830 progress 50 % (2 MB)
34 22:22:52.080864 progress 55 % (2 MB)
35 22:22:52.085015 progress 60 % (3 MB)
36 22:22:52.088649 progress 65 % (3 MB)
37 22:22:52.092640 progress 70 % (3 MB)
38 22:22:52.096244 progress 75 % (4 MB)
39 22:22:52.100272 progress 80 % (4 MB)
40 22:22:52.103842 progress 85 % (4 MB)
41 22:22:52.107847 progress 90 % (4 MB)
42 22:22:52.111734 progress 95 % (5 MB)
43 22:22:52.115174 progress 100 % (5 MB)
44 22:22:52.115856 5 MB downloaded in 0.13 s (42.46 MB/s)
45 22:22:52.116431 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:22:52.117430 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:22:52.117727 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:22:52.117997 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:22:52.118768 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/kernel/Image
51 22:22:52.119060 saving as /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/kernel/Image
52 22:22:52.119276 total size: 45713920 (43 MB)
53 22:22:52.119492 No compression specified
54 22:22:52.161573 progress 0 % (0 MB)
55 22:22:52.201689 progress 5 % (2 MB)
56 22:22:52.243222 progress 10 % (4 MB)
57 22:22:52.280500 progress 15 % (6 MB)
58 22:22:52.311421 progress 20 % (8 MB)
59 22:22:52.344998 progress 25 % (10 MB)
60 22:22:52.375646 progress 30 % (13 MB)
61 22:22:52.407012 progress 35 % (15 MB)
62 22:22:52.439405 progress 40 % (17 MB)
63 22:22:52.470184 progress 45 % (19 MB)
64 22:22:52.501225 progress 50 % (21 MB)
65 22:22:52.536011 progress 55 % (24 MB)
66 22:22:52.568581 progress 60 % (26 MB)
67 22:22:52.598249 progress 65 % (28 MB)
68 22:22:52.627996 progress 70 % (30 MB)
69 22:22:52.657552 progress 75 % (32 MB)
70 22:22:52.687414 progress 80 % (34 MB)
71 22:22:52.716646 progress 85 % (37 MB)
72 22:22:52.746072 progress 90 % (39 MB)
73 22:22:52.775772 progress 95 % (41 MB)
74 22:22:52.805093 progress 100 % (43 MB)
75 22:22:52.805657 43 MB downloaded in 0.69 s (63.52 MB/s)
76 22:22:52.806141 end: 1.2.1 http-download (duration 00:00:01) [common]
78 22:22:52.806965 end: 1.2 download-retry (duration 00:00:01) [common]
79 22:22:52.807245 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:22:52.807512 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:22:52.808035 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 22:22:52.808323 saving as /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/dtb/meson-g12b-a311d-libretech-cc.dtb
83 22:22:52.808537 total size: 54703 (0 MB)
84 22:22:52.808750 No compression specified
85 22:22:52.853961 progress 59 % (0 MB)
86 22:22:52.854830 progress 100 % (0 MB)
87 22:22:52.855405 0 MB downloaded in 0.05 s (1.11 MB/s)
88 22:22:52.855888 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:22:52.856756 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:22:52.857022 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:22:52.857292 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:22:52.857765 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 22:22:52.858010 saving as /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/nfsrootfs/full.rootfs.tar
95 22:22:52.858218 total size: 120894716 (115 MB)
96 22:22:52.858429 Using unxz to decompress xz
97 22:22:52.896548 progress 0 % (0 MB)
98 22:22:53.701641 progress 5 % (5 MB)
99 22:22:54.590209 progress 10 % (11 MB)
100 22:22:55.386048 progress 15 % (17 MB)
101 22:22:56.123223 progress 20 % (23 MB)
102 22:22:56.713032 progress 25 % (28 MB)
103 22:22:57.539175 progress 30 % (34 MB)
104 22:22:58.344029 progress 35 % (40 MB)
105 22:22:58.701714 progress 40 % (46 MB)
106 22:22:59.073627 progress 45 % (51 MB)
107 22:22:59.809633 progress 50 % (57 MB)
108 22:23:00.704578 progress 55 % (63 MB)
109 22:23:01.490972 progress 60 % (69 MB)
110 22:23:02.252176 progress 65 % (74 MB)
111 22:23:03.035321 progress 70 % (80 MB)
112 22:23:03.865816 progress 75 % (86 MB)
113 22:23:04.662886 progress 80 % (92 MB)
114 22:23:05.453760 progress 85 % (98 MB)
115 22:23:06.319770 progress 90 % (103 MB)
116 22:23:07.109927 progress 95 % (109 MB)
117 22:23:07.948216 progress 100 % (115 MB)
118 22:23:07.960727 115 MB downloaded in 15.10 s (7.63 MB/s)
119 22:23:07.961607 end: 1.4.1 http-download (duration 00:00:15) [common]
121 22:23:07.963201 end: 1.4 download-retry (duration 00:00:15) [common]
122 22:23:07.963721 start: 1.5 download-retry (timeout 00:09:44) [common]
123 22:23:07.964285 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 22:23:07.965107 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/modules.tar.xz
125 22:23:07.965576 saving as /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/modules/modules.tar
126 22:23:07.965985 total size: 11624536 (11 MB)
127 22:23:07.966407 Using unxz to decompress xz
128 22:23:08.021299 progress 0 % (0 MB)
129 22:23:08.087721 progress 5 % (0 MB)
130 22:23:08.162172 progress 10 % (1 MB)
131 22:23:08.258385 progress 15 % (1 MB)
132 22:23:08.351456 progress 20 % (2 MB)
133 22:23:08.432638 progress 25 % (2 MB)
134 22:23:08.509407 progress 30 % (3 MB)
135 22:23:08.588638 progress 35 % (3 MB)
136 22:23:08.661465 progress 40 % (4 MB)
137 22:23:08.739014 progress 45 % (5 MB)
138 22:23:08.823456 progress 50 % (5 MB)
139 22:23:08.906593 progress 55 % (6 MB)
140 22:23:08.987203 progress 60 % (6 MB)
141 22:23:09.068539 progress 65 % (7 MB)
142 22:23:09.149133 progress 70 % (7 MB)
143 22:23:09.230948 progress 75 % (8 MB)
144 22:23:09.309439 progress 80 % (8 MB)
145 22:23:09.390178 progress 85 % (9 MB)
146 22:23:09.473254 progress 90 % (10 MB)
147 22:23:09.550607 progress 95 % (10 MB)
148 22:23:09.624123 progress 100 % (11 MB)
149 22:23:09.637904 11 MB downloaded in 1.67 s (6.63 MB/s)
150 22:23:09.638491 end: 1.5.1 http-download (duration 00:00:02) [common]
152 22:23:09.639356 end: 1.5 download-retry (duration 00:00:02) [common]
153 22:23:09.639627 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 22:23:09.639906 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 22:23:28.221043 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/955483/extract-nfsrootfs-b_6ntddj
156 22:23:28.221658 end: 1.6.1 extract-nfsrootfs (duration 00:00:19) [common]
157 22:23:28.221953 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
158 22:23:28.223023 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn
159 22:23:28.223517 makedir: /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin
160 22:23:28.223859 makedir: /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/tests
161 22:23:28.224832 makedir: /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/results
162 22:23:28.225217 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-add-keys
163 22:23:28.225815 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-add-sources
164 22:23:28.226691 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-background-process-start
165 22:23:28.228053 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-background-process-stop
166 22:23:28.230088 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-common-functions
167 22:23:28.231165 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-echo-ipv4
168 22:23:28.232160 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-install-packages
169 22:23:28.233111 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-installed-packages
170 22:23:28.233652 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-os-build
171 22:23:28.234514 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-probe-channel
172 22:23:28.235114 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-probe-ip
173 22:23:28.235754 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-target-ip
174 22:23:28.237018 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-target-mac
175 22:23:28.237632 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-target-storage
176 22:23:28.238373 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-test-case
177 22:23:28.239085 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-test-event
178 22:23:28.239670 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-test-feedback
179 22:23:28.240272 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-test-raise
180 22:23:28.241402 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-test-reference
181 22:23:28.242172 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-test-runner
182 22:23:28.242842 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-test-set
183 22:23:28.243440 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-test-shell
184 22:23:28.244042 Updating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-add-keys (debian)
185 22:23:28.245481 Updating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-add-sources (debian)
186 22:23:28.246983 Updating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-install-packages (debian)
187 22:23:28.247749 Updating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-installed-packages (debian)
188 22:23:28.249717 Updating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/bin/lava-os-build (debian)
189 22:23:28.251807 Creating /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/environment
190 22:23:28.253367 LAVA metadata
191 22:23:28.253980 - LAVA_JOB_ID=955483
192 22:23:28.254266 - LAVA_DISPATCHER_IP=192.168.6.2
193 22:23:28.254708 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
194 22:23:28.257336 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 22:23:28.257746 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
196 22:23:28.258000 skipped lava-vland-overlay
197 22:23:28.258289 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 22:23:28.258581 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
199 22:23:28.258826 skipped lava-multinode-overlay
200 22:23:28.259136 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 22:23:28.259461 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
202 22:23:28.259767 Loading test definitions
203 22:23:28.260146 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
204 22:23:28.260432 Using /lava-955483 at stage 0
205 22:23:28.262841 uuid=955483_1.6.2.4.1 testdef=None
206 22:23:28.263221 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 22:23:28.263505 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
208 22:23:28.265811 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 22:23:28.266771 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
211 22:23:28.270225 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 22:23:28.271140 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
214 22:23:28.276282 runner path: /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/0/tests/0_timesync-off test_uuid 955483_1.6.2.4.1
215 22:23:28.277609 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 22:23:28.278582 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
218 22:23:28.278857 Using /lava-955483 at stage 0
219 22:23:28.279299 Fetching tests from https://github.com/kernelci/test-definitions.git
220 22:23:28.279722 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/0/tests/1_kselftest-dt'
221 22:23:31.848953 Running '/usr/bin/git checkout kernelci.org
222 22:23:32.298051 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 22:23:32.299528 uuid=955483_1.6.2.4.5 testdef=None
224 22:23:32.299885 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 22:23:32.301507 start: 1.6.2.4.6 test-overlay (timeout 00:09:20) [common]
227 22:23:32.307582 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 22:23:32.309634 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:20) [common]
230 22:23:32.318186 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 22:23:32.320277 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:20) [common]
233 22:23:32.329479 runner path: /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/0/tests/1_kselftest-dt test_uuid 955483_1.6.2.4.5
234 22:23:32.330250 BOARD='meson-g12b-a311d-libretech-cc'
235 22:23:32.330855 BRANCH='broonie-sound'
236 22:23:32.331419 SKIPFILE='/dev/null'
237 22:23:32.331962 SKIP_INSTALL='True'
238 22:23:32.332531 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 22:23:32.332990 TST_CASENAME=''
240 22:23:32.333431 TST_CMDFILES='dt'
241 22:23:32.334665 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 22:23:32.336469 Creating lava-test-runner.conf files
244 22:23:32.336925 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/955483/lava-overlay-x04veoxn/lava-955483/0 for stage 0
245 22:23:32.337674 - 0_timesync-off
246 22:23:32.338197 - 1_kselftest-dt
247 22:23:32.338928 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 22:23:32.339540 start: 1.6.2.5 compress-overlay (timeout 00:09:20) [common]
249 22:23:56.100470 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 22:23:56.100931 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:56) [common]
251 22:23:56.101232 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 22:23:56.101546 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 22:23:56.101844 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:56) [common]
254 22:23:56.754199 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 22:23:56.754691 start: 1.6.4 extract-modules (timeout 00:08:55) [common]
256 22:23:56.754969 extracting modules file /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955483/extract-nfsrootfs-b_6ntddj
257 22:23:58.285061 extracting modules file /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955483/extract-overlay-ramdisk-5237j4fu/ramdisk
258 22:24:00.017342 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 22:24:00.017950 start: 1.6.5 apply-overlay-tftp (timeout 00:08:52) [common]
260 22:24:00.018308 [common] Applying overlay to NFS
261 22:24:00.018620 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955483/compress-overlay-_hw2wsr3/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/955483/extract-nfsrootfs-b_6ntddj
262 22:24:03.033576 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 22:24:03.034063 start: 1.6.6 prepare-kernel (timeout 00:08:49) [common]
264 22:24:03.034345 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:49) [common]
265 22:24:03.034578 Converting downloaded kernel to a uImage
266 22:24:03.034893 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/kernel/Image /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/kernel/uImage
267 22:24:03.556719 output: Image Name:
268 22:24:03.557150 output: Created: Thu Nov 7 22:24:03 2024
269 22:24:03.557364 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 22:24:03.557573 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 22:24:03.557779 output: Load Address: 01080000
272 22:24:03.557983 output: Entry Point: 01080000
273 22:24:03.558183 output:
274 22:24:03.558522 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 22:24:03.558797 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 22:24:03.559069 start: 1.6.7 configure-preseed-file (timeout 00:08:48) [common]
277 22:24:03.559325 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 22:24:03.559582 start: 1.6.8 compress-ramdisk (timeout 00:08:48) [common]
279 22:24:03.559852 Building ramdisk /var/lib/lava/dispatcher/tmp/955483/extract-overlay-ramdisk-5237j4fu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/955483/extract-overlay-ramdisk-5237j4fu/ramdisk
280 22:24:05.752321 >> 166792 blocks
281 22:24:13.775402 Adding RAMdisk u-boot header.
282 22:24:13.775915 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/955483/extract-overlay-ramdisk-5237j4fu/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/955483/extract-overlay-ramdisk-5237j4fu/ramdisk.cpio.gz.uboot
283 22:24:14.076384 output: Image Name:
284 22:24:14.076827 output: Created: Thu Nov 7 22:24:13 2024
285 22:24:14.077043 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 22:24:14.077253 output: Data Size: 23432185 Bytes = 22882.99 KiB = 22.35 MiB
287 22:24:14.077459 output: Load Address: 00000000
288 22:24:14.077660 output: Entry Point: 00000000
289 22:24:14.077862 output:
290 22:24:14.078564 rename /var/lib/lava/dispatcher/tmp/955483/extract-overlay-ramdisk-5237j4fu/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/ramdisk/ramdisk.cpio.gz.uboot
291 22:24:14.078998 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 22:24:14.079290 end: 1.6 prepare-tftp-overlay (duration 00:01:04) [common]
293 22:24:14.079589 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:38) [common]
294 22:24:14.079824 No LXC device requested
295 22:24:14.080219 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 22:24:14.080742 start: 1.8 deploy-device-env (timeout 00:08:38) [common]
297 22:24:14.081238 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 22:24:14.081647 Checking files for TFTP limit of 4294967296 bytes.
299 22:24:14.084429 end: 1 tftp-deploy (duration 00:01:22) [common]
300 22:24:14.085016 start: 2 uboot-action (timeout 00:05:00) [common]
301 22:24:14.085538 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 22:24:14.086035 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 22:24:14.086533 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 22:24:14.087064 Using kernel file from prepare-kernel: 955483/tftp-deploy-83s6wpzo/kernel/uImage
305 22:24:14.087693 substitutions:
306 22:24:14.088135 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 22:24:14.088543 - {DTB_ADDR}: 0x01070000
308 22:24:14.088943 - {DTB}: 955483/tftp-deploy-83s6wpzo/dtb/meson-g12b-a311d-libretech-cc.dtb
309 22:24:14.089345 - {INITRD}: 955483/tftp-deploy-83s6wpzo/ramdisk/ramdisk.cpio.gz.uboot
310 22:24:14.089745 - {KERNEL_ADDR}: 0x01080000
311 22:24:14.090138 - {KERNEL}: 955483/tftp-deploy-83s6wpzo/kernel/uImage
312 22:24:14.090529 - {LAVA_MAC}: None
313 22:24:14.090956 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/955483/extract-nfsrootfs-b_6ntddj
314 22:24:14.091354 - {NFS_SERVER_IP}: 192.168.6.2
315 22:24:14.091744 - {PRESEED_CONFIG}: None
316 22:24:14.092162 - {PRESEED_LOCAL}: None
317 22:24:14.092555 - {RAMDISK_ADDR}: 0x08000000
318 22:24:14.092942 - {RAMDISK}: 955483/tftp-deploy-83s6wpzo/ramdisk/ramdisk.cpio.gz.uboot
319 22:24:14.093332 - {ROOT_PART}: None
320 22:24:14.093721 - {ROOT}: None
321 22:24:14.094107 - {SERVER_IP}: 192.168.6.2
322 22:24:14.094492 - {TEE_ADDR}: 0x83000000
323 22:24:14.094878 - {TEE}: None
324 22:24:14.095261 Parsed boot commands:
325 22:24:14.095637 - setenv autoload no
326 22:24:14.096051 - setenv initrd_high 0xffffffff
327 22:24:14.096446 - setenv fdt_high 0xffffffff
328 22:24:14.096828 - dhcp
329 22:24:14.097210 - setenv serverip 192.168.6.2
330 22:24:14.097599 - tftpboot 0x01080000 955483/tftp-deploy-83s6wpzo/kernel/uImage
331 22:24:14.097988 - tftpboot 0x08000000 955483/tftp-deploy-83s6wpzo/ramdisk/ramdisk.cpio.gz.uboot
332 22:24:14.098376 - tftpboot 0x01070000 955483/tftp-deploy-83s6wpzo/dtb/meson-g12b-a311d-libretech-cc.dtb
333 22:24:14.098765 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/955483/extract-nfsrootfs-b_6ntddj,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 22:24:14.099162 - bootm 0x01080000 0x08000000 0x01070000
335 22:24:14.099661 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 22:24:14.101195 start: 2.3 connect-device (timeout 00:05:00) [common]
338 22:24:14.101613 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 22:24:14.118249 Setting prompt string to ['lava-test: # ']
340 22:24:14.119758 end: 2.3 connect-device (duration 00:00:00) [common]
341 22:24:14.120425 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 22:24:14.120998 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 22:24:14.121559 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 22:24:14.122813 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 22:24:14.164271 >> OK - accepted request
346 22:24:14.166776 Returned 0 in 0 seconds
347 22:24:14.267683 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 22:24:14.269361 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 22:24:14.269907 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 22:24:14.270404 Setting prompt string to ['Hit any key to stop autoboot']
352 22:24:14.270854 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 22:24:14.272448 Trying 192.168.56.21...
354 22:24:14.272938 Connected to conserv1.
355 22:24:14.273346 Escape character is '^]'.
356 22:24:14.273760
357 22:24:14.274172 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 22:24:14.274588
359 22:24:25.847821 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 22:24:25.848873 bl2_stage_init 0x01
361 22:24:25.849127 bl2_stage_init 0x81
362 22:24:25.853299 hw id: 0x0000 - pwm id 0x01
363 22:24:25.853686 bl2_stage_init 0xc1
364 22:24:25.853965 bl2_stage_init 0x02
365 22:24:25.854197
366 22:24:25.858900 L0:00000000
367 22:24:25.859256 L1:20000703
368 22:24:25.859476 L2:00008067
369 22:24:25.859688 L3:14000000
370 22:24:25.861616 B2:00402000
371 22:24:25.861915 B1:e0f83180
372 22:24:25.862118
373 22:24:25.862318 TE: 58159
374 22:24:25.862517
375 22:24:25.872782 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 22:24:25.873116
377 22:24:25.873326 Board ID = 1
378 22:24:25.873524 Set A53 clk to 24M
379 22:24:25.873720 Set A73 clk to 24M
380 22:24:25.878403 Set clk81 to 24M
381 22:24:25.878706 A53 clk: 1200 MHz
382 22:24:25.878909 A73 clk: 1200 MHz
383 22:24:25.881711 CLK81: 166.6M
384 22:24:25.881991 smccc: 00012ab5
385 22:24:25.887246 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 22:24:25.892834 board id: 1
387 22:24:25.897238 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 22:24:25.909025 fw parse done
389 22:24:25.914038 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 22:24:25.956642 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 22:24:25.968573 PIEI prepare done
392 22:24:25.969152 fastboot data load
393 22:24:25.969606 fastboot data verify
394 22:24:25.974131 verify result: 266
395 22:24:25.979727 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 22:24:25.980342 LPDDR4 probe
397 22:24:25.980788 ddr clk to 1584MHz
398 22:24:25.986798 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 22:24:26.024030
400 22:24:26.024457 dmc_version 0001
401 22:24:26.030704 Check phy result
402 22:24:26.037598 INFO : End of CA training
403 22:24:26.038243 INFO : End of initialization
404 22:24:26.043098 INFO : Training has run successfully!
405 22:24:26.043468 Check phy result
406 22:24:26.049068 INFO : End of initialization
407 22:24:26.049423 INFO : End of read enable training
408 22:24:26.052153 INFO : End of fine write leveling
409 22:24:26.057771 INFO : End of Write leveling coarse delay
410 22:24:26.063454 INFO : Training has run successfully!
411 22:24:26.063832 Check phy result
412 22:24:26.064098 INFO : End of initialization
413 22:24:26.068750 INFO : End of read dq deskew training
414 22:24:26.074461 INFO : End of MPR read delay center optimization
415 22:24:26.074822 INFO : End of write delay center optimization
416 22:24:26.080091 INFO : End of read delay center optimization
417 22:24:26.085797 INFO : End of max read latency training
418 22:24:26.086188 INFO : Training has run successfully!
419 22:24:26.091365 1D training succeed
420 22:24:26.097086 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 22:24:26.143914 Check phy result
422 22:24:26.144367 INFO : End of initialization
423 22:24:26.165780 INFO : End of 2D read delay Voltage center optimization
424 22:24:26.185486 INFO : End of 2D read delay Voltage center optimization
425 22:24:26.237500 INFO : End of 2D write delay Voltage center optimization
426 22:24:26.287573 INFO : End of 2D write delay Voltage center optimization
427 22:24:26.294398 INFO : Training has run successfully!
428 22:24:26.294773
429 22:24:26.295006 channel==0
430 22:24:26.299005 RxClkDly_Margin_A0==88 ps 9
431 22:24:26.299377 TxDqDly_Margin_A0==98 ps 10
432 22:24:26.302067 RxClkDly_Margin_A1==88 ps 9
433 22:24:26.302412 TxDqDly_Margin_A1==88 ps 9
434 22:24:26.307680 TrainedVREFDQ_A0==74
435 22:24:26.308112 TrainedVREFDQ_A1==74
436 22:24:26.308345 VrefDac_Margin_A0==25
437 22:24:26.313642 DeviceVref_Margin_A0==40
438 22:24:26.314059 VrefDac_Margin_A1==25
439 22:24:26.319337 DeviceVref_Margin_A1==40
440 22:24:26.319804
441 22:24:26.320085
442 22:24:26.320310 channel==1
443 22:24:26.320520 RxClkDly_Margin_A0==88 ps 9
444 22:24:26.325098 TxDqDly_Margin_A0==98 ps 10
445 22:24:26.325479 RxClkDly_Margin_A1==98 ps 10
446 22:24:26.330098 TxDqDly_Margin_A1==88 ps 9
447 22:24:26.330446 TrainedVREFDQ_A0==77
448 22:24:26.330666 TrainedVREFDQ_A1==77
449 22:24:26.335562 VrefDac_Margin_A0==22
450 22:24:26.335893 DeviceVref_Margin_A0==37
451 22:24:26.341896 VrefDac_Margin_A1==22
452 22:24:26.342273 DeviceVref_Margin_A1==37
453 22:24:26.342493
454 22:24:26.346677 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 22:24:26.347025
456 22:24:26.374697 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 22:24:26.380343 2D training succeed
458 22:24:26.386184 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 22:24:26.386640 auto size-- 65535DDR cs0 size: 2048MB
460 22:24:26.391713 DDR cs1 size: 2048MB
461 22:24:26.392311 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 22:24:26.397500 cs0 DataBus test pass
463 22:24:26.397985 cs1 DataBus test pass
464 22:24:26.398305 cs0 AddrBus test pass
465 22:24:26.402827 cs1 AddrBus test pass
466 22:24:26.403251
467 22:24:26.403547 100bdlr_step_size ps== 420
468 22:24:26.403830 result report
469 22:24:26.408420 boot times 0Enable ddr reg access
470 22:24:26.415093 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 22:24:26.429879 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 22:24:27.002136 0.0;M3 CHK:0;cm4_sp_mode 0
473 22:24:27.002561 MVN_1=0x00000000
474 22:24:27.007104 MVN_2=0x00000000
475 22:24:27.012760 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 22:24:27.013193 OPS=0x10
477 22:24:27.013446 ring efuse init
478 22:24:27.013669 chipver efuse init
479 22:24:27.024240 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 22:24:27.024725 [0.018961 Inits done]
481 22:24:27.028429 secure task start!
482 22:24:27.028860 high task start!
483 22:24:27.029105 low task start!
484 22:24:27.029344 run into bl31
485 22:24:27.035167 NOTICE: BL31: v1.3(release):4fc40b1
486 22:24:27.042876 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 22:24:27.043497 NOTICE: BL31: G12A normal boot!
488 22:24:27.068926 NOTICE: BL31: BL33 decompress pass
489 22:24:27.073961 ERROR: Error initializing runtime service opteed_fast
490 22:24:28.306786
491 22:24:28.307372
492 22:24:28.315215 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 22:24:28.315964
494 22:24:28.316317 Model: Libre Computer AML-A311D-CC Alta
495 22:24:28.523729 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 22:24:28.546077 DRAM: 2 GiB (effective 3.8 GiB)
497 22:24:28.689949 Core: 408 devices, 31 uclasses, devicetree: separate
498 22:24:28.694791 WDT: Not starting watchdog@f0d0
499 22:24:28.728059 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 22:24:28.740529 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 22:24:28.745537 ** Bad device specification mmc 0 **
502 22:24:28.755767 Card did not respond to voltage select! : -110
503 22:24:28.763553 ** Bad device specification mmc 0 **
504 22:24:28.764176 Couldn't find partition mmc 0
505 22:24:28.771731 Card did not respond to voltage select! : -110
506 22:24:28.777252 ** Bad device specification mmc 0 **
507 22:24:28.777862 Couldn't find partition mmc 0
508 22:24:28.781333 Error: could not access storage.
509 22:24:30.048104 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 22:24:30.048512 bl2_stage_init 0x01
511 22:24:30.048728 bl2_stage_init 0x81
512 22:24:30.053610 hw id: 0x0000 - pwm id 0x01
513 22:24:30.053928 bl2_stage_init 0xc1
514 22:24:30.054141 bl2_stage_init 0x02
515 22:24:30.054349
516 22:24:30.059241 L0:00000000
517 22:24:30.059582 L1:20000703
518 22:24:30.059792 L2:00008067
519 22:24:30.060094 L3:14000000
520 22:24:30.064795 B2:00402000
521 22:24:30.065103 B1:e0f83180
522 22:24:30.065309
523 22:24:30.065524 TE: 58159
524 22:24:30.065727
525 22:24:30.070373 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 22:24:30.070813
527 22:24:30.071137 Board ID = 1
528 22:24:30.076088 Set A53 clk to 24M
529 22:24:30.077037 Set A73 clk to 24M
530 22:24:30.077642 Set clk81 to 24M
531 22:24:30.081636 A53 clk: 1200 MHz
532 22:24:30.082080 A73 clk: 1200 MHz
533 22:24:30.082425 CLK81: 166.6M
534 22:24:30.082756 smccc: 00012ab5
535 22:24:30.087144 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 22:24:30.092756 board id: 1
537 22:24:30.098701 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 22:24:30.109400 fw parse done
539 22:24:30.115298 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 22:24:30.157285 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 22:24:30.168810 PIEI prepare done
542 22:24:30.169165 fastboot data load
543 22:24:30.169399 fastboot data verify
544 22:24:30.174534 verify result: 266
545 22:24:30.180206 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 22:24:30.180775 LPDDR4 probe
547 22:24:30.181171 ddr clk to 1584MHz
548 22:24:30.188088 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 22:24:30.225343
550 22:24:30.225870 dmc_version 0001
551 22:24:30.232095 Check phy result
552 22:24:30.237858 INFO : End of CA training
553 22:24:30.238326 INFO : End of initialization
554 22:24:30.243471 INFO : Training has run successfully!
555 22:24:30.243924 Check phy result
556 22:24:30.249058 INFO : End of initialization
557 22:24:30.249512 INFO : End of read enable training
558 22:24:30.254735 INFO : End of fine write leveling
559 22:24:30.260274 INFO : End of Write leveling coarse delay
560 22:24:30.260729 INFO : Training has run successfully!
561 22:24:30.261146 Check phy result
562 22:24:30.265849 INFO : End of initialization
563 22:24:30.266322 INFO : End of read dq deskew training
564 22:24:30.271476 INFO : End of MPR read delay center optimization
565 22:24:30.277064 INFO : End of write delay center optimization
566 22:24:30.282735 INFO : End of read delay center optimization
567 22:24:30.283188 INFO : End of max read latency training
568 22:24:30.288260 INFO : Training has run successfully!
569 22:24:30.288711 1D training succeed
570 22:24:30.297440 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 22:24:30.345087 Check phy result
572 22:24:30.345574 INFO : End of initialization
573 22:24:30.368022 INFO : End of 2D read delay Voltage center optimization
574 22:24:30.387684 INFO : End of 2D read delay Voltage center optimization
575 22:24:30.438683 INFO : End of 2D write delay Voltage center optimization
576 22:24:30.488895 INFO : End of 2D write delay Voltage center optimization
577 22:24:30.494302 INFO : Training has run successfully!
578 22:24:30.494761
579 22:24:30.495182 channel==0
580 22:24:30.499921 RxClkDly_Margin_A0==88 ps 9
581 22:24:30.500440 TxDqDly_Margin_A0==98 ps 10
582 22:24:30.505532 RxClkDly_Margin_A1==88 ps 9
583 22:24:30.505995 TxDqDly_Margin_A1==98 ps 10
584 22:24:30.506414 TrainedVREFDQ_A0==74
585 22:24:30.511053 TrainedVREFDQ_A1==74
586 22:24:30.511513 VrefDac_Margin_A0==24
587 22:24:30.511929 DeviceVref_Margin_A0==40
588 22:24:30.516800 VrefDac_Margin_A1==24
589 22:24:30.517256 DeviceVref_Margin_A1==40
590 22:24:30.517669
591 22:24:30.518079
592 22:24:30.522318 channel==1
593 22:24:30.522773 RxClkDly_Margin_A0==98 ps 10
594 22:24:30.523189 TxDqDly_Margin_A0==88 ps 9
595 22:24:30.527903 RxClkDly_Margin_A1==98 ps 10
596 22:24:30.528382 TxDqDly_Margin_A1==108 ps 11
597 22:24:30.533586 TrainedVREFDQ_A0==77
598 22:24:30.534046 TrainedVREFDQ_A1==78
599 22:24:30.534461 VrefDac_Margin_A0==22
600 22:24:30.539180 DeviceVref_Margin_A0==37
601 22:24:30.539640 VrefDac_Margin_A1==22
602 22:24:30.544818 DeviceVref_Margin_A1==36
603 22:24:30.545300
604 22:24:30.545716 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 22:24:30.550341
606 22:24:30.578375 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 22:24:30.578902 2D training succeed
608 22:24:30.583924 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 22:24:30.589558 auto size-- 65535DDR cs0 size: 2048MB
610 22:24:30.590024 DDR cs1 size: 2048MB
611 22:24:30.595159 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 22:24:30.595613 cs0 DataBus test pass
613 22:24:30.600812 cs1 DataBus test pass
614 22:24:30.601282 cs0 AddrBus test pass
615 22:24:30.601697 cs1 AddrBus test pass
616 22:24:30.602101
617 22:24:30.606275 100bdlr_step_size ps== 420
618 22:24:30.606737 result report
619 22:24:30.611855 boot times 0Enable ddr reg access
620 22:24:30.617424 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 22:24:30.630853 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 22:24:31.203310 0.0;M3 CHK:0;cm4_sp_mode 0
623 22:24:31.203956 MVN_1=0x00000000
624 22:24:31.208519 MVN_2=0x00000000
625 22:24:31.214277 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 22:24:31.214818 OPS=0x10
627 22:24:31.215278 ring efuse init
628 22:24:31.215708 chipver efuse init
629 22:24:31.219974 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 22:24:31.225435 [0.018961 Inits done]
631 22:24:31.225890 secure task start!
632 22:24:31.226282 high task start!
633 22:24:31.230080 low task start!
634 22:24:31.230518 run into bl31
635 22:24:31.236729 NOTICE: BL31: v1.3(release):4fc40b1
636 22:24:31.244619 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 22:24:31.245100 NOTICE: BL31: G12A normal boot!
638 22:24:31.269815 NOTICE: BL31: BL33 decompress pass
639 22:24:31.275415 ERROR: Error initializing runtime service opteed_fast
640 22:24:32.508530
641 22:24:32.508961
642 22:24:32.516831 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 22:24:32.517162
644 22:24:32.517379 Model: Libre Computer AML-A311D-CC Alta
645 22:24:32.725416 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 22:24:32.748644 DRAM: 2 GiB (effective 3.8 GiB)
647 22:24:32.891694 Core: 408 devices, 31 uclasses, devicetree: separate
648 22:24:32.897369 WDT: Not starting watchdog@f0d0
649 22:24:32.929707 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 22:24:32.942093 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 22:24:32.947211 ** Bad device specification mmc 0 **
652 22:24:32.957404 Card did not respond to voltage select! : -110
653 22:24:32.965144 ** Bad device specification mmc 0 **
654 22:24:32.965462 Couldn't find partition mmc 0
655 22:24:32.973330 Card did not respond to voltage select! : -110
656 22:24:32.978823 ** Bad device specification mmc 0 **
657 22:24:32.979113 Couldn't find partition mmc 0
658 22:24:32.984011 Error: could not access storage.
659 22:24:33.326455 Net: eth0: ethernet@ff3f0000
660 22:24:33.326866 starting USB...
661 22:24:33.578394 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 22:24:33.578975 Starting the controller
663 22:24:33.585430 USB XHCI 1.10
664 22:24:35.298276 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 22:24:35.298702 bl2_stage_init 0x01
666 22:24:35.298932 bl2_stage_init 0x81
667 22:24:35.303827 hw id: 0x0000 - pwm id 0x01
668 22:24:35.304231 bl2_stage_init 0xc1
669 22:24:35.304568 bl2_stage_init 0x02
670 22:24:35.304890
671 22:24:35.309411 L0:00000000
672 22:24:35.309766 L1:20000703
673 22:24:35.310010 L2:00008067
674 22:24:35.310222 L3:14000000
675 22:24:35.312254 B2:00402000
676 22:24:35.312611 B1:e0f83180
677 22:24:35.312932
678 22:24:35.313250 TE: 58159
679 22:24:35.313568
680 22:24:35.323514 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 22:24:35.323902
682 22:24:35.324181 Board ID = 1
683 22:24:35.324398 Set A53 clk to 24M
684 22:24:35.324606 Set A73 clk to 24M
685 22:24:35.329040 Set clk81 to 24M
686 22:24:35.329465 A53 clk: 1200 MHz
687 22:24:35.329792 A73 clk: 1200 MHz
688 22:24:35.332612 CLK81: 166.6M
689 22:24:35.332978 smccc: 00012ab5
690 22:24:35.338121 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 22:24:35.343492 board id: 1
692 22:24:35.348918 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 22:24:35.359483 fw parse done
694 22:24:35.365505 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 22:24:35.408245 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 22:24:35.419206 PIEI prepare done
697 22:24:35.419817 fastboot data load
698 22:24:35.420576 fastboot data verify
699 22:24:35.424779 verify result: 266
700 22:24:35.430312 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 22:24:35.430833 LPDDR4 probe
702 22:24:35.431304 ddr clk to 1584MHz
703 22:24:35.437295 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 22:24:35.475781
705 22:24:35.476422 dmc_version 0001
706 22:24:35.482271 Check phy result
707 22:24:35.488078 INFO : End of CA training
708 22:24:35.488604 INFO : End of initialization
709 22:24:35.493673 INFO : Training has run successfully!
710 22:24:35.494208 Check phy result
711 22:24:35.499494 INFO : End of initialization
712 22:24:35.500037 INFO : End of read enable training
713 22:24:35.504968 INFO : End of fine write leveling
714 22:24:35.510814 INFO : End of Write leveling coarse delay
715 22:24:35.511338 INFO : Training has run successfully!
716 22:24:35.511801 Check phy result
717 22:24:35.516240 INFO : End of initialization
718 22:24:35.516747 INFO : End of read dq deskew training
719 22:24:35.521793 INFO : End of MPR read delay center optimization
720 22:24:35.527335 INFO : End of write delay center optimization
721 22:24:35.533070 INFO : End of read delay center optimization
722 22:24:35.533604 INFO : End of max read latency training
723 22:24:35.538565 INFO : Training has run successfully!
724 22:24:35.539080 1D training succeed
725 22:24:35.547658 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 22:24:35.595306 Check phy result
727 22:24:35.595885 INFO : End of initialization
728 22:24:35.617877 INFO : End of 2D read delay Voltage center optimization
729 22:24:35.637298 INFO : End of 2D read delay Voltage center optimization
730 22:24:35.688501 INFO : End of 2D write delay Voltage center optimization
731 22:24:35.738716 INFO : End of 2D write delay Voltage center optimization
732 22:24:35.744242 INFO : Training has run successfully!
733 22:24:35.744741
734 22:24:35.745201 channel==0
735 22:24:35.749882 RxClkDly_Margin_A0==88 ps 9
736 22:24:35.750371 TxDqDly_Margin_A0==98 ps 10
737 22:24:35.755512 RxClkDly_Margin_A1==88 ps 9
738 22:24:35.756056 TxDqDly_Margin_A1==98 ps 10
739 22:24:35.756520 TrainedVREFDQ_A0==74
740 22:24:35.760994 TrainedVREFDQ_A1==75
741 22:24:35.761499 VrefDac_Margin_A0==24
742 22:24:35.761948 DeviceVref_Margin_A0==40
743 22:24:35.766612 VrefDac_Margin_A1==24
744 22:24:35.767093 DeviceVref_Margin_A1==39
745 22:24:35.767545
746 22:24:35.768015
747 22:24:35.772247 channel==1
748 22:24:35.772742 RxClkDly_Margin_A0==88 ps 9
749 22:24:35.773195 TxDqDly_Margin_A0==88 ps 9
750 22:24:35.777833 RxClkDly_Margin_A1==88 ps 9
751 22:24:35.778337 TxDqDly_Margin_A1==88 ps 9
752 22:24:35.783433 TrainedVREFDQ_A0==77
753 22:24:35.783928 TrainedVREFDQ_A1==77
754 22:24:35.784415 VrefDac_Margin_A0==23
755 22:24:35.788990 DeviceVref_Margin_A0==37
756 22:24:35.789489 VrefDac_Margin_A1==24
757 22:24:35.794547 DeviceVref_Margin_A1==37
758 22:24:35.795047
759 22:24:35.795503 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 22:24:35.795949
761 22:24:35.828106 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000017 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 22:24:35.828752 2D training succeed
763 22:24:35.833714 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 22:24:35.839292 auto size-- 65535DDR cs0 size: 2048MB
765 22:24:35.839794 DDR cs1 size: 2048MB
766 22:24:35.844920 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 22:24:35.845420 cs0 DataBus test pass
768 22:24:35.850494 cs1 DataBus test pass
769 22:24:35.850980 cs0 AddrBus test pass
770 22:24:35.851425 cs1 AddrBus test pass
771 22:24:35.851873
772 22:24:35.856137 100bdlr_step_size ps== 420
773 22:24:35.856704 result report
774 22:24:35.861730 boot times 0Enable ddr reg access
775 22:24:35.866898 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 22:24:35.880403 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 22:24:36.454061 0.0;M3 CHK:0;cm4_sp_mode 0
778 22:24:36.454491 MVN_1=0x00000000
779 22:24:36.459591 MVN_2=0x00000000
780 22:24:36.465423 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 22:24:36.465971 OPS=0x10
782 22:24:36.466447 ring efuse init
783 22:24:36.466890 chipver efuse init
784 22:24:36.470956 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 22:24:36.476572 [0.018961 Inits done]
786 22:24:36.477075 secure task start!
787 22:24:36.477518 high task start!
788 22:24:36.481107 low task start!
789 22:24:36.481621 run into bl31
790 22:24:36.487739 NOTICE: BL31: v1.3(release):4fc40b1
791 22:24:36.495694 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 22:24:36.496260 NOTICE: BL31: G12A normal boot!
793 22:24:36.520910 NOTICE: BL31: BL33 decompress pass
794 22:24:36.525741 ERROR: Error initializing runtime service opteed_fast
795 22:24:37.759653
796 22:24:37.760380
797 22:24:37.767918 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 22:24:37.768559
799 22:24:37.769054 Model: Libre Computer AML-A311D-CC Alta
800 22:24:37.976453 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 22:24:38.000022 DRAM: 2 GiB (effective 3.8 GiB)
802 22:24:38.143021 Core: 408 devices, 31 uclasses, devicetree: separate
803 22:24:38.148776 WDT: Not starting watchdog@f0d0
804 22:24:38.181043 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 22:24:38.193408 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 22:24:38.198461 ** Bad device specification mmc 0 **
807 22:24:38.208701 Card did not respond to voltage select! : -110
808 22:24:38.215331 ** Bad device specification mmc 0 **
809 22:24:38.215661 Couldn't find partition mmc 0
810 22:24:38.224787 Card did not respond to voltage select! : -110
811 22:24:38.230203 ** Bad device specification mmc 0 **
812 22:24:38.230793 Couldn't find partition mmc 0
813 22:24:38.234302 Error: could not access storage.
814 22:24:38.577771 Net: eth0: ethernet@ff3f0000
815 22:24:38.578415 starting USB...
816 22:24:38.829734 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 22:24:38.830168 Starting the controller
818 22:24:38.836563 USB XHCI 1.10
819 22:24:41.000245 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
820 22:24:41.000862 bl2_stage_init 0x81
821 22:24:41.005530 hw id: 0x0000 - pwm id 0x01
822 22:24:41.005847 bl2_stage_init 0xc1
823 22:24:41.006061 bl2_stage_init 0x02
824 22:24:41.006264
825 22:24:41.011152 L0:00000000
826 22:24:41.011473 L1:20000703
827 22:24:41.011690 L2:00008067
828 22:24:41.011895 L3:14000000
829 22:24:41.012149 B2:00402000
830 22:24:41.016584 B1:e0f83180
831 22:24:41.016987
832 22:24:41.017299 TE: 58150
833 22:24:41.017613
834 22:24:41.022203 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 22:24:41.022661
836 22:24:41.022987 Board ID = 1
837 22:24:41.027714 Set A53 clk to 24M
838 22:24:41.028162 Set A73 clk to 24M
839 22:24:41.028489 Set clk81 to 24M
840 22:24:41.033308 A53 clk: 1200 MHz
841 22:24:41.033615 A73 clk: 1200 MHz
842 22:24:41.033824 CLK81: 166.6M
843 22:24:41.034032 smccc: 00012aac
844 22:24:41.038984 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 22:24:41.044443 board id: 1
846 22:24:41.050277 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 22:24:41.060929 fw parse done
848 22:24:41.066896 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 22:24:41.109633 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 22:24:41.120386 PIEI prepare done
851 22:24:41.120714 fastboot data load
852 22:24:41.120926 fastboot data verify
853 22:24:41.126055 verify result: 266
854 22:24:41.131650 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 22:24:41.132109 LPDDR4 probe
856 22:24:41.132434 ddr clk to 1584MHz
857 22:24:41.139156 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 22:24:41.176939
859 22:24:41.177335 dmc_version 0001
860 22:24:41.183614 Check phy result
861 22:24:41.189450 INFO : End of CA training
862 22:24:41.189876 INFO : End of initialization
863 22:24:41.195058 INFO : Training has run successfully!
864 22:24:41.195363 Check phy result
865 22:24:41.200619 INFO : End of initialization
866 22:24:41.201035 INFO : End of read enable training
867 22:24:41.203961 INFO : End of fine write leveling
868 22:24:41.209511 INFO : End of Write leveling coarse delay
869 22:24:41.215244 INFO : Training has run successfully!
870 22:24:41.215542 Check phy result
871 22:24:41.215752 INFO : End of initialization
872 22:24:41.220739 INFO : End of read dq deskew training
873 22:24:41.226335 INFO : End of MPR read delay center optimization
874 22:24:41.226744 INFO : End of write delay center optimization
875 22:24:41.231976 INFO : End of read delay center optimization
876 22:24:41.237524 INFO : End of max read latency training
877 22:24:41.237818 INFO : Training has run successfully!
878 22:24:41.243221 1D training succeed
879 22:24:41.249040 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 22:24:41.296658 Check phy result
881 22:24:41.297048 INFO : End of initialization
882 22:24:41.317825 INFO : End of 2D read delay Voltage center optimization
883 22:24:41.338523 INFO : End of 2D read delay Voltage center optimization
884 22:24:41.390367 INFO : End of 2D write delay Voltage center optimization
885 22:24:41.439600 INFO : End of 2D write delay Voltage center optimization
886 22:24:41.445082 INFO : Training has run successfully!
887 22:24:41.445394
888 22:24:41.445606 channel==0
889 22:24:41.450598 RxClkDly_Margin_A0==88 ps 9
890 22:24:41.451013 TxDqDly_Margin_A0==98 ps 10
891 22:24:41.456289 RxClkDly_Margin_A1==88 ps 9
892 22:24:41.457849 TxDqDly_Margin_A1==98 ps 10
893 22:24:41.458157 TrainedVREFDQ_A0==74
894 22:24:41.461936 TrainedVREFDQ_A1==74
895 22:24:41.462259 VrefDac_Margin_A0==25
896 22:24:41.462503 DeviceVref_Margin_A0==40
897 22:24:41.467451 VrefDac_Margin_A1==25
898 22:24:41.467789 DeviceVref_Margin_A1==40
899 22:24:41.468074
900 22:24:41.468335
901 22:24:41.473099 channel==1
902 22:24:41.473476 RxClkDly_Margin_A0==98 ps 10
903 22:24:41.473756 TxDqDly_Margin_A0==98 ps 10
904 22:24:41.479353 RxClkDly_Margin_A1==88 ps 9
905 22:24:41.480052 TxDqDly_Margin_A1==88 ps 9
906 22:24:41.484483 TrainedVREFDQ_A0==77
907 22:24:41.485140 TrainedVREFDQ_A1==77
908 22:24:41.485598 VrefDac_Margin_A0==22
909 22:24:41.489968 DeviceVref_Margin_A0==37
910 22:24:41.490571 VrefDac_Margin_A1==24
911 22:24:41.495550 DeviceVref_Margin_A1==37
912 22:24:41.496179
913 22:24:41.496633 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 22:24:41.497073
915 22:24:41.529624 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
916 22:24:41.530307 2D training succeed
917 22:24:41.534745 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 22:24:41.540404 auto size-- 65535DDR cs0 size: 2048MB
919 22:24:41.540964 DDR cs1 size: 2048MB
920 22:24:41.545962 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 22:24:41.546550 cs0 DataBus test pass
922 22:24:41.551543 cs1 DataBus test pass
923 22:24:41.552152 cs0 AddrBus test pass
924 22:24:41.552598 cs1 AddrBus test pass
925 22:24:41.553040
926 22:24:41.557153 100bdlr_step_size ps== 420
927 22:24:41.557724 result report
928 22:24:41.562725 boot times 0Enable ddr reg access
929 22:24:41.568140 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 22:24:41.581508 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 22:24:42.153480 0.0;M3 CHK:0;cm4_sp_mode 0
932 22:24:42.154178 MVN_1=0x00000000
933 22:24:42.158926 MVN_2=0x00000000
934 22:24:42.164660 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 22:24:42.165015 OPS=0x10
936 22:24:42.165242 ring efuse init
937 22:24:42.165465 chipver efuse init
938 22:24:42.172862 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 22:24:42.173386 [0.018960 Inits done]
940 22:24:42.180471 secure task start!
941 22:24:42.180993 high task start!
942 22:24:42.181346 low task start!
943 22:24:42.181676 run into bl31
944 22:24:42.187143 NOTICE: BL31: v1.3(release):4fc40b1
945 22:24:42.194915 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 22:24:42.195282 NOTICE: BL31: G12A normal boot!
947 22:24:42.220399 NOTICE: BL31: BL33 decompress pass
948 22:24:42.225929 ERROR: Error initializing runtime service opteed_fast
949 22:24:43.458881
950 22:24:43.459287
951 22:24:43.467336 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 22:24:43.467815
953 22:24:43.468174 Model: Libre Computer AML-A311D-CC Alta
954 22:24:43.674781 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 22:24:43.698234 DRAM: 2 GiB (effective 3.8 GiB)
956 22:24:43.842115 Core: 408 devices, 31 uclasses, devicetree: separate
957 22:24:43.846896 WDT: Not starting watchdog@f0d0
958 22:24:43.880199 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 22:24:43.892572 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 22:24:43.896649 ** Bad device specification mmc 0 **
961 22:24:43.907917 Card did not respond to voltage select! : -110
962 22:24:43.915604 ** Bad device specification mmc 0 **
963 22:24:43.915964 Couldn't find partition mmc 0
964 22:24:43.923920 Card did not respond to voltage select! : -110
965 22:24:43.929503 ** Bad device specification mmc 0 **
966 22:24:43.929837 Couldn't find partition mmc 0
967 22:24:43.934561 Error: could not access storage.
968 22:24:44.277040 Net: eth0: ethernet@ff3f0000
969 22:24:44.277456 starting USB...
970 22:24:44.528795 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 22:24:44.529212 Starting the controller
972 22:24:44.535804 USB XHCI 1.10
973 22:24:46.399902 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
974 22:24:46.400548 bl2_stage_init 0x01
975 22:24:46.400806 bl2_stage_init 0x81
976 22:24:46.405409 hw id: 0x0000 - pwm id 0x01
977 22:24:46.405747 bl2_stage_init 0xc1
978 22:24:46.405961 bl2_stage_init 0x02
979 22:24:46.406167
980 22:24:46.411316 L0:00000000
981 22:24:46.411712 L1:20000703
982 22:24:46.411939 L2:00008067
983 22:24:46.412183 L3:14000000
984 22:24:46.414052 B2:00402000
985 22:24:46.414372 B1:e0f83180
986 22:24:46.414591
987 22:24:46.414805 TE: 58159
988 22:24:46.415012
989 22:24:46.425006 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 22:24:46.425572
991 22:24:46.425916 Board ID = 1
992 22:24:46.426241 Set A53 clk to 24M
993 22:24:46.426558 Set A73 clk to 24M
994 22:24:46.430469 Set clk81 to 24M
995 22:24:46.430900 A53 clk: 1200 MHz
996 22:24:46.431222 A73 clk: 1200 MHz
997 22:24:46.436083 CLK81: 166.6M
998 22:24:46.436430 smccc: 00012ab5
999 22:24:46.441801 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 22:24:46.442289 board id: 1
1001 22:24:46.450591 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 22:24:46.461121 fw parse done
1003 22:24:46.467121 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 22:24:46.510512 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 22:24:46.520684 PIEI prepare done
1006 22:24:46.521104 fastboot data load
1007 22:24:46.521358 fastboot data verify
1008 22:24:46.526304 verify result: 266
1009 22:24:46.531860 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 22:24:46.532251 LPDDR4 probe
1011 22:24:46.532474 ddr clk to 1584MHz
1012 22:24:46.539833 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 22:24:46.577369
1014 22:24:46.578007 dmc_version 0001
1015 22:24:46.582825 Check phy result
1016 22:24:46.589793 INFO : End of CA training
1017 22:24:46.590344 INFO : End of initialization
1018 22:24:46.595293 INFO : Training has run successfully!
1019 22:24:46.595893 Check phy result
1020 22:24:46.600885 INFO : End of initialization
1021 22:24:46.601248 INFO : End of read enable training
1022 22:24:46.606405 INFO : End of fine write leveling
1023 22:24:46.612055 INFO : End of Write leveling coarse delay
1024 22:24:46.612632 INFO : Training has run successfully!
1025 22:24:46.613102 Check phy result
1026 22:24:46.617602 INFO : End of initialization
1027 22:24:46.618188 INFO : End of read dq deskew training
1028 22:24:46.623216 INFO : End of MPR read delay center optimization
1029 22:24:46.629147 INFO : End of write delay center optimization
1030 22:24:46.634457 INFO : End of read delay center optimization
1031 22:24:46.635016 INFO : End of max read latency training
1032 22:24:46.640202 INFO : Training has run successfully!
1033 22:24:46.640576 1D training succeed
1034 22:24:46.649263 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 22:24:46.695962 Check phy result
1036 22:24:46.696558 INFO : End of initialization
1037 22:24:46.719261 INFO : End of 2D read delay Voltage center optimization
1038 22:24:46.739367 INFO : End of 2D read delay Voltage center optimization
1039 22:24:46.791798 INFO : End of 2D write delay Voltage center optimization
1040 22:24:46.840558 INFO : End of 2D write delay Voltage center optimization
1041 22:24:46.846180 INFO : Training has run successfully!
1042 22:24:46.846570
1043 22:24:46.846851 channel==0
1044 22:24:46.851920 RxClkDly_Margin_A0==88 ps 9
1045 22:24:46.852620 TxDqDly_Margin_A0==98 ps 10
1046 22:24:46.857337 RxClkDly_Margin_A1==88 ps 9
1047 22:24:46.857714 TxDqDly_Margin_A1==88 ps 9
1048 22:24:46.857996 TrainedVREFDQ_A0==74
1049 22:24:46.863051 TrainedVREFDQ_A1==74
1050 22:24:46.863928 VrefDac_Margin_A0==25
1051 22:24:46.864613 DeviceVref_Margin_A0==40
1052 22:24:46.868781 VrefDac_Margin_A1==24
1053 22:24:46.869493 DeviceVref_Margin_A1==40
1054 22:24:46.870081
1055 22:24:46.870603
1056 22:24:46.870903 channel==1
1057 22:24:46.874357 RxClkDly_Margin_A0==98 ps 10
1058 22:24:46.874739 TxDqDly_Margin_A0==98 ps 10
1059 22:24:46.879910 RxClkDly_Margin_A1==98 ps 10
1060 22:24:46.880491 TxDqDly_Margin_A1==88 ps 9
1061 22:24:46.885323 TrainedVREFDQ_A0==76
1062 22:24:46.885886 TrainedVREFDQ_A1==77
1063 22:24:46.886371 VrefDac_Margin_A0==22
1064 22:24:46.890876 DeviceVref_Margin_A0==38
1065 22:24:46.891453 VrefDac_Margin_A1==22
1066 22:24:46.896371 DeviceVref_Margin_A1==37
1067 22:24:46.896917
1068 22:24:46.897402 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 22:24:46.897851
1070 22:24:46.930327 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
1071 22:24:46.930837 2D training succeed
1072 22:24:46.935733 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 22:24:46.941189 auto size-- 65535DDR cs0 size: 2048MB
1074 22:24:46.941702 DDR cs1 size: 2048MB
1075 22:24:46.946752 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 22:24:46.947394 cs0 DataBus test pass
1077 22:24:46.952298 cs1 DataBus test pass
1078 22:24:46.952702 cs0 AddrBus test pass
1079 22:24:46.953491 cs1 AddrBus test pass
1080 22:24:46.954389
1081 22:24:46.958056 100bdlr_step_size ps== 420
1082 22:24:46.958985 result report
1083 22:24:46.963552 boot times 0Enable ddr reg access
1084 22:24:46.968871 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 22:24:46.982311 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 22:24:47.554334 0.0;M3 CHK:0;cm4_sp_mode 0
1087 22:24:47.554764 MVN_1=0x00000000
1088 22:24:47.559808 MVN_2=0x00000000
1089 22:24:47.565568 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 22:24:47.565913 OPS=0x10
1091 22:24:47.566144 ring efuse init
1092 22:24:47.566363 chipver efuse init
1093 22:24:47.573815 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 22:24:47.574179 [0.018961 Inits done]
1095 22:24:47.581399 secure task start!
1096 22:24:47.581762 high task start!
1097 22:24:47.581998 low task start!
1098 22:24:47.582220 run into bl31
1099 22:24:47.588098 NOTICE: BL31: v1.3(release):4fc40b1
1100 22:24:47.595875 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 22:24:47.596301 NOTICE: BL31: G12A normal boot!
1102 22:24:47.621568 NOTICE: BL31: BL33 decompress pass
1103 22:24:47.627243 ERROR: Error initializing runtime service opteed_fast
1104 22:24:48.860047
1105 22:24:48.860763
1106 22:24:48.868409 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 22:24:48.868977
1108 22:24:48.869401 Model: Libre Computer AML-A311D-CC Alta
1109 22:24:49.076800 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 22:24:49.100178 DRAM: 2 GiB (effective 3.8 GiB)
1111 22:24:49.243297 Core: 408 devices, 31 uclasses, devicetree: separate
1112 22:24:49.248273 WDT: Not starting watchdog@f0d0
1113 22:24:49.281348 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 22:24:49.293728 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 22:24:49.298709 ** Bad device specification mmc 0 **
1116 22:24:49.309062 Card did not respond to voltage select! : -110
1117 22:24:49.316689 ** Bad device specification mmc 0 **
1118 22:24:49.317023 Couldn't find partition mmc 0
1119 22:24:49.325025 Card did not respond to voltage select! : -110
1120 22:24:49.330537 ** Bad device specification mmc 0 **
1121 22:24:49.330865 Couldn't find partition mmc 0
1122 22:24:49.335586 Error: could not access storage.
1123 22:24:49.677119 Net: eth0: ethernet@ff3f0000
1124 22:24:49.677510 starting USB...
1125 22:24:49.929876 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 22:24:49.930297 Starting the controller
1127 22:24:49.936833 USB XHCI 1.10
1128 22:24:51.492894 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 22:24:51.501273 scanning usb for storage devices... 0 Storage Device(s) found
1131 22:24:51.552430 Hit any key to stop autoboot: 1
1132 22:24:51.553263 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1133 22:24:51.553629 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1134 22:24:51.553900 Setting prompt string to ['=>']
1135 22:24:51.554157 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1136 22:24:51.558742 0
1137 22:24:51.559357 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 22:24:51.559636 Sending with 10 millisecond of delay
1140 22:24:52.694162 => setenv autoload no
1141 22:24:52.705075 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1142 22:24:52.707686 setenv autoload no
1143 22:24:52.708194 Sending with 10 millisecond of delay
1145 22:24:54.505151 => setenv initrd_high 0xffffffff
1146 22:24:54.516109 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1147 22:24:54.516719 setenv initrd_high 0xffffffff
1148 22:24:54.517192 Sending with 10 millisecond of delay
1150 22:24:56.133060 => setenv fdt_high 0xffffffff
1151 22:24:56.143946 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1152 22:24:56.144541 setenv fdt_high 0xffffffff
1153 22:24:56.145005 Sending with 10 millisecond of delay
1155 22:24:56.436461 => dhcp
1156 22:24:56.447019 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1157 22:24:56.447547 dhcp
1158 22:24:56.447785 Speed: 1000, full duplex
1159 22:24:56.448030 BOOTP broadcast 1
1160 22:24:56.456737 DHCP client bound to address 192.168.6.27 (10 ms)
1161 22:24:56.457255 Sending with 10 millisecond of delay
1163 22:24:58.133575 => setenv serverip 192.168.6.2
1164 22:24:58.144776 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1165 22:24:58.145773 setenv serverip 192.168.6.2
1166 22:24:58.146519 Sending with 10 millisecond of delay
1168 22:25:01.872272 => tftpboot 0x01080000 955483/tftp-deploy-83s6wpzo/kernel/uImage
1169 22:25:01.882823 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1170 22:25:01.883356 tftpboot 0x01080000 955483/tftp-deploy-83s6wpzo/kernel/uImage
1171 22:25:01.883604 Speed: 1000, full duplex
1172 22:25:01.883829 Using ethernet@ff3f0000 device
1173 22:25:01.885514 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1174 22:25:01.891138 Filename '955483/tftp-deploy-83s6wpzo/kernel/uImage'.
1175 22:25:01.895173 Load address: 0x1080000
1176 22:25:04.843543 Loading: *################################################## 43.6 MiB
1177 22:25:04.844263 14.8 MiB/s
1178 22:25:04.844759 done
1179 22:25:04.847214 Bytes transferred = 45713984 (2b98a40 hex)
1180 22:25:04.848074 Sending with 10 millisecond of delay
1182 22:25:09.543541 => tftpboot 0x08000000 955483/tftp-deploy-83s6wpzo/ramdisk/ramdisk.cpio.gz.uboot
1183 22:25:09.554151 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1184 22:25:09.555117 tftpboot 0x08000000 955483/tftp-deploy-83s6wpzo/ramdisk/ramdisk.cpio.gz.uboot
1185 22:25:09.555615 Speed: 1000, full duplex
1186 22:25:09.556114 Using ethernet@ff3f0000 device
1187 22:25:09.556745 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1188 22:25:09.565357 Filename '955483/tftp-deploy-83s6wpzo/ramdisk/ramdisk.cpio.gz.uboot'.
1189 22:25:09.565942 Load address: 0x8000000
1190 22:25:16.150643 Loading: *###############T ################################## UDP wrong checksum 00000005 00009ab4
1191 22:25:18.074459 UDP wrong checksum 000000ff 0000202e
1192 22:25:18.086553 UDP wrong checksum 000000ff 0000a920
1193 22:25:18.816684 UDP wrong checksum 000000ff 00000c42
1194 22:25:18.897365 UDP wrong checksum 000000ff 0000a534
1195 22:25:21.152244 T UDP wrong checksum 00000005 00009ab4
1196 22:25:26.777581 T UDP wrong checksum 000000ff 00000ab6
1197 22:25:26.790030 UDP wrong checksum 000000ff 00009fa8
1198 22:25:31.153985 T UDP wrong checksum 00000005 00009ab4
1199 22:25:47.003017 T T T UDP wrong checksum 000000ff 00003fb9
1200 22:25:47.013686 UDP wrong checksum 000000ff 0000d3ab
1201 22:25:47.607660 UDP wrong checksum 000000ff 0000468b
1202 22:25:47.650241 UDP wrong checksum 000000ff 0000d07d
1203 22:25:51.155952 UDP wrong checksum 00000005 00009ab4
1204 22:26:06.162073 T T T
1205 22:26:06.162729 Retry count exceeded; starting again
1207 22:26:06.164351 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1210 22:26:06.166532 end: 2.4 uboot-commands (duration 00:01:52) [common]
1212 22:26:06.168095 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1214 22:26:06.169286 end: 2 uboot-action (duration 00:01:52) [common]
1216 22:26:06.170949 Cleaning after the job
1217 22:26:06.171540 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/ramdisk
1218 22:26:06.173097 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/kernel
1219 22:26:06.226614 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/dtb
1220 22:26:06.228172 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/nfsrootfs
1221 22:26:06.272365 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955483/tftp-deploy-83s6wpzo/modules
1222 22:26:06.276787 start: 4.1 power-off (timeout 00:00:30) [common]
1223 22:26:06.277372 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1224 22:26:06.310085 >> OK - accepted request
1225 22:26:06.312072 Returned 0 in 0 seconds
1226 22:26:06.412996 end: 4.1 power-off (duration 00:00:00) [common]
1228 22:26:06.414342 start: 4.2 read-feedback (timeout 00:10:00) [common]
1229 22:26:06.415178 Listened to connection for namespace 'common' for up to 1s
1230 22:26:07.416108 Finalising connection for namespace 'common'
1231 22:26:07.416673 Disconnecting from shell: Finalise
1232 22:26:07.417024 =>
1233 22:26:07.517992 end: 4.2 read-feedback (duration 00:00:01) [common]
1234 22:26:07.518985 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/955483
1235 22:26:10.771639 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/955483
1236 22:26:10.772351 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.