Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:26:51.898353 lava-dispatcher, installed at version: 2024.01
2 22:26:51.899147 start: 0 validate
3 22:26:51.899621 Start time: 2024-11-07 22:26:51.899591+00:00 (UTC)
4 22:26:51.900167 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:26:51.900702 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:26:51.944817 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:26:51.945357 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 22:26:51.981534 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:26:51.982167 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 22:26:52.015643 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:26:52.016213 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:26:52.052793 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 22:26:52.053304 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc5-245-g6f5f585ff3e63%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 22:26:52.100964 validate duration: 0.20
16 22:26:52.102857 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:26:52.103616 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:26:52.104423 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:26:52.105615 Not decompressing ramdisk as can be used compressed.
20 22:26:52.106582 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 22:26:52.107233 saving as /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/ramdisk/initrd.cpio.gz
22 22:26:52.107854 total size: 5628169 (5 MB)
23 22:26:52.155005 progress 0 % (0 MB)
24 22:26:52.162762 progress 5 % (0 MB)
25 22:26:52.171104 progress 10 % (0 MB)
26 22:26:52.178475 progress 15 % (0 MB)
27 22:26:52.186462 progress 20 % (1 MB)
28 22:26:52.190875 progress 25 % (1 MB)
29 22:26:52.195041 progress 30 % (1 MB)
30 22:26:52.199355 progress 35 % (1 MB)
31 22:26:52.203151 progress 40 % (2 MB)
32 22:26:52.207419 progress 45 % (2 MB)
33 22:26:52.211319 progress 50 % (2 MB)
34 22:26:52.215601 progress 55 % (2 MB)
35 22:26:52.219901 progress 60 % (3 MB)
36 22:26:52.223754 progress 65 % (3 MB)
37 22:26:52.228067 progress 70 % (3 MB)
38 22:26:52.231866 progress 75 % (4 MB)
39 22:26:52.236123 progress 80 % (4 MB)
40 22:26:52.239926 progress 85 % (4 MB)
41 22:26:52.244188 progress 90 % (4 MB)
42 22:26:52.248255 progress 95 % (5 MB)
43 22:26:52.251524 progress 100 % (5 MB)
44 22:26:52.252184 5 MB downloaded in 0.14 s (37.19 MB/s)
45 22:26:52.252747 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:26:52.253633 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:26:52.253921 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:26:52.254190 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:26:52.254658 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/kernel/Image
51 22:26:52.254926 saving as /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/kernel/Image
52 22:26:52.255139 total size: 45713920 (43 MB)
53 22:26:52.255351 No compression specified
54 22:26:52.296206 progress 0 % (0 MB)
55 22:26:52.330897 progress 5 % (2 MB)
56 22:26:52.363885 progress 10 % (4 MB)
57 22:26:52.394244 progress 15 % (6 MB)
58 22:26:52.425765 progress 20 % (8 MB)
59 22:26:52.455899 progress 25 % (10 MB)
60 22:26:52.486609 progress 30 % (13 MB)
61 22:26:52.517085 progress 35 % (15 MB)
62 22:26:52.547678 progress 40 % (17 MB)
63 22:26:52.577709 progress 45 % (19 MB)
64 22:26:52.608455 progress 50 % (21 MB)
65 22:26:52.638932 progress 55 % (24 MB)
66 22:26:52.669453 progress 60 % (26 MB)
67 22:26:52.699633 progress 65 % (28 MB)
68 22:26:52.730145 progress 70 % (30 MB)
69 22:26:52.760638 progress 75 % (32 MB)
70 22:26:52.791009 progress 80 % (34 MB)
71 22:26:52.821163 progress 85 % (37 MB)
72 22:26:52.851626 progress 90 % (39 MB)
73 22:26:52.882156 progress 95 % (41 MB)
74 22:26:52.911907 progress 100 % (43 MB)
75 22:26:52.912528 43 MB downloaded in 0.66 s (66.32 MB/s)
76 22:26:52.913040 end: 1.2.1 http-download (duration 00:00:01) [common]
78 22:26:52.913904 end: 1.2 download-retry (duration 00:00:01) [common]
79 22:26:52.914199 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:26:52.914482 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:26:52.915081 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 22:26:52.915385 saving as /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/dtb/meson-g12b-a311d-libretech-cc.dtb
83 22:26:52.915609 total size: 54703 (0 MB)
84 22:26:52.915830 No compression specified
85 22:26:52.953984 progress 59 % (0 MB)
86 22:26:52.954882 progress 100 % (0 MB)
87 22:26:52.955460 0 MB downloaded in 0.04 s (1.31 MB/s)
88 22:26:52.955948 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:26:52.956836 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:26:52.957113 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:26:52.957392 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:26:52.957862 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 22:26:52.958116 saving as /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/nfsrootfs/full.rootfs.tar
95 22:26:52.958333 total size: 120894716 (115 MB)
96 22:26:52.958550 Using unxz to decompress xz
97 22:26:52.992419 progress 0 % (0 MB)
98 22:26:53.785356 progress 5 % (5 MB)
99 22:26:54.671879 progress 10 % (11 MB)
100 22:26:55.460135 progress 15 % (17 MB)
101 22:26:56.197337 progress 20 % (23 MB)
102 22:26:56.791907 progress 25 % (28 MB)
103 22:26:57.610793 progress 30 % (34 MB)
104 22:26:58.399525 progress 35 % (40 MB)
105 22:26:58.746167 progress 40 % (46 MB)
106 22:26:59.133792 progress 45 % (51 MB)
107 22:26:59.862629 progress 50 % (57 MB)
108 22:27:00.746760 progress 55 % (63 MB)
109 22:27:01.544029 progress 60 % (69 MB)
110 22:27:02.384208 progress 65 % (74 MB)
111 22:27:03.282731 progress 70 % (80 MB)
112 22:27:04.110875 progress 75 % (86 MB)
113 22:27:04.914529 progress 80 % (92 MB)
114 22:27:05.691153 progress 85 % (98 MB)
115 22:27:06.549335 progress 90 % (103 MB)
116 22:27:07.326334 progress 95 % (109 MB)
117 22:27:08.162200 progress 100 % (115 MB)
118 22:27:08.174707 115 MB downloaded in 15.22 s (7.58 MB/s)
119 22:27:08.175290 end: 1.4.1 http-download (duration 00:00:15) [common]
121 22:27:08.176348 end: 1.4 download-retry (duration 00:00:15) [common]
122 22:27:08.176925 start: 1.5 download-retry (timeout 00:09:44) [common]
123 22:27:08.177509 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 22:27:08.178424 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/modules.tar.xz
125 22:27:08.178929 saving as /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/modules/modules.tar
126 22:27:08.179373 total size: 11624536 (11 MB)
127 22:27:08.179827 Using unxz to decompress xz
128 22:27:08.219319 progress 0 % (0 MB)
129 22:27:08.284999 progress 5 % (0 MB)
130 22:27:08.359825 progress 10 % (1 MB)
131 22:27:08.459793 progress 15 % (1 MB)
132 22:27:08.552045 progress 20 % (2 MB)
133 22:27:08.634283 progress 25 % (2 MB)
134 22:27:08.710192 progress 30 % (3 MB)
135 22:27:08.789466 progress 35 % (3 MB)
136 22:27:08.862310 progress 40 % (4 MB)
137 22:27:08.938408 progress 45 % (5 MB)
138 22:27:09.023531 progress 50 % (5 MB)
139 22:27:09.105691 progress 55 % (6 MB)
140 22:27:09.187132 progress 60 % (6 MB)
141 22:27:09.268088 progress 65 % (7 MB)
142 22:27:09.349902 progress 70 % (7 MB)
143 22:27:09.432272 progress 75 % (8 MB)
144 22:27:09.510995 progress 80 % (8 MB)
145 22:27:09.591926 progress 85 % (9 MB)
146 22:27:09.674817 progress 90 % (10 MB)
147 22:27:09.752676 progress 95 % (10 MB)
148 22:27:09.825673 progress 100 % (11 MB)
149 22:27:09.839781 11 MB downloaded in 1.66 s (6.68 MB/s)
150 22:27:09.840628 end: 1.5.1 http-download (duration 00:00:02) [common]
152 22:27:09.842298 end: 1.5 download-retry (duration 00:00:02) [common]
153 22:27:09.842816 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 22:27:09.843332 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 22:27:28.314859 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/955488/extract-nfsrootfs-_c_hei02
156 22:27:28.315453 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
157 22:27:28.315739 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
158 22:27:28.316506 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x
159 22:27:28.316988 makedir: /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin
160 22:27:28.317322 makedir: /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/tests
161 22:27:28.317636 makedir: /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/results
162 22:27:28.317970 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-add-keys
163 22:27:28.318539 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-add-sources
164 22:27:28.319095 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-background-process-start
165 22:27:28.319602 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-background-process-stop
166 22:27:28.320169 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-common-functions
167 22:27:28.320693 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-echo-ipv4
168 22:27:28.321190 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-install-packages
169 22:27:28.321679 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-installed-packages
170 22:27:28.322185 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-os-build
171 22:27:28.322692 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-probe-channel
172 22:27:28.323183 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-probe-ip
173 22:27:28.323672 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-target-ip
174 22:27:28.324209 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-target-mac
175 22:27:28.324728 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-target-storage
176 22:27:28.325235 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-test-case
177 22:27:28.325754 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-test-event
178 22:27:28.326265 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-test-feedback
179 22:27:28.326758 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-test-raise
180 22:27:28.327244 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-test-reference
181 22:27:28.327732 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-test-runner
182 22:27:28.328270 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-test-set
183 22:27:28.328773 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-test-shell
184 22:27:28.329292 Updating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-add-keys (debian)
185 22:27:28.329851 Updating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-add-sources (debian)
186 22:27:28.330370 Updating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-install-packages (debian)
187 22:27:28.330878 Updating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-installed-packages (debian)
188 22:27:28.331383 Updating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/bin/lava-os-build (debian)
189 22:27:28.331827 Creating /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/environment
190 22:27:28.332251 LAVA metadata
191 22:27:28.332521 - LAVA_JOB_ID=955488
192 22:27:28.332739 - LAVA_DISPATCHER_IP=192.168.6.2
193 22:27:28.333118 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
194 22:27:28.334114 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 22:27:28.334445 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
196 22:27:28.334653 skipped lava-vland-overlay
197 22:27:28.334893 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 22:27:28.335145 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
199 22:27:28.335367 skipped lava-multinode-overlay
200 22:27:28.335609 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 22:27:28.335860 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
202 22:27:28.336144 Loading test definitions
203 22:27:28.336438 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
204 22:27:28.336659 Using /lava-955488 at stage 0
205 22:27:28.337831 uuid=955488_1.6.2.4.1 testdef=None
206 22:27:28.338145 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 22:27:28.338409 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
208 22:27:28.340050 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 22:27:28.340861 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
211 22:27:28.342833 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 22:27:28.343667 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
214 22:27:28.345566 runner path: /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/0/tests/0_timesync-off test_uuid 955488_1.6.2.4.1
215 22:27:28.346153 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 22:27:28.346977 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
218 22:27:28.347203 Using /lava-955488 at stage 0
219 22:27:28.347564 Fetching tests from https://github.com/kernelci/test-definitions.git
220 22:27:28.347858 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/0/tests/1_kselftest-rtc'
221 22:27:31.745684 Running '/usr/bin/git checkout kernelci.org
222 22:27:32.210702 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 22:27:32.213249 uuid=955488_1.6.2.4.5 testdef=None
224 22:27:32.213928 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 22:27:32.215438 start: 1.6.2.4.6 test-overlay (timeout 00:09:20) [common]
227 22:27:32.221371 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 22:27:32.223234 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:20) [common]
230 22:27:32.231065 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 22:27:32.232897 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:20) [common]
233 22:27:32.240320 runner path: /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/0/tests/1_kselftest-rtc test_uuid 955488_1.6.2.4.5
234 22:27:32.240928 BOARD='meson-g12b-a311d-libretech-cc'
235 22:27:32.241339 BRANCH='broonie-sound'
236 22:27:32.241735 SKIPFILE='/dev/null'
237 22:27:32.242134 SKIP_INSTALL='True'
238 22:27:32.242527 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc5-245-g6f5f585ff3e63/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 22:27:32.242933 TST_CASENAME=''
240 22:27:32.243326 TST_CMDFILES='rtc'
241 22:27:32.244474 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 22:27:32.246499 Creating lava-test-runner.conf files
244 22:27:32.246937 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/955488/lava-overlay-1a9_9d1x/lava-955488/0 for stage 0
245 22:27:32.247631 - 0_timesync-off
246 22:27:32.248159 - 1_kselftest-rtc
247 22:27:32.248845 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 22:27:32.249419 start: 1.6.2.5 compress-overlay (timeout 00:09:20) [common]
249 22:27:56.586522 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 22:27:56.586976 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:56) [common]
251 22:27:56.587272 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 22:27:56.587584 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 22:27:56.587880 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:56) [common]
254 22:27:57.209959 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 22:27:57.210446 start: 1.6.4 extract-modules (timeout 00:08:55) [common]
256 22:27:57.210718 extracting modules file /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955488/extract-nfsrootfs-_c_hei02
257 22:27:58.767294 extracting modules file /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955488/extract-overlay-ramdisk-o9kwl33s/ramdisk
258 22:28:00.179753 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 22:28:00.180270 start: 1.6.5 apply-overlay-tftp (timeout 00:08:52) [common]
260 22:28:00.180577 [common] Applying overlay to NFS
261 22:28:00.180810 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955488/compress-overlay-dlf2p5mq/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/955488/extract-nfsrootfs-_c_hei02
262 22:28:03.107084 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 22:28:03.107576 start: 1.6.6 prepare-kernel (timeout 00:08:49) [common]
264 22:28:03.107892 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:49) [common]
265 22:28:03.108188 Converting downloaded kernel to a uImage
266 22:28:03.108525 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/kernel/Image /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/kernel/uImage
267 22:28:03.644924 output: Image Name:
268 22:28:03.645350 output: Created: Thu Nov 7 22:28:03 2024
269 22:28:03.645565 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 22:28:03.645773 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 22:28:03.645978 output: Load Address: 01080000
272 22:28:03.646181 output: Entry Point: 01080000
273 22:28:03.646381 output:
274 22:28:03.646712 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 22:28:03.646983 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 22:28:03.647255 start: 1.6.7 configure-preseed-file (timeout 00:08:48) [common]
277 22:28:03.647511 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 22:28:03.647770 start: 1.6.8 compress-ramdisk (timeout 00:08:48) [common]
279 22:28:03.648059 Building ramdisk /var/lib/lava/dispatcher/tmp/955488/extract-overlay-ramdisk-o9kwl33s/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/955488/extract-overlay-ramdisk-o9kwl33s/ramdisk
280 22:28:06.038437 >> 166792 blocks
281 22:28:13.759907 Adding RAMdisk u-boot header.
282 22:28:13.760621 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/955488/extract-overlay-ramdisk-o9kwl33s/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/955488/extract-overlay-ramdisk-o9kwl33s/ramdisk.cpio.gz.uboot
283 22:28:14.004813 output: Image Name:
284 22:28:14.005238 output: Created: Thu Nov 7 22:28:13 2024
285 22:28:14.005452 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 22:28:14.005661 output: Data Size: 23432285 Bytes = 22883.09 KiB = 22.35 MiB
287 22:28:14.005863 output: Load Address: 00000000
288 22:28:14.006064 output: Entry Point: 00000000
289 22:28:14.006264 output:
290 22:28:14.006943 rename /var/lib/lava/dispatcher/tmp/955488/extract-overlay-ramdisk-o9kwl33s/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/ramdisk/ramdisk.cpio.gz.uboot
291 22:28:14.007373 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 22:28:14.007661 end: 1.6 prepare-tftp-overlay (duration 00:01:04) [common]
293 22:28:14.007963 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:38) [common]
294 22:28:14.008452 No LXC device requested
295 22:28:14.008960 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 22:28:14.009475 start: 1.8 deploy-device-env (timeout 00:08:38) [common]
297 22:28:14.009969 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 22:28:14.010377 Checking files for TFTP limit of 4294967296 bytes.
299 22:28:14.013150 end: 1 tftp-deploy (duration 00:01:22) [common]
300 22:28:14.013728 start: 2 uboot-action (timeout 00:05:00) [common]
301 22:28:14.014245 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 22:28:14.014738 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 22:28:14.015237 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 22:28:14.015764 Using kernel file from prepare-kernel: 955488/tftp-deploy-1z9t64go/kernel/uImage
305 22:28:14.016426 substitutions:
306 22:28:14.016837 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 22:28:14.017239 - {DTB_ADDR}: 0x01070000
308 22:28:14.017637 - {DTB}: 955488/tftp-deploy-1z9t64go/dtb/meson-g12b-a311d-libretech-cc.dtb
309 22:28:14.018038 - {INITRD}: 955488/tftp-deploy-1z9t64go/ramdisk/ramdisk.cpio.gz.uboot
310 22:28:14.018433 - {KERNEL_ADDR}: 0x01080000
311 22:28:14.018823 - {KERNEL}: 955488/tftp-deploy-1z9t64go/kernel/uImage
312 22:28:14.019214 - {LAVA_MAC}: None
313 22:28:14.019642 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/955488/extract-nfsrootfs-_c_hei02
314 22:28:14.020065 - {NFS_SERVER_IP}: 192.168.6.2
315 22:28:14.020463 - {PRESEED_CONFIG}: None
316 22:28:14.020854 - {PRESEED_LOCAL}: None
317 22:28:14.021242 - {RAMDISK_ADDR}: 0x08000000
318 22:28:14.021626 - {RAMDISK}: 955488/tftp-deploy-1z9t64go/ramdisk/ramdisk.cpio.gz.uboot
319 22:28:14.022014 - {ROOT_PART}: None
320 22:28:14.022404 - {ROOT}: None
321 22:28:14.022788 - {SERVER_IP}: 192.168.6.2
322 22:28:14.023171 - {TEE_ADDR}: 0x83000000
323 22:28:14.023555 - {TEE}: None
324 22:28:14.023936 Parsed boot commands:
325 22:28:14.024343 - setenv autoload no
326 22:28:14.024733 - setenv initrd_high 0xffffffff
327 22:28:14.025119 - setenv fdt_high 0xffffffff
328 22:28:14.025507 - dhcp
329 22:28:14.025889 - setenv serverip 192.168.6.2
330 22:28:14.026277 - tftpboot 0x01080000 955488/tftp-deploy-1z9t64go/kernel/uImage
331 22:28:14.026667 - tftpboot 0x08000000 955488/tftp-deploy-1z9t64go/ramdisk/ramdisk.cpio.gz.uboot
332 22:28:14.027054 - tftpboot 0x01070000 955488/tftp-deploy-1z9t64go/dtb/meson-g12b-a311d-libretech-cc.dtb
333 22:28:14.027441 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/955488/extract-nfsrootfs-_c_hei02,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 22:28:14.027843 - bootm 0x01080000 0x08000000 0x01070000
335 22:28:14.028378 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 22:28:14.029882 start: 2.3 connect-device (timeout 00:05:00) [common]
338 22:28:14.030305 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 22:28:14.045456 Setting prompt string to ['lava-test: # ']
340 22:28:14.046963 end: 2.3 connect-device (duration 00:00:00) [common]
341 22:28:14.047569 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 22:28:14.048202 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 22:28:14.048759 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 22:28:14.049873 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 22:28:14.087158 >> OK - accepted request
346 22:28:14.089029 Returned 0 in 0 seconds
347 22:28:14.190088 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 22:28:14.191634 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 22:28:14.192219 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 22:28:14.192727 Setting prompt string to ['Hit any key to stop autoboot']
352 22:28:14.193175 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 22:28:14.194707 Trying 192.168.56.21...
354 22:28:14.195176 Connected to conserv1.
355 22:28:14.195585 Escape character is '^]'.
356 22:28:14.196023
357 22:28:14.196442 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 22:28:14.196867
359 22:28:26.219371 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 22:28:26.219809 bl2_stage_init 0x01
361 22:28:26.220082 bl2_stage_init 0x81
362 22:28:26.224914 hw id: 0x0000 - pwm id 0x01
363 22:28:26.225231 bl2_stage_init 0xc1
364 22:28:26.225462 bl2_stage_init 0x02
365 22:28:26.225685
366 22:28:26.230537 L0:00000000
367 22:28:26.230809 L1:20000703
368 22:28:26.231030 L2:00008067
369 22:28:26.231244 L3:14000000
370 22:28:26.233459 B2:00402000
371 22:28:26.233716 B1:e0f83180
372 22:28:26.233924
373 22:28:26.234128 TE: 58124
374 22:28:26.234335
375 22:28:26.244713 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 22:28:26.244990
377 22:28:26.245200 Board ID = 1
378 22:28:26.245402 Set A53 clk to 24M
379 22:28:26.245601 Set A73 clk to 24M
380 22:28:26.250181 Set clk81 to 24M
381 22:28:26.250450 A53 clk: 1200 MHz
382 22:28:26.250655 A73 clk: 1200 MHz
383 22:28:26.255819 CLK81: 166.6M
384 22:28:26.256091 smccc: 00012a91
385 22:28:26.261456 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 22:28:26.261717 board id: 1
387 22:28:26.269043 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 22:28:26.280518 fw parse done
389 22:28:26.286133 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 22:28:26.328506 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 22:28:26.339955 PIEI prepare done
392 22:28:26.340251 fastboot data load
393 22:28:26.340457 fastboot data verify
394 22:28:26.345684 verify result: 266
395 22:28:26.351249 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 22:28:26.351500 LPDDR4 probe
397 22:28:26.351707 ddr clk to 1584MHz
398 22:28:26.358342 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 22:28:26.396282
400 22:28:26.396653 dmc_version 0001
401 22:28:26.402272 Check phy result
402 22:28:26.409025 INFO : End of CA training
403 22:28:26.409322 INFO : End of initialization
404 22:28:26.414622 INFO : Training has run successfully!
405 22:28:26.414936 Check phy result
406 22:28:26.420188 INFO : End of initialization
407 22:28:26.420473 INFO : End of read enable training
408 22:28:26.423590 INFO : End of fine write leveling
409 22:28:26.429025 INFO : End of Write leveling coarse delay
410 22:28:26.434658 INFO : Training has run successfully!
411 22:28:26.434918 Check phy result
412 22:28:26.435150 INFO : End of initialization
413 22:28:26.440241 INFO : End of read dq deskew training
414 22:28:26.445822 INFO : End of MPR read delay center optimization
415 22:28:26.446090 INFO : End of write delay center optimization
416 22:28:26.451392 INFO : End of read delay center optimization
417 22:28:26.457029 INFO : End of max read latency training
418 22:28:26.457296 INFO : Training has run successfully!
419 22:28:26.462631 1D training succeed
420 22:28:26.468598 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 22:28:26.516223 Check phy result
422 22:28:26.516621 INFO : End of initialization
423 22:28:26.538051 INFO : End of 2D read delay Voltage center optimization
424 22:28:26.557694 INFO : End of 2D read delay Voltage center optimization
425 22:28:26.610393 INFO : End of 2D write delay Voltage center optimization
426 22:28:26.659647 INFO : End of 2D write delay Voltage center optimization
427 22:28:26.665166 INFO : Training has run successfully!
428 22:28:26.665431
429 22:28:26.665641 channel==0
430 22:28:26.670760 RxClkDly_Margin_A0==88 ps 9
431 22:28:26.671002 TxDqDly_Margin_A0==98 ps 10
432 22:28:26.676395 RxClkDly_Margin_A1==88 ps 9
433 22:28:26.676630 TxDqDly_Margin_A1==98 ps 10
434 22:28:26.676838 TrainedVREFDQ_A0==74
435 22:28:26.681941 TrainedVREFDQ_A1==74
436 22:28:26.682194 VrefDac_Margin_A0==25
437 22:28:26.682403 DeviceVref_Margin_A0==40
438 22:28:26.687530 VrefDac_Margin_A1==25
439 22:28:26.687765 DeviceVref_Margin_A1==40
440 22:28:26.687971
441 22:28:26.688209
442 22:28:26.693171 channel==1
443 22:28:26.693417 RxClkDly_Margin_A0==98 ps 10
444 22:28:26.693625 TxDqDly_Margin_A0==98 ps 10
445 22:28:26.698737 RxClkDly_Margin_A1==98 ps 10
446 22:28:26.698979 TxDqDly_Margin_A1==98 ps 10
447 22:28:26.704432 TrainedVREFDQ_A0==77
448 22:28:26.704669 TrainedVREFDQ_A1==77
449 22:28:26.704876 VrefDac_Margin_A0==22
450 22:28:26.709952 DeviceVref_Margin_A0==37
451 22:28:26.710220 VrefDac_Margin_A1==24
452 22:28:26.715538 DeviceVref_Margin_A1==37
453 22:28:26.715775
454 22:28:26.716007 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 22:28:26.721160
456 22:28:26.749160 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 22:28:26.749469 2D training succeed
458 22:28:26.754766 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 22:28:26.760425 auto size-- 65535DDR cs0 size: 2048MB
460 22:28:26.760666 DDR cs1 size: 2048MB
461 22:28:26.765990 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 22:28:26.766250 cs0 DataBus test pass
463 22:28:26.771548 cs1 DataBus test pass
464 22:28:26.771788 cs0 AddrBus test pass
465 22:28:26.772018 cs1 AddrBus test pass
466 22:28:26.772334
467 22:28:26.777196 100bdlr_step_size ps== 420
468 22:28:26.777631 result report
469 22:28:26.782792 boot times 0Enable ddr reg access
470 22:28:26.788174 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 22:28:26.801771 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 22:28:27.375454 0.0;M3 CHK:0;cm4_sp_mode 0
473 22:28:27.376184 MVN_1=0x00000000
474 22:28:27.380931 MVN_2=0x00000000
475 22:28:27.386678 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 22:28:27.387186 OPS=0x10
477 22:28:27.387615 ring efuse init
478 22:28:27.388064 chipver efuse init
479 22:28:27.392218 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 22:28:27.397849 [0.018961 Inits done]
481 22:28:27.398288 secure task start!
482 22:28:27.398695 high task start!
483 22:28:27.402575 low task start!
484 22:28:27.403030 run into bl31
485 22:28:27.409100 NOTICE: BL31: v1.3(release):4fc40b1
486 22:28:27.416910 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 22:28:27.417400 NOTICE: BL31: G12A normal boot!
488 22:28:27.442245 NOTICE: BL31: BL33 decompress pass
489 22:28:27.447881 ERROR: Error initializing runtime service opteed_fast
490 22:28:28.680861
491 22:28:28.681469
492 22:28:28.688219 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 22:28:28.688694
494 22:28:28.689118 Model: Libre Computer AML-A311D-CC Alta
495 22:28:28.896679 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 22:28:28.920957 DRAM: 2 GiB (effective 3.8 GiB)
497 22:28:29.064035 Core: 408 devices, 31 uclasses, devicetree: separate
498 22:28:29.069265 WDT: Not starting watchdog@f0d0
499 22:28:29.102123 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 22:28:29.114529 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 22:28:29.119132 ** Bad device specification mmc 0 **
502 22:28:29.130003 Card did not respond to voltage select! : -110
503 22:28:29.137405 ** Bad device specification mmc 0 **
504 22:28:29.137836 Couldn't find partition mmc 0
505 22:28:29.145895 Card did not respond to voltage select! : -110
506 22:28:29.151348 ** Bad device specification mmc 0 **
507 22:28:29.151780 Couldn't find partition mmc 0
508 22:28:29.155503 Error: could not access storage.
509 22:28:30.419601 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 22:28:30.420343 bl2_stage_init 0x01
511 22:28:30.420832 bl2_stage_init 0x81
512 22:28:30.425260 hw id: 0x0000 - pwm id 0x01
513 22:28:30.425785 bl2_stage_init 0xc1
514 22:28:30.426248 bl2_stage_init 0x02
515 22:28:30.426699
516 22:28:30.430842 L0:00000000
517 22:28:30.431354 L1:20000703
518 22:28:30.431811 L2:00008067
519 22:28:30.432304 L3:14000000
520 22:28:30.433698 B2:00402000
521 22:28:30.434208 B1:e0f83180
522 22:28:30.434662
523 22:28:30.435111 TE: 58124
524 22:28:30.435621
525 22:28:30.444849 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 22:28:30.445398
527 22:28:30.445857 Board ID = 1
528 22:28:30.446305 Set A53 clk to 24M
529 22:28:30.446749 Set A73 clk to 24M
530 22:28:30.450521 Set clk81 to 24M
531 22:28:30.451037 A53 clk: 1200 MHz
532 22:28:30.451492 A73 clk: 1200 MHz
533 22:28:30.453885 CLK81: 166.6M
534 22:28:30.454389 smccc: 00012a92
535 22:28:30.459414 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 22:28:30.465086 board id: 1
537 22:28:30.469540 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 22:28:30.480920 fw parse done
539 22:28:30.486353 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 22:28:30.528551 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 22:28:30.540338 PIEI prepare done
542 22:28:30.540696 fastboot data load
543 22:28:30.540926 fastboot data verify
544 22:28:30.546013 verify result: 266
545 22:28:30.551508 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 22:28:30.551810 LPDDR4 probe
547 22:28:30.552058 ddr clk to 1584MHz
548 22:28:30.559477 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 22:28:30.596275
550 22:28:30.596642 dmc_version 0001
551 22:28:30.603587 Check phy result
552 22:28:30.609293 INFO : End of CA training
553 22:28:30.609581 INFO : End of initialization
554 22:28:30.614935 INFO : Training has run successfully!
555 22:28:30.615203 Check phy result
556 22:28:30.620443 INFO : End of initialization
557 22:28:30.620722 INFO : End of read enable training
558 22:28:30.626095 INFO : End of fine write leveling
559 22:28:30.631725 INFO : End of Write leveling coarse delay
560 22:28:30.632009 INFO : Training has run successfully!
561 22:28:30.632224 Check phy result
562 22:28:30.637310 INFO : End of initialization
563 22:28:30.637591 INFO : End of read dq deskew training
564 22:28:30.642975 INFO : End of MPR read delay center optimization
565 22:28:30.648468 INFO : End of write delay center optimization
566 22:28:30.654138 INFO : End of read delay center optimization
567 22:28:30.654409 INFO : End of max read latency training
568 22:28:30.659722 INFO : Training has run successfully!
569 22:28:30.660022 1D training succeed
570 22:28:30.667932 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 22:28:30.715545 Check phy result
572 22:28:30.715909 INFO : End of initialization
573 22:28:30.738186 INFO : End of 2D read delay Voltage center optimization
574 22:28:30.758444 INFO : End of 2D read delay Voltage center optimization
575 22:28:30.810486 INFO : End of 2D write delay Voltage center optimization
576 22:28:30.859852 INFO : End of 2D write delay Voltage center optimization
577 22:28:30.865391 INFO : Training has run successfully!
578 22:28:30.865663
579 22:28:30.865879 channel==0
580 22:28:30.871081 RxClkDly_Margin_A0==88 ps 9
581 22:28:30.871389 TxDqDly_Margin_A0==98 ps 10
582 22:28:30.876625 RxClkDly_Margin_A1==88 ps 9
583 22:28:30.877102 TxDqDly_Margin_A1==88 ps 9
584 22:28:30.877537 TrainedVREFDQ_A0==74
585 22:28:30.882180 TrainedVREFDQ_A1==74
586 22:28:30.882658 VrefDac_Margin_A0==25
587 22:28:30.883086 DeviceVref_Margin_A0==40
588 22:28:30.887793 VrefDac_Margin_A1==25
589 22:28:30.888294 DeviceVref_Margin_A1==40
590 22:28:30.888723
591 22:28:30.889149
592 22:28:30.889566 channel==1
593 22:28:30.893373 RxClkDly_Margin_A0==98 ps 10
594 22:28:30.893847 TxDqDly_Margin_A0==88 ps 9
595 22:28:30.898984 RxClkDly_Margin_A1==88 ps 9
596 22:28:30.899455 TxDqDly_Margin_A1==88 ps 9
597 22:28:30.904579 TrainedVREFDQ_A0==76
598 22:28:30.905088 TrainedVREFDQ_A1==77
599 22:28:30.905767 VrefDac_Margin_A0==22
600 22:28:30.910164 DeviceVref_Margin_A0==38
601 22:28:30.910687 VrefDac_Margin_A1==24
602 22:28:30.915843 DeviceVref_Margin_A1==37
603 22:28:30.916379
604 22:28:30.916844 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 22:28:30.917313
606 22:28:30.949403 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
607 22:28:30.949995 2D training succeed
608 22:28:30.954989 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 22:28:30.960588 auto size-- 65535DDR cs0 size: 2048MB
610 22:28:30.961061 DDR cs1 size: 2048MB
611 22:28:30.966159 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 22:28:30.966620 cs0 DataBus test pass
613 22:28:30.971786 cs1 DataBus test pass
614 22:28:30.972285 cs0 AddrBus test pass
615 22:28:30.972710 cs1 AddrBus test pass
616 22:28:30.973119
617 22:28:30.977365 100bdlr_step_size ps== 420
618 22:28:30.977838 result report
619 22:28:30.982987 boot times 0Enable ddr reg access
620 22:28:30.987343 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 22:28:31.002253 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 22:28:31.575778 0.0;M3 CHK:0;cm4_sp_mode 0
623 22:28:31.576528 MVN_1=0x00000000
624 22:28:31.581155 MVN_2=0x00000000
625 22:28:31.586867 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 22:28:31.587446 OPS=0x10
627 22:28:31.587899 ring efuse init
628 22:28:31.588384 chipver efuse init
629 22:28:31.592479 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 22:28:31.598171 [0.018961 Inits done]
631 22:28:31.598718 secure task start!
632 22:28:31.599162 high task start!
633 22:28:31.601902 low task start!
634 22:28:31.602427 run into bl31
635 22:28:31.609331 NOTICE: BL31: v1.3(release):4fc40b1
636 22:28:31.616369 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 22:28:31.616758 NOTICE: BL31: G12A normal boot!
638 22:28:31.642337 NOTICE: BL31: BL33 decompress pass
639 22:28:31.647416 ERROR: Error initializing runtime service opteed_fast
640 22:28:32.880942
641 22:28:32.881601
642 22:28:32.889004 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 22:28:32.889531
644 22:28:32.889999 Model: Libre Computer AML-A311D-CC Alta
645 22:28:33.097843 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 22:28:33.121599 DRAM: 2 GiB (effective 3.8 GiB)
647 22:28:33.264241 Core: 408 devices, 31 uclasses, devicetree: separate
648 22:28:33.270049 WDT: Not starting watchdog@f0d0
649 22:28:33.302305 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 22:28:33.314674 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 22:28:33.319200 ** Bad device specification mmc 0 **
652 22:28:33.330087 Card did not respond to voltage select! : -110
653 22:28:33.337148 ** Bad device specification mmc 0 **
654 22:28:33.337679 Couldn't find partition mmc 0
655 22:28:33.345961 Card did not respond to voltage select! : -110
656 22:28:33.351731 ** Bad device specification mmc 0 **
657 22:28:33.352379 Couldn't find partition mmc 0
658 22:28:33.356560 Error: could not access storage.
659 22:28:33.700167 Net: eth0: ethernet@ff3f0000
660 22:28:33.700836 starting USB...
661 22:28:33.952066 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 22:28:33.952687 Starting the controller
663 22:28:33.958609 USB XHCI 1.10
664 22:28:35.669881 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 22:28:35.670571 bl2_stage_init 0x01
666 22:28:35.671054 bl2_stage_init 0x81
667 22:28:35.675511 hw id: 0x0000 - pwm id 0x01
668 22:28:35.676088 bl2_stage_init 0xc1
669 22:28:35.676562 bl2_stage_init 0x02
670 22:28:35.677015
671 22:28:35.681075 L0:00000000
672 22:28:35.681596 L1:20000703
673 22:28:35.682054 L2:00008067
674 22:28:35.682501 L3:14000000
675 22:28:35.684103 B2:00402000
676 22:28:35.684616 B1:e0f83180
677 22:28:35.685073
678 22:28:35.685520 TE: 58159
679 22:28:35.685965
680 22:28:35.695205 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 22:28:35.695744
682 22:28:35.696240 Board ID = 1
683 22:28:35.696689 Set A53 clk to 24M
684 22:28:35.697132 Set A73 clk to 24M
685 22:28:35.700897 Set clk81 to 24M
686 22:28:35.701412 A53 clk: 1200 MHz
687 22:28:35.701869 A73 clk: 1200 MHz
688 22:28:35.706402 CLK81: 166.6M
689 22:28:35.706925 smccc: 00012ab5
690 22:28:35.712564 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 22:28:35.713084 board id: 1
692 22:28:35.720448 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 22:28:35.731151 fw parse done
694 22:28:35.737208 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 22:28:35.779701 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 22:28:35.790730 PIEI prepare done
697 22:28:35.791266 fastboot data load
698 22:28:35.791729 fastboot data verify
699 22:28:35.796309 verify result: 266
700 22:28:35.801897 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 22:28:35.802420 LPDDR4 probe
702 22:28:35.802876 ddr clk to 1584MHz
703 22:28:35.810001 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 22:28:35.847195
705 22:28:35.847749 dmc_version 0001
706 22:28:35.853843 Check phy result
707 22:28:35.859698 INFO : End of CA training
708 22:28:35.860259 INFO : End of initialization
709 22:28:35.865324 INFO : Training has run successfully!
710 22:28:35.865863 Check phy result
711 22:28:35.870983 INFO : End of initialization
712 22:28:35.871541 INFO : End of read enable training
713 22:28:35.874226 INFO : End of fine write leveling
714 22:28:35.879836 INFO : End of Write leveling coarse delay
715 22:28:35.885364 INFO : Training has run successfully!
716 22:28:35.885894 Check phy result
717 22:28:35.886355 INFO : End of initialization
718 22:28:35.890959 INFO : End of read dq deskew training
719 22:28:35.894348 INFO : End of MPR read delay center optimization
720 22:28:35.899959 INFO : End of write delay center optimization
721 22:28:35.905502 INFO : End of read delay center optimization
722 22:28:35.906024 INFO : End of max read latency training
723 22:28:35.911119 INFO : Training has run successfully!
724 22:28:35.911632 1D training succeed
725 22:28:35.919360 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 22:28:35.966927 Check phy result
727 22:28:35.967492 INFO : End of initialization
728 22:28:35.988662 INFO : End of 2D read delay Voltage center optimization
729 22:28:36.008889 INFO : End of 2D read delay Voltage center optimization
730 22:28:36.061015 INFO : End of 2D write delay Voltage center optimization
731 22:28:36.110514 INFO : End of 2D write delay Voltage center optimization
732 22:28:36.115826 INFO : Training has run successfully!
733 22:28:36.116408
734 22:28:36.116875 channel==0
735 22:28:36.121465 RxClkDly_Margin_A0==88 ps 9
736 22:28:36.121998 TxDqDly_Margin_A0==98 ps 10
737 22:28:36.124858 RxClkDly_Margin_A1==88 ps 9
738 22:28:36.125381 TxDqDly_Margin_A1==88 ps 9
739 22:28:36.130806 TrainedVREFDQ_A0==74
740 22:28:36.131344 TrainedVREFDQ_A1==74
741 22:28:36.131800 VrefDac_Margin_A0==25
742 22:28:36.136139 DeviceVref_Margin_A0==40
743 22:28:36.136686 VrefDac_Margin_A1==25
744 22:28:36.141632 DeviceVref_Margin_A1==40
745 22:28:36.142159
746 22:28:36.142620
747 22:28:36.143073 channel==1
748 22:28:36.143518 RxClkDly_Margin_A0==98 ps 10
749 22:28:36.147280 TxDqDly_Margin_A0==98 ps 10
750 22:28:36.147813 RxClkDly_Margin_A1==98 ps 10
751 22:28:36.152917 TxDqDly_Margin_A1==88 ps 9
752 22:28:36.153711 TrainedVREFDQ_A0==77
753 22:28:36.154222 TrainedVREFDQ_A1==77
754 22:28:36.158570 VrefDac_Margin_A0==22
755 22:28:36.159346 DeviceVref_Margin_A0==37
756 22:28:36.164101 VrefDac_Margin_A1==22
757 22:28:36.164706 DeviceVref_Margin_A1==37
758 22:28:36.165185
759 22:28:36.169776 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 22:28:36.170581
761 22:28:36.197502 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 22:28:36.203178 2D training succeed
763 22:28:36.208777 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 22:28:36.209317 auto size-- 65535DDR cs0 size: 2048MB
765 22:28:36.214370 DDR cs1 size: 2048MB
766 22:28:36.214899 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 22:28:36.220030 cs0 DataBus test pass
768 22:28:36.220563 cs1 DataBus test pass
769 22:28:36.221018 cs0 AddrBus test pass
770 22:28:36.225572 cs1 AddrBus test pass
771 22:28:36.226090
772 22:28:36.226546 100bdlr_step_size ps== 420
773 22:28:36.227008 result report
774 22:28:36.231187 boot times 0Enable ddr reg access
775 22:28:36.238761 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 22:28:36.251819 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 22:28:36.825911 0.0;M3 CHK:0;cm4_sp_mode 0
778 22:28:36.826579 MVN_1=0x00000000
779 22:28:36.831354 MVN_2=0x00000000
780 22:28:36.837160 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 22:28:36.837736 OPS=0x10
782 22:28:36.838188 ring efuse init
783 22:28:36.838620 chipver efuse init
784 22:28:36.842628 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 22:28:36.848261 [0.018961 Inits done]
786 22:28:36.848793 secure task start!
787 22:28:36.849245 high task start!
788 22:28:36.852027 low task start!
789 22:28:36.852537 run into bl31
790 22:28:36.859544 NOTICE: BL31: v1.3(release):4fc40b1
791 22:28:36.866357 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 22:28:36.866869 NOTICE: BL31: G12A normal boot!
793 22:28:36.892803 NOTICE: BL31: BL33 decompress pass
794 22:28:36.898048 ERROR: Error initializing runtime service opteed_fast
795 22:28:38.131207
796 22:28:38.131838
797 22:28:38.138705 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 22:28:38.139239
799 22:28:38.139703 Model: Libre Computer AML-A311D-CC Alta
800 22:28:38.347073 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 22:28:38.371792 DRAM: 2 GiB (effective 3.8 GiB)
802 22:28:38.514484 Core: 408 devices, 31 uclasses, devicetree: separate
803 22:28:38.520468 WDT: Not starting watchdog@f0d0
804 22:28:38.552715 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 22:28:38.565154 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 22:28:38.569182 ** Bad device specification mmc 0 **
807 22:28:38.580374 Card did not respond to voltage select! : -110
808 22:28:38.587155 ** Bad device specification mmc 0 **
809 22:28:38.587766 Couldn't find partition mmc 0
810 22:28:38.596392 Card did not respond to voltage select! : -110
811 22:28:38.601934 ** Bad device specification mmc 0 **
812 22:28:38.602511 Couldn't find partition mmc 0
813 22:28:38.606129 Error: could not access storage.
814 22:28:38.948450 Net: eth0: ethernet@ff3f0000
815 22:28:38.949098 starting USB...
816 22:28:39.201359 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 22:28:39.202004 Starting the controller
818 22:28:39.208170 USB XHCI 1.10
819 22:28:41.369809 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 22:28:41.370226 bl2_stage_init 0x01
821 22:28:41.370454 bl2_stage_init 0x81
822 22:28:41.375336 hw id: 0x0000 - pwm id 0x01
823 22:28:41.375646 bl2_stage_init 0xc1
824 22:28:41.375867 bl2_stage_init 0x02
825 22:28:41.376121
826 22:28:41.381049 L0:00000000
827 22:28:41.381366 L1:20000703
828 22:28:41.381602 L2:00008067
829 22:28:41.381830 L3:14000000
830 22:28:41.386762 B2:00402000
831 22:28:41.387061 B1:e0f83180
832 22:28:41.387294
833 22:28:41.387514 TE: 58124
834 22:28:41.387736
835 22:28:41.392168 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 22:28:41.392674
837 22:28:41.392949 Board ID = 1
838 22:28:41.397705 Set A53 clk to 24M
839 22:28:41.398192 Set A73 clk to 24M
840 22:28:41.398446 Set clk81 to 24M
841 22:28:41.403217 A53 clk: 1200 MHz
842 22:28:41.403655 A73 clk: 1200 MHz
843 22:28:41.404022 CLK81: 166.6M
844 22:28:41.404279 smccc: 00012a92
845 22:28:41.408917 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 22:28:41.414565 board id: 1
847 22:28:41.419864 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 22:28:41.431033 fw parse done
849 22:28:41.436172 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 22:28:41.478769 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 22:28:41.490525 PIEI prepare done
852 22:28:41.490888 fastboot data load
853 22:28:41.491167 fastboot data verify
854 22:28:41.496174 verify result: 266
855 22:28:41.501682 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 22:28:41.502040 LPDDR4 probe
857 22:28:41.502315 ddr clk to 1584MHz
858 22:28:41.509657 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 22:28:41.546012
860 22:28:41.546439 dmc_version 0001
861 22:28:41.553254 Check phy result
862 22:28:41.559505 INFO : End of CA training
863 22:28:41.559887 INFO : End of initialization
864 22:28:41.565163 INFO : Training has run successfully!
865 22:28:41.566001 Check phy result
866 22:28:41.570785 INFO : End of initialization
867 22:28:41.571281 INFO : End of read enable training
868 22:28:41.573933 INFO : End of fine write leveling
869 22:28:41.579507 INFO : End of Write leveling coarse delay
870 22:28:41.585075 INFO : Training has run successfully!
871 22:28:41.585442 Check phy result
872 22:28:41.585720 INFO : End of initialization
873 22:28:41.590730 INFO : End of read dq deskew training
874 22:28:41.596313 INFO : End of MPR read delay center optimization
875 22:28:41.597211 INFO : End of write delay center optimization
876 22:28:41.601935 INFO : End of read delay center optimization
877 22:28:41.607615 INFO : End of max read latency training
878 22:28:41.608233 INFO : Training has run successfully!
879 22:28:41.613155 1D training succeed
880 22:28:41.618879 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 22:28:41.666196 Check phy result
882 22:28:41.666650 INFO : End of initialization
883 22:28:41.688806 INFO : End of 2D read delay Voltage center optimization
884 22:28:41.708918 INFO : End of 2D read delay Voltage center optimization
885 22:28:41.761128 INFO : End of 2D write delay Voltage center optimization
886 22:28:41.811126 INFO : End of 2D write delay Voltage center optimization
887 22:28:41.816582 INFO : Training has run successfully!
888 22:28:41.817009
889 22:28:41.817363 channel==0
890 22:28:41.822147 RxClkDly_Margin_A0==88 ps 9
891 22:28:41.822557 TxDqDly_Margin_A0==98 ps 10
892 22:28:41.825384 RxClkDly_Margin_A1==88 ps 9
893 22:28:41.825763 TxDqDly_Margin_A1==88 ps 9
894 22:28:41.831011 TrainedVREFDQ_A0==74
895 22:28:41.831413 TrainedVREFDQ_A1==74
896 22:28:41.831778 VrefDac_Margin_A0==25
897 22:28:41.836722 DeviceVref_Margin_A0==40
898 22:28:41.837222 VrefDac_Margin_A1==24
899 22:28:41.842166 DeviceVref_Margin_A1==40
900 22:28:41.842568
901 22:28:41.842914
902 22:28:41.843232 channel==1
903 22:28:41.843578 RxClkDly_Margin_A0==98 ps 10
904 22:28:41.847805 TxDqDly_Margin_A0==98 ps 10
905 22:28:41.848210 RxClkDly_Margin_A1==88 ps 9
906 22:28:41.853355 TxDqDly_Margin_A1==88 ps 9
907 22:28:41.853784 TrainedVREFDQ_A0==77
908 22:28:41.854129 TrainedVREFDQ_A1==77
909 22:28:41.858966 VrefDac_Margin_A0==23
910 22:28:41.859349 DeviceVref_Margin_A0==37
911 22:28:41.864748 VrefDac_Margin_A1==24
912 22:28:41.865135 DeviceVref_Margin_A1==37
913 22:28:41.865482
914 22:28:41.870142 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 22:28:41.870529
916 22:28:41.898052 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
917 22:28:41.903740 2D training succeed
918 22:28:41.909315 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 22:28:41.909630 auto size-- 65535DDR cs0 size: 2048MB
920 22:28:41.914926 DDR cs1 size: 2048MB
921 22:28:41.915228 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 22:28:41.920602 cs0 DataBus test pass
923 22:28:41.920907 cs1 DataBus test pass
924 22:28:41.921122 cs0 AddrBus test pass
925 22:28:41.926115 cs1 AddrBus test pass
926 22:28:41.926422
927 22:28:41.926638 100bdlr_step_size ps== 420
928 22:28:41.926849 result report
929 22:28:41.931725 boot times 0Enable ddr reg access
930 22:28:41.939372 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 22:28:41.952773 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 22:28:42.525908 0.0;M3 CHK:0;cm4_sp_mode 0
933 22:28:42.526330 MVN_1=0x00000000
934 22:28:42.531422 MVN_2=0x00000000
935 22:28:42.537170 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 22:28:42.537482 OPS=0x10
937 22:28:42.537695 ring efuse init
938 22:28:42.537898 chipver efuse init
939 22:28:42.542751 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 22:28:42.548419 [0.018961 Inits done]
941 22:28:42.548731 secure task start!
942 22:28:42.548945 high task start!
943 22:28:42.552745 low task start!
944 22:28:42.553316 run into bl31
945 22:28:42.559646 NOTICE: BL31: v1.3(release):4fc40b1
946 22:28:42.567353 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 22:28:42.567717 NOTICE: BL31: G12A normal boot!
948 22:28:42.592783 NOTICE: BL31: BL33 decompress pass
949 22:28:42.598110 ERROR: Error initializing runtime service opteed_fast
950 22:28:43.831288
951 22:28:43.831691
952 22:28:43.838991 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 22:28:43.839292
954 22:28:43.839511 Model: Libre Computer AML-A311D-CC Alta
955 22:28:44.048210 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 22:28:44.070830 DRAM: 2 GiB (effective 3.8 GiB)
957 22:28:44.214629 Core: 408 devices, 31 uclasses, devicetree: separate
958 22:28:44.220416 WDT: Not starting watchdog@f0d0
959 22:28:44.252720 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 22:28:44.265164 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 22:28:44.270117 ** Bad device specification mmc 0 **
962 22:28:44.280486 Card did not respond to voltage select! : -110
963 22:28:44.288164 ** Bad device specification mmc 0 **
964 22:28:44.288464 Couldn't find partition mmc 0
965 22:28:44.296467 Card did not respond to voltage select! : -110
966 22:28:44.301971 ** Bad device specification mmc 0 **
967 22:28:44.302272 Couldn't find partition mmc 0
968 22:28:44.307005 Error: could not access storage.
969 22:28:44.649524 Net: eth0: ethernet@ff3f0000
970 22:28:44.649921 starting USB...
971 22:28:44.901292 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 22:28:44.901692 Starting the controller
973 22:28:44.908343 USB XHCI 1.10
974 22:28:46.769602 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 22:28:46.770220 bl2_stage_init 0x01
976 22:28:46.770661 bl2_stage_init 0x81
977 22:28:46.775268 hw id: 0x0000 - pwm id 0x01
978 22:28:46.775766 bl2_stage_init 0xc1
979 22:28:46.776240 bl2_stage_init 0x02
980 22:28:46.776658
981 22:28:46.780711 L0:00000000
982 22:28:46.781190 L1:20000703
983 22:28:46.781607 L2:00008067
984 22:28:46.782014 L3:14000000
985 22:28:46.786318 B2:00402000
986 22:28:46.786790 B1:e0f83180
987 22:28:46.787202
988 22:28:46.787612 TE: 58167
989 22:28:46.788049
990 22:28:46.791897 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 22:28:46.792396
992 22:28:46.792818 Board ID = 1
993 22:28:46.797577 Set A53 clk to 24M
994 22:28:46.798136 Set A73 clk to 24M
995 22:28:46.798555 Set clk81 to 24M
996 22:28:46.803252 A53 clk: 1200 MHz
997 22:28:46.803733 A73 clk: 1200 MHz
998 22:28:46.804229 CLK81: 166.6M
999 22:28:46.804686 smccc: 00012abd
1000 22:28:46.808772 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 22:28:46.814396 board id: 1
1002 22:28:46.820368 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 22:28:46.830943 fw parse done
1004 22:28:46.836925 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 22:28:46.879542 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 22:28:46.890448 PIEI prepare done
1007 22:28:46.891095 fastboot data load
1008 22:28:46.891658 fastboot data verify
1009 22:28:46.896278 verify result: 266
1010 22:28:46.901833 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 22:28:46.902426 LPDDR4 probe
1012 22:28:46.902946 ddr clk to 1584MHz
1013 22:28:46.909703 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 22:28:46.946954
1015 22:28:46.947591 dmc_version 0001
1016 22:28:46.953733 Check phy result
1017 22:28:46.959518 INFO : End of CA training
1018 22:28:46.960098 INFO : End of initialization
1019 22:28:46.965230 INFO : Training has run successfully!
1020 22:28:46.965858 Check phy result
1021 22:28:46.970693 INFO : End of initialization
1022 22:28:46.971268 INFO : End of read enable training
1023 22:28:46.974077 INFO : End of fine write leveling
1024 22:28:46.979648 INFO : End of Write leveling coarse delay
1025 22:28:46.985207 INFO : Training has run successfully!
1026 22:28:46.985771 Check phy result
1027 22:28:46.986309 INFO : End of initialization
1028 22:28:46.990772 INFO : End of read dq deskew training
1029 22:28:46.996292 INFO : End of MPR read delay center optimization
1030 22:28:46.996873 INFO : End of write delay center optimization
1031 22:28:47.001840 INFO : End of read delay center optimization
1032 22:28:47.007441 INFO : End of max read latency training
1033 22:28:47.008014 INFO : Training has run successfully!
1034 22:28:47.013093 1D training succeed
1035 22:28:47.018954 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 22:28:47.066671 Check phy result
1037 22:28:47.067225 INFO : End of initialization
1038 22:28:47.088266 INFO : End of 2D read delay Voltage center optimization
1039 22:28:47.108498 INFO : End of 2D read delay Voltage center optimization
1040 22:28:47.160532 INFO : End of 2D write delay Voltage center optimization
1041 22:28:47.209854 INFO : End of 2D write delay Voltage center optimization
1042 22:28:47.215479 INFO : Training has run successfully!
1043 22:28:47.216044
1044 22:28:47.216534 channel==0
1045 22:28:47.221108 RxClkDly_Margin_A0==88 ps 9
1046 22:28:47.221617 TxDqDly_Margin_A0==98 ps 10
1047 22:28:47.226630 RxClkDly_Margin_A1==88 ps 9
1048 22:28:47.227144 TxDqDly_Margin_A1==88 ps 9
1049 22:28:47.227614 TrainedVREFDQ_A0==74
1050 22:28:47.232323 TrainedVREFDQ_A1==74
1051 22:28:47.232826 VrefDac_Margin_A0==25
1052 22:28:47.233285 DeviceVref_Margin_A0==40
1053 22:28:47.237884 VrefDac_Margin_A1==25
1054 22:28:47.238422 DeviceVref_Margin_A1==40
1055 22:28:47.238887
1056 22:28:47.239337
1057 22:28:47.239785 channel==1
1058 22:28:47.243475 RxClkDly_Margin_A0==98 ps 10
1059 22:28:47.244010 TxDqDly_Margin_A0==98 ps 10
1060 22:28:47.249060 RxClkDly_Margin_A1==88 ps 9
1061 22:28:47.249560 TxDqDly_Margin_A1==88 ps 9
1062 22:28:47.254654 TrainedVREFDQ_A0==77
1063 22:28:47.255166 TrainedVREFDQ_A1==77
1064 22:28:47.255629 VrefDac_Margin_A0==22
1065 22:28:47.260362 DeviceVref_Margin_A0==37
1066 22:28:47.260862 VrefDac_Margin_A1==24
1067 22:28:47.265880 DeviceVref_Margin_A1==37
1068 22:28:47.266376
1069 22:28:47.266838 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 22:28:47.267289
1071 22:28:47.299411 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 22:28:47.299951 2D training succeed
1073 22:28:47.305106 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 22:28:47.310622 auto size-- 65535DDR cs0 size: 2048MB
1075 22:28:47.311121 DDR cs1 size: 2048MB
1076 22:28:47.316345 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 22:28:47.316841 cs0 DataBus test pass
1078 22:28:47.321834 cs1 DataBus test pass
1079 22:28:47.322334 cs0 AddrBus test pass
1080 22:28:47.322790 cs1 AddrBus test pass
1081 22:28:47.323240
1082 22:28:47.327417 100bdlr_step_size ps== 420
1083 22:28:47.327931 result report
1084 22:28:47.333117 boot times 0Enable ddr reg access
1085 22:28:47.338049 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 22:28:47.350875 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 22:28:47.925608 0.0;M3 CHK:0;cm4_sp_mode 0
1088 22:28:47.926276 MVN_1=0x00000000
1089 22:28:47.931003 MVN_2=0x00000000
1090 22:28:47.936765 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 22:28:47.937267 OPS=0x10
1092 22:28:47.937731 ring efuse init
1093 22:28:47.938189 chipver efuse init
1094 22:28:47.942447 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 22:28:47.947967 [0.018961 Inits done]
1096 22:28:47.948519 secure task start!
1097 22:28:47.948983 high task start!
1098 22:28:47.952545 low task start!
1099 22:28:47.953040 run into bl31
1100 22:28:47.959169 NOTICE: BL31: v1.3(release):4fc40b1
1101 22:28:47.967005 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 22:28:47.967508 NOTICE: BL31: G12A normal boot!
1103 22:28:47.992310 NOTICE: BL31: BL33 decompress pass
1104 22:28:47.997973 ERROR: Error initializing runtime service opteed_fast
1105 22:28:49.230917
1106 22:28:49.231539
1107 22:28:49.239298 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 22:28:49.239811
1109 22:28:49.240357 Model: Libre Computer AML-A311D-CC Alta
1110 22:28:49.447821 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 22:28:49.471077 DRAM: 2 GiB (effective 3.8 GiB)
1112 22:28:49.614088 Core: 408 devices, 31 uclasses, devicetree: separate
1113 22:28:49.619953 WDT: Not starting watchdog@f0d0
1114 22:28:49.652217 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 22:28:49.664640 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 22:28:49.669596 ** Bad device specification mmc 0 **
1117 22:28:49.679896 Card did not respond to voltage select! : -110
1118 22:28:49.687531 ** Bad device specification mmc 0 **
1119 22:28:49.688072 Couldn't find partition mmc 0
1120 22:28:49.695874 Card did not respond to voltage select! : -110
1121 22:28:49.701444 ** Bad device specification mmc 0 **
1122 22:28:49.701957 Couldn't find partition mmc 0
1123 22:28:49.706513 Error: could not access storage.
1124 22:28:50.048981 Net: eth0: ethernet@ff3f0000
1125 22:28:50.049640 starting USB...
1126 22:28:50.300794 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 22:28:50.301389 Starting the controller
1128 22:28:50.307795 USB XHCI 1.10
1129 22:28:51.862034 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 22:28:51.870267 scanning usb for storage devices... 0 Storage Device(s) found
1132 22:28:51.922018 Hit any key to stop autoboot: 1
1133 22:28:51.922771 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1134 22:28:51.923090 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1135 22:28:51.923337 Setting prompt string to ['=>']
1136 22:28:51.923584 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1137 22:28:51.937681 0
1138 22:28:51.938616 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 22:28:51.939145 Sending with 10 millisecond of delay
1141 22:28:53.074202 => setenv autoload no
1142 22:28:53.085004 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1143 22:28:53.089923 setenv autoload no
1144 22:28:53.090693 Sending with 10 millisecond of delay
1146 22:28:54.887688 => setenv initrd_high 0xffffffff
1147 22:28:54.898491 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1148 22:28:54.899107 setenv initrd_high 0xffffffff
1149 22:28:54.899627 Sending with 10 millisecond of delay
1151 22:28:56.517012 => setenv fdt_high 0xffffffff
1152 22:28:56.528077 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1153 22:28:56.528965 setenv fdt_high 0xffffffff
1154 22:28:56.529712 Sending with 10 millisecond of delay
1156 22:28:56.821895 => dhcp
1157 22:28:56.832967 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1158 22:28:56.834112 dhcp
1159 22:28:56.834694 Speed: 1000, full duplex
1160 22:28:56.835238 BOOTP broadcast 1
1161 22:28:56.841543 DHCP client bound to address 192.168.6.27 (9 ms)
1162 22:28:56.842592 Sending with 10 millisecond of delay
1164 22:28:58.521051 => setenv serverip 192.168.6.2
1165 22:28:58.533883 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1166 22:28:58.534931 setenv serverip 192.168.6.2
1167 22:28:58.535700 Sending with 10 millisecond of delay
1169 22:29:02.262363 => tftpboot 0x01080000 955488/tftp-deploy-1z9t64go/kernel/uImage
1170 22:29:02.273282 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 22:29:02.274303 tftpboot 0x01080000 955488/tftp-deploy-1z9t64go/kernel/uImage
1172 22:29:02.274796 Speed: 1000, full duplex
1173 22:29:02.275261 Using ethernet@ff3f0000 device
1174 22:29:02.276038 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 22:29:02.281394 Filename '955488/tftp-deploy-1z9t64go/kernel/uImage'.
1176 22:29:02.285305 Load address: 0x1080000
1177 22:29:05.198416 Loading: *################################################## 43.6 MiB
1178 22:29:05.199057 14.9 MiB/s
1179 22:29:05.199517 done
1180 22:29:05.202969 Bytes transferred = 45713984 (2b98a40 hex)
1181 22:29:05.203742 Sending with 10 millisecond of delay
1183 22:29:09.900815 => tftpboot 0x08000000 955488/tftp-deploy-1z9t64go/ramdisk/ramdisk.cpio.gz.uboot
1184 22:29:09.911626 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1185 22:29:09.912520 tftpboot 0x08000000 955488/tftp-deploy-1z9t64go/ramdisk/ramdisk.cpio.gz.uboot
1186 22:29:09.913000 Speed: 1000, full duplex
1187 22:29:09.913448 Using ethernet@ff3f0000 device
1188 22:29:09.914365 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 22:29:09.925228 Filename '955488/tftp-deploy-1z9t64go/ramdisk/ramdisk.cpio.gz.uboot'.
1190 22:29:09.925765 Load address: 0x8000000
1191 22:29:11.402351 Loading: *################################################# UDP wrong checksum 00000005 0000bd14
1192 22:29:16.402945 T UDP wrong checksum 00000005 0000bd14
1193 22:29:20.954513 UDP wrong checksum 000000ff 000053e0
1194 22:29:20.966501 UDP wrong checksum 000000ff 0000e9d2
1195 22:29:26.406098 T T UDP wrong checksum 00000005 0000bd14
1196 22:29:46.409937 T T T T UDP wrong checksum 00000005 0000bd14
1197 22:30:06.415033 T T T
1198 22:30:06.415714 Retry count exceeded; starting again
1200 22:30:06.417273 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1203 22:30:06.419267 end: 2.4 uboot-commands (duration 00:01:52) [common]
1205 22:30:06.420846 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1207 22:30:06.421917 end: 2 uboot-action (duration 00:01:52) [common]
1209 22:30:06.423533 Cleaning after the job
1210 22:30:06.424126 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/ramdisk
1211 22:30:06.426399 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/kernel
1212 22:30:06.474027 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/dtb
1213 22:30:06.474820 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/nfsrootfs
1214 22:30:06.515436 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955488/tftp-deploy-1z9t64go/modules
1215 22:30:06.518931 start: 4.1 power-off (timeout 00:00:30) [common]
1216 22:30:06.519455 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1217 22:30:06.550148 >> OK - accepted request
1218 22:30:06.552283 Returned 0 in 0 seconds
1219 22:30:06.653583 end: 4.1 power-off (duration 00:00:00) [common]
1221 22:30:06.654621 start: 4.2 read-feedback (timeout 00:10:00) [common]
1222 22:30:06.655524 Listened to connection for namespace 'common' for up to 1s
1223 22:30:07.655669 Finalising connection for namespace 'common'
1224 22:30:07.656540 Disconnecting from shell: Finalise
1225 22:30:07.657128 =>
1226 22:30:07.758224 end: 4.2 read-feedback (duration 00:00:01) [common]
1227 22:30:07.758953 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/955488
1228 22:30:10.549535 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/955488
1229 22:30:10.550206 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.