Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 00:47:22.456667 lava-dispatcher, installed at version: 2024.01
2 00:47:22.457449 start: 0 validate
3 00:47:22.457953 Start time: 2024-11-08 00:47:22.457922+00:00 (UTC)
4 00:47:22.458511 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 00:47:22.459046 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 00:47:22.491617 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 00:47:22.492178 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-244-g80b3d72150d5%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 00:47:22.514957 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 00:47:22.515543 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-244-g80b3d72150d5%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 00:47:22.537599 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 00:47:22.538263 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 00:47:22.563357 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 00:47:22.563849 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-244-g80b3d72150d5%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 00:47:22.597025 validate duration: 0.14
16 00:47:22.597973 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:47:22.598316 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:47:22.598618 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:47:22.599225 Not decompressing ramdisk as can be used compressed.
20 00:47:22.599688 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 00:47:22.599981 saving as /var/lib/lava/dispatcher/tmp/956692/tftp-deploy-qg4u5umr/ramdisk/initrd.cpio.gz
22 00:47:22.600257 total size: 4775763 (4 MB)
23 00:47:22.631424 progress 0 % (0 MB)
24 00:47:22.635185 progress 5 % (0 MB)
25 00:47:22.638707 progress 10 % (0 MB)
26 00:47:22.642079 progress 15 % (0 MB)
27 00:47:22.645904 progress 20 % (0 MB)
28 00:47:22.649171 progress 25 % (1 MB)
29 00:47:22.652497 progress 30 % (1 MB)
30 00:47:22.656217 progress 35 % (1 MB)
31 00:47:22.659535 progress 40 % (1 MB)
32 00:47:22.662792 progress 45 % (2 MB)
33 00:47:22.666086 progress 50 % (2 MB)
34 00:47:22.669787 progress 55 % (2 MB)
35 00:47:22.673164 progress 60 % (2 MB)
36 00:47:22.676456 progress 65 % (2 MB)
37 00:47:22.680255 progress 70 % (3 MB)
38 00:47:22.683548 progress 75 % (3 MB)
39 00:47:22.686844 progress 80 % (3 MB)
40 00:47:22.690192 progress 85 % (3 MB)
41 00:47:22.694006 progress 90 % (4 MB)
42 00:47:22.697130 progress 95 % (4 MB)
43 00:47:22.700208 progress 100 % (4 MB)
44 00:47:22.700845 4 MB downloaded in 0.10 s (45.29 MB/s)
45 00:47:22.701407 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:47:22.702362 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:47:22.702665 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:47:22.702938 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:47:22.703409 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 00:47:22.703670 saving as /var/lib/lava/dispatcher/tmp/956692/tftp-deploy-qg4u5umr/kernel/zImage
52 00:47:22.703891 total size: 11440640 (10 MB)
53 00:47:22.704102 No compression specified
54 00:47:22.738999 progress 0 % (0 MB)
55 00:47:22.748903 progress 5 % (0 MB)
56 00:47:22.759492 progress 10 % (1 MB)
57 00:47:22.769579 progress 15 % (1 MB)
58 00:47:22.779148 progress 20 % (2 MB)
59 00:47:22.789441 progress 25 % (2 MB)
60 00:47:22.797033 progress 30 % (3 MB)
61 00:47:22.804945 progress 35 % (3 MB)
62 00:47:22.813615 progress 40 % (4 MB)
63 00:47:22.821961 progress 45 % (4 MB)
64 00:47:22.829601 progress 50 % (5 MB)
65 00:47:22.838084 progress 55 % (6 MB)
66 00:47:22.847147 progress 60 % (6 MB)
67 00:47:22.854383 progress 65 % (7 MB)
68 00:47:22.861976 progress 70 % (7 MB)
69 00:47:22.869077 progress 75 % (8 MB)
70 00:47:22.876770 progress 80 % (8 MB)
71 00:47:22.883898 progress 85 % (9 MB)
72 00:47:22.891633 progress 90 % (9 MB)
73 00:47:22.898762 progress 95 % (10 MB)
74 00:47:22.905853 progress 100 % (10 MB)
75 00:47:22.906386 10 MB downloaded in 0.20 s (53.88 MB/s)
76 00:47:22.906873 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:47:22.907694 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:47:22.907974 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:47:22.908239 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:47:22.908721 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 00:47:22.908979 saving as /var/lib/lava/dispatcher/tmp/956692/tftp-deploy-qg4u5umr/dtb/am335x-boneblack.dtb
83 00:47:22.909185 total size: 70568 (0 MB)
84 00:47:22.909392 No compression specified
85 00:47:22.940981 progress 46 % (0 MB)
86 00:47:22.941903 progress 92 % (0 MB)
87 00:47:22.942639 progress 100 % (0 MB)
88 00:47:22.943049 0 MB downloaded in 0.03 s (1.99 MB/s)
89 00:47:22.943522 end: 1.3.1 http-download (duration 00:00:00) [common]
91 00:47:22.944359 end: 1.3 download-retry (duration 00:00:00) [common]
92 00:47:22.944637 start: 1.4 download-retry (timeout 00:10:00) [common]
93 00:47:22.944909 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 00:47:22.945481 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 00:47:22.945771 saving as /var/lib/lava/dispatcher/tmp/956692/tftp-deploy-qg4u5umr/nfsrootfs/full.rootfs.tar
96 00:47:22.946016 total size: 117747780 (112 MB)
97 00:47:22.946234 Using unxz to decompress xz
98 00:47:22.979303 progress 0 % (0 MB)
99 00:47:23.715273 progress 5 % (5 MB)
100 00:47:24.470647 progress 10 % (11 MB)
101 00:47:25.254829 progress 15 % (16 MB)
102 00:47:25.975468 progress 20 % (22 MB)
103 00:47:26.576129 progress 25 % (28 MB)
104 00:47:28.061038 progress 30 % (33 MB)
105 00:47:28.934845 progress 35 % (39 MB)
106 00:47:29.280064 progress 40 % (44 MB)
107 00:47:29.649941 progress 45 % (50 MB)
108 00:47:30.314083 progress 50 % (56 MB)
109 00:47:31.115008 progress 55 % (61 MB)
110 00:47:31.837996 progress 60 % (67 MB)
111 00:47:32.560698 progress 65 % (73 MB)
112 00:47:33.313701 progress 70 % (78 MB)
113 00:47:34.069374 progress 75 % (84 MB)
114 00:47:34.816358 progress 80 % (89 MB)
115 00:47:35.544064 progress 85 % (95 MB)
116 00:47:36.340150 progress 90 % (101 MB)
117 00:47:37.102517 progress 95 % (106 MB)
118 00:47:37.933307 progress 100 % (112 MB)
119 00:47:37.946473 112 MB downloaded in 15.00 s (7.49 MB/s)
120 00:47:37.947405 end: 1.4.1 http-download (duration 00:00:15) [common]
122 00:47:37.949161 end: 1.4 download-retry (duration 00:00:15) [common]
123 00:47:37.949724 start: 1.5 download-retry (timeout 00:09:45) [common]
124 00:47:37.950331 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 00:47:37.951221 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 00:47:37.951717 saving as /var/lib/lava/dispatcher/tmp/956692/tftp-deploy-qg4u5umr/modules/modules.tar
127 00:47:37.952165 total size: 6609564 (6 MB)
128 00:47:37.952619 Using unxz to decompress xz
129 00:47:37.991622 progress 0 % (0 MB)
130 00:47:38.027089 progress 5 % (0 MB)
131 00:47:38.070747 progress 10 % (0 MB)
132 00:47:38.114727 progress 15 % (0 MB)
133 00:47:38.158987 progress 20 % (1 MB)
134 00:47:38.206961 progress 25 % (1 MB)
135 00:47:38.250717 progress 30 % (1 MB)
136 00:47:38.293337 progress 35 % (2 MB)
137 00:47:38.336736 progress 40 % (2 MB)
138 00:47:38.387919 progress 45 % (2 MB)
139 00:47:38.434515 progress 50 % (3 MB)
140 00:47:38.480927 progress 55 % (3 MB)
141 00:47:38.532511 progress 60 % (3 MB)
142 00:47:38.574777 progress 65 % (4 MB)
143 00:47:38.618153 progress 70 % (4 MB)
144 00:47:38.663946 progress 75 % (4 MB)
145 00:47:38.706335 progress 80 % (5 MB)
146 00:47:38.748698 progress 85 % (5 MB)
147 00:47:38.795399 progress 90 % (5 MB)
148 00:47:38.840368 progress 95 % (6 MB)
149 00:47:38.885753 progress 100 % (6 MB)
150 00:47:38.899761 6 MB downloaded in 0.95 s (6.65 MB/s)
151 00:47:38.900327 end: 1.5.1 http-download (duration 00:00:01) [common]
153 00:47:38.901149 end: 1.5 download-retry (duration 00:00:01) [common]
154 00:47:38.901418 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 00:47:38.901706 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 00:47:55.313552 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/956692/extract-nfsrootfs-1hrqq9am
157 00:47:55.314160 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 00:47:55.314447 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 00:47:55.315145 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz
160 00:47:55.315599 makedir: /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin
161 00:47:55.315922 makedir: /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/tests
162 00:47:55.316228 makedir: /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/results
163 00:47:55.316559 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-add-keys
164 00:47:55.317104 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-add-sources
165 00:47:55.317626 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-background-process-start
166 00:47:55.318337 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-background-process-stop
167 00:47:55.318881 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-common-functions
168 00:47:55.319378 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-echo-ipv4
169 00:47:55.319867 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-install-packages
170 00:47:55.320344 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-installed-packages
171 00:47:55.320830 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-os-build
172 00:47:55.321349 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-probe-channel
173 00:47:55.321851 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-probe-ip
174 00:47:55.322360 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-target-ip
175 00:47:55.322839 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-target-mac
176 00:47:55.323485 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-target-storage
177 00:47:55.324062 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-test-case
178 00:47:55.324553 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-test-event
179 00:47:55.325043 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-test-feedback
180 00:47:55.325538 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-test-raise
181 00:47:55.326039 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-test-reference
182 00:47:55.326526 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-test-runner
183 00:47:55.327003 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-test-set
184 00:47:55.327534 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-test-shell
185 00:47:55.328049 Updating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-add-keys (debian)
186 00:47:55.328580 Updating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-add-sources (debian)
187 00:47:55.329211 Updating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-install-packages (debian)
188 00:47:55.329774 Updating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-installed-packages (debian)
189 00:47:55.330335 Updating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/bin/lava-os-build (debian)
190 00:47:55.330824 Creating /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/environment
191 00:47:55.331199 LAVA metadata
192 00:47:55.331457 - LAVA_JOB_ID=956692
193 00:47:55.331667 - LAVA_DISPATCHER_IP=192.168.6.3
194 00:47:55.332020 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 00:47:55.332937 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 00:47:55.333242 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 00:47:55.333445 skipped lava-vland-overlay
198 00:47:55.333682 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 00:47:55.333957 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 00:47:55.334158 skipped lava-multinode-overlay
201 00:47:55.334391 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 00:47:55.334740 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 00:47:55.335035 Loading test definitions
204 00:47:55.335312 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 00:47:55.335547 Using /lava-956692 at stage 0
206 00:47:55.336622 uuid=956692_1.6.2.4.1 testdef=None
207 00:47:55.336919 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 00:47:55.337179 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 00:47:55.338736 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 00:47:55.339514 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 00:47:55.341576 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 00:47:55.342408 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 00:47:55.344181 runner path: /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/0/tests/0_timesync-off test_uuid 956692_1.6.2.4.1
216 00:47:55.344730 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 00:47:55.345540 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 00:47:55.345878 Using /lava-956692 at stage 0
220 00:47:55.346272 Fetching tests from https://github.com/kernelci/test-definitions.git
221 00:47:55.346563 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/0/tests/1_kselftest-dt'
222 00:47:59.127863 Running '/usr/bin/git checkout kernelci.org
223 00:47:59.293478 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 00:47:59.294955 uuid=956692_1.6.2.4.5 testdef=None
225 00:47:59.295295 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 00:47:59.296034 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 00:47:59.298902 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 00:47:59.299715 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 00:47:59.303431 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 00:47:59.304281 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 00:47:59.307858 runner path: /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/0/tests/1_kselftest-dt test_uuid 956692_1.6.2.4.5
235 00:47:59.308159 BOARD='beaglebone-black'
236 00:47:59.308366 BRANCH='broonie-sound'
237 00:47:59.308564 SKIPFILE='/dev/null'
238 00:47:59.308761 SKIP_INSTALL='True'
239 00:47:59.308955 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 00:47:59.309154 TST_CASENAME=''
241 00:47:59.309347 TST_CMDFILES='dt'
242 00:47:59.309900 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 00:47:59.310733 Creating lava-test-runner.conf files
245 00:47:59.310942 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/956692/lava-overlay-fif6qdqz/lava-956692/0 for stage 0
246 00:47:59.311312 - 0_timesync-off
247 00:47:59.311554 - 1_kselftest-dt
248 00:47:59.311887 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 00:47:59.312167 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 00:48:23.547164 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 00:48:23.547622 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
252 00:48:23.547886 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 00:48:23.548156 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 00:48:23.548422 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
255 00:48:23.957105 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 00:48:23.957593 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
257 00:48:23.957880 extracting modules file /var/lib/lava/dispatcher/tmp/956692/tftp-deploy-qg4u5umr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956692/extract-nfsrootfs-1hrqq9am
258 00:48:24.890741 extracting modules file /var/lib/lava/dispatcher/tmp/956692/tftp-deploy-qg4u5umr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956692/extract-overlay-ramdisk-2cb40pb5/ramdisk
259 00:48:25.854990 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 00:48:25.855455 start: 1.6.5 apply-overlay-tftp (timeout 00:08:57) [common]
261 00:48:25.855730 [common] Applying overlay to NFS
262 00:48:25.855943 [common] Applying overlay /var/lib/lava/dispatcher/tmp/956692/compress-overlay-4if8snxh/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/956692/extract-nfsrootfs-1hrqq9am
263 00:48:28.696608 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 00:48:28.697096 start: 1.6.6 prepare-kernel (timeout 00:08:54) [common]
265 00:48:28.697374 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:54) [common]
266 00:48:28.697675 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 00:48:28.697965 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 00:48:28.698241 start: 1.6.7 configure-preseed-file (timeout 00:08:54) [common]
269 00:48:28.698508 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 00:48:28.698782 start: 1.6.8 compress-ramdisk (timeout 00:08:54) [common]
271 00:48:28.699023 Building ramdisk /var/lib/lava/dispatcher/tmp/956692/extract-overlay-ramdisk-2cb40pb5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/956692/extract-overlay-ramdisk-2cb40pb5/ramdisk
272 00:48:29.943016 >> 74896 blocks
273 00:48:34.500267 Adding RAMdisk u-boot header.
274 00:48:34.500741 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/956692/extract-overlay-ramdisk-2cb40pb5/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/956692/extract-overlay-ramdisk-2cb40pb5/ramdisk.cpio.gz.uboot
275 00:48:34.654039 output: Image Name:
276 00:48:34.654703 output: Created: Fri Nov 8 00:48:34 2024
277 00:48:34.655162 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 00:48:34.655607 output: Data Size: 14789553 Bytes = 14442.92 KiB = 14.10 MiB
279 00:48:34.656053 output: Load Address: 00000000
280 00:48:34.656611 output: Entry Point: 00000000
281 00:48:34.657165 output:
282 00:48:34.658222 rename /var/lib/lava/dispatcher/tmp/956692/extract-overlay-ramdisk-2cb40pb5/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/956692/tftp-deploy-qg4u5umr/ramdisk/ramdisk.cpio.gz.uboot
283 00:48:34.658995 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 00:48:34.659592 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 00:48:34.660172 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
286 00:48:34.660672 No LXC device requested
287 00:48:34.661222 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 00:48:34.661780 start: 1.8 deploy-device-env (timeout 00:08:48) [common]
289 00:48:34.662538 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 00:48:34.663029 Checking files for TFTP limit of 4294967296 bytes.
291 00:48:34.666003 end: 1 tftp-deploy (duration 00:01:12) [common]
292 00:48:34.666634 start: 2 uboot-action (timeout 00:05:00) [common]
293 00:48:34.667212 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 00:48:34.667755 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 00:48:34.668302 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 00:48:34.669125 substitutions:
297 00:48:34.669589 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 00:48:34.670072 - {DTB_ADDR}: 0x88000000
299 00:48:34.670514 - {DTB}: 956692/tftp-deploy-qg4u5umr/dtb/am335x-boneblack.dtb
300 00:48:34.670950 - {INITRD}: 956692/tftp-deploy-qg4u5umr/ramdisk/ramdisk.cpio.gz.uboot
301 00:48:34.671384 - {KERNEL_ADDR}: 0x82000000
302 00:48:34.671814 - {KERNEL}: 956692/tftp-deploy-qg4u5umr/kernel/zImage
303 00:48:34.672244 - {LAVA_MAC}: None
304 00:48:34.672715 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/956692/extract-nfsrootfs-1hrqq9am
305 00:48:34.673157 - {NFS_SERVER_IP}: 192.168.6.3
306 00:48:34.673588 - {PRESEED_CONFIG}: None
307 00:48:34.674046 - {PRESEED_LOCAL}: None
308 00:48:34.674482 - {RAMDISK_ADDR}: 0x83000000
309 00:48:34.674909 - {RAMDISK}: 956692/tftp-deploy-qg4u5umr/ramdisk/ramdisk.cpio.gz.uboot
310 00:48:34.675341 - {ROOT_PART}: None
311 00:48:34.675767 - {ROOT}: None
312 00:48:34.676193 - {SERVER_IP}: 192.168.6.3
313 00:48:34.676618 - {TEE_ADDR}: 0x83000000
314 00:48:34.677040 - {TEE}: None
315 00:48:34.677463 Parsed boot commands:
316 00:48:34.677893 - setenv autoload no
317 00:48:34.678324 - setenv initrd_high 0xffffffff
318 00:48:34.678920 - setenv fdt_high 0xffffffff
319 00:48:34.679366 - dhcp
320 00:48:34.679790 - setenv serverip 192.168.6.3
321 00:48:34.680211 - tftp 0x82000000 956692/tftp-deploy-qg4u5umr/kernel/zImage
322 00:48:34.680638 - tftp 0x83000000 956692/tftp-deploy-qg4u5umr/ramdisk/ramdisk.cpio.gz.uboot
323 00:48:34.681063 - setenv initrd_size ${filesize}
324 00:48:34.681482 - tftp 0x88000000 956692/tftp-deploy-qg4u5umr/dtb/am335x-boneblack.dtb
325 00:48:34.681940 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/956692/extract-nfsrootfs-1hrqq9am,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 00:48:34.682384 - bootz 0x82000000 0x83000000 0x88000000
327 00:48:34.682932 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 00:48:34.684707 start: 2.3 connect-device (timeout 00:05:00) [common]
330 00:48:34.685186 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 00:48:34.700199 Setting prompt string to ['lava-test: # ']
332 00:48:34.701762 end: 2.3 connect-device (duration 00:00:00) [common]
333 00:48:34.702465 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 00:48:34.703075 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 00:48:34.703665 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 00:48:34.704978 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 00:48:34.759385 >> OK - accepted request
338 00:48:34.761259 Returned 0 in 0 seconds
339 00:48:34.862509 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 00:48:34.864298 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 00:48:34.864931 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 00:48:34.865495 Setting prompt string to ['Hit any key to stop autoboot']
344 00:48:34.866068 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 00:48:34.867803 Trying 192.168.56.22...
346 00:48:34.868360 Connected to conserv3.
347 00:48:34.868824 Escape character is '^]'.
348 00:48:34.869281
349 00:48:34.869740 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 00:48:34.870227
351 00:48:43.238297
352 00:48:43.245268 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 00:48:43.245783 Trying to boot from MMC1
354 00:48:47.291640
355 00:48:47.297497 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 00:48:47.297946 Trying to boot from MMC1
357 00:48:49.980270
358 00:48:49.986235 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 00:48:49.987275 Trying to boot from MMC1
360 00:48:50.574079
361 00:48:50.574730
362 00:48:50.579512 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 00:48:50.580033
364 00:48:50.580512 CPU : AM335X-GP rev 2.0
365 00:48:50.583692 Model: TI AM335x BeagleBone Black
366 00:48:50.584191 DRAM: 512 MiB
367 00:48:50.664809 Core: 160 devices, 18 uclasses, devicetree: separate
368 00:48:50.677788 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 00:48:51.079508 NAND: 0 MiB
370 00:48:51.089736 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 00:48:51.216419 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 00:48:51.237851 <ethaddr> not set. Validating first E-fuse MAC
373 00:48:51.268139 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 00:48:51.327459 Hit any key to stop autoboot: 2
376 00:48:51.328768 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
377 00:48:51.329537 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
378 00:48:51.330220 Setting prompt string to ['=>']
379 00:48:51.330851 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
380 00:48:51.337744 0
381 00:48:51.339138 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 00:48:51.339812 Sending with 10 millisecond of delay
384 00:48:52.475755 => setenv autoload no
385 00:48:52.486646 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
386 00:48:52.492141 setenv autoload no
387 00:48:52.492939 Sending with 10 millisecond of delay
389 00:48:54.291075 => setenv initrd_high 0xffffffff
390 00:48:54.301834 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
391 00:48:54.302398 setenv initrd_high 0xffffffff
392 00:48:54.302891 Sending with 10 millisecond of delay
394 00:48:55.919654 => setenv fdt_high 0xffffffff
395 00:48:55.930368 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
396 00:48:55.931065 setenv fdt_high 0xffffffff
397 00:48:55.931652 Sending with 10 millisecond of delay
399 00:48:56.223482 => dhcp
400 00:48:56.234204 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
401 00:48:56.234999 dhcp
402 00:48:56.235359 link up on port 0, speed 100, full duplex
403 00:48:56.235687 BOOTP broadcast 1
404 00:48:56.488943 BOOTP broadcast 2
405 00:48:56.565173 DHCP client bound to address 192.168.6.8 (325 ms)
406 00:48:56.565927 Sending with 10 millisecond of delay
408 00:48:58.243608 => setenv serverip 192.168.6.3
409 00:48:58.254286 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
410 00:48:58.254982 setenv serverip 192.168.6.3
411 00:48:58.255538 Sending with 10 millisecond of delay
413 00:49:01.743093 => tftp 0x82000000 956692/tftp-deploy-qg4u5umr/kernel/zImage
414 00:49:01.753840 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
415 00:49:01.754419 tftp 0x82000000 956692/tftp-deploy-qg4u5umr/kernel/zImage
416 00:49:01.754672 link up on port 0, speed 100, full duplex
417 00:49:01.758462 Using ethernet@4a100000 device
418 00:49:01.764075 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
419 00:49:01.765017 Filename '956692/tftp-deploy-qg4u5umr/kernel/zImage'.
420 00:49:01.771368 Load address: 0x82000000
421 00:49:03.906392 Loading: *################################################## 10.9 MiB
422 00:49:03.907018 5.1 MiB/s
423 00:49:03.907420 done
424 00:49:03.910505 Bytes transferred = 11440640 (ae9200 hex)
425 00:49:03.911264 Sending with 10 millisecond of delay
427 00:49:08.358864 => tftp 0x83000000 956692/tftp-deploy-qg4u5umr/ramdisk/ramdisk.cpio.gz.uboot
428 00:49:08.369624 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
429 00:49:08.370485 tftp 0x83000000 956692/tftp-deploy-qg4u5umr/ramdisk/ramdisk.cpio.gz.uboot
430 00:49:08.370925 link up on port 0, speed 100, full duplex
431 00:49:08.374750 Using ethernet@4a100000 device
432 00:49:08.380306 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
433 00:49:08.383806 Filename '956692/tftp-deploy-qg4u5umr/ramdisk/ramdisk.cpio.gz.uboot'.
434 00:49:08.388774 Load address: 0x83000000
435 00:49:10.768512 Loading: *################################################## 14.1 MiB
436 00:49:10.769116 5.9 MiB/s
437 00:49:10.769546 done
438 00:49:10.772757 Bytes transferred = 14789617 (e1abf1 hex)
439 00:49:10.773558 Sending with 10 millisecond of delay
441 00:49:12.632640 => setenv initrd_size ${filesize}
442 00:49:12.643497 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
443 00:49:12.644007 setenv initrd_size ${filesize}
444 00:49:12.644471 Sending with 10 millisecond of delay
446 00:49:16.790592 => tftp 0x88000000 956692/tftp-deploy-qg4u5umr/dtb/am335x-boneblack.dtb
447 00:49:16.801407 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
448 00:49:16.802392 tftp 0x88000000 956692/tftp-deploy-qg4u5umr/dtb/am335x-boneblack.dtb
449 00:49:16.802860 link up on port 0, speed 100, full duplex
450 00:49:16.806323 Using ethernet@4a100000 device
451 00:49:16.811874 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
452 00:49:16.819079 Filename '956692/tftp-deploy-qg4u5umr/dtb/am335x-boneblack.dtb'.
453 00:49:16.819634 Load address: 0x88000000
454 00:49:16.831530 Loading: *################################################## 68.9 KiB
455 00:49:16.839614 4.8 MiB/s
456 00:49:16.840130 done
457 00:49:16.840549 Bytes transferred = 70568 (113a8 hex)
458 00:49:16.841239 Sending with 10 millisecond of delay
460 00:49:30.032972 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/956692/extract-nfsrootfs-1hrqq9am,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
461 00:49:30.044041 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
462 00:49:30.045183 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/956692/extract-nfsrootfs-1hrqq9am,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
463 00:49:30.046339 Sending with 10 millisecond of delay
465 00:49:32.387869 => bootz 0x82000000 0x83000000 0x88000000
466 00:49:32.398559 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
467 00:49:32.399026 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
468 00:49:32.399649 bootz 0x82000000 0x83000000 0x88000000
469 00:49:32.399886 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
470 00:49:32.400578 ## Loading init Ramdisk from Legacy Image at 83000000 ...
471 00:49:32.405972 Image Name:
472 00:49:32.406554 Created: 2024-11-08 0:48:34 UTC
473 00:49:32.411386 Image Type: ARM Linux RAMDisk Image (uncompressed)
474 00:49:32.417002 Data Size: 14789553 Bytes = 14.1 MiB
475 00:49:32.417488 Load Address: 00000000
476 00:49:32.423096 Entry Point: 00000000
477 00:49:32.591567 Verifying Checksum ... OK
478 00:49:32.591965 ## Flattened Device Tree blob at 88000000
479 00:49:32.598016 Booting using the fdt blob at 0x88000000
480 00:49:32.598317 Working FDT set to 88000000
481 00:49:32.603575 Using Device Tree in place at 88000000, end 880143a7
482 00:49:32.607966 Working FDT set to 88000000
483 00:49:32.621497
484 00:49:32.621885 Starting kernel ...
485 00:49:32.622140
486 00:49:32.622727 end: 2.4.3 bootloader-commands (duration 00:00:41) [common]
487 00:49:32.623100 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
488 00:49:32.623381 Setting prompt string to ['Linux version [0-9]']
489 00:49:32.623633 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
490 00:49:32.623890 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
491 00:49:33.468075 [ 0.000000] Booting Linux on physical CPU 0x0
492 00:49:33.474031 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
493 00:49:33.474548 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
494 00:49:33.474850 Setting prompt string to []
495 00:49:33.475126 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
496 00:49:33.475376 Using line separator: #'\n'#
497 00:49:33.475593 No login prompt set.
498 00:49:33.475817 Parsing kernel messages
499 00:49:33.476025 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
500 00:49:33.476446 [login-action] Waiting for messages, (timeout 00:04:01)
501 00:49:33.476684 Waiting using forced prompt support (timeout 00:02:01)
502 00:49:33.490808 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j367674-arm-gcc-12-multi-v7-defconfig-bgnmv) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Fri Nov 8 00:29:03 UTC 2024
503 00:49:33.496542 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
504 00:49:33.502269 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
505 00:49:33.513695 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
506 00:49:33.519425 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
507 00:49:33.525273 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
508 00:49:33.525585 [ 0.000000] Memory policy: Data cache writeback
509 00:49:33.531935 [ 0.000000] efi: UEFI not found.
510 00:49:33.540594 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
511 00:49:33.540905 [ 0.000000] Zone ranges:
512 00:49:33.546321 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
513 00:49:33.552053 [ 0.000000] Normal empty
514 00:49:33.557791 [ 0.000000] HighMem empty
515 00:49:33.558104 [ 0.000000] Movable zone start for each node
516 00:49:33.563621 [ 0.000000] Early memory node ranges
517 00:49:33.569364 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
518 00:49:33.577046 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
519 00:49:33.602372 [ 0.000000] CPU: All CPU(s) started in SVC mode.
520 00:49:33.608053 [ 0.000000] AM335X ES2.0 (sgx neon)
521 00:49:33.619668 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
522 00:49:33.637422 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/956692/extract-nfsrootfs-1hrqq9am,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
523 00:49:33.649002 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
524 00:49:33.654636 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
525 00:49:33.660398 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
526 00:49:33.670436 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
527 00:49:33.699494 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
528 00:49:33.705452 <6>[ 0.000000] trace event string verifier disabled
529 00:49:33.705734 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
530 00:49:33.713498 <6>[ 0.000000] rcu: RCU event tracing is enabled.
531 00:49:33.719361 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
532 00:49:33.730668 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
533 00:49:33.735682 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
534 00:49:33.750550 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
535 00:49:33.767642 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
536 00:49:33.774415 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
537 00:49:33.866019 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
538 00:49:33.877483 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
539 00:49:33.884368 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
540 00:49:33.896507 <6>[ 0.019147] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
541 00:49:33.904629 <6>[ 0.033940] Console: colour dummy device 80x30
542 00:49:33.910665 Matched prompt #6: WARNING:
543 00:49:33.910965 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
544 00:49:33.916143 <3>[ 0.038836] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
545 00:49:33.921912 <3>[ 0.045906] This ensures that you still see kernel messages. Please
546 00:49:33.925152 <3>[ 0.052633] update your kernel commandline.
547 00:49:33.965884 <6>[ 0.057248] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
548 00:49:33.971666 <6>[ 0.096158] CPU: Testing write buffer coherency: ok
549 00:49:33.977708 <6>[ 0.101526] CPU0: Spectre v2: using BPIALL workaround
550 00:49:33.978000 <6>[ 0.106993] pid_max: default: 32768 minimum: 301
551 00:49:33.989095 <6>[ 0.112186] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
552 00:49:33.996058 <6>[ 0.120011] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
553 00:49:34.003201 <6>[ 0.129359] CPU0: thread -1, cpu 0, socket -1, mpidr 0
554 00:49:34.011518 <6>[ 0.136340] Setting up static identity map for 0x80300000 - 0x803000ac
555 00:49:34.017285 <6>[ 0.146008] rcu: Hierarchical SRCU implementation.
556 00:49:34.023968 <6>[ 0.151297] rcu: Max phase no-delay instances is 1000.
557 00:49:34.033553 <6>[ 0.162414] EFI services will not be available.
558 00:49:34.039350 <6>[ 0.167694] smp: Bringing up secondary CPUs ...
559 00:49:34.045062 <6>[ 0.172745] smp: Brought up 1 node, 1 CPU
560 00:49:34.050765 <6>[ 0.177146] SMP: Total of 1 processors activated (996.14 BogoMIPS).
561 00:49:34.056682 <6>[ 0.183916] CPU: All CPU(s) started in SVC mode.
562 00:49:34.077107 <6>[ 0.189101] Memory: 406000K/522240K available (16384K kernel code, 2542K rwdata, 6784K rodata, 2048K init, 431K bss, 49048K reserved, 65536K cma-reserved, 0K highmem)
563 00:49:34.077416 <6>[ 0.205379] devtmpfs: initialized
564 00:49:34.099208 <6>[ 0.222436] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
565 00:49:34.110741 <6>[ 0.231019] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
566 00:49:34.116662 <6>[ 0.241473] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
567 00:49:34.128026 <6>[ 0.253862] pinctrl core: initialized pinctrl subsystem
568 00:49:34.136829 <6>[ 0.264486] DMI not present or invalid.
569 00:49:34.145128 <6>[ 0.270342] NET: Registered PF_NETLINK/PF_ROUTE protocol family
570 00:49:34.154510 <6>[ 0.279223] DMA: preallocated 256 KiB pool for atomic coherent allocations
571 00:49:34.169699 <6>[ 0.290778] thermal_sys: Registered thermal governor 'step_wise'
572 00:49:34.170008 <6>[ 0.290945] cpuidle: using governor menu
573 00:49:34.197270 <6>[ 0.326543] No ATAGs?
574 00:49:34.203485 <6>[ 0.329189] hw-breakpoint: debug architecture 0x4 unsupported.
575 00:49:34.213696 <6>[ 0.341255] Serial: AMBA PL011 UART driver
576 00:49:34.246013 <6>[ 0.375249] iommu: Default domain type: Translated
577 00:49:34.255133 <6>[ 0.380600] iommu: DMA domain TLB invalidation policy: strict mode
578 00:49:34.282242 <5>[ 0.410852] SCSI subsystem initialized
579 00:49:34.288079 <6>[ 0.415747] usbcore: registered new interface driver usbfs
580 00:49:34.293867 <6>[ 0.421803] usbcore: registered new interface driver hub
581 00:49:34.300677 <6>[ 0.427584] usbcore: registered new device driver usb
582 00:49:34.306484 <6>[ 0.434095] pps_core: LinuxPPS API ver. 1 registered
583 00:49:34.317951 <6>[ 0.439523] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
584 00:49:34.325133 <6>[ 0.449207] PTP clock support registered
585 00:49:34.325398 <6>[ 0.453667] EDAC MC: Ver: 3.0.0
586 00:49:34.373931 <6>[ 0.500591] scmi_core: SCMI protocol bus registered
587 00:49:34.388971 <6>[ 0.517938] vgaarb: loaded
588 00:49:34.401582 <6>[ 0.530968] clocksource: Switched to clocksource dmtimer
589 00:49:34.438201 <6>[ 0.567124] NET: Registered PF_INET protocol family
590 00:49:34.450727 <6>[ 0.572817] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
591 00:49:34.456509 <6>[ 0.581622] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
592 00:49:34.467969 <6>[ 0.590554] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
593 00:49:34.473771 <6>[ 0.598815] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
594 00:49:34.485338 <6>[ 0.607101] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
595 00:49:34.491216 <6>[ 0.614828] TCP: Hash tables configured (established 4096 bind 4096)
596 00:49:34.496957 <6>[ 0.621731] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
597 00:49:34.502861 <6>[ 0.628772] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
598 00:49:34.510412 <6>[ 0.636378] NET: Registered PF_UNIX/PF_LOCAL protocol family
599 00:49:34.587298 <6>[ 0.710900] RPC: Registered named UNIX socket transport module.
600 00:49:34.587676 <6>[ 0.717337] RPC: Registered udp transport module.
601 00:49:34.593067 <6>[ 0.722470] RPC: Registered tcp transport module.
602 00:49:34.598761 <6>[ 0.727575] RPC: Registered tcp-with-tls transport module.
603 00:49:34.611772 <6>[ 0.733501] RPC: Registered tcp NFSv4.1 backchannel transport module.
604 00:49:34.612056 <6>[ 0.740409] PCI: CLS 0 bytes, default 64
605 00:49:34.618097 <5>[ 0.746197] Initialise system trusted keyrings
606 00:49:34.640012 <6>[ 0.766241] Trying to unpack rootfs image as initramfs...
607 00:49:34.719171 <6>[ 0.842213] workingset: timestamp_bits=30 max_order=17 bucket_order=0
608 00:49:34.723912 <6>[ 0.849726] squashfs: version 4.0 (2009/01/31) Phillip Lougher
609 00:49:34.763159 <5>[ 0.892325] NFS: Registering the id_resolver key type
610 00:49:34.768906 <5>[ 0.897929] Key type id_resolver registered
611 00:49:34.774676 <5>[ 0.902596] Key type id_legacy registered
612 00:49:34.780489 <6>[ 0.907031] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
613 00:49:34.790030 <6>[ 0.914228] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
614 00:49:34.863568 <5>[ 0.992751] Key type asymmetric registered
615 00:49:34.869312 <5>[ 0.997276] Asymmetric key parser 'x509' registered
616 00:49:34.877708 <6>[ 1.002763] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
617 00:49:34.883514 <6>[ 1.010650] io scheduler mq-deadline registered
618 00:49:34.892193 <6>[ 1.015627] io scheduler kyber registered
619 00:49:34.892660 <6>[ 1.020081] io scheduler bfq registered
620 00:49:34.992391 <6>[ 1.118050] ledtrig-cpu: registered to indicate activity on CPUs
621 00:49:35.287591 <6>[ 1.412898] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
622 00:49:35.327046 <6>[ 1.456163] msm_serial: driver initialized
623 00:49:35.333129 <6>[ 1.460948] SuperH (H)SCI(F) driver initialized
624 00:49:35.339017 <6>[ 1.466253] STMicroelectronics ASC driver initialized
625 00:49:35.344292 <6>[ 1.471907] STM32 USART driver initialized
626 00:49:35.475573 <6>[ 1.604125] brd: module loaded
627 00:49:35.512781 <6>[ 1.641304] loop: module loaded
628 00:49:35.541360 <6>[ 1.669671] CAN device driver interface
629 00:49:35.548068 <6>[ 1.674980] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
630 00:49:35.553701 <6>[ 1.682008] e1000e: Intel(R) PRO/1000 Network Driver
631 00:49:35.559555 <6>[ 1.687393] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
632 00:49:35.565204 <6>[ 1.693836] igb: Intel(R) Gigabit Ethernet Network Driver
633 00:49:35.573675 <6>[ 1.699659] igb: Copyright (c) 2007-2014 Intel Corporation.
634 00:49:35.585274 <6>[ 1.708816] pegasus: Pegasus/Pegasus II USB Ethernet driver
635 00:49:35.590957 <6>[ 1.714978] usbcore: registered new interface driver pegasus
636 00:49:35.596821 <6>[ 1.721104] usbcore: registered new interface driver asix
637 00:49:35.602578 <6>[ 1.726997] usbcore: registered new interface driver ax88179_178a
638 00:49:35.608353 <6>[ 1.733588] usbcore: registered new interface driver cdc_ether
639 00:49:35.614184 <6>[ 1.739882] usbcore: registered new interface driver smsc75xx
640 00:49:35.619975 <6>[ 1.746110] usbcore: registered new interface driver smsc95xx
641 00:49:35.625691 <6>[ 1.752350] usbcore: registered new interface driver net1080
642 00:49:35.631611 <6>[ 1.758474] usbcore: registered new interface driver cdc_subset
643 00:49:35.637303 <6>[ 1.764883] usbcore: registered new interface driver zaurus
644 00:49:35.645012 <6>[ 1.770930] usbcore: registered new interface driver cdc_ncm
645 00:49:35.654659 <6>[ 1.780304] usbcore: registered new interface driver usb-storage
646 00:49:35.937270 <6>[ 2.064532] i2c_dev: i2c /dev entries driver
647 00:49:35.997461 <5>[ 2.118623] cpuidle: enable-method property 'ti,am3352' found operations
648 00:49:36.003376 <6>[ 2.128252] sdhci: Secure Digital Host Controller Interface driver
649 00:49:36.010747 <6>[ 2.135030] sdhci: Copyright(c) Pierre Ossman
650 00:49:36.017942 <6>[ 2.141409] Synopsys Designware Multimedia Card Interface Driver
651 00:49:36.023431 <6>[ 2.149363] sdhci-pltfm: SDHCI platform and OF driver helper
652 00:49:36.151512 <6>[ 2.273265] usbcore: registered new interface driver usbhid
653 00:49:36.152152 <6>[ 2.279307] usbhid: USB HID core driver
654 00:49:36.191966 <6>[ 2.318501] NET: Registered PF_INET6 protocol family
655 00:49:36.223866 <6>[ 2.353025] Segment Routing with IPv6
656 00:49:36.229591 <6>[ 2.357174] In-situ OAM (IOAM) with IPv6
657 00:49:36.236464 <6>[ 2.361576] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
658 00:49:36.242252 <6>[ 2.368954] NET: Registered PF_PACKET protocol family
659 00:49:36.247991 <6>[ 2.374520] can: controller area network core
660 00:49:36.253795 <6>[ 2.379354] NET: Registered PF_CAN protocol family
661 00:49:36.254314 <6>[ 2.384582] can: raw protocol
662 00:49:36.259739 <6>[ 2.387910] can: broadcast manager protocol
663 00:49:36.266114 <6>[ 2.392509] can: netlink gateway - max_hops=1
664 00:49:36.272310 <5>[ 2.398003] Key type dns_resolver registered
665 00:49:36.278554 <6>[ 2.403075] ThumbEE CPU extension supported.
666 00:49:36.279033 <5>[ 2.407766] Registering SWP/SWPB emulation handler
667 00:49:36.288399 <3>[ 2.413461] omap_voltage_late_init: Voltage driver support not added
668 00:49:36.494279 <5>[ 2.620893] Loading compiled-in X.509 certificates
669 00:49:36.644459 <6>[ 2.760731] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
670 00:49:36.651844 <6>[ 2.777433] pinctrl-single 44e10800.pinmux: 142 pins, size 568
671 00:49:36.678156 <3>[ 2.801217] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
672 00:49:36.871735 <3>[ 2.994724] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
673 00:49:37.065845 <6>[ 3.193063] OMAP GPIO hardware version 0.1
674 00:49:37.086560 <6>[ 3.211940] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
675 00:49:37.178855 <4>[ 3.304023] at24 2-0054: supply vcc not found, using dummy regulator
676 00:49:37.215952 <4>[ 3.340973] at24 2-0055: supply vcc not found, using dummy regulator
677 00:49:37.253566 <4>[ 3.378664] at24 2-0056: supply vcc not found, using dummy regulator
678 00:49:37.293037 <4>[ 3.418099] at24 2-0057: supply vcc not found, using dummy regulator
679 00:49:37.330818 <6>[ 3.456681] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
680 00:49:37.412630 <3>[ 3.534412] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
681 00:49:37.437306 <6>[ 3.555487] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
682 00:49:37.459376 <4>[ 3.582346] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
683 00:49:37.467254 <4>[ 3.590956] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
684 00:49:37.596956 <6>[ 3.722220] omap_rng 48310000.rng: Random Number Generator ver. 20
685 00:49:37.620491 <5>[ 3.748547] random: crng init done
686 00:49:37.658232 <6>[ 3.785534] Freeing initrd memory: 14444K
687 00:49:37.668165 <6>[ 3.791899] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
688 00:49:37.721286 <6>[ 3.844227] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
689 00:49:37.727133 <6>[ 3.854545] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
690 00:49:37.738849 <6>[ 3.861878] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
691 00:49:37.744814 <6>[ 3.869330] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
692 00:49:37.756188 <6>[ 3.877470] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
693 00:49:37.763632 <6>[ 3.889100] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
694 00:49:37.776814 <5>[ 3.898116] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
695 00:49:37.804491 <3>[ 3.927978] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
696 00:49:37.810241 <6>[ 3.936571] edma 49000000.dma: TI EDMA DMA engine driver
697 00:49:37.881893 <3>[ 4.004679] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
698 00:49:37.896611 <6>[ 4.019068] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
699 00:49:37.909575 <3>[ 4.036210] l3-aon-clkctrl:0000:0: failed to disable
700 00:49:37.959439 <6>[ 4.082952] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
701 00:49:37.965193 <6>[ 4.092427] printk: legacy console [ttyS0] enabled
702 00:49:37.968057 <6>[ 4.092427] printk: legacy console [ttyS0] enabled
703 00:49:37.973577 <6>[ 4.102754] printk: legacy bootconsole [omap8250] disabled
704 00:49:37.979295 <6>[ 4.102754] printk: legacy bootconsole [omap8250] disabled
705 00:49:38.020086 <4>[ 4.142547] tps65217-pmic: Failed to locate of_node [id: -1]
706 00:49:38.023799 <4>[ 4.149943] tps65217-bl: Failed to locate of_node [id: -1]
707 00:49:38.040201 <6>[ 4.169638] tps65217 0-0024: TPS65217 ID 0xe version 1.2
708 00:49:38.058539 <6>[ 4.176603] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
709 00:49:38.070553 <6>[ 4.190296] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
710 00:49:38.075986 <6>[ 4.202188] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
711 00:49:38.098061 <6>[ 4.221962] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
712 00:49:38.104068 <6>[ 4.231019] sdhci-omap 48060000.mmc: Got CD GPIO
713 00:49:38.111955 <4>[ 4.236195] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
714 00:49:38.126701 <4>[ 4.249861] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
715 00:49:38.133117 <4>[ 4.258511] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
716 00:49:38.142929 <4>[ 4.267179] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
717 00:49:38.241914 <6>[ 4.366713] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
718 00:49:38.289134 <6>[ 4.412626] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
719 00:49:38.295480 <6>[ 4.421026] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
720 00:49:38.304544 <6>[ 4.429810] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
721 00:49:38.378595 <6>[ 4.504859] mmc1: new high speed MMC card at address 0001
722 00:49:38.387205 <6>[ 4.514500] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
723 00:49:38.401322 <6>[ 4.522312] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
724 00:49:38.409973 <6>[ 4.536830] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
725 00:49:38.422773 <6>[ 4.550153] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
726 00:49:38.431736 <6>[ 4.557333] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
727 00:49:38.483867 <6>[ 4.602739] mmc0: new high speed SDHC card at address aaaa
728 00:49:38.484443 <6>[ 4.611237] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
729 00:49:38.517410 <6>[ 4.644657] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
730 00:49:40.559405 <6>[ 6.682855] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
731 00:49:40.672708 <5>[ 6.721884] Sending DHCP requests ., OK
732 00:49:40.683976 <6>[ 6.806354] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
733 00:49:40.684372 <6>[ 6.814430] IP-Config: Complete:
734 00:49:40.695359 <6>[ 6.817969] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
735 00:49:40.700986 <6>[ 6.828410] host=192.168.6.8, domain=, nis-domain=(none)
736 00:49:40.706851 <6>[ 6.834535] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
737 00:49:40.713454 <6>[ 6.834569] nameserver0=10.255.253.1
738 00:49:40.719548 <6>[ 6.847202] clk: Disabling unused clocks
739 00:49:40.725077 <6>[ 6.851933] PM: genpd: Disabling unused power domains
740 00:49:40.744600 <6>[ 6.870561] Freeing unused kernel image (initmem) memory: 2048K
741 00:49:40.752075 <6>[ 6.880307] Run /init as init process
742 00:49:40.777134 Loading, please wait...
743 00:49:40.852730 Starting systemd-udevd version 252.22-1~deb12u1
744 00:49:43.874852 <4>[ 9.996903] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
745 00:49:44.053117 <4>[ 10.175291] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
746 00:49:44.195986 <6>[ 10.325571] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
747 00:49:44.206693 <6>[ 10.331246] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
748 00:49:44.444321 <6>[ 10.572367] hub 1-0:1.0: USB hub found
749 00:49:44.467841 <6>[ 10.595573] hub 1-0:1.0: 1 port detected
750 00:49:44.618820 <6>[ 10.746601] tda998x 0-0070: found TDA19988
751 00:49:47.697241 Begin: Loading essential drivers ... done.
752 00:49:47.702753 Begin: Running /scripts/init-premount ... done.
753 00:49:47.708349 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
754 00:49:47.717534 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
755 00:49:47.726822 Device /sys/class/net/eth0 found
756 00:49:47.727372 done.
757 00:49:47.807164 Begin: Waiting up to 180 secs for any network device to become available ... done.
758 00:49:47.875386 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
759 00:49:47.982591 IP-Config: eth0 guessed broadcast address 192.168.6.255
760 00:49:47.988090 IP-Config: eth0 complete (dhcp from 192.168.6.1):
761 00:49:47.993771 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
762 00:49:48.002626 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
763 00:49:48.008593 rootserver: 192.168.6.1 rootpath:
764 00:49:48.009333 filename :
765 00:49:48.104878 done.
766 00:49:48.120898 Begin: Running /scripts/nfs-bottom ... done.
767 00:49:48.188758 Begin: Running /scripts/init-bottom ... done.
768 00:49:49.588891 <30>[ 15.714390] systemd[1]: System time before build time, advancing clock.
769 00:49:49.797121 <30>[ 15.896465] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
770 00:49:49.805841 <30>[ 15.933153] systemd[1]: Detected architecture arm.
771 00:49:49.817999
772 00:49:49.818332 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
773 00:49:49.818559
774 00:49:49.846249 <30>[ 15.972323] systemd[1]: Hostname set to <debian-bookworm-armhf>.
775 00:49:51.988016 <30>[ 18.112714] systemd[1]: Queued start job for default target graphical.target.
776 00:49:52.004654 <30>[ 18.127421] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
777 00:49:52.012320 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
778 00:49:52.042844 <30>[ 18.164641] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
779 00:49:52.050293 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
780 00:49:52.074963 <30>[ 18.198060] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
781 00:49:52.088219 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
782 00:49:52.110091 <30>[ 18.233659] systemd[1]: Created slice user.slice - User and Session Slice.
783 00:49:52.116743 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
784 00:49:52.146532 <30>[ 18.263248] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
785 00:49:52.152663 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
786 00:49:52.181776 <30>[ 18.304233] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
787 00:49:52.192859 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
788 00:49:52.230363 <30>[ 18.342808] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
789 00:49:52.236748 <30>[ 18.363273] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
790 00:49:52.245235 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
791 00:49:52.268526 <30>[ 18.392219] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
792 00:49:52.276827 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
793 00:49:52.299426 <30>[ 18.422659] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
794 00:49:52.307810 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
795 00:49:52.332322 <30>[ 18.454013] systemd[1]: Reached target paths.target - Path Units.
796 00:49:52.337347 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
797 00:49:52.358667 <30>[ 18.482364] systemd[1]: Reached target remote-fs.target - Remote File Systems.
798 00:49:52.366049 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
799 00:49:52.388651 <30>[ 18.512348] systemd[1]: Reached target slices.target - Slice Units.
800 00:49:52.394138 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
801 00:49:52.419073 <30>[ 18.542613] systemd[1]: Reached target swap.target - Swaps.
802 00:49:52.423085 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
803 00:49:52.449324 <30>[ 18.572686] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
804 00:49:52.458281 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
805 00:49:52.480361 <30>[ 18.603549] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
806 00:49:52.488551 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
807 00:49:52.567333 <30>[ 18.685914] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
808 00:49:52.580190 <30>[ 18.703637] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
809 00:49:52.588635 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
810 00:49:52.612286 <30>[ 18.734686] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
811 00:49:52.619711 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
812 00:49:52.641542 <30>[ 18.764936] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
813 00:49:52.649738 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
814 00:49:52.674461 <30>[ 18.796744] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
815 00:49:52.680066 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
816 00:49:52.711436 <30>[ 18.833587] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
817 00:49:52.719213 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
818 00:49:52.746274 <30>[ 18.863653] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
819 00:49:52.764876 <30>[ 18.882224] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
820 00:49:52.812974 <30>[ 18.937199] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
821 00:49:52.839487 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
822 00:49:52.891033 <30>[ 19.015125] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
823 00:49:52.910626 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
824 00:49:52.971864 <30>[ 19.094986] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
825 00:49:52.990219 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
826 00:49:53.040260 <30>[ 19.163814] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
827 00:49:53.059722 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
828 00:49:53.120002 <30>[ 19.244045] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
829 00:49:53.138209 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
830 00:49:53.161360 <30>[ 19.286007] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
831 00:49:53.185503 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
832 00:49:53.250075 <30>[ 19.373421] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
833 00:49:53.268975 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
834 00:49:53.327978 <30>[ 19.453241] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
835 00:49:53.356113 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
836 00:49:53.409370 <30>[ 19.532840] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
837 00:49:53.415771 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
838 00:49:53.446087 <28>[ 19.566189] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
839 00:49:53.466292 <28>[ 19.590620] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
840 00:49:53.509372 <30>[ 19.635181] systemd[1]: Starting systemd-journald.service - Journal Service...
841 00:49:53.527580 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
842 00:49:53.599733 <30>[ 19.723919] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
843 00:49:53.615007 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
844 00:49:53.652751 <30>[ 19.777107] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
845 00:49:53.693361 Starting [0;1;39msystemd-network-g… units from Kernel command line...
846 00:49:53.749329 <30>[ 19.873126] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
847 00:49:53.800352 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
848 00:49:53.862596 <30>[ 19.987297] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
849 00:49:53.936915 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
850 00:49:53.957295 <30>[ 20.081907] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
851 00:49:54.055843 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
852 00:49:54.078745 <30>[ 20.204149] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
853 00:49:54.110094 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
854 00:49:54.143096 <30>[ 20.266417] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
855 00:49:54.169481 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
856 00:49:54.321033 <30>[ 20.446209] systemd[1]: modprobe@configfs.service: Deactivated successfully.
857 00:49:54.357726 <30>[ 20.482601] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
858 00:49:54.386913 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
859 00:49:54.408468 <30>[ 20.534577] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
860 00:49:54.437317 <30>[ 20.561564] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
861 00:49:54.458051 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
862 00:49:54.479890 <30>[ 20.603623] systemd[1]: Started systemd-journald.service - Journal Service.
863 00:49:54.485797 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
864 00:49:54.517171 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
865 00:49:54.543213 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
866 00:49:54.573600 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
867 00:49:54.609687 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
868 00:49:54.639029 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
869 00:49:54.667786 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
870 00:49:54.697768 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
871 00:49:54.722536 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
872 00:49:54.791904 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
873 00:49:54.832879 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
874 00:49:54.874131 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
875 00:49:54.942136 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
876 00:49:55.043250 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
877 00:49:55.210133 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
878 00:49:55.289857 <46>[ 21.414248] systemd-journald[164]: Received client request to flush runtime journal.
879 00:49:55.341495 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
880 00:49:55.442281 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
881 00:49:56.233201 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
882 00:49:56.310773 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
883 00:49:56.951890 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
884 00:49:57.112858 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
885 00:49:57.140950 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
886 00:49:57.158735 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
887 00:49:57.229075 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
888 00:49:57.285075 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
889 00:49:58.204258 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
890 00:49:58.258039 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
891 00:49:58.667118 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
892 00:49:58.820255 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
893 00:49:58.899028 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
894 00:50:00.742105 <5>[ 26.866503] cfg80211: Loading compiled-in X.509 certificates for regulatory database
895 00:50:00.852061 [[0m[0;31m* [0m] (1 of 5) Job systemd-timesyncd.service/start running (8s / 1min 36s)
896 00:50:01.122074 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
897 00:50:01.169612 [K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
898 00:50:01.751102 <5>[ 27.877850] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
899 00:50:01.794381 <5>[ 27.917161] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
900 00:50:01.800233 <4>[ 27.926493] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
901 00:50:01.807938 <6>[ 27.935675] cfg80211: failed to load regulatory.db
902 00:50:01.992740 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
903 00:50:02.854084 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
904 00:50:02.873746 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
905 00:50:03.289408 <46>[ 29.404083] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
906 00:50:03.436356 <46>[ 29.554175] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
907 00:50:12.850189 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
908 00:50:12.879913 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
909 00:50:12.900367 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
910 00:50:12.923070 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
911 00:50:12.988646 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
912 00:50:13.030828 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
913 00:50:13.093011 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
914 00:50:13.153123 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
915 00:50:13.211444 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
916 00:50:13.244783 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
917 00:50:13.275849 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
918 00:50:13.303129 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
919 00:50:13.345299 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
920 00:50:13.376192 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
921 00:50:13.409308 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
922 00:50:13.439393 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
923 00:50:13.463676 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
924 00:50:13.496325 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
925 00:50:13.520300 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
926 00:50:13.541308 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
927 00:50:13.577091 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
928 00:50:13.602434 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
929 00:50:13.630381 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
930 00:50:13.698823 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
931 00:50:13.739019 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
932 00:50:13.845708 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
933 00:50:13.937989 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
934 00:50:14.007510 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
935 00:50:14.043940 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
936 00:50:14.072324 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
937 00:50:14.261472 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
938 00:50:14.321009 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
939 00:50:14.402647 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
940 00:50:14.418639 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
941 00:50:14.446256 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
942 00:50:14.729962 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
943 00:50:15.130417 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
944 00:50:15.190853 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
945 00:50:15.222613 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
946 00:50:15.311641 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
947 00:50:15.491511 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
948 00:50:15.650254
949 00:50:15.653865 Debian GNU/Linux 12 debworm-armhf login: root (automatic login)
950 00:50:15.654150
951 00:50:15.956333 Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Fri Nov 8 00:29:03 UTC 2024 armv7l
952 00:50:15.956724
953 00:50:15.961956 The programs included with the Debian GNU/Linux system are free software;
954 00:50:15.967502 the exact distribution terms for each program are described in the
955 00:50:15.973194 individual files in /usr/share/doc/*/copyright.
956 00:50:15.973478
957 00:50:15.981131 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
958 00:50:15.981437 permitted by applicable law.
959 00:50:20.972921 Unable to match end of the kernel message
961 00:50:20.974681 Setting prompt string to ['/ #']
962 00:50:20.975303 end: 2.4.4.1 login-action (duration 00:00:48) [common]
964 00:50:20.976793 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
965 00:50:20.977436 start: 2.4.5 expect-shell-connection (timeout 00:03:14) [common]
966 00:50:20.977990 Setting prompt string to ['/ #']
967 00:50:20.978488 Forcing a shell prompt, looking for ['/ #']
969 00:50:21.029539 / #
970 00:50:21.030135 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
971 00:50:21.030409 Waiting using forced prompt support (timeout 00:02:30)
972 00:50:21.034616
973 00:50:21.043456 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
974 00:50:21.044263 start: 2.4.6 export-device-env (timeout 00:03:14) [common]
975 00:50:21.044901 Sending with 10 millisecond of delay
977 00:50:26.038067 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/956692/extract-nfsrootfs-1hrqq9am'
978 00:50:26.049326 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/956692/extract-nfsrootfs-1hrqq9am'
979 00:50:26.050439 Sending with 10 millisecond of delay
981 00:50:28.150671 / # export NFS_SERVER_IP='192.168.6.3'
982 00:50:28.161643 export NFS_SERVER_IP='192.168.6.3'
983 00:50:28.162930 end: 2.4.6 export-device-env (duration 00:00:07) [common]
984 00:50:28.163566 end: 2.4 uboot-commands (duration 00:01:53) [common]
985 00:50:28.164233 end: 2 uboot-action (duration 00:01:53) [common]
986 00:50:28.164856 start: 3 lava-test-retry (timeout 00:06:54) [common]
987 00:50:28.165469 start: 3.1 lava-test-shell (timeout 00:06:54) [common]
988 00:50:28.166006 Using namespace: common
990 00:50:28.267261 / # #
991 00:50:28.268040 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
992 00:50:28.272896 #
993 00:50:28.278513 Using /lava-956692
995 00:50:28.379883 / # export SHELL=/bin/bash
996 00:50:28.384351 export SHELL=/bin/bash
998 00:50:28.492592 / # . /lava-956692/environment
999 00:50:28.498331 . /lava-956692/environment
1001 00:50:28.611633 / # /lava-956692/bin/lava-test-runner /lava-956692/0
1002 00:50:28.612423 Test shell timeout: 10s (minimum of the action and connection timeout)
1003 00:50:28.617208 /lava-956692/bin/lava-test-runner /lava-956692/0
1004 00:50:28.996354 + export TESTRUN_ID=0_timesync-off
1005 00:50:29.004247 + TESTRUN_ID=0_timesync-off
1006 00:50:29.004790 + cd /lava-956692/0/tests/0_timesync-off
1007 00:50:29.005253 ++ cat uuid
1008 00:50:29.020117 + UUID=956692_1.6.2.4.1
1009 00:50:29.020663 + set +x
1010 00:50:29.028808 <LAVA_SIGNAL_STARTRUN 0_timesync-off 956692_1.6.2.4.1>
1011 00:50:29.029394 + systemctl stop systemd-timesyncd
1012 00:50:29.030196 Received signal: <STARTRUN> 0_timesync-off 956692_1.6.2.4.1
1013 00:50:29.030681 Starting test lava.0_timesync-off (956692_1.6.2.4.1)
1014 00:50:29.031251 Skipping test definition patterns.
1015 00:50:29.331510 + set +x
1016 00:50:29.332164 <LAVA_SIGNAL_ENDRUN 0_timesync-off 956692_1.6.2.4.1>
1017 00:50:29.332907 Received signal: <ENDRUN> 0_timesync-off 956692_1.6.2.4.1
1018 00:50:29.333443 Ending use of test pattern.
1019 00:50:29.333945 Ending test lava.0_timesync-off (956692_1.6.2.4.1), duration 0.30
1021 00:50:29.487113 + export TESTRUN_ID=1_kselftest-dt
1022 00:50:29.495066 + TESTRUN_ID=1_kselftest-dt
1023 00:50:29.495641 + cd /lava-956692/0/tests/1_kselftest-dt
1024 00:50:29.496135 ++ cat uuid
1025 00:50:29.510699 + UUID=956692_1.6.2.4.5
1026 00:50:29.511301 + set +x
1027 00:50:29.516288 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 956692_1.6.2.4.5>
1028 00:50:29.516788 + cd ./automated/linux/kselftest/
1029 00:50:29.517505 Received signal: <STARTRUN> 1_kselftest-dt 956692_1.6.2.4.5
1030 00:50:29.518013 Starting test lava.1_kselftest-dt (956692_1.6.2.4.5)
1031 00:50:29.518563 Skipping test definition patterns.
1032 00:50:29.546240 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1033 00:50:29.655373 INFO: install_deps skipped
1034 00:50:30.275016 --2024-11-08 00:50:30-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1035 00:50:30.308761 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1036 00:50:30.454527 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1037 00:50:30.603520 HTTP request sent, awaiting response... 200 OK
1038 00:50:30.603890 Length: 4099492 (3.9M) [application/octet-stream]
1039 00:50:30.608732 Saving to: 'kselftest_armhf.tar.gz'
1040 00:50:30.609220
1041 00:50:32.262780
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 175KB/s
kselftest_armhf.tar 5%[> ] 218.67K 384KB/s
kselftest_armhf.tar 20%[===> ] 808.32K 810KB/s
kselftest_armhf.tar 56%[==========> ] 2.21M 1.81MB/s
kselftest_armhf.tar 74%[=============> ] 2.90M 2.03MB/s
kselftest_armhf.tar 97%[==================> ] 3.80M 2.31MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.37MB/s in 1.6s
1042 00:50:32.263496
1043 00:50:32.766222 2024-11-08 00:50:32 (2.37 MB/s) - 'kselftest_armhf.tar.gz' saved [4099492/4099492]
1044 00:50:32.766631
1045 00:50:47.733160 skiplist:
1046 00:50:47.733574 ========================================
1047 00:50:47.738873 ========================================
1048 00:50:47.845606 dt:test_unprobed_devices.sh
1049 00:50:47.880709 ============== Tests to run ===============
1050 00:50:47.887729 dt:test_unprobed_devices.sh
1051 00:50:47.891958 ===========End Tests to run ===============
1052 00:50:47.903051 shardfile-dt pass
1053 00:50:48.128108 <12>[ 74.257544] kselftest: Running tests in dt
1054 00:50:48.155732 TAP version 13
1055 00:50:48.180526 1..1
1056 00:50:48.233551 # timeout set to 45
1057 00:50:48.234018 # selftests: dt: test_unprobed_devices.sh
1058 00:50:49.076222 # TAP version 13
1059 00:51:14.035558 # 1..257
1060 00:51:14.215299 # ok 1 / # SKIP
1061 00:51:14.232662 # ok 2 /clk_mcasp0
1062 00:51:14.309229 # ok 3 /clk_mcasp0_fixed # SKIP
1063 00:51:14.374793 # ok 4 /cpus/cpu@0 # SKIP
1064 00:51:14.450338 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1065 00:51:14.466442 # ok 6 /fixedregulator0
1066 00:51:14.488637 # ok 7 /leds
1067 00:51:14.512276 # ok 8 /ocp
1068 00:51:14.536430 # ok 9 /ocp/interconnect@44c00000
1069 00:51:14.555010 # ok 10 /ocp/interconnect@44c00000/segment@0
1070 00:51:14.581930 # ok 11 /ocp/interconnect@44c00000/segment@100000
1071 00:51:14.603870 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1072 00:51:14.674615 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1073 00:51:14.694994 # ok 14 /ocp/interconnect@44c00000/segment@200000
1074 00:51:14.723311 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1075 00:51:14.829133 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1076 00:51:14.901590 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1077 00:51:14.973905 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1078 00:51:15.045884 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1079 00:51:15.113632 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1080 00:51:15.187777 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1081 00:51:15.257035 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1082 00:51:15.329486 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1083 00:51:15.401912 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1084 00:51:15.473935 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1085 00:51:15.548176 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1086 00:51:15.622173 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1087 00:51:15.695611 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1088 00:51:15.767281 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1089 00:51:15.834455 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1090 00:51:15.907069 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1091 00:51:15.978917 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1092 00:51:16.052189 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1093 00:51:16.123200 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1094 00:51:16.195974 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1095 00:51:16.265199 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1096 00:51:16.343234 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1097 00:51:16.416179 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1098 00:51:16.483569 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1099 00:51:16.555545 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1100 00:51:16.634817 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1101 00:51:16.706344 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1102 00:51:16.776838 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1103 00:51:16.844826 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1104 00:51:16.924587 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1105 00:51:16.990510 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1106 00:51:17.063843 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1107 00:51:17.133648 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1108 00:51:17.205750 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1109 00:51:17.281325 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1110 00:51:17.354648 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1111 00:51:17.426758 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1112 00:51:17.494136 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1113 00:51:17.567330 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1114 00:51:17.642391 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1115 00:51:17.714915 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1116 00:51:17.787132 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1117 00:51:17.856036 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1118 00:51:17.930329 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1119 00:51:17.998305 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1120 00:51:18.070589 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1121 00:51:18.142491 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1122 00:51:18.214696 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1123 00:51:18.287686 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1124 00:51:18.357970 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1125 00:51:18.432779 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1126 00:51:18.505476 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1127 00:51:18.581775 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1128 00:51:18.649708 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1129 00:51:18.722971 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1130 00:51:18.797868 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1131 00:51:18.870098 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1132 00:51:18.942221 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1133 00:51:19.013599 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1134 00:51:19.085753 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1135 00:51:19.162160 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1136 00:51:19.230642 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1137 00:51:19.302311 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1138 00:51:19.373951 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1139 00:51:19.445737 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1140 00:51:19.517772 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1141 00:51:19.589802 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1142 00:51:19.661155 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1143 00:51:19.732983 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1144 00:51:19.805143 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1145 00:51:19.876996 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1146 00:51:19.949066 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1147 00:51:20.020539 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1148 00:51:20.097386 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1149 00:51:20.172512 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1150 00:51:20.238133 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1151 00:51:20.316079 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1152 00:51:20.383365 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1153 00:51:20.456586 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1154 00:51:20.477670 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1155 00:51:20.501438 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1156 00:51:20.525461 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1157 00:51:20.549463 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1158 00:51:20.573306 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1159 00:51:20.601930 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1160 00:51:20.624810 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1161 00:51:20.648570 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1162 00:51:20.750220 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1163 00:51:20.776192 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1164 00:51:20.798944 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1165 00:51:20.823316 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1166 00:51:20.930795 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1167 00:51:21.007015 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1168 00:51:21.086334 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1169 00:51:21.156118 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1170 00:51:21.227589 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1171 00:51:21.296634 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1172 00:51:21.368902 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1173 00:51:21.440621 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1174 00:51:21.513518 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1175 00:51:21.587699 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1176 00:51:21.660232 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1177 00:51:21.732738 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1178 00:51:21.803351 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1179 00:51:21.877562 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1180 00:51:21.955652 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1181 00:51:22.028071 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1182 00:51:22.046670 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1183 00:51:22.122369 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1184 00:51:22.192683 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1185 00:51:22.264765 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1186 00:51:22.283235 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1187 00:51:22.355238 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1188 00:51:22.382801 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1189 00:51:22.454269 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1190 00:51:22.480349 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1191 00:51:22.497744 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1192 00:51:22.522733 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1193 00:51:22.551934 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1194 00:51:22.583331 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1195 00:51:22.601061 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1196 00:51:22.623712 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1197 00:51:22.693434 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1198 00:51:22.714645 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1199 00:51:22.742429 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1200 00:51:22.815436 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1201 00:51:22.882796 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1202 00:51:22.909075 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1203 00:51:23.010643 # not ok 144 /ocp/interconnect@47c00000
1204 00:51:23.078027 # not ok 145 /ocp/interconnect@47c00000/segment@0
1205 00:51:23.100179 # ok 146 /ocp/interconnect@48000000
1206 00:51:23.127085 # ok 147 /ocp/interconnect@48000000/segment@0
1207 00:51:23.152060 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1208 00:51:23.173101 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1209 00:51:23.199199 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1210 00:51:23.222342 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1211 00:51:23.242897 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1212 00:51:23.271014 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1213 00:51:23.292855 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1214 00:51:23.361745 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1215 00:51:23.441573 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1216 00:51:23.456802 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1217 00:51:23.483632 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1218 00:51:23.509019 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1219 00:51:23.533512 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1220 00:51:23.551396 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1221 00:51:23.575752 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1222 00:51:23.602169 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1223 00:51:23.623558 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1224 00:51:23.645198 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1225 00:51:23.669012 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1226 00:51:23.691445 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1227 00:51:23.715801 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1228 00:51:23.742426 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1229 00:51:23.763293 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1230 00:51:23.784094 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1231 00:51:23.813798 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1232 00:51:23.832754 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1233 00:51:23.860773 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1234 00:51:23.881514 # ok 175 /ocp/interconnect@48000000/segment@100000
1235 00:51:23.903226 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1236 00:51:23.926349 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1237 00:51:24.003468 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1238 00:51:24.076933 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1239 00:51:24.142507 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1240 00:51:24.216114 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1241 00:51:24.290937 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1242 00:51:24.361186 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1243 00:51:24.431621 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1244 00:51:24.505460 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1245 00:51:24.525513 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1246 00:51:24.548685 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1247 00:51:24.572032 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1248 00:51:24.600521 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1249 00:51:24.623405 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1250 00:51:24.649097 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1251 00:51:24.671884 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1252 00:51:24.695918 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1253 00:51:24.719724 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1254 00:51:24.743412 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1255 00:51:24.767714 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1256 00:51:24.788058 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1257 00:51:24.809356 # ok 198 /ocp/interconnect@48000000/segment@200000
1258 00:51:24.839042 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1259 00:51:24.912214 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1260 00:51:24.930838 # ok 201 /ocp/interconnect@48000000/segment@300000
1261 00:51:24.958187 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1262 00:51:24.982081 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1263 00:51:25.003789 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1264 00:51:25.025438 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1265 00:51:25.048533 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1266 00:51:25.071835 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1267 00:51:25.145661 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1268 00:51:25.161966 # ok 209 /ocp/interconnect@4a000000
1269 00:51:25.185989 # ok 210 /ocp/interconnect@4a000000/segment@0
1270 00:51:25.212870 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1271 00:51:25.240190 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1272 00:51:25.264626 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1273 00:51:25.290805 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1274 00:51:25.355066 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1275 00:51:25.461544 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1276 00:51:25.533349 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1277 00:51:25.636473 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1278 00:51:25.709438 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1279 00:51:25.775974 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1280 00:51:25.878107 # not ok 221 /ocp/interconnect@4b140000
1281 00:51:25.949318 # not ok 222 /ocp/interconnect@4b140000/segment@0
1282 00:51:26.015561 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1283 00:51:26.040362 # ok 224 /ocp/target-module@40300000
1284 00:51:26.063317 # ok 225 /ocp/target-module@40300000/sram@0
1285 00:51:26.133608 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1286 00:51:26.205393 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1287 00:51:26.228811 # ok 228 /ocp/target-module@47400000
1288 00:51:26.252161 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1289 00:51:26.276189 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1290 00:51:26.299312 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1291 00:51:26.321364 # ok 232 /ocp/target-module@47400000/usb@1400
1292 00:51:26.340059 # ok 233 /ocp/target-module@47400000/usb@1800
1293 00:51:26.362177 # ok 234 /ocp/target-module@47810000
1294 00:51:26.384614 # ok 235 /ocp/target-module@49000000
1295 00:51:26.410938 # ok 236 /ocp/target-module@49000000/dma@0
1296 00:51:26.437039 # ok 237 /ocp/target-module@49800000
1297 00:51:26.453057 # ok 238 /ocp/target-module@49800000/dma@0
1298 00:51:26.475741 # ok 239 /ocp/target-module@49900000
1299 00:51:26.501064 # ok 240 /ocp/target-module@49900000/dma@0
1300 00:51:26.520854 # ok 241 /ocp/target-module@49a00000
1301 00:51:26.549332 # ok 242 /ocp/target-module@49a00000/dma@0
1302 00:51:26.570444 # ok 243 /ocp/target-module@4c000000
1303 00:51:26.639016 # not ok 244 /ocp/target-module@4c000000/emif@0
1304 00:51:26.660840 # ok 245 /ocp/target-module@50000000
1305 00:51:26.682176 # ok 246 /ocp/target-module@53100000
1306 00:51:26.754531 # not ok 247 /ocp/target-module@53100000/sham@0
1307 00:51:26.775746 # ok 248 /ocp/target-module@53500000
1308 00:51:26.851370 # not ok 249 /ocp/target-module@53500000/aes@0
1309 00:51:26.869046 # ok 250 /ocp/target-module@56000000
1310 00:51:26.974704 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1311 00:51:27.043731 # ok 252 /opp-table # SKIP
1312 00:51:27.117707 # ok 253 /soc # SKIP
1313 00:51:27.138509 # ok 254 /sound
1314 00:51:27.158604 # ok 255 /target-module@4b000000
1315 00:51:27.184233 # ok 256 /target-module@4b000000/target-module@140000
1316 00:51:27.204731 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1317 00:51:27.213133 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1318 00:51:27.221078 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1319 00:51:29.402725 dt_test_unprobed_devices_sh_ skip
1320 00:51:29.408368 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1321 00:51:29.413974 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1322 00:51:29.414464 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1323 00:51:29.422783 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1324 00:51:29.423263 dt_test_unprobed_devices_sh_fixedregulator0 pass
1325 00:51:29.428507 dt_test_unprobed_devices_sh_leds pass
1326 00:51:29.434115 dt_test_unprobed_devices_sh_ocp pass
1327 00:51:29.439656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1328 00:51:29.445285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1329 00:51:29.450737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1330 00:51:29.456504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1331 00:51:29.467618 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1332 00:51:29.473417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1333 00:51:29.478787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1334 00:51:29.490172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1335 00:51:29.496557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1336 00:51:29.506996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1337 00:51:29.518266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1338 00:51:29.529690 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1339 00:51:29.540689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1340 00:51:29.546265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1341 00:51:29.557539 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1342 00:51:29.568571 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1343 00:51:29.579880 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1344 00:51:29.591165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1345 00:51:29.596618 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1346 00:51:29.607769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1347 00:51:29.618964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1348 00:51:29.630158 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1349 00:51:29.641334 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1350 00:51:29.646983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1351 00:51:29.658176 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1352 00:51:29.669358 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1353 00:51:29.680494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1354 00:51:29.686117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1355 00:51:29.697388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1356 00:51:29.708636 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1357 00:51:29.719879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1358 00:51:29.730965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1359 00:51:29.742159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1360 00:51:29.753309 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1361 00:51:29.764547 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1362 00:51:29.775658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1363 00:51:29.786837 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1364 00:51:29.798073 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1365 00:51:29.809334 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1366 00:51:29.820538 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1367 00:51:29.831673 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1368 00:51:29.842874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1369 00:51:29.854075 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1370 00:51:29.865196 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1371 00:51:29.876397 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1372 00:51:29.887583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1373 00:51:29.898799 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1374 00:51:29.910045 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1375 00:51:29.921232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1376 00:51:29.932386 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1377 00:51:29.938105 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1378 00:51:29.949173 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1379 00:51:29.960412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1380 00:51:29.971617 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1381 00:51:29.982780 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1382 00:51:29.993964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1383 00:51:30.005149 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1384 00:51:30.016350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1385 00:51:30.027841 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1386 00:51:30.038953 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1387 00:51:30.044583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1388 00:51:30.055781 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1389 00:51:30.066705 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1390 00:51:30.077957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1391 00:51:30.089115 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1392 00:51:30.100370 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1393 00:51:30.111591 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1394 00:51:30.122643 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1395 00:51:30.133879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1396 00:51:30.145026 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1397 00:51:30.156238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1398 00:51:30.167437 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1399 00:51:30.178599 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1400 00:51:30.189851 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1401 00:51:30.200974 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1402 00:51:30.212201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1403 00:51:30.217843 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1404 00:51:30.228989 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1405 00:51:30.240163 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1406 00:51:30.251353 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1407 00:51:30.262645 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1408 00:51:30.273749 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1409 00:51:30.284908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1410 00:51:30.296133 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1411 00:51:30.307296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1412 00:51:30.318664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1413 00:51:30.329672 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1414 00:51:30.340890 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1415 00:51:30.346552 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1416 00:51:30.358013 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1417 00:51:30.368900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1418 00:51:30.374550 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1419 00:51:30.385650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1420 00:51:30.391341 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1421 00:51:30.402483 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1422 00:51:30.413674 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1423 00:51:30.419300 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1424 00:51:30.430452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1425 00:51:30.441648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1426 00:51:30.452846 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1427 00:51:30.464020 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1428 00:51:30.475206 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1429 00:51:30.486420 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1430 00:51:30.503303 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1431 00:51:30.514477 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1432 00:51:30.525723 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1433 00:51:30.536632 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1434 00:51:30.547983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1435 00:51:30.559024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1436 00:51:30.570200 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1437 00:51:30.581558 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1438 00:51:30.598195 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1439 00:51:30.609412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1440 00:51:30.626402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1441 00:51:30.637455 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1442 00:51:30.643039 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1443 00:51:30.654272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1444 00:51:30.659838 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1445 00:51:30.671119 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1446 00:51:30.682250 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1447 00:51:30.687874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1448 00:51:30.699143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1449 00:51:30.704770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1450 00:51:30.715798 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1451 00:51:30.721397 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1452 00:51:30.732691 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1453 00:51:30.738247 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1454 00:51:30.749420 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1455 00:51:30.760662 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1456 00:51:30.771746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1457 00:51:30.777411 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1458 00:51:30.788768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1459 00:51:30.799776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1460 00:51:30.810999 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1461 00:51:30.816683 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1462 00:51:30.822180 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1463 00:51:30.827745 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1464 00:51:30.833437 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1465 00:51:30.838998 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1466 00:51:30.850224 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1467 00:51:30.855780 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1468 00:51:30.861333 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1469 00:51:30.872488 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1470 00:51:30.878278 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1471 00:51:30.889376 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1472 00:51:30.894893 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1473 00:51:30.906117 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1474 00:51:30.911773 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1475 00:51:30.922891 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1476 00:51:30.928497 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1477 00:51:30.939705 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1478 00:51:30.945299 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1479 00:51:30.950887 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1480 00:51:30.962075 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1481 00:51:30.967845 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1482 00:51:30.978898 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1483 00:51:30.984462 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1484 00:51:30.995752 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1485 00:51:31.001283 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1486 00:51:31.012554 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1487 00:51:31.018060 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1488 00:51:31.029275 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1489 00:51:31.034896 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1490 00:51:31.046139 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1491 00:51:31.052271 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1492 00:51:31.062855 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1493 00:51:31.068381 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1494 00:51:31.074134 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1495 00:51:31.085249 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1496 00:51:31.096386 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1497 00:51:31.107573 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1498 00:51:31.118844 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1499 00:51:31.129959 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1500 00:51:31.135550 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1501 00:51:31.146825 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1502 00:51:31.157926 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1503 00:51:31.169116 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1504 00:51:31.180261 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1505 00:51:31.185939 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1506 00:51:31.197088 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1507 00:51:31.202849 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1508 00:51:31.214033 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1509 00:51:31.219486 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1510 00:51:31.230983 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1511 00:51:31.236334 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1512 00:51:31.247480 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1513 00:51:31.253034 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1514 00:51:31.264205 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1515 00:51:31.269861 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1516 00:51:31.281045 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1517 00:51:31.286814 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1518 00:51:31.297874 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1519 00:51:31.303768 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1520 00:51:31.309142 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1521 00:51:31.320417 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1522 00:51:31.325945 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1523 00:51:31.337143 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1524 00:51:31.342731 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1525 00:51:31.353790 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1526 00:51:31.359413 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1527 00:51:31.364984 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1528 00:51:31.370711 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1529 00:51:31.381871 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1530 00:51:31.387395 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1531 00:51:31.398583 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1532 00:51:31.404218 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1533 00:51:31.415522 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1534 00:51:31.426510 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1535 00:51:31.438053 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1536 00:51:31.443366 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1537 00:51:31.454560 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1538 00:51:31.465839 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1539 00:51:31.471490 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1540 00:51:31.477094 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1541 00:51:31.482689 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1542 00:51:31.488281 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1543 00:51:31.493978 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1544 00:51:31.499562 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1545 00:51:31.505113 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1546 00:51:31.510759 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1547 00:51:31.521861 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1548 00:51:31.529090 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1549 00:51:31.533045 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1550 00:51:31.538634 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1551 00:51:31.544218 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1552 00:51:31.549799 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1553 00:51:31.555391 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1554 00:51:31.561030 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1555 00:51:31.566607 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1556 00:51:31.572186 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1557 00:51:31.577875 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1558 00:51:31.583452 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1559 00:51:31.589153 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1560 00:51:31.594757 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1561 00:51:31.600339 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1562 00:51:31.605951 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1563 00:51:31.611486 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1564 00:51:31.617221 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1565 00:51:31.622917 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1566 00:51:31.628352 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1567 00:51:31.634011 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1568 00:51:31.639578 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1569 00:51:31.645124 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1570 00:51:31.650833 dt_test_unprobed_devices_sh_opp-table skip
1571 00:51:31.651423 dt_test_unprobed_devices_sh_soc skip
1572 00:51:31.656317 dt_test_unprobed_devices_sh_sound pass
1573 00:51:31.661930 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1574 00:51:31.667590 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1575 00:51:31.673102 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1576 00:51:31.678883 dt_test_unprobed_devices_sh fail
1577 00:51:31.684371 + ../../utils/send-to-lava.sh ./output/result.txt
1578 00:51:31.689943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1579 00:51:31.691004 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1581 00:51:31.695398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1582 00:51:31.696241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1584 00:51:31.785129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1585 00:51:31.786075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1587 00:51:31.878728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1588 00:51:31.879620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1590 00:51:31.970102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1591 00:51:31.970974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1593 00:51:32.066285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1594 00:51:32.067585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1596 00:51:32.159480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1597 00:51:32.160355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1599 00:51:32.253539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1600 00:51:32.254188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1602 00:51:32.345858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1603 00:51:32.346679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1605 00:51:32.441771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1606 00:51:32.442418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1608 00:51:32.534962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1609 00:51:32.535631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1611 00:51:32.628277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1612 00:51:32.629144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1614 00:51:32.722689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1615 00:51:32.723483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1617 00:51:32.823590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1618 00:51:32.824764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1620 00:51:32.927449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1621 00:51:32.928093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1623 00:51:33.022788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1624 00:51:33.023573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1626 00:51:33.120500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1627 00:51:33.121315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1629 00:51:33.216150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1630 00:51:33.216970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1632 00:51:33.309905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1633 00:51:33.310615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1635 00:51:33.404467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1636 00:51:33.405212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1638 00:51:33.494837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1639 00:51:33.495856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1641 00:51:33.588162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1642 00:51:33.589085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1644 00:51:33.681989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1645 00:51:33.682892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1647 00:51:33.774470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1648 00:51:33.775504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1650 00:51:33.863057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1651 00:51:33.863968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1653 00:51:33.955371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1654 00:51:33.956307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1656 00:51:34.049208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1657 00:51:34.050343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1659 00:51:34.143204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1660 00:51:34.144092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1662 00:51:34.236349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1663 00:51:34.237372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1665 00:51:34.332626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1666 00:51:34.333514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1668 00:51:34.424125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1669 00:51:34.425008 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1671 00:51:34.522186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1672 00:51:34.523095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1674 00:51:34.613886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1675 00:51:34.614766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1677 00:51:34.702884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1678 00:51:34.703731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1680 00:51:34.793903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1681 00:51:34.794754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1683 00:51:34.887661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1684 00:51:34.888526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1686 00:51:34.981122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1687 00:51:34.981934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1689 00:51:35.076995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1690 00:51:35.077880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1692 00:51:35.172176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1693 00:51:35.173016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1695 00:51:35.267955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1696 00:51:35.268765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1698 00:51:35.360877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1699 00:51:35.361726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1701 00:51:35.456795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1702 00:51:35.457590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1704 00:51:35.549440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1705 00:51:35.550489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1707 00:51:35.642890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1708 00:51:35.643735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1710 00:51:35.737013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1711 00:51:35.737979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1713 00:51:35.831195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1714 00:51:35.832028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1716 00:51:35.924227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1717 00:51:35.925435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1719 00:51:36.017132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1720 00:51:36.018036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1722 00:51:36.112768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1723 00:51:36.113621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1725 00:51:36.206651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1726 00:51:36.207480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1728 00:51:36.299749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1729 00:51:36.300653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1731 00:51:36.394211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1732 00:51:36.395097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1734 00:51:36.485963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1735 00:51:36.486605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1737 00:51:36.577994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1738 00:51:36.578881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1740 00:51:36.673750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1741 00:51:36.674658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1743 00:51:36.767104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1744 00:51:36.767990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1746 00:51:36.862876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1747 00:51:36.863724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1749 00:51:36.964430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1750 00:51:36.965252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1752 00:51:37.062590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1753 00:51:37.063461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1755 00:51:37.155257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1756 00:51:37.156116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1758 00:51:37.249423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1759 00:51:37.250341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1761 00:51:37.343908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1762 00:51:37.344793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1764 00:51:37.434873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1765 00:51:37.435740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1767 00:51:37.529447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1768 00:51:37.530115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1770 00:51:37.624959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1771 00:51:37.626281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1773 00:51:37.716947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1774 00:51:37.718150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1776 00:51:37.812339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1777 00:51:37.813561 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1779 00:51:37.905846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1780 00:51:37.906774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1782 00:51:37.997228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1783 00:51:37.998123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1785 00:51:38.090930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1786 00:51:38.091862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1788 00:51:38.187890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1789 00:51:38.188776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1791 00:51:38.289007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1792 00:51:38.289920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1794 00:51:38.388260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1795 00:51:38.389174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1797 00:51:38.485432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1798 00:51:38.486590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1800 00:51:38.577843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1801 00:51:38.578413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1803 00:51:38.670956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1804 00:51:38.672044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1806 00:51:38.764784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1807 00:51:38.765651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1809 00:51:38.857361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1810 00:51:38.858225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1812 00:51:38.952431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1813 00:51:38.953213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1815 00:51:39.045445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1816 00:51:39.046076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1818 00:51:39.136673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1819 00:51:39.137692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1821 00:51:39.232221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1822 00:51:39.233055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1824 00:51:39.324613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1825 00:51:39.325442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1827 00:51:39.417133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1828 00:51:39.417945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1830 00:51:39.509905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1831 00:51:39.511034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1833 00:51:39.602383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1834 00:51:39.603415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1836 00:51:39.697053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1837 00:51:39.698130 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1839 00:51:39.790075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1840 00:51:39.791080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1842 00:51:39.883497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1843 00:51:39.884643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1845 00:51:39.977706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1846 00:51:39.978706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1848 00:51:40.072236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1849 00:51:40.073120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1851 00:51:40.163233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1852 00:51:40.164092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1854 00:51:40.256229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1855 00:51:40.257064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1857 00:51:40.349802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1858 00:51:40.350979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1860 00:51:40.451337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1861 00:51:40.452463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1863 00:51:40.543982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1864 00:51:40.545044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1866 00:51:40.637342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1867 00:51:40.638207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1869 00:51:40.731698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1870 00:51:40.732542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1872 00:51:40.825507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1873 00:51:40.826653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1875 00:51:40.917782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1876 00:51:40.918977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1878 00:51:41.011112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1879 00:51:41.012189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1881 00:51:41.104543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1882 00:51:41.105594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1884 00:51:41.201730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1885 00:51:41.202728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1887 00:51:41.295415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1888 00:51:41.296274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1890 00:51:41.390832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1891 00:51:41.391721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1893 00:51:41.484861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1894 00:51:41.485768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1896 00:51:41.576384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1897 00:51:41.577240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1899 00:51:41.669375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1900 00:51:41.670228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1902 00:51:41.763853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1903 00:51:41.764696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1905 00:51:41.856433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1906 00:51:41.857514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1908 00:51:41.949490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1909 00:51:41.951868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1911 00:51:42.041703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1912 00:51:42.042576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1914 00:51:42.134114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1915 00:51:42.135205 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1917 00:51:42.231293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1918 00:51:42.232219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1920 00:51:42.328269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1921 00:51:42.329100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1923 00:51:42.423425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1924 00:51:42.424277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1926 00:51:42.519217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1927 00:51:42.520100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1929 00:51:42.614712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1930 00:51:42.615595 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1932 00:51:42.707899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1933 00:51:42.708763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1935 00:51:42.800466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1936 00:51:42.801331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1938 00:51:42.891867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1940 00:51:42.894988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1941 00:51:42.984125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1943 00:51:42.987202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1944 00:51:43.075744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1946 00:51:43.078882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1947 00:51:43.169913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1948 00:51:43.170717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1950 00:51:43.262697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1951 00:51:43.263555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1953 00:51:43.353859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1954 00:51:43.354696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1956 00:51:43.447872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1957 00:51:43.448700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1959 00:51:43.540743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1960 00:51:43.541569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1962 00:51:43.634848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1963 00:51:43.635689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1965 00:51:43.727161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1966 00:51:43.728004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1968 00:51:43.821915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1969 00:51:43.822857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1971 00:51:43.914208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1972 00:51:43.915189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1974 00:51:44.007480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1975 00:51:44.008797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1977 00:51:44.099971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1978 00:51:44.101278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1980 00:51:44.194876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1981 00:51:44.195821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1983 00:51:44.286772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1984 00:51:44.287727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1986 00:51:44.390352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1987 00:51:44.391442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1989 00:51:44.491940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1990 00:51:44.492859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1992 00:51:44.589369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1993 00:51:44.590493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
1995 00:51:44.682453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1996 00:51:44.683393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
1998 00:51:44.776126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
1999 00:51:44.777361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2001 00:51:44.877918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2002 00:51:44.878878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2004 00:51:44.973419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2005 00:51:44.974228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2007 00:51:45.063252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2008 00:51:45.064253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2010 00:51:45.152300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2011 00:51:45.153376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2013 00:51:45.245885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2014 00:51:45.246985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2016 00:51:45.337874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2017 00:51:45.338852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2019 00:51:45.431940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2020 00:51:45.432949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2022 00:51:45.527120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2023 00:51:45.527772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2025 00:51:45.620008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2026 00:51:45.620716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2028 00:51:45.712212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2029 00:51:45.713479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2031 00:51:45.804927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2032 00:51:45.805633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2034 00:51:45.899555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2035 00:51:45.900427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2037 00:51:45.990586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2038 00:51:45.991406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2040 00:51:46.081055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2041 00:51:46.081925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2043 00:51:46.177356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2044 00:51:46.178200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2046 00:51:46.277867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2047 00:51:46.278725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2049 00:51:46.373792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2050 00:51:46.374710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2052 00:51:46.473519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2053 00:51:46.474434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2055 00:51:46.583185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2056 00:51:46.584075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2058 00:51:46.688420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2059 00:51:46.689266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2061 00:51:46.791341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2062 00:51:46.792279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2064 00:51:46.892924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2065 00:51:46.893788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2067 00:51:46.997370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2068 00:51:46.998399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2070 00:51:47.105747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2071 00:51:47.106832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2073 00:51:47.209333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2074 00:51:47.210247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2076 00:51:47.311825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2077 00:51:47.312817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2079 00:51:47.423786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2080 00:51:47.424698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2082 00:51:47.527705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2083 00:51:47.528682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2085 00:51:47.622299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2086 00:51:47.623568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2088 00:51:47.715966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2089 00:51:47.716952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2091 00:51:47.808736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2092 00:51:47.809693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2094 00:51:47.902743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2095 00:51:47.903692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2097 00:51:47.994356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2098 00:51:47.995169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2100 00:51:48.090165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2101 00:51:48.090850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2103 00:51:48.180799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2104 00:51:48.181482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2106 00:51:48.276029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2107 00:51:48.276706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2109 00:51:48.372790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2110 00:51:48.374104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2112 00:51:48.464416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2113 00:51:48.465681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2115 00:51:48.559923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2116 00:51:48.560824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2118 00:51:48.654447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2119 00:51:48.655330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2121 00:51:48.745355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2122 00:51:48.746322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2124 00:51:48.833865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2125 00:51:48.835193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2127 00:51:48.922153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2128 00:51:48.923108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2130 00:51:49.012593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2131 00:51:49.013470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2133 00:51:49.107596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2134 00:51:49.108233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2136 00:51:49.200611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2137 00:51:49.201234 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2139 00:51:49.294082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2140 00:51:49.295347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2142 00:51:49.386937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2143 00:51:49.388021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2145 00:51:49.482286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2146 00:51:49.483209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2148 00:51:49.574364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2149 00:51:49.575340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2151 00:51:49.668762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2152 00:51:49.669945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2154 00:51:49.761875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2155 00:51:49.762785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2157 00:51:49.853182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2158 00:51:49.854095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2160 00:51:49.946683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2161 00:51:49.947578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2163 00:51:50.040790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2164 00:51:50.041766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2166 00:51:50.135761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2167 00:51:50.136682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2169 00:51:50.230237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2170 00:51:50.231206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2172 00:51:50.319803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2173 00:51:50.320732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2175 00:51:50.413121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2176 00:51:50.414124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2178 00:51:50.507826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2179 00:51:50.508786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2181 00:51:50.598817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2182 00:51:50.599733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2184 00:51:50.690869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2185 00:51:50.691786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2187 00:51:50.785073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2188 00:51:50.785723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2190 00:51:50.879506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2191 00:51:50.880507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2193 00:51:50.971673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2194 00:51:50.972564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2196 00:51:51.063196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2197 00:51:51.064101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2199 00:51:51.161165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2200 00:51:51.162131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2202 00:51:51.252740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2203 00:51:51.253359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2205 00:51:51.339164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2206 00:51:51.339786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2208 00:51:51.432627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2209 00:51:51.433259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2211 00:51:51.526434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2212 00:51:51.527086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2214 00:51:51.620572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2215 00:51:51.621224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2217 00:51:51.713237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2218 00:51:51.713877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2220 00:51:51.802158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2221 00:51:51.802790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2223 00:51:51.895015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2224 00:51:51.895667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2226 00:51:51.988425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2227 00:51:51.989043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2229 00:51:52.081900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2230 00:51:52.082497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2232 00:51:52.173345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2233 00:51:52.173954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2235 00:51:52.263290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2236 00:51:52.263883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2238 00:51:52.354865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2239 00:51:52.355489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2241 00:51:52.442192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2242 00:51:52.442793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2244 00:51:52.535463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2245 00:51:52.536089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2247 00:51:52.630257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2248 00:51:52.630885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2250 00:51:52.719457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2251 00:51:52.720082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2253 00:51:52.811212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2254 00:51:52.811862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2256 00:51:52.906375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2257 00:51:52.906969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2259 00:51:52.996989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2261 00:51:53.000046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2262 00:51:53.092182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2263 00:51:53.092825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2265 00:51:53.189591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2266 00:51:53.190225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2268 00:51:53.282298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2269 00:51:53.282945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2271 00:51:53.398573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2272 00:51:53.399308 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2274 00:51:53.489427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2275 00:51:53.490096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2277 00:51:53.580153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2278 00:51:53.580753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2280 00:51:53.671323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2281 00:51:53.671953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2283 00:51:53.763801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2284 00:51:53.764399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2286 00:51:53.858137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2287 00:51:53.858769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2289 00:51:53.948166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2290 00:51:53.948771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2292 00:51:54.040262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2293 00:51:54.040912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2295 00:51:54.131857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2296 00:51:54.132485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2298 00:51:54.225169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2299 00:51:54.225775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2301 00:51:54.317604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2302 00:51:54.318231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2304 00:51:54.411214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2305 00:51:54.411819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2307 00:51:54.504577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2308 00:51:54.505202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2310 00:51:54.597405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2311 00:51:54.598033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2313 00:51:54.689235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2314 00:51:54.690366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2316 00:51:54.775242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2317 00:51:54.776133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2319 00:51:54.867734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2320 00:51:54.868631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2322 00:51:54.962047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2323 00:51:54.963269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2325 00:51:55.057630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2326 00:51:55.058596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2328 00:51:55.149502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2329 00:51:55.150500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2331 00:51:55.243335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2332 00:51:55.244235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2334 00:51:55.335697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2335 00:51:55.336683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2337 00:51:55.429043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2338 00:51:55.429941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2340 00:51:55.519610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2341 00:51:55.520299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2343 00:51:55.615757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2344 00:51:55.616697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2346 00:51:55.710149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2347 00:51:55.711005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2349 00:51:55.801111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2350 00:51:55.801999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2352 00:51:55.884570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2353 00:51:55.885130 + set +x
2354 00:51:55.885871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2356 00:51:55.894039 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 956692_1.6.2.4.5>
2357 00:51:55.894550 <LAVA_TEST_RUNNER EXIT>
2358 00:51:55.895251 Received signal: <ENDRUN> 1_kselftest-dt 956692_1.6.2.4.5
2359 00:51:55.895742 Ending use of test pattern.
2360 00:51:55.896182 Ending test lava.1_kselftest-dt (956692_1.6.2.4.5), duration 86.38
2362 00:51:55.897869 ok: lava_test_shell seems to have completed
2363 00:51:55.911801 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2364 00:51:55.913928 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2365 00:51:55.914572 end: 3 lava-test-retry (duration 00:01:28) [common]
2366 00:51:55.915192 start: 4 finalize (timeout 00:05:27) [common]
2367 00:51:55.915808 start: 4.1 power-off (timeout 00:00:30) [common]
2368 00:51:55.916864 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2369 00:51:55.952691 >> OK - accepted request
2370 00:51:55.954567 Returned 0 in 0 seconds
2371 00:51:56.055863 end: 4.1 power-off (duration 00:00:00) [common]
2373 00:51:56.057775 start: 4.2 read-feedback (timeout 00:05:27) [common]
2374 00:51:56.059189 Listened to connection for namespace 'common' for up to 1s
2375 00:51:56.060168 Listened to connection for namespace 'common' for up to 1s
2376 00:51:57.058987 Finalising connection for namespace 'common'
2377 00:51:57.059778 Disconnecting from shell: Finalise
2378 00:51:57.060348 / #
2379 00:51:57.161336 end: 4.2 read-feedback (duration 00:00:01) [common]
2380 00:51:57.161888 end: 4 finalize (duration 00:00:01) [common]
2381 00:51:57.162297 Cleaning after the job
2382 00:51:57.162687 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956692/tftp-deploy-qg4u5umr/ramdisk
2383 00:51:57.167718 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956692/tftp-deploy-qg4u5umr/kernel
2384 00:51:57.171708 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956692/tftp-deploy-qg4u5umr/dtb
2385 00:51:57.172513 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956692/tftp-deploy-qg4u5umr/nfsrootfs
2386 00:51:57.213130 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956692/tftp-deploy-qg4u5umr/modules
2387 00:51:57.220428 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/956692
2388 00:52:01.530080 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/956692
2389 00:52:01.530657 Job finished correctly