Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 00:56:58.094991 lava-dispatcher, installed at version: 2024.01
2 00:56:58.095810 start: 0 validate
3 00:56:58.096306 Start time: 2024-11-08 00:56:58.096275+00:00 (UTC)
4 00:56:58.096865 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:56:58.097393 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 00:56:58.141101 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:56:58.141667 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-244-g80b3d72150d5%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 00:56:58.170521 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:56:58.171177 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-244-g80b3d72150d5%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 00:56:59.223665 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:56:59.224206 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-244-g80b3d72150d5%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 00:56:59.265416 validate duration: 1.17
14 00:56:59.266498 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:56:59.266829 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:56:59.267137 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:56:59.267750 Not decompressing ramdisk as can be used compressed.
18 00:56:59.268228 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 00:56:59.268508 saving as /var/lib/lava/dispatcher/tmp/956746/tftp-deploy-yzpteu8c/ramdisk/rootfs.cpio.gz
20 00:56:59.268810 total size: 8181887 (7 MB)
21 00:56:59.305019 progress 0 % (0 MB)
22 00:56:59.310996 progress 5 % (0 MB)
23 00:56:59.316908 progress 10 % (0 MB)
24 00:56:59.322912 progress 15 % (1 MB)
25 00:56:59.328653 progress 20 % (1 MB)
26 00:56:59.334479 progress 25 % (1 MB)
27 00:56:59.339910 progress 30 % (2 MB)
28 00:56:59.345840 progress 35 % (2 MB)
29 00:56:59.351261 progress 40 % (3 MB)
30 00:56:59.357384 progress 45 % (3 MB)
31 00:56:59.362832 progress 50 % (3 MB)
32 00:56:59.368636 progress 55 % (4 MB)
33 00:56:59.374016 progress 60 % (4 MB)
34 00:56:59.379877 progress 65 % (5 MB)
35 00:56:59.385236 progress 70 % (5 MB)
36 00:56:59.390720 progress 75 % (5 MB)
37 00:56:59.395763 progress 80 % (6 MB)
38 00:56:59.401255 progress 85 % (6 MB)
39 00:56:59.406446 progress 90 % (7 MB)
40 00:56:59.412101 progress 95 % (7 MB)
41 00:56:59.416904 progress 100 % (7 MB)
42 00:56:59.417590 7 MB downloaded in 0.15 s (52.45 MB/s)
43 00:56:59.418133 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:56:59.419004 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:56:59.419290 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:56:59.419556 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:56:59.420056 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm64/defconfig/gcc-12/kernel/Image
49 00:56:59.420305 saving as /var/lib/lava/dispatcher/tmp/956746/tftp-deploy-yzpteu8c/kernel/Image
50 00:56:59.420513 total size: 45713920 (43 MB)
51 00:56:59.420723 No compression specified
52 00:56:59.461300 progress 0 % (0 MB)
53 00:56:59.489661 progress 5 % (2 MB)
54 00:56:59.518432 progress 10 % (4 MB)
55 00:56:59.547109 progress 15 % (6 MB)
56 00:56:59.576199 progress 20 % (8 MB)
57 00:56:59.604532 progress 25 % (10 MB)
58 00:56:59.633361 progress 30 % (13 MB)
59 00:56:59.662105 progress 35 % (15 MB)
60 00:56:59.690508 progress 40 % (17 MB)
61 00:56:59.718854 progress 45 % (19 MB)
62 00:56:59.747094 progress 50 % (21 MB)
63 00:56:59.775786 progress 55 % (24 MB)
64 00:56:59.804560 progress 60 % (26 MB)
65 00:56:59.832809 progress 65 % (28 MB)
66 00:56:59.861479 progress 70 % (30 MB)
67 00:56:59.889886 progress 75 % (32 MB)
68 00:56:59.918517 progress 80 % (34 MB)
69 00:56:59.946555 progress 85 % (37 MB)
70 00:56:59.975149 progress 90 % (39 MB)
71 00:57:00.003767 progress 95 % (41 MB)
72 00:57:00.031673 progress 100 % (43 MB)
73 00:57:00.032222 43 MB downloaded in 0.61 s (71.27 MB/s)
74 00:57:00.032700 end: 1.2.1 http-download (duration 00:00:01) [common]
76 00:57:00.033500 end: 1.2 download-retry (duration 00:00:01) [common]
77 00:57:00.033775 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:57:00.034038 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:57:00.034588 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 00:57:00.034869 saving as /var/lib/lava/dispatcher/tmp/956746/tftp-deploy-yzpteu8c/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 00:57:00.035077 total size: 53209 (0 MB)
82 00:57:00.035285 No compression specified
83 00:57:00.075624 progress 61 % (0 MB)
84 00:57:00.076524 progress 100 % (0 MB)
85 00:57:00.077115 0 MB downloaded in 0.04 s (1.21 MB/s)
86 00:57:00.077599 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:57:00.078436 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:57:00.078714 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:57:00.078988 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:57:00.079459 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm64/defconfig/gcc-12/modules.tar.xz
92 00:57:00.079739 saving as /var/lib/lava/dispatcher/tmp/956746/tftp-deploy-yzpteu8c/modules/modules.tar
93 00:57:00.079956 total size: 11616160 (11 MB)
94 00:57:00.080204 Using unxz to decompress xz
95 00:57:00.115914 progress 0 % (0 MB)
96 00:57:00.185805 progress 5 % (0 MB)
97 00:57:00.262372 progress 10 % (1 MB)
98 00:57:00.358956 progress 15 % (1 MB)
99 00:57:00.450930 progress 20 % (2 MB)
100 00:57:00.532688 progress 25 % (2 MB)
101 00:57:00.609459 progress 30 % (3 MB)
102 00:57:00.689649 progress 35 % (3 MB)
103 00:57:00.763273 progress 40 % (4 MB)
104 00:57:00.840401 progress 45 % (5 MB)
105 00:57:00.925920 progress 50 % (5 MB)
106 00:57:01.004118 progress 55 % (6 MB)
107 00:57:01.090318 progress 60 % (6 MB)
108 00:57:01.172330 progress 65 % (7 MB)
109 00:57:01.253654 progress 70 % (7 MB)
110 00:57:01.332878 progress 75 % (8 MB)
111 00:57:01.417565 progress 80 % (8 MB)
112 00:57:01.498600 progress 85 % (9 MB)
113 00:57:01.582888 progress 90 % (10 MB)
114 00:57:01.657274 progress 95 % (10 MB)
115 00:57:01.735068 progress 100 % (11 MB)
116 00:57:01.747382 11 MB downloaded in 1.67 s (6.64 MB/s)
117 00:57:01.748102 end: 1.4.1 http-download (duration 00:00:02) [common]
119 00:57:01.749900 end: 1.4 download-retry (duration 00:00:02) [common]
120 00:57:01.750477 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 00:57:01.751044 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 00:57:01.751582 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:57:01.752160 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 00:57:01.753221 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj
125 00:57:01.754151 makedir: /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin
126 00:57:01.754842 makedir: /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/tests
127 00:57:01.755516 makedir: /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/results
128 00:57:01.756210 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-add-keys
129 00:57:01.757261 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-add-sources
130 00:57:01.758276 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-background-process-start
131 00:57:01.759293 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-background-process-stop
132 00:57:01.760399 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-common-functions
133 00:57:01.761476 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-echo-ipv4
134 00:57:01.762465 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-install-packages
135 00:57:01.763441 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-installed-packages
136 00:57:01.764443 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-os-build
137 00:57:01.765426 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-probe-channel
138 00:57:01.766398 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-probe-ip
139 00:57:01.767367 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-target-ip
140 00:57:01.768373 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-target-mac
141 00:57:01.769359 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-target-storage
142 00:57:01.770359 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-test-case
143 00:57:01.771337 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-test-event
144 00:57:01.772338 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-test-feedback
145 00:57:01.773324 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-test-raise
146 00:57:01.774300 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-test-reference
147 00:57:01.775270 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-test-runner
148 00:57:01.776288 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-test-set
149 00:57:01.777312 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-test-shell
150 00:57:01.778327 Updating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-install-packages (oe)
151 00:57:01.779386 Updating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/bin/lava-installed-packages (oe)
152 00:57:01.780328 Creating /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/environment
153 00:57:01.781132 LAVA metadata
154 00:57:01.781659 - LAVA_JOB_ID=956746
155 00:57:01.782129 - LAVA_DISPATCHER_IP=192.168.6.2
156 00:57:01.782859 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 00:57:01.784881 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 00:57:01.785511 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 00:57:01.785919 skipped lava-vland-overlay
160 00:57:01.786400 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 00:57:01.786898 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 00:57:01.787323 skipped lava-multinode-overlay
163 00:57:01.787802 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 00:57:01.788417 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 00:57:01.788910 Loading test definitions
166 00:57:01.789452 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 00:57:01.789888 Using /lava-956746 at stage 0
168 00:57:01.792140 uuid=956746_1.5.2.4.1 testdef=None
169 00:57:01.792479 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 00:57:01.792749 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 00:57:01.794614 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 00:57:01.795426 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 00:57:01.797816 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 00:57:01.798711 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 00:57:01.801010 runner path: /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/0/tests/0_dmesg test_uuid 956746_1.5.2.4.1
178 00:57:01.801638 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 00:57:01.802417 Creating lava-test-runner.conf files
181 00:57:01.802621 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/956746/lava-overlay-8hcl76fj/lava-956746/0 for stage 0
182 00:57:01.802970 - 0_dmesg
183 00:57:01.803329 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 00:57:01.803607 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 00:57:01.828185 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 00:57:01.828633 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 00:57:01.828896 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 00:57:01.829162 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 00:57:01.829425 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 00:57:02.908081 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 00:57:02.908573 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 00:57:02.908841 extracting modules file /var/lib/lava/dispatcher/tmp/956746/tftp-deploy-yzpteu8c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956746/extract-overlay-ramdisk-aqu7nx3s/ramdisk
193 00:57:04.227856 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 00:57:04.228375 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 00:57:04.228653 [common] Applying overlay /var/lib/lava/dispatcher/tmp/956746/compress-overlay-7ssaec_i/overlay-1.5.2.5.tar.gz to ramdisk
196 00:57:04.228867 [common] Applying overlay /var/lib/lava/dispatcher/tmp/956746/compress-overlay-7ssaec_i/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/956746/extract-overlay-ramdisk-aqu7nx3s/ramdisk
197 00:57:04.259176 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 00:57:04.259617 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 00:57:04.259886 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 00:57:04.260138 Converting downloaded kernel to a uImage
201 00:57:04.260443 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/956746/tftp-deploy-yzpteu8c/kernel/Image /var/lib/lava/dispatcher/tmp/956746/tftp-deploy-yzpteu8c/kernel/uImage
202 00:57:04.754658 output: Image Name:
203 00:57:04.755082 output: Created: Fri Nov 8 00:57:04 2024
204 00:57:04.755291 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 00:57:04.755493 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 00:57:04.755694 output: Load Address: 01080000
207 00:57:04.755890 output: Entry Point: 01080000
208 00:57:04.756131 output:
209 00:57:04.756468 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 00:57:04.756736 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 00:57:04.757006 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 00:57:04.757257 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 00:57:04.757511 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 00:57:04.757763 Building ramdisk /var/lib/lava/dispatcher/tmp/956746/extract-overlay-ramdisk-aqu7nx3s/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/956746/extract-overlay-ramdisk-aqu7nx3s/ramdisk
215 00:57:07.255545 >> 181575 blocks
216 00:57:15.668615 Adding RAMdisk u-boot header.
217 00:57:15.669048 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/956746/extract-overlay-ramdisk-aqu7nx3s/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/956746/extract-overlay-ramdisk-aqu7nx3s/ramdisk.cpio.gz.uboot
218 00:57:15.934283 output: Image Name:
219 00:57:15.934690 output: Created: Fri Nov 8 00:57:15 2024
220 00:57:15.934895 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 00:57:15.935097 output: Data Size: 26053117 Bytes = 25442.50 KiB = 24.85 MiB
222 00:57:15.935294 output: Load Address: 00000000
223 00:57:15.935489 output: Entry Point: 00000000
224 00:57:15.935680 output:
225 00:57:15.936415 rename /var/lib/lava/dispatcher/tmp/956746/extract-overlay-ramdisk-aqu7nx3s/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/956746/tftp-deploy-yzpteu8c/ramdisk/ramdisk.cpio.gz.uboot
226 00:57:15.937187 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 00:57:15.937772 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 00:57:15.938343 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 00:57:15.938836 No LXC device requested
230 00:57:15.939379 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 00:57:15.939948 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 00:57:15.940582 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 00:57:15.941080 Checking files for TFTP limit of 4294967296 bytes.
234 00:57:15.944017 end: 1 tftp-deploy (duration 00:00:17) [common]
235 00:57:15.944646 start: 2 uboot-action (timeout 00:05:00) [common]
236 00:57:15.945213 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 00:57:15.945757 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 00:57:15.946300 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 00:57:15.946872 Using kernel file from prepare-kernel: 956746/tftp-deploy-yzpteu8c/kernel/uImage
240 00:57:15.947543 substitutions:
241 00:57:15.948012 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 00:57:15.948459 - {DTB_ADDR}: 0x01070000
243 00:57:15.948894 - {DTB}: 956746/tftp-deploy-yzpteu8c/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 00:57:15.949329 - {INITRD}: 956746/tftp-deploy-yzpteu8c/ramdisk/ramdisk.cpio.gz.uboot
245 00:57:15.949762 - {KERNEL_ADDR}: 0x01080000
246 00:57:15.950189 - {KERNEL}: 956746/tftp-deploy-yzpteu8c/kernel/uImage
247 00:57:15.950616 - {LAVA_MAC}: None
248 00:57:15.951083 - {PRESEED_CONFIG}: None
249 00:57:15.951509 - {PRESEED_LOCAL}: None
250 00:57:15.951929 - {RAMDISK_ADDR}: 0x08000000
251 00:57:15.952461 - {RAMDISK}: 956746/tftp-deploy-yzpteu8c/ramdisk/ramdisk.cpio.gz.uboot
252 00:57:15.952895 - {ROOT_PART}: None
253 00:57:15.953323 - {ROOT}: None
254 00:57:15.953750 - {SERVER_IP}: 192.168.6.2
255 00:57:15.954181 - {TEE_ADDR}: 0x83000000
256 00:57:15.954610 - {TEE}: None
257 00:57:15.955035 Parsed boot commands:
258 00:57:15.955450 - setenv autoload no
259 00:57:15.955877 - setenv initrd_high 0xffffffff
260 00:57:15.956354 - setenv fdt_high 0xffffffff
261 00:57:15.956800 - dhcp
262 00:57:15.957225 - setenv serverip 192.168.6.2
263 00:57:15.957648 - tftpboot 0x01080000 956746/tftp-deploy-yzpteu8c/kernel/uImage
264 00:57:15.958073 - tftpboot 0x08000000 956746/tftp-deploy-yzpteu8c/ramdisk/ramdisk.cpio.gz.uboot
265 00:57:15.958497 - tftpboot 0x01070000 956746/tftp-deploy-yzpteu8c/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 00:57:15.958919 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 00:57:15.959351 - bootm 0x01080000 0x08000000 0x01070000
268 00:57:15.959893 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 00:57:15.961562 start: 2.3 connect-device (timeout 00:05:00) [common]
271 00:57:15.962050 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 00:57:15.976699 Setting prompt string to ['lava-test: # ']
273 00:57:15.978305 end: 2.3 connect-device (duration 00:00:00) [common]
274 00:57:15.978956 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 00:57:15.979539 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 00:57:15.980133 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 00:57:15.981364 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 00:57:16.017422 >> OK - accepted request
279 00:57:16.019515 Returned 0 in 0 seconds
280 00:57:16.120728 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 00:57:16.122427 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 00:57:16.123039 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 00:57:16.123579 Setting prompt string to ['Hit any key to stop autoboot']
285 00:57:16.124110 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 00:57:16.125819 Trying 192.168.56.21...
287 00:57:16.126325 Connected to conserv1.
288 00:57:16.126784 Escape character is '^]'.
289 00:57:16.127242
290 00:57:16.127701 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 00:57:16.128213
292 00:57:24.471153 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 00:57:24.471815 bl2_stage_init 0x01
294 00:57:24.472344 bl2_stage_init 0x81
295 00:57:24.476618 hw id: 0x0000 - pwm id 0x01
296 00:57:24.477118 bl2_stage_init 0xc1
297 00:57:24.482129 bl2_stage_init 0x02
298 00:57:24.482610
299 00:57:24.483046 L0:00000000
300 00:57:24.483482 L1:00000703
301 00:57:24.483905 L2:00008067
302 00:57:24.484372 L3:15000000
303 00:57:24.487679 S1:00000000
304 00:57:24.488180 B2:20282000
305 00:57:24.488611 B1:a0f83180
306 00:57:24.489039
307 00:57:24.489468 TE: 69021
308 00:57:24.489894
309 00:57:24.493342 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 00:57:24.493817
311 00:57:24.498889 Board ID = 1
312 00:57:24.499365 Set cpu clk to 24M
313 00:57:24.499797 Set clk81 to 24M
314 00:57:24.504544 Use GP1_pll as DSU clk.
315 00:57:24.505017 DSU clk: 1200 Mhz
316 00:57:24.505447 CPU clk: 1200 MHz
317 00:57:24.509992 Set clk81 to 166.6M
318 00:57:24.515674 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 00:57:24.516178 board id: 1
320 00:57:24.522965 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 00:57:24.533783 fw parse done
322 00:57:24.539743 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 00:57:24.582879 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 00:57:24.593932 PIEI prepare done
325 00:57:24.594397 fastboot data load
326 00:57:24.594834 fastboot data verify
327 00:57:24.599577 verify result: 266
328 00:57:24.605176 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 00:57:24.605643 LPDDR4 probe
330 00:57:24.606070 ddr clk to 1584MHz
331 00:57:24.613193 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 00:57:24.651006
333 00:57:24.651485 dmc_version 0001
334 00:57:24.658023 Check phy result
335 00:57:24.664049 INFO : End of CA training
336 00:57:24.664523 INFO : End of initialization
337 00:57:24.669600 INFO : Training has run successfully!
338 00:57:24.670061 Check phy result
339 00:57:24.675170 INFO : End of initialization
340 00:57:24.675622 INFO : End of read enable training
341 00:57:24.680800 INFO : End of fine write leveling
342 00:57:24.686371 INFO : End of Write leveling coarse delay
343 00:57:24.686826 INFO : Training has run successfully!
344 00:57:24.687259 Check phy result
345 00:57:24.691949 INFO : End of initialization
346 00:57:24.692433 INFO : End of read dq deskew training
347 00:57:24.697580 INFO : End of MPR read delay center optimization
348 00:57:24.703134 INFO : End of write delay center optimization
349 00:57:24.708747 INFO : End of read delay center optimization
350 00:57:24.709213 INFO : End of max read latency training
351 00:57:24.714312 INFO : Training has run successfully!
352 00:57:24.714776 1D training succeed
353 00:57:24.723625 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 00:57:24.772453 Check phy result
355 00:57:24.773077 INFO : End of initialization
356 00:57:24.799251 INFO : End of 2D read delay Voltage center optimization
357 00:57:24.823481 INFO : End of 2D read delay Voltage center optimization
358 00:57:24.880329 INFO : End of 2D write delay Voltage center optimization
359 00:57:24.934163 INFO : End of 2D write delay Voltage center optimization
360 00:57:24.939736 INFO : Training has run successfully!
361 00:57:24.940289
362 00:57:24.940760 channel==0
363 00:57:24.945376 RxClkDly_Margin_A0==88 ps 9
364 00:57:24.945859 TxDqDly_Margin_A0==98 ps 10
365 00:57:24.948683 RxClkDly_Margin_A1==88 ps 9
366 00:57:24.949148 TxDqDly_Margin_A1==98 ps 10
367 00:57:24.954421 TrainedVREFDQ_A0==74
368 00:57:24.954965 TrainedVREFDQ_A1==75
369 00:57:24.955441 VrefDac_Margin_A0==24
370 00:57:24.959937 DeviceVref_Margin_A0==40
371 00:57:24.960439 VrefDac_Margin_A1==23
372 00:57:24.965504 DeviceVref_Margin_A1==39
373 00:57:24.966109
374 00:57:24.966573
375 00:57:24.967030 channel==1
376 00:57:24.967477 RxClkDly_Margin_A0==78 ps 8
377 00:57:24.971057 TxDqDly_Margin_A0==98 ps 10
378 00:57:24.971577 RxClkDly_Margin_A1==78 ps 8
379 00:57:24.976605 TxDqDly_Margin_A1==78 ps 8
380 00:57:24.977120 TrainedVREFDQ_A0==78
381 00:57:24.977554 TrainedVREFDQ_A1==77
382 00:57:24.982243 VrefDac_Margin_A0==22
383 00:57:24.982742 DeviceVref_Margin_A0==36
384 00:57:24.987878 VrefDac_Margin_A1==22
385 00:57:24.988375 DeviceVref_Margin_A1==37
386 00:57:24.988806
387 00:57:24.993426 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 00:57:24.993888
389 00:57:25.021588 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000062
390 00:57:25.027075 2D training succeed
391 00:57:25.032604 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 00:57:25.033070 auto size-- 65535DDR cs0 size: 2048MB
393 00:57:25.038227 DDR cs1 size: 2048MB
394 00:57:25.038683 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 00:57:25.043856 cs0 DataBus test pass
396 00:57:25.044358 cs1 DataBus test pass
397 00:57:25.044787 cs0 AddrBus test pass
398 00:57:25.049444 cs1 AddrBus test pass
399 00:57:25.049898
400 00:57:25.050329 100bdlr_step_size ps== 485
401 00:57:25.050769 result report
402 00:57:25.055041 boot times 0Enable ddr reg access
403 00:57:25.062526 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 00:57:25.076303 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 00:57:25.735716 bl2z: ptr: 05129330, size: 00001e40
406 00:57:25.744914 0.0;M3 CHK:0;cm4_sp_mode 0
407 00:57:25.745533 MVN_1=0x00000000
408 00:57:25.745969 MVN_2=0x00000000
409 00:57:25.756404 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 00:57:25.757005 OPS=0x04
411 00:57:25.757446 ring efuse init
412 00:57:25.759351 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 00:57:25.765626 [0.017354 Inits done]
414 00:57:25.766192 secure task start!
415 00:57:25.766632 high task start!
416 00:57:25.767062 low task start!
417 00:57:25.769744 run into bl31
418 00:57:25.778634 NOTICE: BL31: v1.3(release):4fc40b1
419 00:57:25.786290 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 00:57:25.786788 NOTICE: BL31: G12A normal boot!
421 00:57:25.801980 NOTICE: BL31: BL33 decompress pass
422 00:57:25.809667 ERROR: Error initializing runtime service opteed_fast
423 00:57:27.019177 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 00:57:27.019815 bl2_stage_init 0x01
425 00:57:27.020341 bl2_stage_init 0x81
426 00:57:27.024716 hw id: 0x0000 - pwm id 0x01
427 00:57:27.025237 bl2_stage_init 0xc1
428 00:57:27.030234 bl2_stage_init 0x02
429 00:57:27.030781
430 00:57:27.031214 L0:00000000
431 00:57:27.031638 L1:00000703
432 00:57:27.032104 L2:00008067
433 00:57:27.032528 L3:15000000
434 00:57:27.035823 S1:00000000
435 00:57:27.036314 B2:20282000
436 00:57:27.036743 B1:a0f83180
437 00:57:27.037163
438 00:57:27.037583 TE: 67383
439 00:57:27.038005
440 00:57:27.041391 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 00:57:27.041846
442 00:57:27.046988 Board ID = 1
443 00:57:27.047435 Set cpu clk to 24M
444 00:57:27.047860 Set clk81 to 24M
445 00:57:27.052613 Use GP1_pll as DSU clk.
446 00:57:27.053061 DSU clk: 1200 Mhz
447 00:57:27.053483 CPU clk: 1200 MHz
448 00:57:27.058203 Set clk81 to 166.6M
449 00:57:27.063810 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 00:57:27.064313 board id: 1
451 00:57:27.070997 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 00:57:27.081806 fw parse done
453 00:57:27.087640 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 00:57:27.130311 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 00:57:27.141180 PIEI prepare done
456 00:57:27.141669 fastboot data load
457 00:57:27.142098 fastboot data verify
458 00:57:27.146858 verify result: 266
459 00:57:27.152411 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 00:57:27.152870 LPDDR4 probe
461 00:57:27.153293 ddr clk to 1584MHz
462 00:57:28.518992 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 00:57:28.519674 bl2_stage_init 0x01
464 00:57:28.520198 bl2_stage_init 0x81
465 00:57:28.524431 hw id: 0x0000 - pwm id 0x01
466 00:57:28.524919 bl2_stage_init 0xc1
467 00:57:28.529789 bl2_stage_init 0x02
468 00:57:28.530271
469 00:57:28.530721 L0:00000000
470 00:57:28.531161 L1:00000703
471 00:57:28.531603 L2:00008067
472 00:57:28.532073 L3:15000000
473 00:57:28.535393 S1:00000000
474 00:57:28.535872 B2:20282000
475 00:57:28.536357 B1:a0f83180
476 00:57:28.536794
477 00:57:28.537230 TE: 68410
478 00:57:28.537664
479 00:57:28.541038 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 00:57:28.541523
481 00:57:28.546542 Board ID = 1
482 00:57:28.547010 Set cpu clk to 24M
483 00:57:28.547453 Set clk81 to 24M
484 00:57:28.552195 Use GP1_pll as DSU clk.
485 00:57:28.552722 DSU clk: 1200 Mhz
486 00:57:28.553172 CPU clk: 1200 MHz
487 00:57:28.557767 Set clk81 to 166.6M
488 00:57:28.563379 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 00:57:28.563856 board id: 1
490 00:57:28.570873 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 00:57:28.581498 fw parse done
492 00:57:28.587459 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 00:57:28.630106 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 00:57:28.641059 PIEI prepare done
495 00:57:28.641524 fastboot data load
496 00:57:28.641970 fastboot data verify
497 00:57:28.646587 verify result: 266
498 00:57:28.652221 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 00:57:28.652694 LPDDR4 probe
500 00:57:28.653139 ddr clk to 1584MHz
501 00:57:28.660199 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 00:57:28.697416
503 00:57:28.697903 dmc_version 0001
504 00:57:28.704166 Check phy result
505 00:57:28.710047 INFO : End of CA training
506 00:57:28.710506 INFO : End of initialization
507 00:57:28.715638 INFO : Training has run successfully!
508 00:57:28.716150 Check phy result
509 00:57:28.721280 INFO : End of initialization
510 00:57:28.721747 INFO : End of read enable training
511 00:57:28.726913 INFO : End of fine write leveling
512 00:57:28.732444 INFO : End of Write leveling coarse delay
513 00:57:28.732912 INFO : Training has run successfully!
514 00:57:28.733355 Check phy result
515 00:57:28.738066 INFO : End of initialization
516 00:57:28.738531 INFO : End of read dq deskew training
517 00:57:28.743620 INFO : End of MPR read delay center optimization
518 00:57:28.749231 INFO : End of write delay center optimization
519 00:57:28.754867 INFO : End of read delay center optimization
520 00:57:28.755336 INFO : End of max read latency training
521 00:57:28.760447 INFO : Training has run successfully!
522 00:57:28.760910 1D training succeed
523 00:57:28.769626 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 00:57:28.817216 Check phy result
525 00:57:28.817693 INFO : End of initialization
526 00:57:28.839549 INFO : End of 2D read delay Voltage center optimization
527 00:57:28.858768 INFO : End of 2D read delay Voltage center optimization
528 00:57:28.909618 INFO : End of 2D write delay Voltage center optimization
529 00:57:28.959859 INFO : End of 2D write delay Voltage center optimization
530 00:57:28.965394 INFO : Training has run successfully!
531 00:57:28.965855
532 00:57:28.966298 channel==0
533 00:57:28.971093 RxClkDly_Margin_A0==88 ps 9
534 00:57:28.971568 TxDqDly_Margin_A0==88 ps 9
535 00:57:28.976588 RxClkDly_Margin_A1==88 ps 9
536 00:57:28.977051 TxDqDly_Margin_A1==98 ps 10
537 00:57:28.977492 TrainedVREFDQ_A0==74
538 00:57:28.982171 TrainedVREFDQ_A1==74
539 00:57:28.982633 VrefDac_Margin_A0==24
540 00:57:28.983072 DeviceVref_Margin_A0==40
541 00:57:28.987861 VrefDac_Margin_A1==23
542 00:57:28.988374 DeviceVref_Margin_A1==40
543 00:57:28.988826
544 00:57:28.989265
545 00:57:28.989701 channel==1
546 00:57:28.993375 RxClkDly_Margin_A0==78 ps 8
547 00:57:28.993838 TxDqDly_Margin_A0==98 ps 10
548 00:57:28.999069 RxClkDly_Margin_A1==88 ps 9
549 00:57:28.999529 TxDqDly_Margin_A1==88 ps 9
550 00:57:29.004589 TrainedVREFDQ_A0==78
551 00:57:29.005060 TrainedVREFDQ_A1==78
552 00:57:29.005502 VrefDac_Margin_A0==22
553 00:57:29.010185 DeviceVref_Margin_A0==36
554 00:57:29.010661 VrefDac_Margin_A1==21
555 00:57:29.015874 DeviceVref_Margin_A1==36
556 00:57:29.016372
557 00:57:29.016809 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 00:57:29.017246
559 00:57:29.049376 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
560 00:57:29.049927 2D training succeed
561 00:57:29.055108 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 00:57:29.060566 auto size-- 65535DDR cs0 size: 2048MB
563 00:57:29.061041 DDR cs1 size: 2048MB
564 00:57:29.066162 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 00:57:29.066636 cs0 DataBus test pass
566 00:57:29.071767 cs1 DataBus test pass
567 00:57:29.072297 cs0 AddrBus test pass
568 00:57:29.072742 cs1 AddrBus test pass
569 00:57:29.073181
570 00:57:29.077391 100bdlr_step_size ps== 464
571 00:57:29.077882 result report
572 00:57:29.083136 boot times 0Enable ddr reg access
573 00:57:29.088215 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 00:57:29.101988 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 00:57:29.756364 bl2z: ptr: 05129330, size: 00001e40
576 00:57:29.762992 0.0;M3 CHK:0;cm4_sp_mode 0
577 00:57:29.763563 MVN_1=0x00000000
578 00:57:29.764093 MVN_2=0x00000000
579 00:57:29.774385 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 00:57:29.774928 OPS=0x04
581 00:57:29.775384 ring efuse init
582 00:57:29.779974 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 00:57:29.780565 [0.017320 Inits done]
584 00:57:29.781022 secure task start!
585 00:57:29.787642 high task start!
586 00:57:29.788220 low task start!
587 00:57:29.788677 run into bl31
588 00:57:29.796226 NOTICE: BL31: v1.3(release):4fc40b1
589 00:57:29.803971 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 00:57:29.804300 NOTICE: BL31: G12A normal boot!
591 00:57:29.819520 NOTICE: BL31: BL33 decompress pass
592 00:57:29.825415 ERROR: Error initializing runtime service opteed_fast
593 00:57:31.075874 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 00:57:31.076341 bl2_stage_init 0x01
595 00:57:31.076569 bl2_stage_init 0x81
596 00:57:31.081429 hw id: 0x0000 - pwm id 0x01
597 00:57:31.081891 bl2_stage_init 0xc1
598 00:57:31.085946 bl2_stage_init 0x02
599 00:57:31.086364
600 00:57:31.086730 L0:00000000
601 00:57:31.086971 L1:00000703
602 00:57:31.087188 L2:00008067
603 00:57:31.091595 L3:15000000
604 00:57:31.092085 S1:00000000
605 00:57:31.092445 B2:20282000
606 00:57:31.092750 B1:a0f83180
607 00:57:31.093047
608 00:57:31.093342 TE: 73698
609 00:57:31.093564
610 00:57:31.102674 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 00:57:31.103040
612 00:57:31.103266 Board ID = 1
613 00:57:31.103480 Set cpu clk to 24M
614 00:57:31.103693 Set clk81 to 24M
615 00:57:31.108426 Use GP1_pll as DSU clk.
616 00:57:31.108784 DSU clk: 1200 Mhz
617 00:57:31.109043 CPU clk: 1200 MHz
618 00:57:31.113963 Set clk81 to 166.6M
619 00:57:31.119647 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 00:57:31.120024 board id: 1
621 00:57:31.127684 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 00:57:31.138381 fw parse done
623 00:57:31.144292 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 00:57:31.186951 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 00:57:31.197954 PIEI prepare done
626 00:57:31.198306 fastboot data load
627 00:57:31.198551 fastboot data verify
628 00:57:31.203483 verify result: 266
629 00:57:31.209082 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 00:57:31.209425 LPDDR4 probe
631 00:57:31.209661 ddr clk to 1584MHz
632 00:57:31.217111 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 00:57:31.254396
634 00:57:31.254778 dmc_version 0001
635 00:57:31.261072 Check phy result
636 00:57:31.266943 INFO : End of CA training
637 00:57:31.267279 INFO : End of initialization
638 00:57:31.272555 INFO : Training has run successfully!
639 00:57:31.273015 Check phy result
640 00:57:31.278167 INFO : End of initialization
641 00:57:31.278665 INFO : End of read enable training
642 00:57:31.281565 INFO : End of fine write leveling
643 00:57:31.287133 INFO : End of Write leveling coarse delay
644 00:57:31.292649 INFO : Training has run successfully!
645 00:57:31.292983 Check phy result
646 00:57:31.293214 INFO : End of initialization
647 00:57:31.298291 INFO : End of read dq deskew training
648 00:57:31.301753 INFO : End of MPR read delay center optimization
649 00:57:31.307288 INFO : End of write delay center optimization
650 00:57:31.312874 INFO : End of read delay center optimization
651 00:57:31.313230 INFO : End of max read latency training
652 00:57:31.318510 INFO : Training has run successfully!
653 00:57:31.319012 1D training succeed
654 00:57:31.326571 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 00:57:31.374054 Check phy result
656 00:57:31.374427 INFO : End of initialization
657 00:57:31.396418 INFO : End of 2D read delay Voltage center optimization
658 00:57:31.415650 INFO : End of 2D read delay Voltage center optimization
659 00:57:31.466625 INFO : End of 2D write delay Voltage center optimization
660 00:57:31.516711 INFO : End of 2D write delay Voltage center optimization
661 00:57:31.522237 INFO : Training has run successfully!
662 00:57:31.522732
663 00:57:31.522994 channel==0
664 00:57:31.527811 RxClkDly_Margin_A0==88 ps 9
665 00:57:31.528185 TxDqDly_Margin_A0==88 ps 9
666 00:57:31.533485 RxClkDly_Margin_A1==69 ps 7
667 00:57:31.533954 TxDqDly_Margin_A1==88 ps 9
668 00:57:31.534312 TrainedVREFDQ_A0==74
669 00:57:31.539047 TrainedVREFDQ_A1==74
670 00:57:31.539397 VrefDac_Margin_A0==24
671 00:57:31.539612 DeviceVref_Margin_A0==40
672 00:57:31.544635 VrefDac_Margin_A1==22
673 00:57:31.545115 DeviceVref_Margin_A1==40
674 00:57:31.545496
675 00:57:31.545853
676 00:57:31.546117 channel==1
677 00:57:31.550255 RxClkDly_Margin_A0==88 ps 9
678 00:57:31.550715 TxDqDly_Margin_A0==98 ps 10
679 00:57:31.555817 RxClkDly_Margin_A1==78 ps 8
680 00:57:31.556177 TxDqDly_Margin_A1==78 ps 8
681 00:57:31.561503 TrainedVREFDQ_A0==78
682 00:57:31.561987 TrainedVREFDQ_A1==75
683 00:57:31.562341 VrefDac_Margin_A0==22
684 00:57:31.566998 DeviceVref_Margin_A0==36
685 00:57:31.567326 VrefDac_Margin_A1==22
686 00:57:31.567539 DeviceVref_Margin_A1==39
687 00:57:31.572678
688 00:57:31.573039 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 00:57:31.573264
690 00:57:31.606132 soc_vref_reg_value 0x 00000019 00000018 00000017 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000016 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
691 00:57:31.606702 2D training succeed
692 00:57:31.611811 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 00:57:31.617489 auto size-- 65535DDR cs0 size: 2048MB
694 00:57:31.617826 DDR cs1 size: 2048MB
695 00:57:31.622962 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 00:57:31.623405 cs0 DataBus test pass
697 00:57:31.628583 cs1 DataBus test pass
698 00:57:31.628899 cs0 AddrBus test pass
699 00:57:31.629105 cs1 AddrBus test pass
700 00:57:31.629301
701 00:57:31.634257 100bdlr_step_size ps== 478
702 00:57:31.634809 result report
703 00:57:31.639794 boot times 0Enable ddr reg access
704 00:57:31.644870 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 00:57:31.658676 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 00:57:32.313199 bl2z: ptr: 05129330, size: 00001e40
707 00:57:32.321624 0.0;M3 CHK:0;cm4_sp_mode 0
708 00:57:32.322209 MVN_1=0x00000000
709 00:57:32.322626 MVN_2=0x00000000
710 00:57:32.332784 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 00:57:32.333365 OPS=0x04
712 00:57:32.333785 ring efuse init
713 00:57:32.338546 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 00:57:32.339068 [0.017310 Inits done]
715 00:57:32.339466 secure task start!
716 00:57:32.345869 high task start!
717 00:57:32.346359 low task start!
718 00:57:32.346749 run into bl31
719 00:57:32.354600 NOTICE: BL31: v1.3(release):4fc40b1
720 00:57:32.362422 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 00:57:32.362956 NOTICE: BL31: G12A normal boot!
722 00:57:32.377914 NOTICE: BL31: BL33 decompress pass
723 00:57:32.383725 ERROR: Error initializing runtime service opteed_fast
724 00:57:33.178990
725 00:57:33.179588
726 00:57:33.184430 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 00:57:33.184925
728 00:57:33.187898 Model: Libre Computer AML-S905D3-CC Solitude
729 00:57:33.334938 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 00:57:33.350345 DRAM: 2 GiB (effective 3.8 GiB)
731 00:57:33.451371 Core: 406 devices, 33 uclasses, devicetree: separate
732 00:57:33.456691 WDT: Not starting watchdog@f0d0
733 00:57:33.482197 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 00:57:33.494481 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 00:57:33.499442 ** Bad device specification mmc 0 **
736 00:57:33.509481 Card did not respond to voltage select! : -110
737 00:57:33.516870 ** Bad device specification mmc 0 **
738 00:57:33.517219 Couldn't find partition mmc 0
739 00:57:33.525432 Card did not respond to voltage select! : -110
740 00:57:33.530953 ** Bad device specification mmc 0 **
741 00:57:33.531425 Couldn't find partition mmc 0
742 00:57:33.536039 Error: could not access storage.
743 00:57:33.832425 Net: eth0: ethernet@ff3f0000
744 00:57:33.833013 starting USB...
745 00:57:34.077116 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 00:57:34.077678 Starting the controller
747 00:57:34.084092 USB XHCI 1.10
748 00:57:35.638276 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 00:57:35.646545 scanning usb for storage devices... 0 Storage Device(s) found
751 00:57:35.698269 Hit any key to stop autoboot: 1
752 00:57:35.699539 end: 2.4.2 bootloader-interrupt (duration 00:00:20) [common]
753 00:57:35.700259 start: 2.4.3 bootloader-commands (timeout 00:04:40) [common]
754 00:57:35.700763 Setting prompt string to ['=>']
755 00:57:35.701242 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:40)
756 00:57:35.712572 0
757 00:57:35.713568 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 00:57:35.814520 => setenv autoload no
760 00:57:35.815301 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
761 00:57:35.820412 setenv autoload no
763 00:57:35.922006 => setenv initrd_high 0xffffffff
764 00:57:35.922791 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
765 00:57:35.927213 setenv initrd_high 0xffffffff
767 00:57:36.028856 => setenv fdt_high 0xffffffff
768 00:57:36.029444 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
769 00:57:36.034075 setenv fdt_high 0xffffffff
771 00:57:36.135703 => dhcp
772 00:57:36.136550 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
773 00:57:36.140379 dhcp
774 00:57:36.696050 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
775 00:57:36.696659 Speed: 1000, full duplex
776 00:57:36.697080 BOOTP broadcast 1
777 00:57:36.943892 BOOTP broadcast 2
778 00:57:36.964088 DHCP client bound to address 192.168.6.21 (268 ms)
780 00:57:37.065581 => setenv serverip 192.168.6.2
781 00:57:37.066271 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
782 00:57:37.070962 setenv serverip 192.168.6.2
784 00:57:37.172423 => tftpboot 0x01080000 956746/tftp-deploy-yzpteu8c/kernel/uImage
785 00:57:37.173078 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
786 00:57:37.179832 tftpboot 0x01080000 956746/tftp-deploy-yzpteu8c/kernel/uImage
787 00:57:37.180354 Speed: 1000, full duplex
788 00:57:37.180769 Using ethernet@ff3f0000 device
789 00:57:37.185377 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
790 00:57:37.190815 Filename '956746/tftp-deploy-yzpteu8c/kernel/uImage'.
791 00:57:37.194786 Load address: 0x1080000
792 00:57:39.980236 Loading: *################################################## 43.6 MiB
793 00:57:39.980806 15.6 MiB/s
794 00:57:39.981051 done
795 00:57:39.985030 Bytes transferred = 45713984 (2b98a40 hex)
797 00:57:40.086389 => tftpboot 0x08000000 956746/tftp-deploy-yzpteu8c/ramdisk/ramdisk.cpio.gz.uboot
798 00:57:40.087010 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
799 00:57:40.093815 tftpboot 0x08000000 956746/tftp-deploy-yzpteu8c/ramdisk/ramdisk.cpio.gz.uboot
800 00:57:40.094185 Speed: 1000, full duplex
801 00:57:40.094418 Using ethernet@ff3f0000 device
802 00:57:40.099276 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
803 00:57:40.109150 Filename '956746/tftp-deploy-yzpteu8c/ramdisk/ramdisk.cpio.gz.uboot'.
804 00:57:40.109504 Load address: 0x8000000
805 00:57:41.686883 Loading: *################################################# UDP wrong checksum 00000005 0000f79a
806 00:57:44.500807 UDP wrong checksum 000000ff 000018ff
807 00:57:44.542310 UDP wrong checksum 000000ff 0000abf1
808 00:57:46.688022 T UDP wrong checksum 00000005 0000f79a
809 00:57:56.689652 T T UDP wrong checksum 00000005 0000f79a
810 00:58:16.693879 T T T T UDP wrong checksum 00000005 0000f79a
811 00:58:36.698864 T T T
812 00:58:36.699489 Retry count exceeded; starting again
814 00:58:36.700933 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
817 00:58:36.702786 end: 2.4 uboot-commands (duration 00:01:21) [common]
819 00:58:36.704266 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
821 00:58:36.705367 end: 2 uboot-action (duration 00:01:21) [common]
823 00:58:36.706953 Cleaning after the job
824 00:58:36.707509 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956746/tftp-deploy-yzpteu8c/ramdisk
825 00:58:36.708859 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956746/tftp-deploy-yzpteu8c/kernel
826 00:58:36.753274 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956746/tftp-deploy-yzpteu8c/dtb
827 00:58:36.754051 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956746/tftp-deploy-yzpteu8c/modules
828 00:58:36.772420 start: 4.1 power-off (timeout 00:00:30) [common]
829 00:58:36.773078 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
830 00:58:36.806239 >> OK - accepted request
831 00:58:36.808416 Returned 0 in 0 seconds
832 00:58:36.909604 end: 4.1 power-off (duration 00:00:00) [common]
834 00:58:36.911328 start: 4.2 read-feedback (timeout 00:10:00) [common]
835 00:58:36.912530 Listened to connection for namespace 'common' for up to 1s
836 00:58:37.912690 Finalising connection for namespace 'common'
837 00:58:37.913435 Disconnecting from shell: Finalise
838 00:58:37.913967 =>
839 00:58:38.015055 end: 4.2 read-feedback (duration 00:00:01) [common]
840 00:58:38.015753 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/956746
841 00:58:38.314765 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/956746
842 00:58:38.315394 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.