Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 6
- Errors: 0
- Boot result: PASS
- Kernel Errors: 5
1 02:22:00.837718 lava-dispatcher, installed at version: 2024.01
2 02:22:00.838526 start: 0 validate
3 02:22:00.838994 Start time: 2024-11-08 02:22:00.838964+00:00 (UTC)
4 02:22:00.839536 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:22:00.840096 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:22:00.881819 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:22:00.882495 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-244-g80b3d72150d5%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:22:00.915058 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:22:00.915671 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-244-g80b3d72150d5%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:22:00.945853 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:22:00.946354 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:22:00.977618 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:22:00.978109 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-244-g80b3d72150d5%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 02:22:01.014966 validate duration: 0.18
16 02:22:01.015856 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:22:01.016240 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:22:01.016593 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:22:01.017190 Not decompressing ramdisk as can be used compressed.
20 02:22:01.017668 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 02:22:01.017970 saving as /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/ramdisk/initrd.cpio.gz
22 02:22:01.018247 total size: 5628169 (5 MB)
23 02:22:01.054485 progress 0 % (0 MB)
24 02:22:01.060363 progress 5 % (0 MB)
25 02:22:01.064503 progress 10 % (0 MB)
26 02:22:01.068130 progress 15 % (0 MB)
27 02:22:01.072030 progress 20 % (1 MB)
28 02:22:01.075542 progress 25 % (1 MB)
29 02:22:01.079417 progress 30 % (1 MB)
30 02:22:01.083443 progress 35 % (1 MB)
31 02:22:01.086999 progress 40 % (2 MB)
32 02:22:01.090891 progress 45 % (2 MB)
33 02:22:01.094425 progress 50 % (2 MB)
34 02:22:01.098315 progress 55 % (2 MB)
35 02:22:01.102174 progress 60 % (3 MB)
36 02:22:01.105696 progress 65 % (3 MB)
37 02:22:01.109552 progress 70 % (3 MB)
38 02:22:01.112886 progress 75 % (4 MB)
39 02:22:01.116595 progress 80 % (4 MB)
40 02:22:01.119876 progress 85 % (4 MB)
41 02:22:01.123618 progress 90 % (4 MB)
42 02:22:01.127215 progress 95 % (5 MB)
43 02:22:01.130516 progress 100 % (5 MB)
44 02:22:01.131169 5 MB downloaded in 0.11 s (47.54 MB/s)
45 02:22:01.131736 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:22:01.132698 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:22:01.133010 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:22:01.133295 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:22:01.133775 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm64/defconfig/gcc-12/kernel/Image
51 02:22:01.134030 saving as /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/kernel/Image
52 02:22:01.134249 total size: 45713920 (43 MB)
53 02:22:01.134466 No compression specified
54 02:22:01.169947 progress 0 % (0 MB)
55 02:22:01.197617 progress 5 % (2 MB)
56 02:22:01.225404 progress 10 % (4 MB)
57 02:22:01.253162 progress 15 % (6 MB)
58 02:22:01.280921 progress 20 % (8 MB)
59 02:22:01.308467 progress 25 % (10 MB)
60 02:22:01.336456 progress 30 % (13 MB)
61 02:22:01.364396 progress 35 % (15 MB)
62 02:22:01.392671 progress 40 % (17 MB)
63 02:22:01.419767 progress 45 % (19 MB)
64 02:22:01.447524 progress 50 % (21 MB)
65 02:22:01.475112 progress 55 % (24 MB)
66 02:22:01.502828 progress 60 % (26 MB)
67 02:22:01.530620 progress 65 % (28 MB)
68 02:22:01.559021 progress 70 % (30 MB)
69 02:22:01.587275 progress 75 % (32 MB)
70 02:22:01.615315 progress 80 % (34 MB)
71 02:22:01.642607 progress 85 % (37 MB)
72 02:22:01.670170 progress 90 % (39 MB)
73 02:22:01.697526 progress 95 % (41 MB)
74 02:22:01.723801 progress 100 % (43 MB)
75 02:22:01.724367 43 MB downloaded in 0.59 s (73.88 MB/s)
76 02:22:01.724884 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:22:01.725755 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:22:01.726054 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:22:01.726336 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:22:01.726815 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 02:22:01.727091 saving as /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/dtb/meson-g12b-a311d-libretech-cc.dtb
83 02:22:01.727307 total size: 54703 (0 MB)
84 02:22:01.727522 No compression specified
85 02:22:01.763766 progress 59 % (0 MB)
86 02:22:01.764649 progress 100 % (0 MB)
87 02:22:01.765228 0 MB downloaded in 0.04 s (1.38 MB/s)
88 02:22:01.765722 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:22:01.766567 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:22:01.766843 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:22:01.767121 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:22:01.767594 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 02:22:01.767850 saving as /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/nfsrootfs/full.rootfs.tar
95 02:22:01.768094 total size: 120894716 (115 MB)
96 02:22:01.768315 Using unxz to decompress xz
97 02:22:01.803251 progress 0 % (0 MB)
98 02:22:02.593626 progress 5 % (5 MB)
99 02:22:03.431900 progress 10 % (11 MB)
100 02:22:04.221471 progress 15 % (17 MB)
101 02:22:04.954579 progress 20 % (23 MB)
102 02:22:05.545908 progress 25 % (28 MB)
103 02:22:06.364080 progress 30 % (34 MB)
104 02:22:07.149422 progress 35 % (40 MB)
105 02:22:07.491587 progress 40 % (46 MB)
106 02:22:07.860165 progress 45 % (51 MB)
107 02:22:08.578476 progress 50 % (57 MB)
108 02:22:09.465035 progress 55 % (63 MB)
109 02:22:10.248097 progress 60 % (69 MB)
110 02:22:11.007380 progress 65 % (74 MB)
111 02:22:11.786418 progress 70 % (80 MB)
112 02:22:12.611396 progress 75 % (86 MB)
113 02:22:13.399554 progress 80 % (92 MB)
114 02:22:14.160914 progress 85 % (98 MB)
115 02:22:15.013159 progress 90 % (103 MB)
116 02:22:15.784889 progress 95 % (109 MB)
117 02:22:16.613021 progress 100 % (115 MB)
118 02:22:16.625597 115 MB downloaded in 14.86 s (7.76 MB/s)
119 02:22:16.626468 end: 1.4.1 http-download (duration 00:00:15) [common]
121 02:22:16.628083 end: 1.4 download-retry (duration 00:00:15) [common]
122 02:22:16.628603 start: 1.5 download-retry (timeout 00:09:44) [common]
123 02:22:16.629112 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 02:22:16.630022 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm64/defconfig/gcc-12/modules.tar.xz
125 02:22:16.630539 saving as /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/modules/modules.tar
126 02:22:16.630946 total size: 11616160 (11 MB)
127 02:22:16.631360 Using unxz to decompress xz
128 02:22:16.673687 progress 0 % (0 MB)
129 02:22:16.740914 progress 5 % (0 MB)
130 02:22:16.814714 progress 10 % (1 MB)
131 02:22:16.910143 progress 15 % (1 MB)
132 02:22:17.001663 progress 20 % (2 MB)
133 02:22:17.082385 progress 25 % (2 MB)
134 02:22:17.157547 progress 30 % (3 MB)
135 02:22:17.235633 progress 35 % (3 MB)
136 02:22:17.308091 progress 40 % (4 MB)
137 02:22:17.384921 progress 45 % (5 MB)
138 02:22:17.469303 progress 50 % (5 MB)
139 02:22:17.554083 progress 55 % (6 MB)
140 02:22:17.654603 progress 60 % (6 MB)
141 02:22:17.749756 progress 65 % (7 MB)
142 02:22:17.843952 progress 70 % (7 MB)
143 02:22:17.928092 progress 75 % (8 MB)
144 02:22:18.012664 progress 80 % (8 MB)
145 02:22:18.092478 progress 85 % (9 MB)
146 02:22:18.175175 progress 90 % (10 MB)
147 02:22:18.248170 progress 95 % (10 MB)
148 02:22:18.325954 progress 100 % (11 MB)
149 02:22:18.338164 11 MB downloaded in 1.71 s (6.49 MB/s)
150 02:22:18.338769 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:22:18.339615 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:22:18.339887 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 02:22:18.340358 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 02:22:34.797106 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/956803/extract-nfsrootfs-ccv3mfs8
156 02:22:34.797723 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 02:22:34.798008 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 02:22:34.798626 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k
159 02:22:34.799062 makedir: /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin
160 02:22:34.799390 makedir: /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/tests
161 02:22:34.799703 makedir: /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/results
162 02:22:34.800069 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-add-keys
163 02:22:34.800627 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-add-sources
164 02:22:34.801162 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-background-process-start
165 02:22:34.801684 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-background-process-stop
166 02:22:34.802245 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-common-functions
167 02:22:34.802790 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-echo-ipv4
168 02:22:34.803279 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-install-packages
169 02:22:34.803748 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-installed-packages
170 02:22:34.804321 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-os-build
171 02:22:34.804832 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-probe-channel
172 02:22:34.805307 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-probe-ip
173 02:22:34.805774 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-target-ip
174 02:22:34.806244 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-target-mac
175 02:22:34.806709 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-target-storage
176 02:22:34.807179 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-test-case
177 02:22:34.807653 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-test-event
178 02:22:34.808153 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-test-feedback
179 02:22:34.808647 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-test-raise
180 02:22:34.809113 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-test-reference
181 02:22:34.809577 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-test-runner
182 02:22:34.810048 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-test-set
183 02:22:34.810509 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-test-shell
184 02:22:34.810985 Updating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-add-keys (debian)
185 02:22:34.811505 Updating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-add-sources (debian)
186 02:22:34.812026 Updating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-install-packages (debian)
187 02:22:34.812534 Updating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-installed-packages (debian)
188 02:22:34.813089 Updating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/bin/lava-os-build (debian)
189 02:22:34.813529 Creating /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/environment
190 02:22:34.813892 LAVA metadata
191 02:22:34.814145 - LAVA_JOB_ID=956803
192 02:22:34.814359 - LAVA_DISPATCHER_IP=192.168.6.2
193 02:22:34.814711 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 02:22:34.815641 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 02:22:34.815948 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 02:22:34.816187 skipped lava-vland-overlay
197 02:22:34.816428 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 02:22:34.816679 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 02:22:34.816896 skipped lava-multinode-overlay
200 02:22:34.817136 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 02:22:34.817382 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 02:22:34.817626 Loading test definitions
203 02:22:34.817897 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 02:22:34.818114 Using /lava-956803 at stage 0
205 02:22:34.819187 uuid=956803_1.6.2.4.1 testdef=None
206 02:22:34.819487 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 02:22:34.819746 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 02:22:34.821324 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 02:22:34.822110 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 02:22:34.824009 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 02:22:34.824826 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 02:22:34.826618 runner path: /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/0/tests/0_timesync-off test_uuid 956803_1.6.2.4.1
215 02:22:34.827166 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 02:22:34.828033 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 02:22:34.828266 Using /lava-956803 at stage 0
219 02:22:34.828613 Fetching tests from https://github.com/kernelci/test-definitions.git
220 02:22:34.828902 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/0/tests/1_kselftest-alsa'
221 02:22:38.157095 Running '/usr/bin/git checkout kernelci.org
222 02:22:38.390577 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 02:22:38.393220 uuid=956803_1.6.2.4.5 testdef=None
224 02:22:38.393874 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 02:22:38.395350 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
227 02:22:38.401009 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 02:22:38.402645 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
230 02:22:38.410198 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 02:22:38.412006 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
233 02:22:38.419280 runner path: /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/0/tests/1_kselftest-alsa test_uuid 956803_1.6.2.4.5
234 02:22:38.419870 BOARD='meson-g12b-a311d-libretech-cc'
235 02:22:38.420317 BRANCH='broonie-sound'
236 02:22:38.420713 SKIPFILE='/dev/null'
237 02:22:38.421105 SKIP_INSTALL='True'
238 02:22:38.421496 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 02:22:38.421898 TST_CASENAME=''
240 02:22:38.422290 TST_CMDFILES='alsa'
241 02:22:38.423401 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 02:22:38.425030 Creating lava-test-runner.conf files
244 02:22:38.425441 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/956803/lava-overlay-91ctwb8k/lava-956803/0 for stage 0
245 02:22:38.426128 - 0_timesync-off
246 02:22:38.426600 - 1_kselftest-alsa
247 02:22:38.427259 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 02:22:38.427815 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
249 02:23:01.739879 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 02:23:01.740344 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 02:23:01.740610 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 02:23:01.740884 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 02:23:01.741150 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 02:23:02.394980 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 02:23:02.395458 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
256 02:23:02.395713 extracting modules file /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956803/extract-nfsrootfs-ccv3mfs8
257 02:23:03.915288 extracting modules file /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956803/extract-overlay-ramdisk-j7x3ko1l/ramdisk
258 02:23:05.307066 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 02:23:05.307554 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
260 02:23:05.307851 [common] Applying overlay to NFS
261 02:23:05.308104 [common] Applying overlay /var/lib/lava/dispatcher/tmp/956803/compress-overlay-ym7n8sus/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/956803/extract-nfsrootfs-ccv3mfs8
262 02:23:08.026584 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 02:23:08.027054 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 02:23:08.027365 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 02:23:08.027634 Converting downloaded kernel to a uImage
266 02:23:08.027964 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/kernel/Image /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/kernel/uImage
267 02:23:08.506306 output: Image Name:
268 02:23:08.506745 output: Created: Fri Nov 8 02:23:08 2024
269 02:23:08.506984 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 02:23:08.507207 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 02:23:08.507421 output: Load Address: 01080000
272 02:23:08.507632 output: Entry Point: 01080000
273 02:23:08.507840 output:
274 02:23:08.508236 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 02:23:08.508544 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 02:23:08.508840 start: 1.6.7 configure-preseed-file (timeout 00:08:53) [common]
277 02:23:08.509119 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 02:23:08.509404 start: 1.6.8 compress-ramdisk (timeout 00:08:53) [common]
279 02:23:08.509686 Building ramdisk /var/lib/lava/dispatcher/tmp/956803/extract-overlay-ramdisk-j7x3ko1l/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/956803/extract-overlay-ramdisk-j7x3ko1l/ramdisk
280 02:23:10.697938 >> 166792 blocks
281 02:23:18.407666 Adding RAMdisk u-boot header.
282 02:23:18.408380 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/956803/extract-overlay-ramdisk-j7x3ko1l/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/956803/extract-overlay-ramdisk-j7x3ko1l/ramdisk.cpio.gz.uboot
283 02:23:18.657750 output: Image Name:
284 02:23:18.658180 output: Created: Fri Nov 8 02:23:18 2024
285 02:23:18.658395 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 02:23:18.658601 output: Data Size: 23431912 Bytes = 22882.73 KiB = 22.35 MiB
287 02:23:18.658805 output: Load Address: 00000000
288 02:23:18.659005 output: Entry Point: 00000000
289 02:23:18.659205 output:
290 02:23:18.659868 rename /var/lib/lava/dispatcher/tmp/956803/extract-overlay-ramdisk-j7x3ko1l/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/ramdisk/ramdisk.cpio.gz.uboot
291 02:23:18.660615 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 02:23:18.661222 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 02:23:18.661804 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 02:23:18.662306 No LXC device requested
295 02:23:18.662863 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 02:23:18.663427 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 02:23:18.663975 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 02:23:18.664477 Checking files for TFTP limit of 4294967296 bytes.
299 02:23:18.667398 end: 1 tftp-deploy (duration 00:01:18) [common]
300 02:23:18.668052 start: 2 uboot-action (timeout 00:05:00) [common]
301 02:23:18.668640 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 02:23:18.669188 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 02:23:18.669740 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 02:23:18.670318 Using kernel file from prepare-kernel: 956803/tftp-deploy-s1y1wl91/kernel/uImage
305 02:23:18.671012 substitutions:
306 02:23:18.671463 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 02:23:18.671910 - {DTB_ADDR}: 0x01070000
308 02:23:18.672390 - {DTB}: 956803/tftp-deploy-s1y1wl91/dtb/meson-g12b-a311d-libretech-cc.dtb
309 02:23:18.672837 - {INITRD}: 956803/tftp-deploy-s1y1wl91/ramdisk/ramdisk.cpio.gz.uboot
310 02:23:18.673282 - {KERNEL_ADDR}: 0x01080000
311 02:23:18.673719 - {KERNEL}: 956803/tftp-deploy-s1y1wl91/kernel/uImage
312 02:23:18.674156 - {LAVA_MAC}: None
313 02:23:18.674629 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/956803/extract-nfsrootfs-ccv3mfs8
314 02:23:18.675069 - {NFS_SERVER_IP}: 192.168.6.2
315 02:23:18.675500 - {PRESEED_CONFIG}: None
316 02:23:18.675932 - {PRESEED_LOCAL}: None
317 02:23:18.676407 - {RAMDISK_ADDR}: 0x08000000
318 02:23:18.676840 - {RAMDISK}: 956803/tftp-deploy-s1y1wl91/ramdisk/ramdisk.cpio.gz.uboot
319 02:23:18.677274 - {ROOT_PART}: None
320 02:23:18.677707 - {ROOT}: None
321 02:23:18.678136 - {SERVER_IP}: 192.168.6.2
322 02:23:18.678563 - {TEE_ADDR}: 0x83000000
323 02:23:18.678993 - {TEE}: None
324 02:23:18.679423 Parsed boot commands:
325 02:23:18.679841 - setenv autoload no
326 02:23:18.680304 - setenv initrd_high 0xffffffff
327 02:23:18.680735 - setenv fdt_high 0xffffffff
328 02:23:18.681162 - dhcp
329 02:23:18.681589 - setenv serverip 192.168.6.2
330 02:23:18.682021 - tftpboot 0x01080000 956803/tftp-deploy-s1y1wl91/kernel/uImage
331 02:23:18.682455 - tftpboot 0x08000000 956803/tftp-deploy-s1y1wl91/ramdisk/ramdisk.cpio.gz.uboot
332 02:23:18.682888 - tftpboot 0x01070000 956803/tftp-deploy-s1y1wl91/dtb/meson-g12b-a311d-libretech-cc.dtb
333 02:23:18.683319 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/956803/extract-nfsrootfs-ccv3mfs8,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 02:23:18.683762 - bootm 0x01080000 0x08000000 0x01070000
335 02:23:18.684334 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 02:23:18.685977 start: 2.3 connect-device (timeout 00:05:00) [common]
338 02:23:18.686439 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 02:23:18.702103 Setting prompt string to ['lava-test: # ']
340 02:23:18.703722 end: 2.3 connect-device (duration 00:00:00) [common]
341 02:23:18.704431 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 02:23:18.705060 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 02:23:18.705660 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 02:23:18.706890 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 02:23:18.743879 >> OK - accepted request
346 02:23:18.745775 Returned 0 in 0 seconds
347 02:23:18.846918 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 02:23:18.848685 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 02:23:18.849286 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 02:23:18.849839 Setting prompt string to ['Hit any key to stop autoboot']
352 02:23:18.850330 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 02:23:18.852036 Trying 192.168.56.21...
354 02:23:18.852559 Connected to conserv1.
355 02:23:18.853001 Escape character is '^]'.
356 02:23:18.853447
357 02:23:18.853896 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 02:23:18.854348
359 02:23:30.447024 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 02:23:30.447724 bl2_stage_init 0x01
361 02:23:30.448287 bl2_stage_init 0x81
362 02:23:30.452557 hw id: 0x0000 - pwm id 0x01
363 02:23:30.453100 bl2_stage_init 0xc1
364 02:23:30.453558 bl2_stage_init 0x02
365 02:23:30.454010
366 02:23:30.458093 L0:00000000
367 02:23:30.458588 L1:20000703
368 02:23:30.459041 L2:00008067
369 02:23:30.459477 L3:14000000
370 02:23:30.463659 B2:00402000
371 02:23:30.464173 B1:e0f83180
372 02:23:30.464604
373 02:23:30.465034 TE: 58124
374 02:23:30.465499
375 02:23:30.469314 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 02:23:30.469862
377 02:23:30.470302 Board ID = 1
378 02:23:30.474842 Set A53 clk to 24M
379 02:23:30.475311 Set A73 clk to 24M
380 02:23:30.475737 Set clk81 to 24M
381 02:23:30.480429 A53 clk: 1200 MHz
382 02:23:30.480884 A73 clk: 1200 MHz
383 02:23:30.481338 CLK81: 166.6M
384 02:23:30.481769 smccc: 00012a91
385 02:23:30.486056 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 02:23:30.491641 board id: 1
387 02:23:30.497523 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 02:23:30.508324 fw parse done
389 02:23:30.514195 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 02:23:30.556826 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 02:23:30.567739 PIEI prepare done
392 02:23:30.568428 fastboot data load
393 02:23:30.568911 fastboot data verify
394 02:23:30.573440 verify result: 266
395 02:23:30.579051 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 02:23:30.579526 LPDDR4 probe
397 02:23:30.579958 ddr clk to 1584MHz
398 02:23:30.586945 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 02:23:30.624288
400 02:23:30.624850 dmc_version 0001
401 02:23:30.630877 Check phy result
402 02:23:30.636753 INFO : End of CA training
403 02:23:30.637226 INFO : End of initialization
404 02:23:30.642370 INFO : Training has run successfully!
405 02:23:30.642871 Check phy result
406 02:23:30.647934 INFO : End of initialization
407 02:23:30.648462 INFO : End of read enable training
408 02:23:30.651439 INFO : End of fine write leveling
409 02:23:30.657086 INFO : End of Write leveling coarse delay
410 02:23:30.662708 INFO : Training has run successfully!
411 02:23:30.663372 Check phy result
412 02:23:30.664019 INFO : End of initialization
413 02:23:30.668340 INFO : End of read dq deskew training
414 02:23:30.673876 INFO : End of MPR read delay center optimization
415 02:23:30.674510 INFO : End of write delay center optimization
416 02:23:30.679486 INFO : End of read delay center optimization
417 02:23:30.685111 INFO : End of max read latency training
418 02:23:30.685768 INFO : Training has run successfully!
419 02:23:30.690683 1D training succeed
420 02:23:30.696617 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 02:23:30.744049 Check phy result
422 02:23:30.744647 INFO : End of initialization
423 02:23:30.765681 INFO : End of 2D read delay Voltage center optimization
424 02:23:30.785790 INFO : End of 2D read delay Voltage center optimization
425 02:23:30.837726 INFO : End of 2D write delay Voltage center optimization
426 02:23:30.886926 INFO : End of 2D write delay Voltage center optimization
427 02:23:30.892538 INFO : Training has run successfully!
428 02:23:30.893205
429 02:23:30.893783 channel==0
430 02:23:30.898077 RxClkDly_Margin_A0==88 ps 9
431 02:23:30.898736 TxDqDly_Margin_A0==98 ps 10
432 02:23:30.903683 RxClkDly_Margin_A1==88 ps 9
433 02:23:30.904376 TxDqDly_Margin_A1==98 ps 10
434 02:23:30.904970 TrainedVREFDQ_A0==74
435 02:23:30.909272 TrainedVREFDQ_A1==75
436 02:23:30.909929 VrefDac_Margin_A0==25
437 02:23:30.910482 DeviceVref_Margin_A0==40
438 02:23:30.914872 VrefDac_Margin_A1==25
439 02:23:30.915520 DeviceVref_Margin_A1==39
440 02:23:30.916131
441 02:23:30.916695
442 02:23:30.920544 channel==1
443 02:23:30.921200 RxClkDly_Margin_A0==98 ps 10
444 02:23:30.921752 TxDqDly_Margin_A0==98 ps 10
445 02:23:30.926082 RxClkDly_Margin_A1==98 ps 10
446 02:23:30.926736 TxDqDly_Margin_A1==88 ps 9
447 02:23:30.931685 TrainedVREFDQ_A0==77
448 02:23:30.932388 TrainedVREFDQ_A1==77
449 02:23:30.932950 VrefDac_Margin_A0==22
450 02:23:30.937287 DeviceVref_Margin_A0==37
451 02:23:30.937928 VrefDac_Margin_A1==24
452 02:23:30.942884 DeviceVref_Margin_A1==37
453 02:23:30.943529
454 02:23:30.944127 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 02:23:30.948537
456 02:23:30.976490 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 02:23:30.977283 2D training succeed
458 02:23:30.982104 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 02:23:30.987682 auto size-- 65535DDR cs0 size: 2048MB
460 02:23:30.988409 DDR cs1 size: 2048MB
461 02:23:30.993328 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 02:23:30.993982 cs0 DataBus test pass
463 02:23:30.998860 cs1 DataBus test pass
464 02:23:30.999519 cs0 AddrBus test pass
465 02:23:31.000109 cs1 AddrBus test pass
466 02:23:31.000662
467 02:23:31.004550 100bdlr_step_size ps== 420
468 02:23:31.005219 result report
469 02:23:31.010050 boot times 0Enable ddr reg access
470 02:23:31.015667 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 02:23:31.028944 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 02:23:31.600961 0.0;M3 CHK:0;cm4_sp_mode 0
473 02:23:31.601769 MVN_1=0x00000000
474 02:23:31.606533 MVN_2=0x00000000
475 02:23:31.612114 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 02:23:31.612621 OPS=0x10
477 02:23:31.613055 ring efuse init
478 02:23:31.613471 chipver efuse init
479 02:23:31.620281 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 02:23:31.620753 [0.018961 Inits done]
481 02:23:31.627916 secure task start!
482 02:23:31.628573 high task start!
483 02:23:31.629140 low task start!
484 02:23:31.629684 run into bl31
485 02:23:31.634574 NOTICE: BL31: v1.3(release):4fc40b1
486 02:23:31.642351 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 02:23:31.642961 NOTICE: BL31: G12A normal boot!
488 02:23:31.667766 NOTICE: BL31: BL33 decompress pass
489 02:23:31.673435 ERROR: Error initializing runtime service opteed_fast
490 02:23:32.906412
491 02:23:32.907189
492 02:23:32.914918 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 02:23:32.915517
494 02:23:32.916100 Model: Libre Computer AML-A311D-CC Alta
495 02:23:33.123339 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 02:23:33.146681 DRAM: 2 GiB (effective 3.8 GiB)
497 02:23:33.289798 Core: 408 devices, 31 uclasses, devicetree: separate
498 02:23:33.295460 WDT: Not starting watchdog@f0d0
499 02:23:33.327829 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 02:23:33.340218 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 02:23:33.345276 ** Bad device specification mmc 0 **
502 02:23:33.355431 Card did not respond to voltage select! : -110
503 02:23:33.362133 ** Bad device specification mmc 0 **
504 02:23:33.362718 Couldn't find partition mmc 0
505 02:23:33.371501 Card did not respond to voltage select! : -110
506 02:23:33.377073 ** Bad device specification mmc 0 **
507 02:23:33.377650 Couldn't find partition mmc 0
508 02:23:33.382160 Error: could not access storage.
509 02:23:34.647584 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 02:23:34.648449 bl2_stage_init 0x01
511 02:23:34.649018 bl2_stage_init 0x81
512 02:23:34.653256 hw id: 0x0000 - pwm id 0x01
513 02:23:34.653845 bl2_stage_init 0xc1
514 02:23:34.654392 bl2_stage_init 0x02
515 02:23:34.654914
516 02:23:34.658751 L0:00000000
517 02:23:34.659317 L1:20000703
518 02:23:34.659852 L2:00008067
519 02:23:34.660417 L3:14000000
520 02:23:34.664401 B2:00402000
521 02:23:34.664960 B1:e0f83180
522 02:23:34.665494
523 02:23:34.666012 TE: 58124
524 02:23:34.666528
525 02:23:34.669989 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 02:23:34.670563
527 02:23:34.671086 Board ID = 1
528 02:23:34.675530 Set A53 clk to 24M
529 02:23:34.676116 Set A73 clk to 24M
530 02:23:34.676658 Set clk81 to 24M
531 02:23:34.681127 A53 clk: 1200 MHz
532 02:23:34.681680 A73 clk: 1200 MHz
533 02:23:34.682212 CLK81: 166.6M
534 02:23:34.682727 smccc: 00012a92
535 02:23:34.686743 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 02:23:34.692331 board id: 1
537 02:23:34.698426 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 02:23:34.708967 fw parse done
539 02:23:34.714781 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 02:23:34.757408 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 02:23:34.768288 PIEI prepare done
542 02:23:34.768868 fastboot data load
543 02:23:34.769401 fastboot data verify
544 02:23:34.774019 verify result: 266
545 02:23:34.779562 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 02:23:34.780179 LPDDR4 probe
547 02:23:34.780706 ddr clk to 1584MHz
548 02:23:34.787588 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 02:23:34.824881
550 02:23:34.825486 dmc_version 0001
551 02:23:34.831602 Check phy result
552 02:23:34.837607 INFO : End of CA training
553 02:23:34.838175 INFO : End of initialization
554 02:23:34.843817 INFO : Training has run successfully!
555 02:23:34.844543 Check phy result
556 02:23:34.848983 INFO : End of initialization
557 02:23:34.849631 INFO : End of read enable training
558 02:23:34.854827 INFO : End of fine write leveling
559 02:23:34.860082 INFO : End of Write leveling coarse delay
560 02:23:34.860610 INFO : Training has run successfully!
561 02:23:34.861035 Check phy result
562 02:23:34.865590 INFO : End of initialization
563 02:23:34.866109 INFO : End of read dq deskew training
564 02:23:34.871500 INFO : End of MPR read delay center optimization
565 02:23:34.876657 INFO : End of write delay center optimization
566 02:23:34.882479 INFO : End of read delay center optimization
567 02:23:34.882937 INFO : End of max read latency training
568 02:23:34.887836 INFO : Training has run successfully!
569 02:23:34.888360 1D training succeed
570 02:23:34.900590 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 02:23:34.944779 Check phy result
572 02:23:34.945570 INFO : End of initialization
573 02:23:34.966507 INFO : End of 2D read delay Voltage center optimization
574 02:23:34.986788 INFO : End of 2D read delay Voltage center optimization
575 02:23:35.039051 INFO : End of 2D write delay Voltage center optimization
576 02:23:35.088164 INFO : End of 2D write delay Voltage center optimization
577 02:23:35.093686 INFO : Training has run successfully!
578 02:23:35.094233
579 02:23:35.094646 channel==0
580 02:23:35.099210 RxClkDly_Margin_A0==88 ps 9
581 02:23:35.099797 TxDqDly_Margin_A0==98 ps 10
582 02:23:35.104874 RxClkDly_Margin_A1==88 ps 9
583 02:23:35.105424 TxDqDly_Margin_A1==98 ps 10
584 02:23:35.105830 TrainedVREFDQ_A0==74
585 02:23:35.110749 TrainedVREFDQ_A1==74
586 02:23:35.111242 VrefDac_Margin_A0==25
587 02:23:35.111638 DeviceVref_Margin_A0==40
588 02:23:35.116098 VrefDac_Margin_A1==25
589 02:23:35.116613 DeviceVref_Margin_A1==40
590 02:23:35.117010
591 02:23:35.117405
592 02:23:35.121659 channel==1
593 02:23:35.122148 RxClkDly_Margin_A0==98 ps 10
594 02:23:35.122549 TxDqDly_Margin_A0==98 ps 10
595 02:23:35.127199 RxClkDly_Margin_A1==98 ps 10
596 02:23:35.127695 TxDqDly_Margin_A1==98 ps 10
597 02:23:35.132801 TrainedVREFDQ_A0==77
598 02:23:35.133293 TrainedVREFDQ_A1==78
599 02:23:35.133689 VrefDac_Margin_A0==22
600 02:23:35.138464 DeviceVref_Margin_A0==37
601 02:23:35.138964 VrefDac_Margin_A1==22
602 02:23:35.144040 DeviceVref_Margin_A1==36
603 02:23:35.144578
604 02:23:35.144981 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 02:23:35.149593
606 02:23:35.177619 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
607 02:23:35.178254 2D training succeed
608 02:23:35.183172 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 02:23:35.188820 auto size-- 65535DDR cs0 size: 2048MB
610 02:23:35.189400 DDR cs1 size: 2048MB
611 02:23:35.194493 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 02:23:35.195110 cs0 DataBus test pass
613 02:23:35.199968 cs1 DataBus test pass
614 02:23:35.200492 cs0 AddrBus test pass
615 02:23:35.200889 cs1 AddrBus test pass
616 02:23:35.201279
617 02:23:35.205654 100bdlr_step_size ps== 420
618 02:23:35.206254 result report
619 02:23:35.211268 boot times 0Enable ddr reg access
620 02:23:35.217879 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 02:23:35.230228 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 02:23:35.803841 0.0;M3 CHK:0;cm4_sp_mode 0
623 02:23:35.804521 MVN_1=0x00000000
624 02:23:35.809346 MVN_2=0x00000000
625 02:23:35.815220 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 02:23:35.815704 OPS=0x10
627 02:23:35.816160 ring efuse init
628 02:23:35.816576 chipver efuse init
629 02:23:35.823324 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 02:23:35.823844 [0.018961 Inits done]
631 02:23:35.830801 secure task start!
632 02:23:35.831239 high task start!
633 02:23:35.831632 low task start!
634 02:23:35.832054 run into bl31
635 02:23:35.837445 NOTICE: BL31: v1.3(release):4fc40b1
636 02:23:35.845292 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 02:23:35.845736 NOTICE: BL31: G12A normal boot!
638 02:23:35.870722 NOTICE: BL31: BL33 decompress pass
639 02:23:35.876370 ERROR: Error initializing runtime service opteed_fast
640 02:23:37.109819
641 02:23:37.110433
642 02:23:37.117859 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 02:23:37.118320
644 02:23:37.118732 Model: Libre Computer AML-A311D-CC Alta
645 02:23:37.326168 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 02:23:37.349521 DRAM: 2 GiB (effective 3.8 GiB)
647 02:23:37.492527 Core: 408 devices, 31 uclasses, devicetree: separate
648 02:23:37.498395 WDT: Not starting watchdog@f0d0
649 02:23:37.530575 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 02:23:37.543066 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 02:23:37.548079 ** Bad device specification mmc 0 **
652 02:23:37.558487 Card did not respond to voltage select! : -110
653 02:23:37.566049 ** Bad device specification mmc 0 **
654 02:23:37.566518 Couldn't find partition mmc 0
655 02:23:37.574434 Card did not respond to voltage select! : -110
656 02:23:37.579843 ** Bad device specification mmc 0 **
657 02:23:37.580338 Couldn't find partition mmc 0
658 02:23:37.584908 Error: could not access storage.
659 02:23:37.927486 Net: eth0: ethernet@ff3f0000
660 02:23:37.928102 starting USB...
661 02:23:38.179242 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 02:23:38.179779 Starting the controller
663 02:23:38.186189 USB XHCI 1.10
664 02:23:39.896273 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 02:23:39.896896 bl2_stage_init 0x01
666 02:23:39.897322 bl2_stage_init 0x81
667 02:23:39.901814 hw id: 0x0000 - pwm id 0x01
668 02:23:39.902263 bl2_stage_init 0xc1
669 02:23:39.902674 bl2_stage_init 0x02
670 02:23:39.903074
671 02:23:39.907441 L0:00000000
672 02:23:39.907874 L1:20000703
673 02:23:39.908368 L2:00008067
674 02:23:39.908770 L3:14000000
675 02:23:39.910305 B2:00402000
676 02:23:39.910736 B1:e0f83180
677 02:23:39.911139
678 02:23:39.911539 TE: 58124
679 02:23:39.911938
680 02:23:39.921446 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 02:23:39.921904
682 02:23:39.922311 Board ID = 1
683 02:23:39.922706 Set A53 clk to 24M
684 02:23:39.923100 Set A73 clk to 24M
685 02:23:39.926988 Set clk81 to 24M
686 02:23:39.927424 A53 clk: 1200 MHz
687 02:23:39.927828 A73 clk: 1200 MHz
688 02:23:39.932689 CLK81: 166.6M
689 02:23:39.933128 smccc: 00012a92
690 02:23:39.938266 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 02:23:39.938705 board id: 1
692 02:23:39.947057 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 02:23:39.957399 fw parse done
694 02:23:39.963416 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 02:23:40.006032 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 02:23:40.016909 PIEI prepare done
697 02:23:40.017366 fastboot data load
698 02:23:40.017778 fastboot data verify
699 02:23:40.022653 verify result: 266
700 02:23:40.028166 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 02:23:40.028628 LPDDR4 probe
702 02:23:40.029032 ddr clk to 1584MHz
703 02:23:40.036183 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 02:23:40.073419
705 02:23:40.073892 dmc_version 0001
706 02:23:40.080162 Check phy result
707 02:23:40.086016 INFO : End of CA training
708 02:23:40.086451 INFO : End of initialization
709 02:23:40.091671 INFO : Training has run successfully!
710 02:23:40.092140 Check phy result
711 02:23:40.097202 INFO : End of initialization
712 02:23:40.097634 INFO : End of read enable training
713 02:23:40.100480 INFO : End of fine write leveling
714 02:23:40.106032 INFO : End of Write leveling coarse delay
715 02:23:40.111674 INFO : Training has run successfully!
716 02:23:40.112126 Check phy result
717 02:23:40.112530 INFO : End of initialization
718 02:23:40.117234 INFO : End of read dq deskew training
719 02:23:40.122784 INFO : End of MPR read delay center optimization
720 02:23:40.123213 INFO : End of write delay center optimization
721 02:23:40.128406 INFO : End of read delay center optimization
722 02:23:40.134017 INFO : End of max read latency training
723 02:23:40.134460 INFO : Training has run successfully!
724 02:23:40.139728 1D training succeed
725 02:23:40.145564 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 02:23:40.193129 Check phy result
727 02:23:40.193577 INFO : End of initialization
728 02:23:40.215823 INFO : End of 2D read delay Voltage center optimization
729 02:23:40.235961 INFO : End of 2D read delay Voltage center optimization
730 02:23:40.288093 INFO : End of 2D write delay Voltage center optimization
731 02:23:40.337441 INFO : End of 2D write delay Voltage center optimization
732 02:23:40.342965 INFO : Training has run successfully!
733 02:23:40.343397
734 02:23:40.343802 channel==0
735 02:23:40.348504 RxClkDly_Margin_A0==88 ps 9
736 02:23:40.348967 TxDqDly_Margin_A0==98 ps 10
737 02:23:40.354178 RxClkDly_Margin_A1==88 ps 9
738 02:23:40.354613 TxDqDly_Margin_A1==98 ps 10
739 02:23:40.355018 TrainedVREFDQ_A0==74
740 02:23:40.359763 TrainedVREFDQ_A1==74
741 02:23:40.360230 VrefDac_Margin_A0==25
742 02:23:40.360633 DeviceVref_Margin_A0==40
743 02:23:40.365359 VrefDac_Margin_A1==26
744 02:23:40.365783 DeviceVref_Margin_A1==40
745 02:23:40.366186
746 02:23:40.366585
747 02:23:40.370891 channel==1
748 02:23:40.371331 RxClkDly_Margin_A0==98 ps 10
749 02:23:40.371734 TxDqDly_Margin_A0==98 ps 10
750 02:23:40.376525 RxClkDly_Margin_A1==98 ps 10
751 02:23:40.376964 TxDqDly_Margin_A1==88 ps 9
752 02:23:40.382120 TrainedVREFDQ_A0==77
753 02:23:40.382557 TrainedVREFDQ_A1==77
754 02:23:40.382963 VrefDac_Margin_A0==22
755 02:23:40.387785 DeviceVref_Margin_A0==37
756 02:23:40.388258 VrefDac_Margin_A1==22
757 02:23:40.393308 DeviceVref_Margin_A1==37
758 02:23:40.393743
759 02:23:40.394154 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 02:23:40.398897
761 02:23:40.426950 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000017 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 02:23:40.427456 2D training succeed
763 02:23:40.432481 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 02:23:40.438113 auto size-- 65535DDR cs0 size: 2048MB
765 02:23:40.438549 DDR cs1 size: 2048MB
766 02:23:40.443704 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 02:23:40.444176 cs0 DataBus test pass
768 02:23:40.449295 cs1 DataBus test pass
769 02:23:40.449728 cs0 AddrBus test pass
770 02:23:40.450126 cs1 AddrBus test pass
771 02:23:40.450523
772 02:23:40.454914 100bdlr_step_size ps== 420
773 02:23:40.455362 result report
774 02:23:40.460505 boot times 0Enable ddr reg access
775 02:23:40.465941 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 02:23:40.479454 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 02:23:41.052585 0.0;M3 CHK:0;cm4_sp_mode 0
778 02:23:41.053225 MVN_1=0x00000000
779 02:23:41.058075 MVN_2=0x00000000
780 02:23:41.063863 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 02:23:41.064401 OPS=0x10
782 02:23:41.064808 ring efuse init
783 02:23:41.065198 chipver efuse init
784 02:23:41.072133 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 02:23:41.072583 [0.018961 Inits done]
786 02:23:41.072973 secure task start!
787 02:23:41.079722 high task start!
788 02:23:41.080182 low task start!
789 02:23:41.080574 run into bl31
790 02:23:41.086278 NOTICE: BL31: v1.3(release):4fc40b1
791 02:23:41.094117 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 02:23:41.094556 NOTICE: BL31: G12A normal boot!
793 02:23:41.119440 NOTICE: BL31: BL33 decompress pass
794 02:23:41.125038 ERROR: Error initializing runtime service opteed_fast
795 02:23:42.358070
796 02:23:42.358682
797 02:23:42.366543 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 02:23:42.367001
799 02:23:42.367408 Model: Libre Computer AML-A311D-CC Alta
800 02:23:42.574959 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 02:23:42.598415 DRAM: 2 GiB (effective 3.8 GiB)
802 02:23:42.741227 Core: 408 devices, 31 uclasses, devicetree: separate
803 02:23:42.747253 WDT: Not starting watchdog@f0d0
804 02:23:42.779349 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 02:23:42.792023 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 02:23:42.796824 ** Bad device specification mmc 0 **
807 02:23:42.807174 Card did not respond to voltage select! : -110
808 02:23:42.814886 ** Bad device specification mmc 0 **
809 02:23:42.815597 Couldn't find partition mmc 0
810 02:23:42.823127 Card did not respond to voltage select! : -110
811 02:23:42.828635 ** Bad device specification mmc 0 **
812 02:23:42.829232 Couldn't find partition mmc 0
813 02:23:42.833771 Error: could not access storage.
814 02:23:43.177409 Net: eth0: ethernet@ff3f0000
815 02:23:43.178201 starting USB...
816 02:23:43.429149 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 02:23:43.429873 Starting the controller
818 02:23:43.436063 USB XHCI 1.10
819 02:23:45.596546 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 02:23:45.597338 bl2_stage_init 0x01
821 02:23:45.597894 bl2_stage_init 0x81
822 02:23:45.602067 hw id: 0x0000 - pwm id 0x01
823 02:23:45.602678 bl2_stage_init 0xc1
824 02:23:45.603212 bl2_stage_init 0x02
825 02:23:45.603747
826 02:23:45.607677 L0:00000000
827 02:23:45.608330 L1:20000703
828 02:23:45.608879 L2:00008067
829 02:23:45.609411 L3:14000000
830 02:23:45.610542 B2:00402000
831 02:23:45.611116 B1:e0f83180
832 02:23:45.611651
833 02:23:45.612211 TE: 58167
834 02:23:45.612749
835 02:23:45.621643 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 02:23:45.622268
837 02:23:45.622807 Board ID = 1
838 02:23:45.623320 Set A53 clk to 24M
839 02:23:45.623828 Set A73 clk to 24M
840 02:23:45.627370 Set clk81 to 24M
841 02:23:45.627948 A53 clk: 1200 MHz
842 02:23:45.628526 A73 clk: 1200 MHz
843 02:23:45.632885 CLK81: 166.6M
844 02:23:45.633467 smccc: 00012abe
845 02:23:45.638487 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 02:23:45.639141 board id: 1
847 02:23:45.644184 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 02:23:45.657794 fw parse done
849 02:23:45.662964 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 02:23:45.705511 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 02:23:45.717438 PIEI prepare done
852 02:23:45.718017 fastboot data load
853 02:23:45.718559 fastboot data verify
854 02:23:45.722932 verify result: 266
855 02:23:45.728526 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 02:23:45.729088 LPDDR4 probe
857 02:23:45.729624 ddr clk to 1584MHz
858 02:23:45.735520 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 02:23:45.772836
860 02:23:45.773496 dmc_version 0001
861 02:23:45.779552 Check phy result
862 02:23:45.786451 INFO : End of CA training
863 02:23:45.787029 INFO : End of initialization
864 02:23:45.791929 INFO : Training has run successfully!
865 02:23:45.792560 Check phy result
866 02:23:45.797595 INFO : End of initialization
867 02:23:45.798114 INFO : End of read enable training
868 02:23:45.803126 INFO : End of fine write leveling
869 02:23:45.808771 INFO : End of Write leveling coarse delay
870 02:23:45.809230 INFO : Training has run successfully!
871 02:23:45.809646 Check phy result
872 02:23:45.814439 INFO : End of initialization
873 02:23:45.814872 INFO : End of read dq deskew training
874 02:23:45.819899 INFO : End of MPR read delay center optimization
875 02:23:45.825521 INFO : End of write delay center optimization
876 02:23:45.831130 INFO : End of read delay center optimization
877 02:23:45.831581 INFO : End of max read latency training
878 02:23:45.836712 INFO : Training has run successfully!
879 02:23:45.837175 1D training succeed
880 02:23:45.844956 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 02:23:45.892621 Check phy result
882 02:23:45.893153 INFO : End of initialization
883 02:23:45.914301 INFO : End of 2D read delay Voltage center optimization
884 02:23:45.934701 INFO : End of 2D read delay Voltage center optimization
885 02:23:45.986762 INFO : End of 2D write delay Voltage center optimization
886 02:23:46.037008 INFO : End of 2D write delay Voltage center optimization
887 02:23:46.042467 INFO : Training has run successfully!
888 02:23:46.042917
889 02:23:46.043332 channel==0
890 02:23:46.048047 RxClkDly_Margin_A0==88 ps 9
891 02:23:46.048507 TxDqDly_Margin_A0==98 ps 10
892 02:23:46.051386 RxClkDly_Margin_A1==88 ps 9
893 02:23:46.051828 TxDqDly_Margin_A1==98 ps 10
894 02:23:46.056918 TrainedVREFDQ_A0==74
895 02:23:46.057370 TrainedVREFDQ_A1==75
896 02:23:46.062541 VrefDac_Margin_A0==25
897 02:23:46.063047 DeviceVref_Margin_A0==40
898 02:23:46.063448 VrefDac_Margin_A1==25
899 02:23:46.068106 DeviceVref_Margin_A1==39
900 02:23:46.068602
901 02:23:46.068995
902 02:23:46.069380 channel==1
903 02:23:46.069763 RxClkDly_Margin_A0==98 ps 10
904 02:23:46.073643 TxDqDly_Margin_A0==88 ps 9
905 02:23:46.074084 RxClkDly_Margin_A1==98 ps 10
906 02:23:46.079244 TxDqDly_Margin_A1==98 ps 10
907 02:23:46.079678 TrainedVREFDQ_A0==76
908 02:23:46.080098 TrainedVREFDQ_A1==77
909 02:23:46.084831 VrefDac_Margin_A0==22
910 02:23:46.085258 DeviceVref_Margin_A0==38
911 02:23:46.090443 VrefDac_Margin_A1==22
912 02:23:46.090886 DeviceVref_Margin_A1==37
913 02:23:46.091272
914 02:23:46.096052 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 02:23:46.096483
916 02:23:46.124048 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 0000001a 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
917 02:23:46.129637 2D training succeed
918 02:23:46.135215 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 02:23:46.135637 auto size-- 65535DDR cs0 size: 2048MB
920 02:23:46.140873 DDR cs1 size: 2048MB
921 02:23:46.141302 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 02:23:46.146498 cs0 DataBus test pass
923 02:23:46.146919 cs1 DataBus test pass
924 02:23:46.147306 cs0 AddrBus test pass
925 02:23:46.152066 cs1 AddrBus test pass
926 02:23:46.152489
927 02:23:46.152883 100bdlr_step_size ps== 420
928 02:23:46.153280 result report
929 02:23:46.157650 boot times 0Enable ddr reg access
930 02:23:46.164626 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 02:23:46.178036 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 02:23:46.752737 0.0;M3 CHK:0;cm4_sp_mode 0
933 02:23:46.753373 MVN_1=0x00000000
934 02:23:46.758100 MVN_2=0x00000000
935 02:23:46.763906 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 02:23:46.764434 OPS=0x10
937 02:23:46.764848 ring efuse init
938 02:23:46.765249 chipver efuse init
939 02:23:46.772129 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 02:23:46.772638 [0.018960 Inits done]
941 02:23:46.779701 secure task start!
942 02:23:46.780286 high task start!
943 02:23:46.780702 low task start!
944 02:23:46.781107 run into bl31
945 02:23:46.786303 NOTICE: BL31: v1.3(release):4fc40b1
946 02:23:46.794098 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 02:23:46.794573 NOTICE: BL31: G12A normal boot!
948 02:23:46.819681 NOTICE: BL31: BL33 decompress pass
949 02:23:46.825211 ERROR: Error initializing runtime service opteed_fast
950 02:23:48.058114
951 02:23:48.058887
952 02:23:48.065497 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 02:23:48.066088
954 02:23:48.066632 Model: Libre Computer AML-A311D-CC Alta
955 02:23:48.274034 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 02:23:48.297349 DRAM: 2 GiB (effective 3.8 GiB)
957 02:23:48.441350 Core: 408 devices, 31 uclasses, devicetree: separate
958 02:23:48.446185 WDT: Not starting watchdog@f0d0
959 02:23:48.479382 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 02:23:48.492045 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 02:23:48.495976 ** Bad device specification mmc 0 **
962 02:23:48.507194 Card did not respond to voltage select! : -110
963 02:23:48.513956 ** Bad device specification mmc 0 **
964 02:23:48.514471 Couldn't find partition mmc 0
965 02:23:48.523173 Card did not respond to voltage select! : -110
966 02:23:48.528923 ** Bad device specification mmc 0 **
967 02:23:48.529389 Couldn't find partition mmc 0
968 02:23:48.532769 Error: could not access storage.
969 02:23:48.876354 Net: eth0: ethernet@ff3f0000
970 02:23:48.876768 starting USB...
971 02:23:49.129029 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 02:23:49.129432 Starting the controller
973 02:23:49.135067 USB XHCI 1.10
974 02:23:50.690118 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 02:23:50.698418 scanning usb for storage devices... 0 Storage Device(s) found
977 02:23:50.750100 Hit any key to stop autoboot: 1
978 02:23:50.750962 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
979 02:23:50.751620 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
980 02:23:50.752162 Setting prompt string to ['=>']
981 02:23:50.752650 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
982 02:23:50.765829 0
983 02:23:50.766728 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 02:23:50.767241 Sending with 10 millisecond of delay
986 02:23:51.901894 => setenv autoload no
987 02:23:51.912679 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
988 02:23:51.917593 setenv autoload no
989 02:23:51.918312 Sending with 10 millisecond of delay
991 02:23:53.715033 => setenv initrd_high 0xffffffff
992 02:23:53.725783 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
993 02:23:53.726623 setenv initrd_high 0xffffffff
994 02:23:53.727334 Sending with 10 millisecond of delay
996 02:23:55.343524 => setenv fdt_high 0xffffffff
997 02:23:55.354348 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
998 02:23:55.355182 setenv fdt_high 0xffffffff
999 02:23:55.355894 Sending with 10 millisecond of delay
1001 02:23:55.647799 => dhcp
1002 02:23:55.658622 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1003 02:23:55.659448 dhcp
1004 02:23:55.659886 Speed: 1000, full duplex
1005 02:23:55.660349 BOOTP broadcast 1
1006 02:23:55.853822 DHCP client bound to address 192.168.6.27 (194 ms)
1007 02:23:55.854692 Sending with 10 millisecond of delay
1009 02:23:57.530989 => setenv serverip 192.168.6.2
1010 02:23:57.541790 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1011 02:23:57.542725 setenv serverip 192.168.6.2
1012 02:23:57.543415 Sending with 10 millisecond of delay
1014 02:24:01.266965 => tftpboot 0x01080000 956803/tftp-deploy-s1y1wl91/kernel/uImage
1015 02:24:01.277777 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1016 02:24:01.278652 tftpboot 0x01080000 956803/tftp-deploy-s1y1wl91/kernel/uImage
1017 02:24:01.279105 Speed: 1000, full duplex
1018 02:24:01.279524 Using ethernet@ff3f0000 device
1019 02:24:01.280581 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1020 02:24:01.286017 Filename '956803/tftp-deploy-s1y1wl91/kernel/uImage'.
1021 02:24:01.289900 Load address: 0x1080000
1022 02:24:04.144285 Loading: *################################################## 43.6 MiB
1023 02:24:04.144705 15.3 MiB/s
1024 02:24:04.144934 done
1025 02:24:04.148447 Bytes transferred = 45713984 (2b98a40 hex)
1026 02:24:04.148963 Sending with 10 millisecond of delay
1028 02:24:08.837210 => tftpboot 0x08000000 956803/tftp-deploy-s1y1wl91/ramdisk/ramdisk.cpio.gz.uboot
1029 02:24:08.847971 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1030 02:24:08.848827 tftpboot 0x08000000 956803/tftp-deploy-s1y1wl91/ramdisk/ramdisk.cpio.gz.uboot
1031 02:24:08.849275 Speed: 1000, full duplex
1032 02:24:08.849695 Using ethernet@ff3f0000 device
1033 02:24:08.850847 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1034 02:24:08.859538 Filename '956803/tftp-deploy-s1y1wl91/ramdisk/ramdisk.cpio.gz.uboot'.
1035 02:24:08.860080 Load address: 0x8000000
1036 02:24:15.326471 Loading: *###################T ############################### 22.3 MiB
1037 02:24:15.327089 3.5 MiB/s
1038 02:24:15.327516 done
1039 02:24:15.329494 Bytes transferred = 23431976 (1658b28 hex)
1040 02:24:15.330250 Sending with 10 millisecond of delay
1042 02:24:20.499312 => tftpboot 0x01070000 956803/tftp-deploy-s1y1wl91/dtb/meson-g12b-a311d-libretech-cc.dtb
1043 02:24:20.510103 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
1044 02:24:20.510941 tftpboot 0x01070000 956803/tftp-deploy-s1y1wl91/dtb/meson-g12b-a311d-libretech-cc.dtb
1045 02:24:20.511406 Speed: 1000, full duplex
1046 02:24:20.511820 Using ethernet@ff3f0000 device
1047 02:24:20.515249 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1048 02:24:20.522711 Filename '956803/tftp-deploy-s1y1wl91/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1049 02:24:20.533174 Load address: 0x1070000
1050 02:24:20.544727 Loading: *################################################## 53.4 KiB
1051 02:24:20.545223 3.3 MiB/s
1052 02:24:20.545635 done
1053 02:24:20.549235 Bytes transferred = 54703 (d5af hex)
1054 02:24:20.549978 Sending with 10 millisecond of delay
1056 02:24:33.845665 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/956803/extract-nfsrootfs-ccv3mfs8,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1057 02:24:33.856468 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:45)
1058 02:24:33.857321 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/956803/extract-nfsrootfs-ccv3mfs8,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1059 02:24:33.858026 Sending with 10 millisecond of delay
1061 02:24:36.196298 => bootm 0x01080000 0x08000000 0x01070000
1062 02:24:36.207090 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1063 02:24:36.207629 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:42)
1064 02:24:36.208650 bootm 0x01080000 0x08000000 0x01070000
1065 02:24:36.209093 ## Booting kernel from Legacy Image at 01080000 ...
1066 02:24:36.212089 Image Name:
1067 02:24:36.217511 Image Type: AArch64 Linux Kernel Image (uncompressed)
1068 02:24:36.217980 Data Size: 45713920 Bytes = 43.6 MiB
1069 02:24:36.223127 Load Address: 01080000
1070 02:24:36.223582 Entry Point: 01080000
1071 02:24:36.418282 Verifying Checksum ... OK
1072 02:24:36.418820 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1073 02:24:36.423820 Image Name:
1074 02:24:36.429336 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1075 02:24:36.429801 Data Size: 23431912 Bytes = 22.3 MiB
1076 02:24:36.431648 Load Address: 00000000
1077 02:24:36.438882 Entry Point: 00000000
1078 02:24:36.537068 Verifying Checksum ... OK
1079 02:24:36.537610 ## Flattened Device Tree blob at 01070000
1080 02:24:36.542538 Booting using the fdt blob at 0x1070000
1081 02:24:36.543018 Working FDT set to 1070000
1082 02:24:36.546972 Loading Kernel Image
1083 02:24:36.591454 Loading Ramdisk to 7e9a7000, end 7ffffae8 ... OK
1084 02:24:36.599859 Loading Device Tree to 000000007e996000, end 000000007e9a65ae ... OK
1085 02:24:36.600372 Working FDT set to 7e996000
1086 02:24:36.600790
1087 02:24:36.601674 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1088 02:24:36.602255 start: 2.4.4 auto-login-action (timeout 00:03:42) [common]
1089 02:24:36.602722 Setting prompt string to ['Linux version [0-9]']
1090 02:24:36.603346 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1091 02:24:36.603832 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1092 02:24:36.604895 Starting kernel ...
1093 02:24:36.605348
1094 02:24:36.640077 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1095 02:24:36.641002 start: 2.4.4.1 login-action (timeout 00:03:42) [common]
1096 02:24:36.641530 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1097 02:24:36.641998 Setting prompt string to []
1098 02:24:36.642483 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1099 02:24:36.642941 Using line separator: #'\n'#
1100 02:24:36.643350 No login prompt set.
1101 02:24:36.643785 Parsing kernel messages
1102 02:24:36.644225 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1103 02:24:36.645016 [login-action] Waiting for messages, (timeout 00:03:42)
1104 02:24:36.645497 Waiting using forced prompt support (timeout 00:01:51)
1105 02:24:36.660198 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j367672-arm64-gcc-12-defconfig-tngf7) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Fri Nov 8 00:30:12 UTC 2024
1106 02:24:36.660694 [ 0.000000] KASLR disabled due to lack of seed
1107 02:24:36.665754 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1108 02:24:36.671257 [ 0.000000] efi: UEFI not found.
1109 02:24:36.676761 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1110 02:24:36.687785 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1111 02:24:36.693369 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1112 02:24:36.704335 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1113 02:24:36.715314 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1114 02:24:36.726436 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1115 02:24:36.731965 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1116 02:24:36.737410 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1117 02:24:36.742894 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1118 02:24:36.748420 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1119 02:24:36.753917 [ 0.000000] Zone ranges:
1120 02:24:36.759445 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1121 02:24:36.759900 [ 0.000000] DMA32 empty
1122 02:24:36.764978 [ 0.000000] Normal empty
1123 02:24:36.770502 [ 0.000000] Movable zone start for each node
1124 02:24:36.770957 [ 0.000000] Early memory node ranges
1125 02:24:36.776048 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1126 02:24:36.781538 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1127 02:24:36.792514 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1128 02:24:36.797641 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1129 02:24:36.821881 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1130 02:24:36.827482 [ 0.000000] psci: probing for conduit method from DT.
1131 02:24:36.827935 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1132 02:24:36.836472 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1133 02:24:36.836930 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1134 02:24:36.842040 [ 0.000000] psci: SMC Calling Convention v1.1
1135 02:24:36.847570 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1136 02:24:36.853060 [ 0.000000] Detected VIPT I-cache on CPU0
1137 02:24:36.858591 [ 0.000000] CPU features: detected: ARM erratum 845719
1138 02:24:36.864126 [ 0.000000] alternatives: applying boot alternatives
1139 02:24:36.886135 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/956803/extract-nfsrootfs-ccv3mfs8,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1140 02:24:36.891754 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1141 02:24:36.902699 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1142 02:24:36.903170 <6>[ 0.000000] Fallback order for Node 0: 0
1143 02:24:36.913768 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1144 02:24:36.914229 <6>[ 0.000000] Policy zone: DMA
1145 02:24:36.919318 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1146 02:24:36.930396 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1147 02:24:36.930858 <6>[ 0.000000] software IO TLB: area num 8.
1148 02:24:36.941338 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1149 02:24:36.987938 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1150 02:24:36.993522 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1151 02:24:36.999026 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1152 02:24:37.004537 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1153 02:24:37.010079 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1154 02:24:37.015619 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1155 02:24:37.021121 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1156 02:24:37.026657 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1157 02:24:37.037601 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1158 02:24:37.048654 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1159 02:24:37.054220 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1160 02:24:37.059757 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1161 02:24:37.060240 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1162 02:24:37.069587 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1163 02:24:37.082282 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1164 02:24:37.091317 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1165 02:24:37.096869 <6>[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1166 02:24:37.102483 <6>[ 0.008794] Console: colour dummy device 80x25
1167 02:24:37.113460 <6>[ 0.012939] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1168 02:24:37.118935 <6>[ 0.023295] pid_max: default: 32768 minimum: 301
1169 02:24:37.124503 <6>[ 0.028189] LSM: initializing lsm=capability
1170 02:24:37.130009 <6>[ 0.032728] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1171 02:24:37.140985 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1172 02:24:37.146531 <6>[ 0.052299] rcu: Hierarchical SRCU implementation.
1173 02:24:37.152082 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1174 02:24:37.157575 <6>[ 0.058879] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1175 02:24:37.163120 <6>[ 0.071575] EFI services will not be available.
1176 02:24:37.168005 <6>[ 0.075232] smp: Bringing up secondary CPUs ...
1177 02:24:37.180240 <6>[ 0.077132] Detected VIPT I-cache on CPU1
1178 02:24:37.185756 <6>[ 0.077252] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1179 02:24:37.191283 <6>[ 0.078585] CPU features: detected: Spectre-v2
1180 02:24:37.196800 <6>[ 0.078600] CPU features: detected: Spectre-v4
1181 02:24:37.202358 <6>[ 0.078606] CPU features: detected: Spectre-BHB
1182 02:24:37.207839 <6>[ 0.078611] CPU features: detected: ARM erratum 858921
1183 02:24:37.213377 <6>[ 0.078619] Detected VIPT I-cache on CPU2
1184 02:24:37.218882 <6>[ 0.078692] arch_timer: Enabling local workaround for ARM erratum 858921
1185 02:24:37.225809 <6>[ 0.078710] arch_timer: CPU2: Trapping CNTVCT access
1186 02:24:37.229996 <6>[ 0.078720] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1187 02:24:37.235512 <6>[ 0.083580] Detected VIPT I-cache on CPU3
1188 02:24:37.240960 <6>[ 0.083626] arch_timer: Enabling local workaround for ARM erratum 858921
1189 02:24:37.246497 <6>[ 0.083636] arch_timer: CPU3: Trapping CNTVCT access
1190 02:24:37.251950 <6>[ 0.083643] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1191 02:24:37.257541 <6>[ 0.087622] Detected VIPT I-cache on CPU4
1192 02:24:37.263015 <6>[ 0.087669] arch_timer: Enabling local workaround for ARM erratum 858921
1193 02:24:37.268535 <6>[ 0.087679] arch_timer: CPU4: Trapping CNTVCT access
1194 02:24:37.279545 <6>[ 0.087686] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1195 02:24:37.280036 <6>[ 0.091617] Detected VIPT I-cache on CPU5
1196 02:24:37.290592 <6>[ 0.091664] arch_timer: Enabling local workaround for ARM erratum 858921
1197 02:24:37.291057 <6>[ 0.091674] arch_timer: CPU5: Trapping CNTVCT access
1198 02:24:37.301640 <6>[ 0.091682] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1199 02:24:37.302117 <6>[ 0.091795] smp: Brought up 1 node, 6 CPUs
1200 02:24:37.307209 <6>[ 0.213029] SMP: Total of 6 processors activated.
1201 02:24:37.312709 <6>[ 0.217934] CPU: All CPU(s) started at EL2
1202 02:24:37.318236 <6>[ 0.222284] CPU features: detected: 32-bit EL0 Support
1203 02:24:37.323773 <6>[ 0.227596] CPU features: detected: 32-bit EL1 Support
1204 02:24:37.329286 <6>[ 0.232942] CPU features: detected: CRC32 instructions
1205 02:24:37.334773 <6>[ 0.238345] alternatives: applying system-wide alternatives
1206 02:24:37.352731 <6>[ 0.245528] Memory: 3557436K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187796K reserved, 262144K cma-reserved)
1207 02:24:37.353218 <6>[ 0.259875] devtmpfs: initialized
1208 02:24:37.363737 <6>[ 0.269080] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1209 02:24:37.369396 <6>[ 0.273437] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1210 02:24:37.374860 <6>[ 0.284236] 21392 pages in range for non-PLT usage
1211 02:24:37.380399 <6>[ 0.284247] 512912 pages in range for PLT usage
1212 02:24:37.385917 <6>[ 0.285791] pinctrl core: initialized pinctrl subsystem
1213 02:24:37.391531 <6>[ 0.297878] DMI not present or invalid.
1214 02:24:37.396942 <6>[ 0.302155] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1215 02:24:37.402520 <6>[ 0.306900] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1216 02:24:37.413465 <6>[ 0.313676] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1217 02:24:37.419058 <6>[ 0.321776] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1218 02:24:37.424530 <6>[ 0.329269] audit: initializing netlink subsys (disabled)
1219 02:24:37.435520 <5>[ 0.334994] audit: type=2000 audit(0.256:1): state=initialized audit_enabled=0 res=1
1220 02:24:37.441084 <6>[ 0.336410] thermal_sys: Registered thermal governor 'step_wise'
1221 02:24:37.446594 <6>[ 0.342775] thermal_sys: Registered thermal governor 'power_allocator'
1222 02:24:37.452150 <6>[ 0.349037] cpuidle: using governor menu
1223 02:24:37.457675 <6>[ 0.360066] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1224 02:24:37.463183 <6>[ 0.366949] ASID allocator initialised with 65536 entries
1225 02:24:37.471405 <6>[ 0.374488] Serial: AMBA PL011 UART driver
1226 02:24:37.479220 <6>[ 0.385036] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1227 02:24:37.494479 <6>[ 0.400590] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1228 02:24:37.503543 <6>[ 0.403252] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1229 02:24:37.509117 <6>[ 0.416409] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1230 02:24:37.520151 <6>[ 0.419630] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1231 02:24:37.529172 <6>[ 0.428059] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1232 02:24:37.534782 <6>[ 0.435680] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1233 02:24:37.540298 <6>[ 0.449265] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1234 02:24:37.549290 <6>[ 0.451498] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1235 02:24:37.554848 <6>[ 0.457979] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1236 02:24:37.560425 <6>[ 0.464957] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1237 02:24:37.571373 <6>[ 0.471426] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1238 02:24:37.576938 <6>[ 0.478412] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1239 02:24:37.582542 <6>[ 0.484881] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1240 02:24:37.587947 <6>[ 0.491866] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1241 02:24:37.593539 <6>[ 0.499874] ACPI: Interpreter disabled.
1242 02:24:37.599000 <6>[ 0.505376] iommu: Default domain type: Translated
1243 02:24:37.604549 <6>[ 0.507399] iommu: DMA domain TLB invalidation policy: strict mode
1244 02:24:37.610011 <5>[ 0.514116] SCSI subsystem initialized
1245 02:24:37.615572 <6>[ 0.517981] usbcore: registered new interface driver usbfs
1246 02:24:37.621087 <6>[ 0.523457] usbcore: registered new interface driver hub
1247 02:24:37.626609 <6>[ 0.528973] usbcore: registered new device driver usb
1248 02:24:37.632112 <6>[ 0.535252] pps_core: LinuxPPS API ver. 1 registered
1249 02:24:37.637614 <6>[ 0.539393] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1250 02:24:37.643158 <6>[ 0.548712] PTP clock support registered
1251 02:24:37.648686 <6>[ 0.552952] EDAC MC: Ver: 3.0.0
1252 02:24:37.654188 <6>[ 0.556594] scmi_core: SCMI protocol bus registered
1253 02:24:37.654645 <6>[ 0.562199] FPGA manager framework
1254 02:24:37.659725 <6>[ 0.564973] Advanced Linux Sound Architecture Driver Initialized.
1255 02:24:37.665238 <6>[ 0.571916] vgaarb: loaded
1256 02:24:37.670745 <6>[ 0.574469] clocksource: Switched to clocksource arch_sys_counter
1257 02:24:37.676275 <5>[ 0.580620] VFS: Disk quotas dquot_6.6.0
1258 02:24:37.681794 <6>[ 0.584613] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1259 02:24:37.687323 <6>[ 0.591819] pnp: PnP ACPI: disabled
1260 02:24:37.692841 <6>[ 0.600395] NET: Registered PF_INET protocol family
1261 02:24:37.698359 <6>[ 0.600637] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1262 02:24:37.709391 <6>[ 0.610816] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1263 02:24:37.714908 <6>[ 0.616815] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1264 02:24:37.725903 <6>[ 0.624705] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1265 02:24:37.731572 <6>[ 0.632943] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1266 02:24:37.736990 <6>[ 0.640743] TCP: Hash tables configured (established 32768 bind 32768)
1267 02:24:37.742587 <6>[ 0.647215] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1268 02:24:37.753535 <6>[ 0.654063] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1269 02:24:37.759055 <6>[ 0.661493] NET: Registered PF_UNIX/PF_LOCAL protocol family
1270 02:24:37.764590 <6>[ 0.667590] RPC: Registered named UNIX socket transport module.
1271 02:24:37.770089 <6>[ 0.673351] RPC: Registered udp transport module.
1272 02:24:37.775638 <6>[ 0.678256] RPC: Registered tcp transport module.
1273 02:24:37.781143 <6>[ 0.683170] RPC: Registered tcp-with-tls transport module.
1274 02:24:37.786735 <6>[ 0.688863] RPC: Registered tcp NFSv4.1 backchannel transport module.
1275 02:24:37.792565 <6>[ 0.695512] PCI: CLS 0 bytes, default 64
1276 02:24:37.793023 <6>[ 0.699827] Unpacking initramfs...
1277 02:24:37.798000 <6>[ 0.709149] kvm [1]: nv: 554 coarse grained trap handlers
1278 02:24:37.803573 <6>[ 0.709457] kvm [1]: IPA Size Limit: 40 bits
1279 02:24:37.809048 <6>[ 0.715127] kvm [1]: vgic interrupt IRQ9
1280 02:24:37.814619 <6>[ 0.717821] kvm [1]: Hyp nVHE mode initialized successfully
1281 02:24:37.820192 <5>[ 0.725026] Initialise system trusted keyrings
1282 02:24:37.825762 <6>[ 0.728425] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1283 02:24:37.831263 <6>[ 0.735156] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1284 02:24:37.836771 <5>[ 0.741183] NFS: Registering the id_resolver key type
1285 02:24:37.842294 <5>[ 0.746227] Key type id_resolver registered
1286 02:24:37.847803 <5>[ 0.750578] Key type id_legacy registered
1287 02:24:37.854043 <6>[ 0.754833] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1288 02:24:37.859004 <6>[ 0.761704] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1289 02:24:37.867082 <6>[ 0.769483] 9p: Installing v9fs 9p2000 file system support
1290 02:24:37.904797 <5>[ 0.816144] Key type asymmetric registered
1291 02:24:37.910206 <5>[ 0.816187] Asymmetric key parser 'x509' registered
1292 02:24:37.921338 <6>[ 0.820048] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1293 02:24:37.921981 <6>[ 0.827571] io scheduler mq-deadline registered
1294 02:24:37.927123 <6>[ 0.832313] io scheduler kyber registered
1295 02:24:37.932260 <6>[ 0.836575] io scheduler bfq registered
1296 02:24:37.940119 <6>[ 0.842487] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1297 02:24:37.955040 <6>[ 0.862737] ledtrig-cpu: registered to indicate activity on CPUs
1298 02:24:37.988068 <6>[ 0.894125] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1299 02:24:38.006809 <6>[ 0.907213] Serial: 8250/16550 driver, 4 ports<6>[ 0.911818] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1300 02:24:38.012360 <6>[ 0.921434] printk: legacy console [ttyAML0] enabled
1301 02:24:38.017941 <6>[ 0.921434] printk: legacy console [ttyAML0] enabled
1302 02:24:38.023622 <6>[ 0.926239] printk: legacy bootconsole [meson0] disabled
1303 02:24:38.029046 <6>[ 0.926239] printk: legacy bootconsole [meson0] disabled
1304 02:24:38.034602 <6>[ 0.939279] msm_serial: driver initialized
1305 02:24:38.040160 <6>[ 0.942201] SuperH (H)SCI(F) driver initialized
1306 02:24:38.040634 <6>[ 0.946800] STM32 USART driver initialized
1307 02:24:38.047600 <5>[ 0.952965] random: crng init done
1308 02:24:38.054666 <6>[ 0.961909] loop: module loaded
1309 02:24:38.055132 <6>[ 0.963226] megasas: 07.727.03.00-rc1
1310 02:24:38.060176 <6>[ 0.970678] tun: Universal TUN/TAP device driver, 1.6
1311 02:24:38.065732 <6>[ 0.971887] thunder_xcv, ver 1.0
1312 02:24:38.071238 <6>[ 0.973841] thunder_bgx, ver 1.0
1313 02:24:38.071696 <6>[ 0.977327] nicpf, ver 1.0
1314 02:24:38.076802 <6>[ 0.981860] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1315 02:24:38.082345 <6>[ 0.987698] hns3: Copyright (c) 2017 Huawei Corporation.
1316 02:24:38.087891 <6>[ 0.993289] hclge is initializing
1317 02:24:38.093459 <6>[ 0.996828] e1000: Intel(R) PRO/1000 Network Driver
1318 02:24:38.098991 <6>[ 1.001907] e1000: Copyright (c) 1999-2006 Intel Corporation.
1319 02:24:38.104623 <6>[ 1.007931] e1000e: Intel(R) PRO/1000 Network Driver
1320 02:24:38.110075 <6>[ 1.013087] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1321 02:24:38.115629 <6>[ 1.019269] igb: Intel(R) Gigabit Ethernet Network Driver
1322 02:24:38.121152 <6>[ 1.024872] igb: Copyright (c) 2007-2014 Intel Corporation.
1323 02:24:38.126722 <6>[ 1.030706] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1324 02:24:38.132283 <6>[ 1.037179] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1325 02:24:38.137801 <6>[ 1.043946] sky2: driver version 1.30
1326 02:24:38.143360 <6>[ 1.049093] VFIO - User Level meta-driver version: 0.3
1327 02:24:38.148897 <6>[ 1.056566] usbcore: registered new interface driver usb-storage
1328 02:24:38.154925 <6>[ 1.062827] i2c_dev: i2c /dev entries driver
1329 02:24:38.167754 <6>[ 1.073815] sdhci: Secure Digital Host Controller Interface driver
1330 02:24:38.168241 <6>[ 1.074646] sdhci: Copyright(c) Pierre Ossman
1331 02:24:38.178862 <6>[ 1.080369] Synopsys Designware Multimedia Card Interface Driver
1332 02:24:38.184467 <6>[ 1.086936] sdhci-pltfm: SDHCI platform and OF driver helper
1333 02:24:38.184929 <6>[ 1.094537] meson-sm: secure-monitor enabled
1334 02:24:38.197272 <6>[ 1.097139] usbcore: registered new interface driver usbhid
1335 02:24:38.197739 <6>[ 1.101681] usbhid: USB HID core driver
1336 02:24:38.204937 <6>[ 1.116492] NET: Registered PF_PACKET protocol family
1337 02:24:38.210474 <6>[ 1.116585] 9pnet: Installing 9P2000 support
1338 02:24:38.217603 <5>[ 1.120749] Key type dns_resolver registered
1339 02:24:38.224949 <6>[ 1.132301] registered taskstats version 1
1340 02:24:38.225412 <5>[ 1.132460] Loading compiled-in X.509 certificates
1341 02:24:38.232258 <6>[ 1.141115] Demotion targets for Node 0: null
1342 02:24:38.272499 <6>[ 1.184017] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1343 02:24:38.278002 <6>[ 1.184062] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1344 02:24:38.289077 <4>[ 1.194271] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1345 02:24:38.294664 <4>[ 1.196836] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1346 02:24:38.300261 <6>[ 1.204396] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1347 02:24:38.305749 <6>[ 1.213659] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1348 02:24:38.316785 <6>[ 1.217102] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1349 02:24:38.327878 <6>[ 1.225086] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1350 02:24:38.333493 <6>[ 1.234634] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1351 02:24:38.339013 <6>[ 1.240842] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1352 02:24:38.344613 <6>[ 1.246481] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1353 02:24:38.350105 <6>[ 1.254355] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1354 02:24:38.355650 <6>[ 1.261603] hub 1-0:1.0: USB hub found
1355 02:24:38.361170 <6>[ 1.265117] hub 1-0:1.0: 2 ports detected
1356 02:24:38.366746 <6>[ 1.271212] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1357 02:24:38.372305 <6>[ 1.278087] hub 2-0:1.0: USB hub found
1358 02:24:38.377366 <6>[ 1.281666] hub 2-0:1.0: 1 port detected
1359 02:24:38.398981 <6>[ 1.307964] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1360 02:24:38.408759 <6>[ 1.317018] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1361 02:24:38.445472 <6>[ 1.353382] Trying to probe devices needed for running init ...
1362 02:24:38.611246 <6>[ 1.518506] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1363 02:24:38.751684 <6>[ 1.657755] mmc0: new ultra high speed SDR104 SDXC card at address e624
1364 02:24:38.757880 <6>[ 1.659677] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1365 02:24:38.758353 <6>[ 1.665282] mmcblk0: p1
1366 02:24:38.761766 <6>[ 1.672553] Freeing initrd memory: 22880K
1367 02:24:38.797871 <6>[ 1.709421] hub 1-1:1.0: USB hub found
1368 02:24:38.803646 <6>[ 1.709743] hub 1-1:1.0: 4 ports detected
1369 02:24:38.867295 <6>[ 1.774611] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1370 02:24:38.910609 <6>[ 1.822084] hub 2-1:1.0: USB hub found
1371 02:24:38.916288 <6>[ 1.822908] hub 2-1:1.0: 4 ports detected
1372 02:24:50.735275 <6>[ 13.646562] clk: Disabling unused clocks
1373 02:24:50.740632 <6>[ 13.646810] PM: genpd: Disabling unused power domains
1374 02:24:50.748939 <6>[ 13.650447] ALSA device list:
1375 02:24:50.749400 <6>[ 13.653636] No soundcards found.
1376 02:24:50.755835 <6>[ 13.667433] Freeing unused kernel memory: 10432K
1377 02:24:50.762291 <6>[ 13.667563] Run /init as init process
1378 02:24:50.769742 Loading, please wait...
1379 02:24:50.809215 Starting systemd-udevd version 252.22-1~deb12u1
1380 02:24:51.265587 <6>[ 14.174813] mc: Linux media interface: v0.10
1381 02:24:51.281714 <6>[ 14.187741] videodev: Linux video capture interface: v2.00
1382 02:24:51.289156 <3>[ 14.190819] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1383 02:24:51.296441 <6>[ 14.202451] panfrost ffe40000.gpu: clock rate = 24000000
1384 02:24:51.302578 <3>[ 14.203348] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1385 02:24:51.307832 <6>[ 14.218228] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1386 02:24:51.313433 <6>[ 14.219411] Registered IR keymap rc-empty
1387 02:24:51.324530 <6>[ 14.224411] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1388 02:24:51.329994 <6>[ 14.224661] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1389 02:24:51.341145 <6>[ 14.231000] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1390 02:24:51.346729 <6>[ 14.231858] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1391 02:24:51.352368 <6>[ 14.231869] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1392 02:24:51.357986 <6>[ 14.231874] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1393 02:24:51.363343 <6>[ 14.231936] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1394 02:24:51.368803 <6>[ 14.233891] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1395 02:24:51.374350 <6>[ 14.233902] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1396 02:24:51.385499 <6>[ 14.233907] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1397 02:24:51.390992 <6>[ 14.233912] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1398 02:24:51.396556 <6>[ 14.233916] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1399 02:24:51.407645 <6>[ 14.233921] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1400 02:24:51.413255 <6>[ 14.233925] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1401 02:24:51.418747 <6>[ 14.238740] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1402 02:24:51.424365 <6>[ 14.239393] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1403 02:24:51.429840 <6>[ 14.239403] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1404 02:24:51.440923 <6>[ 14.239407] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1405 02:24:51.446460 <6>[ 14.247588] rc rc0: sw decoder init
1406 02:24:51.457558 <6>[ 14.254161] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1407 02:24:51.463077 <6>[ 14.260598] meson-ir ff808000.ir: receiver initialized
1408 02:24:51.468619 <6>[ 14.261429] meson-vrtc ff8000a8.rtc: registered as rtc0
1409 02:24:51.474227 <6>[ 14.261456] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1410 02:24:51.479766 <6>[ 14.266865] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1411 02:24:51.490830 <4>[ 14.267661] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1412 02:24:51.501930 <6>[ 14.270575] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1413 02:24:51.513003 <6>[ 14.274172] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1414 02:24:51.518562 <4>[ 14.274584] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1415 02:24:51.524191 <6>[ 14.393377] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1416 02:24:51.535282 <6>[ 14.401715] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1417 02:24:51.540781 <3>[ 14.443862] meson-drm ff900000.vpu: DSI transceiver device is disabled
1418 02:24:51.546389 <6>[ 14.444113] usbcore: registered new device driver onboard-usb-dev
1419 02:24:51.551831 <6>[ 14.451711] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1420 02:24:51.561480 <6>[ 14.460537] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1421 02:24:51.747312 <6>[ 14.635286] Console: switching to colour frame buffer device 128x48
1422 02:24:51.756222 <6>[ 14.643132] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1423 02:24:51.764007 <6>[ 14.665127] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1424 02:24:51.866907 <4>[ 14.778496] rc rc0: two consecutive events of type space
1425 02:24:51.981885 <6>[ 14.893472] hub 1-1:1.0: USB hub found
1426 02:24:51.987598 <6>[ 14.893777] hub 1-1:1.0: 4 ports detected
1427 02:24:52.128483 <4>[ 15.034486] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1428 02:24:52.133936 <3>[ 15.036846] onboard-usb-dev 1-1: Failed to suspend device, error -32
1429 02:24:52.140927 <3>[ 15.043283] onboard-usb-dev 1-1: can't set config #1, error -71
1430 02:24:52.150561 Begin: Loading essential drivers ... done.
1431 02:24:52.156135 Begin: Running /scripts/init-premount ... done.
1432 02:24:52.161599 Begin: Mo<4>[ 15.066482] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1433 02:24:52.172689 unt<3>[ 15.073746] onboard-usb-dev 1-1: Failed to suspend device, error -32
1434 02:24:52.178302 <6>[ 15.080205] onboard-usb-dev 1-1: USB disconnect, device number 2
1435 02:24:52.183771 ing root file system ... Begin: Running /scripts/nfs-top ... done.
1436 02:24:52.189417 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1437 02:24:52.194881 Device /sys/class/net/end0 found
1438 02:24:52.195321 done.
1439 02:24:52.203254 Begin: Waiting up to 180 secs for any network device to become available ... done.
1440 02:24:52.257989 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.160272] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1441 02:24:52.258476
1442 02:24:52.347136 <6>[ 15.250582] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=31)
1443 02:24:52.360541 <6>[ 15.266647] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1444 02:24:52.366075 <6>[ 15.268831] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1445 02:24:52.375414 <6>[ 15.276217] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1446 02:24:52.427154 <6>[ 15.334499] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1447 02:24:52.622032 <6>[ 15.533538] hub 1-1:1.0: USB hub found
1448 02:24:52.627680 <6>[ 15.533884] hub 1-1:1.0: 4 ports detected
1449 02:24:52.754256 <6>[ 15.661410] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1450 02:24:53.010211 <6>[ 15.917390] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1451 02:24:53.851800 IP-Config: no response after 2 secs - giving up
1452 02:24:53.890034 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1453 02:24:55.325270 <6>[ 18.230764] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1454 02:24:56.127470 IP-Config: end0 guessed broadcast address 192.168.6.255
1455 02:24:56.132825 IP-Config: end0 complete (dhcp from 192.168.6.1):
1456 02:24:56.138361 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1457 02:24:56.149457 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1458 02:24:56.149890 rootserver: 192.168.6.1 rootpath:
1459 02:24:56.152929 filename :
1460 02:24:56.255724 done.
1461 02:24:56.265949 Begin: Running /scripts/nfs-bottom ... done.
1462 02:24:56.284705 Begin: Running /scripts/init-bottom ... done.
1463 02:24:56.592835 <30>[ 19.499732] systemd[1]: System time before build time, advancing clock.
1464 02:24:56.643324 <6>[ 19.554843] NET: Registered PF_INET6 protocol family
1465 02:24:56.648883 <6>[ 19.555631] Segment Routing with IPv6
1466 02:24:56.654174 <6>[ 19.558350] In-situ OAM (IOAM) with IPv6
1467 02:24:56.734335 <30>[ 19.618184] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1468 02:24:56.739875 <30>[ 19.645554] systemd[1]: Detected architecture arm64.
1469 02:24:56.740364
1470 02:24:56.748227 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1471 02:24:56.748668
1472 02:24:56.756456 <30>[ 19.664139] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1473 02:24:57.415021 <30>[ 20.321507] systemd[1]: Queued start job for default target graphical.target.
1474 02:24:57.442926 <30>[ 20.348851] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1475 02:24:57.450533 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1476 02:24:57.461668 <30>[ 20.367536] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1477 02:24:57.469924 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1478 02:24:57.481496 <30>[ 20.387474] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1479 02:24:57.490575 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1480 02:24:57.501486 <30>[ 20.407247] systemd[1]: Created slice user.slice - User and Session Slice.
1481 02:24:57.507847 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1482 02:24:57.518952 <30>[ 20.422741] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1483 02:24:57.530405 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1484 02:24:57.541506 <30>[ 20.442676] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1485 02:24:57.548086 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1486 02:24:57.570265 <30>[ 20.462643] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1487 02:24:57.575700 <30>[ 20.476694] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1488 02:24:57.583375 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1489 02:24:57.594533 <30>[ 20.498559] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1490 02:24:57.600608 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1491 02:24:57.616454 <30>[ 20.522579] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1492 02:24:57.630192 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1493 02:24:57.635695 <30>[ 20.542605] systemd[1]: Reached target paths.target - Path Units.
1494 02:24:57.644213 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1495 02:24:57.649683 <30>[ 20.558581] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1496 02:24:57.661421 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1497 02:24:57.666972 <30>[ 20.574565] systemd[1]: Reached target slices.target - Slice Units.
1498 02:24:57.675209 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1499 02:24:57.680682 <30>[ 20.590578] systemd[1]: Reached target swap.target - Swaps.
1500 02:24:57.688596 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1501 02:24:57.700607 <30>[ 20.606610] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1502 02:24:57.709422 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1503 02:24:57.724676 <30>[ 20.630757] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1504 02:24:57.733916 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1505 02:24:57.745815 <30>[ 20.651895] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1506 02:24:57.754606 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1507 02:24:57.769375 <30>[ 20.675481] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1508 02:24:57.778809 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1509 02:24:57.792812 <30>[ 20.698881] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1510 02:24:57.799686 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1511 02:24:57.810730 <30>[ 20.715505] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1512 02:24:57.818631 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1513 02:24:57.830252 <30>[ 20.736360] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1514 02:24:57.835876 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1515 02:24:57.848720 <30>[ 20.754804] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1516 02:24:57.857294 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1517 02:24:57.896705 <30>[ 20.802677] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1518 02:24:57.903386 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1519 02:24:57.915157 <30>[ 20.821222] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1520 02:24:57.922806 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1521 02:24:57.935229 <30>[ 20.841207] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1522 02:24:57.942988 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1523 02:24:57.959592 <30>[ 20.858903] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1524 02:24:57.970665 <30>[ 20.872035] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1525 02:24:57.976567 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1526 02:24:57.995315 <30>[ 20.901328] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1527 02:24:58.003256 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1528 02:24:58.015370 <30>[ 20.921437] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1529 02:24:58.023060 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1530 02:24:58.035358 <30>[ 20.941254] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1531 02:24:58.051284 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel <6>[ 20.951513] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1532 02:24:58.051831 Module drm...
1533 02:24:58.063473 <30>[ 20.969530] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1534 02:24:58.071791 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1535 02:24:58.083369 <30>[ 20.989343] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1536 02:24:58.090581 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1537 02:24:58.100420 <6>[ 21.011904] fuse: init (API version 7.41)
1538 02:24:58.111434 <30>[ 21.013461] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1539 02:24:58.115368 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1540 02:24:58.136983 <30>[ 21.043045] systemd[1]: Starting systemd-journald.service - Journal Service...
1541 02:24:58.143460 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1542 02:24:58.160471 <30>[ 21.066455] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1543 02:24:58.168770 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1544 02:24:58.180520 <30>[ 21.084756] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1545 02:24:58.189064 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1546 02:24:58.202705 <30>[ 21.108704] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1547 02:24:58.211478 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1548 02:24:58.224525 <30>[ 21.130590] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1549 02:24:58.232595 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1550 02:24:58.260123 <30>[ 21.166174] systemd[1]: Started systemd-journald.service - Journal Service.
1551 02:24:58.266961 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1552 02:24:58.281327 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1553 02:24:58.288389 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1554 02:24:58.305348 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1555 02:24:58.321491 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1556 02:24:58.337859 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1557 02:24:58.349726 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1558 02:24:58.365443 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1559 02:24:58.381755 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1560 02:24:58.397543 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1561 02:24:58.413578 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1562 02:24:58.429566 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1563 02:24:58.445463 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1564 02:24:58.461486 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1565 02:24:58.477824 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1566 02:24:58.548101 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1567 02:24:58.559899 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1568 02:24:58.577300 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1569 02:24:58.594380 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1570 02:24:58.609843 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1571 02:24:58.617193 <46>[ 21.521880] systemd-journald[228]: Received client request to flush runtime journal.
1572 02:24:58.635512 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1573 02:24:58.665266 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1574 02:24:58.674650 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1575 02:24:58.688388 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1576 02:24:58.705642 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1577 02:24:58.711899 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1578 02:24:58.779655 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1579 02:24:58.828694 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1580 02:24:58.924978 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1581 02:24:58.940826 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1582 02:24:58.957211 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1583 02:24:58.972280 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1584 02:24:59.016229 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1585 02:24:59.026824 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1586 02:24:59.239615 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1587 02:24:59.288582 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1588 02:24:59.301721 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1589 02:24:59.353589 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1590 02:24:59.419925 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1591 02:24:59.426395 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1592 02:24:59.462013 <5>[ 22.368159] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1593 02:24:59.500564 <5>[ 22.406108] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1594 02:24:59.505672 <5>[ 22.407377] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1595 02:24:59.516671 [[<4>[ 22.416372] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1596 02:24:59.517155 <6>[ 22.424171] cfg80211: failed to load regulatory.db
1597 02:24:59.527572 0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1598 02:24:59.584835 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1599 02:24:59.591567 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1600 02:24:59.617482 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1601 02:24:59.623713 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1602 02:24:59.644896 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1603 02:24:59.652945 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1604 02:24:59.664634 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1605 02:24:59.681289 <46>[ 22.577505] systemd-journald[228]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1606 02:24:59.696986 <46>[ 22.590652] systemd-journald[228]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1607 02:24:59.722370 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1608 02:24:59.736658 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1609 02:24:59.744302 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1610 02:24:59.821350 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1611 02:24:59.841624 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1612 02:24:59.855773 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1613 02:24:59.892731 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1614 02:24:59.898912 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1615 02:24:59.913117 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1616 02:24:59.920220 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1617 02:24:59.996008 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1618 02:25:00.014536 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1619 02:25:00.047097 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1620 02:25:00.069560 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1621 02:25:00.128715 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1622 02:25:00.144774 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1623 02:25:00.173782 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1624 02:25:00.181215 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1625 02:25:00.193527 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1626 02:25:00.212052 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1627 02:25:00.251893 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1628 02:25:00.263734 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1629 02:25:00.278315 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1630 02:25:00.285152 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1631 02:25:00.305658 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1632 02:25:00.316797 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1633 02:25:00.352540 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1634 02:25:00.395781 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1635 02:25:00.471894
1636 02:25:00.472514 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1637 02:25:00.472941
1638 02:25:00.479030 debian-bookworm-arm64 login: root (automatic login)
1639 02:25:00.479499
1640 02:25:00.616679 Linux debian-bookworm-arm64 6.12.0-rc2 #1 SMP PREEMPT Fri Nov 8 00:30:12 UTC 2024 aarch64
1641 02:25:00.617275
1642 02:25:00.622124 The programs included with the Debian GNU/Linux system are free software;
1643 02:25:00.631091 the exact distribution terms for each program are described in the
1644 02:25:00.631566 individual files in /usr/share/doc/*/copyright.
1645 02:25:00.632039
1646 02:25:00.636704 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1647 02:25:00.641883 permitted by applicable law.
1648 02:25:01.296892 Matched prompt #10: / #
1650 02:25:01.298453 Setting prompt string to ['/ #']
1651 02:25:01.299036 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1653 02:25:01.300557 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1654 02:25:01.301104 start: 2.4.5 expect-shell-connection (timeout 00:03:17) [common]
1655 02:25:01.301536 Setting prompt string to ['/ #']
1656 02:25:01.301941 Forcing a shell prompt, looking for ['/ #']
1658 02:25:01.352919 / #
1659 02:25:01.353672 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1660 02:25:01.354136 Waiting using forced prompt support (timeout 00:02:30)
1661 02:25:01.359705
1662 02:25:01.360591 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1663 02:25:01.361172 start: 2.4.6 export-device-env (timeout 00:03:17) [common]
1664 02:25:01.361657 Sending with 10 millisecond of delay
1666 02:25:06.363646 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/956803/extract-nfsrootfs-ccv3mfs8'
1667 02:25:06.374578 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/956803/extract-nfsrootfs-ccv3mfs8'
1668 02:25:06.375506 Sending with 10 millisecond of delay
1670 02:25:08.473514 / # export NFS_SERVER_IP='192.168.6.2'
1671 02:25:08.484428 export NFS_SERVER_IP='192.168.6.2'
1672 02:25:08.485284 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1673 02:25:08.485868 end: 2.4 uboot-commands (duration 00:01:50) [common]
1674 02:25:08.486443 end: 2 uboot-action (duration 00:01:50) [common]
1675 02:25:08.487010 start: 3 lava-test-retry (timeout 00:06:53) [common]
1676 02:25:08.487590 start: 3.1 lava-test-shell (timeout 00:06:53) [common]
1677 02:25:08.488105 Using namespace: common
1679 02:25:08.589326 / # #
1680 02:25:08.589873 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1681 02:25:08.594783 #
1682 02:25:08.595280 Using /lava-956803
1684 02:25:08.696035 / # export SHELL=/bin/bash
1685 02:25:08.701631 export SHELL=/bin/bash
1687 02:25:08.802990 / # . /lava-956803/environment
1688 02:25:08.807809 . /lava-956803/environment
1690 02:25:08.912766 / # /lava-956803/bin/lava-test-runner /lava-956803/0
1691 02:25:08.913399 Test shell timeout: 10s (minimum of the action and connection timeout)
1692 02:25:08.917626 /lava-956803/bin/lava-test-runner /lava-956803/0
1693 02:25:09.112270 + export TESTRUN_ID=0_timesync-off
1694 02:25:09.119895 + TESTRUN_ID=0_timesync-off
1695 02:25:09.120430 + cd /lava-956803/0/tests/0_timesync-off
1696 02:25:09.120861 ++ cat uuid
1697 02:25:09.130618 + UUID=956803_1.6.2.4.1
1698 02:25:09.131122 + set +x
1699 02:25:09.139126 <LAVA_SIGNAL_STARTRUN 0_timesync-off 956803_1.6.2.4.1>
1700 02:25:09.139598 + systemctl stop systemd-timesyncd
1701 02:25:09.140353 Received signal: <STARTRUN> 0_timesync-off 956803_1.6.2.4.1
1702 02:25:09.140835 Starting test lava.0_timesync-off (956803_1.6.2.4.1)
1703 02:25:09.141374 Skipping test definition patterns.
1704 02:25:09.201178 + set +x
1705 02:25:09.201753 <LAVA_SIGNAL_ENDRUN 0_timesync-off 956803_1.6.2.4.1>
1706 02:25:09.202432 Received signal: <ENDRUN> 0_timesync-off 956803_1.6.2.4.1
1707 02:25:09.202927 Ending use of test pattern.
1708 02:25:09.203334 Ending test lava.0_timesync-off (956803_1.6.2.4.1), duration 0.06
1710 02:25:09.279916 + export TESTRUN_ID=1_kselftest-alsa
1711 02:25:09.288400 + TESTRUN_ID=1_kselftest-alsa
1712 02:25:09.289035 + cd /lava-956803/0/tests/1_kselftest-alsa
1713 02:25:09.289584 ++ cat uuid
1714 02:25:09.296227 + UUID=956803_1.6.2.4.5
1715 02:25:09.296838 + set +x
1716 02:25:09.301706 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 956803_1.6.2.4.5>
1717 02:25:09.302188 + cd ./automated/linux/kselftest/
1718 02:25:09.302882 Received signal: <STARTRUN> 1_kselftest-alsa 956803_1.6.2.4.5
1719 02:25:09.303311 Starting test lava.1_kselftest-alsa (956803_1.6.2.4.5)
1720 02:25:09.303797 Skipping test definition patterns.
1721 02:25:09.332322 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1722 02:25:09.362155 INFO: install_deps skipped
1723 02:25:09.478199 --2024-11-08 02:25:09-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-244-g80b3d72150d5/arm64/defconfig/gcc-12/kselftest.tar.xz
1724 02:25:09.508109 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1725 02:25:09.652795 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1726 02:25:09.801426 HTTP request sent, awaiting response... 200 OK
1727 02:25:09.802040 Length: 6923632 (6.6M) [application/octet-stream]
1728 02:25:09.806922 Saving to: 'kselftest_armhf.tar.gz'
1729 02:25:09.807395
1730 02:25:11.243315
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 49.92K 175KB/s
kselftest_armhf.tar 3%[ ] 216.29K 379KB/s
kselftest_armhf.tar 13%[=> ] 889.89K 1.02MB/s
kselftest_armhf.tar 45%[========> ] 3.02M 2.32MB/s
kselftest_armhf.tar 100%[===================>] 6.60M 4.59MB/s in 1.4s
1731 02:25:11.244015
1732 02:25:11.340181 2024-11-08 02:25:11 (4.59 MB/s) - 'kselftest_armhf.tar.gz' saved [6923632/6923632]
1733 02:25:11.340801
1734 02:25:20.382698 skiplist:
1735 02:25:20.383316 ========================================
1736 02:25:20.388322 ========================================
1737 02:25:20.424788 alsa:mixer-test
1738 02:25:20.425295 alsa:pcm-test
1739 02:25:20.425711 alsa:test-pcmtest-driver
1740 02:25:20.428727 alsa:utimer-test
1741 02:25:20.440413 ============== Tests to run ===============
1742 02:25:20.440892 alsa:mixer-test
1743 02:25:20.445814 alsa:pcm-test
1744 02:25:20.446261 alsa:test-pcmtest-driver
1745 02:25:20.446669 alsa:utimer-test
1746 02:25:20.454139 ===========End Tests to run ===============
1747 02:25:20.454593 shardfile-alsa pass
1748 02:25:20.562666 <12>[ 43.471908] kselftest: Running tests in alsa
1749 02:25:20.569300 TAP version 13
1750 02:25:20.576833 1..4
1751 02:25:20.597883 # timeout set to 45
1752 02:25:20.598355 # selftests: alsa: mixer-test
1753 02:25:20.753273 # TAP version 13
1754 02:25:20.753866 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1755 02:25:20.758661 # 1..427
1756 02:25:20.759106 # ok 1 get_value.LCALTA.60
1757 02:25:20.759519 # # LCALTA.60 TDMOUT_A SRC SEL
1758 02:25:20.764134 # ok 2 name.LCALTA.60
1759 02:25:20.764567 # ok 3 write_default.LCALTA.60
1760 02:25:20.767959 # ok 4 write_valid.LCALTA.60
1761 02:25:20.773234 # ok 5 write_invalid.LCALTA.60
1762 02:25:20.773664 # ok 6 event_missing.LCALTA.60
1763 02:25:20.778749 # ok 7 event_spurious.LCALTA.60
1764 02:25:20.779178 # ok 8 get_value.LCALTA.59
1765 02:25:20.784264 # # LCALTA.59 TDMOUT_B SRC SEL
1766 02:25:20.784686 # ok 9 name.LCALTA.59
1767 02:25:20.788287 # ok 10 write_default.LCALTA.59
1768 02:25:20.788716 # ok 11 write_valid.LCALTA.59
1769 02:25:20.793719 # ok 12 write_invalid.LCALTA.59
1770 02:25:20.794159 # ok 13 event_missing.LCALTA.59
1771 02:25:20.799217 # ok 14 event_spurious.LCALTA.59
1772 02:25:20.799661 # ok 15 get_value.LCALTA.58
1773 02:25:20.804824 # # LCALTA.58 TDMOUT_C SRC SEL
1774 02:25:20.805282 # ok 16 name.LCALTA.58
1775 02:25:20.810327 # ok 17 write_default.LCALTA.58
1776 02:25:20.810775 # ok 18 write_valid.LCALTA.58
1777 02:25:20.815853 # ok 19 write_invalid.LCALTA.58
1778 02:25:20.816332 # ok 20 event_missing.LCALTA.58
1779 02:25:20.821597 # ok 21 event_spurious.LCALTA.58
1780 02:25:20.822047 # ok 22 get_value.LCALTA.57
1781 02:25:20.826985 # # LCALTA.57 TDMIN_A SRC SEL
1782 02:25:20.827433 # ok 23 name.LCALTA.57
1783 02:25:20.832496 # ok 24 write_default.LCALTA.57
1784 02:25:20.832936 # ok 25 write_valid.LCALTA.57
1785 02:25:20.838090 # ok 26 write_invalid.LCALTA.57
1786 02:25:20.838530 # ok 27 event_missing.LCALTA.57
1787 02:25:20.843599 # ok 28 event_spurious.LCALTA.57
1788 02:25:20.844067 # ok 29 get_value.LCALTA.56
1789 02:25:20.849164 # # LCALTA.56 TDMIN_B SRC SEL
1790 02:25:20.849601 # ok 30 name.LCALTA.56
1791 02:25:20.850006 # ok 31 write_default.LCALTA.56
1792 02:25:20.854648 # ok 32 write_valid.LCALTA.56
1793 02:25:20.865788 # ok 33 wr<3>[ 43.764312] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1794 02:25:20.871302 ite_invalid.LCALTA.56
1795 02:25:20.871743 # ok 34 event_missing.LCALTA.56
1796 02:25:20.876745 # ok 35 event_spurious.LCALTA.56
1797 02:25:20.877180 # ok 36 get_value.LCALTA.55
1798 02:25:20.882383 # # LCALTA.55 TDMIN_C SRC SEL
1799 02:25:20.882823 # ok 37 name.LCALTA.55
1800 02:25:20.887837 # ok 38 write_default.LCALTA.55
1801 02:25:20.888304 # ok 39 write_valid.LCALTA.55
1802 02:25:20.893365 # ok 40 write_invalid.LCALTA.55
1803 02:25:20.893798 # ok 41 event_missing.LCALTA.55
1804 02:25:20.898903 # ok 42 event_spurious.LCALTA.55
1805 02:25:20.899329 # ok 43 get_value.LCALTA.54
1806 02:25:20.904482 # # LCALTA.54 ACODEC Left DAC Sel
1807 02:25:20.904916 # ok 44 name.LCALTA.54
1808 02:25:20.905320 # ok 45 write_default.LCALTA.54
1809 02:25:20.910042 # ok 46 write_valid.LCALTA.54
1810 02:25:20.910478 # ok 47 write_invalid.LCALTA.54
1811 02:25:20.915635 # ok 48 event_missing.LCALTA.54
1812 02:25:20.921206 # ok 49 event_spurious.LCALTA.54
1813 02:25:20.921688 # ok 50 get_value.LCALTA.53
1814 02:25:20.926663 # # LCALTA.53 ACODEC Right DAC Sel
1815 02:25:20.927136 # ok 51 name.LCALTA.53
1816 02:25:20.927574 # ok 52 write_default.LCALTA.53
1817 02:25:20.932230 # ok 53 write_valid.LCALTA.53
1818 02:25:20.932684 # ok 54 write_invalid.LCALTA.53
1819 02:25:20.937761 # ok 55 event_missing.LCALTA.53
1820 02:25:20.938233 # ok 56 event_spurious.LCALTA.53
1821 02:25:20.943377 # ok 57 get_value.LCALTA.52
1822 02:25:20.948851 # # LCALTA.52 TOACODEC OUT EN Switch
1823 02:25:20.949324 # ok 58 name.LCALTA.52
1824 02:25:20.949742 # ok 59 write_default.LCALTA.52
1825 02:25:20.954425 # ok 60 write_valid.LCALTA.52
1826 02:25:20.954902 # ok 61 write_invalid.LCALTA.52
1827 02:25:20.959930 # ok 62 event_missing.LCALTA.52
1828 02:25:20.960475 # ok 63 event_spurious.LCALTA.52
1829 02:25:20.965469 # ok 64 get_value.LCALTA.51
1830 02:25:20.965903 # # LCALTA.51 TOACODEC SRC
1831 02:25:20.971005 # ok 65 name.LCALTA.51
1832 02:25:20.971434 # ok 66 write_default.LCALTA.51
1833 02:25:20.976563 # ok 67 write_valid.LCALTA.51
1834 02:25:20.976993 # ok 68 write_invalid.LCALTA.51
1835 02:25:20.982112 # ok 69 event_missing.LCALTA.51
1836 02:25:20.982534 # ok 70 event_spurious.LCALTA.51
1837 02:25:20.987641 # ok 71 get_value.LCALTA.50
1838 02:25:20.988153 # # LCALTA.50 TOHDMITX SPDIF SRC
1839 02:25:20.993256 # ok 72 name.LCALTA.50
1840 02:25:20.993728 # ok 73 write_default.LCALTA.50
1841 02:25:20.998802 # ok 74 write_valid.LCALTA.50
1842 02:25:20.999261 # ok 75 write_invalid.LCALTA.50
1843 02:25:21.004398 # ok 76 event_missing.LCALTA.50
1844 02:25:21.004866 # ok 77 event_spurious.LCALTA.50
1845 02:25:21.009918 # ok 78 get_value.LCALTA.49
1846 02:25:21.010375 # # LCALTA.49 TOHDMITX Switch
1847 02:25:21.015442 # ok 79 name.LCALTA.49
1848 02:25:21.015895 # ok 80 write_default.LCALTA.49
1849 02:25:21.021000 # ok 81 write_valid.LCALTA.49
1850 02:25:21.021543 # ok 82 write_invalid.LCALTA.49
1851 02:25:21.026578 # ok 83 event_missing.LCALTA.49
1852 02:25:21.027126 # ok 84 event_spurious.LCALTA.49
1853 02:25:21.032253 # ok 85 get_value.LCALTA.48
1854 02:25:21.032972 # # LCALTA.48 TOHDMITX I2S SRC
1855 02:25:21.033510 # ok 86 name.LCALTA.48
1856 02:25:21.037721 # ok 87 write_default.LCALTA.48
1857 02:25:21.038352 # ok 88 write_valid.LCALTA.48
1858 02:25:21.043203 # ok 89 write_invalid.LCALTA.48
1859 02:25:21.043814 # ok 90 event_missing.LCALTA.48
1860 02:25:21.048724 # ok 91 event_spurious.LCALTA.48
1861 02:25:21.049326 # ok 92 get_value.LCALTA.47
1862 02:25:21.054336 # # LCALTA.47 TODDR_C SRC SEL
1863 02:25:21.054678 # ok 93 name.LCALTA.47
1864 02:25:21.059832 # ok 94 write_default.LCALTA.47
1865 02:25:21.060209 # ok 95 write_valid.LCALTA.47
1866 02:25:21.065841 # ok 96 write_invalid.LCALTA.47
1867 02:25:21.066192 # ok 97 event_missing.LCALTA.47
1868 02:25:21.070953 # ok 98 event_spurious.LCALTA.47
1869 02:25:21.071248 # ok 99 get_value.LCALTA.46
1870 02:25:21.076486 # # LCALTA.46 TODDR_B SRC SEL
1871 02:25:21.076776 # ok 100 name.LCALTA.46
1872 02:25:21.082027 # ok 101 write_default.LCALTA.46
1873 02:25:21.082313 # ok 102 write_valid.LCALTA.46
1874 02:25:21.087661 # ok 103 write_invalid.LCALTA.46
1875 02:25:21.088366 # ok 104 event_missing.LCALTA.46
1876 02:25:21.093259 # ok 105 event_spurious.LCALTA.46
1877 02:25:21.093932 # ok 106 get_value.LCALTA.45
1878 02:25:21.098707 # # LCALTA.45 TODDR_A SRC SEL
1879 02:25:21.099288 # ok 107 name.LCALTA.45
1880 02:25:21.104270 # ok 108 write_default.LCALTA.45
1881 02:25:21.104845 # ok 109 write_valid.LCALTA.45
1882 02:25:21.109833 # ok 110 write_invalid.LCALTA.45
1883 02:25:21.110390 # ok 111 event_missing.LCALTA.45
1884 02:25:21.115400 # ok 112 event_spurious.LCALTA.45
1885 02:25:21.115951 # ok 113 get_value.LCALTA.44
1886 02:25:21.120935 # # LCALTA.44 FRDDR_C SINK 3 SEL
1887 02:25:21.121542 # ok 114 name.LCALTA.44
1888 02:25:21.126577 # ok 115 write_default.LCALTA.44
1889 02:25:21.127150 # ok 116 write_valid.LCALTA.44
1890 02:25:21.132056 # ok 117 write_invalid.LCALTA.44
1891 02:25:21.132632 # ok 118 event_missing.LCALTA.44
1892 02:25:21.137541 # ok 119 event_spurious.LCALTA.44
1893 02:25:21.138100 # ok 120 get_value.LCALTA.43
1894 02:25:21.143052 # # LCALTA.43 FRDDR_C SINK 2 SEL
1895 02:25:21.143605 # ok 121 name.LCALTA.43
1896 02:25:21.148612 # ok 122 write_default.LCALTA.43
1897 02:25:21.149167 # ok 123 write_valid.LCALTA.43
1898 02:25:21.154161 # ok 124 write_invalid.LCALTA.43
1899 02:25:21.154500 # ok 125 event_missing.LCALTA.43
1900 02:25:21.159696 # ok 126 event_spurious.LCALTA.43
1901 02:25:21.160118 # ok 127 get_value.LCALTA.42
1902 02:25:21.165221 # # LCALTA.42 FRDDR_C SINK 1 SEL
1903 02:25:21.165571 # ok 128 name.LCALTA.42
1904 02:25:21.170988 # ok 129 write_default.LCALTA.42
1905 02:25:21.171344 # ok 130 write_valid.LCALTA.42
1906 02:25:21.176508 # ok 131 write_invalid.LCALTA.42
1907 02:25:21.177143 # ok 132 event_missing.LCALTA.42
1908 02:25:21.181916 # ok 133 event_spurious.LCALTA.42
1909 02:25:21.182494 # ok 134 get_value.LCALTA.41
1910 02:25:21.187469 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1911 02:25:21.188081 # ok 135 name.LCALTA.41
1912 02:25:21.192963 # ok 136 write_default.LCALTA.41
1913 02:25:21.193524 # ok 137 write_valid.LCALTA.41
1914 02:25:21.198502 # ok 138 write_invalid.LCALTA.41
1915 02:25:21.199070 # ok 139 event_missing.LCALTA.41
1916 02:25:21.204086 # ok 140 event_spurious.LCALTA.41
1917 02:25:21.204676 # ok 141 get_value.LCALTA.40
1918 02:25:21.209666 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1919 02:25:21.210222 # ok 142 name.LCALTA.40
1920 02:25:21.215150 # ok 143 write_default.LCALTA.40
1921 02:25:21.215707 # ok 144 write_valid.LCALTA.40
1922 02:25:21.220698 # ok 145 write_invalid.LCALTA.40
1923 02:25:21.226233 # ok 146 event_missing.LCALTA.40
1924 02:25:21.226778 # ok 147 event_spurious.LCALTA.40
1925 02:25:21.231789 # ok 148 get_value.LCALTA.39
1926 02:25:21.232383 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1927 02:25:21.237372 # ok 149 name.LCALTA.39
1928 02:25:21.237951 # ok 150 write_default.LCALTA.39
1929 02:25:21.242884 # ok 151 write_valid.LCALTA.39
1930 02:25:21.243445 # ok 152 write_invalid.LCALTA.39
1931 02:25:21.248503 # ok 153 event_missing.LCALTA.39
1932 02:25:21.249071 # ok 154 event_spurious.LCALTA.39
1933 02:25:21.254001 # ok 155 get_value.LCALTA.38
1934 02:25:21.254556 # # LCALTA.38 FRDDR_B SINK 3 SEL
1935 02:25:21.259521 # ok 156 name.LCALTA.38
1936 02:25:21.260101 # ok 157 write_default.LCALTA.38
1937 02:25:21.265076 # ok 158 write_valid.LCALTA.38
1938 02:25:21.265623 # ok 159 write_invalid.LCALTA.38
1939 02:25:21.270644 # ok 160 event_missing.LCALTA.38
1940 02:25:21.271211 # ok 161 event_spurious.LCALTA.38
1941 02:25:21.276220 # ok 162 get_value.LCALTA.37
1942 02:25:21.276795 # # LCALTA.37 FRDDR_B SINK 2 SEL
1943 02:25:21.281743 # ok 163 name.LCALTA.37
1944 02:25:21.282288 # ok 164 write_default.LCALTA.37
1945 02:25:21.287264 # ok 165 write_valid.LCALTA.37
1946 02:25:21.287807 # ok 166 write_invalid.LCALTA.37
1947 02:25:21.292815 # ok 167 event_missing.LCALTA.37
1948 02:25:21.293360 # ok 168 event_spurious.LCALTA.37
1949 02:25:21.298364 # ok 169 get_value.LCALTA.36
1950 02:25:21.298902 # # LCALTA.36 FRDDR_B SINK 1 SEL
1951 02:25:21.303924 # ok 170 name.LCALTA.36
1952 02:25:21.304547 # ok 171 write_default.LCALTA.36
1953 02:25:21.309498 # ok 172 write_valid.LCALTA.36
1954 02:25:21.310055 # ok 173 write_invalid.LCALTA.36
1955 02:25:21.315010 # ok 174 event_missing.LCALTA.36
1956 02:25:21.315560 # ok 175 event_spurious.LCALTA.36
1957 02:25:21.320570 # ok 176 get_value.LCALTA.35
1958 02:25:21.321120 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1959 02:25:21.326068 # ok 177 name.LCALTA.35
1960 02:25:21.326618 # ok 178 write_default.LCALTA.35
1961 02:25:21.331605 # ok 179 write_valid.LCALTA.35
1962 02:25:21.332197 # ok 180 write_invalid.LCALTA.35
1963 02:25:21.337211 # ok 181 event_missing.LCALTA.35
1964 02:25:21.337796 # ok 182 event_spurious.LCALTA.35
1965 02:25:21.342768 # ok 183 get_value.LCALTA.34
1966 02:25:21.343356 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1967 02:25:21.348280 # ok 184 name.LCALTA.34
1968 02:25:21.348843 # ok 185 write_default.LCALTA.34
1969 02:25:21.353819 # ok 186 write_valid.LCALTA.34
1970 02:25:21.354366 # ok 187 write_invalid.LCALTA.34
1971 02:25:21.359356 # ok 188 event_missing.LCALTA.34
1972 02:25:21.364908 # ok 189 event_spurious.LCALTA.34
1973 02:25:21.365464 # ok 190 get_value.LCALTA.33
1974 02:25:21.370566 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1975 02:25:21.371113 # ok 191 name.LCALTA.33
1976 02:25:21.376145 # ok 192 write_default.LCALTA.33
1977 02:25:21.376708 # ok 193 write_valid.LCALTA.33
1978 02:25:21.381653 # ok 194 write_invalid.LCALTA.33
1979 02:25:21.382211 # ok 195 event_missing.LCALTA.33
1980 02:25:21.387169 # ok 196 event_spurious.LCALTA.33
1981 02:25:21.387725 # ok 197 get_value.LCALTA.32
1982 02:25:21.392613 # # LCALTA.32 FRDDR_A SINK 3 SEL
1983 02:25:21.393161 # ok 198 name.LCALTA.32
1984 02:25:21.398193 # ok 199 write_default.LCALTA.32
1985 02:25:21.398756 # ok 200 write_valid.LCALTA.32
1986 02:25:21.403692 # ok 201 write_invalid.LCALTA.32
1987 02:25:21.404288 # ok 202 event_missing.LCALTA.32
1988 02:25:21.410264 # ok 203 event_spurious.LCALTA.32
1989 02:25:21.410819 # ok 204 get_value.LCALTA.31
1990 02:25:21.414869 # # LCALTA.31 FRDDR_A SINK 2 SEL
1991 02:25:21.415473 # ok 205 name.LCALTA.31
1992 02:25:21.420357 # ok 206 write_default.LCALTA.31
1993 02:25:21.420907 # ok 207 write_valid.LCALTA.31
1994 02:25:21.425878 # ok 208 write_invalid.LCALTA.31
1995 02:25:21.426430 # ok 209 event_missing.LCALTA.31
1996 02:25:21.431484 # ok 210 event_spurious.LCALTA.31
1997 02:25:21.432070 # ok 211 get_value.LCALTA.30
1998 02:25:21.436961 # # LCALTA.30 FRDDR_A SINK 1 SEL
1999 02:25:21.437505 # ok 212 name.LCALTA.30
2000 02:25:21.442546 # ok 213 write_default.LCALTA.30
2001 02:25:21.443095 # ok 214 write_valid.LCALTA.30
2002 02:25:21.448101 # ok 215 write_invalid.LCALTA.30
2003 02:25:21.448653 # ok 216 event_missing.LCALTA.30
2004 02:25:21.453628 # ok 217 event_spurious.LCALTA.30
2005 02:25:21.454180 # ok 218 get_value.LCALTA.29
2006 02:25:21.459182 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2007 02:25:21.459731 # ok 219 name.LCALTA.29
2008 02:25:21.464734 # ok 220 write_default.LCALTA.29
2009 02:25:21.465296 # ok 221 write_valid.LCALTA.29
2010 02:25:21.470235 # ok 222 write_invalid.LCALTA.29
2011 02:25:21.470803 # ok 223 event_missing.LCALTA.29
2012 02:25:21.475780 # ok 224 event_spurious.LCALTA.29
2013 02:25:21.476361 # ok 225 get_value.LCALTA.28
2014 02:25:21.481329 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2015 02:25:21.481897 # ok 226 name.LCALTA.28
2016 02:25:21.486884 # ok 227 write_default.LCALTA.28
2017 02:25:21.487443 # ok 228 write_valid.LCALTA.28
2018 02:25:21.492485 # ok 229 write_invalid.LCALTA.28
2019 02:25:21.493030 # ok 230 event_missing.LCALTA.28
2020 02:25:21.498021 # ok 231 event_spurious.LCALTA.28
2021 02:25:21.498619 # ok 232 get_value.LCALTA.27
2022 02:25:21.503588 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2023 02:25:21.504235 # ok 233 name.LCALTA.27
2024 02:25:21.509121 # ok 234 write_default.LCALTA.27
2025 02:25:21.509715 # ok 235 write_valid.LCALTA.27
2026 02:25:21.514631 # ok 236 write_invalid.LCALTA.27
2027 02:25:21.520188 # ok 237 event_missing.LCALTA.27
2028 02:25:21.520651 # ok 238 event_spurious.LCALTA.27
2029 02:25:21.525783 # ok 239 get_value.LCALTA.26
2030 02:25:21.526260 # # LCALTA.26 ELD
2031 02:25:21.526680 # ok 240 name.LCALTA.26
2032 02:25:21.531297 # # ELD is not writeable
2033 02:25:21.531753 # ok 241 # SKIP write_default.LCALTA.26
2034 02:25:21.536828 # # ELD is not writeable
2035 02:25:21.537303 # ok 242 # SKIP write_valid.LCALTA.26
2036 02:25:21.542384 # # ELD is not writeable
2037 02:25:21.542859 # ok 243 # SKIP write_invalid.LCALTA.26
2038 02:25:21.547895 # ok 244 event_missing.LCALTA.26
2039 02:25:21.548381 # ok 245 event_spurious.LCALTA.26
2040 02:25:21.553490 # ok 246 get_value.LCALTA.25
2041 02:25:21.553952 # # LCALTA.25 IEC958 Playback Default
2042 02:25:21.559013 # ok 247 name.LCALTA.25
2043 02:25:21.559472 # ok 248 write_default.LCALTA.25
2044 02:25:21.564544 # ok 249 # SKIP write_valid.LCALTA.25
2045 02:25:21.570113 # ok 250 # SKIP write_invalid.LCALTA.25
2046 02:25:21.570591 # ok 251 event_missing.LCALTA.25
2047 02:25:21.575640 # ok 252 event_spurious.LCALTA.25
2048 02:25:21.576115 # ok 253 get_value.LCALTA.24
2049 02:25:21.581193 # # LCALTA.24 IEC958 Playback Mask
2050 02:25:21.581649 # ok 254 name.LCALTA.24
2051 02:25:21.586739 # # IEC958 Playback Mask is not writeable
2052 02:25:21.587192 # ok 255 # SKIP write_default.LCALTA.24
2053 02:25:21.592303 # # IEC958 Playback Mask is not writeable
2054 02:25:21.597820 # ok 256 # SKIP write_valid.LCALTA.24
2055 02:25:21.598285 # # IEC958 Playback Mask is not writeable
2056 02:25:21.603377 # ok 257 # SKIP write_invalid.LCALTA.24
2057 02:25:21.608945 # ok 258 event_missing.LCALTA.24
2058 02:25:21.609404 # ok 259 event_spurious.LCALTA.24
2059 02:25:21.614486 # ok 260 get_value.LCALTA.23
2060 02:25:21.614933 # # LCALTA.23 Playback Channel Map
2061 02:25:21.620045 # ok 261 name.LCALTA.23
2062 02:25:21.620513 # # Playback Channel Map is not writeable
2063 02:25:21.625558 # ok 262 # SKIP write_default.LCALTA.23
2064 02:25:21.631113 # # Playback Channel Map is not writeable
2065 02:25:21.631559 # ok 263 # SKIP write_valid.LCALTA.23
2066 02:25:21.636674 # # Playback Channel Map is not writeable
2067 02:25:21.637140 # ok 264 # SKIP write_invalid.LCALTA.23
2068 02:25:21.642224 # ok 265 event_missing.LCALTA.23
2069 02:25:21.647786 # ok 266 event_spurious.LCALTA.23
2070 02:25:21.648273 # ok 267 get_value.LCALTA.22
2071 02:25:21.653296 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2072 02:25:21.653740 # ok 268 name.LCALTA.22
2073 02:25:21.658861 # ok 269 write_default.LCALTA.22
2074 02:25:21.659320 # ok 270 write_valid.LCALTA.22
2075 02:25:21.664525 # ok 271 write_invalid.LCALTA.22
2076 02:25:21.664986 # ok 272 event_missing.LCALTA.22
2077 02:25:21.669941 # ok 273 event_spurious.LCALTA.22
2078 02:25:21.670388 # ok 274 get_value.LCALTA.21
2079 02:25:21.675501 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2080 02:25:21.675976 # ok 275 name.LCALTA.21
2081 02:25:21.681047 # ok 276 write_default.LCALTA.21
2082 02:25:21.681505 # ok 277 write_valid.LCALTA.21
2083 02:25:21.686583 # ok 278 write_invalid.LCALTA.21
2084 02:25:21.687041 # ok 279 event_missing.LCALTA.21
2085 02:25:21.692180 # ok 280 event_spurious.LCALTA.21
2086 02:25:21.692649 # ok 281 get_value.LCALTA.20
2087 02:25:21.697659 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2088 02:25:21.698118 # ok 282 name.LCALTA.20
2089 02:25:21.703232 # ok 283 write_default.LCALTA.20
2090 02:25:21.703704 # ok 284 write_valid.LCALTA.20
2091 02:25:21.708768 # ok 285 write_invalid.LCALTA.20
2092 02:25:21.709219 # ok 286 event_missing.LCALTA.20
2093 02:25:21.714319 # ok 287 event_spurious.LCALTA.20
2094 02:25:21.714769 # ok 288 get_value.LCALTA.19
2095 02:25:21.719839 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2096 02:25:21.720338 # ok 289 name.LCALTA.19
2097 02:25:21.725511 # ok 290 write_default.LCALTA.19
2098 02:25:21.725970 # ok 291 write_valid.LCALTA.19
2099 02:25:21.730955 # ok 292 write_invalid.LCALTA.19
2100 02:25:21.731445 # ok 293 event_missing.LCALTA.19
2101 02:25:21.736498 # ok 294 event_spurious.LCALTA.19
2102 02:25:21.736948 # ok 295 get_value.LCALTA.18
2103 02:25:21.742021 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2104 02:25:21.742459 # ok 296 name.LCALTA.18
2105 02:25:21.747625 # ok 297 write_default.LCALTA.18
2106 02:25:21.748142 # ok 298 write_valid.LCALTA.18
2107 02:25:21.753153 # ok 299 write_invalid.LCALTA.18
2108 02:25:21.758682 # ok 300 event_missing.LCALTA.18
2109 02:25:21.759151 # ok 301 event_spurious.LCALTA.18
2110 02:25:21.764247 # ok 302 get_value.LCALTA.17
2111 02:25:21.764700 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2112 02:25:21.769764 # ok 303 name.LCALTA.17
2113 02:25:21.770210 # ok 304 write_default.LCALTA.17
2114 02:25:21.775380 # ok 305 write_valid.LCALTA.17
2115 02:25:21.775828 # ok 306 write_invalid.LCALTA.17
2116 02:25:21.780870 # ok 307 event_missing.LCALTA.17
2117 02:25:21.781308 # ok 308 event_spurious.LCALTA.17
2118 02:25:21.786527 # ok 309 get_value.LCALTA.16
2119 02:25:21.786978 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2120 02:25:21.791958 # ok 310 name.LCALTA.16
2121 02:25:21.792423 # ok 311 write_default.LCALTA.16
2122 02:25:21.797509 # ok 312 write_valid.LCALTA.16
2123 02:25:21.797947 # ok 313 write_invalid.LCALTA.16
2124 02:25:21.803048 # ok 314 event_missing.LCALTA.16
2125 02:25:21.803491 # ok 315 event_spurious.LCALTA.16
2126 02:25:21.808592 # ok 316 get_value.LCALTA.15
2127 02:25:21.809029 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2128 02:25:21.814142 # ok 317 name.LCALTA.15
2129 02:25:21.814589 # ok 318 write_default.LCALTA.15
2130 02:25:21.819687 # ok 319 write_valid.LCALTA.15
2131 02:25:21.820161 # ok 320 write_invalid.LCALTA.15
2132 02:25:21.825251 # ok 321 event_missing.LCALTA.15
2133 02:25:21.825690 # ok 322 event_spurious.LCALTA.15
2134 02:25:21.830777 # ok 323 get_value.LCALTA.14
2135 02:25:21.836411 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2136 02:25:21.836873 # ok 324 name.LCALTA.14
2137 02:25:21.837281 # ok 325 write_default.LCALTA.14
2138 02:25:21.841893 # ok 326 write_valid.LCALTA.14
2139 02:25:21.842332 # ok 327 write_invalid.LCALTA.14
2140 02:25:21.847582 # ok 328 event_missing.LCALTA.14
2141 02:25:21.852982 # ok 329 event_spurious.LCALTA.14
2142 02:25:21.853454 # ok 330 get_value.LCALTA.13
2143 02:25:21.858597 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2144 02:25:21.859058 # ok 331 name.LCALTA.13
2145 02:25:21.864089 # ok 332 write_default.LCALTA.13
2146 02:25:21.864546 # ok 333 write_valid.LCALTA.13
2147 02:25:21.869598 # ok 334 write_invalid.LCALTA.13
2148 02:25:21.870051 # ok 335 event_missing.LCALTA.13
2149 02:25:21.875097 # ok 336 event_spurious.LCALTA.13
2150 02:25:21.875539 # ok 337 get_value.LCALTA.12
2151 02:25:21.880648 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2152 02:25:21.881092 # ok 338 name.LCALTA.12
2153 02:25:21.886183 # ok 339 write_default.LCALTA.12
2154 02:25:21.886619 # ok 340 write_valid.LCALTA.12
2155 02:25:21.891844 # ok 341 write_invalid.LCALTA.12
2156 02:25:21.892339 # ok 342 event_missing.LCALTA.12
2157 02:25:21.897419 # ok 343 event_spurious.LCALTA.12
2158 02:25:21.897870 # ok 344 get_value.LCALTA.11
2159 02:25:21.902900 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2160 02:25:21.903355 # ok 345 name.LCALTA.11
2161 02:25:21.908534 # ok 346 write_default.LCALTA.11
2162 02:25:21.908975 # ok 347 write_valid.LCALTA.11
2163 02:25:21.913981 # ok 348 write_invalid.LCALTA.11
2164 02:25:21.914420 # ok 349 event_missing.LCALTA.11
2165 02:25:21.919541 # ok 350 event_spurious.LCALTA.11
2166 02:25:21.920025 # ok 351 get_value.LCALTA.10
2167 02:25:21.925101 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2168 02:25:21.925723 # ok 352 name.LCALTA.10
2169 02:25:21.930622 # ok 353 write_default.LCALTA.10
2170 02:25:21.931211 # ok 354 write_valid.LCALTA.10
2171 02:25:21.936214 # ok 355 write_invalid.LCALTA.10
2172 02:25:21.936823 # ok 356 event_missing.LCALTA.10
2173 02:25:21.941748 # ok 357 event_spurious.LCALTA.10
2174 02:25:21.942334 # ok 358 get_value.LCALTA.9
2175 02:25:21.947289 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2176 02:25:21.947859 # ok 359 name.LCALTA.9
2177 02:25:21.952863 # ok 360 write_default.LCALTA.9
2178 02:25:21.953468 # ok 361 write_valid.LCALTA.9
2179 02:25:21.958434 # ok 362 write_invalid.LCALTA.9
2180 02:25:21.959015 # ok 363 event_missing.LCALTA.9
2181 02:25:21.963922 # ok 364 event_spurious.LCALTA.9
2182 02:25:21.964532 # ok 365 get_value.LCALTA.8
2183 02:25:21.969567 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2184 02:25:21.970147 # ok 366 name.LCALTA.8
2185 02:25:21.975010 # ok 367 write_default.LCALTA.8
2186 02:25:21.975571 # ok 368 write_valid.LCALTA.8
2187 02:25:21.980575 # ok 369 write_invalid.LCALTA.8
2188 02:25:21.981163 # ok 370 event_missing.LCALTA.8
2189 02:25:21.986108 # ok 371 event_spurious.LCALTA.8
2190 02:25:21.986696 # ok 372 get_value.LCALTA.7
2191 02:25:21.991697 # # LCALTA.7 ACODEC Unmute Ramp Switch
2192 02:25:21.992305 # ok 373 name.LCALTA.7
2193 02:25:21.997206 # ok 374 write_default.LCALTA.7
2194 02:25:21.997788 # ok 375 write_valid.LCALTA.7
2195 02:25:22.002758 # ok 376 write_invalid.LCALTA.7
2196 02:25:22.003344 # ok 377 event_missing.LCALTA.7
2197 02:25:22.008308 # ok 378 event_spurious.LCALTA.7
2198 02:25:22.008900 # ok 379 get_value.LCALTA.6
2199 02:25:22.013989 # # LCALTA.6 ACODEC Mute Ramp Switch
2200 02:25:22.014675 # ok 380 name.LCALTA.6
2201 02:25:22.019541 # ok 381 write_default.LCALTA.6
2202 02:25:22.020260 # ok 382 write_valid.LCALTA.6
2203 02:25:22.025041 # ok 383 write_invalid.LCALTA.6
2204 02:25:22.025703 # ok 384 event_missing.LCALTA.6
2205 02:25:22.030617 # ok 385 event_spurious.LCALTA.6
2206 02:25:22.031231 # ok 386 get_value.LCALTA.5
2207 02:25:22.036087 # # LCALTA.5 ACODEC Volume Ramp Switch
2208 02:25:22.036661 # ok 387 name.LCALTA.5
2209 02:25:22.041599 # ok 388 write_default.LCALTA.5
2210 02:25:22.042090 # ok 389 write_valid.LCALTA.5
2211 02:25:22.047124 # ok 390 write_invalid.LCALTA.5
2212 02:25:22.047573 # ok 391 event_missing.LCALTA.5
2213 02:25:22.052673 # ok 392 event_spurious.LCALTA.5
2214 02:25:22.053117 # ok 393 get_value.LCALTA.4
2215 02:25:22.058217 # # LCALTA.4 ACODEC Ramp Rate
2216 02:25:22.058659 # ok 394 name.LCALTA.4
2217 02:25:22.063769 # ok 395 write_default.LCALTA.4
2218 02:25:22.064247 # ok 396 write_valid.LCALTA.4
2219 02:25:22.069332 # ok 397 write_invalid.LCALTA.4
2220 02:25:22.069782 # ok 398 event_missing.LCALTA.4
2221 02:25:22.074852 # ok 399 event_spurious.LCALTA.4
2222 02:25:22.075295 # ok 400 get_value.LCALTA.3
2223 02:25:22.080450 # # LCALTA.3 ACODEC Playback Volume
2224 02:25:22.080890 # ok 401 name.LCALTA.3
2225 02:25:22.085975 # ok 402 write_default.LCALTA.3
2226 02:25:22.086425 # ok 403 write_valid.LCALTA.3
2227 02:25:22.091598 # ok 404 write_invalid.LCALTA.3
2228 02:25:22.092086 # ok 405 event_missing.LCALTA.3
2229 02:25:22.097068 # ok 406 event_spurious.LCALTA.3
2230 02:25:22.097518 # ok 407 get_value.LCALTA.2
2231 02:25:22.102676 # # LCALTA.2 ACODEC Playback Switch
2232 02:25:22.103126 # ok 408 name.LCALTA.2
2233 02:25:22.108204 # ok 409 write_default.LCALTA.2
2234 02:25:22.108653 # ok 410 write_valid.LCALTA.2
2235 02:25:22.113720 # ok 411 write_invalid.LCALTA.2
2236 02:25:22.114168 # ok 412 event_missing.LCALTA.2
2237 02:25:22.119251 # ok 413 event_spurious.LCALTA.2
2238 02:25:22.119697 # ok 414 get_value.LCALTA.1
2239 02:25:22.124798 # # LCALTA.1 ACODEC Playback Channel Mode
2240 02:25:22.125258 # ok 415 name.LCALTA.1
2241 02:25:22.130353 # ok 416 write_default.LCALTA.1
2242 02:25:22.130791 # ok 417 write_valid.LCALTA.1
2243 02:25:22.135881 # ok 418 write_invalid.LCALTA.1
2244 02:25:22.136353 # ok 419 event_missing.LCALTA.1
2245 02:25:22.141487 # ok 420 event_spurious.LCALTA.1
2246 02:25:22.141948 # ok 421 get_value.LCALTA.0
2247 02:25:22.146993 # # LCALTA.0 TOACODEC Lane Select
2248 02:25:22.147451 # ok 422 name.LCALTA.0
2249 02:25:22.152625 # ok 423 write_default.LCALTA.0
2250 02:25:22.153072 # ok 424 write_valid.LCALTA.0
2251 02:25:22.158056 # ok 425 write_invalid.LCALTA.0
2252 02:25:22.158503 # ok 426 event_missing.LCALTA.0
2253 02:25:22.163635 # ok 427 event_spurious.LCALTA.0
2254 02:25:22.169159 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2255 02:25:22.169608 ok 1 selftests: alsa: mixer-test
2256 02:25:22.174738 # timeout set to 45
2257 02:25:22.175185 # selftests: alsa: pcm-test
2258 02:25:22.175596 # TAP version 13
2259 02:25:22.180275 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2260 02:25:22.180740 # # LCALTA.0 - fe.dai-link-0 (*)
2261 02:25:22.185804 # # LCALTA.0 - fe.dai-link-1 (*)
2262 02:25:22.191384 # # LCALTA.0 - fe.dai-link-2 (*)
2263 02:25:22.192035 # # LCALTA.0 - fe.dai-link-3 (*)
2264 02:25:22.196887 # # LCALTA.0 - fe.dai-link-4 (*)
2265 02:25:22.197469 # # LCALTA.0 - fe.dai-link-5 (*)
2266 02:25:22.198002 # 1..42
2267 02:25:22.202490 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2268 02:25:22.208055 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2269 02:25:22.213649 # # snd_pcm_hw_params: Invalid argument
2270 02:25:22.219090 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2271 02:25:22.219553 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2272 02:25:22.224652 # # snd_pcm_hw_params: Invalid argument
2273 02:25:22.230171 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2274 02:25:22.235718 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2275 02:25:22.241280 # # snd_pcm_hw_params: Invalid argument
2276 02:25:22.246819 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2277 02:25:22.247287 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2278 02:25:22.252385 # # snd_pcm_hw_params: Invalid argument
2279 02:25:22.257926 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2280 02:25:22.263492 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2281 02:25:22.263949 # # snd_pcm_hw_params: Invalid argument
2282 02:25:22.269032 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2283 02:25:22.274652 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2284 02:25:22.280137 # # snd_pcm_hw_params: Invalid argument
2285 02:25:22.285686 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2286 02:25:22.291206 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2287 02:25:22.291680 # # snd_pcm_hw_params: Invalid argument
2288 02:25:22.296802 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2289 02:25:22.302278 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2290 02:25:22.307801 # # snd_pcm_hw_params: Invalid argument
2291 02:25:22.313369 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2292 02:25:22.313824 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2293 02:25:22.318896 # # snd_pcm_hw_params: Invalid argument
2294 02:25:22.324517 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2295 02:25:22.330009 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2296 02:25:22.335632 # # snd_pcm_hw_params: Invalid argument
2297 02:25:22.341142 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2298 02:25:22.341625 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2299 02:25:22.346678 # # snd_pcm_hw_params: Invalid argument
2300 02:25:22.352192 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2301 02:25:22.357749 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2302 02:25:22.363297 # # snd_pcm_hw_params: Invalid argument
2303 02:25:22.368827 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2304 02:25:22.369284 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2305 02:25:22.374389 # # snd_pcm_hw_params: Invalid argument
2306 02:25:22.379953 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2307 02:25:22.385513 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2308 02:25:22.385975 # # snd_pcm_hw_params: Invalid argument
2309 02:25:22.391037 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2310 02:25:22.396608 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2311 02:25:22.402145 # # snd_pcm_hw_params: Invalid argument
2312 02:25:22.407666 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2313 02:25:22.413414 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2314 02:25:22.413880 # # snd_pcm_hw_params: Invalid argument
2315 02:25:22.418885 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2316 02:25:22.424304 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2317 02:25:22.429855 # # snd_pcm_hw_params: Invalid argument
2318 02:25:22.435409 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2319 02:25:22.440952 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2320 02:25:22.441401 # # snd_pcm_hw_params: Invalid argument
2321 02:25:22.446502 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2322 02:25:22.452062 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2323 02:25:22.457635 # # snd_pcm_hw_params: Invalid argument
2324 02:25:22.463117 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2325 02:25:22.468690 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2326 02:25:22.469169 # # snd_pcm_hw_params: Invalid argument
2327 02:25:22.474275 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2328 02:25:22.479888 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2329 02:25:22.485400 # # snd_pcm_hw_params: Invalid argument
2330 02:25:22.490958 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2331 02:25:22.491413 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2332 02:25:22.496462 # # snd_pcm_hw_params: Invalid argument
2333 02:25:22.501997 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2334 02:25:22.508052 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2335 02:25:22.513142 # # snd_pcm_hw_params: Invalid argument
2336 02:25:22.518777 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2337 02:25:22.519514 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2338 02:25:22.524290 # # snd_pcm_hw_params: Invalid argument
2339 02:25:22.529727 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2340 02:25:22.535237 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2341 02:25:22.540760 # # snd_pcm_hw_params: Invalid argument
2342 02:25:22.546329 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2343 02:25:22.546826 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2344 02:25:22.551864 # # snd_pcm_hw_params: Invalid argument
2345 02:25:22.557388 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2346 02:25:22.562964 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2347 02:25:22.568530 # # snd_pcm_hw_params: Invalid argument
2348 02:25:22.574068 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2349 02:25:22.574520 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2350 02:25:22.579644 # # snd_pcm_hw_params: Invalid argument
2351 02:25:22.585158 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2352 02:25:22.590703 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2353 02:25:22.596250 # # snd_pcm_hw_params: Invalid argument
2354 02:25:22.601782 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2355 02:25:22.602248 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2356 02:25:22.607343 # # snd_pcm_hw_params: Invalid argument
2357 02:25:22.612903 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2358 02:25:22.618455 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2359 02:25:22.618938 # # snd_pcm_hw_params: Invalid argument
2360 02:25:22.629527 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2361 02:25:22.630006 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2362 02:25:22.635075 # # snd_pcm_hw_params: Invalid argument
2363 02:25:22.640654 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2364 02:25:22.646173 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2365 02:25:22.646641 # # snd_pcm_hw_params: Invalid argument
2366 02:25:22.657261 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2367 02:25:22.657746 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2368 02:25:22.662805 # # snd_pcm_hw_params: Invalid argument
2369 02:25:22.668352 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2370 02:25:22.673919 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2371 02:25:22.674365 # # snd_pcm_hw_params: Invalid argument
2372 02:25:22.679429 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2373 02:25:22.684994 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2374 02:25:22.690547 # # snd_pcm_hw_params: Invalid argument
2375 02:25:22.696083 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2376 02:25:22.701698 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2377 02:25:22.702225 # # snd_pcm_hw_params: Invalid argument
2378 02:25:22.707196 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2379 02:25:22.712738 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2380 02:25:22.718354 # # snd_pcm_hw_params: Invalid argument
2381 02:25:22.723873 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2382 02:25:22.729382 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2383 02:25:22.729992 # # snd_pcm_hw_params: Invalid argument
2384 02:25:22.734928 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2385 02:25:22.740475 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2386 02:25:22.746027 # # snd_pcm_hw_params: Invalid argument
2387 02:25:22.751681 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2388 02:25:22.757120 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2389 02:25:22.757715 # # snd_pcm_hw_params: Invalid argument
2390 02:25:22.762695 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2391 02:25:22.768218 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2392 02:25:22.773756 # # snd_pcm_hw_params: Invalid argument
2393 02:25:22.779315 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2394 02:25:22.779906 ok 2 selftests: alsa: pcm-test
2395 02:25:22.784911 # timeout set to 45
2396 02:25:22.785546 # selftests: alsa: test-pcmtest-driver
2397 02:25:22.790395 # TAP version 13
2398 02:25:22.790981 # 1..5
2399 02:25:22.791505 # # Starting 5 tests from 1 test cases.
2400 02:25:22.796009 # # RUN pcmtest.playback ...
2401 02:25:22.801487 # # SKIP Can't read patterns. Probably, module isn't loaded
2402 02:25:22.807027 # # OK pcmtest.playback
2403 02:25:22.812711 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2404 02:25:22.818126 # # RUN pcmtest.capture ...
2405 02:25:22.823722 # # SKIP Can't read patterns. Probably, module isn't loaded
2406 02:25:22.824280 # # OK pcmtest.capture
2407 02:25:22.834784 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2408 02:25:22.835338 # # RUN pcmtest.ni_capture ...
2409 02:25:22.840334 # # SKIP Can't read patterns. Probably, module isn't loaded
2410 02:25:22.845870 # # OK pcmtest.ni_capture
2411 02:25:22.851418 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2412 02:25:22.856971 # # RUN pcmtest.ni_playback ...
2413 02:25:22.862540 # # SKIP Can't read patterns. Probably, module isn't loaded
2414 02:25:22.868057 # # OK pcmtest.ni_playback
2415 02:25:22.873709 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2416 02:25:22.879163 # # RUN pcmtest.reset_ioctl ...
2417 02:25:22.884710 # # SKIP Can't read patterns. Probably, module isn't loaded
2418 02:25:22.885237 # # OK pcmtest.reset_ioctl
2419 02:25:22.895754 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2420 02:25:22.896291 # # PASSED: 5 / 5 tests passed.
2421 02:25:22.901309 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2422 02:25:22.906865 ok 3 selftests: alsa: test-pcmtest-driver
2423 02:25:22.907307 # timeout set to 45
2424 02:25:22.912388 # selftests: alsa: utimer-test
2425 02:25:22.912819 # TAP version 13
2426 02:25:22.913224 # 1..2
2427 02:25:22.917959 # # Starting 2 tests from 2 test cases.
2428 02:25:22.918410 # # RUN global.wrong_timers_test ...
2429 02:25:22.923492 # # OK global.wrong_timers_test
2430 02:25:22.929048 # ok 1 global.wrong_timers_test
2431 02:25:22.929501 # # RUN timer_f.utimer ...
2432 02:25:22.940224 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2433 02:25:22.945741 # # utimer: Test terminated by assertion
2434 02:25:22.946382 # # FAIL timer_f.utimer
2435 02:25:22.951239 # not ok 2 timer_f.utimer
2436 02:25:22.951843 # # FAILED: 1 / 2 tests passed.
2437 02:25:22.956806 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2438 02:25:22.962403 not ok 4 selftests: alsa: utimer-test # exit=1
2439 02:25:23.469760 alsa_mixer-test_get_value_LCALTA_60 pass
2440 02:25:23.475110 alsa_mixer-test_name_LCALTA_60 pass
2441 02:25:23.475580 alsa_mixer-test_write_default_LCALTA_60 pass
2442 02:25:23.480684 alsa_mixer-test_write_valid_LCALTA_60 pass
2443 02:25:23.486194 alsa_mixer-test_write_invalid_LCALTA_60 pass
2444 02:25:23.491737 alsa_mixer-test_event_missing_LCALTA_60 pass
2445 02:25:23.492218 alsa_mixer-test_event_spurious_LCALTA_60 pass
2446 02:25:23.497290 alsa_mixer-test_get_value_LCALTA_59 pass
2447 02:25:23.502847 alsa_mixer-test_name_LCALTA_59 pass
2448 02:25:23.503323 alsa_mixer-test_write_default_LCALTA_59 pass
2449 02:25:23.508380 alsa_mixer-test_write_valid_LCALTA_59 pass
2450 02:25:23.513947 alsa_mixer-test_write_invalid_LCALTA_59 pass
2451 02:25:23.514403 alsa_mixer-test_event_missing_LCALTA_59 pass
2452 02:25:23.519471 alsa_mixer-test_event_spurious_LCALTA_59 pass
2453 02:25:23.525025 alsa_mixer-test_get_value_LCALTA_58 pass
2454 02:25:23.525495 alsa_mixer-test_name_LCALTA_58 pass
2455 02:25:23.530548 alsa_mixer-test_write_default_LCALTA_58 pass
2456 02:25:23.536124 alsa_mixer-test_write_valid_LCALTA_58 pass
2457 02:25:23.536584 alsa_mixer-test_write_invalid_LCALTA_58 pass
2458 02:25:23.541699 alsa_mixer-test_event_missing_LCALTA_58 pass
2459 02:25:23.547206 alsa_mixer-test_event_spurious_LCALTA_58 pass
2460 02:25:23.552755 alsa_mixer-test_get_value_LCALTA_57 pass
2461 02:25:23.553205 alsa_mixer-test_name_LCALTA_57 pass
2462 02:25:23.558372 alsa_mixer-test_write_default_LCALTA_57 pass
2463 02:25:23.563899 alsa_mixer-test_write_valid_LCALTA_57 pass
2464 02:25:23.564376 alsa_mixer-test_write_invalid_LCALTA_57 pass
2465 02:25:23.569471 alsa_mixer-test_event_missing_LCALTA_57 pass
2466 02:25:23.574980 alsa_mixer-test_event_spurious_LCALTA_57 pass
2467 02:25:23.575420 alsa_mixer-test_get_value_LCALTA_56 pass
2468 02:25:23.580620 alsa_mixer-test_name_LCALTA_56 pass
2469 02:25:23.586073 alsa_mixer-test_write_default_LCALTA_56 pass
2470 02:25:23.586513 alsa_mixer-test_write_valid_LCALTA_56 pass
2471 02:25:23.591721 alsa_mixer-test_write_invalid_LCALTA_56 pass
2472 02:25:23.597195 alsa_mixer-test_event_missing_LCALTA_56 pass
2473 02:25:23.602748 alsa_mixer-test_event_spurious_LCALTA_56 pass
2474 02:25:23.603211 alsa_mixer-test_get_value_LCALTA_55 pass
2475 02:25:23.608271 alsa_mixer-test_name_LCALTA_55 pass
2476 02:25:23.613819 alsa_mixer-test_write_default_LCALTA_55 pass
2477 02:25:23.614270 alsa_mixer-test_write_valid_LCALTA_55 pass
2478 02:25:23.619368 alsa_mixer-test_write_invalid_LCALTA_55 pass
2479 02:25:23.624931 alsa_mixer-test_event_missing_LCALTA_55 pass
2480 02:25:23.625401 alsa_mixer-test_event_spurious_LCALTA_55 pass
2481 02:25:23.630458 alsa_mixer-test_get_value_LCALTA_54 pass
2482 02:25:23.636005 alsa_mixer-test_name_LCALTA_54 pass
2483 02:25:23.636452 alsa_mixer-test_write_default_LCALTA_54 pass
2484 02:25:23.641556 alsa_mixer-test_write_valid_LCALTA_54 pass
2485 02:25:23.647097 alsa_mixer-test_write_invalid_LCALTA_54 pass
2486 02:25:23.647551 alsa_mixer-test_event_missing_LCALTA_54 pass
2487 02:25:23.652753 alsa_mixer-test_event_spurious_LCALTA_54 pass
2488 02:25:23.658196 alsa_mixer-test_get_value_LCALTA_53 pass
2489 02:25:23.658649 alsa_mixer-test_name_LCALTA_53 pass
2490 02:25:23.663745 alsa_mixer-test_write_default_LCALTA_53 pass
2491 02:25:23.669286 alsa_mixer-test_write_valid_LCALTA_53 pass
2492 02:25:23.674822 alsa_mixer-test_write_invalid_LCALTA_53 pass
2493 02:25:23.675267 alsa_mixer-test_event_missing_LCALTA_53 pass
2494 02:25:23.680382 alsa_mixer-test_event_spurious_LCALTA_53 pass
2495 02:25:23.685920 alsa_mixer-test_get_value_LCALTA_52 pass
2496 02:25:23.686362 alsa_mixer-test_name_LCALTA_52 pass
2497 02:25:23.691468 alsa_mixer-test_write_default_LCALTA_52 pass
2498 02:25:23.697007 alsa_mixer-test_write_valid_LCALTA_52 pass
2499 02:25:23.697456 alsa_mixer-test_write_invalid_LCALTA_52 pass
2500 02:25:23.702643 alsa_mixer-test_event_missing_LCALTA_52 pass
2501 02:25:23.708221 alsa_mixer-test_event_spurious_LCALTA_52 pass
2502 02:25:23.708717 alsa_mixer-test_get_value_LCALTA_51 pass
2503 02:25:23.713789 alsa_mixer-test_name_LCALTA_51 pass
2504 02:25:23.719230 alsa_mixer-test_write_default_LCALTA_51 pass
2505 02:25:23.719699 alsa_mixer-test_write_valid_LCALTA_51 pass
2506 02:25:23.724810 alsa_mixer-test_write_invalid_LCALTA_51 pass
2507 02:25:23.730323 alsa_mixer-test_event_missing_LCALTA_51 pass
2508 02:25:23.735920 alsa_mixer-test_event_spurious_LCALTA_51 pass
2509 02:25:23.736474 alsa_mixer-test_get_value_LCALTA_50 pass
2510 02:25:23.741466 alsa_mixer-test_name_LCALTA_50 pass
2511 02:25:23.746951 alsa_mixer-test_write_default_LCALTA_50 pass
2512 02:25:23.747437 alsa_mixer-test_write_valid_LCALTA_50 pass
2513 02:25:23.752494 alsa_mixer-test_write_invalid_LCALTA_50 pass
2514 02:25:23.758049 alsa_mixer-test_event_missing_LCALTA_50 pass
2515 02:25:23.758515 alsa_mixer-test_event_spurious_LCALTA_50 pass
2516 02:25:23.763648 alsa_mixer-test_get_value_LCALTA_49 pass
2517 02:25:23.769156 alsa_mixer-test_name_LCALTA_49 pass
2518 02:25:23.769614 alsa_mixer-test_write_default_LCALTA_49 pass
2519 02:25:23.774775 alsa_mixer-test_write_valid_LCALTA_49 pass
2520 02:25:23.780232 alsa_mixer-test_write_invalid_LCALTA_49 pass
2521 02:25:23.785782 alsa_mixer-test_event_missing_LCALTA_49 pass
2522 02:25:23.786238 alsa_mixer-test_event_spurious_LCALTA_49 pass
2523 02:25:23.791313 alsa_mixer-test_get_value_LCALTA_48 pass
2524 02:25:23.791777 alsa_mixer-test_name_LCALTA_48 pass
2525 02:25:23.796863 alsa_mixer-test_write_default_LCALTA_48 pass
2526 02:25:23.802422 alsa_mixer-test_write_valid_LCALTA_48 pass
2527 02:25:23.807949 alsa_mixer-test_write_invalid_LCALTA_48 pass
2528 02:25:23.808425 alsa_mixer-test_event_missing_LCALTA_48 pass
2529 02:25:23.813526 alsa_mixer-test_event_spurious_LCALTA_48 pass
2530 02:25:23.819025 alsa_mixer-test_get_value_LCALTA_47 pass
2531 02:25:23.819468 alsa_mixer-test_name_LCALTA_47 pass
2532 02:25:23.824674 alsa_mixer-test_write_default_LCALTA_47 pass
2533 02:25:23.830161 alsa_mixer-test_write_valid_LCALTA_47 pass
2534 02:25:23.830625 alsa_mixer-test_write_invalid_LCALTA_47 pass
2535 02:25:23.835780 alsa_mixer-test_event_missing_LCALTA_47 pass
2536 02:25:23.841229 alsa_mixer-test_event_spurious_LCALTA_47 pass
2537 02:25:23.846790 alsa_mixer-test_get_value_LCALTA_46 pass
2538 02:25:23.847241 alsa_mixer-test_name_LCALTA_46 pass
2539 02:25:23.852310 alsa_mixer-test_write_default_LCALTA_46 pass
2540 02:25:23.857853 alsa_mixer-test_write_valid_LCALTA_46 pass
2541 02:25:23.858299 alsa_mixer-test_write_invalid_LCALTA_46 pass
2542 02:25:23.863406 alsa_mixer-test_event_missing_LCALTA_46 pass
2543 02:25:23.868957 alsa_mixer-test_event_spurious_LCALTA_46 pass
2544 02:25:23.869403 alsa_mixer-test_get_value_LCALTA_45 pass
2545 02:25:23.874531 alsa_mixer-test_name_LCALTA_45 pass
2546 02:25:23.880079 alsa_mixer-test_write_default_LCALTA_45 pass
2547 02:25:23.880536 alsa_mixer-test_write_valid_LCALTA_45 pass
2548 02:25:23.885669 alsa_mixer-test_write_invalid_LCALTA_45 pass
2549 02:25:23.891172 alsa_mixer-test_event_missing_LCALTA_45 pass
2550 02:25:23.891625 alsa_mixer-test_event_spurious_LCALTA_45 pass
2551 02:25:23.896785 alsa_mixer-test_get_value_LCALTA_44 pass
2552 02:25:23.902258 alsa_mixer-test_name_LCALTA_44 pass
2553 02:25:23.902702 alsa_mixer-test_write_default_LCALTA_44 pass
2554 02:25:23.907793 alsa_mixer-test_write_valid_LCALTA_44 pass
2555 02:25:23.913342 alsa_mixer-test_write_invalid_LCALTA_44 pass
2556 02:25:23.918876 alsa_mixer-test_event_missing_LCALTA_44 pass
2557 02:25:23.919320 alsa_mixer-test_event_spurious_LCALTA_44 pass
2558 02:25:23.924441 alsa_mixer-test_get_value_LCALTA_43 pass
2559 02:25:23.929966 alsa_mixer-test_name_LCALTA_43 pass
2560 02:25:23.930410 alsa_mixer-test_write_default_LCALTA_43 pass
2561 02:25:23.935524 alsa_mixer-test_write_valid_LCALTA_43 pass
2562 02:25:23.941052 alsa_mixer-test_write_invalid_LCALTA_43 pass
2563 02:25:23.941501 alsa_mixer-test_event_missing_LCALTA_43 pass
2564 02:25:23.946677 alsa_mixer-test_event_spurious_LCALTA_43 pass
2565 02:25:23.952177 alsa_mixer-test_get_value_LCALTA_42 pass
2566 02:25:23.952629 alsa_mixer-test_name_LCALTA_42 pass
2567 02:25:23.957803 alsa_mixer-test_write_default_LCALTA_42 pass
2568 02:25:23.963259 alsa_mixer-test_write_valid_LCALTA_42 pass
2569 02:25:23.963701 alsa_mixer-test_write_invalid_LCALTA_42 pass
2570 02:25:23.968796 alsa_mixer-test_event_missing_LCALTA_42 pass
2571 02:25:23.974346 alsa_mixer-test_event_spurious_LCALTA_42 pass
2572 02:25:23.979909 alsa_mixer-test_get_value_LCALTA_41 pass
2573 02:25:23.980387 alsa_mixer-test_name_LCALTA_41 pass
2574 02:25:23.985487 alsa_mixer-test_write_default_LCALTA_41 pass
2575 02:25:23.991009 alsa_mixer-test_write_valid_LCALTA_41 pass
2576 02:25:23.991608 alsa_mixer-test_write_invalid_LCALTA_41 pass
2577 02:25:23.996529 alsa_mixer-test_event_missing_LCALTA_41 pass
2578 02:25:24.002132 alsa_mixer-test_event_spurious_LCALTA_41 pass
2579 02:25:24.002459 alsa_mixer-test_get_value_LCALTA_40 pass
2580 02:25:24.007722 alsa_mixer-test_name_LCALTA_40 pass
2581 02:25:24.013252 alsa_mixer-test_write_default_LCALTA_40 pass
2582 02:25:24.013751 alsa_mixer-test_write_valid_LCALTA_40 pass
2583 02:25:24.018906 alsa_mixer-test_write_invalid_LCALTA_40 pass
2584 02:25:24.024257 alsa_mixer-test_event_missing_LCALTA_40 pass
2585 02:25:24.029849 alsa_mixer-test_event_spurious_LCALTA_40 pass
2586 02:25:24.030142 alsa_mixer-test_get_value_LCALTA_39 pass
2587 02:25:24.035358 alsa_mixer-test_name_LCALTA_39 pass
2588 02:25:24.040876 alsa_mixer-test_write_default_LCALTA_39 pass
2589 02:25:24.041173 alsa_mixer-test_write_valid_LCALTA_39 pass
2590 02:25:24.046401 alsa_mixer-test_write_invalid_LCALTA_39 pass
2591 02:25:24.051952 alsa_mixer-test_event_missing_LCALTA_39 pass
2592 02:25:24.052260 alsa_mixer-test_event_spurious_LCALTA_39 pass
2593 02:25:24.057535 alsa_mixer-test_get_value_LCALTA_38 pass
2594 02:25:24.063052 alsa_mixer-test_name_LCALTA_38 pass
2595 02:25:24.063326 alsa_mixer-test_write_default_LCALTA_38 pass
2596 02:25:24.068957 alsa_mixer-test_write_valid_LCALTA_38 pass
2597 02:25:24.074172 alsa_mixer-test_write_invalid_LCALTA_38 pass
2598 02:25:24.074651 alsa_mixer-test_event_missing_LCALTA_38 pass
2599 02:25:24.079831 alsa_mixer-test_event_spurious_LCALTA_38 pass
2600 02:25:24.085294 alsa_mixer-test_get_value_LCALTA_37 pass
2601 02:25:24.085776 alsa_mixer-test_name_LCALTA_37 pass
2602 02:25:24.090873 alsa_mixer-test_write_default_LCALTA_37 pass
2603 02:25:24.096369 alsa_mixer-test_write_valid_LCALTA_37 pass
2604 02:25:24.101927 alsa_mixer-test_write_invalid_LCALTA_37 pass
2605 02:25:24.102398 alsa_mixer-test_event_missing_LCALTA_37 pass
2606 02:25:24.107461 alsa_mixer-test_event_spurious_LCALTA_37 pass
2607 02:25:24.113042 alsa_mixer-test_get_value_LCALTA_36 pass
2608 02:25:24.113552 alsa_mixer-test_name_LCALTA_36 pass
2609 02:25:24.118678 alsa_mixer-test_write_default_LCALTA_36 pass
2610 02:25:24.124118 alsa_mixer-test_write_valid_LCALTA_36 pass
2611 02:25:24.124591 alsa_mixer-test_write_invalid_LCALTA_36 pass
2612 02:25:24.129689 alsa_mixer-test_event_missing_LCALTA_36 pass
2613 02:25:24.135193 alsa_mixer-test_event_spurious_LCALTA_36 pass
2614 02:25:24.135661 alsa_mixer-test_get_value_LCALTA_35 pass
2615 02:25:24.140834 alsa_mixer-test_name_LCALTA_35 pass
2616 02:25:24.146291 alsa_mixer-test_write_default_LCALTA_35 pass
2617 02:25:24.146762 alsa_mixer-test_write_valid_LCALTA_35 pass
2618 02:25:24.151880 alsa_mixer-test_write_invalid_LCALTA_35 pass
2619 02:25:24.157437 alsa_mixer-test_event_missing_LCALTA_35 pass
2620 02:25:24.163079 alsa_mixer-test_event_spurious_LCALTA_35 pass
2621 02:25:24.163576 alsa_mixer-test_get_value_LCALTA_34 pass
2622 02:25:24.168555 alsa_mixer-test_name_LCALTA_34 pass
2623 02:25:24.174122 alsa_mixer-test_write_default_LCALTA_34 pass
2624 02:25:24.174611 alsa_mixer-test_write_valid_LCALTA_34 pass
2625 02:25:24.179640 alsa_mixer-test_write_invalid_LCALTA_34 pass
2626 02:25:24.185233 alsa_mixer-test_event_missing_LCALTA_34 pass
2627 02:25:24.185769 alsa_mixer-test_event_spurious_LCALTA_34 pass
2628 02:25:24.190819 alsa_mixer-test_get_value_LCALTA_33 pass
2629 02:25:24.196400 alsa_mixer-test_name_LCALTA_33 pass
2630 02:25:24.197027 alsa_mixer-test_write_default_LCALTA_33 pass
2631 02:25:24.202726 alsa_mixer-test_write_valid_LCALTA_33 pass
2632 02:25:24.208058 alsa_mixer-test_write_invalid_LCALTA_33 pass
2633 02:25:24.212936 alsa_mixer-test_event_missing_LCALTA_33 pass
2634 02:25:24.213490 alsa_mixer-test_event_spurious_LCALTA_33 pass
2635 02:25:24.218853 alsa_mixer-test_get_value_LCALTA_32 pass
2636 02:25:24.219289 alsa_mixer-test_name_LCALTA_32 pass
2637 02:25:24.224135 alsa_mixer-test_write_default_LCALTA_32 pass
2638 02:25:24.229642 alsa_mixer-test_write_valid_LCALTA_32 pass
2639 02:25:24.235182 alsa_mixer-test_write_invalid_LCALTA_32 pass
2640 02:25:24.235601 alsa_mixer-test_event_missing_LCALTA_32 pass
2641 02:25:24.240779 alsa_mixer-test_event_spurious_LCALTA_32 pass
2642 02:25:24.246357 alsa_mixer-test_get_value_LCALTA_31 pass
2643 02:25:24.246804 alsa_mixer-test_name_LCALTA_31 pass
2644 02:25:24.251868 alsa_mixer-test_write_default_LCALTA_31 pass
2645 02:25:24.257440 alsa_mixer-test_write_valid_LCALTA_31 pass
2646 02:25:24.257884 alsa_mixer-test_write_invalid_LCALTA_31 pass
2647 02:25:24.262955 alsa_mixer-test_event_missing_LCALTA_31 pass
2648 02:25:24.268497 alsa_mixer-test_event_spurious_LCALTA_31 pass
2649 02:25:24.274300 alsa_mixer-test_get_value_LCALTA_30 pass
2650 02:25:24.275412 alsa_mixer-test_name_LCALTA_30 pass
2651 02:25:24.280465 alsa_mixer-test_write_default_LCALTA_30 pass
2652 02:25:24.286179 alsa_mixer-test_write_valid_LCALTA_30 pass
2653 02:25:24.286884 alsa_mixer-test_write_invalid_LCALTA_30 pass
2654 02:25:24.290903 alsa_mixer-test_event_missing_LCALTA_30 pass
2655 02:25:24.296535 alsa_mixer-test_event_spurious_LCALTA_30 pass
2656 02:25:24.297015 alsa_mixer-test_get_value_LCALTA_29 pass
2657 02:25:24.301814 alsa_mixer-test_name_LCALTA_29 pass
2658 02:25:24.307693 alsa_mixer-test_write_default_LCALTA_29 pass
2659 02:25:24.310349 alsa_mixer-test_write_valid_LCALTA_29 pass
2660 02:25:24.313416 alsa_mixer-test_write_invalid_LCALTA_29 pass
2661 02:25:24.318465 alsa_mixer-test_event_missing_LCALTA_29 pass
2662 02:25:24.319059 alsa_mixer-test_event_spurious_LCALTA_29 pass
2663 02:25:24.325526 alsa_mixer-test_get_value_LCALTA_28 pass
2664 02:25:24.329499 alsa_mixer-test_name_LCALTA_28 pass
2665 02:25:24.329907 alsa_mixer-test_write_default_LCALTA_28 pass
2666 02:25:24.337201 alsa_mixer-test_write_valid_LCALTA_28 pass
2667 02:25:24.340536 alsa_mixer-test_write_invalid_LCALTA_28 pass
2668 02:25:24.346590 alsa_mixer-test_event_missing_LCALTA_28 pass
2669 02:25:24.346958 alsa_mixer-test_event_spurious_LCALTA_28 pass
2670 02:25:24.351943 alsa_mixer-test_get_value_LCALTA_27 pass
2671 02:25:24.357780 alsa_mixer-test_name_LCALTA_27 pass
2672 02:25:24.358129 alsa_mixer-test_write_default_LCALTA_27 pass
2673 02:25:24.363439 alsa_mixer-test_write_valid_LCALTA_27 pass
2674 02:25:24.368907 alsa_mixer-test_write_invalid_LCALTA_27 pass
2675 02:25:24.369372 alsa_mixer-test_event_missing_LCALTA_27 pass
2676 02:25:24.374145 alsa_mixer-test_event_spurious_LCALTA_27 pass
2677 02:25:24.379391 alsa_mixer-test_get_value_LCALTA_26 pass
2678 02:25:24.379762 alsa_mixer-test_name_LCALTA_26 pass
2679 02:25:24.385013 alsa_mixer-test_write_default_LCALTA_26 skip
2680 02:25:24.390869 alsa_mixer-test_write_valid_LCALTA_26 skip
2681 02:25:24.391243 alsa_mixer-test_write_invalid_LCALTA_26 skip
2682 02:25:24.396351 alsa_mixer-test_event_missing_LCALTA_26 pass
2683 02:25:24.401695 alsa_mixer-test_event_spurious_LCALTA_26 pass
2684 02:25:24.412126 alsa_mixer-test_get_value_LCALTA_25 pass
2685 02:25:24.412848 alsa_mixer-test_name_LCALTA_25 pass
2686 02:25:24.413822 alsa_mixer-test_write_default_LCALTA_25 pass
2687 02:25:24.418741 alsa_mixer-test_write_valid_LCALTA_25 skip
2688 02:25:24.419326 alsa_mixer-test_write_invalid_LCALTA_25 skip
2689 02:25:24.424162 alsa_mixer-test_event_missing_LCALTA_25 pass
2690 02:25:24.429928 alsa_mixer-test_event_spurious_LCALTA_25 pass
2691 02:25:24.430566 alsa_mixer-test_get_value_LCALTA_24 pass
2692 02:25:24.435142 alsa_mixer-test_name_LCALTA_24 pass
2693 02:25:24.440504 alsa_mixer-test_write_default_LCALTA_24 skip
2694 02:25:24.441115 alsa_mixer-test_write_valid_LCALTA_24 skip
2695 02:25:24.452668 alsa_mixer-test_write_invalid_LCALTA_24 skip
2696 02:25:24.453333 alsa_mixer-test_event_missing_LCALTA_24 pass
2697 02:25:24.458044 alsa_mixer-test_event_spurious_LCALTA_24 pass
2698 02:25:24.458657 alsa_mixer-test_get_value_LCALTA_23 pass
2699 02:25:24.463778 alsa_mixer-test_name_LCALTA_23 pass
2700 02:25:24.468503 alsa_mixer-test_write_default_LCALTA_23 skip
2701 02:25:24.469177 alsa_mixer-test_write_valid_LCALTA_23 skip
2702 02:25:24.477278 alsa_mixer-test_write_invalid_LCALTA_23 skip
2703 02:25:24.479272 alsa_mixer-test_event_missing_LCALTA_23 pass
2704 02:25:24.479856 alsa_mixer-test_event_spurious_LCALTA_23 pass
2705 02:25:24.485594 alsa_mixer-test_get_value_LCALTA_22 pass
2706 02:25:24.496716 alsa_mixer-test_name_LCALTA_22 pass
2707 02:25:24.497326 alsa_mixer-test_write_default_LCALTA_22 pass
2708 02:25:24.497709 alsa_mixer-test_write_valid_LCALTA_22 pass
2709 02:25:24.502401 alsa_mixer-test_write_invalid_LCALTA_22 pass
2710 02:25:24.503032 alsa_mixer-test_event_missing_LCALTA_22 pass
2711 02:25:24.509868 alsa_mixer-test_event_spurious_LCALTA_22 pass
2712 02:25:24.516840 alsa_mixer-test_get_value_LCALTA_21 pass
2713 02:25:24.517524 alsa_mixer-test_name_LCALTA_21 pass
2714 02:25:24.523160 alsa_mixer-test_write_default_LCALTA_21 pass
2715 02:25:24.531798 alsa_mixer-test_write_valid_LCALTA_21 pass
2716 02:25:24.532534 alsa_mixer-test_write_invalid_LCALTA_21 pass
2717 02:25:24.533024 alsa_mixer-test_event_missing_LCALTA_21 pass
2718 02:25:24.544165 alsa_mixer-test_event_spurious_LCALTA_21 pass
2719 02:25:24.544792 alsa_mixer-test_get_value_LCALTA_20 pass
2720 02:25:24.545262 alsa_mixer-test_name_LCALTA_20 pass
2721 02:25:24.546550 alsa_mixer-test_write_default_LCALTA_20 pass
2722 02:25:24.551432 alsa_mixer-test_write_valid_LCALTA_20 pass
2723 02:25:24.552044 alsa_mixer-test_write_invalid_LCALTA_20 pass
2724 02:25:24.557406 alsa_mixer-test_event_missing_LCALTA_20 pass
2725 02:25:24.563158 alsa_mixer-test_event_spurious_LCALTA_20 pass
2726 02:25:24.563748 alsa_mixer-test_get_value_LCALTA_19 pass
2727 02:25:24.568800 alsa_mixer-test_name_LCALTA_19 pass
2728 02:25:24.573588 alsa_mixer-test_write_default_LCALTA_19 pass
2729 02:25:24.574171 alsa_mixer-test_write_valid_LCALTA_19 pass
2730 02:25:24.579708 alsa_mixer-test_write_invalid_LCALTA_19 pass
2731 02:25:24.585069 alsa_mixer-test_event_missing_LCALTA_19 pass
2732 02:25:24.590278 alsa_mixer-test_event_spurious_LCALTA_19 pass
2733 02:25:24.590924 alsa_mixer-test_get_value_LCALTA_18 pass
2734 02:25:24.598777 alsa_mixer-test_name_LCALTA_18 pass
2735 02:25:24.611283 alsa_mixer-test_write_default_LCALTA_18 pass
2736 02:25:24.611967 alsa_mixer-test_write_valid_LCALTA_18 pass
2737 02:25:24.612488 alsa_mixer-test_write_invalid_LCALTA_18 pass
2738 02:25:24.615848 alsa_mixer-test_event_missing_LCALTA_18 pass
2739 02:25:24.616462 alsa_mixer-test_event_spurious_LCALTA_18 pass
2740 02:25:24.617862 alsa_mixer-test_get_value_LCALTA_17 pass
2741 02:25:24.634162 alsa_mixer-test_name_LCALTA_17 pass
2742 02:25:24.634720 alsa_mixer-test_write_default_LCALTA_17 pass
2743 02:25:24.635186 alsa_mixer-test_write_valid_LCALTA_17 pass
2744 02:25:24.636072 alsa_mixer-test_write_invalid_LCALTA_17 pass
2745 02:25:24.640029 alsa_mixer-test_event_missing_LCALTA_17 pass
2746 02:25:24.640531 alsa_mixer-test_event_spurious_LCALTA_17 pass
2747 02:25:24.645445 alsa_mixer-test_get_value_LCALTA_16 pass
2748 02:25:24.645938 alsa_mixer-test_name_LCALTA_16 pass
2749 02:25:24.650983 alsa_mixer-test_write_default_LCALTA_16 pass
2750 02:25:24.656530 alsa_mixer-test_write_valid_LCALTA_16 pass
2751 02:25:24.662088 alsa_mixer-test_write_invalid_LCALTA_16 pass
2752 02:25:24.662577 alsa_mixer-test_event_missing_LCALTA_16 pass
2753 02:25:24.667648 alsa_mixer-test_event_spurious_LCALTA_16 pass
2754 02:25:24.673270 alsa_mixer-test_get_value_LCALTA_15 pass
2755 02:25:24.673785 alsa_mixer-test_name_LCALTA_15 pass
2756 02:25:24.678955 alsa_mixer-test_write_default_LCALTA_15 pass
2757 02:25:24.684369 alsa_mixer-test_write_valid_LCALTA_15 pass
2758 02:25:24.684868 alsa_mixer-test_write_invalid_LCALTA_15 pass
2759 02:25:24.689943 alsa_mixer-test_event_missing_LCALTA_15 pass
2760 02:25:24.695469 alsa_mixer-test_event_spurious_LCALTA_15 pass
2761 02:25:24.701012 alsa_mixer-test_get_value_LCALTA_14 pass
2762 02:25:24.701519 alsa_mixer-test_name_LCALTA_14 pass
2763 02:25:24.706578 alsa_mixer-test_write_default_LCALTA_14 pass
2764 02:25:24.712120 alsa_mixer-test_write_valid_LCALTA_14 pass
2765 02:25:24.712623 alsa_mixer-test_write_invalid_LCALTA_14 pass
2766 02:25:24.717654 alsa_mixer-test_event_missing_LCALTA_14 pass
2767 02:25:24.723239 alsa_mixer-test_event_spurious_LCALTA_14 pass
2768 02:25:24.723769 alsa_mixer-test_get_value_LCALTA_13 pass
2769 02:25:24.728763 alsa_mixer-test_name_LCALTA_13 pass
2770 02:25:24.734309 alsa_mixer-test_write_default_LCALTA_13 pass
2771 02:25:24.734813 alsa_mixer-test_write_valid_LCALTA_13 pass
2772 02:25:24.739963 alsa_mixer-test_write_invalid_LCALTA_13 pass
2773 02:25:24.745392 alsa_mixer-test_event_missing_LCALTA_13 pass
2774 02:25:24.745884 alsa_mixer-test_event_spurious_LCALTA_13 pass
2775 02:25:24.750960 alsa_mixer-test_get_value_LCALTA_12 pass
2776 02:25:24.756484 alsa_mixer-test_name_LCALTA_12 pass
2777 02:25:24.756982 alsa_mixer-test_write_default_LCALTA_12 pass
2778 02:25:24.762029 alsa_mixer-test_write_valid_LCALTA_12 pass
2779 02:25:24.767591 alsa_mixer-test_write_invalid_LCALTA_12 pass
2780 02:25:24.773110 alsa_mixer-test_event_missing_LCALTA_12 pass
2781 02:25:24.773603 alsa_mixer-test_event_spurious_LCALTA_12 pass
2782 02:25:24.778643 alsa_mixer-test_get_value_LCALTA_11 pass
2783 02:25:24.784227 alsa_mixer-test_name_LCALTA_11 pass
2784 02:25:24.784736 alsa_mixer-test_write_default_LCALTA_11 pass
2785 02:25:24.789815 alsa_mixer-test_write_valid_LCALTA_11 pass
2786 02:25:24.795312 alsa_mixer-test_write_invalid_LCALTA_11 pass
2787 02:25:24.795822 alsa_mixer-test_event_missing_LCALTA_11 pass
2788 02:25:24.800968 alsa_mixer-test_event_spurious_LCALTA_11 pass
2789 02:25:24.806406 alsa_mixer-test_get_value_LCALTA_10 pass
2790 02:25:24.806899 alsa_mixer-test_name_LCALTA_10 pass
2791 02:25:24.811955 alsa_mixer-test_write_default_LCALTA_10 pass
2792 02:25:24.817490 alsa_mixer-test_write_valid_LCALTA_10 pass
2793 02:25:24.817980 alsa_mixer-test_write_invalid_LCALTA_10 pass
2794 02:25:24.823032 alsa_mixer-test_event_missing_LCALTA_10 pass
2795 02:25:24.828612 alsa_mixer-test_event_spurious_LCALTA_10 pass
2796 02:25:24.834187 alsa_mixer-test_get_value_LCALTA_9 pass
2797 02:25:24.834675 alsa_mixer-test_name_LCALTA_9 pass
2798 02:25:24.839692 alsa_mixer-test_write_default_LCALTA_9 pass
2799 02:25:24.845236 alsa_mixer-test_write_valid_LCALTA_9 pass
2800 02:25:24.845745 alsa_mixer-test_write_invalid_LCALTA_9 pass
2801 02:25:24.850843 alsa_mixer-test_event_missing_LCALTA_9 pass
2802 02:25:24.856334 alsa_mixer-test_event_spurious_LCALTA_9 pass
2803 02:25:24.856824 alsa_mixer-test_get_value_LCALTA_8 pass
2804 02:25:24.861977 alsa_mixer-test_name_LCALTA_8 pass
2805 02:25:24.867425 alsa_mixer-test_write_default_LCALTA_8 pass
2806 02:25:24.867915 alsa_mixer-test_write_valid_LCALTA_8 pass
2807 02:25:24.872974 alsa_mixer-test_write_invalid_LCALTA_8 pass
2808 02:25:24.878504 alsa_mixer-test_event_missing_LCALTA_8 pass
2809 02:25:24.878990 alsa_mixer-test_event_spurious_LCALTA_8 pass
2810 02:25:24.884075 alsa_mixer-test_get_value_LCALTA_7 pass
2811 02:25:24.889595 alsa_mixer-test_name_LCALTA_7 pass
2812 02:25:24.890085 alsa_mixer-test_write_default_LCALTA_7 pass
2813 02:25:24.895150 alsa_mixer-test_write_valid_LCALTA_7 pass
2814 02:25:24.900688 alsa_mixer-test_write_invalid_LCALTA_7 pass
2815 02:25:24.901177 alsa_mixer-test_event_missing_LCALTA_7 pass
2816 02:25:24.906248 alsa_mixer-test_event_spurious_LCALTA_7 pass
2817 02:25:24.911857 alsa_mixer-test_get_value_LCALTA_6 pass
2818 02:25:24.912376 alsa_mixer-test_name_LCALTA_6 pass
2819 02:25:24.917320 alsa_mixer-test_write_default_LCALTA_6 pass
2820 02:25:24.922960 alsa_mixer-test_write_valid_LCALTA_6 pass
2821 02:25:24.923455 alsa_mixer-test_write_invalid_LCALTA_6 pass
2822 02:25:24.928527 alsa_mixer-test_event_missing_LCALTA_6 pass
2823 02:25:24.933979 alsa_mixer-test_event_spurious_LCALTA_6 pass
2824 02:25:24.934470 alsa_mixer-test_get_value_LCALTA_5 pass
2825 02:25:24.939519 alsa_mixer-test_name_LCALTA_5 pass
2826 02:25:24.945078 alsa_mixer-test_write_default_LCALTA_5 pass
2827 02:25:24.945567 alsa_mixer-test_write_valid_LCALTA_5 pass
2828 02:25:24.950629 alsa_mixer-test_write_invalid_LCALTA_5 pass
2829 02:25:24.956195 alsa_mixer-test_event_missing_LCALTA_5 pass
2830 02:25:24.956690 alsa_mixer-test_event_spurious_LCALTA_5 pass
2831 02:25:24.961738 alsa_mixer-test_get_value_LCALTA_4 pass
2832 02:25:24.967244 alsa_mixer-test_name_LCALTA_4 pass
2833 02:25:24.967727 alsa_mixer-test_write_default_LCALTA_4 pass
2834 02:25:24.972843 alsa_mixer-test_write_valid_LCALTA_4 pass
2835 02:25:24.978334 alsa_mixer-test_write_invalid_LCALTA_4 pass
2836 02:25:24.978824 alsa_mixer-test_event_missing_LCALTA_4 pass
2837 02:25:24.983961 alsa_mixer-test_event_spurious_LCALTA_4 pass
2838 02:25:24.989433 alsa_mixer-test_get_value_LCALTA_3 pass
2839 02:25:24.989914 alsa_mixer-test_name_LCALTA_3 pass
2840 02:25:24.994985 alsa_mixer-test_write_default_LCALTA_3 pass
2841 02:25:25.000534 alsa_mixer-test_write_valid_LCALTA_3 pass
2842 02:25:25.001023 alsa_mixer-test_write_invalid_LCALTA_3 pass
2843 02:25:25.006075 alsa_mixer-test_event_missing_LCALTA_3 pass
2844 02:25:25.011631 alsa_mixer-test_event_spurious_LCALTA_3 pass
2845 02:25:25.012150 alsa_mixer-test_get_value_LCALTA_2 pass
2846 02:25:25.017161 alsa_mixer-test_name_LCALTA_2 pass
2847 02:25:25.022730 alsa_mixer-test_write_default_LCALTA_2 pass
2848 02:25:25.023250 alsa_mixer-test_write_valid_LCALTA_2 pass
2849 02:25:25.028258 alsa_mixer-test_write_invalid_LCALTA_2 pass
2850 02:25:25.033953 alsa_mixer-test_event_missing_LCALTA_2 pass
2851 02:25:25.039366 alsa_mixer-test_event_spurious_LCALTA_2 pass
2852 02:25:25.039858 alsa_mixer-test_get_value_LCALTA_1 pass
2853 02:25:25.045018 alsa_mixer-test_name_LCALTA_1 pass
2854 02:25:25.045502 alsa_mixer-test_write_default_LCALTA_1 pass
2855 02:25:25.050445 alsa_mixer-test_write_valid_LCALTA_1 pass
2856 02:25:25.056023 alsa_mixer-test_write_invalid_LCALTA_1 pass
2857 02:25:25.061544 alsa_mixer-test_event_missing_LCALTA_1 pass
2858 02:25:25.062023 alsa_mixer-test_event_spurious_LCALTA_1 pass
2859 02:25:25.067102 alsa_mixer-test_get_value_LCALTA_0 pass
2860 02:25:25.067591 alsa_mixer-test_name_LCALTA_0 pass
2861 02:25:25.072650 alsa_mixer-test_write_default_LCALTA_0 pass
2862 02:25:25.078183 alsa_mixer-test_write_valid_LCALTA_0 pass
2863 02:25:25.083748 alsa_mixer-test_write_invalid_LCALTA_0 pass
2864 02:25:25.084270 alsa_mixer-test_event_missing_LCALTA_0 pass
2865 02:25:25.089292 alsa_mixer-test_event_spurious_LCALTA_0 pass
2866 02:25:25.089781 alsa_mixer-test pass
2867 02:25:25.094846 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2868 02:25:25.100366 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2869 02:25:25.106005 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2870 02:25:25.111479 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2871 02:25:25.111962 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2872 02:25:25.117003 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2873 02:25:25.122558 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2874 02:25:25.128105 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2875 02:25:25.133746 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2876 02:25:25.139206 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2877 02:25:25.139695 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2878 02:25:25.144774 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2879 02:25:25.150285 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2880 02:25:25.155927 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2881 02:25:25.161423 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2882 02:25:25.167023 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2883 02:25:25.167566 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2884 02:25:25.172495 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2885 02:25:25.178149 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2886 02:25:25.183552 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2887 02:25:25.189142 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2888 02:25:25.194683 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2889 02:25:25.195205 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2890 02:25:25.200238 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2891 02:25:25.205799 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2892 02:25:25.211336 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2893 02:25:25.216915 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2894 02:25:25.222420 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2895 02:25:25.222983 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2896 02:25:25.228051 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2897 02:25:25.233568 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2898 02:25:25.239079 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2899 02:25:25.244602 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2900 02:25:25.250131 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2901 02:25:25.255652 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2902 02:25:25.256180 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2903 02:25:25.261194 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2904 02:25:25.266776 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2905 02:25:25.272394 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2906 02:25:25.277935 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2907 02:25:25.283431 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2908 02:25:25.283920 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2909 02:25:25.289056 alsa_pcm-test pass
2910 02:25:25.294513 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2911 02:25:25.305599 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2912 02:25:25.311182 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2913 02:25:25.322296 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2914 02:25:25.327830 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2915 02:25:25.333391 alsa_test-pcmtest-driver pass
2916 02:25:25.338881 alsa_utimer-test_global_wrong_timers_test pass
2917 02:25:25.339365 alsa_utimer-test_timer_f_utimer fail
2918 02:25:25.344398 alsa_utimer-test fail
2919 02:25:25.344878 + ../../utils/send-to-lava.sh ./output/result.txt
2920 02:25:25.350025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2921 02:25:25.351031 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2923 02:25:25.361120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2924 02:25:25.361910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2926 02:25:25.368602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2927 02:25:25.369354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2929 02:25:25.376496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2930 02:25:25.377300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2932 02:25:25.425904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2933 02:25:25.426719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2935 02:25:25.469832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2936 02:25:25.470626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2938 02:25:25.514505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2939 02:25:25.515324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2941 02:25:25.559169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2942 02:25:25.560122 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2944 02:25:25.604453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2945 02:25:25.605280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2947 02:25:25.648865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2948 02:25:25.649655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2950 02:25:25.708543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2951 02:25:25.709333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2953 02:25:25.752853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2954 02:25:25.753655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2956 02:25:25.808531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2957 02:25:25.809338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2959 02:25:25.853909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2960 02:25:25.854698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2962 02:25:25.903435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2963 02:25:25.904269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2965 02:25:25.955413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2966 02:25:25.956217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2968 02:25:26.005693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2969 02:25:26.006560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2971 02:25:26.053413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2972 02:25:26.054191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2974 02:25:26.099007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2975 02:25:26.099775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2977 02:25:26.152934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2978 02:25:26.153688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2980 02:25:26.208109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2981 02:25:26.208956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2983 02:25:26.254168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2984 02:25:26.254921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2986 02:25:26.304407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2987 02:25:26.305251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2989 02:25:26.347964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2990 02:25:26.348820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2992 02:25:26.389536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2993 02:25:26.390340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2995 02:25:26.438814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2996 02:25:26.439598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2998 02:25:26.485855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
2999 02:25:26.486644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3001 02:25:26.541400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3002 02:25:26.542235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3004 02:25:26.588021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3005 02:25:26.588864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3007 02:25:26.632737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3008 02:25:26.633545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3010 02:25:26.689153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3011 02:25:26.689936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3013 02:25:26.734497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3014 02:25:26.735310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3016 02:25:26.788819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3017 02:25:26.789614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3019 02:25:26.833075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3020 02:25:26.833900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3022 02:25:26.876713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3023 02:25:26.877541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3025 02:25:26.923186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3026 02:25:26.924016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3028 02:25:26.967647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3029 02:25:26.968558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3031 02:25:27.012729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3032 02:25:27.013591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3034 02:25:27.057863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3035 02:25:27.058759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3037 02:25:27.109621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3038 02:25:27.110490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3040 02:25:27.156167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3041 02:25:27.157033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3043 02:25:27.202055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3044 02:25:27.202912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3046 02:25:27.259832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3047 02:25:27.260748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3049 02:25:27.311563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3050 02:25:27.312471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3052 02:25:27.369683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3053 02:25:27.370572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3055 02:25:27.420866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3056 02:25:27.421737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3058 02:25:27.472550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3059 02:25:27.474524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3061 02:25:27.516550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3062 02:25:27.517411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3064 02:25:27.566599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3065 02:25:27.567473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3067 02:25:27.619114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3068 02:25:27.619903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3070 02:25:27.662839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3071 02:25:27.663679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3073 02:25:27.706131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3074 02:25:27.706911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3076 02:25:27.752224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3077 02:25:27.753096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3079 02:25:27.806442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3080 02:25:27.807248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3082 02:25:27.850495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3083 02:25:27.851380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3085 02:25:27.901897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3086 02:25:27.902746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3088 02:25:27.948730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3089 02:25:27.949586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3091 02:25:27.993746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3092 02:25:27.994555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3094 02:25:28.046397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3095 02:25:28.047243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3097 02:25:28.097601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3098 02:25:28.098370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3100 02:25:28.141574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3101 02:25:28.142333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3103 02:25:28.185079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3104 02:25:28.185874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3106 02:25:28.228316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3107 02:25:28.229108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3109 02:25:28.280792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3110 02:25:28.281630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3112 02:25:28.323936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3113 02:25:28.324745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3115 02:25:28.367110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3116 02:25:28.367956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3118 02:25:28.413664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3119 02:25:28.414446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3121 02:25:28.461093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3122 02:25:28.461949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3124 02:25:28.513937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3125 02:25:28.514717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3127 02:25:28.562972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3128 02:25:28.563845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3130 02:25:28.606952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3131 02:25:28.607732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3133 02:25:28.651485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3134 02:25:28.652366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3136 02:25:28.701549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3137 02:25:28.702363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3139 02:25:28.755703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3140 02:25:28.756604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3142 02:25:28.806591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3143 02:25:28.807381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3145 02:25:28.852557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3146 02:25:28.853461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3148 02:25:28.905218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3149 02:25:28.906029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3151 02:25:28.951087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3152 02:25:28.951942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3154 02:25:29.000141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3155 02:25:29.001073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3157 02:25:29.050405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3158 02:25:29.051495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3160 02:25:29.101175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3161 02:25:29.102174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3163 02:25:29.143846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3164 02:25:29.144806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3166 02:25:29.187780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3167 02:25:29.188736 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3169 02:25:29.262548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3170 02:25:29.263450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3172 02:25:29.308464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3173 02:25:29.309471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3175 02:25:29.353861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3176 02:25:29.354493 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3178 02:25:29.400957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3179 02:25:29.401645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3181 02:25:29.457603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3182 02:25:29.458263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3184 02:25:29.515662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3185 02:25:29.516423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3187 02:25:29.573745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3188 02:25:29.574422 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3190 02:25:29.631850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3191 02:25:29.632595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3193 02:25:29.677325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3194 02:25:29.678013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3196 02:25:29.722724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3197 02:25:29.723433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3199 02:25:29.776833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3200 02:25:29.777563 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3202 02:25:29.831172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3203 02:25:29.831905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3205 02:25:29.883355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3206 02:25:29.884048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3208 02:25:29.928011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3209 02:25:29.928945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3211 02:25:29.986305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3212 02:25:29.987232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3214 02:25:30.032309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3215 02:25:30.033227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3217 02:25:30.090431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3218 02:25:30.091242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3220 02:25:30.135620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3221 02:25:30.136455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3223 02:25:30.192453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3224 02:25:30.193253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3226 02:25:30.238167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3227 02:25:30.238973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3229 02:25:30.288035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3230 02:25:30.288826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3232 02:25:30.345329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3233 02:25:30.346154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3235 02:25:30.394867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3236 02:25:30.395686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3238 02:25:30.441199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3239 02:25:30.442056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3241 02:25:30.495115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3242 02:25:30.495923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3244 02:25:30.549591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3245 02:25:30.550461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3247 02:25:30.605282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3248 02:25:30.606139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3250 02:25:30.654328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3251 02:25:30.655145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3253 02:25:30.705327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3254 02:25:30.706176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3256 02:25:30.757369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3257 02:25:30.758289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3259 02:25:30.811500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3260 02:25:30.812430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3262 02:25:30.861187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3263 02:25:30.861998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3265 02:25:30.907151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3266 02:25:30.907954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3268 02:25:30.958778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3269 02:25:30.959580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3271 02:25:31.011831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3272 02:25:31.012770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3274 02:25:31.074771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3275 02:25:31.075568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3277 02:25:31.126817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3278 02:25:31.127689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3280 02:25:31.185833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3281 02:25:31.186647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3283 02:25:31.230142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3284 02:25:31.231020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3286 02:25:31.290467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3287 02:25:31.291277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3289 02:25:31.341568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3290 02:25:31.342450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3292 02:25:31.393253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3293 02:25:31.394147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3295 02:25:31.451295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3296 02:25:31.452214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3298 02:25:31.502222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3299 02:25:31.503103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3301 02:25:31.548121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3302 02:25:31.549034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3304 02:25:31.600588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3305 02:25:31.601498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3307 02:25:31.657142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3308 02:25:31.657936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3310 02:25:31.711976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3311 02:25:31.712824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3313 02:25:31.767723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3314 02:25:31.768545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3316 02:25:31.813826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3317 02:25:31.814678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3319 02:25:31.865030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3320 02:25:31.865907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3322 02:25:31.917796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3323 02:25:31.918594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3325 02:25:31.966951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3326 02:25:31.967873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3328 02:25:32.016104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3329 02:25:32.016911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3331 02:25:32.068518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3332 02:25:32.069332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3334 02:25:32.121389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3335 02:25:32.122267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3337 02:25:32.167356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3338 02:25:32.168164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3340 02:25:32.220893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3341 02:25:32.221790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3343 02:25:32.267060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3344 02:25:32.267963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3346 02:25:32.321304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3347 02:25:32.322277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3349 02:25:32.370982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3350 02:25:32.372235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3352 02:25:32.417479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3353 02:25:32.418368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3355 02:25:32.473414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3356 02:25:32.474255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3358 02:25:32.520203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3359 02:25:32.521053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3361 02:25:32.573604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3362 02:25:32.574446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3364 02:25:32.627047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3365 02:25:32.627877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3367 02:25:32.674377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3368 02:25:32.675219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3370 02:25:32.740191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3371 02:25:32.741016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3373 02:25:32.794364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3374 02:25:32.795181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3376 02:25:32.844089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3377 02:25:32.844916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3379 02:25:32.898080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3380 02:25:32.898928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3382 02:25:32.958668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3383 02:25:32.959478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3385 02:25:33.004720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3386 02:25:33.005557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3388 02:25:33.056355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3389 02:25:33.057179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3391 02:25:33.110077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3392 02:25:33.110904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3394 02:25:33.155381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3395 02:25:33.156205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3397 02:25:33.208227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3398 02:25:33.209050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3400 02:25:33.253538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3401 02:25:33.254511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3403 02:25:33.312301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3404 02:25:33.313196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3406 02:25:33.365308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3407 02:25:33.366232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3409 02:25:33.416395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3410 02:25:33.417277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3412 02:25:33.465230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3413 02:25:33.466057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3415 02:25:33.513896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3416 02:25:33.514723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3418 02:25:33.575334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3419 02:25:33.576094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3421 02:25:33.624895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3422 02:25:33.625583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3424 02:25:33.669368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3425 02:25:33.670076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3427 02:25:33.717143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3428 02:25:33.717813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3430 02:25:33.768537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3431 02:25:33.769259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3433 02:25:33.816064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3434 02:25:33.816694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3436 02:25:33.860905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3437 02:25:33.861600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3439 02:25:33.906860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3440 02:25:33.907551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3442 02:25:33.953892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3443 02:25:33.954796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3445 02:25:34.011084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3446 02:25:34.012024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3448 02:25:34.056489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3449 02:25:34.057432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3451 02:25:34.108943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3452 02:25:34.109793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3454 02:25:34.157390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3455 02:25:34.158196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3457 02:25:34.204798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3458 02:25:34.205715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3460 02:25:34.264338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3461 02:25:34.265217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3463 02:25:34.315965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3464 02:25:34.316829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3466 02:25:34.368767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3467 02:25:34.369647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3469 02:25:34.412794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3470 02:25:34.413709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3472 02:25:34.467544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3473 02:25:34.468595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3475 02:25:34.513964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3476 02:25:34.514924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3478 02:25:34.571822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3479 02:25:34.572817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3481 02:25:34.617812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3482 02:25:34.618761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3484 02:25:34.665101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3485 02:25:34.665998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3487 02:25:34.709711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3488 02:25:34.710601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3490 02:25:34.755224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3491 02:25:34.756090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3493 02:25:34.807538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3494 02:25:34.808466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3496 02:25:34.855129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3497 02:25:34.855967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3499 02:25:34.905460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3500 02:25:34.906362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3502 02:25:34.949187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3503 02:25:34.950113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3505 02:25:34.996244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3506 02:25:34.997182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3508 02:25:35.042012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3509 02:25:35.042933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3511 02:25:35.096440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3512 02:25:35.097340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3514 02:25:35.141917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3515 02:25:35.142797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3517 02:25:35.186876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3518 02:25:35.187771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3520 02:25:35.234718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3521 02:25:35.235654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3523 02:25:35.289661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3524 02:25:35.290590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3526 02:25:35.335712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3527 02:25:35.336701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3529 02:25:35.388688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3530 02:25:35.389636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3532 02:25:35.450509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3533 02:25:35.451184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3535 02:25:35.500035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3536 02:25:35.500680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3538 02:25:35.546807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3539 02:25:35.547770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3541 02:25:35.599833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3542 02:25:35.600864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3544 02:25:35.645843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3545 02:25:35.646779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3547 02:25:35.704119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3548 02:25:35.705073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3550 02:25:35.751412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3551 02:25:35.752317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3553 02:25:35.798955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3554 02:25:35.799827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3556 02:25:35.846984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3557 02:25:35.847864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3559 02:25:35.894915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3560 02:25:35.895815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3562 02:25:35.944924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3563 02:25:35.945825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3565 02:25:35.993713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3566 02:25:35.994620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3568 02:25:36.039200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3569 02:25:36.040116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3571 02:25:36.088770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3572 02:25:36.089667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3574 02:25:36.135017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3575 02:25:36.135943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3577 02:25:36.188582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3578 02:25:36.189482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3580 02:25:36.235251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3581 02:25:36.236147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3583 02:25:36.286905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3584 02:25:36.287861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3586 02:25:36.335316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3587 02:25:36.336231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3589 02:25:36.381305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3590 02:25:36.382217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3592 02:25:36.429808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3593 02:25:36.430733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3595 02:25:36.475263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3596 02:25:36.476095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3598 02:25:36.520101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3599 02:25:36.520904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3601 02:25:36.566857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3602 02:25:36.567676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3604 02:25:36.626920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3605 02:25:36.627801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3607 02:25:36.680335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3608 02:25:36.681206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3610 02:25:36.729605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3611 02:25:36.730478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3613 02:25:36.782530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3614 02:25:36.783411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3616 02:25:36.827908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3617 02:25:36.828794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3619 02:25:36.879625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3620 02:25:36.880520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3622 02:25:36.924237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3623 02:25:36.924826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3625 02:25:36.971144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3626 02:25:36.971814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3628 02:25:37.018339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3629 02:25:37.019233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3631 02:25:37.063934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3632 02:25:37.064844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3634 02:25:37.120129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3635 02:25:37.120982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3637 02:25:37.184229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3638 02:25:37.185017 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3640 02:25:37.231326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3641 02:25:37.232081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3643 02:25:37.279097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3644 02:25:37.279913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3646 02:25:37.335215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3647 02:25:37.336035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3649 02:25:37.392195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3650 02:25:37.393056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3652 02:25:37.456877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3653 02:25:37.457690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3655 02:25:37.502085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3656 02:25:37.502801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3658 02:25:37.558302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3659 02:25:37.559344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3661 02:25:37.606967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3662 02:25:37.608028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3664 02:25:37.654983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3665 02:25:37.656039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3667 02:25:37.699091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3668 02:25:37.700128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3670 02:25:37.753453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3671 02:25:37.754321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3673 02:25:37.797233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3674 02:25:37.798045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3676 02:25:37.849813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3677 02:25:37.850812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3679 02:25:37.893967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3680 02:25:37.894971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3682 02:25:37.935558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3683 02:25:37.936592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3685 02:25:37.979195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3686 02:25:37.980240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3688 02:25:38.029456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3689 02:25:38.030198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3691 02:25:38.081894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3692 02:25:38.082951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3694 02:25:38.127473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3695 02:25:38.128551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3697 02:25:38.171348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3698 02:25:38.172374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3700 02:25:38.214961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3701 02:25:38.216020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3703 02:25:38.261090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3704 02:25:38.262103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3706 02:25:38.307665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3707 02:25:38.308711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3709 02:25:38.357260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3710 02:25:38.358254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3712 02:25:38.412502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3713 02:25:38.413554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3715 02:25:38.458745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3716 02:25:38.459712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3718 02:25:38.503114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3719 02:25:38.504124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3721 02:25:38.558544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3722 02:25:38.559254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3724 02:25:38.599872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3725 02:25:38.601044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3727 02:25:38.645769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3728 02:25:38.646411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3730 02:25:38.697115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3731 02:25:38.697735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3733 02:25:38.749173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3734 02:25:38.749813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3736 02:25:38.789956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3737 02:25:38.790655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3739 02:25:38.842598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3740 02:25:38.843226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3742 02:25:38.890224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3743 02:25:38.890844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3745 02:25:38.933509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3746 02:25:38.934487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3748 02:25:38.993274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3749 02:25:38.994154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3751 02:25:39.047731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3752 02:25:39.048682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3754 02:25:39.094280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3755 02:25:39.095185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3757 02:25:39.147795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3758 02:25:39.148691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3760 02:25:39.197429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3761 02:25:39.198315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3763 02:25:39.251745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3764 02:25:39.252783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3766 02:25:39.313497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3767 02:25:39.314658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3769 02:25:39.359488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3770 02:25:39.360538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3772 02:25:39.413970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3773 02:25:39.414936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3775 02:25:39.459070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3776 02:25:39.459968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3778 02:25:39.504292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3779 02:25:39.504928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3781 02:25:39.550391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3782 02:25:39.551274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3784 02:25:39.596290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3785 02:25:39.597212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3787 02:25:39.642033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3788 02:25:39.642940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3790 02:25:39.688302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3791 02:25:39.689203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3793 02:25:39.733067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3794 02:25:39.733980 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3796 02:25:39.777603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3797 02:25:39.778503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3799 02:25:39.823318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3800 02:25:39.824207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3802 02:25:39.869726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3803 02:25:39.870617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3805 02:25:39.913939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3806 02:25:39.914855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3808 02:25:39.964371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3809 02:25:39.965240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3811 02:25:40.017861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3812 02:25:40.018736 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3814 02:25:40.075908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3815 02:25:40.077026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3817 02:25:40.124714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3818 02:25:40.125727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3820 02:25:40.176193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3821 02:25:40.177207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3823 02:25:40.231066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3824 02:25:40.232114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3826 02:25:40.281594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3827 02:25:40.282617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3829 02:25:40.339263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3830 02:25:40.340376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3832 02:25:40.384691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3833 02:25:40.385726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3835 02:25:40.428603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3836 02:25:40.429424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3838 02:25:40.476803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3839 02:25:40.477551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3841 02:25:40.520975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3842 02:25:40.521731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3844 02:25:40.569618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3845 02:25:40.570232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3847 02:25:40.617159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3848 02:25:40.617759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3850 02:25:40.662991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3851 02:25:40.663575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3853 02:25:40.710001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3854 02:25:40.710586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3856 02:25:40.767769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3857 02:25:40.768434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3859 02:25:40.821884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3860 02:25:40.822479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3862 02:25:40.867364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3863 02:25:40.867951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3865 02:25:40.922437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3866 02:25:40.923038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3868 02:25:40.970465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3869 02:25:40.971059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3871 02:25:41.023620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3872 02:25:41.024547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3874 02:25:41.084556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3875 02:25:41.085374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3877 02:25:41.128349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3878 02:25:41.129148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3880 02:25:41.178372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3881 02:25:41.179177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3883 02:25:41.223505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3884 02:25:41.224334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3886 02:25:41.276642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3887 02:25:41.277443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3889 02:25:41.323086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3890 02:25:41.323886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3892 02:25:41.374116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3893 02:25:41.374924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3895 02:25:41.426420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3896 02:25:41.427284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3898 02:25:41.473095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3899 02:25:41.473773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3901 02:25:41.528215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3902 02:25:41.528863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3904 02:25:41.579877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3905 02:25:41.580857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3907 02:25:41.627128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3908 02:25:41.627959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3910 02:25:41.677907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3911 02:25:41.678871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3913 02:25:41.730009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3914 02:25:41.730936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3916 02:25:41.778793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3917 02:25:41.779754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3919 02:25:41.829948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3920 02:25:41.830839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3922 02:25:41.881496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3923 02:25:41.882389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3925 02:25:41.934520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3926 02:25:41.935368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3928 02:25:41.978533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3929 02:25:41.979410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3931 02:25:42.032012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3932 02:25:42.032970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3934 02:25:42.086504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3935 02:25:42.087400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3937 02:25:42.130406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3938 02:25:42.131265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3940 02:25:42.180529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3941 02:25:42.181425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3943 02:25:42.233480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3944 02:25:42.234335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3946 02:25:42.282025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3947 02:25:42.282942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3949 02:25:42.340059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3950 02:25:42.340865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3952 02:25:42.385688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3953 02:25:42.386496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3955 02:25:42.439844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3956 02:25:42.440752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3958 02:25:42.486017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3959 02:25:42.486787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3961 02:25:42.541072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3962 02:25:42.542018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3964 02:25:42.593597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3965 02:25:42.594484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3967 02:25:42.639157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3968 02:25:42.639933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3970 02:25:42.684159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3971 02:25:42.684932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3973 02:25:42.729111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3974 02:25:42.729900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3976 02:25:42.774082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3977 02:25:42.774860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3979 02:25:42.819396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3980 02:25:42.820164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3982 02:25:42.873141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3983 02:25:42.873940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3985 02:25:42.917743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3986 02:25:42.918565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3988 02:25:42.962818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3989 02:25:42.963668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3991 02:25:43.008966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3992 02:25:43.009811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3994 02:25:43.057860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3995 02:25:43.058658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3997 02:25:43.102324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3998 02:25:43.103120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4000 02:25:43.156317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4001 02:25:43.157096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4003 02:25:43.202327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4004 02:25:43.203095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4006 02:25:43.252778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4007 02:25:43.253537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4009 02:25:43.303177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4010 02:25:43.303942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4012 02:25:43.348919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4013 02:25:43.349679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4015 02:25:43.392691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4016 02:25:43.393549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4018 02:25:43.437292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4019 02:25:43.438184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4021 02:25:43.481692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4022 02:25:43.482527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4024 02:25:43.538767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4025 02:25:43.539679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4027 02:25:43.591551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4028 02:25:43.592466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4030 02:25:43.641393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4031 02:25:43.642263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4033 02:25:43.693772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4034 02:25:43.694642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4036 02:25:43.742643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4037 02:25:43.743518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4039 02:25:43.791711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4040 02:25:43.792617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4042 02:25:43.845267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4043 02:25:43.846079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4045 02:25:43.890322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4046 02:25:43.891206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4048 02:25:43.941713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4049 02:25:43.942578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4051 02:25:43.991278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4052 02:25:43.992164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4054 02:25:44.037209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4055 02:25:44.038080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4057 02:25:44.200171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4058 02:25:44.201053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4060 02:25:44.242646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4061 02:25:44.243468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4063 02:25:44.296525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4064 02:25:44.297302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4066 02:25:44.341456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4067 02:25:44.342252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4069 02:25:44.392046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4070 02:25:44.392862 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4072 02:25:44.437918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4073 02:25:44.438757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4075 02:25:44.495029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4076 02:25:44.495863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4078 02:25:44.546669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4079 02:25:44.547534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4081 02:25:44.602162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4082 02:25:44.603000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4084 02:25:44.648311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4085 02:25:44.649133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4087 02:25:44.693186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4088 02:25:44.694035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4090 02:25:44.738178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4091 02:25:44.739013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4093 02:25:44.791017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4094 02:25:44.791739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4096 02:25:44.847706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4097 02:25:44.848516 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4099 02:25:44.900486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4100 02:25:44.901182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4102 02:25:44.945463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4103 02:25:44.946247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4105 02:25:44.993947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4106 02:25:44.994655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4108 02:25:45.059212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4109 02:25:45.060058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4111 02:25:45.117811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4112 02:25:45.118514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4114 02:25:45.168744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4115 02:25:45.169575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4117 02:25:45.228777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4118 02:25:45.229624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4120 02:25:45.290588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4121 02:25:45.291413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4123 02:25:45.343573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4124 02:25:45.344380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4126 02:25:45.395327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4127 02:25:45.396084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4129 02:25:45.446668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4130 02:25:45.447463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4132 02:25:45.499025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4133 02:25:45.499805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4135 02:25:45.559078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4136 02:25:45.559934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4138 02:25:45.615058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4139 02:25:45.615816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4141 02:25:45.670498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4142 02:25:45.671294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4144 02:25:45.726606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4145 02:25:45.727371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4147 02:25:45.777781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4148 02:25:45.778559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4150 02:25:45.833530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4151 02:25:45.834316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4153 02:25:45.887817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4154 02:25:45.888594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4156 02:25:45.938591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4157 02:25:45.939351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4159 02:25:45.986666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4160 02:25:45.987403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4162 02:25:46.043880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4163 02:25:46.044738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4165 02:25:46.101544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4166 02:25:46.102284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4168 02:25:46.145250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4169 02:25:46.146076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4171 02:25:46.190815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4172 02:25:46.191442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4174 02:25:46.254486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4175 02:25:46.255124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4177 02:25:46.305443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4178 02:25:46.306077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4180 02:25:46.355438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4181 02:25:46.356068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4183 02:25:46.405989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4184 02:25:46.406623 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4186 02:25:46.452541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4187 02:25:46.453203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4189 02:25:46.507683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4190 02:25:46.508373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4192 02:25:46.553057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4193 02:25:46.553939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4195 02:25:46.606943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4196 02:25:46.607748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4198 02:25:46.663907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4199 02:25:46.664770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4201 02:25:46.723500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4202 02:25:46.724322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4204 02:25:46.770849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4206 02:25:46.773746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4207 02:25:46.827111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4208 02:25:46.827895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4210 02:25:46.878686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4211 02:25:46.879514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4213 02:25:46.938467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4214 02:25:46.939286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4216 02:25:46.995231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4217 02:25:46.996052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4219 02:25:47.038831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4220 02:25:47.039694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4222 02:25:47.085095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4223 02:25:47.085709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4225 02:25:47.135190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4226 02:25:47.135810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4228 02:25:47.187843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4229 02:25:47.188708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4231 02:25:47.237493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4232 02:25:47.238281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4234 02:25:47.287119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4235 02:25:47.287935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4237 02:25:47.345947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4238 02:25:47.346744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4240 02:25:47.398316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4241 02:25:47.399098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4243 02:25:47.444459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4244 02:25:47.445263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4246 02:25:47.498868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4247 02:25:47.499658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4249 02:25:47.546299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4250 02:25:47.547177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4252 02:25:47.602511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4253 02:25:47.603251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4255 02:25:47.654720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4256 02:25:47.655517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4258 02:25:47.698662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4259 02:25:47.699386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4261 02:25:47.745891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4262 02:25:47.746693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4264 02:25:47.792771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4265 02:25:47.793512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4267 02:25:47.850284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4268 02:25:47.851057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4270 02:25:47.898293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4271 02:25:47.899003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4273 02:25:47.948246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4274 02:25:47.949019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4276 02:25:47.994154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4277 02:25:47.994861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4279 02:25:48.051543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4280 02:25:48.052526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4282 02:25:48.099340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4283 02:25:48.100079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4285 02:25:48.153482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4286 02:25:48.154267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4288 02:25:48.202729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4289 02:25:48.203467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4291 02:25:48.254918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4292 02:25:48.255770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4294 02:25:48.313577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4295 02:25:48.314361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4297 02:25:48.372583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4298 02:25:48.373437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4300 02:25:48.439931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4301 02:25:48.441200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4303 02:25:48.483424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4304 02:25:48.484318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4306 02:25:48.536061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4307 02:25:48.536910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4309 02:25:48.596420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4310 02:25:48.597273 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4312 02:25:48.648315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4313 02:25:48.648961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4315 02:25:48.706243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4316 02:25:48.706898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4318 02:25:48.762055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4319 02:25:48.762743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4321 02:25:48.815195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4322 02:25:48.815876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4324 02:25:48.877236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4325 02:25:48.877885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4327 02:25:48.929061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4328 02:25:48.929712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4330 02:25:48.983684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4331 02:25:48.984400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4333 02:25:49.044176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4334 02:25:49.044845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4336 02:25:49.096915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4337 02:25:49.097570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4339 02:25:49.147817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4340 02:25:49.148537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4342 02:25:49.211724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4343 02:25:49.212411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4345 02:25:49.276661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4346 02:25:49.277440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4348 02:25:49.332147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4349 02:25:49.332787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4351 02:25:49.380158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4352 02:25:49.381267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4354 02:25:49.441431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4355 02:25:49.442936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4357 02:25:49.500684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4358 02:25:49.501392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4360 02:25:49.562709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4362 02:25:49.567854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4363 02:25:49.568272 + set +x
4364 02:25:49.574075 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 956803_1.6.2.4.5>
4365 02:25:49.574468 <LAVA_TEST_RUNNER EXIT>
4366 02:25:49.575006 Received signal: <ENDRUN> 1_kselftest-alsa 956803_1.6.2.4.5
4367 02:25:49.575442 Ending use of test pattern.
4368 02:25:49.575801 Ending test lava.1_kselftest-alsa (956803_1.6.2.4.5), duration 40.27
4370 02:25:49.576848 ok: lava_test_shell seems to have completed
4371 02:25:49.588326 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4372 02:25:49.589385 end: 3.1 lava-test-shell (duration 00:00:41) [common]
4373 02:25:49.589746 end: 3 lava-test-retry (duration 00:00:41) [common]
4374 02:25:49.590065 start: 4 finalize (timeout 00:06:11) [common]
4375 02:25:49.590394 start: 4.1 power-off (timeout 00:00:30) [common]
4376 02:25:49.590948 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4377 02:25:49.623720 >> OK - accepted request
4378 02:25:49.625726 Returned 0 in 0 seconds
4379 02:25:49.726763 end: 4.1 power-off (duration 00:00:00) [common]
4381 02:25:49.728120 start: 4.2 read-feedback (timeout 00:06:11) [common]
4382 02:25:49.728834 Listened to connection for namespace 'common' for up to 1s
4383 02:25:50.729773 Finalising connection for namespace 'common'
4384 02:25:50.730328 Disconnecting from shell: Finalise
4385 02:25:50.730638 / #
4386 02:25:50.831425 end: 4.2 read-feedback (duration 00:00:01) [common]
4387 02:25:50.832211 end: 4 finalize (duration 00:00:01) [common]
4388 02:25:50.832677 Cleaning after the job
4389 02:25:50.833065 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/ramdisk
4390 02:25:50.841087 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/kernel
4391 02:25:50.868893 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/dtb
4392 02:25:50.869992 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/nfsrootfs
4393 02:25:51.039845 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956803/tftp-deploy-s1y1wl91/modules
4394 02:25:51.059653 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/956803
4395 02:25:54.441153 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/956803
4396 02:25:54.441710 Job finished correctly