Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 28
- Errors: 0
- Boot result: PASS
- Kernel Errors: 57
1 01:54:15.933245 lava-dispatcher, installed at version: 2024.01
2 01:54:15.934053 start: 0 validate
3 01:54:15.934544 Start time: 2024-11-09 01:54:15.934513+00:00 (UTC)
4 01:54:15.935093 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:54:15.935641 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 01:54:15.981122 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:54:15.981941 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-246-gdbbaaaa6179b%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 01:54:16.014325 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:54:16.014997 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-246-gdbbaaaa6179b%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 01:54:16.045428 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:54:16.045932 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 01:54:16.075790 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:54:16.076370 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-246-gdbbaaaa6179b%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 01:54:16.112632 validate duration: 0.18
16 01:54:16.113562 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:54:16.113890 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:54:16.114193 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:54:16.114795 Not decompressing ramdisk as can be used compressed.
20 01:54:16.115218 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 01:54:16.115487 saving as /var/lib/lava/dispatcher/tmp/964071/tftp-deploy-o1rzsm1j/ramdisk/initrd.cpio.gz
22 01:54:16.115773 total size: 4775763 (4 MB)
23 01:54:16.152867 progress 0 % (0 MB)
24 01:54:16.160036 progress 5 % (0 MB)
25 01:54:16.166661 progress 10 % (0 MB)
26 01:54:16.172811 progress 15 % (0 MB)
27 01:54:16.176707 progress 20 % (0 MB)
28 01:54:16.180238 progress 25 % (1 MB)
29 01:54:16.183548 progress 30 % (1 MB)
30 01:54:16.187312 progress 35 % (1 MB)
31 01:54:16.190745 progress 40 % (1 MB)
32 01:54:16.194077 progress 45 % (2 MB)
33 01:54:16.197394 progress 50 % (2 MB)
34 01:54:16.201125 progress 55 % (2 MB)
35 01:54:16.204466 progress 60 % (2 MB)
36 01:54:16.207701 progress 65 % (2 MB)
37 01:54:16.211393 progress 70 % (3 MB)
38 01:54:16.214759 progress 75 % (3 MB)
39 01:54:16.218049 progress 80 % (3 MB)
40 01:54:16.221381 progress 85 % (3 MB)
41 01:54:16.225080 progress 90 % (4 MB)
42 01:54:16.228171 progress 95 % (4 MB)
43 01:54:16.231135 progress 100 % (4 MB)
44 01:54:16.231792 4 MB downloaded in 0.12 s (39.26 MB/s)
45 01:54:16.232362 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:54:16.233282 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:54:16.233598 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:54:16.233885 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:54:16.234354 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 01:54:16.234629 saving as /var/lib/lava/dispatcher/tmp/964071/tftp-deploy-o1rzsm1j/kernel/zImage
52 01:54:16.234846 total size: 11440640 (10 MB)
53 01:54:16.235067 No compression specified
54 01:54:16.274019 progress 0 % (0 MB)
55 01:54:16.281606 progress 5 % (0 MB)
56 01:54:16.288860 progress 10 % (1 MB)
57 01:54:16.296906 progress 15 % (1 MB)
58 01:54:16.304278 progress 20 % (2 MB)
59 01:54:16.311758 progress 25 % (2 MB)
60 01:54:16.318884 progress 30 % (3 MB)
61 01:54:16.326607 progress 35 % (3 MB)
62 01:54:16.333816 progress 40 % (4 MB)
63 01:54:16.341412 progress 45 % (4 MB)
64 01:54:16.348519 progress 50 % (5 MB)
65 01:54:16.355976 progress 55 % (6 MB)
66 01:54:16.363105 progress 60 % (6 MB)
67 01:54:16.370280 progress 65 % (7 MB)
68 01:54:16.377985 progress 70 % (7 MB)
69 01:54:16.385071 progress 75 % (8 MB)
70 01:54:16.392612 progress 80 % (8 MB)
71 01:54:16.399753 progress 85 % (9 MB)
72 01:54:16.407275 progress 90 % (9 MB)
73 01:54:16.414397 progress 95 % (10 MB)
74 01:54:16.421808 progress 100 % (10 MB)
75 01:54:16.422350 10 MB downloaded in 0.19 s (58.19 MB/s)
76 01:54:16.422850 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:54:16.423747 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:54:16.424096 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:54:16.424393 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:54:16.424863 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 01:54:16.425135 saving as /var/lib/lava/dispatcher/tmp/964071/tftp-deploy-o1rzsm1j/dtb/am335x-boneblack.dtb
83 01:54:16.425342 total size: 70568 (0 MB)
84 01:54:16.425552 No compression specified
85 01:54:16.462308 progress 46 % (0 MB)
86 01:54:16.463116 progress 92 % (0 MB)
87 01:54:16.463781 progress 100 % (0 MB)
88 01:54:16.464194 0 MB downloaded in 0.04 s (1.73 MB/s)
89 01:54:16.464651 end: 1.3.1 http-download (duration 00:00:00) [common]
91 01:54:16.465456 end: 1.3 download-retry (duration 00:00:00) [common]
92 01:54:16.465717 start: 1.4 download-retry (timeout 00:10:00) [common]
93 01:54:16.465981 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 01:54:16.466432 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 01:54:16.466668 saving as /var/lib/lava/dispatcher/tmp/964071/tftp-deploy-o1rzsm1j/nfsrootfs/full.rootfs.tar
96 01:54:16.466872 total size: 117747780 (112 MB)
97 01:54:16.467081 Using unxz to decompress xz
98 01:54:16.512583 progress 0 % (0 MB)
99 01:54:17.231063 progress 5 % (5 MB)
100 01:54:17.969869 progress 10 % (11 MB)
101 01:54:18.734697 progress 15 % (16 MB)
102 01:54:19.446375 progress 20 % (22 MB)
103 01:54:20.019257 progress 25 % (28 MB)
104 01:54:20.818917 progress 30 % (33 MB)
105 01:54:21.612600 progress 35 % (39 MB)
106 01:54:21.941038 progress 40 % (44 MB)
107 01:54:22.290511 progress 45 % (50 MB)
108 01:54:22.939929 progress 50 % (56 MB)
109 01:54:23.738855 progress 55 % (61 MB)
110 01:54:24.463528 progress 60 % (67 MB)
111 01:54:25.170495 progress 65 % (73 MB)
112 01:54:25.931804 progress 70 % (78 MB)
113 01:54:26.685737 progress 75 % (84 MB)
114 01:54:27.411700 progress 80 % (89 MB)
115 01:54:28.119228 progress 85 % (95 MB)
116 01:54:28.903439 progress 90 % (101 MB)
117 01:54:29.691139 progress 95 % (106 MB)
118 01:54:30.498056 progress 100 % (112 MB)
119 01:54:30.510368 112 MB downloaded in 14.04 s (8.00 MB/s)
120 01:54:30.511136 end: 1.4.1 http-download (duration 00:00:14) [common]
122 01:54:30.512853 end: 1.4 download-retry (duration 00:00:14) [common]
123 01:54:30.513391 start: 1.5 download-retry (timeout 00:09:46) [common]
124 01:54:30.513908 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 01:54:30.514704 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 01:54:30.515173 saving as /var/lib/lava/dispatcher/tmp/964071/tftp-deploy-o1rzsm1j/modules/modules.tar
127 01:54:30.515592 total size: 6608008 (6 MB)
128 01:54:30.516044 Using unxz to decompress xz
129 01:54:30.558547 progress 0 % (0 MB)
130 01:54:30.593352 progress 5 % (0 MB)
131 01:54:30.636206 progress 10 % (0 MB)
132 01:54:30.678833 progress 15 % (0 MB)
133 01:54:30.722307 progress 20 % (1 MB)
134 01:54:30.768519 progress 25 % (1 MB)
135 01:54:30.810865 progress 30 % (1 MB)
136 01:54:30.852967 progress 35 % (2 MB)
137 01:54:30.895969 progress 40 % (2 MB)
138 01:54:30.938752 progress 45 % (2 MB)
139 01:54:30.981824 progress 50 % (3 MB)
140 01:54:31.024232 progress 55 % (3 MB)
141 01:54:31.069471 progress 60 % (3 MB)
142 01:54:31.115725 progress 65 % (4 MB)
143 01:54:31.158815 progress 70 % (4 MB)
144 01:54:31.204412 progress 75 % (4 MB)
145 01:54:31.246709 progress 80 % (5 MB)
146 01:54:31.288957 progress 85 % (5 MB)
147 01:54:31.331640 progress 90 % (5 MB)
148 01:54:31.375445 progress 95 % (6 MB)
149 01:54:31.419741 progress 100 % (6 MB)
150 01:54:31.432562 6 MB downloaded in 0.92 s (6.87 MB/s)
151 01:54:31.433354 end: 1.5.1 http-download (duration 00:00:01) [common]
153 01:54:31.435037 end: 1.5 download-retry (duration 00:00:01) [common]
154 01:54:31.435572 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 01:54:31.436142 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 01:54:47.273168 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/964071/extract-nfsrootfs-un0dug5y
157 01:54:47.273773 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 01:54:47.274059 start: 1.6.2 lava-overlay (timeout 00:09:29) [common]
159 01:54:47.274669 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6
160 01:54:47.275092 makedir: /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin
161 01:54:47.275418 makedir: /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/tests
162 01:54:47.275729 makedir: /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/results
163 01:54:47.276089 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-add-keys
164 01:54:47.276621 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-add-sources
165 01:54:47.277121 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-background-process-start
166 01:54:47.277602 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-background-process-stop
167 01:54:47.278117 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-common-functions
168 01:54:47.278606 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-echo-ipv4
169 01:54:47.279076 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-install-packages
170 01:54:47.279544 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-installed-packages
171 01:54:47.280033 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-os-build
172 01:54:47.280518 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-probe-channel
173 01:54:47.281005 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-probe-ip
174 01:54:47.281499 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-target-ip
175 01:54:47.281962 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-target-mac
176 01:54:47.282420 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-target-storage
177 01:54:47.282889 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-test-case
178 01:54:47.283353 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-test-event
179 01:54:47.283908 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-test-feedback
180 01:54:47.284467 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-test-raise
181 01:54:47.284959 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-test-reference
182 01:54:47.285464 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-test-runner
183 01:54:47.285945 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-test-set
184 01:54:47.286411 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-test-shell
185 01:54:47.286883 Updating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-add-keys (debian)
186 01:54:47.287402 Updating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-add-sources (debian)
187 01:54:47.287915 Updating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-install-packages (debian)
188 01:54:47.288441 Updating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-installed-packages (debian)
189 01:54:47.288927 Updating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/bin/lava-os-build (debian)
190 01:54:47.289348 Creating /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/environment
191 01:54:47.289701 LAVA metadata
192 01:54:47.289952 - LAVA_JOB_ID=964071
193 01:54:47.290163 - LAVA_DISPATCHER_IP=192.168.6.2
194 01:54:47.290517 start: 1.6.2.1 ssh-authorize (timeout 00:09:29) [common]
195 01:54:47.291446 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 01:54:47.291749 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:29) [common]
197 01:54:47.291953 skipped lava-vland-overlay
198 01:54:47.292225 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 01:54:47.292478 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:29) [common]
200 01:54:47.292695 skipped lava-multinode-overlay
201 01:54:47.292935 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 01:54:47.293182 start: 1.6.2.4 test-definition (timeout 00:09:29) [common]
203 01:54:47.293425 Loading test definitions
204 01:54:47.293698 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:29) [common]
205 01:54:47.293915 Using /lava-964071 at stage 0
206 01:54:47.294971 uuid=964071_1.6.2.4.1 testdef=None
207 01:54:47.295269 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 01:54:47.295528 start: 1.6.2.4.2 test-overlay (timeout 00:09:29) [common]
209 01:54:47.297106 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 01:54:47.297885 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:29) [common]
212 01:54:47.299765 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 01:54:47.300600 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:29) [common]
215 01:54:47.302382 runner path: /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/0/tests/0_timesync-off test_uuid 964071_1.6.2.4.1
216 01:54:47.302902 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 01:54:47.303704 start: 1.6.2.4.5 git-repo-action (timeout 00:09:29) [common]
219 01:54:47.303923 Using /lava-964071 at stage 0
220 01:54:47.304291 Fetching tests from https://github.com/kernelci/test-definitions.git
221 01:54:47.304578 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/0/tests/1_kselftest-dt'
222 01:54:50.801343 Running '/usr/bin/git checkout kernelci.org
223 01:54:51.246737 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 01:54:51.249068 uuid=964071_1.6.2.4.5 testdef=None
225 01:54:51.249677 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 01:54:51.251138 start: 1.6.2.4.6 test-overlay (timeout 00:09:25) [common]
228 01:54:51.256507 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 01:54:51.258090 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:25) [common]
231 01:54:51.265190 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 01:54:51.266847 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:25) [common]
234 01:54:51.273799 runner path: /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/0/tests/1_kselftest-dt test_uuid 964071_1.6.2.4.5
235 01:54:51.274322 BOARD='beaglebone-black'
236 01:54:51.274737 BRANCH='broonie-sound'
237 01:54:51.275136 SKIPFILE='/dev/null'
238 01:54:51.275531 SKIP_INSTALL='True'
239 01:54:51.275922 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 01:54:51.276356 TST_CASENAME=''
241 01:54:51.276754 TST_CMDFILES='dt'
242 01:54:51.277724 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 01:54:51.279268 Creating lava-test-runner.conf files
245 01:54:51.279679 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/964071/lava-overlay-sy4m4cu6/lava-964071/0 for stage 0
246 01:54:51.280378 - 0_timesync-off
247 01:54:51.280847 - 1_kselftest-dt
248 01:54:51.281486 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 01:54:51.282068 start: 1.6.2.5 compress-overlay (timeout 00:09:25) [common]
250 01:55:14.570363 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 01:55:14.570824 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:02) [common]
252 01:55:14.571092 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 01:55:14.571366 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 01:55:14.571632 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:02) [common]
255 01:55:14.935484 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 01:55:14.935965 start: 1.6.4 extract-modules (timeout 00:09:01) [common]
257 01:55:14.936262 extracting modules file /var/lib/lava/dispatcher/tmp/964071/tftp-deploy-o1rzsm1j/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964071/extract-nfsrootfs-un0dug5y
258 01:55:15.848849 extracting modules file /var/lib/lava/dispatcher/tmp/964071/tftp-deploy-o1rzsm1j/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964071/extract-overlay-ramdisk-tml46kl9/ramdisk
259 01:55:16.774493 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 01:55:16.774985 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 01:55:16.775277 [common] Applying overlay to NFS
262 01:55:16.775499 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964071/compress-overlay-592o8f0a/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/964071/extract-nfsrootfs-un0dug5y
263 01:55:19.704378 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 01:55:19.704855 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 01:55:19.705131 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 01:55:19.705407 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 01:55:19.705659 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 01:55:19.705913 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 01:55:19.706162 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 01:55:19.706416 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 01:55:19.706665 Building ramdisk /var/lib/lava/dispatcher/tmp/964071/extract-overlay-ramdisk-tml46kl9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/964071/extract-overlay-ramdisk-tml46kl9/ramdisk
272 01:55:20.756485 >> 74896 blocks
273 01:55:25.363197 Adding RAMdisk u-boot header.
274 01:55:25.363712 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/964071/extract-overlay-ramdisk-tml46kl9/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/964071/extract-overlay-ramdisk-tml46kl9/ramdisk.cpio.gz.uboot
275 01:55:25.524853 output: Image Name:
276 01:55:25.525315 output: Created: Sat Nov 9 01:55:25 2024
277 01:55:25.525546 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 01:55:25.525764 output: Data Size: 14788921 Bytes = 14442.31 KiB = 14.10 MiB
279 01:55:25.525979 output: Load Address: 00000000
280 01:55:25.526191 output: Entry Point: 00000000
281 01:55:25.526412 output:
282 01:55:25.527004 rename /var/lib/lava/dispatcher/tmp/964071/extract-overlay-ramdisk-tml46kl9/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/964071/tftp-deploy-o1rzsm1j/ramdisk/ramdisk.cpio.gz.uboot
283 01:55:25.527448 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 01:55:25.527784 end: 1.6 prepare-tftp-overlay (duration 00:00:54) [common]
285 01:55:25.528573 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:51) [common]
286 01:55:25.529412 No LXC device requested
287 01:55:25.529767 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 01:55:25.530069 start: 1.8 deploy-device-env (timeout 00:08:51) [common]
289 01:55:25.530365 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 01:55:25.530597 Checking files for TFTP limit of 4294967296 bytes.
291 01:55:25.532853 end: 1 tftp-deploy (duration 00:01:09) [common]
292 01:55:25.533501 start: 2 uboot-action (timeout 00:05:00) [common]
293 01:55:25.533960 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 01:55:25.534564 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 01:55:25.534990 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 01:55:25.535690 substitutions:
297 01:55:25.536246 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 01:55:25.536657 - {DTB_ADDR}: 0x88000000
299 01:55:25.537005 - {DTB}: 964071/tftp-deploy-o1rzsm1j/dtb/am335x-boneblack.dtb
300 01:55:25.537338 - {INITRD}: 964071/tftp-deploy-o1rzsm1j/ramdisk/ramdisk.cpio.gz.uboot
301 01:55:25.537668 - {KERNEL_ADDR}: 0x82000000
302 01:55:25.538198 - {KERNEL}: 964071/tftp-deploy-o1rzsm1j/kernel/zImage
303 01:55:25.538697 - {LAVA_MAC}: None
304 01:55:25.539089 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/964071/extract-nfsrootfs-un0dug5y
305 01:55:25.539438 - {NFS_SERVER_IP}: 192.168.6.2
306 01:55:25.539809 - {PRESEED_CONFIG}: None
307 01:55:25.540167 - {PRESEED_LOCAL}: None
308 01:55:25.540404 - {RAMDISK_ADDR}: 0x83000000
309 01:55:25.540617 - {RAMDISK}: 964071/tftp-deploy-o1rzsm1j/ramdisk/ramdisk.cpio.gz.uboot
310 01:55:25.540830 - {ROOT_PART}: None
311 01:55:25.541059 - {ROOT}: None
312 01:55:25.541281 - {SERVER_IP}: 192.168.6.2
313 01:55:25.541486 - {TEE_ADDR}: 0x83000000
314 01:55:25.541690 - {TEE}: None
315 01:55:25.541893 Parsed boot commands:
316 01:55:25.542102 - setenv autoload no
317 01:55:25.542315 - setenv initrd_high 0xffffffff
318 01:55:25.543435 - setenv fdt_high 0xffffffff
319 01:55:25.544106 - dhcp
320 01:55:25.544536 - setenv serverip 192.168.6.2
321 01:55:25.544880 - tftp 0x82000000 964071/tftp-deploy-o1rzsm1j/kernel/zImage
322 01:55:25.545366 - tftp 0x83000000 964071/tftp-deploy-o1rzsm1j/ramdisk/ramdisk.cpio.gz.uboot
323 01:55:25.545764 - setenv initrd_size ${filesize}
324 01:55:25.546393 - tftp 0x88000000 964071/tftp-deploy-o1rzsm1j/dtb/am335x-boneblack.dtb
325 01:55:25.546806 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/964071/extract-nfsrootfs-un0dug5y,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 01:55:25.547174 - bootz 0x82000000 0x83000000 0x88000000
327 01:55:25.547603 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 01:55:25.548747 start: 2.3 connect-device (timeout 00:05:00) [common]
330 01:55:25.549120 [common] connect-device Connecting to device using 'telnet conserv3 3001'
331 01:55:25.561902 Setting prompt string to ['lava-test: # ']
332 01:55:25.563217 end: 2.3 connect-device (duration 00:00:00) [common]
333 01:55:25.563804 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 01:55:25.564561 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 01:55:25.565442 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 01:55:25.566480 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-04'
337 01:55:25.599291 >> OK - accepted request
338 01:55:25.601480 Returned 0 in 0 seconds
339 01:55:25.702470 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 01:55:25.703504 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 01:55:25.703827 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 01:55:25.704167 Setting prompt string to ['Hit any key to stop autoboot']
344 01:55:25.704436 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 01:55:25.705364 Trying 192.168.56.22...
346 01:55:25.705653 Connected to conserv3.
347 01:55:25.705881 Escape character is '^]'.
348 01:55:25.706101
349 01:55:25.706318 ser2net port telnet,3001 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 01:55:25.706539
351 01:56:02.660224
352 01:56:02.667084 U-Boot SPL 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
353 01:56:02.667408 Trying to boot from MMC1
354 01:56:03.245365
355 01:56:03.245758
356 01:56:03.250900 U-Boot 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
357 01:56:03.251185
358 01:56:03.251398 CPU : AM335X-GP rev 2.0
359 01:56:03.256040 Model: TI AM335x BeagleBone Black
360 01:56:03.256330 DRAM: 512 MiB
361 01:56:03.340944 Core: 160 devices, 18 uclasses, devicetree: separate
362 01:56:03.354697 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
363 01:56:03.755443 NAND: 0 MiB
364 01:56:03.765580 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
365 01:56:03.840258 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
366 01:56:03.861591 <ethaddr> not set. Validating first E-fuse MAC
367 01:56:03.891350 Net: eth2: ethernet@4a100000, eth3: usb_ether
369 01:56:03.949592 Hit any key to stop autoboot: 2
370 01:56:03.950307 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
371 01:56:03.950664 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
372 01:56:03.950923 Setting prompt string to ['=>']
373 01:56:03.951183 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
374 01:56:03.959738 0
375 01:56:03.960388 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
376 01:56:03.960674 Sending with 10 millisecond of delay
378 01:56:05.095530 => setenv autoload no
379 01:56:05.106793 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
380 01:56:05.111766 setenv autoload no
381 01:56:05.112554 Sending with 10 millisecond of delay
383 01:56:06.912196 => setenv initrd_high 0xffffffff
384 01:56:06.923044 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
385 01:56:06.923707 setenv initrd_high 0xffffffff
386 01:56:06.924465 Sending with 10 millisecond of delay
388 01:56:08.540859 => setenv fdt_high 0xffffffff
389 01:56:08.551512 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
390 01:56:08.552188 setenv fdt_high 0xffffffff
391 01:56:08.552665 Sending with 10 millisecond of delay
393 01:56:08.844185 => dhcp
394 01:56:08.854773 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
395 01:56:08.855335 dhcp
396 01:56:08.857246 link up on port 0, speed 100, full duplex
397 01:56:08.857522 BOOTP broadcast 1
398 01:56:08.943173 DHCP client bound to address 192.168.6.16 (83 ms)
399 01:56:08.943828 Sending with 10 millisecond of delay
401 01:56:10.620583 => setenv serverip 192.168.6.2
402 01:56:10.631134 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
403 01:56:10.631639 setenv serverip 192.168.6.2
404 01:56:10.632119 Sending with 10 millisecond of delay
406 01:56:14.112848 => tftp 0x82000000 964071/tftp-deploy-o1rzsm1j/kernel/zImage
407 01:56:14.124014 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
408 01:56:14.124591 tftp 0x82000000 964071/tftp-deploy-o1rzsm1j/kernel/zImage
409 01:56:14.124851 link up on port 0, speed 100, full duplex
410 01:56:14.128068 Using ethernet@4a100000 device
411 01:56:14.133657 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
412 01:56:14.141941 Filename '964071/tftp-deploy-o1rzsm1j/kernel/zImage'.
413 01:56:14.142343 Load address: 0x82000000
414 01:56:16.450778 Loading: *################################################## 10.9 MiB
415 01:56:16.451400 4.7 MiB/s
416 01:56:16.451832 done
417 01:56:16.454992 Bytes transferred = 11440640 (ae9200 hex)
418 01:56:16.455731 Sending with 10 millisecond of delay
420 01:56:20.907183 => tftp 0x83000000 964071/tftp-deploy-o1rzsm1j/ramdisk/ramdisk.cpio.gz.uboot
421 01:56:20.917853 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
422 01:56:20.918558 tftp 0x83000000 964071/tftp-deploy-o1rzsm1j/ramdisk/ramdisk.cpio.gz.uboot
423 01:56:20.918832 link up on port 0, speed 100, full duplex
424 01:56:20.922900 Using ethernet@4a100000 device
425 01:56:20.928457 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
426 01:56:20.938881 Filename '964071/tftp-deploy-o1rzsm1j/ramdisk/ramdisk.cpio.gz.uboot'.
427 01:56:20.939549 Load address: 0x83000000
428 01:56:23.535624 Loading: *################################################## 14.1 MiB
429 01:56:23.536558 5.4 MiB/s
430 01:56:23.537704 done
431 01:56:23.539823 Bytes transferred = 14788985 (e1a979 hex)
432 01:56:23.540824 Sending with 10 millisecond of delay
434 01:56:25.404633 => setenv initrd_size ${filesize}
435 01:56:25.415443 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
436 01:56:25.416362 setenv initrd_size ${filesize}
437 01:56:25.417068 Sending with 10 millisecond of delay
439 01:56:29.567261 => tftp 0x88000000 964071/tftp-deploy-o1rzsm1j/dtb/am335x-boneblack.dtb
440 01:56:29.578103 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:56)
441 01:56:29.578699 tftp 0x88000000 964071/tftp-deploy-o1rzsm1j/dtb/am335x-boneblack.dtb
442 01:56:29.578955 link up on port 0, speed 100, full duplex
443 01:56:29.582685 Using ethernet@4a100000 device
444 01:56:29.588186 TFTP from server 192.168.6.2; our IP address is 192.168.6.16
445 01:56:29.601384 Filename '964071/tftp-deploy-o1rzsm1j/dtb/am335x-boneblack.dtb'.
446 01:56:29.601751 Load address: 0x88000000
447 01:56:29.612497 Loading: *################################################## 68.9 KiB
448 01:56:29.612836 4.2 MiB/s
449 01:56:29.613139 done
450 01:56:29.618664 Bytes transferred = 70568 (113a8 hex)
451 01:56:29.619192 Sending with 10 millisecond of delay
453 01:56:42.800071 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/964071/extract-nfsrootfs-un0dug5y,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
454 01:56:42.811112 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:43)
455 01:56:42.812267 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/964071/extract-nfsrootfs-un0dug5y,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
456 01:56:42.813156 Sending with 10 millisecond of delay
458 01:56:45.154293 => bootz 0x82000000 0x83000000 0x88000000
459 01:56:45.165075 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
460 01:56:45.165618 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:40)
461 01:56:45.166606 bootz 0x82000000 0x83000000 0x88000000
462 01:56:45.167054 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
463 01:56:45.167533 ## Loading init Ramdisk from Legacy Image at 83000000 ...
464 01:56:45.172803 Image Name:
465 01:56:45.173237 Created: 2024-11-09 1:55:25 UTC
466 01:56:45.178291 Image Type: ARM Linux RAMDisk Image (uncompressed)
467 01:56:45.183878 Data Size: 14788921 Bytes = 14.1 MiB
468 01:56:45.184341 Load Address: 00000000
469 01:56:45.190057 Entry Point: 00000000
470 01:56:45.358437 Verifying Checksum ... OK
471 01:56:45.358928 ## Flattened Device Tree blob at 88000000
472 01:56:45.364867 Booting using the fdt blob at 0x88000000
473 01:56:45.365322 Working FDT set to 88000000
474 01:56:45.370502 Using Device Tree in place at 88000000, end 880143a7
475 01:56:45.374878 Working FDT set to 88000000
476 01:56:45.388257
477 01:56:45.388695 Starting kernel ...
478 01:56:45.389093
479 01:56:45.389941 end: 2.4.3 bootloader-commands (duration 00:00:41) [common]
480 01:56:45.390521 start: 2.4.4 auto-login-action (timeout 00:03:40) [common]
481 01:56:45.390974 Setting prompt string to ['Linux version [0-9]']
482 01:56:45.391414 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 01:56:45.391863 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
484 01:56:46.234305 [ 0.000000] Booting Linux on physical CPU 0x0
485 01:56:46.240316 start: 2.4.4.1 login-action (timeout 00:03:39) [common]
486 01:56:46.240953 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
487 01:56:46.241463 Setting prompt string to []
488 01:56:46.241986 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
489 01:56:46.242479 Using line separator: #'\n'#
490 01:56:46.242920 No login prompt set.
491 01:56:46.243385 Parsing kernel messages
492 01:56:46.243813 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
493 01:56:46.244685 [login-action] Waiting for messages, (timeout 00:03:39)
494 01:56:46.245170 Waiting using forced prompt support (timeout 00:01:50)
495 01:56:46.256929 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j370458-arm-gcc-12-multi-v7-defconfig-vlf86) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Sat Nov 9 01:33:17 UTC 2024
496 01:56:46.262630 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
497 01:56:46.268363 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
498 01:56:46.279772 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
499 01:56:46.285529 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
500 01:56:46.291210 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
501 01:56:46.291724 [ 0.000000] Memory policy: Data cache writeback
502 01:56:46.298028 [ 0.000000] efi: UEFI not found.
503 01:56:46.306702 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
504 01:56:46.307207 [ 0.000000] Zone ranges:
505 01:56:46.312407 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
506 01:56:46.318163 [ 0.000000] Normal empty
507 01:56:46.323842 [ 0.000000] HighMem empty
508 01:56:46.324426 [ 0.000000] Movable zone start for each node
509 01:56:46.329756 [ 0.000000] Early memory node ranges
510 01:56:46.335487 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
511 01:56:46.342218 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
512 01:56:46.368400 [ 0.000000] CPU: All CPU(s) started in SVC mode.
513 01:56:46.374143 [ 0.000000] AM335X ES2.0 (sgx neon)
514 01:56:46.385778 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
515 01:56:46.403326 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/964071/extract-nfsrootfs-un0dug5y,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
516 01:56:46.414921 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
517 01:56:46.420691 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
518 01:56:46.426398 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
519 01:56:46.436382 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
520 01:56:46.465413 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
521 01:56:46.471430 <6>[ 0.000000] trace event string verifier disabled
522 01:56:46.471968 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
523 01:56:46.479409 <6>[ 0.000000] rcu: RCU event tracing is enabled.
524 01:56:46.485199 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
525 01:56:46.496638 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
526 01:56:46.501630 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
527 01:56:46.516492 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
528 01:56:46.533621 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
529 01:56:46.540477 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
530 01:56:46.632080 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
531 01:56:46.643491 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
532 01:56:46.650312 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
533 01:56:46.663296 <6>[ 0.019144] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
534 01:56:46.670632 <6>[ 0.033926] Console: colour dummy device 80x30
535 01:56:46.676792 Matched prompt #6: WARNING:
536 01:56:46.677390 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
537 01:56:46.682167 <3>[ 0.038825] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
538 01:56:46.685046 <3>[ 0.045893] This ensures that you still see kernel messages. Please
539 01:56:46.691181 <3>[ 0.052621] update your kernel commandline.
540 01:56:46.731795 <6>[ 0.057234] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
541 01:56:46.737637 <6>[ 0.096151] CPU: Testing write buffer coherency: ok
542 01:56:46.743549 <6>[ 0.101518] CPU0: Spectre v2: using BPIALL workaround
543 01:56:46.744108 <6>[ 0.106984] pid_max: default: 32768 minimum: 301
544 01:56:46.754971 <6>[ 0.112182] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
545 01:56:46.762070 <6>[ 0.120006] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
546 01:56:46.769096 <6>[ 0.129357] CPU0: thread -1, cpu 0, socket -1, mpidr 0
547 01:56:46.777465 <6>[ 0.136350] Setting up static identity map for 0x80300000 - 0x803000ac
548 01:56:46.783273 <6>[ 0.145975] rcu: Hierarchical SRCU implementation.
549 01:56:46.790884 <6>[ 0.151260] rcu: Max phase no-delay instances is 1000.
550 01:56:46.799407 <6>[ 0.162356] EFI services will not be available.
551 01:56:46.805241 <6>[ 0.167636] smp: Bringing up secondary CPUs ...
552 01:56:46.810951 <6>[ 0.172689] smp: Brought up 1 node, 1 CPU
553 01:56:46.816723 <6>[ 0.177089] SMP: Total of 1 processors activated (996.14 BogoMIPS).
554 01:56:46.822669 <6>[ 0.183858] CPU: All CPU(s) started in SVC mode.
555 01:56:46.842938 <6>[ 0.189035] Memory: 406000K/522240K available (16384K kernel code, 2542K rwdata, 6784K rodata, 2048K init, 431K bss, 49048K reserved, 65536K cma-reserved, 0K highmem)
556 01:56:46.843552 <6>[ 0.205328] devtmpfs: initialized
557 01:56:46.865156 <6>[ 0.222396] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
558 01:56:46.876632 <6>[ 0.230979] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
559 01:56:46.882415 <6>[ 0.241442] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
560 01:56:46.893406 <6>[ 0.253737] pinctrl core: initialized pinctrl subsystem
561 01:56:46.902667 <6>[ 0.264361] DMI not present or invalid.
562 01:56:46.910938 <6>[ 0.270228] NET: Registered PF_NETLINK/PF_ROUTE protocol family
563 01:56:46.920391 <6>[ 0.279120] DMA: preallocated 256 KiB pool for atomic coherent allocations
564 01:56:46.935510 <6>[ 0.290670] thermal_sys: Registered thermal governor 'step_wise'
565 01:56:46.936076 <6>[ 0.290836] cpuidle: using governor menu
566 01:56:46.963142 <6>[ 0.326417] No ATAGs?
567 01:56:46.969318 <6>[ 0.329058] hw-breakpoint: debug architecture 0x4 unsupported.
568 01:56:46.979601 <6>[ 0.341099] Serial: AMBA PL011 UART driver
569 01:56:47.012113 <6>[ 0.375262] iommu: Default domain type: Translated
570 01:56:47.021145 <6>[ 0.380614] iommu: DMA domain TLB invalidation policy: strict mode
571 01:56:47.048107 <5>[ 0.410656] SCSI subsystem initialized
572 01:56:47.053958 <6>[ 0.415533] usbcore: registered new interface driver usbfs
573 01:56:47.059713 <6>[ 0.421598] usbcore: registered new interface driver hub
574 01:56:47.068407 <6>[ 0.427380] usbcore: registered new device driver usb
575 01:56:47.074198 <6>[ 0.433904] pps_core: LinuxPPS API ver. 1 registered
576 01:56:47.080102 <6>[ 0.439292] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
577 01:56:47.085904 <6>[ 0.449021] PTP clock support registered
578 01:56:47.090929 <6>[ 0.453483] EDAC MC: Ver: 3.0.0
579 01:56:47.139655 <6>[ 0.500402] scmi_core: SCMI protocol bus registered
580 01:56:47.154776 <6>[ 0.517760] vgaarb: loaded
581 01:56:47.167216 <6>[ 0.530791] clocksource: Switched to clocksource dmtimer
582 01:56:47.203809 <6>[ 0.566930] NET: Registered PF_INET protocol family
583 01:56:47.216335 <6>[ 0.572626] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
584 01:56:47.222144 <6>[ 0.581438] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
585 01:56:47.233615 <6>[ 0.590372] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
586 01:56:47.239417 <6>[ 0.598634] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
587 01:56:47.250974 <6>[ 0.606917] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
588 01:56:47.256931 <6>[ 0.614644] TCP: Hash tables configured (established 4096 bind 4096)
589 01:56:47.262585 <6>[ 0.621545] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
590 01:56:47.268504 <6>[ 0.628587] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
591 01:56:47.276116 <6>[ 0.636185] NET: Registered PF_UNIX/PF_LOCAL protocol family
592 01:56:47.367244 <6>[ 0.724926] RPC: Registered named UNIX socket transport module.
593 01:56:47.368069 <6>[ 0.731312] RPC: Registered udp transport module.
594 01:56:47.373114 <6>[ 0.736466] RPC: Registered tcp transport module.
595 01:56:47.378946 <6>[ 0.741592] RPC: Registered tcp-with-tls transport module.
596 01:56:47.391910 <6>[ 0.747501] RPC: Registered tcp NFSv4.1 backchannel transport module.
597 01:56:47.392500 <6>[ 0.754424] PCI: CLS 0 bytes, default 64
598 01:56:47.398992 <5>[ 0.760205] Initialise system trusted keyrings
599 01:56:47.418510 <6>[ 0.778783] Trying to unpack rootfs image as initramfs...
600 01:56:47.504200 <6>[ 0.861193] workingset: timestamp_bits=30 max_order=17 bucket_order=0
601 01:56:47.508910 <6>[ 0.868736] squashfs: version 4.0 (2009/01/31) Phillip Lougher
602 01:56:47.529489 <5>[ 0.892705] NFS: Registering the id_resolver key type
603 01:56:47.535284 <5>[ 0.898307] Key type id_resolver registered
604 01:56:47.541101 <5>[ 0.902995] Key type id_legacy registered
605 01:56:47.546928 <6>[ 0.907437] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
606 01:56:47.556548 <6>[ 0.914633] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
607 01:56:47.625386 <5>[ 0.988559] Key type asymmetric registered
608 01:56:47.631145 <5>[ 0.993136] Asymmetric key parser 'x509' registered
609 01:56:47.642757 <6>[ 0.998566] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
610 01:56:47.643336 <6>[ 1.006486] io scheduler mq-deadline registered
611 01:56:47.648428 <6>[ 1.011418] io scheduler kyber registered
612 01:56:47.653947 <6>[ 1.015901] io scheduler bfq registered
613 01:56:47.773395 <6>[ 1.132968] ledtrig-cpu: registered to indicate activity on CPUs
614 01:56:48.064452 <6>[ 1.423816] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
615 01:56:48.093504 <6>[ 1.456656] msm_serial: driver initialized
616 01:56:48.099705 <6>[ 1.461437] SuperH (H)SCI(F) driver initialized
617 01:56:48.105524 <6>[ 1.466780] STMicroelectronics ASC driver initialized
618 01:56:48.110834 <6>[ 1.472456] STM32 USART driver initialized
619 01:56:48.251802 <6>[ 1.614482] brd: module loaded
620 01:56:48.286432 <6>[ 1.649013] loop: module loaded
621 01:56:48.326709 <6>[ 1.689152] CAN device driver interface
622 01:56:48.333135 <6>[ 1.694344] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
623 01:56:48.338970 <6>[ 1.701246] e1000e: Intel(R) PRO/1000 Network Driver
624 01:56:48.344892 <6>[ 1.706698] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
625 01:56:48.350512 <6>[ 1.713146] igb: Intel(R) Gigabit Ethernet Network Driver
626 01:56:48.358882 <6>[ 1.718970] igb: Copyright (c) 2007-2014 Intel Corporation.
627 01:56:48.370578 <6>[ 1.728108] pegasus: Pegasus/Pegasus II USB Ethernet driver
628 01:56:48.376315 <6>[ 1.734266] usbcore: registered new interface driver pegasus
629 01:56:48.382027 <6>[ 1.740392] usbcore: registered new interface driver asix
630 01:56:48.387785 <6>[ 1.746271] usbcore: registered new interface driver ax88179_178a
631 01:56:48.393599 <6>[ 1.752860] usbcore: registered new interface driver cdc_ether
632 01:56:48.399298 <6>[ 1.759159] usbcore: registered new interface driver smsc75xx
633 01:56:48.405162 <6>[ 1.765399] usbcore: registered new interface driver smsc95xx
634 01:56:48.411036 <6>[ 1.771638] usbcore: registered new interface driver net1080
635 01:56:48.416818 <6>[ 1.777764] usbcore: registered new interface driver cdc_subset
636 01:56:48.422529 <6>[ 1.784195] usbcore: registered new interface driver zaurus
637 01:56:48.430144 <6>[ 1.790241] usbcore: registered new interface driver cdc_ncm
638 01:56:48.439875 <6>[ 1.799624] usbcore: registered new interface driver usb-storage
639 01:56:48.712485 <6>[ 2.073972] i2c_dev: i2c /dev entries driver
640 01:56:48.763020 <5>[ 2.118431] cpuidle: enable-method property 'ti,am3352' found operations
641 01:56:48.768850 <6>[ 2.128043] sdhci: Secure Digital Host Controller Interface driver
642 01:56:48.776600 <6>[ 2.134814] sdhci: Copyright(c) Pierre Ossman
643 01:56:48.783778 <6>[ 2.141197] Synopsys Designware Multimedia Card Interface Driver
644 01:56:48.788926 <6>[ 2.149101] sdhci-pltfm: SDHCI platform and OF driver helper
645 01:56:48.920590 <6>[ 2.276479] usbcore: registered new interface driver usbhid
646 01:56:48.921119 <6>[ 2.282656] usbhid: USB HID core driver
647 01:56:48.957429 <6>[ 2.318257] NET: Registered PF_INET6 protocol family
648 01:56:49.000095 <6>[ 2.363577] Segment Routing with IPv6
649 01:56:49.006031 <6>[ 2.367725] In-situ OAM (IOAM) with IPv6
650 01:56:49.012681 <6>[ 2.372251] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
651 01:56:49.018542 <6>[ 2.379528] NET: Registered PF_PACKET protocol family
652 01:56:49.024402 <6>[ 2.385091] can: controller area network core
653 01:56:49.030249 <6>[ 2.389916] NET: Registered PF_CAN protocol family
654 01:56:49.030725 <6>[ 2.395142] can: raw protocol
655 01:56:49.035937 <6>[ 2.398469] can: broadcast manager protocol
656 01:56:49.042471 <6>[ 2.403073] can: netlink gateway - max_hops=1
657 01:56:49.048604 <5>[ 2.408571] Key type dns_resolver registered
658 01:56:49.054914 <6>[ 2.413659] ThumbEE CPU extension supported.
659 01:56:49.055408 <5>[ 2.418347] Registering SWP/SWPB emulation handler
660 01:56:49.064624 <3>[ 2.424043] omap_voltage_late_init: Voltage driver support not added
661 01:56:49.271484 <5>[ 2.632321] Loading compiled-in X.509 certificates
662 01:56:49.414282 <6>[ 2.764420] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
663 01:56:49.420274 <6>[ 2.781086] pinctrl-single 44e10800.pinmux: 142 pins, size 568
664 01:56:49.447812 <3>[ 2.805009] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
665 01:56:49.643831 <3>[ 3.001097] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
666 01:56:49.840510 <6>[ 3.202026] OMAP GPIO hardware version 0.1
667 01:56:49.861094 <6>[ 3.220721] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
668 01:56:49.954237 <4>[ 3.313585] at24 2-0054: supply vcc not found, using dummy regulator
669 01:56:49.989796 <4>[ 3.349162] at24 2-0055: supply vcc not found, using dummy regulator
670 01:56:50.028777 <4>[ 3.388127] at24 2-0056: supply vcc not found, using dummy regulator
671 01:56:50.066031 <4>[ 3.425390] at24 2-0057: supply vcc not found, using dummy regulator
672 01:56:50.104520 <6>[ 3.464676] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
673 01:56:50.181921 <3>[ 3.538049] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
674 01:56:50.205514 <6>[ 3.558878] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
675 01:56:50.228672 <4>[ 3.585265] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
676 01:56:50.236547 <4>[ 3.594524] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
677 01:56:50.342799 <6>[ 3.702309] omap_rng 48310000.rng: Random Number Generator ver. 20
678 01:56:50.366644 <5>[ 3.728920] random: crng init done
679 01:56:50.421232 <6>[ 3.784297] Freeing initrd memory: 14444K
680 01:56:50.430855 <6>[ 3.788937] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
681 01:56:50.486886 <6>[ 3.844044] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
682 01:56:50.492743 <6>[ 3.854371] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
683 01:56:50.504571 <6>[ 3.861711] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
684 01:56:50.510390 <6>[ 3.869164] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
685 01:56:50.521810 <6>[ 3.877295] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
686 01:56:50.529217 <6>[ 3.888937] cpsw-switch 4a100000.switch: Detected MACID = c8:a0:30:c2:c5:7d
687 01:56:50.542324 <5>[ 3.897956] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
688 01:56:50.570192 <3>[ 3.927825] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
689 01:56:50.576060 <6>[ 3.936419] edma 49000000.dma: TI EDMA DMA engine driver
690 01:56:50.647482 <3>[ 4.004413] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
691 01:56:50.662203 <6>[ 4.018799] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
692 01:56:50.675207 <3>[ 4.035938] l3-aon-clkctrl:0000:0: failed to disable
693 01:56:50.725114 <6>[ 4.082742] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
694 01:56:50.730839 <6>[ 4.092215] printk: legacy console [ttyS0] enabled
695 01:56:50.736601 <6>[ 4.092215] printk: legacy console [ttyS0] enabled
696 01:56:50.742241 <6>[ 4.102552] printk: legacy bootconsole [omap8250] disabled
697 01:56:50.747168 <6>[ 4.102552] printk: legacy bootconsole [omap8250] disabled
698 01:56:50.785758 <4>[ 4.142387] tps65217-pmic: Failed to locate of_node [id: -1]
699 01:56:50.789396 <4>[ 4.149775] tps65217-bl: Failed to locate of_node [id: -1]
700 01:56:50.805963 <6>[ 4.169489] tps65217 0-0024: TPS65217 ID 0xe version 1.2
701 01:56:50.824313 <6>[ 4.176450] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
702 01:56:50.835957 <6>[ 4.190131] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
703 01:56:50.841734 <6>[ 4.202018] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
704 01:56:50.863756 <6>[ 4.221808] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
705 01:56:50.869680 <6>[ 4.230865] sdhci-omap 48060000.mmc: Got CD GPIO
706 01:56:50.877721 <4>[ 4.236043] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
707 01:56:50.892230 <4>[ 4.249541] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
708 01:56:50.898615 <4>[ 4.258160] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
709 01:56:50.908481 <4>[ 4.266812] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
710 01:56:51.007326 <6>[ 4.366344] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
711 01:56:51.054691 <6>[ 4.412428] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
712 01:56:51.061094 <6>[ 4.420839] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
713 01:56:51.070212 <6>[ 4.429615] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
714 01:56:51.122660 <6>[ 4.482995] mmc0: new high speed SDHC card at address 0001
715 01:56:51.130843 <6>[ 4.492305] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
716 01:56:51.140712 <6>[ 4.503948] mmcblk0: p1
717 01:56:51.158108 <6>[ 4.513418] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
718 01:56:51.167361 <4>[ 4.527754] mmc1: unexpected status 0x2000980 after switch
719 01:56:51.184732 <4>[ 4.542066] mmc1: unexpected status 0x2000900 after switch
720 01:56:51.192652 <4>[ 4.548614] mmc1: unexpected status 0x2000900 after switch
721 01:56:51.198340 <4>[ 4.556652] mmc1: unexpected status 0x2000900 after switch
722 01:56:51.208089 <6>[ 4.562546] mmc1: new high speed MMC card at address 0001
723 01:56:51.208623 <6>[ 4.569486] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
724 01:56:52.868128 <4>[ 6.224424] mmc1: unexpected status 0x2000980 after switch
725 01:56:52.874110 <4>[ 6.231972] mmc1: unexpected status 0x2000900 after switch
726 01:56:52.880420 <4>[ 6.238141] mmc1: unexpected status 0x2000900 after switch
727 01:56:52.884231 <4>[ 6.244627] mmc1: unexpected status 0x2000900 after switch
728 01:56:53.324980 <6>[ 6.682674] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
729 01:56:53.646871 <5>[ 6.721623] Sending DHCP requests .,
730 01:56:53.658477 <3>[ 7.010173] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
731 01:56:53.659029 <4>[ 7.023342] OK
732 01:56:53.669938 <6>[ 7.025599] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.16
733 01:56:53.670486 <6>[ 7.033800] IP-Config: Complete:
734 01:56:53.681195 <6>[ 7.037341] device=eth0, hwaddr=c8:a0:30:c2:c5:7d, ipaddr=192.168.6.16, mask=255.255.255.0, gw=192.168.6.1
735 01:56:53.686984 <6>[ 7.047857] host=192.168.6.16, domain=, nis-domain=(none)
736 01:56:53.692685 <6>[ 7.054068] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
737 01:56:53.699388 <6>[ 7.054102] nameserver0=10.255.253.1
738 01:56:53.705350 <6>[ 7.066726] clk: Disabling unused clocks
739 01:56:53.710389 <6>[ 7.071329] PM: genpd: Disabling unused power domains
740 01:56:53.728991 <6>[ 7.089008] Freeing unused kernel image (initmem) memory: 2048K
741 01:56:53.736301 <6>[ 7.098582] Run /init as init process
742 01:56:53.762621 Loading, please wait...
743 01:56:53.838119 Starting systemd-udevd version 252.22-1~deb12u1
744 01:56:54.430619 <3>[ 7.788170] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
745 01:56:55.203362 <3>[ 8.561843] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
746 01:56:55.979192 <3>[ 9.336764] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
747 01:56:56.776301 <3>[ 10.134092] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
748 01:56:57.109654 <4>[ 10.465716] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 01:56:57.276962 <4>[ 10.633224] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
750 01:56:57.417583 <6>[ 10.781478] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
751 01:56:57.428584 <6>[ 10.787334] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
752 01:56:57.589574 <3>[ 10.947316] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
753 01:56:57.708568 <6>[ 11.070715] hub 1-0:1.0: USB hub found
754 01:56:57.758894 <6>[ 11.121004] hub 1-0:1.0: 1 port detected
755 01:56:58.348533 <6>[ 11.710322] tda998x 0-0070: found TDA19988
756 01:56:58.364258 <3>[ 11.721868] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
757 01:56:58.552239 <6>[ 11.911836] usb 1-1: new low-speed USB device number 2 using musb-hdrc
758 01:56:58.691551 <3>[ 12.052153] usb 1-1: device descriptor read/64, error -71
759 01:56:58.961570 <3>[ 12.321980] usb 1-1: device descriptor read/64, error -71
760 01:56:59.148732 <3>[ 12.506933] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
761 01:56:59.156504 <3>[ 12.515909] Buffer I/O error on dev mmcblk1, logical block 0, async page read
762 01:56:59.372360 <6>[ 12.731888] usb 1-1: new low-speed USB device number 3 using musb-hdrc
763 01:56:59.511477 <3>[ 12.872000] usb 1-1: device descriptor read/64, error -71
764 01:56:59.761429 <3>[ 13.121948] usb 1-1: device descriptor read/64, error -71
765 01:56:59.979546 <6>[ 13.341023] usb usb1-port1: attempt power cycle
766 01:57:00.162348 <6>[ 13.521951] usb 1-1: new low-speed USB device number 4 using musb-hdrc
767 01:57:00.815878 <6>[ 14.175300] usb 1-1: new low-speed USB device number 5 using musb-hdrc
768 01:57:01.302697 Begin: Loading essential drivers ... done.
769 01:57:01.308241 Begin: Running /scripts/init-premount ... done.
770 01:57:01.313695 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
771 01:57:01.324068 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
772 01:57:01.332740 Device /sys/class/net/eth0 found
773 01:57:01.333233 done.
774 01:57:01.412896 Begin: Waiting up to 180 secs for any network device to become available ... done.
775 01:57:01.547876 IP-Config: eth0 hardware address c8:a0:30:c2:c5:7d mtu 1500 DHCP
776 01:57:01.637230 IP-Config: eth0 guessed broadcast address 192.168.6.255
777 01:57:01.642611 IP-Config: eth0 complete (dhcp from 192.168.6.1):
778 01:57:01.648244 address: 192.168.6.16 broadcast: 192.168.6.255 netmask: 255.255.255.0
779 01:57:01.657103 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
780 01:57:01.662959 rootserver: 192.168.6.1 rootpath:
781 01:57:01.663451 filename :
782 01:57:01.787735 done.
783 01:57:01.806026 Begin: Running /scripts/nfs-bottom ... done.
784 01:57:01.871015 Begin: Running /scripts/init-bottom ... done.
785 01:57:02.355896 <3>[ 15.713460] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
786 01:57:03.115952 <3>[ 16.473520] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
787 01:57:03.611935 <30>[ 16.971460] systemd[1]: System time before build time, advancing clock.
788 01:57:03.831110 <30>[ 17.164520] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
789 01:57:03.890560 <3>[ 17.248468] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
790 01:57:03.899157 <30>[ 17.260689] systemd[1]: Detected architecture arm.
791 01:57:03.911749
792 01:57:03.912245 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
793 01:57:03.912570
794 01:57:03.941915 <30>[ 17.302169] systemd[1]: Hostname set to <debian-bookworm-armhf>.
795 01:57:04.724224 <3>[ 18.082042] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
796 01:57:05.482671 <3>[ 18.840487] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
797 01:57:06.240997 <3>[ 19.599044] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
798 01:57:06.265570 <30>[ 19.624789] systemd[1]: Queued start job for default target graphical.target.
799 01:57:06.282355 <30>[ 19.639305] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
800 01:57:06.289832 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
801 01:57:06.315166 <30>[ 19.674482] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
802 01:57:06.325728 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
803 01:57:06.350357 <30>[ 19.707854] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
804 01:57:06.363769 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
805 01:57:06.385708 <30>[ 19.743483] systemd[1]: Created slice user.slice - User and Session Slice.
806 01:57:06.392256 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
807 01:57:06.421101 <30>[ 19.772984] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
808 01:57:06.426271 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
809 01:57:06.445087 <30>[ 19.802763] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
810 01:57:06.456185 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
811 01:57:06.486047 <30>[ 19.832777] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
812 01:57:06.492437 <30>[ 19.853281] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
813 01:57:06.500975 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
814 01:57:06.524138 <30>[ 19.882088] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
815 01:57:06.532364 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
816 01:57:06.554892 <30>[ 19.912500] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
817 01:57:06.563517 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
818 01:57:06.584644 <30>[ 19.942518] systemd[1]: Reached target paths.target - Path Units.
819 01:57:06.589711 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
820 01:57:06.614304 <30>[ 19.972245] systemd[1]: Reached target remote-fs.target - Remote File Systems.
821 01:57:06.621674 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
822 01:57:06.644266 <30>[ 20.002162] systemd[1]: Reached target slices.target - Slice Units.
823 01:57:06.649712 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
824 01:57:06.674448 <30>[ 20.032425] systemd[1]: Reached target swap.target - Swaps.
825 01:57:06.678516 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
826 01:57:06.704751 <30>[ 20.062447] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
827 01:57:06.713620 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
828 01:57:06.735563 <30>[ 20.093200] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
829 01:57:06.743873 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
830 01:57:06.835146 <30>[ 20.188037] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
831 01:57:06.849104 <30>[ 20.206800] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
832 01:57:06.857568 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
833 01:57:06.886832 <30>[ 20.246037] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
834 01:57:06.899367 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
835 01:57:06.928185 <30>[ 20.284696] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
836 01:57:06.935333 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
837 01:57:07.002096 <3>[ 20.360119] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
838 01:57:07.018329 <30>[ 20.374966] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
839 01:57:07.024021 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
840 01:57:07.045568 <30>[ 20.403369] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
841 01:57:07.054058 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
842 01:57:07.081953 <30>[ 20.433524] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
843 01:57:07.098601 <30>[ 20.450213] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
844 01:57:07.154624 <30>[ 20.513237] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
845 01:57:07.180758 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
846 01:57:07.236207 <30>[ 20.594675] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
847 01:57:07.253480 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
848 01:57:07.315454 <30>[ 20.672890] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
849 01:57:07.326411 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
850 01:57:07.364708 <30>[ 20.722748] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
851 01:57:07.393302 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
852 01:57:07.445914 <30>[ 20.804281] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
853 01:57:07.465402 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
854 01:57:07.494181 <30>[ 20.853227] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
855 01:57:07.520701 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
856 01:57:07.575266 <30>[ 20.932944] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
857 01:57:07.595580 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
858 01:57:07.654041 <30>[ 21.012840] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
859 01:57:07.671725 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
860 01:57:07.761814 <30>[ 21.119641] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
861 01:57:07.775433 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<3>[ 21.128924] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
862 01:57:07.775962 el Module loop...
863 01:57:07.786942 <3>[ 21.143187] Buffer I/O error on dev mmcblk1, logical block 0, async page read
864 01:57:07.793002 <6>[ 21.152394] mmcblk1: unable to read partition table
865 01:57:07.796523 <6>[ 21.158229] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
866 01:57:07.816387 <28>[ 21.166593] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
867 01:57:07.820934 <6>[ 21.182664] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
868 01:57:07.834951 <6>[ 21.193373] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
869 01:57:07.842227 <28>[ 21.200227] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
870 01:57:07.875070 <30>[ 21.233055] systemd[1]: Starting systemd-journald.service - Journal Service...
871 01:57:07.881466 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
872 01:57:07.925569 <30>[ 21.284121] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
873 01:57:07.959441 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
874 01:57:08.026275 <30>[ 21.384968] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
875 01:57:08.069927 Starting [0;1;39msystemd-network-g… units from Kernel command line...
876 01:57:08.120166 <30>[ 21.477397] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
877 01:57:08.184779 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
878 01:57:08.259511 <30>[ 21.617551] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
879 01:57:08.305227 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
880 01:57:08.385123 <30>[ 21.744055] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
881 01:57:08.416336 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
882 01:57:08.434967 <30>[ 21.793637] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
883 01:57:08.475635 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
884 01:57:08.498350 <30>[ 21.855967] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
885 01:57:08.526417 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
886 01:57:08.686660 <30>[ 22.046144] systemd[1]: modprobe@configfs.service: Deactivated successfully.
887 01:57:08.725087 <30>[ 22.083467] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
888 01:57:08.754096 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
889 01:57:08.774751 <30>[ 22.134394] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
890 01:57:08.814227 <30>[ 22.172312] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
891 01:57:08.822639 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
892 01:57:08.835214 <30>[ 22.193364] systemd[1]: Started systemd-journald.service - Journal Service.
893 01:57:08.842069 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
894 01:57:08.885258 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
895 01:57:08.915611 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
896 01:57:08.939181 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
897 01:57:08.977682 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
898 01:57:09.007096 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
899 01:57:09.034389 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
900 01:57:09.057417 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
901 01:57:09.089745 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
902 01:57:09.153649 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
903 01:57:09.200305 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
904 01:57:09.260720 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
905 01:57:09.345477 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
906 01:57:09.427010 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
907 01:57:09.565206 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
908 01:57:09.615501 <46>[ 22.974343] systemd-journald[164]: Received client request to flush runtime journal.
909 01:57:09.661399 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
910 01:57:09.806413 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
911 01:57:10.428687 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
912 01:57:10.505875 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
913 01:57:11.458718 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
914 01:57:11.536709 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
915 01:57:11.574487 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
916 01:57:11.593953 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
917 01:57:11.685386 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
918 01:57:11.712630 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
919 01:57:12.683336 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
920 01:57:12.785305 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
921 01:57:12.870282 <4>[ 26.232283] mmc1: unexpected status 0x2000980 after switch
922 01:57:12.883271 <4>[ 26.244410] mmc1: unexpected status 0x2000900 after switch
923 01:57:12.905360 <4>[ 26.267356] mmc1: unexpected status 0x2000900 after switch
924 01:57:12.932348 <4>[ 26.294027] mmc1: unexpected status 0x2000900 after switch
925 01:57:12.999916 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
926 01:57:13.054632 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
927 01:57:13.097889 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
928 01:57:14.344545 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
929 01:57:15.405651 <5>[ 28.764649] cfg80211: Loading compiled-in X.509 certificates for regulatory database
930 01:57:15.516953 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
931 01:57:16.194524 <3>[ 29.551877] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
932 01:57:16.436166 <5>[ 29.797127] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
933 01:57:16.469848 <5>[ 29.829150] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
934 01:57:16.493344 <4>[ 29.852179] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
935 01:57:16.499193 <6>[ 29.861162] cfg80211: failed to load regulatory.db
936 01:57:16.982487 <3>[ 30.339942] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
937 01:57:17.195446 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
938 01:57:17.476358 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0<46>[ 30.821233] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
939 01:57:17.479940 m - Network Configuration.
940 01:57:17.673943 <46>[ 31.025925] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
941 01:57:17.754437 <3>[ 31.111815] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
942 01:57:18.516212 <3>[ 31.873615] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
943 01:57:19.294352 <3>[ 32.651819] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
944 01:57:19.560995 [[0m[0;31m* [0m] Job dev-ttyS0.device/start running (13s / 1min 30s)
945 01:57:20.071592 M
[K[[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (13s / 1min 30s)
946 01:57:20.086073 <3>[ 33.443663] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
947 01:57:20.496237 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (14s / 1min 30s)
948 01:57:20.850603 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (14s / 1min 30s)
949 01:57:20.860815 <3>[ 34.218470] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
950 01:57:21.257163 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (14s / 1min 30s)
951 01:57:21.634372 <3>[ 34.992024] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
952 01:57:21.659244 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job dev-ttyS0.device/start running (15s / 1min 30s)
953 01:57:22.126499 M
[K[ [0;31m*[0;1;31m*[0m] Job dev-ttyS0.device/start running (15s / 1min 30s)
954 01:57:22.513399 M
[K[ [0;31m*[0m] Job dev-ttyS0.device/start running (16s / 1min 30s)
955 01:57:22.927056 M
[K[ [0;31m*[0;1;31m*[0m] Job dev-ttyS0.device/start running (16s / 1min 30s)
956 01:57:23.364159 M
[K[ [0;31m*[0;1;31m*[0m[0;31m*[0m] Job dev-ttyS0.device/start running (17s / 1min 30s)
957 01:57:23.749988 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (17s / 1min 30s)
958 01:57:24.178162 M
[K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (17s / 1min 30s)
959 01:57:24.520745 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (18s / 1min 30s)
960 01:57:24.890179 <3>[ 38.248093] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
961 01:57:24.914164 M
[K[[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (18s / 1min 30s)
962 01:57:25.158700 M
[K[[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
963 01:57:25.183265 [K[[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
964 01:57:25.212337 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
965 01:57:25.274593 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
966 01:57:25.324031 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
967 01:57:25.386185 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
968 01:57:25.428256 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
969 01:57:25.471677 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
970 01:57:25.496086 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
971 01:57:25.519096 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
972 01:57:25.549237 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
973 01:57:25.589896 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
974 01:57:25.649130 <3>[ 39.007092] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
975 01:57:25.668313 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
976 01:57:25.699115 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
977 01:57:25.732019 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
978 01:57:25.766052 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
979 01:57:25.813960 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
980 01:57:25.835111 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
981 01:57:25.854563 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
982 01:57:25.884556 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
983 01:57:25.910032 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
984 01:57:25.936825 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
985 01:57:26.004087 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
986 01:57:26.046075 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
987 01:57:26.135023 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
988 01:57:26.216828 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
989 01:57:26.274952 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
990 01:57:26.327735 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
991 01:57:26.418944 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - S<3>[ 39.771754] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
992 01:57:26.419604 ound Card.
993 01:57:26.577459 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
994 01:57:26.634955 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
995 01:57:26.842346 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
996 01:57:27.095403 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
997 01:57:27.178028 <3>[ 40.536129] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
998 01:57:27.502068 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
999 01:57:27.947105 <3>[ 41.305082] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1000 01:57:28.716088 <3>[ 42.074115] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1001 01:57:29.485197 <3>[ 42.843193] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1002 01:57:29.777679 [[0m[0;31m* [0m] Job dev-ttyS0.device/start running (23s / 1min 30s)
1003 01:57:30.253508 <3>[ 43.612500] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1004 01:57:30.262537 <3>[ 43.622006] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
1005 01:57:30.747886 M
[K[[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (24s / 1min 30s)
1006 01:57:31.861660 M
[K[[0;31m*[0;1;31m*[0m[0;31m* [0m] Job dev-ttyS0.device/start running (25s / 1min 30s)
1007 01:57:32.263931 M
[K[[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
1008 01:57:33.483704 [K[[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1009 01:57:33.574347 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1010 01:57:33.592059 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1011 01:57:33.627957 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1012 01:57:33.787396 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1013 01:57:33.867451 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1014 01:57:34.145540
1015 01:57:34.148985 Debian GNU/Linux 12 dworm-armhf login: root (automatic login)
1016 01:57:34.149551
1017 01:57:34.507259 <3>[ 47.865006] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1018 01:57:34.518210 Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Sat Nov 9 01:33:17 UTC 2024 armv7l
1019 01:57:34.518751
1020 01:57:34.523928 The programs included with the Debian GNU/Linux system are free software;
1021 01:57:34.529485 the exact distribution terms for each program are described in the
1022 01:57:34.535115 individual files in /usr/share/doc/*/copyright.
1023 01:57:34.535587
1024 01:57:34.541410 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1025 01:57:34.541884 permitted by applicable law.
1026 01:57:35.266265 <3>[ 48.624234] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1027 01:57:36.025304 <3>[ 49.383329] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1028 01:57:36.783915 <3>[ 50.142430] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1029 01:57:37.543555 <3>[ 50.901539] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1030 01:57:38.302600 <3>[ 51.660621] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1031 01:57:39.063103 <3>[ 52.421090] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1032 01:57:39.647616 Unable to match end of the kernel message
1034 01:57:39.649333 Setting prompt string to ['/ #']
1035 01:57:39.649953 end: 2.4.4.1 login-action (duration 00:00:53) [common]
1037 01:57:39.651497 end: 2.4.4 auto-login-action (duration 00:00:54) [common]
1038 01:57:39.652124 start: 2.4.5 expect-shell-connection (timeout 00:02:46) [common]
1039 01:57:39.652624 Setting prompt string to ['/ #']
1040 01:57:39.653094 Forcing a shell prompt, looking for ['/ #']
1042 01:57:39.704173 / #
1043 01:57:39.704924 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1044 01:57:39.705486 Waiting using forced prompt support (timeout 00:02:30)
1045 01:57:39.708850
1046 01:57:39.719088 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1047 01:57:39.719768 start: 2.4.6 export-device-env (timeout 00:02:46) [common]
1048 01:57:39.720351 Sending with 10 millisecond of delay
1050 01:57:44.709463 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/964071/extract-nfsrootfs-un0dug5y'
1051 01:57:44.721903 <3>[ 53.190503] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
1052 01:57:44.722264 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/9640<3>[ 56.299453] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1053 01:57:44.722489 71/extract-nf<3>[ 57.068578] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1054 01:57:44.722707 srootfs-un0d<3>[ 57.837751] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1055 01:57:44.722915 ug5y'
1056 01:57:44.723391 Sending with 10 millisecond of delay
1058 01:57:46.822621 / # export NFS_SERVER_IP='192.168.6.2'
1059 01:57:46.833326 export <3>[ 58.606891] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1060 01:57:46.833655 NFS_SERVER_IP<3>[ 59.375990] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1061 01:57:46.833883 ='192.168.6.2<3>[ 60.145108] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1062 01:57:46.834106 '
1063 01:57:46.834628 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1064 01:57:46.834956 end: 2.4 uboot-commands (duration 00:02:21) [common]
1065 01:57:46.835288 end: 2 uboot-action (duration 00:02:21) [common]
1066 01:57:46.835599 start: 3 lava-test-retry (timeout 00:06:29) [common]
1067 01:57:46.835905 start: 3.1 lava-test-shell (timeout 00:06:29) [common]
1068 01:57:46.836199 Using namespace: common
1070 01:57:46.936974 / # #
1071 01:57:46.937490 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1072 01:57:46.942191 #
1073 01:57:46.948526 Using /lava-964071
1075 01:57:47.049325 / # export SHELL=/bin/bash
1076 01:57:47.054677 export SHELL=/bin/bash
1078 01:57:47.161376 / # . /lava-964071/environment
1079 01:57:47.165677 . /lava-964071/environment
1081 01:57:47.276106 / # /lava-964071/bin/lava-test-runner /lava-964071/0
1082 01:57:47.276630 Test shell timeout: 10s (minimum of the action and connection timeout)
1083 01:57:47.281557 /lava-964071/bin/lava-test-runner /lava-964071/0
1084 01:57:47.547086 <3>[ 60.905867] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1085 01:57:47.764974 + export TESTRUN_ID=0_timesync-off
1086 01:57:47.772866 + TESTRUN_ID=0_timesync-off
1087 01:57:47.773196 + cd /lava-964071/0/tests/0_timesync-off
1088 01:57:47.773424 ++ cat uuid
1089 01:57:47.788937 + UUID=964071_1.6.2.4.1
1090 01:57:47.789284 + set +x
1091 01:57:47.797331 <LAVA_SIGNAL_STARTRUN 0_timesync-off 964071_1.6.2.4.1>
1092 01:57:47.797636 + systemctl stop systemd-timesyncd
1093 01:57:47.798098 Received signal: <STARTRUN> 0_timesync-off 964071_1.6.2.4.1
1094 01:57:47.798343 Starting test lava.0_timesync-off (964071_1.6.2.4.1)
1095 01:57:47.798627 Skipping test definition patterns.
1096 01:57:48.063123 + set +x
1097 01:57:48.063526 <LAVA_SIGNAL_ENDRUN 0_timesync-off 964071_1.6.2.4.1>
1098 01:57:48.064013 Received signal: <ENDRUN> 0_timesync-off 964071_1.6.2.4.1
1099 01:57:48.064533 Ending use of test pattern.
1100 01:57:48.064944 Ending test lava.0_timesync-off (964071_1.6.2.4.1), duration 0.27
1102 01:57:48.298744 + export TESTRUN_ID=1_kselftest-dt
1103 01:57:48.299306 + TESTRUN_ID=1_kselftest-dt
1104 01:57:48.309923 + cd /lava-964071/0/tests/1_kself<3>[ 61.665019] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1105 01:57:48.310387 test-dt
1106 01:57:48.319833 <3>[ 61.679423] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
1107 01:57:48.389371 ++ cat uuid
1108 01:57:48.411380 + UUID=964071_1.6.2.4.5
1109 01:57:48.411744 + set +x
1110 01:57:48.416878 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 964071_1.6.2.4.5>
1111 01:57:48.417226 + cd ./automated/linux/kselftest/
1112 01:57:48.417698 Received signal: <STARTRUN> 1_kselftest-dt 964071_1.6.2.4.5
1113 01:57:48.417963 Starting test lava.1_kselftest-dt (964071_1.6.2.4.5)
1114 01:57:48.418252 Skipping test definition patterns.
1115 01:57:48.446945 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1116 01:57:48.547176 INFO: install_deps skipped
1117 01:57:49.161276 --2024-11-09 01:57:49-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1118 01:57:49.184426 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1119 01:57:49.324829 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1120 01:57:49.466108 HTTP request sent, awaiting response... 200 OK
1121 01:57:49.466528 Length: 4098644 (3.9M) [application/octet-stream]
1122 01:57:49.471412 Saving to: 'kselftest_armhf.tar.gz'
1123 01:57:49.471758
1124 01:57:52.061230
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 180KB/s
kselftest_armhf.tar 4%[ ] 194.76K 345KB/s
kselftest_armhf.tar 9%[> ] 360.70K 433KB/s
kselftest_armhf.tar 21%[===> ] 866.95K 779KB/s
kselftest_armhf.tar 34%[=====> ] 1.35M 997KB/s
kselftest_armhf.tar 48%[========> ] 1.89M 1.14MB/s
kselftest_armhf.tar 60%[===========> ] 2.38M 1.25MB/s
kselftest_armhf.tar 73%[=============> ] 2.88M 1.35MB/s
kselftest_armhf.tar 86%[================> ] 3.37M 1.42MB/s
kselftest_armhf.tar 97%[==================> ] 3.82M 1.48MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 1.51MB/s in 2.6s
1125 01:57:52.061689
1126 01:57:52.822322 2024-11-09 01:57:52 (1.51 MB/s) - 'kselftest_armhf.tar.gz' saved [4098644/4098644]
1127 01:57:52.823013
1128 01:58:05.387050 skiplist:
1129 01:58:05.387737 ========================================
1130 01:58:05.392667 ========================================
1131 01:58:05.489956 dt:test_unprobed_devices.sh
1132 01:58:05.518863 ============== Tests to run ===============
1133 01:58:05.528057 dt:test_unprobed_devices.sh
1134 01:58:05.531959 ===========End Tests to run ===============
1135 01:58:05.542646 shardfile-dt pass
1136 01:58:05.760708 <12>[ 79.125081] kselftest: Running tests in dt
1137 01:58:05.791052 TAP version 13
1138 01:58:05.812883 1..1
1139 01:58:05.866382 # timeout set to 45
1140 01:58:05.866906 # selftests: dt: test_unprobed_devices.sh
1141 01:58:06.723270 # TAP version 13
1142 01:58:31.549993 # 1..257
1143 01:58:31.742459 # ok 1 / # SKIP
1144 01:58:31.761869 # ok 2 /clk_mcasp0
1145 01:58:31.838610 # ok 3 /clk_mcasp0_fixed # SKIP
1146 01:58:31.903915 # ok 4 /cpus/cpu@0 # SKIP
1147 01:58:31.979786 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1148 01:58:31.999976 # ok 6 /fixedregulator0
1149 01:58:32.015934 # ok 7 /leds
1150 01:58:32.041256 # ok 8 /ocp
1151 01:58:32.065142 # ok 9 /ocp/interconnect@44c00000
1152 01:58:32.092214 # ok 10 /ocp/interconnect@44c00000/segment@0
1153 01:58:32.108291 # ok 11 /ocp/interconnect@44c00000/segment@100000
1154 01:58:32.132507 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1155 01:58:32.203056 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1156 01:58:32.225596 # ok 14 /ocp/interconnect@44c00000/segment@200000
1157 01:58:32.252066 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1158 01:58:32.355073 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1159 01:58:32.430586 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1160 01:58:32.502026 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1161 01:58:32.573558 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1162 01:58:32.644694 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1163 01:58:32.715727 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1164 01:58:32.787436 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1165 01:58:32.858457 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1166 01:58:32.935591 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1167 01:58:33.007019 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1168 01:58:33.078084 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1169 01:58:33.150296 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1170 01:58:33.216862 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1171 01:58:33.288313 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1172 01:58:33.359043 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1173 01:58:33.433702 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1174 01:58:33.500937 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1175 01:58:33.576481 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1176 01:58:33.642209 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1177 01:58:33.714112 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1178 01:58:33.788100 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1179 01:58:33.860214 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1180 01:58:33.927244 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1181 01:58:33.999352 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1182 01:58:34.071885 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1183 01:58:34.143490 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1184 01:58:34.216881 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1185 01:58:34.288938 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1186 01:58:34.361031 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1187 01:58:34.432167 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1188 01:58:34.504105 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1189 01:58:34.576683 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1190 01:58:34.647076 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1191 01:58:34.718868 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1192 01:58:34.792123 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1193 01:58:34.866772 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1194 01:58:34.934849 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1195 01:58:35.006351 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1196 01:58:35.078203 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1197 01:58:35.148558 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1198 01:58:35.221003 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1199 01:58:35.290952 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1200 01:58:35.369496 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1201 01:58:35.439942 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1202 01:58:35.514409 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1203 01:58:35.581415 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1204 01:58:35.652889 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1205 01:58:35.724117 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1206 01:58:35.795556 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1207 01:58:35.866279 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1208 01:58:35.939834 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1209 01:58:36.016680 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1210 01:58:36.088870 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1211 01:58:36.159695 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1212 01:58:36.230700 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1213 01:58:36.299154 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1214 01:58:36.371755 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1215 01:58:36.447622 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1216 01:58:36.518041 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1217 01:58:36.589600 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1218 01:58:36.662806 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1219 01:58:36.733068 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1220 01:58:36.803632 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1221 01:58:36.879671 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1222 01:58:36.947029 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1223 01:58:37.021769 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1224 01:58:37.091591 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1225 01:58:37.159535 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1226 01:58:37.237549 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1227 01:58:37.308848 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1228 01:58:37.379601 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1229 01:58:37.448405 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1230 01:58:37.521073 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1231 01:58:37.593658 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1232 01:58:37.671615 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1233 01:58:37.736062 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1234 01:58:37.811376 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1235 01:58:37.881902 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1236 01:58:37.958588 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1237 01:58:37.978616 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1238 01:58:38.004156 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1239 01:58:38.028991 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1240 01:58:38.053337 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1241 01:58:38.076898 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1242 01:58:38.098250 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1243 01:58:38.121585 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1244 01:58:38.142980 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1245 01:58:38.247560 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1246 01:58:38.272265 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1247 01:58:38.296214 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1248 01:58:38.319644 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1249 01:58:38.424873 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1250 01:58:38.499347 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1251 01:58:38.571590 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1252 01:58:38.647659 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1253 01:58:38.719770 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1254 01:58:38.787788 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1255 01:58:38.859794 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1256 01:58:38.936793 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1257 01:58:39.004602 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1258 01:58:39.077224 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1259 01:58:39.148541 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1260 01:58:39.220096 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1261 01:58:39.292888 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1262 01:58:39.363933 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1263 01:58:39.440975 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1264 01:58:39.508632 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1265 01:58:39.534192 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1266 01:58:39.599957 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1267 01:58:39.669365 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1268 01:58:39.741528 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1269 01:58:39.763144 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1270 01:58:39.837930 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1271 01:58:39.859193 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1272 01:58:39.928699 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1273 01:58:39.951314 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1274 01:58:39.975629 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1275 01:58:40.003230 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1276 01:58:40.027929 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1277 01:58:40.053183 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1278 01:58:40.070782 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1279 01:58:40.097115 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1280 01:58:40.170354 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1281 01:58:40.192046 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1282 01:58:40.214986 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1283 01:58:40.289271 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1284 01:58:40.356889 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1285 01:58:40.380409 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1286 01:58:40.479324 # not ok 144 /ocp/interconnect@47c00000
1287 01:58:40.550495 # not ok 145 /ocp/interconnect@47c00000/segment@0
1288 01:58:40.571211 # ok 146 /ocp/interconnect@48000000
1289 01:58:40.594455 # ok 147 /ocp/interconnect@48000000/segment@0
1290 01:58:40.619584 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1291 01:58:40.646602 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1292 01:58:40.668462 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1293 01:58:40.687501 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1294 01:58:40.711218 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1295 01:58:40.735168 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1296 01:58:40.757259 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1297 01:58:40.833161 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1298 01:58:40.906170 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1299 01:58:40.928284 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1300 01:58:40.952766 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1301 01:58:40.971732 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1302 01:58:40.995463 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1303 01:58:41.022739 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1304 01:58:41.046977 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1305 01:58:41.064854 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1306 01:58:41.093579 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1307 01:58:41.116035 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1308 01:58:41.138356 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1309 01:58:41.157563 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1310 01:58:41.182212 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1311 01:58:41.206566 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1312 01:58:41.229269 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1313 01:58:41.251972 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1314 01:58:41.276192 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1315 01:58:41.298349 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1316 01:58:41.323102 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1317 01:58:41.343282 # ok 175 /ocp/interconnect@48000000/segment@100000
1318 01:58:41.373035 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1319 01:58:41.397454 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1320 01:58:41.469465 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1321 01:58:41.539779 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1322 01:58:41.608545 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1323 01:58:41.686537 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1324 01:58:41.756422 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1325 01:58:41.828938 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1326 01:58:41.899559 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1327 01:58:41.970020 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1328 01:58:41.993450 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1329 01:58:42.016991 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1330 01:58:42.037921 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1331 01:58:42.059561 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1332 01:58:42.087081 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1333 01:58:42.109602 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1334 01:58:42.129877 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1335 01:58:42.154643 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1336 01:58:42.179171 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1337 01:58:42.199942 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1338 01:58:42.226937 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1339 01:58:42.249434 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1340 01:58:42.274262 # ok 198 /ocp/interconnect@48000000/segment@200000
1341 01:58:42.296879 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1342 01:58:42.367484 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1343 01:58:42.387704 # ok 201 /ocp/interconnect@48000000/segment@300000
1344 01:58:42.415913 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1345 01:58:42.438025 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1346 01:58:42.464584 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1347 01:58:42.486490 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1348 01:58:42.507466 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1349 01:58:42.533731 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1350 01:58:42.599618 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1351 01:58:42.621497 # ok 209 /ocp/interconnect@4a000000
1352 01:58:42.645336 # ok 210 /ocp/interconnect@4a000000/segment@0
1353 01:58:42.666714 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1354 01:58:42.689745 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1355 01:58:42.718437 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1356 01:58:42.739564 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1357 01:58:42.812575 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1358 01:58:42.913402 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1359 01:58:42.983601 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1360 01:58:43.085915 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1361 01:58:43.154632 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1362 01:58:43.228617 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1363 01:58:43.323491 # not ok 221 /ocp/interconnect@4b140000
1364 01:58:43.393715 # not ok 222 /ocp/interconnect@4b140000/segment@0
1365 01:58:43.464532 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1366 01:58:43.485915 # ok 224 /ocp/target-module@40300000
1367 01:58:43.513662 # ok 225 /ocp/target-module@40300000/sram@0
1368 01:58:43.586612 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1369 01:58:43.656735 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1370 01:58:43.671453 # ok 228 /ocp/target-module@47400000
1371 01:58:43.700262 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1372 01:58:43.718704 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1373 01:58:43.745456 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1374 01:58:43.763156 # ok 232 /ocp/target-module@47400000/usb@1400
1375 01:58:43.790059 # ok 233 /ocp/target-module@47400000/usb@1800
1376 01:58:43.811595 # ok 234 /ocp/target-module@47810000
1377 01:58:43.828963 # ok 235 /ocp/target-module@49000000
1378 01:58:43.854827 # ok 236 /ocp/target-module@49000000/dma@0
1379 01:58:43.873706 # ok 237 /ocp/target-module@49800000
1380 01:58:43.897493 # ok 238 /ocp/target-module@49800000/dma@0
1381 01:58:43.918247 # ok 239 /ocp/target-module@49900000
1382 01:58:43.941230 # ok 240 /ocp/target-module@49900000/dma@0
1383 01:58:43.965159 # ok 241 /ocp/target-module@49a00000
1384 01:58:43.990832 # ok 242 /ocp/target-module@49a00000/dma@0
1385 01:58:44.008342 # ok 243 /ocp/target-module@4c000000
1386 01:58:44.084188 # not ok 244 /ocp/target-module@4c000000/emif@0
1387 01:58:44.100545 # ok 245 /ocp/target-module@50000000
1388 01:58:44.124260 # ok 246 /ocp/target-module@53100000
1389 01:58:44.193947 # not ok 247 /ocp/target-module@53100000/sham@0
1390 01:58:44.220918 # ok 248 /ocp/target-module@53500000
1391 01:58:44.286490 # not ok 249 /ocp/target-module@53500000/aes@0
1392 01:58:44.311571 # ok 250 /ocp/target-module@56000000
1393 01:58:44.415898 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1394 01:58:44.478391 # ok 252 /opp-table # SKIP
1395 01:58:44.552603 # ok 253 /soc # SKIP
1396 01:58:44.569044 # ok 254 /sound
1397 01:58:44.594160 # ok 255 /target-module@4b000000
1398 01:58:44.622149 # ok 256 /target-module@4b000000/target-module@140000
1399 01:58:44.639338 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1400 01:58:44.647393 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1401 01:58:44.654446 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1402 01:58:46.776463 dt_test_unprobed_devices_sh_ skip
1403 01:58:46.782289 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1404 01:58:46.787612 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1405 01:58:46.788220 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1406 01:58:46.796404 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1407 01:58:46.796923 dt_test_unprobed_devices_sh_fixedregulator0 pass
1408 01:58:46.801999 dt_test_unprobed_devices_sh_leds pass
1409 01:58:46.807643 dt_test_unprobed_devices_sh_ocp pass
1410 01:58:46.811183 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1411 01:58:46.816534 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1412 01:58:46.822152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1413 01:58:46.831418 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1414 01:58:46.836912 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1415 01:58:46.848190 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1416 01:58:46.853800 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1417 01:58:46.865016 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1418 01:58:46.870798 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1419 01:58:46.881842 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1420 01:58:46.893036 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1421 01:58:46.904298 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1422 01:58:46.909962 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1423 01:58:46.921123 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1424 01:58:46.932325 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1425 01:58:46.943531 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1426 01:58:46.954737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1427 01:58:46.960469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1428 01:58:46.971495 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1429 01:58:46.982733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1430 01:58:46.993878 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1431 01:58:47.005072 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1432 01:58:47.010800 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1433 01:58:47.021971 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1434 01:58:47.033086 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1435 01:58:47.044285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1436 01:58:47.049929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1437 01:58:47.061005 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1438 01:58:47.072253 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1439 01:58:47.083388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1440 01:58:47.094585 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1441 01:58:47.100279 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1442 01:58:47.111402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1443 01:58:47.122581 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1444 01:58:47.133837 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1445 01:58:47.145013 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1446 01:58:47.156259 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1447 01:58:47.167388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1448 01:58:47.178554 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1449 01:58:47.189779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1450 01:58:47.200942 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1451 01:58:47.212232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1452 01:58:47.223304 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1453 01:58:47.234555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1454 01:58:47.245782 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1455 01:58:47.256926 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1456 01:58:47.268087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1457 01:58:47.279302 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1458 01:58:47.290484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1459 01:58:47.301700 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1460 01:58:47.312852 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1461 01:58:47.324088 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1462 01:58:47.335233 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1463 01:58:47.346439 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1464 01:58:47.357605 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1465 01:58:47.368894 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1466 01:58:47.380064 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1467 01:58:47.385682 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1468 01:58:47.402551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1469 01:58:47.408089 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1470 01:58:47.419268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1471 01:58:47.430347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1472 01:58:47.441576 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1473 01:58:47.452853 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1474 01:58:47.464020 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1475 01:58:47.475160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1476 01:58:47.486376 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1477 01:58:47.497461 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1478 01:58:47.508676 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1479 01:58:47.519889 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1480 01:58:47.531065 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1481 01:58:47.542295 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1482 01:58:47.553469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1483 01:58:47.564659 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1484 01:58:47.576201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1485 01:58:47.581403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1486 01:58:47.592504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1487 01:58:47.603701 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1488 01:58:47.614954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1489 01:58:47.626192 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1490 01:58:47.637404 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1491 01:58:47.648568 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1492 01:58:47.659794 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1493 01:58:47.670964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1494 01:58:47.682137 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1495 01:58:47.693347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1496 01:58:47.704548 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1497 01:58:47.710100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1498 01:58:47.721317 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1499 01:58:47.732506 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1500 01:58:47.738100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1501 01:58:47.749279 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1502 01:58:47.760475 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1503 01:58:47.766080 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1504 01:58:47.777292 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1505 01:58:47.782877 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1506 01:58:47.794075 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1507 01:58:47.805252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1508 01:58:47.816447 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1509 01:58:47.827657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1510 01:58:47.838843 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1511 01:58:47.850063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1512 01:58:47.861228 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1513 01:58:47.872417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1514 01:58:47.883603 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1515 01:58:47.900406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1516 01:58:47.911571 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1517 01:58:47.922829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1518 01:58:47.933972 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1519 01:58:47.945134 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1520 01:58:47.956363 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1521 01:58:47.973145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1522 01:58:47.984341 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1523 01:58:47.995493 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1524 01:58:48.006689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1525 01:58:48.018029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1526 01:58:48.029175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1527 01:58:48.034809 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1528 01:58:48.045895 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1529 01:58:48.051483 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1530 01:58:48.062691 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1531 01:58:48.068293 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1532 01:58:48.079445 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1533 01:58:48.085088 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1534 01:58:48.096230 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1535 01:58:48.101831 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1536 01:58:48.113037 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1537 01:58:48.124248 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1538 01:58:48.129852 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1539 01:58:48.141082 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1540 01:58:48.152268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1541 01:58:48.163466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1542 01:58:48.174643 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1543 01:58:48.185850 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1544 01:58:48.191414 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1545 01:58:48.197021 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1546 01:58:48.202689 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1547 01:58:48.208259 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1548 01:58:48.213862 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1549 01:58:48.219415 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1550 01:58:48.230620 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1551 01:58:48.236274 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1552 01:58:48.247441 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1553 01:58:48.253007 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1554 01:58:48.264221 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1555 01:58:48.269890 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1556 01:58:48.275394 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1557 01:58:48.286602 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1558 01:58:48.292219 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1559 01:58:48.303391 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1560 01:58:48.309004 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1561 01:58:48.320205 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1562 01:58:48.325750 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1563 01:58:48.336951 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1564 01:58:48.342574 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1565 01:58:48.353755 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1566 01:58:48.359369 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1567 01:58:48.370572 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1568 01:58:48.376208 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1569 01:58:48.387395 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1570 01:58:48.393023 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1571 01:58:48.398628 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1572 01:58:48.409903 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1573 01:58:48.415449 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1574 01:58:48.426649 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1575 01:58:48.432285 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1576 01:58:48.443498 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1577 01:58:48.449112 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1578 01:58:48.460276 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1579 01:58:48.465908 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1580 01:58:48.482723 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1581 01:58:48.488364 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1582 01:58:48.499474 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1583 01:58:48.510756 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1584 01:58:48.521905 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1585 01:58:48.533065 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1586 01:58:48.544312 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1587 01:58:48.555441 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1588 01:58:48.561014 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1589 01:58:48.572272 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1590 01:58:48.577837 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1591 01:58:48.588933 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1592 01:58:48.594542 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1593 01:58:48.605866 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1594 01:58:48.611439 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1595 01:58:48.622649 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1596 01:58:48.628247 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1597 01:58:48.639433 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1598 01:58:48.645039 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1599 01:58:48.650576 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1600 01:58:48.661810 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1601 01:58:48.667420 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1602 01:58:48.678598 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1603 01:58:48.684214 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1604 01:58:48.689863 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1605 01:58:48.700970 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1606 01:58:48.706599 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1607 01:58:48.717783 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1608 01:58:48.723377 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1609 01:58:48.734560 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1610 01:58:48.740152 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1611 01:58:48.745730 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1612 01:58:48.751414 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1613 01:58:48.762503 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1614 01:58:48.773702 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1615 01:58:48.779364 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1616 01:58:48.790477 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1617 01:58:48.796414 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1618 01:58:48.807281 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1619 01:58:48.818495 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1620 01:58:48.829702 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1621 01:58:48.841010 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1622 01:58:48.841461 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1623 01:58:48.852202 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1624 01:58:48.857810 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1625 01:58:48.863417 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1626 01:58:48.869030 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1627 01:58:48.874649 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1628 01:58:48.880294 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1629 01:58:48.885885 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1630 01:58:48.891474 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1631 01:58:48.902668 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1632 01:58:48.908288 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1633 01:58:48.913876 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1634 01:58:48.919464 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1635 01:58:48.925084 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1636 01:58:48.930675 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1637 01:58:48.936281 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1638 01:58:48.941968 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1639 01:58:48.947465 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1640 01:58:48.953085 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1641 01:58:48.958707 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1642 01:58:48.964337 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1643 01:58:48.969963 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1644 01:58:48.975508 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1645 01:58:48.981122 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1646 01:58:48.986676 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1647 01:58:48.992311 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1648 01:58:48.997962 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1649 01:58:49.003498 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1650 01:58:49.009133 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1651 01:58:49.014753 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1652 01:58:49.020363 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1653 01:58:49.026014 dt_test_unprobed_devices_sh_opp-table skip
1654 01:58:49.026543 dt_test_unprobed_devices_sh_soc skip
1655 01:58:49.031453 dt_test_unprobed_devices_sh_sound pass
1656 01:58:49.037257 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1657 01:58:49.042930 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1658 01:58:49.048421 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1659 01:58:49.054120 dt_test_unprobed_devices_sh fail
1660 01:58:49.059765 + ../../utils/send-to-lava.sh ./output/result.txt
1661 01:58:49.065246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1662 01:58:49.066225 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1664 01:58:49.069115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1665 01:58:49.069949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1667 01:58:49.145386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1668 01:58:49.146288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1670 01:58:49.230716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1671 01:58:49.231577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1673 01:58:49.320093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1674 01:58:49.320943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1676 01:58:49.413227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1677 01:58:49.414128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1679 01:58:49.496543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1680 01:58:49.497395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1682 01:58:49.586355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1683 01:58:49.586972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1685 01:58:49.671602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1686 01:58:49.672493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1688 01:58:49.764311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1689 01:58:49.765155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1691 01:58:49.849179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1692 01:58:49.850058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1694 01:58:49.939681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1695 01:58:49.940582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1697 01:58:50.026795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1698 01:58:50.027653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1700 01:58:50.111568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1701 01:58:50.112429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1703 01:58:50.195375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1704 01:58:50.196336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1706 01:58:50.287162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1707 01:58:50.288045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1709 01:58:50.376236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1710 01:58:50.377084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1712 01:58:50.465068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1713 01:58:50.465948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1715 01:58:50.556155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1716 01:58:50.556787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1718 01:58:50.646693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1719 01:58:50.647601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1721 01:58:50.737787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1722 01:58:50.738682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1724 01:58:50.826238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1725 01:58:50.827052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1727 01:58:50.910933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1728 01:58:50.911737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1730 01:58:51.002201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1731 01:58:51.003016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1733 01:58:51.086513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1734 01:58:51.087352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1736 01:58:51.172464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1737 01:58:51.173285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1739 01:58:51.256291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1740 01:58:51.257091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1742 01:58:51.339147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1743 01:58:51.339952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1745 01:58:51.423469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1746 01:58:51.424383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1748 01:58:51.507672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1749 01:58:51.508280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1751 01:58:51.597532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1752 01:58:51.598103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1754 01:58:51.682718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1755 01:58:51.683550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1757 01:58:51.772951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1758 01:58:51.773759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1760 01:58:51.858470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1761 01:58:51.859288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1763 01:58:51.948978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1764 01:58:51.949784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1766 01:58:52.036310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1767 01:58:52.037145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1769 01:58:52.125337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1770 01:58:52.126161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1772 01:58:52.211378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1773 01:58:52.212317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1775 01:58:52.297674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1776 01:58:52.298526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1778 01:58:52.382516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1779 01:58:52.383380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1781 01:58:52.467465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1782 01:58:52.468380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1784 01:58:52.557815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1785 01:58:52.558487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1787 01:58:52.644118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1788 01:58:52.645006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1790 01:58:52.735572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1791 01:58:52.736561 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1793 01:58:52.827560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1794 01:58:52.828531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1796 01:58:52.919011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1797 01:58:52.919872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1799 01:58:53.004110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1800 01:58:53.004948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1802 01:58:53.095764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1803 01:58:53.096701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1805 01:58:53.180540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1806 01:58:53.181356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1808 01:58:53.272799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1809 01:58:53.273648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1811 01:58:53.364663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1812 01:58:53.365588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1814 01:58:53.454840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1815 01:58:53.455759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1817 01:58:53.543210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1818 01:58:53.543890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1820 01:58:53.627788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1821 01:58:53.628723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1823 01:58:53.720749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1824 01:58:53.721406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1826 01:58:53.809834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1827 01:58:53.810473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1829 01:58:53.897413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1830 01:58:53.898051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1832 01:58:53.988606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1833 01:58:53.989465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1835 01:58:54.077977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1836 01:58:54.078813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1838 01:58:54.163400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1839 01:58:54.164188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1841 01:58:54.253827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1842 01:58:54.254588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1844 01:58:54.340027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1845 01:58:54.340922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1847 01:58:54.432663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1848 01:58:54.433562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1850 01:58:54.523793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1851 01:58:54.524465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1853 01:58:54.610032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1854 01:58:54.610961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1856 01:58:54.701498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1857 01:58:54.702370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1859 01:58:54.787940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1860 01:58:54.788853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1862 01:58:54.873035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1863 01:58:54.873976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1865 01:58:54.964062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1866 01:58:54.964924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1868 01:58:55.049355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1869 01:58:55.050236 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1871 01:58:55.140065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1872 01:58:55.140938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1874 01:58:55.224832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1875 01:58:55.225686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1877 01:58:55.310791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1878 01:58:55.311646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1880 01:58:55.401791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1881 01:58:55.402694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1883 01:58:55.486852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1884 01:58:55.487750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1886 01:58:55.577881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1887 01:58:55.578498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1889 01:58:55.668520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1890 01:58:55.669375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1892 01:58:55.752533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1893 01:58:55.753381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1895 01:58:55.836447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1896 01:58:55.837295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1898 01:58:55.920984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1899 01:58:55.921579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1901 01:58:56.012876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1902 01:58:56.013527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1904 01:58:56.102970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1905 01:58:56.103622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1907 01:58:56.188090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1908 01:58:56.188741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1910 01:58:56.271645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1911 01:58:56.272299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1913 01:58:56.355704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1914 01:58:56.356653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1916 01:58:56.440594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1917 01:58:56.441495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1919 01:58:56.532054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1920 01:58:56.532714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1922 01:58:56.624912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1923 01:58:56.625840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1925 01:58:56.709552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1926 01:58:56.710423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1928 01:58:56.794917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1929 01:58:56.795786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1931 01:58:56.880783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1932 01:58:56.881664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1934 01:58:56.962108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1935 01:58:56.963018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1937 01:58:57.047790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1938 01:58:57.048668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1940 01:58:57.131868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1941 01:58:57.132737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1943 01:58:57.223884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1944 01:58:57.224785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1946 01:58:57.311656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1947 01:58:57.312539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1949 01:58:57.397321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1950 01:58:57.398209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1952 01:58:57.482656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1953 01:58:57.483570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1955 01:58:57.568802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1956 01:58:57.569436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1958 01:58:57.658467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1959 01:58:57.659343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1961 01:58:57.746467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1962 01:58:57.747117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1964 01:58:57.834902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1965 01:58:57.835558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1967 01:58:57.926559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1968 01:58:57.927487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1970 01:58:58.017388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1971 01:58:58.018283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1973 01:58:58.103129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1974 01:58:58.104032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1976 01:58:58.192999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1977 01:58:58.193819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1979 01:58:58.278029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1980 01:58:58.278937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1982 01:58:58.369178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1983 01:58:58.370023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1985 01:58:58.457895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1986 01:58:58.458795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1988 01:58:58.544065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1989 01:58:58.544725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1991 01:58:58.630612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1992 01:58:58.631558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1994 01:58:58.720847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1995 01:58:58.721745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1997 01:58:58.805589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1998 01:58:58.806434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
2000 01:58:58.896747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
2001 01:58:58.897566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
2003 01:58:58.989229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
2004 01:58:58.990073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
2006 01:58:59.078541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
2007 01:58:59.079414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
2009 01:58:59.163968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
2010 01:58:59.164860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
2012 01:58:59.248744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
2013 01:58:59.249580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
2015 01:58:59.334157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2016 01:58:59.335010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2018 01:58:59.417999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2019 01:58:59.418901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2021 01:58:59.508062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2023 01:58:59.511178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2024 01:58:59.592848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2026 01:58:59.595210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2027 01:58:59.683792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2029 01:58:59.686228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2030 01:58:59.768877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2031 01:58:59.769678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2033 01:58:59.853105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2034 01:58:59.853916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2036 01:58:59.936483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2037 01:58:59.937288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2039 01:59:00.021870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2040 01:59:00.022725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2042 01:59:00.106554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2043 01:59:00.107406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2045 01:59:00.192050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2046 01:59:00.192921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2048 01:59:00.275681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2049 01:59:00.276576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2051 01:59:00.365481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2052 01:59:00.366340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2054 01:59:00.448110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2055 01:59:00.449014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2057 01:59:00.531116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2058 01:59:00.531769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2060 01:59:00.621417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2061 01:59:00.622336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2063 01:59:00.707405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2064 01:59:00.708237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2066 01:59:00.791871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2067 01:59:00.792722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2069 01:59:00.877393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2070 01:59:00.878203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2072 01:59:00.970267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2073 01:59:00.971068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2075 01:59:01.057540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2076 01:59:01.058405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2078 01:59:01.146127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2079 01:59:01.146984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2081 01:59:01.236194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2082 01:59:01.237051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2084 01:59:01.322984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2085 01:59:01.323858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2087 01:59:01.415558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2088 01:59:01.416504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2090 01:59:01.499348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2091 01:59:01.499970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2093 01:59:01.587198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2094 01:59:01.587809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2096 01:59:01.679061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2097 01:59:01.679904 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2099 01:59:01.762999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2100 01:59:01.763836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2102 01:59:01.848883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2103 01:59:01.849722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2105 01:59:01.935856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2106 01:59:01.936744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2108 01:59:02.027039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2109 01:59:02.027951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2111 01:59:02.111195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2112 01:59:02.112053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2114 01:59:02.203595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2115 01:59:02.204484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2117 01:59:02.289090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2118 01:59:02.289931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2120 01:59:02.376590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2121 01:59:02.377447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2123 01:59:02.467207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2124 01:59:02.468117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2126 01:59:02.554886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2127 01:59:02.555533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2129 01:59:02.646523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2130 01:59:02.647438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2132 01:59:02.729776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2133 01:59:02.730595 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2135 01:59:02.814835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2136 01:59:02.815658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2138 01:59:02.902081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2139 01:59:02.902900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2141 01:59:02.986347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2142 01:59:02.987166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2144 01:59:03.069288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2145 01:59:03.070128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2147 01:59:03.154087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2148 01:59:03.154902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2150 01:59:03.236273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2151 01:59:03.237091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2153 01:59:03.319903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2154 01:59:03.320758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2156 01:59:03.402643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2157 01:59:03.403496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2159 01:59:03.492868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2160 01:59:03.493734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2162 01:59:03.576906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2163 01:59:03.577764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2165 01:59:03.667573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2166 01:59:03.668423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2168 01:59:03.756634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2169 01:59:03.757435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2171 01:59:03.840409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2172 01:59:03.841205 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2174 01:59:03.923841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2175 01:59:03.924694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2177 01:59:04.008251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2178 01:59:04.009102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2180 01:59:04.090592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2181 01:59:04.091468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2183 01:59:04.175129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2184 01:59:04.176028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2186 01:59:04.256677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2187 01:59:04.257516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2189 01:59:04.342109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2190 01:59:04.342922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2192 01:59:04.426849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2193 01:59:04.427727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2195 01:59:04.751791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2196 01:59:04.752594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2197 01:59:04.753374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2199 01:59:04.754818 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2201 01:59:04.756324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2202 01:59:04.757074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2204 01:59:04.782585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2205 01:59:04.783390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2207 01:59:04.865812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2208 01:59:04.866626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2210 01:59:04.950378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2211 01:59:04.951184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2213 01:59:05.032789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2214 01:59:05.033624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2216 01:59:05.118191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2217 01:59:05.118996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2219 01:59:05.204289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2220 01:59:05.205092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2222 01:59:05.286788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2223 01:59:05.287587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2225 01:59:05.370608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2226 01:59:05.371417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2228 01:59:05.454936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2229 01:59:05.455813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2231 01:59:05.539081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2232 01:59:05.540020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2234 01:59:05.624021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2235 01:59:05.624877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2237 01:59:05.707316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2238 01:59:05.708167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2240 01:59:05.797583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2241 01:59:05.798425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2243 01:59:05.887581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2244 01:59:05.888459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2246 01:59:05.969498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2247 01:59:05.970354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2249 01:59:06.051762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2250 01:59:06.052649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2252 01:59:06.136888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2253 01:59:06.137740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2255 01:59:06.218299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2256 01:59:06.219129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2258 01:59:06.309203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2259 01:59:06.310045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2261 01:59:06.393046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2262 01:59:06.393892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2264 01:59:06.475267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2265 01:59:06.476188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2267 01:59:06.560130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2268 01:59:06.561046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2270 01:59:06.644605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2271 01:59:06.645462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2273 01:59:06.728436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2274 01:59:06.729278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2276 01:59:06.811481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2277 01:59:06.812371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2279 01:59:06.894585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2280 01:59:06.895421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2282 01:59:06.987917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2283 01:59:06.990055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2285 01:59:07.112246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2286 01:59:07.113224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2288 01:59:07.198164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2289 01:59:07.199012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2291 01:59:07.293444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2292 01:59:07.294388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2294 01:59:07.380880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2295 01:59:07.381837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2297 01:59:07.466989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2298 01:59:07.467960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2300 01:59:07.560244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2301 01:59:07.561185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2303 01:59:07.644248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2304 01:59:07.645120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2306 01:59:07.734853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2307 01:59:07.735683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2309 01:59:07.825026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2310 01:59:07.825895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2312 01:59:07.917448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2313 01:59:07.918292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2315 01:59:08.000227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2316 01:59:08.001058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2318 01:59:08.152753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2319 01:59:08.153616 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2321 01:59:08.247727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2322 01:59:08.248613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2324 01:59:08.332866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2325 01:59:08.333663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2327 01:59:08.417592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2328 01:59:08.418487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2330 01:59:08.508206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2331 01:59:08.509070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2333 01:59:08.592179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2334 01:59:08.593027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2336 01:59:08.683491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2337 01:59:08.684343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2339 01:59:08.769458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2340 01:59:08.770255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2342 01:59:08.857958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2344 01:59:08.860273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2345 01:59:08.947414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2346 01:59:08.948336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2348 01:59:09.033777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2349 01:59:09.034649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2351 01:59:09.125579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2352 01:59:09.126412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2354 01:59:09.215214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2355 01:59:09.216040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2357 01:59:09.299786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2358 01:59:09.300604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2360 01:59:09.389087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2361 01:59:09.389912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2363 01:59:09.473067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2364 01:59:09.473939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2366 01:59:09.562495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2367 01:59:09.563395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2369 01:59:09.648828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2370 01:59:09.649647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2372 01:59:09.738617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2373 01:59:09.739402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2375 01:59:09.823597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2376 01:59:09.824410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2378 01:59:09.908075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2379 01:59:09.908860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2381 01:59:09.992608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2382 01:59:09.993387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2384 01:59:10.077196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2385 01:59:10.078013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2387 01:59:10.162757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2388 01:59:10.163543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2390 01:59:10.249457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2391 01:59:10.250242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2393 01:59:10.332779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2394 01:59:10.333608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2396 01:59:10.416504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2397 01:59:10.417401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2399 01:59:10.501105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2400 01:59:10.501991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2402 01:59:10.588082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2403 01:59:10.588937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2405 01:59:10.672418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2406 01:59:10.673245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2408 01:59:10.757590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2409 01:59:10.758415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2411 01:59:10.842545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2412 01:59:10.843372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2414 01:59:10.932328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2415 01:59:10.933163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2417 01:59:11.016080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2418 01:59:11.016919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2420 01:59:11.107523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2421 01:59:11.108394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2423 01:59:11.200305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2424 01:59:11.201125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2426 01:59:11.291031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2427 01:59:11.291888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2429 01:59:11.378137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2430 01:59:11.378982 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2432 01:59:11.464560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2433 01:59:11.465465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2435 01:59:11.551242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2436 01:59:11.551881 + set +x
2437 01:59:11.552666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2439 01:59:11.558477 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 964071_1.6.2.4.5>
2440 01:59:11.559020 <LAVA_TEST_RUNNER EXIT>
2441 01:59:11.559730 Received signal: <ENDRUN> 1_kselftest-dt 964071_1.6.2.4.5
2442 01:59:11.560272 Ending use of test pattern.
2443 01:59:11.560723 Ending test lava.1_kselftest-dt (964071_1.6.2.4.5), duration 83.14
2445 01:59:11.562422 ok: lava_test_shell seems to have completed
2446 01:59:11.576624 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2447 01:59:11.578728 end: 3.1 lava-test-shell (duration 00:01:25) [common]
2448 01:59:11.579350 end: 3 lava-test-retry (duration 00:01:25) [common]
2449 01:59:11.579998 start: 4 finalize (timeout 00:05:05) [common]
2450 01:59:11.580624 start: 4.1 power-off (timeout 00:00:30) [common]
2451 01:59:11.581748 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-04'
2452 01:59:11.615805 >> OK - accepted request
2453 01:59:11.617914 Returned 0 in 0 seconds
2454 01:59:11.719111 end: 4.1 power-off (duration 00:00:00) [common]
2456 01:59:11.720995 start: 4.2 read-feedback (timeout 00:05:04) [common]
2457 01:59:11.722209 Listened to connection for namespace 'common' for up to 1s
2458 01:59:11.723137 Listened to connection for namespace 'common' for up to 1s
2459 01:59:12.526334 Listened to connection for namespace 'common' for up to 1s
2460 01:59:12.722191 Finalising connection for namespace 'common'
2461 01:59:12.722956 Disconnecting from shell: Finalise
2462 01:59:12.723490 / # <3>[ 14
2463 01:59:12.824598 end: 4.2 read-feedback (duration 00:00:01) [common]
2464 01:59:12.825339 end: 4 finalize (duration 00:00:01) [common]
2465 01:59:12.826041 Cleaning after the job
2466 01:59:12.826662 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964071/tftp-deploy-o1rzsm1j/ramdisk
2467 01:59:12.829493 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964071/tftp-deploy-o1rzsm1j/kernel
2468 01:59:12.836999 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964071/tftp-deploy-o1rzsm1j/dtb
2469 01:59:12.838455 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964071/tftp-deploy-o1rzsm1j/nfsrootfs
2470 01:59:12.876879 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964071/tftp-deploy-o1rzsm1j/modules
2471 01:59:12.882160 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/964071
2472 01:59:15.663741 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/964071
2473 01:59:15.664688 Job finished correctly