Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:59:56.432450 lava-dispatcher, installed at version: 2024.01
2 01:59:56.433750 start: 0 validate
3 01:59:56.434298 Start time: 2024-11-09 01:59:56.434266+00:00 (UTC)
4 01:59:56.434858 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:59:56.435423 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 01:59:56.483787 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:59:56.484443 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-246-gdbbaaaa6179b%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:59:56.518052 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:59:56.518713 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-246-gdbbaaaa6179b%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:59:57.568250 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:59:57.568804 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-246-gdbbaaaa6179b%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 01:59:57.608911 validate duration: 1.17
14 01:59:57.609825 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:59:57.610180 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:59:57.610494 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:59:57.611303 Not decompressing ramdisk as can be used compressed.
18 01:59:57.611884 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 01:59:57.612186 saving as /var/lib/lava/dispatcher/tmp/964231/tftp-deploy-4hkk71vb/ramdisk/rootfs.cpio.gz
20 01:59:57.612468 total size: 8181887 (7 MB)
21 01:59:57.648415 progress 0 % (0 MB)
22 01:59:57.654651 progress 5 % (0 MB)
23 01:59:57.660212 progress 10 % (0 MB)
24 01:59:57.665979 progress 15 % (1 MB)
25 01:59:57.671360 progress 20 % (1 MB)
26 01:59:57.678540 progress 25 % (1 MB)
27 01:59:57.684933 progress 30 % (2 MB)
28 01:59:57.690624 progress 35 % (2 MB)
29 01:59:57.695858 progress 40 % (3 MB)
30 01:59:57.701535 progress 45 % (3 MB)
31 01:59:57.706689 progress 50 % (3 MB)
32 01:59:57.712249 progress 55 % (4 MB)
33 01:59:57.717447 progress 60 % (4 MB)
34 01:59:57.722974 progress 65 % (5 MB)
35 01:59:57.728819 progress 70 % (5 MB)
36 01:59:57.734468 progress 75 % (5 MB)
37 01:59:57.739623 progress 80 % (6 MB)
38 01:59:57.745069 progress 85 % (6 MB)
39 01:59:57.749955 progress 90 % (7 MB)
40 01:59:57.755102 progress 95 % (7 MB)
41 01:59:57.759910 progress 100 % (7 MB)
42 01:59:57.760607 7 MB downloaded in 0.15 s (52.68 MB/s)
43 01:59:57.761187 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:59:57.762144 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:59:57.762474 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:59:57.762771 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:59:57.763302 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm64/defconfig/gcc-12/kernel/Image
49 01:59:57.763572 saving as /var/lib/lava/dispatcher/tmp/964231/tftp-deploy-4hkk71vb/kernel/Image
50 01:59:57.763799 total size: 45713920 (43 MB)
51 01:59:57.764060 No compression specified
52 01:59:57.805314 progress 0 % (0 MB)
53 01:59:57.834531 progress 5 % (2 MB)
54 01:59:57.863235 progress 10 % (4 MB)
55 01:59:57.889738 progress 15 % (6 MB)
56 01:59:57.917124 progress 20 % (8 MB)
57 01:59:57.944667 progress 25 % (10 MB)
58 01:59:57.972681 progress 30 % (13 MB)
59 01:59:58.001016 progress 35 % (15 MB)
60 01:59:58.029070 progress 40 % (17 MB)
61 01:59:58.056420 progress 45 % (19 MB)
62 01:59:58.083959 progress 50 % (21 MB)
63 01:59:58.111757 progress 55 % (24 MB)
64 01:59:58.139476 progress 60 % (26 MB)
65 01:59:58.167117 progress 65 % (28 MB)
66 01:59:58.194582 progress 70 % (30 MB)
67 01:59:58.221824 progress 75 % (32 MB)
68 01:59:58.249577 progress 80 % (34 MB)
69 01:59:58.276944 progress 85 % (37 MB)
70 01:59:58.304482 progress 90 % (39 MB)
71 01:59:58.332020 progress 95 % (41 MB)
72 01:59:58.358716 progress 100 % (43 MB)
73 01:59:58.359285 43 MB downloaded in 0.60 s (73.21 MB/s)
74 01:59:58.359805 end: 1.2.1 http-download (duration 00:00:01) [common]
76 01:59:58.360699 end: 1.2 download-retry (duration 00:00:01) [common]
77 01:59:58.360998 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:59:58.361339 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:59:58.361856 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 01:59:58.362159 saving as /var/lib/lava/dispatcher/tmp/964231/tftp-deploy-4hkk71vb/dtb/meson-g12b-a311d-libretech-cc.dtb
81 01:59:58.362374 total size: 54703 (0 MB)
82 01:59:58.362588 No compression specified
83 01:59:58.398385 progress 59 % (0 MB)
84 01:59:58.399242 progress 100 % (0 MB)
85 01:59:58.399818 0 MB downloaded in 0.04 s (1.39 MB/s)
86 01:59:58.400362 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:59:58.401202 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:59:58.401475 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:59:58.401751 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:59:58.402232 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm64/defconfig/gcc-12/modules.tar.xz
92 01:59:58.402511 saving as /var/lib/lava/dispatcher/tmp/964231/tftp-deploy-4hkk71vb/modules/modules.tar
93 01:59:58.402724 total size: 11610740 (11 MB)
94 01:59:58.402938 Using unxz to decompress xz
95 01:59:58.437614 progress 0 % (0 MB)
96 01:59:58.506352 progress 5 % (0 MB)
97 01:59:58.582141 progress 10 % (1 MB)
98 01:59:58.679879 progress 15 % (1 MB)
99 01:59:58.773661 progress 20 % (2 MB)
100 01:59:58.854956 progress 25 % (2 MB)
101 01:59:58.932912 progress 30 % (3 MB)
102 01:59:59.012784 progress 35 % (3 MB)
103 01:59:59.086212 progress 40 % (4 MB)
104 01:59:59.163372 progress 45 % (5 MB)
105 01:59:59.248604 progress 50 % (5 MB)
106 01:59:59.327377 progress 55 % (6 MB)
107 01:59:59.413921 progress 60 % (6 MB)
108 01:59:59.495339 progress 65 % (7 MB)
109 01:59:59.578219 progress 70 % (7 MB)
110 01:59:59.656564 progress 75 % (8 MB)
111 01:59:59.741288 progress 80 % (8 MB)
112 01:59:59.822498 progress 85 % (9 MB)
113 01:59:59.902753 progress 90 % (9 MB)
114 01:59:59.981556 progress 95 % (10 MB)
115 02:00:00.059525 progress 100 % (11 MB)
116 02:00:00.071173 11 MB downloaded in 1.67 s (6.64 MB/s)
117 02:00:00.071831 end: 1.4.1 http-download (duration 00:00:02) [common]
119 02:00:00.073332 end: 1.4 download-retry (duration 00:00:02) [common]
120 02:00:00.073857 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 02:00:00.074376 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 02:00:00.074864 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 02:00:00.075362 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 02:00:00.076511 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv
125 02:00:00.077382 makedir: /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin
126 02:00:00.078019 makedir: /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/tests
127 02:00:00.078635 makedir: /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/results
128 02:00:00.079246 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-add-keys
129 02:00:00.080341 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-add-sources
130 02:00:00.081317 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-background-process-start
131 02:00:00.082276 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-background-process-stop
132 02:00:00.083269 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-common-functions
133 02:00:00.084289 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-echo-ipv4
134 02:00:00.085276 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-install-packages
135 02:00:00.086189 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-installed-packages
136 02:00:00.087081 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-os-build
137 02:00:00.088074 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-probe-channel
138 02:00:00.089017 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-probe-ip
139 02:00:00.089928 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-target-ip
140 02:00:00.090833 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-target-mac
141 02:00:00.091723 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-target-storage
142 02:00:00.092715 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-test-case
143 02:00:00.093639 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-test-event
144 02:00:00.094542 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-test-feedback
145 02:00:00.095432 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-test-raise
146 02:00:00.096392 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-test-reference
147 02:00:00.097322 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-test-runner
148 02:00:00.098230 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-test-set
149 02:00:00.099123 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-test-shell
150 02:00:00.100060 Updating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-install-packages (oe)
151 02:00:00.101052 Updating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/bin/lava-installed-packages (oe)
152 02:00:00.101889 Creating /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/environment
153 02:00:00.102618 LAVA metadata
154 02:00:00.103100 - LAVA_JOB_ID=964231
155 02:00:00.103528 - LAVA_DISPATCHER_IP=192.168.6.2
156 02:00:00.104299 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 02:00:00.106173 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 02:00:00.106788 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 02:00:00.107196 skipped lava-vland-overlay
160 02:00:00.107677 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 02:00:00.108221 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 02:00:00.108653 skipped lava-multinode-overlay
163 02:00:00.109131 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 02:00:00.109627 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 02:00:00.110108 Loading test definitions
166 02:00:00.110654 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 02:00:00.111094 Using /lava-964231 at stage 0
168 02:00:00.113015 uuid=964231_1.5.2.4.1 testdef=None
169 02:00:00.113376 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 02:00:00.113651 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 02:00:00.115528 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 02:00:00.116386 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 02:00:00.118747 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 02:00:00.119598 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 02:00:00.121928 runner path: /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/0/tests/0_dmesg test_uuid 964231_1.5.2.4.1
178 02:00:00.122555 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 02:00:00.123338 Creating lava-test-runner.conf files
181 02:00:00.123541 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/964231/lava-overlay-0c40f8rv/lava-964231/0 for stage 0
182 02:00:00.123899 - 0_dmesg
183 02:00:00.124310 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 02:00:00.124602 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 02:00:00.150754 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 02:00:00.151250 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 02:00:00.151568 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 02:00:00.151900 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 02:00:00.152264 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 02:00:01.078925 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 02:00:01.079401 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 02:00:01.079650 extracting modules file /var/lib/lava/dispatcher/tmp/964231/tftp-deploy-4hkk71vb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964231/extract-overlay-ramdisk-rr2lzuxt/ramdisk
193 02:00:02.458709 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 02:00:02.459208 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 02:00:02.459491 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964231/compress-overlay-apf5e68l/overlay-1.5.2.5.tar.gz to ramdisk
196 02:00:02.459707 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964231/compress-overlay-apf5e68l/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/964231/extract-overlay-ramdisk-rr2lzuxt/ramdisk
197 02:00:02.491305 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 02:00:02.491770 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 02:00:02.492106 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 02:00:02.492350 Converting downloaded kernel to a uImage
201 02:00:02.492669 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/964231/tftp-deploy-4hkk71vb/kernel/Image /var/lib/lava/dispatcher/tmp/964231/tftp-deploy-4hkk71vb/kernel/uImage
202 02:00:02.998839 output: Image Name:
203 02:00:02.999357 output: Created: Sat Nov 9 02:00:02 2024
204 02:00:02.999640 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 02:00:02.999902 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 02:00:03.000225 output: Load Address: 01080000
207 02:00:03.000485 output: Entry Point: 01080000
208 02:00:03.000734 output:
209 02:00:03.001152 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 02:00:03.001511 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 02:00:03.001865 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 02:00:03.002199 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 02:00:03.002532 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 02:00:03.002862 Building ramdisk /var/lib/lava/dispatcher/tmp/964231/extract-overlay-ramdisk-rr2lzuxt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/964231/extract-overlay-ramdisk-rr2lzuxt/ramdisk
215 02:00:05.773363 >> 181575 blocks
216 02:00:14.188316 Adding RAMdisk u-boot header.
217 02:00:14.189180 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/964231/extract-overlay-ramdisk-rr2lzuxt/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/964231/extract-overlay-ramdisk-rr2lzuxt/ramdisk.cpio.gz.uboot
218 02:00:14.453243 output: Image Name:
219 02:00:14.453673 output: Created: Sat Nov 9 02:00:14 2024
220 02:00:14.454132 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 02:00:14.454589 output: Data Size: 26054451 Bytes = 25443.80 KiB = 24.85 MiB
222 02:00:14.455033 output: Load Address: 00000000
223 02:00:14.455477 output: Entry Point: 00000000
224 02:00:14.455915 output:
225 02:00:14.457094 rename /var/lib/lava/dispatcher/tmp/964231/extract-overlay-ramdisk-rr2lzuxt/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/964231/tftp-deploy-4hkk71vb/ramdisk/ramdisk.cpio.gz.uboot
226 02:00:14.457877 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 02:00:14.458479 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 02:00:14.459070 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 02:00:14.459585 No LXC device requested
230 02:00:14.460188 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 02:00:14.460770 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 02:00:14.461324 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 02:00:14.461782 Checking files for TFTP limit of 4294967296 bytes.
234 02:00:14.464749 end: 1 tftp-deploy (duration 00:00:17) [common]
235 02:00:14.465387 start: 2 uboot-action (timeout 00:05:00) [common]
236 02:00:14.465975 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 02:00:14.466533 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 02:00:14.467114 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 02:00:14.467706 Using kernel file from prepare-kernel: 964231/tftp-deploy-4hkk71vb/kernel/uImage
240 02:00:14.468419 substitutions:
241 02:00:14.468878 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 02:00:14.469328 - {DTB_ADDR}: 0x01070000
243 02:00:14.469772 - {DTB}: 964231/tftp-deploy-4hkk71vb/dtb/meson-g12b-a311d-libretech-cc.dtb
244 02:00:14.470219 - {INITRD}: 964231/tftp-deploy-4hkk71vb/ramdisk/ramdisk.cpio.gz.uboot
245 02:00:14.470660 - {KERNEL_ADDR}: 0x01080000
246 02:00:14.471098 - {KERNEL}: 964231/tftp-deploy-4hkk71vb/kernel/uImage
247 02:00:14.471538 - {LAVA_MAC}: None
248 02:00:14.472043 - {PRESEED_CONFIG}: None
249 02:00:14.472496 - {PRESEED_LOCAL}: None
250 02:00:14.472931 - {RAMDISK_ADDR}: 0x08000000
251 02:00:14.473363 - {RAMDISK}: 964231/tftp-deploy-4hkk71vb/ramdisk/ramdisk.cpio.gz.uboot
252 02:00:14.473801 - {ROOT_PART}: None
253 02:00:14.474232 - {ROOT}: None
254 02:00:14.474665 - {SERVER_IP}: 192.168.6.2
255 02:00:14.475101 - {TEE_ADDR}: 0x83000000
256 02:00:14.475533 - {TEE}: None
257 02:00:14.475965 Parsed boot commands:
258 02:00:14.476437 - setenv autoload no
259 02:00:14.476874 - setenv initrd_high 0xffffffff
260 02:00:14.477304 - setenv fdt_high 0xffffffff
261 02:00:14.477732 - dhcp
262 02:00:14.478160 - setenv serverip 192.168.6.2
263 02:00:14.478589 - tftpboot 0x01080000 964231/tftp-deploy-4hkk71vb/kernel/uImage
264 02:00:14.479017 - tftpboot 0x08000000 964231/tftp-deploy-4hkk71vb/ramdisk/ramdisk.cpio.gz.uboot
265 02:00:14.479447 - tftpboot 0x01070000 964231/tftp-deploy-4hkk71vb/dtb/meson-g12b-a311d-libretech-cc.dtb
266 02:00:14.479876 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 02:00:14.480348 - bootm 0x01080000 0x08000000 0x01070000
268 02:00:14.480914 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 02:00:14.482558 start: 2.3 connect-device (timeout 00:05:00) [common]
271 02:00:14.483057 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 02:00:14.499649 Setting prompt string to ['lava-test: # ']
273 02:00:14.500686 end: 2.3 connect-device (duration 00:00:00) [common]
274 02:00:14.501068 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 02:00:14.501395 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 02:00:14.501690 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 02:00:14.502358 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 02:00:14.540244 >> OK - accepted request
279 02:00:14.541960 Returned 0 in 0 seconds
280 02:00:14.643088 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 02:00:14.645035 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 02:00:14.645689 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 02:00:14.646272 Setting prompt string to ['Hit any key to stop autoboot']
285 02:00:14.646786 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 02:00:14.648548 Trying 192.168.56.21...
287 02:00:14.649082 Connected to conserv1.
288 02:00:14.649567 Escape character is '^]'.
289 02:00:14.650033
290 02:00:14.650513 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 02:00:14.650997
292 02:00:25.825885 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 02:00:25.826347 bl2_stage_init 0x01
294 02:00:25.826618 bl2_stage_init 0x81
295 02:00:25.831334 hw id: 0x0000 - pwm id 0x01
296 02:00:25.831739 bl2_stage_init 0xc1
297 02:00:25.832050 bl2_stage_init 0x02
298 02:00:25.832328
299 02:00:25.836871 L0:00000000
300 02:00:25.837252 L1:20000703
301 02:00:25.837523 L2:00008067
302 02:00:25.837776 L3:14000000
303 02:00:25.842453 B2:00402000
304 02:00:25.842826 B1:e0f83180
305 02:00:25.843089
306 02:00:25.843342 TE: 58167
307 02:00:25.843592
308 02:00:25.848098 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 02:00:25.848614
310 02:00:25.849014 Board ID = 1
311 02:00:25.853659 Set A53 clk to 24M
312 02:00:25.854148 Set A73 clk to 24M
313 02:00:25.854556 Set clk81 to 24M
314 02:00:25.859246 A53 clk: 1200 MHz
315 02:00:25.859686 A73 clk: 1200 MHz
316 02:00:25.860114 CLK81: 166.6M
317 02:00:25.860514 smccc: 00012abd
318 02:00:25.864863 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 02:00:25.870454 board id: 1
320 02:00:25.876314 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 02:00:25.887021 fw parse done
322 02:00:25.892968 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 02:00:25.935593 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 02:00:25.946520 PIEI prepare done
325 02:00:25.946990 fastboot data load
326 02:00:25.947390 fastboot data verify
327 02:00:25.952205 verify result: 266
328 02:00:25.957868 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 02:00:25.958305 LPDDR4 probe
330 02:00:25.958699 ddr clk to 1584MHz
331 02:00:25.965789 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 02:00:26.003074
333 02:00:26.003527 dmc_version 0001
334 02:00:26.009674 Check phy result
335 02:00:26.015582 INFO : End of CA training
336 02:00:26.016043 INFO : End of initialization
337 02:00:26.021155 INFO : Training has run successfully!
338 02:00:26.021594 Check phy result
339 02:00:26.026719 INFO : End of initialization
340 02:00:26.027164 INFO : End of read enable training
341 02:00:26.032323 INFO : End of fine write leveling
342 02:00:26.037918 INFO : End of Write leveling coarse delay
343 02:00:26.038355 INFO : Training has run successfully!
344 02:00:26.038752 Check phy result
345 02:00:26.043525 INFO : End of initialization
346 02:00:26.043968 INFO : End of read dq deskew training
347 02:00:26.049121 INFO : End of MPR read delay center optimization
348 02:00:26.054716 INFO : End of write delay center optimization
349 02:00:26.060333 INFO : End of read delay center optimization
350 02:00:26.060763 INFO : End of max read latency training
351 02:00:26.065966 INFO : Training has run successfully!
352 02:00:26.066392 1D training succeed
353 02:00:26.075152 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 02:00:26.122060 Check phy result
355 02:00:26.122537 INFO : End of initialization
356 02:00:26.144519 INFO : End of 2D read delay Voltage center optimization
357 02:00:26.164697 INFO : End of 2D read delay Voltage center optimization
358 02:00:26.216749 INFO : End of 2D write delay Voltage center optimization
359 02:00:26.266085 INFO : End of 2D write delay Voltage center optimization
360 02:00:26.271672 INFO : Training has run successfully!
361 02:00:26.272193
362 02:00:26.272604 channel==0
363 02:00:26.277365 RxClkDly_Margin_A0==78 ps 8
364 02:00:26.277794 TxDqDly_Margin_A0==98 ps 10
365 02:00:26.282900 RxClkDly_Margin_A1==88 ps 9
366 02:00:26.283340 TxDqDly_Margin_A1==98 ps 10
367 02:00:26.283741 TrainedVREFDQ_A0==74
368 02:00:26.288468 TrainedVREFDQ_A1==74
369 02:00:26.288906 VrefDac_Margin_A0==25
370 02:00:26.289298 DeviceVref_Margin_A0==40
371 02:00:26.294065 VrefDac_Margin_A1==25
372 02:00:26.294502 DeviceVref_Margin_A1==40
373 02:00:26.294902
374 02:00:26.295293
375 02:00:26.299670 channel==1
376 02:00:26.300133 RxClkDly_Margin_A0==88 ps 9
377 02:00:26.300534 TxDqDly_Margin_A0==98 ps 10
378 02:00:26.305262 RxClkDly_Margin_A1==98 ps 10
379 02:00:26.305706 TxDqDly_Margin_A1==88 ps 9
380 02:00:26.310863 TrainedVREFDQ_A0==77
381 02:00:26.311295 TrainedVREFDQ_A1==77
382 02:00:26.311692 VrefDac_Margin_A0==22
383 02:00:26.316483 DeviceVref_Margin_A0==37
384 02:00:26.316914 VrefDac_Margin_A1==23
385 02:00:26.322047 DeviceVref_Margin_A1==37
386 02:00:26.322476
387 02:00:26.322878 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 02:00:26.323273
389 02:00:26.355640 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 02:00:26.356201 2D training succeed
391 02:00:26.361297 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 02:00:26.366878 auto size-- 65535DDR cs0 size: 2048MB
393 02:00:26.367317 DDR cs1 size: 2048MB
394 02:00:26.372440 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 02:00:26.372874 cs0 DataBus test pass
396 02:00:26.378043 cs1 DataBus test pass
397 02:00:26.378470 cs0 AddrBus test pass
398 02:00:26.378859 cs1 AddrBus test pass
399 02:00:26.379245
400 02:00:26.383656 100bdlr_step_size ps== 420
401 02:00:26.384134 result report
402 02:00:26.389271 boot times 0Enable ddr reg access
403 02:00:26.394594 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 02:00:26.407229 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 02:00:26.981851 0.0;M3 CHK:0;cm4_sp_mode 0
406 02:00:26.982609 MVN_1=0x00000000
407 02:00:26.987325 MVN_2=0x00000000
408 02:00:26.993088 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 02:00:26.993458 OPS=0x10
410 02:00:26.993793 ring efuse init
411 02:00:26.994059 chipver efuse init
412 02:00:27.001246 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 02:00:27.001701 [0.018961 Inits done]
414 02:00:27.008655 secure task start!
415 02:00:27.009061 high task start!
416 02:00:27.009318 low task start!
417 02:00:27.009569 run into bl31
418 02:00:27.015467 NOTICE: BL31: v1.3(release):4fc40b1
419 02:00:27.022939 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 02:00:27.023437 NOTICE: BL31: G12A normal boot!
421 02:00:27.048818 NOTICE: BL31: BL33 decompress pass
422 02:00:27.053395 ERROR: Error initializing runtime service opteed_fast
423 02:00:28.287455
424 02:00:28.288303
425 02:00:28.295306 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 02:00:28.296141
427 02:00:28.296737 Model: Libre Computer AML-A311D-CC Alta
428 02:00:28.504335 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 02:00:28.527574 DRAM: 2 GiB (effective 3.8 GiB)
430 02:00:28.670585 Core: 408 devices, 31 uclasses, devicetree: separate
431 02:00:28.675791 WDT: Not starting watchdog@f0d0
432 02:00:28.708898 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 02:00:28.721185 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 02:00:28.725318 ** Bad device specification mmc 0 **
435 02:00:28.736671 Card did not respond to voltage select! : -110
436 02:00:28.743558 ** Bad device specification mmc 0 **
437 02:00:28.744003 Couldn't find partition mmc 0
438 02:00:28.752576 Card did not respond to voltage select! : -110
439 02:00:28.757919 ** Bad device specification mmc 0 **
440 02:00:28.758267 Couldn't find partition mmc 0
441 02:00:28.762581 Error: could not access storage.
442 02:00:30.027456 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 02:00:30.028621 bl2_stage_init 0x81
444 02:00:30.031894 hw id: 0x0000 - pwm id 0x01
445 02:00:30.032443 bl2_stage_init 0xc1
446 02:00:30.033361 bl2_stage_init 0x02
447 02:00:30.033780
448 02:00:30.037480 L0:00000000
449 02:00:30.038515 L1:20000703
450 02:00:30.038937 L2:00008067
451 02:00:30.039340 L3:14000000
452 02:00:30.039737 B2:00402000
453 02:00:30.044167 B1:e0f83180
454 02:00:30.044679
455 02:00:30.045089 TE: 58150
456 02:00:30.045492
457 02:00:30.051431 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 02:00:30.051791
459 02:00:30.052059 Board ID = 1
460 02:00:30.052463 Set A53 clk to 24M
461 02:00:30.052877 Set A73 clk to 24M
462 02:00:30.057035 Set clk81 to 24M
463 02:00:30.057573 A53 clk: 1200 MHz
464 02:00:30.057982 A73 clk: 1200 MHz
465 02:00:30.060523 CLK81: 166.6M
466 02:00:30.060836 smccc: 00012aac
467 02:00:30.065986 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 02:00:30.071480 board id: 1
469 02:00:30.076322 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 02:00:30.087956 fw parse done
471 02:00:30.092782 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 02:00:30.136008 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 02:00:30.147220 PIEI prepare done
474 02:00:30.147869 fastboot data load
475 02:00:30.148434 fastboot data verify
476 02:00:30.152876 verify result: 266
477 02:00:30.158375 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 02:00:30.158758 LPDDR4 probe
479 02:00:30.159252 ddr clk to 1584MHz
480 02:00:30.166380 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 02:00:30.206294
482 02:00:30.207260 dmc_version 0001
483 02:00:30.209931 Check phy result
484 02:00:30.216209 INFO : End of CA training
485 02:00:30.216618 INFO : End of initialization
486 02:00:30.221787 INFO : Training has run successfully!
487 02:00:30.222252 Check phy result
488 02:00:30.227278 INFO : End of initialization
489 02:00:30.227780 INFO : End of read enable training
490 02:00:30.232934 INFO : End of fine write leveling
491 02:00:30.238542 INFO : End of Write leveling coarse delay
492 02:00:30.238970 INFO : Training has run successfully!
493 02:00:30.239267 Check phy result
494 02:00:30.244364 INFO : End of initialization
495 02:00:30.244765 INFO : End of read dq deskew training
496 02:00:30.249632 INFO : End of MPR read delay center optimization
497 02:00:30.255301 INFO : End of write delay center optimization
498 02:00:30.261004 INFO : End of read delay center optimization
499 02:00:30.261396 INFO : End of max read latency training
500 02:00:30.268288 INFO : Training has run successfully!
501 02:00:30.268709 1D training succeed
502 02:00:30.275131 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 02:00:30.322865 Check phy result
504 02:00:30.323313 INFO : End of initialization
505 02:00:30.344020 INFO : End of 2D read delay Voltage center optimization
506 02:00:30.365160 INFO : End of 2D read delay Voltage center optimization
507 02:00:30.416118 INFO : End of 2D write delay Voltage center optimization
508 02:00:30.466234 INFO : End of 2D write delay Voltage center optimization
509 02:00:30.471673 INFO : Training has run successfully!
510 02:00:30.472122
511 02:00:30.472395 channel==0
512 02:00:30.477234 RxClkDly_Margin_A0==88 ps 9
513 02:00:30.477639 TxDqDly_Margin_A0==98 ps 10
514 02:00:30.482917 RxClkDly_Margin_A1==88 ps 9
515 02:00:30.483292 TxDqDly_Margin_A1==98 ps 10
516 02:00:30.483555 TrainedVREFDQ_A0==74
517 02:00:30.488453 TrainedVREFDQ_A1==74
518 02:00:30.488854 VrefDac_Margin_A0==25
519 02:00:30.489255 DeviceVref_Margin_A0==40
520 02:00:30.494048 VrefDac_Margin_A1==25
521 02:00:30.494463 DeviceVref_Margin_A1==40
522 02:00:30.494722
523 02:00:30.495003
524 02:00:30.499656 channel==1
525 02:00:30.500056 RxClkDly_Margin_A0==98 ps 10
526 02:00:30.500321 TxDqDly_Margin_A0==98 ps 10
527 02:00:30.505406 RxClkDly_Margin_A1==98 ps 10
528 02:00:30.505825 TxDqDly_Margin_A1==88 ps 9
529 02:00:30.510852 TrainedVREFDQ_A0==77
530 02:00:30.511270 TrainedVREFDQ_A1==77
531 02:00:30.511532 VrefDac_Margin_A0==22
532 02:00:30.516488 DeviceVref_Margin_A0==37
533 02:00:30.516891 VrefDac_Margin_A1==24
534 02:00:30.522082 DeviceVref_Margin_A1==37
535 02:00:30.522495
536 02:00:30.522817 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 02:00:30.527693
538 02:00:30.556711 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
539 02:00:30.557400 2D training succeed
540 02:00:30.561252 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 02:00:30.566893 auto size-- 65535DDR cs0 size: 2048MB
542 02:00:30.567450 DDR cs1 size: 2048MB
543 02:00:30.572472 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 02:00:30.572979 cs0 DataBus test pass
545 02:00:30.578194 cs1 DataBus test pass
546 02:00:30.578671 cs0 AddrBus test pass
547 02:00:30.579075 cs1 AddrBus test pass
548 02:00:30.579472
549 02:00:30.583638 100bdlr_step_size ps== 420
550 02:00:30.584213 result report
551 02:00:30.589229 boot times 0Enable ddr reg access
552 02:00:30.594301 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 02:00:30.607928 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 02:00:31.180214 0.0;M3 CHK:0;cm4_sp_mode 0
555 02:00:31.180644 MVN_1=0x00000000
556 02:00:31.185592 MVN_2=0x00000000
557 02:00:31.191363 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 02:00:31.191903 OPS=0x10
559 02:00:31.192418 ring efuse init
560 02:00:31.192849 chipver efuse init
561 02:00:31.197009 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 02:00:31.202532 [0.018961 Inits done]
563 02:00:31.202876 secure task start!
564 02:00:31.203114 high task start!
565 02:00:31.206700 low task start!
566 02:00:31.207007 run into bl31
567 02:00:31.213699 NOTICE: BL31: v1.3(release):4fc40b1
568 02:00:31.221489 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 02:00:31.221847 NOTICE: BL31: G12A normal boot!
570 02:00:31.247030 NOTICE: BL31: BL33 decompress pass
571 02:00:31.251915 ERROR: Error initializing runtime service opteed_fast
572 02:00:32.485608
573 02:00:32.486043
574 02:00:32.493977 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 02:00:32.494440
576 02:00:32.494755 Model: Libre Computer AML-A311D-CC Alta
577 02:00:32.702440 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 02:00:32.725946 DRAM: 2 GiB (effective 3.8 GiB)
579 02:00:32.868911 Core: 408 devices, 31 uclasses, devicetree: separate
580 02:00:32.874666 WDT: Not starting watchdog@f0d0
581 02:00:32.906931 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 02:00:32.919336 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 02:00:32.924323 ** Bad device specification mmc 0 **
584 02:00:32.934690 Card did not respond to voltage select! : -110
585 02:00:32.942318 ** Bad device specification mmc 0 **
586 02:00:32.942603 Couldn't find partition mmc 0
587 02:00:32.950682 Card did not respond to voltage select! : -110
588 02:00:32.956207 ** Bad device specification mmc 0 **
589 02:00:32.956499 Couldn't find partition mmc 0
590 02:00:32.961272 Error: could not access storage.
591 02:00:33.303800 Net: eth0: ethernet@ff3f0000
592 02:00:33.304264 starting USB...
593 02:00:33.555569 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 02:00:33.556034 Starting the controller
595 02:00:33.562449 USB XHCI 1.10
596 02:00:35.276570 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 02:00:35.277174 bl2_stage_init 0x01
598 02:00:35.277434 bl2_stage_init 0x81
599 02:00:35.282010 hw id: 0x0000 - pwm id 0x01
600 02:00:35.282337 bl2_stage_init 0xc1
601 02:00:35.282560 bl2_stage_init 0x02
602 02:00:35.282781
603 02:00:35.289612 L0:00000000
604 02:00:35.289971 L1:20000703
605 02:00:35.290194 L2:00008067
606 02:00:35.290417 L3:14000000
607 02:00:35.293190 B2:00402000
608 02:00:35.293499 B1:e0f83180
609 02:00:35.293729
610 02:00:35.293952 TE: 58159
611 02:00:35.294164
612 02:00:35.299328 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 02:00:35.299663
614 02:00:35.299888 Board ID = 1
615 02:00:35.304431 Set A53 clk to 24M
616 02:00:35.304906 Set A73 clk to 24M
617 02:00:35.305270 Set clk81 to 24M
618 02:00:35.311445 A53 clk: 1200 MHz
619 02:00:35.311917 A73 clk: 1200 MHz
620 02:00:35.312320 CLK81: 166.6M
621 02:00:35.312592 smccc: 00012ab5
622 02:00:35.316377 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 02:00:35.321147 board id: 1
624 02:00:35.327208 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 02:00:35.338541 fw parse done
626 02:00:35.343493 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 02:00:35.386283 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 02:00:35.397095 PIEI prepare done
629 02:00:35.397627 fastboot data load
630 02:00:35.397898 fastboot data verify
631 02:00:35.402778 verify result: 266
632 02:00:35.410847 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 02:00:35.411246 LPDDR4 probe
634 02:00:35.411477 ddr clk to 1584MHz
635 02:00:35.416395 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 02:00:35.453217
637 02:00:35.453629 dmc_version 0001
638 02:00:35.460366 Check phy result
639 02:00:35.466089 INFO : End of CA training
640 02:00:35.466424 INFO : End of initialization
641 02:00:35.471861 INFO : Training has run successfully!
642 02:00:35.472227 Check phy result
643 02:00:35.477306 INFO : End of initialization
644 02:00:35.477791 INFO : End of read enable training
645 02:00:35.483320 INFO : End of fine write leveling
646 02:00:35.488500 INFO : End of Write leveling coarse delay
647 02:00:35.488855 INFO : Training has run successfully!
648 02:00:35.489105 Check phy result
649 02:00:35.495927 INFO : End of initialization
650 02:00:35.496452 INFO : End of read dq deskew training
651 02:00:35.499670 INFO : End of MPR read delay center optimization
652 02:00:35.505276 INFO : End of write delay center optimization
653 02:00:35.514269 INFO : End of read delay center optimization
654 02:00:35.514653 INFO : End of max read latency training
655 02:00:35.516532 INFO : Training has run successfully!
656 02:00:35.517007 1D training succeed
657 02:00:35.525914 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 02:00:35.573447 Check phy result
659 02:00:35.573870 INFO : End of initialization
660 02:00:35.595767 INFO : End of 2D read delay Voltage center optimization
661 02:00:35.614941 INFO : End of 2D read delay Voltage center optimization
662 02:00:35.667849 INFO : End of 2D write delay Voltage center optimization
663 02:00:35.717134 INFO : End of 2D write delay Voltage center optimization
664 02:00:35.722652 INFO : Training has run successfully!
665 02:00:35.723208
666 02:00:35.723640 channel==0
667 02:00:35.728292 RxClkDly_Margin_A0==88 ps 9
668 02:00:35.728698 TxDqDly_Margin_A0==98 ps 10
669 02:00:35.733826 RxClkDly_Margin_A1==88 ps 9
670 02:00:35.734203 TxDqDly_Margin_A1==98 ps 10
671 02:00:35.734462 TrainedVREFDQ_A0==74
672 02:00:35.739392 TrainedVREFDQ_A1==74
673 02:00:35.739762 VrefDac_Margin_A0==25
674 02:00:35.740072 DeviceVref_Margin_A0==40
675 02:00:35.744964 VrefDac_Margin_A1==25
676 02:00:35.745326 DeviceVref_Margin_A1==40
677 02:00:35.745565
678 02:00:35.745795
679 02:00:35.750643 channel==1
680 02:00:35.751013 RxClkDly_Margin_A0==98 ps 10
681 02:00:35.751271 TxDqDly_Margin_A0==88 ps 9
682 02:00:35.756270 RxClkDly_Margin_A1==98 ps 10
683 02:00:35.756648 TxDqDly_Margin_A1==98 ps 10
684 02:00:35.761868 TrainedVREFDQ_A0==76
685 02:00:35.762244 TrainedVREFDQ_A1==77
686 02:00:35.762481 VrefDac_Margin_A0==22
687 02:00:35.767406 DeviceVref_Margin_A0==38
688 02:00:35.767770 VrefDac_Margin_A1==22
689 02:00:35.773084 DeviceVref_Margin_A1==37
690 02:00:35.773653
691 02:00:35.774064 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 02:00:35.778664
693 02:00:35.806581 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 0000001a 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
694 02:00:35.806999 2D training succeed
695 02:00:35.812212 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 02:00:35.817812 auto size-- 65535DDR cs0 size: 2048MB
697 02:00:35.818168 DDR cs1 size: 2048MB
698 02:00:35.823420 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 02:00:35.823783 cs0 DataBus test pass
700 02:00:35.828997 cs1 DataBus test pass
701 02:00:35.829365 cs0 AddrBus test pass
702 02:00:35.829621 cs1 AddrBus test pass
703 02:00:35.829858
704 02:00:35.834630 100bdlr_step_size ps== 420
705 02:00:35.835001 result report
706 02:00:35.840245 boot times 0Enable ddr reg access
707 02:00:35.845780 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 02:00:35.859135 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 02:00:36.430971 0.0;M3 CHK:0;cm4_sp_mode 0
710 02:00:36.431391 MVN_1=0x00000000
711 02:00:36.436555 MVN_2=0x00000000
712 02:00:36.442435 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 02:00:36.442786 OPS=0x10
714 02:00:36.443019 ring efuse init
715 02:00:36.443253 chipver efuse init
716 02:00:36.447855 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 02:00:36.453439 [0.018961 Inits done]
718 02:00:36.454037 secure task start!
719 02:00:36.454566 high task start!
720 02:00:36.458105 low task start!
721 02:00:36.458447 run into bl31
722 02:00:36.464765 NOTICE: BL31: v1.3(release):4fc40b1
723 02:00:36.472670 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 02:00:36.473324 NOTICE: BL31: G12A normal boot!
725 02:00:36.498087 NOTICE: BL31: BL33 decompress pass
726 02:00:36.503740 ERROR: Error initializing runtime service opteed_fast
727 02:00:37.736399
728 02:00:37.736829
729 02:00:37.744271 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 02:00:37.744710
731 02:00:37.745027 Model: Libre Computer AML-A311D-CC Alta
732 02:00:37.952400 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 02:00:37.976740 DRAM: 2 GiB (effective 3.8 GiB)
734 02:00:38.120192 Core: 408 devices, 31 uclasses, devicetree: separate
735 02:00:38.124732 WDT: Not starting watchdog@f0d0
736 02:00:38.157783 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 02:00:38.170195 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 02:00:38.175022 ** Bad device specification mmc 0 **
739 02:00:38.185552 Card did not respond to voltage select! : -110
740 02:00:38.192233 ** Bad device specification mmc 0 **
741 02:00:38.192588 Couldn't find partition mmc 0
742 02:00:38.201585 Card did not respond to voltage select! : -110
743 02:00:38.207059 ** Bad device specification mmc 0 **
744 02:00:38.207395 Couldn't find partition mmc 0
745 02:00:38.211198 Error: could not access storage.
746 02:00:38.554901 Net: eth0: ethernet@ff3f0000
747 02:00:38.555330 starting USB...
748 02:00:38.807337 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 02:00:38.807731 Starting the controller
750 02:00:38.813550 USB XHCI 1.10
751 02:00:40.976549 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 02:00:40.977006 bl2_stage_init 0x01
753 02:00:40.977287 bl2_stage_init 0x81
754 02:00:40.982122 hw id: 0x0000 - pwm id 0x01
755 02:00:40.982545 bl2_stage_init 0xc1
756 02:00:40.982813 bl2_stage_init 0x02
757 02:00:40.983072
758 02:00:40.987638 L0:00000000
759 02:00:40.988054 L1:20000703
760 02:00:40.988312 L2:00008067
761 02:00:40.988539 L3:14000000
762 02:00:40.993281 B2:00402000
763 02:00:40.993890 B1:e0f83180
764 02:00:40.994404
765 02:00:40.994681 TE: 58124
766 02:00:40.994940
767 02:00:40.998866 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 02:00:40.999248
769 02:00:40.999489 Board ID = 1
770 02:00:41.004478 Set A53 clk to 24M
771 02:00:41.004871 Set A73 clk to 24M
772 02:00:41.005120 Set clk81 to 24M
773 02:00:41.010238 A53 clk: 1200 MHz
774 02:00:41.010816 A73 clk: 1200 MHz
775 02:00:41.011345 CLK81: 166.6M
776 02:00:41.011607 smccc: 00012a92
777 02:00:41.015604 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 02:00:41.021250 board id: 1
779 02:00:41.026643 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 02:00:41.037823 fw parse done
781 02:00:41.043130 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 02:00:41.085619 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 02:00:41.097320 PIEI prepare done
784 02:00:41.097970 fastboot data load
785 02:00:41.098425 fastboot data verify
786 02:00:41.104194 verify result: 266
787 02:00:41.108873 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 02:00:41.109322 LPDDR4 probe
789 02:00:41.109596 ddr clk to 1584MHz
790 02:00:41.115853 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 02:00:41.153487
792 02:00:41.153924 dmc_version 0001
793 02:00:41.159440 Check phy result
794 02:00:41.166209 INFO : End of CA training
795 02:00:41.166572 INFO : End of initialization
796 02:00:41.172269 INFO : Training has run successfully!
797 02:00:41.172659 Check phy result
798 02:00:41.177454 INFO : End of initialization
799 02:00:41.177845 INFO : End of read enable training
800 02:00:41.183823 INFO : End of fine write leveling
801 02:00:41.189395 INFO : End of Write leveling coarse delay
802 02:00:41.189794 INFO : Training has run successfully!
803 02:00:41.190028 Check phy result
804 02:00:41.194342 INFO : End of initialization
805 02:00:41.194798 INFO : End of read dq deskew training
806 02:00:41.199836 INFO : End of MPR read delay center optimization
807 02:00:41.205566 INFO : End of write delay center optimization
808 02:00:41.211275 INFO : End of read delay center optimization
809 02:00:41.211727 INFO : End of max read latency training
810 02:00:41.216592 INFO : Training has run successfully!
811 02:00:41.217009 1D training succeed
812 02:00:41.225731 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 02:00:41.273472 Check phy result
814 02:00:41.273921 INFO : End of initialization
815 02:00:41.295145 INFO : End of 2D read delay Voltage center optimization
816 02:00:41.315320 INFO : End of 2D read delay Voltage center optimization
817 02:00:41.367436 INFO : End of 2D write delay Voltage center optimization
818 02:00:41.418366 INFO : End of 2D write delay Voltage center optimization
819 02:00:41.422721 INFO : Training has run successfully!
820 02:00:41.423125
821 02:00:41.423372 channel==0
822 02:00:41.428218 RxClkDly_Margin_A0==88 ps 9
823 02:00:41.428675 TxDqDly_Margin_A0==98 ps 10
824 02:00:41.433781 RxClkDly_Margin_A1==88 ps 9
825 02:00:41.434194 TxDqDly_Margin_A1==98 ps 10
826 02:00:41.434444 TrainedVREFDQ_A0==74
827 02:00:41.439389 TrainedVREFDQ_A1==74
828 02:00:41.439802 VrefDac_Margin_A0==25
829 02:00:41.440083 DeviceVref_Margin_A0==40
830 02:00:41.445084 VrefDac_Margin_A1==25
831 02:00:41.445463 DeviceVref_Margin_A1==40
832 02:00:41.445695
833 02:00:41.445916
834 02:00:41.450548 channel==1
835 02:00:41.450915 RxClkDly_Margin_A0==98 ps 10
836 02:00:41.451126 TxDqDly_Margin_A0==98 ps 10
837 02:00:41.456197 RxClkDly_Margin_A1==88 ps 9
838 02:00:41.456601 TxDqDly_Margin_A1==88 ps 9
839 02:00:41.461853 TrainedVREFDQ_A0==77
840 02:00:41.462236 TrainedVREFDQ_A1==77
841 02:00:41.462476 VrefDac_Margin_A0==22
842 02:00:41.467321 DeviceVref_Margin_A0==37
843 02:00:41.467675 VrefDac_Margin_A1==24
844 02:00:41.472994 DeviceVref_Margin_A1==37
845 02:00:41.473338
846 02:00:41.473569 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 02:00:41.473794
848 02:00:41.506728 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000016 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
849 02:00:41.507143 2D training succeed
850 02:00:41.512374 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 02:00:41.518370 auto size-- 65535DDR cs0 size: 2048MB
852 02:00:41.518751 DDR cs1 size: 2048MB
853 02:00:41.523492 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 02:00:41.523871 cs0 DataBus test pass
855 02:00:41.529121 cs1 DataBus test pass
856 02:00:41.529520 cs0 AddrBus test pass
857 02:00:41.529769 cs1 AddrBus test pass
858 02:00:41.530013
859 02:00:41.534648 100bdlr_step_size ps== 420
860 02:00:41.535063 result report
861 02:00:41.540264 boot times 0Enable ddr reg access
862 02:00:41.545665 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 02:00:41.558869 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 02:00:42.131192 0.0;M3 CHK:0;cm4_sp_mode 0
865 02:00:42.131621 MVN_1=0x00000000
866 02:00:42.136535 MVN_2=0x00000000
867 02:00:42.142376 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 02:00:42.142804 OPS=0x10
869 02:00:42.143082 ring efuse init
870 02:00:42.143347 chipver efuse init
871 02:00:42.150647 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 02:00:42.151095 [0.018960 Inits done]
873 02:00:42.151384 secure task start!
874 02:00:42.157630 high task start!
875 02:00:42.158024 low task start!
876 02:00:42.158250 run into bl31
877 02:00:42.164870 NOTICE: BL31: v1.3(release):4fc40b1
878 02:00:42.171677 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 02:00:42.172148 NOTICE: BL31: G12A normal boot!
880 02:00:42.197900 NOTICE: BL31: BL33 decompress pass
881 02:00:42.202602 ERROR: Error initializing runtime service opteed_fast
882 02:00:43.436343
883 02:00:43.436783
884 02:00:43.443877 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 02:00:43.444291
886 02:00:43.444524 Model: Libre Computer AML-A311D-CC Alta
887 02:00:43.652417 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 02:00:43.676023 DRAM: 2 GiB (effective 3.8 GiB)
889 02:00:43.819599 Core: 408 devices, 31 uclasses, devicetree: separate
890 02:00:43.825167 WDT: Not starting watchdog@f0d0
891 02:00:43.857741 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 02:00:43.870383 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 02:00:43.874516 ** Bad device specification mmc 0 **
894 02:00:43.885553 Card did not respond to voltage select! : -110
895 02:00:43.893177 ** Bad device specification mmc 0 **
896 02:00:43.893598 Couldn't find partition mmc 0
897 02:00:43.901508 Card did not respond to voltage select! : -110
898 02:00:43.907023 ** Bad device specification mmc 0 **
899 02:00:43.907425 Couldn't find partition mmc 0
900 02:00:43.911501 Error: could not access storage.
901 02:00:44.254998 Net: eth0: ethernet@ff3f0000
902 02:00:44.255439 starting USB...
903 02:00:44.507581 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 02:00:44.508043 Starting the controller
905 02:00:44.513464 USB XHCI 1.10
906 02:00:46.376105 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 02:00:46.376521 bl2_stage_init 0x01
908 02:00:46.376750 bl2_stage_init 0x81
909 02:00:46.381707 hw id: 0x0000 - pwm id 0x01
910 02:00:46.382062 bl2_stage_init 0xc1
911 02:00:46.382293 bl2_stage_init 0x02
912 02:00:46.382507
913 02:00:46.387302 L0:00000000
914 02:00:46.387639 L1:20000703
915 02:00:46.387866 L2:00008067
916 02:00:46.388108 L3:14000000
917 02:00:46.390172 B2:00402000
918 02:00:46.390466 B1:e0f83180
919 02:00:46.390681
920 02:00:46.390887 TE: 58124
921 02:00:46.391095
922 02:00:46.401320 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 02:00:46.401901
924 02:00:46.402330 Board ID = 1
925 02:00:46.402740 Set A53 clk to 24M
926 02:00:46.403098 Set A73 clk to 24M
927 02:00:46.406877 Set clk81 to 24M
928 02:00:46.407410 A53 clk: 1200 MHz
929 02:00:46.407833 A73 clk: 1200 MHz
930 02:00:46.410418 CLK81: 166.6M
931 02:00:46.410942 smccc: 00012a91
932 02:00:46.416142 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 02:00:46.421652 board id: 1
934 02:00:46.426361 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 02:00:46.437428 fw parse done
936 02:00:46.442432 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 02:00:46.484962 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 02:00:46.496963 PIEI prepare done
939 02:00:46.497308 fastboot data load
940 02:00:46.497527 fastboot data verify
941 02:00:46.502638 verify result: 266
942 02:00:46.508226 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 02:00:46.508547 LPDDR4 probe
944 02:00:46.508764 ddr clk to 1584MHz
945 02:00:46.515170 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 02:00:46.552573
947 02:00:46.553144 dmc_version 0001
948 02:00:46.559114 Check phy result
949 02:00:46.565872 INFO : End of CA training
950 02:00:46.566206 INFO : End of initialization
951 02:00:46.571525 INFO : Training has run successfully!
952 02:00:46.571868 Check phy result
953 02:00:46.577157 INFO : End of initialization
954 02:00:46.577519 INFO : End of read enable training
955 02:00:46.580357 INFO : End of fine write leveling
956 02:00:46.585968 INFO : End of Write leveling coarse delay
957 02:00:46.591569 INFO : Training has run successfully!
958 02:00:46.591946 Check phy result
959 02:00:46.592238 INFO : End of initialization
960 02:00:46.597120 INFO : End of read dq deskew training
961 02:00:46.600617 INFO : End of MPR read delay center optimization
962 02:00:46.606097 INFO : End of write delay center optimization
963 02:00:46.611826 INFO : End of read delay center optimization
964 02:00:46.612217 INFO : End of max read latency training
965 02:00:46.617306 INFO : Training has run successfully!
966 02:00:46.617656 1D training succeed
967 02:00:46.624506 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 02:00:46.672260 Check phy result
969 02:00:46.672842 INFO : End of initialization
970 02:00:46.694876 INFO : End of 2D read delay Voltage center optimization
971 02:00:46.715150 INFO : End of 2D read delay Voltage center optimization
972 02:00:46.767152 INFO : End of 2D write delay Voltage center optimization
973 02:00:46.817541 INFO : End of 2D write delay Voltage center optimization
974 02:00:46.822916 INFO : Training has run successfully!
975 02:00:46.823257
976 02:00:46.823603 channel==0
977 02:00:46.828566 RxClkDly_Margin_A0==88 ps 9
978 02:00:46.828903 TxDqDly_Margin_A0==98 ps 10
979 02:00:46.831745 RxClkDly_Margin_A1==78 ps 8
980 02:00:46.832047 TxDqDly_Margin_A1==98 ps 10
981 02:00:46.837295 TrainedVREFDQ_A0==74
982 02:00:46.837589 TrainedVREFDQ_A1==74
983 02:00:46.842976 VrefDac_Margin_A0==24
984 02:00:46.843295 DeviceVref_Margin_A0==40
985 02:00:46.843512 VrefDac_Margin_A1==25
986 02:00:46.848559 DeviceVref_Margin_A1==40
987 02:00:46.848872
988 02:00:46.849093
989 02:00:46.849304 channel==1
990 02:00:46.849513 RxClkDly_Margin_A0==98 ps 10
991 02:00:46.851841 TxDqDly_Margin_A0==88 ps 9
992 02:00:46.857441 RxClkDly_Margin_A1==98 ps 10
993 02:00:46.857755 TxDqDly_Margin_A1==108 ps 11
994 02:00:46.863030 TrainedVREFDQ_A0==77
995 02:00:46.863322 TrainedVREFDQ_A1==78
996 02:00:46.863534 VrefDac_Margin_A0==22
997 02:00:46.868679 DeviceVref_Margin_A0==37
998 02:00:46.868972 VrefDac_Margin_A1==24
999 02:00:46.869182 DeviceVref_Margin_A1==36
1000 02:00:46.869387
1001 02:00:46.874274 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 02:00:46.874634
1003 02:00:46.907901 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1004 02:00:46.908588 2D training succeed
1005 02:00:46.913479 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 02:00:46.919059 auto size-- 65535DDR cs0 size: 2048MB
1007 02:00:46.919577 DDR cs1 size: 2048MB
1008 02:00:46.924679 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 02:00:46.925195 cs0 DataBus test pass
1010 02:00:46.925610 cs1 DataBus test pass
1011 02:00:46.930259 cs0 AddrBus test pass
1012 02:00:46.930767 cs1 AddrBus test pass
1013 02:00:46.931185
1014 02:00:46.935896 100bdlr_step_size ps== 420
1015 02:00:46.936470 result report
1016 02:00:46.936903 boot times 0Enable ddr reg access
1017 02:00:46.945141 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 02:00:46.958684 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 02:00:47.533228 0.0;M3 CHK:0;cm4_sp_mode 0
1020 02:00:47.533840 MVN_1=0x00000000
1021 02:00:47.538678 MVN_2=0x00000000
1022 02:00:47.544462 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 02:00:47.544929 OPS=0x10
1024 02:00:47.545337 ring efuse init
1025 02:00:47.545738 chipver efuse init
1026 02:00:47.550014 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 02:00:47.555599 [0.018961 Inits done]
1028 02:00:47.556082 secure task start!
1029 02:00:47.556492 high task start!
1030 02:00:47.559315 low task start!
1031 02:00:47.559759 run into bl31
1032 02:00:47.566858 NOTICE: BL31: v1.3(release):4fc40b1
1033 02:00:47.574710 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 02:00:47.575166 NOTICE: BL31: G12A normal boot!
1035 02:00:47.600089 NOTICE: BL31: BL33 decompress pass
1036 02:00:47.605691 ERROR: Error initializing runtime service opteed_fast
1037 02:00:48.838629
1038 02:00:48.839261
1039 02:00:48.847004 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 02:00:48.847468
1041 02:00:48.847876 Model: Libre Computer AML-A311D-CC Alta
1042 02:00:49.055380 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 02:00:49.078813 DRAM: 2 GiB (effective 3.8 GiB)
1044 02:00:49.221886 Core: 408 devices, 31 uclasses, devicetree: separate
1045 02:00:49.227872 WDT: Not starting watchdog@f0d0
1046 02:00:49.259924 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 02:00:49.272463 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 02:00:49.277432 ** Bad device specification mmc 0 **
1049 02:00:49.287766 Card did not respond to voltage select! : -110
1050 02:00:49.295432 ** Bad device specification mmc 0 **
1051 02:00:49.295837 Couldn't find partition mmc 0
1052 02:00:49.303760 Card did not respond to voltage select! : -110
1053 02:00:49.309238 ** Bad device specification mmc 0 **
1054 02:00:49.309837 Couldn't find partition mmc 0
1055 02:00:49.314310 Error: could not access storage.
1056 02:00:49.656706 Net: eth0: ethernet@ff3f0000
1057 02:00:49.657140 starting USB...
1058 02:00:49.908424 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 02:00:49.908839 Starting the controller
1060 02:00:49.915408 USB XHCI 1.10
1061 02:00:51.469913 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 02:00:51.478142 scanning usb for storage devices... 0 Storage Device(s) found
1064 02:00:51.529918 Hit any key to stop autoboot: 1
1065 02:00:51.530860 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1066 02:00:51.531244 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1067 02:00:51.531523 Setting prompt string to ['=>']
1068 02:00:51.531801 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1069 02:00:51.545628 0
1070 02:00:51.546378 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 02:00:51.546688 Sending with 10 millisecond of delay
1073 02:00:52.681738 => setenv autoload no
1074 02:00:52.692548 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1075 02:00:52.697474 setenv autoload no
1076 02:00:52.698206 Sending with 10 millisecond of delay
1078 02:00:54.495682 => setenv initrd_high 0xffffffff
1079 02:00:54.506459 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1080 02:00:54.507099 setenv initrd_high 0xffffffff
1081 02:00:54.507626 Sending with 10 millisecond of delay
1083 02:00:56.126523 => setenv fdt_high 0xffffffff
1084 02:00:56.137319 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1085 02:00:56.138159 setenv fdt_high 0xffffffff
1086 02:00:56.138868 Sending with 10 millisecond of delay
1088 02:00:56.430700 => dhcp
1089 02:00:56.441496 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1090 02:00:56.442378 dhcp
1091 02:00:56.442820 Speed: 1000, full duplex
1092 02:00:56.443239 BOOTP broadcast 1
1093 02:00:56.445120 DHCP client bound to address 192.168.6.27 (3 ms)
1094 02:00:56.445859 Sending with 10 millisecond of delay
1096 02:00:58.123732 => setenv serverip 192.168.6.2
1097 02:00:58.134672 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1098 02:00:58.135647 setenv serverip 192.168.6.2
1099 02:00:58.136436 Sending with 10 millisecond of delay
1101 02:01:01.862556 => tftpboot 0x01080000 964231/tftp-deploy-4hkk71vb/kernel/uImage
1102 02:01:01.873181 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1103 02:01:01.873732 tftpboot 0x01080000 964231/tftp-deploy-4hkk71vb/kernel/uImage
1104 02:01:01.873994 Speed: 1000, full duplex
1105 02:01:01.874222 Using ethernet@ff3f0000 device
1106 02:01:01.876048 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1107 02:01:01.881386 Filename '964231/tftp-deploy-4hkk71vb/kernel/uImage'.
1108 02:01:01.885381 Load address: 0x1080000
1109 02:01:03.694726 Loading: *######################## UDP wrong checksum 000000ff 0000482a
1110 02:01:03.702695 UDP wrong checksum 000000ff 0000cd1c
1111 02:01:05.238290 ########################## 43.6 MiB
1112 02:01:05.238908 13 MiB/s
1113 02:01:05.239342 done
1114 02:01:05.242652 Bytes transferred = 45713984 (2b98a40 hex)
1115 02:01:05.243444 Sending with 10 millisecond of delay
1117 02:01:09.932184 => tftpboot 0x08000000 964231/tftp-deploy-4hkk71vb/ramdisk/ramdisk.cpio.gz.uboot
1118 02:01:09.943004 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1119 02:01:09.943929 tftpboot 0x08000000 964231/tftp-deploy-4hkk71vb/ramdisk/ramdisk.cpio.gz.uboot
1120 02:01:09.944474 Speed: 1000, full duplex
1121 02:01:09.944926 Using ethernet@ff3f0000 device
1122 02:01:09.945866 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1123 02:01:09.957680 Filename '964231/tftp-deploy-4hkk71vb/ramdisk/ramdisk.cpio.gz.uboot'.
1124 02:01:09.958207 Load address: 0x8000000
1125 02:01:16.753175 Loading: *###T ############################################## UDP wrong checksum 00000005 00007415
1126 02:01:21.753641 UDP wrong checksum 00000005 00007415
1127 02:01:31.756252 T T UDP wrong checksum 00000005 00007415
1128 02:01:34.031696 T UDP wrong checksum 000000ff 000046a8
1129 02:01:34.052003 UDP wrong checksum 000000ff 0000db9a
1130 02:01:51.762448 T T T T UDP wrong checksum 00000005 00007415
1131 02:02:06.765589 T T
1132 02:02:06.766253 Retry count exceeded; starting again
1134 02:02:06.767794 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1137 02:02:06.769921 end: 2.4 uboot-commands (duration 00:01:52) [common]
1139 02:02:06.771450 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1141 02:02:06.772750 end: 2 uboot-action (duration 00:01:52) [common]
1143 02:02:06.774436 Cleaning after the job
1144 02:02:06.775021 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964231/tftp-deploy-4hkk71vb/ramdisk
1145 02:02:06.776539 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964231/tftp-deploy-4hkk71vb/kernel
1146 02:02:06.784731 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964231/tftp-deploy-4hkk71vb/dtb
1147 02:02:06.786088 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964231/tftp-deploy-4hkk71vb/modules
1148 02:02:06.797927 start: 4.1 power-off (timeout 00:00:30) [common]
1149 02:02:06.799022 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1150 02:02:06.834337 >> OK - accepted request
1151 02:02:06.836124 Returned 0 in 0 seconds
1152 02:02:06.937361 end: 4.1 power-off (duration 00:00:00) [common]
1154 02:02:06.939199 start: 4.2 read-feedback (timeout 00:10:00) [common]
1155 02:02:06.940459 Listened to connection for namespace 'common' for up to 1s
1156 02:02:07.940347 Finalising connection for namespace 'common'
1157 02:02:07.941161 Disconnecting from shell: Finalise
1158 02:02:07.941731 =>
1159 02:02:08.042835 end: 4.2 read-feedback (duration 00:00:01) [common]
1160 02:02:08.043594 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/964231
1161 02:02:08.326320 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/964231
1162 02:02:08.326888 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.