Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 6
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 02:15:56.961496 lava-dispatcher, installed at version: 2024.01
2 02:15:56.962401 start: 0 validate
3 02:15:56.962938 Start time: 2024-11-09 02:15:56.962905+00:00 (UTC)
4 02:15:56.963712 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:15:56.964360 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:15:57.003228 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:15:57.003810 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-246-gdbbaaaa6179b%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:15:57.035796 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:15:57.036459 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-246-gdbbaaaa6179b%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:15:57.070149 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:15:57.070686 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:15:57.114891 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:15:57.115413 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-246-gdbbaaaa6179b%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 02:15:57.156151 validate duration: 0.19
16 02:15:57.157052 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:15:57.157402 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:15:57.157754 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:15:57.158436 Not decompressing ramdisk as can be used compressed.
20 02:15:57.158925 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 02:15:57.159230 saving as /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/ramdisk/initrd.cpio.gz
22 02:15:57.159529 total size: 5628169 (5 MB)
23 02:15:57.198363 progress 0 % (0 MB)
24 02:15:57.202891 progress 5 % (0 MB)
25 02:15:57.207299 progress 10 % (0 MB)
26 02:15:57.211113 progress 15 % (0 MB)
27 02:15:57.215380 progress 20 % (1 MB)
28 02:15:57.219125 progress 25 % (1 MB)
29 02:15:57.223402 progress 30 % (1 MB)
30 02:15:57.227667 progress 35 % (1 MB)
31 02:15:57.231375 progress 40 % (2 MB)
32 02:15:57.235373 progress 45 % (2 MB)
33 02:15:57.239158 progress 50 % (2 MB)
34 02:15:57.243179 progress 55 % (2 MB)
35 02:15:57.247152 progress 60 % (3 MB)
36 02:15:57.250650 progress 65 % (3 MB)
37 02:15:57.254754 progress 70 % (3 MB)
38 02:15:57.258265 progress 75 % (4 MB)
39 02:15:57.262156 progress 80 % (4 MB)
40 02:15:57.265513 progress 85 % (4 MB)
41 02:15:57.269133 progress 90 % (4 MB)
42 02:15:57.272713 progress 95 % (5 MB)
43 02:15:57.275970 progress 100 % (5 MB)
44 02:15:57.276645 5 MB downloaded in 0.12 s (45.84 MB/s)
45 02:15:57.277153 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:15:57.278031 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:15:57.278320 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:15:57.278586 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:15:57.279055 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm64/defconfig/gcc-12/kernel/Image
51 02:15:57.279292 saving as /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/kernel/Image
52 02:15:57.279499 total size: 45713920 (43 MB)
53 02:15:57.279708 No compression specified
54 02:15:57.320918 progress 0 % (0 MB)
55 02:15:57.348259 progress 5 % (2 MB)
56 02:15:57.376770 progress 10 % (4 MB)
57 02:15:57.404542 progress 15 % (6 MB)
58 02:15:57.431944 progress 20 % (8 MB)
59 02:15:57.459327 progress 25 % (10 MB)
60 02:15:57.486742 progress 30 % (13 MB)
61 02:15:57.516088 progress 35 % (15 MB)
62 02:15:57.543535 progress 40 % (17 MB)
63 02:15:57.570170 progress 45 % (19 MB)
64 02:15:57.597489 progress 50 % (21 MB)
65 02:15:57.624883 progress 55 % (24 MB)
66 02:15:57.652401 progress 60 % (26 MB)
67 02:15:57.678939 progress 65 % (28 MB)
68 02:15:57.705937 progress 70 % (30 MB)
69 02:15:57.733146 progress 75 % (32 MB)
70 02:15:57.760544 progress 80 % (34 MB)
71 02:15:57.787736 progress 85 % (37 MB)
72 02:15:57.815155 progress 90 % (39 MB)
73 02:15:57.842768 progress 95 % (41 MB)
74 02:15:57.869129 progress 100 % (43 MB)
75 02:15:57.869640 43 MB downloaded in 0.59 s (73.88 MB/s)
76 02:15:57.870105 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:15:57.870916 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:15:57.871188 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:15:57.871450 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:15:57.871918 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 02:15:57.872211 saving as /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/dtb/meson-g12b-a311d-libretech-cc.dtb
83 02:15:57.872419 total size: 54703 (0 MB)
84 02:15:57.872627 No compression specified
85 02:15:57.913175 progress 59 % (0 MB)
86 02:15:57.914033 progress 100 % (0 MB)
87 02:15:57.914624 0 MB downloaded in 0.04 s (1.24 MB/s)
88 02:15:57.915126 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:15:57.915968 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:15:57.916287 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:15:57.916566 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:15:57.917040 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 02:15:57.917290 saving as /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/nfsrootfs/full.rootfs.tar
95 02:15:57.917508 total size: 120894716 (115 MB)
96 02:15:57.917728 Using unxz to decompress xz
97 02:15:57.954128 progress 0 % (0 MB)
98 02:15:58.743056 progress 5 % (5 MB)
99 02:15:59.596372 progress 10 % (11 MB)
100 02:16:00.401156 progress 15 % (17 MB)
101 02:16:01.138991 progress 20 % (23 MB)
102 02:16:01.745146 progress 25 % (28 MB)
103 02:16:02.568435 progress 30 % (34 MB)
104 02:16:03.385038 progress 35 % (40 MB)
105 02:16:03.746038 progress 40 % (46 MB)
106 02:16:04.117861 progress 45 % (51 MB)
107 02:16:04.836536 progress 50 % (57 MB)
108 02:16:05.718551 progress 55 % (63 MB)
109 02:16:06.507644 progress 60 % (69 MB)
110 02:16:07.286235 progress 65 % (74 MB)
111 02:16:08.077573 progress 70 % (80 MB)
112 02:16:08.900219 progress 75 % (86 MB)
113 02:16:09.682728 progress 80 % (92 MB)
114 02:16:10.438701 progress 85 % (98 MB)
115 02:16:11.283627 progress 90 % (103 MB)
116 02:16:12.050433 progress 95 % (109 MB)
117 02:16:12.871189 progress 100 % (115 MB)
118 02:16:12.883618 115 MB downloaded in 14.97 s (7.70 MB/s)
119 02:16:12.884363 end: 1.4.1 http-download (duration 00:00:15) [common]
121 02:16:12.886136 end: 1.4 download-retry (duration 00:00:15) [common]
122 02:16:12.886714 start: 1.5 download-retry (timeout 00:09:44) [common]
123 02:16:12.887287 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 02:16:12.888176 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm64/defconfig/gcc-12/modules.tar.xz
125 02:16:12.888718 saving as /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/modules/modules.tar
126 02:16:12.889177 total size: 11610740 (11 MB)
127 02:16:12.889640 Using unxz to decompress xz
128 02:16:12.940031 progress 0 % (0 MB)
129 02:16:13.009164 progress 5 % (0 MB)
130 02:16:13.086600 progress 10 % (1 MB)
131 02:16:13.181571 progress 15 % (1 MB)
132 02:16:13.271614 progress 20 % (2 MB)
133 02:16:13.350427 progress 25 % (2 MB)
134 02:16:13.426048 progress 30 % (3 MB)
135 02:16:13.503247 progress 35 % (3 MB)
136 02:16:13.575347 progress 40 % (4 MB)
137 02:16:13.649957 progress 45 % (5 MB)
138 02:16:13.733006 progress 50 % (5 MB)
139 02:16:13.808776 progress 55 % (6 MB)
140 02:16:13.892082 progress 60 % (6 MB)
141 02:16:13.971130 progress 65 % (7 MB)
142 02:16:14.050357 progress 70 % (7 MB)
143 02:16:14.126856 progress 75 % (8 MB)
144 02:16:14.208809 progress 80 % (8 MB)
145 02:16:14.287625 progress 85 % (9 MB)
146 02:16:14.365198 progress 90 % (9 MB)
147 02:16:14.442411 progress 95 % (10 MB)
148 02:16:14.518845 progress 100 % (11 MB)
149 02:16:14.530277 11 MB downloaded in 1.64 s (6.75 MB/s)
150 02:16:14.530874 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:16:14.531699 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:16:14.531969 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 02:16:14.532593 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 02:16:31.108994 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/964271/extract-nfsrootfs-gb3yb0qe
156 02:16:31.109616 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 02:16:31.109942 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 02:16:31.110584 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7
159 02:16:31.111077 makedir: /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin
160 02:16:31.111491 makedir: /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/tests
161 02:16:31.111872 makedir: /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/results
162 02:16:31.112265 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-add-keys
163 02:16:31.112807 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-add-sources
164 02:16:31.113303 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-background-process-start
165 02:16:31.113785 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-background-process-stop
166 02:16:31.114290 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-common-functions
167 02:16:31.114770 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-echo-ipv4
168 02:16:31.115238 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-install-packages
169 02:16:31.115697 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-installed-packages
170 02:16:31.116190 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-os-build
171 02:16:31.116666 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-probe-channel
172 02:16:31.117133 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-probe-ip
173 02:16:31.117598 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-target-ip
174 02:16:31.118059 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-target-mac
175 02:16:31.118516 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-target-storage
176 02:16:31.119015 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-test-case
177 02:16:31.119583 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-test-event
178 02:16:31.120076 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-test-feedback
179 02:16:31.120560 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-test-raise
180 02:16:31.121022 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-test-reference
181 02:16:31.121487 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-test-runner
182 02:16:31.121953 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-test-set
183 02:16:31.122421 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-test-shell
184 02:16:31.122913 Updating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-add-keys (debian)
185 02:16:31.123453 Updating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-add-sources (debian)
186 02:16:31.123969 Updating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-install-packages (debian)
187 02:16:31.124543 Updating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-installed-packages (debian)
188 02:16:31.125032 Updating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/bin/lava-os-build (debian)
189 02:16:31.125460 Creating /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/environment
190 02:16:31.125826 LAVA metadata
191 02:16:31.126079 - LAVA_JOB_ID=964271
192 02:16:31.126291 - LAVA_DISPATCHER_IP=192.168.6.2
193 02:16:31.126643 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 02:16:31.127573 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 02:16:31.127877 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 02:16:31.128147 skipped lava-vland-overlay
197 02:16:31.128393 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 02:16:31.128647 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 02:16:31.128863 skipped lava-multinode-overlay
200 02:16:31.129103 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 02:16:31.129353 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 02:16:31.129595 Loading test definitions
203 02:16:31.129867 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 02:16:31.130083 Using /lava-964271 at stage 0
205 02:16:31.131124 uuid=964271_1.6.2.4.1 testdef=None
206 02:16:31.131418 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 02:16:31.131675 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 02:16:31.133241 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 02:16:31.134026 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 02:16:31.135889 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 02:16:31.136728 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 02:16:31.138520 runner path: /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/0/tests/0_timesync-off test_uuid 964271_1.6.2.4.1
215 02:16:31.139046 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 02:16:31.139851 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 02:16:31.140131 Using /lava-964271 at stage 0
219 02:16:31.140484 Fetching tests from https://github.com/kernelci/test-definitions.git
220 02:16:31.140766 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/0/tests/1_kselftest-alsa'
221 02:16:35.264725 Running '/usr/bin/git checkout kernelci.org
222 02:16:35.511079 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 02:16:35.512590 uuid=964271_1.6.2.4.5 testdef=None
224 02:16:35.512946 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 02:16:35.513695 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 02:16:35.516505 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 02:16:35.517319 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 02:16:35.521009 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 02:16:35.521861 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 02:16:35.525452 runner path: /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/0/tests/1_kselftest-alsa test_uuid 964271_1.6.2.4.5
234 02:16:35.525741 BOARD='meson-g12b-a311d-libretech-cc'
235 02:16:35.525945 BRANCH='broonie-sound'
236 02:16:35.526142 SKIPFILE='/dev/null'
237 02:16:35.526339 SKIP_INSTALL='True'
238 02:16:35.526533 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 02:16:35.526731 TST_CASENAME=''
240 02:16:35.526927 TST_CMDFILES='alsa'
241 02:16:35.527471 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 02:16:35.528280 Creating lava-test-runner.conf files
244 02:16:35.528488 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/964271/lava-overlay-2wcsoxh7/lava-964271/0 for stage 0
245 02:16:35.528841 - 0_timesync-off
246 02:16:35.529081 - 1_kselftest-alsa
247 02:16:35.529409 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 02:16:35.529687 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 02:16:58.918643 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 02:16:58.919114 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 02:16:58.919386 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 02:16:58.919666 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 02:16:58.919934 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 02:16:59.535485 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 02:16:59.535959 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 02:16:59.536286 extracting modules file /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964271/extract-nfsrootfs-gb3yb0qe
257 02:17:00.915232 extracting modules file /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964271/extract-overlay-ramdisk-k56g3jc9/ramdisk
258 02:17:02.322080 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 02:17:02.322565 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 02:17:02.322852 [common] Applying overlay to NFS
261 02:17:02.323071 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964271/compress-overlay-n22094xb/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/964271/extract-nfsrootfs-gb3yb0qe
262 02:17:05.055462 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 02:17:05.055940 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 02:17:05.056241 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 02:17:05.056472 Converting downloaded kernel to a uImage
266 02:17:05.056783 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/kernel/Image /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/kernel/uImage
267 02:17:05.537140 output: Image Name:
268 02:17:05.537571 output: Created: Sat Nov 9 02:17:05 2024
269 02:17:05.537790 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 02:17:05.537998 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 02:17:05.538205 output: Load Address: 01080000
272 02:17:05.538406 output: Entry Point: 01080000
273 02:17:05.538605 output:
274 02:17:05.538938 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 02:17:05.539206 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 02:17:05.539475 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 02:17:05.539731 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 02:17:05.540022 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 02:17:05.540302 Building ramdisk /var/lib/lava/dispatcher/tmp/964271/extract-overlay-ramdisk-k56g3jc9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/964271/extract-overlay-ramdisk-k56g3jc9/ramdisk
280 02:17:07.807350 >> 166792 blocks
281 02:17:15.673686 Adding RAMdisk u-boot header.
282 02:17:15.674328 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/964271/extract-overlay-ramdisk-k56g3jc9/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/964271/extract-overlay-ramdisk-k56g3jc9/ramdisk.cpio.gz.uboot
283 02:17:15.921010 output: Image Name:
284 02:17:15.921461 output: Created: Sat Nov 9 02:17:15 2024
285 02:17:15.921675 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 02:17:15.921883 output: Data Size: 23432036 Bytes = 22882.85 KiB = 22.35 MiB
287 02:17:15.922085 output: Load Address: 00000000
288 02:17:15.922286 output: Entry Point: 00000000
289 02:17:15.922487 output:
290 02:17:15.923137 rename /var/lib/lava/dispatcher/tmp/964271/extract-overlay-ramdisk-k56g3jc9/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/ramdisk/ramdisk.cpio.gz.uboot
291 02:17:15.923596 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 02:17:15.923894 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 02:17:15.924412 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 02:17:15.924882 No LXC device requested
295 02:17:15.925395 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 02:17:15.925914 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 02:17:15.926412 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 02:17:15.926826 Checking files for TFTP limit of 4294967296 bytes.
299 02:17:15.929613 end: 1 tftp-deploy (duration 00:01:19) [common]
300 02:17:15.930249 start: 2 uboot-action (timeout 00:05:00) [common]
301 02:17:15.930781 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 02:17:15.931276 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 02:17:15.931784 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 02:17:15.932361 Using kernel file from prepare-kernel: 964271/tftp-deploy-4cjq8gop/kernel/uImage
305 02:17:15.933007 substitutions:
306 02:17:15.933416 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 02:17:15.933821 - {DTB_ADDR}: 0x01070000
308 02:17:15.934222 - {DTB}: 964271/tftp-deploy-4cjq8gop/dtb/meson-g12b-a311d-libretech-cc.dtb
309 02:17:15.934622 - {INITRD}: 964271/tftp-deploy-4cjq8gop/ramdisk/ramdisk.cpio.gz.uboot
310 02:17:15.935019 - {KERNEL_ADDR}: 0x01080000
311 02:17:15.935411 - {KERNEL}: 964271/tftp-deploy-4cjq8gop/kernel/uImage
312 02:17:15.935800 - {LAVA_MAC}: None
313 02:17:15.936268 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/964271/extract-nfsrootfs-gb3yb0qe
314 02:17:15.936674 - {NFS_SERVER_IP}: 192.168.6.2
315 02:17:15.937067 - {PRESEED_CONFIG}: None
316 02:17:15.937460 - {PRESEED_LOCAL}: None
317 02:17:15.937847 - {RAMDISK_ADDR}: 0x08000000
318 02:17:15.938233 - {RAMDISK}: 964271/tftp-deploy-4cjq8gop/ramdisk/ramdisk.cpio.gz.uboot
319 02:17:15.938623 - {ROOT_PART}: None
320 02:17:15.939010 - {ROOT}: None
321 02:17:15.939398 - {SERVER_IP}: 192.168.6.2
322 02:17:15.939786 - {TEE_ADDR}: 0x83000000
323 02:17:15.940207 - {TEE}: None
324 02:17:15.940598 Parsed boot commands:
325 02:17:15.940974 - setenv autoload no
326 02:17:15.941357 - setenv initrd_high 0xffffffff
327 02:17:15.941739 - setenv fdt_high 0xffffffff
328 02:17:15.942123 - dhcp
329 02:17:15.942505 - setenv serverip 192.168.6.2
330 02:17:15.942889 - tftpboot 0x01080000 964271/tftp-deploy-4cjq8gop/kernel/uImage
331 02:17:15.943281 - tftpboot 0x08000000 964271/tftp-deploy-4cjq8gop/ramdisk/ramdisk.cpio.gz.uboot
332 02:17:15.943670 - tftpboot 0x01070000 964271/tftp-deploy-4cjq8gop/dtb/meson-g12b-a311d-libretech-cc.dtb
333 02:17:15.944081 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/964271/extract-nfsrootfs-gb3yb0qe,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 02:17:15.944485 - bootm 0x01080000 0x08000000 0x01070000
335 02:17:15.944999 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 02:17:15.946514 start: 2.3 connect-device (timeout 00:05:00) [common]
338 02:17:15.946939 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 02:17:15.963395 Setting prompt string to ['lava-test: # ']
340 02:17:15.965065 end: 2.3 connect-device (duration 00:00:00) [common]
341 02:17:15.965738 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 02:17:15.966326 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 02:17:15.967062 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 02:17:15.968382 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 02:17:16.007094 >> OK - accepted request
346 02:17:16.009402 Returned 0 in 0 seconds
347 02:17:16.110622 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 02:17:16.112368 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 02:17:16.112926 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 02:17:16.113434 Setting prompt string to ['Hit any key to stop autoboot']
352 02:17:16.113879 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 02:17:16.115419 Trying 192.168.56.21...
354 02:17:16.115885 Connected to conserv1.
355 02:17:16.116323 Escape character is '^]'.
356 02:17:16.116735
357 02:17:16.117153 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 02:17:16.117576
359 02:17:28.294332 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 02:17:28.294739 bl2_stage_init 0x01
361 02:17:28.294966 bl2_stage_init 0x81
362 02:17:28.299873 hw id: 0x0000 - pwm id 0x01
363 02:17:28.300222 bl2_stage_init 0xc1
364 02:17:28.300459 bl2_stage_init 0x02
365 02:17:28.300676
366 02:17:28.305515 L0:00000000
367 02:17:28.305831 L1:20000703
368 02:17:28.306055 L2:00008067
369 02:17:28.306266 L3:14000000
370 02:17:28.311014 B2:00402000
371 02:17:28.311281 B1:e0f83180
372 02:17:28.311500
373 02:17:28.311709 TE: 58124
374 02:17:28.311913
375 02:17:28.316640 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 02:17:28.316905
377 02:17:28.317114 Board ID = 1
378 02:17:28.322206 Set A53 clk to 24M
379 02:17:28.322446 Set A73 clk to 24M
380 02:17:28.322645 Set clk81 to 24M
381 02:17:28.327886 A53 clk: 1200 MHz
382 02:17:28.328471 A73 clk: 1200 MHz
383 02:17:28.328919 CLK81: 166.6M
384 02:17:28.329361 smccc: 00012a91
385 02:17:28.333486 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 02:17:28.339151 board id: 1
387 02:17:28.344978 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 02:17:28.355761 fw parse done
389 02:17:28.361660 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 02:17:28.404322 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 02:17:28.415205 PIEI prepare done
392 02:17:28.415800 fastboot data load
393 02:17:28.416388 fastboot data verify
394 02:17:28.420886 verify result: 266
395 02:17:28.426491 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 02:17:28.427076 LPDDR4 probe
397 02:17:28.427551 ddr clk to 1584MHz
398 02:17:28.433523 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 02:17:28.471749
400 02:17:28.472409 dmc_version 0001
401 02:17:28.478375 Check phy result
402 02:17:28.484302 INFO : End of CA training
403 02:17:28.484871 INFO : End of initialization
404 02:17:28.489955 INFO : Training has run successfully!
405 02:17:28.490530 Check phy result
406 02:17:28.495459 INFO : End of initialization
407 02:17:28.496054 INFO : End of read enable training
408 02:17:28.501071 INFO : End of fine write leveling
409 02:17:28.506526 INFO : End of Write leveling coarse delay
410 02:17:28.506997 INFO : Training has run successfully!
411 02:17:28.507295 Check phy result
412 02:17:28.512173 INFO : End of initialization
413 02:17:28.512519 INFO : End of read dq deskew training
414 02:17:28.517797 INFO : End of MPR read delay center optimization
415 02:17:28.523335 INFO : End of write delay center optimization
416 02:17:28.528923 INFO : End of read delay center optimization
417 02:17:28.529288 INFO : End of max read latency training
418 02:17:28.534545 INFO : Training has run successfully!
419 02:17:28.534911 1D training succeed
420 02:17:28.543848 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 02:17:28.591287 Check phy result
422 02:17:28.591665 INFO : End of initialization
423 02:17:28.612997 INFO : End of 2D read delay Voltage center optimization
424 02:17:28.632588 INFO : End of 2D read delay Voltage center optimization
425 02:17:28.684584 INFO : End of 2D write delay Voltage center optimization
426 02:17:28.733989 INFO : End of 2D write delay Voltage center optimization
427 02:17:28.739494 INFO : Training has run successfully!
428 02:17:28.740106
429 02:17:28.740613 channel==0
430 02:17:28.744979 RxClkDly_Margin_A0==88 ps 9
431 02:17:28.745334 TxDqDly_Margin_A0==108 ps 11
432 02:17:28.750622 RxClkDly_Margin_A1==88 ps 9
433 02:17:28.750956 TxDqDly_Margin_A1==98 ps 10
434 02:17:28.751170 TrainedVREFDQ_A0==74
435 02:17:28.756229 TrainedVREFDQ_A1==75
436 02:17:28.756726 VrefDac_Margin_A0==25
437 02:17:28.761827 DeviceVref_Margin_A0==40
438 02:17:28.762321 VrefDac_Margin_A1==25
439 02:17:28.762752 DeviceVref_Margin_A1==39
440 02:17:28.763054
441 02:17:28.763328
442 02:17:28.767379 channel==1
443 02:17:28.767852 RxClkDly_Margin_A0==98 ps 10
444 02:17:28.768296 TxDqDly_Margin_A0==98 ps 10
445 02:17:28.772999 RxClkDly_Margin_A1==88 ps 9
446 02:17:28.773338 TxDqDly_Margin_A1==88 ps 9
447 02:17:28.778633 TrainedVREFDQ_A0==77
448 02:17:28.779124 TrainedVREFDQ_A1==77
449 02:17:28.779562 VrefDac_Margin_A0==23
450 02:17:28.784284 DeviceVref_Margin_A0==37
451 02:17:28.784898 VrefDac_Margin_A1==24
452 02:17:28.789796 DeviceVref_Margin_A1==37
453 02:17:28.790381
454 02:17:28.790928 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 02:17:28.795627
456 02:17:28.823497 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 02:17:28.824203 2D training succeed
458 02:17:28.828967 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 02:17:28.834661 auto size-- 65535DDR cs0 size: 2048MB
460 02:17:28.835047 DDR cs1 size: 2048MB
461 02:17:28.840300 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 02:17:28.840772 cs0 DataBus test pass
463 02:17:28.845847 cs1 DataBus test pass
464 02:17:28.846315 cs0 AddrBus test pass
465 02:17:28.846588 cs1 AddrBus test pass
466 02:17:28.846810
467 02:17:28.851354 100bdlr_step_size ps== 420
468 02:17:28.851809 result report
469 02:17:28.856942 boot times 0Enable ddr reg access
470 02:17:28.861443 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 02:17:28.874922 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 02:17:29.449613 0.0;M3 CHK:0;cm4_sp_mode 0
473 02:17:29.450024 MVN_1=0x00000000
474 02:17:29.455059 MVN_2=0x00000000
475 02:17:29.460826 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 02:17:29.461271 OPS=0x10
477 02:17:29.461538 ring efuse init
478 02:17:29.461757 chipver efuse init
479 02:17:29.466466 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 02:17:29.472133 [0.018961 Inits done]
481 02:17:29.472726 secure task start!
482 02:17:29.473214 high task start!
483 02:17:29.476747 low task start!
484 02:17:29.477384 run into bl31
485 02:17:29.483427 NOTICE: BL31: v1.3(release):4fc40b1
486 02:17:29.490403 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 02:17:29.490893 NOTICE: BL31: G12A normal boot!
488 02:17:29.518652 NOTICE: BL31: BL33 decompress pass
489 02:17:29.521552 ERROR: Error initializing runtime service opteed_fast
490 02:17:30.755207
491 02:17:30.755850
492 02:17:30.763596 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 02:17:30.764198
494 02:17:30.764712 Model: Libre Computer AML-A311D-CC Alta
495 02:17:30.972722 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 02:17:30.994504 DRAM: 2 GiB (effective 3.8 GiB)
497 02:17:31.138409 Core: 408 devices, 31 uclasses, devicetree: separate
498 02:17:31.144265 WDT: Not starting watchdog@f0d0
499 02:17:31.176426 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 02:17:31.188921 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 02:17:31.193275 ** Bad device specification mmc 0 **
502 02:17:31.204228 Card did not respond to voltage select! : -110
503 02:17:31.211892 ** Bad device specification mmc 0 **
504 02:17:31.212445 Couldn't find partition mmc 0
505 02:17:32.455175 Card did not respo� G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
506 02:17:32.456148 bl2_stage_init 0x01
507 02:17:32.456680 bl2_stage_init 0x81
508 02:17:32.460594 hw id: 0x0000 - pwm id 0x01
509 02:17:32.461110 bl2_stage_init 0xc1
510 02:17:32.461629 bl2_stage_init 0x02
511 02:17:32.462119
512 02:17:32.466293 L0:00000000
513 02:17:32.466799 L1:20000703
514 02:17:32.467301 L2:00008067
515 02:17:32.467790 L3:14000000
516 02:17:32.471883 B2:00402000
517 02:17:32.472419 B1:e0f83180
518 02:17:32.472909
519 02:17:32.473388 TE: 58167
520 02:17:32.473834
521 02:17:32.477472 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
522 02:17:32.477979
523 02:17:32.478466 Board ID = 1
524 02:17:32.483044 Set A53 clk to 24M
525 02:17:32.483550 Set A73 clk to 24M
526 02:17:32.484036 Set clk81 to 24M
527 02:17:32.488604 A53 clk: 1200 MHz
528 02:17:32.489132 A73 clk: 1200 MHz
529 02:17:32.489593 CLK81: 166.6M
530 02:17:32.490042 smccc: 00012abe
531 02:17:32.494178 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
532 02:17:32.499724 board id: 1
533 02:17:32.505616 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
534 02:17:32.516343 fw parse done
535 02:17:32.522266 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
536 02:17:32.564883 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
537 02:17:32.575747 PIEI prepare done
538 02:17:32.576332 fastboot data load
539 02:17:32.576797 fastboot data verify
540 02:17:32.581435 verify result: 266
541 02:17:32.587034 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
542 02:17:32.587523 LPDDR4 probe
543 02:17:32.588007 ddr clk to 1584MHz
544 02:17:32.595088 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
545 02:17:32.632826
546 02:17:32.633420 dmc_version 0001
547 02:17:32.639128 Check phy result
548 02:17:32.645013 INFO : End of CA training
549 02:17:32.645626 INFO : End of initialization
550 02:17:32.650498 INFO : Training has run successfully!
551 02:17:32.651084 Check phy result
552 02:17:32.656135 INFO : End of initialization
553 02:17:32.656760 INFO : End of read enable training
554 02:17:32.661648 INFO : End of fine write leveling
555 02:17:32.667364 INFO : End of Write leveling coarse delay
556 02:17:32.667950 INFO : Training has run successfully!
557 02:17:32.668466 Check phy result
558 02:17:32.672953 INFO : End of initialization
559 02:17:32.673537 INFO : End of read dq deskew training
560 02:17:32.678598 INFO : End of MPR read delay center optimization
561 02:17:32.684312 INFO : End of write delay center optimization
562 02:17:32.689761 INFO : End of read delay center optimization
563 02:17:32.690345 INFO : End of max read latency training
564 02:17:32.695357 INFO : Training has run successfully!
565 02:17:32.695959 1D training succeed
566 02:17:32.704719 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
567 02:17:32.752283 Check phy result
568 02:17:32.752912 INFO : End of initialization
569 02:17:32.773852 INFO : End of 2D read delay Voltage center optimization
570 02:17:32.793969 INFO : End of 2D read delay Voltage center optimization
571 02:17:32.845897 INFO : End of 2D write delay Voltage center optimization
572 02:17:32.895187 INFO : End of 2D write delay Voltage center optimization
573 02:17:32.900770 INFO : Training has run successfully!
574 02:17:32.901189
575 02:17:32.901402 channel==0
576 02:17:32.906351 RxClkDly_Margin_A0==88 ps 9
577 02:17:32.906792 TxDqDly_Margin_A0==98 ps 10
578 02:17:32.912010 RxClkDly_Margin_A1==88 ps 9
579 02:17:32.912455 TxDqDly_Margin_A1==88 ps 9
580 02:17:32.912714 TrainedVREFDQ_A0==74
581 02:17:32.917572 TrainedVREFDQ_A1==74
582 02:17:32.918224 VrefDac_Margin_A0==25
583 02:17:32.918712 DeviceVref_Margin_A0==40
584 02:17:32.922999 VrefDac_Margin_A1==23
585 02:17:32.923354 DeviceVref_Margin_A1==40
586 02:17:32.923828
587 02:17:32.924317
588 02:17:32.924772 channel==1
589 02:17:32.929903 RxClkDly_Margin_A0==98 ps 10
590 02:17:32.930348 TxDqDly_Margin_A0==88 ps 9
591 02:17:32.935260 RxClkDly_Margin_A1==88 ps 9
592 02:17:32.935893 TxDqDly_Margin_A1==88 ps 9
593 02:17:32.936427 TrainedVREFDQ_A0==77
594 02:17:32.940726 TrainedVREFDQ_A1==77
595 02:17:32.941338 VrefDac_Margin_A0==22
596 02:17:32.946445 DeviceVref_Margin_A0==37
597 02:17:32.947030 VrefDac_Margin_A1==24
598 02:17:32.947499 DeviceVref_Margin_A1==37
599 02:17:32.947953
600 02:17:32.952210 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
601 02:17:32.952738
602 02:17:32.983549 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
603 02:17:32.983924 2D training succeed
604 02:17:32.989231 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
605 02:17:32.994776 auto size-- 65535DDR cs0 size: 2048MB
606 02:17:32.995268 DDR cs1 size: 2048MB
607 02:17:33.000506 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
608 02:17:33.001052 cs0 DataBus test pass
609 02:17:33.005990 cs1 DataBus test pass
610 02:17:33.006515 cs0 AddrBus test pass
611 02:17:33.006980 cs1 AddrBus test pass
612 02:17:33.007438
613 02:17:33.011583 100bdlr_step_size ps== 420
614 02:17:33.012143 result report
615 02:17:33.017210 boot times 0Enable ddr reg access
616 02:17:33.023148 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
617 02:17:33.036582 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
618 02:17:33.608666 0.0;M3 CHK:0;cm4_sp_mode 0
619 02:17:33.609325 MVN_1=0x00000000
620 02:17:33.614146 MVN_2=0x00000000
621 02:17:33.619848 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
622 02:17:33.620447 OPS=0x10
623 02:17:33.620923 ring efuse init
624 02:17:33.621406 chipver efuse init
625 02:17:33.625455 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
626 02:17:33.631011 [0.018961 Inits done]
627 02:17:33.631512 secure task start!
628 02:17:33.631951 high task start!
629 02:17:33.635590 low task start!
630 02:17:33.636105 run into bl31
631 02:17:33.642219 NOTICE: BL31: v1.3(release):4fc40b1
632 02:17:33.650049 NOTICE: BL31: Built : 15:58:17, May 22 2019
633 02:17:33.650562 NOTICE: BL31: G12A normal boot!
634 02:17:33.675470 NOTICE: BL31: BL33 decompress pass
635 02:17:33.681073 ERROR: Error initializing runtime service opteed_fast
636 02:17:34.913966
637 02:17:34.914607
638 02:17:34.921431 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
639 02:17:34.921966
640 02:17:34.922436 Model: Libre Computer AML-A311D-CC Alta
641 02:17:35.130816 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
642 02:17:35.154141 DRAM: 2 GiB (effective 3.8 GiB)
643 02:17:35.297141 Core: 408 devices, 31 uclasses, devicetree: separate
644 02:17:35.303013 WDT: Not starting watchdog@f0d0
645 02:17:35.335290 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
646 02:17:35.347711 Loading Environment from FAT... Card did not respond to voltage select! : -110
647 02:17:35.352756 ** Bad device specification mmc 0 **
648 02:17:35.363015 Card did not respond to voltage select! : -110
649 02:17:35.370773 ** Bad device specification mmc 0 **
650 02:17:35.371280 Couldn't find partition mmc 0
651 02:17:35.379026 Card did not respond to voltage select! : -110
652 02:17:35.384705 ** Bad device specification mmc 0 **
653 02:17:35.385249 Couldn't find partition mmc 0
654 02:17:35.389607 Error: could not access storage.
655 02:17:35.732199 Net: eth0: ethernet@ff3f0000
656 02:17:35.732869 starting USB...
657 02:17:35.983970 Bus usb@ff500000: Register 3000140 NbrPorts 3
658 02:17:35.984667 Starting the controller
659 02:17:35.990459 USB XHCI 1.10
660 02:17:37.703753 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
661 02:17:37.704489 bl2_stage_init 0x81
662 02:17:37.709251 hw id: 0x0000 - pwm id 0x01
663 02:17:37.709785 bl2_stage_init 0xc1
664 02:17:37.710253 bl2_stage_init 0x02
665 02:17:37.710705
666 02:17:37.714832 L0:00000000
667 02:17:37.715361 L1:20000703
668 02:17:37.715821 L2:00008067
669 02:17:37.716312 L3:14000000
670 02:17:37.716765 B2:00402000
671 02:17:37.720473 B1:e0f83180
672 02:17:37.720996
673 02:17:37.721457 TE: 58150
674 02:17:37.721903
675 02:17:37.726085 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
676 02:17:37.726610
677 02:17:37.727068 Board ID = 1
678 02:17:37.731687 Set A53 clk to 24M
679 02:17:37.732251 Set A73 clk to 24M
680 02:17:37.732708 Set clk81 to 24M
681 02:17:37.737225 A53 clk: 1200 MHz
682 02:17:37.737757 A73 clk: 1200 MHz
683 02:17:37.738213 CLK81: 166.6M
684 02:17:37.738660 smccc: 00012aab
685 02:17:37.742828 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
686 02:17:37.748450 board id: 1
687 02:17:37.754205 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
688 02:17:37.764909 fw parse done
689 02:17:37.770903 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
690 02:17:37.813176 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
691 02:17:37.824405 PIEI prepare done
692 02:17:37.824959 fastboot data load
693 02:17:37.825427 fastboot data verify
694 02:17:37.830224 verify result: 266
695 02:17:37.835697 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
696 02:17:37.836284 LPDDR4 probe
697 02:17:37.836747 ddr clk to 1584MHz
698 02:17:37.843709 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
699 02:17:37.880913
700 02:17:37.881478 dmc_version 0001
701 02:17:37.887643 Check phy result
702 02:17:37.893518 INFO : End of CA training
703 02:17:37.894052 INFO : End of initialization
704 02:17:37.899114 INFO : Training has run successfully!
705 02:17:37.899640 Check phy result
706 02:17:37.904694 INFO : End of initialization
707 02:17:37.905212 INFO : End of read enable training
708 02:17:37.910478 INFO : End of fine write leveling
709 02:17:37.916020 INFO : End of Write leveling coarse delay
710 02:17:37.916555 INFO : Training has run successfully!
711 02:17:37.917011 Check phy result
712 02:17:37.921508 INFO : End of initialization
713 02:17:37.922029 INFO : End of read dq deskew training
714 02:17:37.927067 INFO : End of MPR read delay center optimization
715 02:17:37.932645 INFO : End of write delay center optimization
716 02:17:37.938350 INFO : End of read delay center optimization
717 02:17:37.938882 INFO : End of max read latency training
718 02:17:37.943874 INFO : Training has run successfully!
719 02:17:37.944433 1D training succeed
720 02:17:37.952999 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
721 02:17:38.000124 Check phy result
722 02:17:38.000731 INFO : End of initialization
723 02:17:38.022595 INFO : End of 2D read delay Voltage center optimization
724 02:17:38.042765 INFO : End of 2D read delay Voltage center optimization
725 02:17:38.094729 INFO : End of 2D write delay Voltage center optimization
726 02:17:38.144067 INFO : End of 2D write delay Voltage center optimization
727 02:17:38.149774 INFO : Training has run successfully!
728 02:17:38.150256
729 02:17:38.150682 channel==0
730 02:17:38.155206 RxClkDly_Margin_A0==88 ps 9
731 02:17:38.155689 TxDqDly_Margin_A0==98 ps 10
732 02:17:38.158815 RxClkDly_Margin_A1==88 ps 9
733 02:17:38.159275 TxDqDly_Margin_A1==88 ps 9
734 02:17:38.164042 TrainedVREFDQ_A0==74
735 02:17:38.164511 TrainedVREFDQ_A1==74
736 02:17:38.164929 VrefDac_Margin_A0==25
737 02:17:38.169552 DeviceVref_Margin_A0==40
738 02:17:38.170021 VrefDac_Margin_A1==25
739 02:17:38.175193 DeviceVref_Margin_A1==40
740 02:17:38.175664
741 02:17:38.176119
742 02:17:38.176537 channel==1
743 02:17:38.176933 RxClkDly_Margin_A0==98 ps 10
744 02:17:38.178720 TxDqDly_Margin_A0==98 ps 10
745 02:17:38.184274 RxClkDly_Margin_A1==98 ps 10
746 02:17:38.184728 TxDqDly_Margin_A1==88 ps 9
747 02:17:38.185147 TrainedVREFDQ_A0==77
748 02:17:38.190088 TrainedVREFDQ_A1==77
749 02:17:38.190415 VrefDac_Margin_A0==22
750 02:17:38.195575 DeviceVref_Margin_A0==37
751 02:17:38.195873 VrefDac_Margin_A1==22
752 02:17:38.196149 DeviceVref_Margin_A1==37
753 02:17:38.196393
754 02:17:38.204716 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
755 02:17:38.205063
756 02:17:38.232646 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
757 02:17:38.233190 2D training succeed
758 02:17:38.243868 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
759 02:17:38.244491 auto size-- 65535DDR cs0 size: 2048MB
760 02:17:38.244941 DDR cs1 size: 2048MB
761 02:17:38.249657 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
762 02:17:38.250129 cs0 DataBus test pass
763 02:17:38.255091 cs1 DataBus test pass
764 02:17:38.255547 cs0 AddrBus test pass
765 02:17:38.260596 cs1 AddrBus test pass
766 02:17:38.261065
767 02:17:38.261469 100bdlr_step_size ps== 420
768 02:17:38.261873 result report
769 02:17:38.266245 boot times 0Enable ddr reg access
770 02:17:38.272595 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
771 02:17:38.286085 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
772 02:17:38.859612 0.0;M3 CHK:0;cm4_sp_mode 0
773 02:17:38.860295 MVN_1=0x00000000
774 02:17:38.865175 MVN_2=0x00000000
775 02:17:38.871085 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
776 02:17:38.871623 OPS=0x10
777 02:17:38.872063 ring efuse init
778 02:17:38.872463 chipver efuse init
779 02:17:38.876446 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
780 02:17:38.882145 [0.018960 Inits done]
781 02:17:38.882579 secure task start!
782 02:17:38.882979 high task start!
783 02:17:38.886615 low task start!
784 02:17:38.887054 run into bl31
785 02:17:38.893300 NOTICE: BL31: v1.3(release):4fc40b1
786 02:17:38.900634 NOTICE: BL31: Built : 15:58:17, May 22 2019
787 02:17:38.901087 NOTICE: BL31: G12A normal boot!
788 02:17:38.928185 NOTICE: BL31: BL33 decompress pass
789 02:17:38.932774 ERROR: Error initializing runtime service opteed_fast
790 02:17:40.165724
791 02:17:40.166358
792 02:17:40.173949 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
793 02:17:40.174417
794 02:17:40.174834 Model: Libre Computer AML-A311D-CC Alta
795 02:17:40.382700 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
796 02:17:40.405821 DRAM: 2 GiB (effective 3.8 GiB)
797 02:17:40.548846 Core: 408 devices, 31 uclasses, devicetree: separate
798 02:17:40.554731 WDT: Not starting watchdog@f0d0
799 02:17:40.586965 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
800 02:17:40.599373 Loading Environment from FAT... Card did not respond to voltage select! : -110
801 02:17:40.604258 ** Bad device specification mmc 0 **
802 02:17:40.614605 Card did not respond to voltage select! : -110
803 02:17:40.622325 ** Bad device specification mmc 0 **
804 02:17:40.622792 Couldn't find partition mmc 0
805 02:17:40.630640 Card did not respond to voltage select! : -110
806 02:17:40.636190 ** Bad device specification mmc 0 **
807 02:17:40.636637 Couldn't find partition mmc 0
808 02:17:40.641200 Error: could not access storage.
809 02:17:40.983745 Net: eth0: ethernet@ff3f0000
810 02:17:40.984365 starting USB...
811 02:17:41.235666 Bus usb@ff500000: Register 3000140 NbrPorts 3
812 02:17:41.236300 Starting the controller
813 02:17:41.242565 USB XHCI 1.10
814 02:17:43.403821 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
815 02:17:43.404310 bl2_stage_init 0x01
816 02:17:43.404546 bl2_stage_init 0x81
817 02:17:43.409353 hw id: 0x0000 - pwm id 0x01
818 02:17:43.409665 bl2_stage_init 0xc1
819 02:17:43.409890 bl2_stage_init 0x02
820 02:17:43.410121
821 02:17:43.414923 L0:00000000
822 02:17:43.415384 L1:20000703
823 02:17:43.415728 L2:00008067
824 02:17:43.416107 L3:14000000
825 02:17:43.420419 B2:00402000
826 02:17:43.420714 B1:e0f83180
827 02:17:43.420928
828 02:17:43.421137 TE: 58159
829 02:17:43.421347
830 02:17:43.426077 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
831 02:17:43.426363
832 02:17:43.426595 Board ID = 1
833 02:17:43.431663 Set A53 clk to 24M
834 02:17:43.431959 Set A73 clk to 24M
835 02:17:43.432219 Set clk81 to 24M
836 02:17:43.437295 A53 clk: 1200 MHz
837 02:17:43.437588 A73 clk: 1200 MHz
838 02:17:43.437804 CLK81: 166.6M
839 02:17:43.438010 smccc: 00012ab5
840 02:17:43.442865 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
841 02:17:43.448473 board id: 1
842 02:17:43.454449 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
843 02:17:43.465120 fw parse done
844 02:17:43.471034 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
845 02:17:43.512641 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
846 02:17:43.524483 PIEI prepare done
847 02:17:43.524840 fastboot data load
848 02:17:43.525065 fastboot data verify
849 02:17:43.530123 verify result: 266
850 02:17:43.535748 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
851 02:17:43.536255 LPDDR4 probe
852 02:17:43.536612 ddr clk to 1584MHz
853 02:17:43.543789 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
854 02:17:43.581087
855 02:17:43.581486 dmc_version 0001
856 02:17:43.587616 Check phy result
857 02:17:43.593462 INFO : End of CA training
858 02:17:43.593981 INFO : End of initialization
859 02:17:43.599006 INFO : Training has run successfully!
860 02:17:43.599522 Check phy result
861 02:17:43.604615 INFO : End of initialization
862 02:17:43.605134 INFO : End of read enable training
863 02:17:43.610337 INFO : End of fine write leveling
864 02:17:43.615941 INFO : End of Write leveling coarse delay
865 02:17:43.616486 INFO : Training has run successfully!
866 02:17:43.616955 Check phy result
867 02:17:43.621558 INFO : End of initialization
868 02:17:43.622061 INFO : End of read dq deskew training
869 02:17:43.627054 INFO : End of MPR read delay center optimization
870 02:17:43.632655 INFO : End of write delay center optimization
871 02:17:43.638341 INFO : End of read delay center optimization
872 02:17:43.638846 INFO : End of max read latency training
873 02:17:43.643962 INFO : Training has run successfully!
874 02:17:43.644516 1D training succeed
875 02:17:43.653160 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
876 02:17:43.700764 Check phy result
877 02:17:43.701293 INFO : End of initialization
878 02:17:43.722316 INFO : End of 2D read delay Voltage center optimization
879 02:17:43.743278 INFO : End of 2D read delay Voltage center optimization
880 02:17:43.795213 INFO : End of 2D write delay Voltage center optimization
881 02:17:43.844515 INFO : End of 2D write delay Voltage center optimization
882 02:17:43.850076 INFO : Training has run successfully!
883 02:17:43.850638
884 02:17:43.851116 channel==0
885 02:17:43.855591 RxClkDly_Margin_A0==88 ps 9
886 02:17:43.856166 TxDqDly_Margin_A0==98 ps 10
887 02:17:43.861172 RxClkDly_Margin_A1==88 ps 9
888 02:17:43.861685 TxDqDly_Margin_A1==98 ps 10
889 02:17:43.862177 TrainedVREFDQ_A0==74
890 02:17:43.866794 TrainedVREFDQ_A1==74
891 02:17:43.867380 VrefDac_Margin_A0==24
892 02:17:43.867852 DeviceVref_Margin_A0==40
893 02:17:43.872384 VrefDac_Margin_A1==24
894 02:17:43.872978 DeviceVref_Margin_A1==40
895 02:17:43.873422
896 02:17:43.873855
897 02:17:43.878028 channel==1
898 02:17:43.878523 RxClkDly_Margin_A0==98 ps 10
899 02:17:43.878961 TxDqDly_Margin_A0==98 ps 10
900 02:17:43.883578 RxClkDly_Margin_A1==98 ps 10
901 02:17:43.884096 TxDqDly_Margin_A1==88 ps 9
902 02:17:43.889187 TrainedVREFDQ_A0==77
903 02:17:43.889705 TrainedVREFDQ_A1==77
904 02:17:43.890145 VrefDac_Margin_A0==22
905 02:17:43.894813 DeviceVref_Margin_A0==37
906 02:17:43.895303 VrefDac_Margin_A1==22
907 02:17:43.900431 DeviceVref_Margin_A1==37
908 02:17:43.900917
909 02:17:43.901347 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
910 02:17:43.906087
911 02:17:43.933925 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
912 02:17:43.934458 2D training succeed
913 02:17:43.939436 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
914 02:17:43.945089 auto size-- 65535DDR cs0 size: 2048MB
915 02:17:43.945586 DDR cs1 size: 2048MB
916 02:17:43.950722 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
917 02:17:43.951211 cs0 DataBus test pass
918 02:17:43.956361 cs1 DataBus test pass
919 02:17:43.956839 cs0 AddrBus test pass
920 02:17:43.957271 cs1 AddrBus test pass
921 02:17:43.957695
922 02:17:43.961964 100bdlr_step_size ps== 420
923 02:17:43.962450 result report
924 02:17:43.967525 boot times 0Enable ddr reg access
925 02:17:43.973079 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
926 02:17:43.986357 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
927 02:17:44.558366 0.0;M3 CHK:0;cm4_sp_mode 0
928 02:17:44.558806 MVN_1=0x00000000
929 02:17:44.563936 MVN_2=0x00000000
930 02:17:44.569601 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
931 02:17:44.570144 OPS=0x10
932 02:17:44.570502 ring efuse init
933 02:17:44.570805 chipver efuse init
934 02:17:44.575161 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
935 02:17:44.580774 [0.018961 Inits done]
936 02:17:44.581074 secure task start!
937 02:17:44.581291 high task start!
938 02:17:44.585294 low task start!
939 02:17:44.585590 run into bl31
940 02:17:44.591966 NOTICE: BL31: v1.3(release):4fc40b1
941 02:17:44.599779 NOTICE: BL31: Built : 15:58:17, May 22 2019
942 02:17:44.600092 NOTICE: BL31: G12A normal boot!
943 02:17:44.625248 NOTICE: BL31: BL33 decompress pass
944 02:17:44.630902 ERROR: Error initializing runtime service opteed_fast
945 02:17:45.863829
946 02:17:45.864537
947 02:17:45.872248 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
948 02:17:45.873049
949 02:17:45.873591 Model: Libre Computer AML-A311D-CC Alta
950 02:17:46.080653 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
951 02:17:46.104022 DRAM: 2 GiB (effective 3.8 GiB)
952 02:17:46.247042 Core: 408 devices, 31 uclasses, devicetree: separate
953 02:17:46.252192 WDT: Not starting watchdog@f0d0
954 02:17:46.285103 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
955 02:17:46.297551 Loading Environment from FAT... Card did not respond to voltage select! : -110
956 02:17:46.302469 ** Bad device specification mmc 0 **
957 02:17:46.312872 Card did not respond to voltage select! : -110
958 02:17:46.320466 ** Bad device specification mmc 0 **
959 02:17:46.321000 Couldn't find partition mmc 0
960 02:17:46.328822 Card did not respond to voltage select! : -110
961 02:17:46.334363 ** Bad device specification mmc 0 **
962 02:17:46.334875 Couldn't find partition mmc 0
963 02:17:46.339412 Error: could not access storage.
964 02:17:46.682976 Net: eth0: ethernet@ff3f0000
965 02:17:46.683645 starting USB...
966 02:17:46.934812 Bus usb@ff500000: Register 3000140 NbrPorts 3
967 02:17:46.935480 Starting the controller
968 02:17:46.941672 USB XHCI 1.10
969 02:17:48.803675 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
970 02:17:48.804411 bl2_stage_init 0x01
971 02:17:48.804891 bl2_stage_init 0x81
972 02:17:48.809303 hw id: 0x0000 - pwm id 0x01
973 02:17:48.809804 bl2_stage_init 0xc1
974 02:17:48.810264 bl2_stage_init 0x02
975 02:17:48.810714
976 02:17:48.814805 L0:00000000
977 02:17:48.815293 L1:20000703
978 02:17:48.815743 L2:00008067
979 02:17:48.816234 L3:14000000
980 02:17:48.820396 B2:00402000
981 02:17:48.820882 B1:e0f83180
982 02:17:48.821330
983 02:17:48.821775 TE: 58159
984 02:17:48.822215
985 02:17:48.825994 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
986 02:17:48.826485
987 02:17:48.826933 Board ID = 1
988 02:17:48.831651 Set A53 clk to 24M
989 02:17:48.832166 Set A73 clk to 24M
990 02:17:48.832618 Set clk81 to 24M
991 02:17:48.837188 A53 clk: 1200 MHz
992 02:17:48.837669 A73 clk: 1200 MHz
993 02:17:48.838111 CLK81: 166.6M
994 02:17:48.838544 smccc: 00012ab4
995 02:17:48.842784 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
996 02:17:48.848567 board id: 1
997 02:17:48.854248 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
998 02:17:48.864951 fw parse done
999 02:17:48.870911 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1000 02:17:48.913706 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1001 02:17:48.924727 PIEI prepare done
1002 02:17:48.925207 fastboot data load
1003 02:17:48.925644 fastboot data verify
1004 02:17:48.930213 verify result: 266
1005 02:17:48.935819 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1006 02:17:48.936330 LPDDR4 probe
1007 02:17:48.936757 ddr clk to 1584MHz
1008 02:17:48.943862 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1009 02:17:48.981125
1010 02:17:48.981610 dmc_version 0001
1011 02:17:48.987866 Check phy result
1012 02:17:48.993584 INFO : End of CA training
1013 02:17:48.994046 INFO : End of initialization
1014 02:17:48.999216 INFO : Training has run successfully!
1015 02:17:48.999754 Check phy result
1016 02:17:49.004813 INFO : End of initialization
1017 02:17:49.005307 INFO : End of read enable training
1018 02:17:49.008180 INFO : End of fine write leveling
1019 02:17:49.013752 INFO : End of Write leveling coarse delay
1020 02:17:49.019411 INFO : Training has run successfully!
1021 02:17:49.019906 Check phy result
1022 02:17:49.020404 INFO : End of initialization
1023 02:17:49.024904 INFO : End of read dq deskew training
1024 02:17:49.030457 INFO : End of MPR read delay center optimization
1025 02:17:49.030959 INFO : End of write delay center optimization
1026 02:17:49.036153 INFO : End of read delay center optimization
1027 02:17:49.041719 INFO : End of max read latency training
1028 02:17:49.042198 INFO : Training has run successfully!
1029 02:17:49.047216 1D training succeed
1030 02:17:49.052373 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1031 02:17:49.099951 Check phy result
1032 02:17:49.100576 INFO : End of initialization
1033 02:17:49.123293 INFO : End of 2D read delay Voltage center optimization
1034 02:17:49.142953 INFO : End of 2D read delay Voltage center optimization
1035 02:17:49.195293 INFO : End of 2D write delay Voltage center optimization
1036 02:17:49.244580 INFO : End of 2D write delay Voltage center optimization
1037 02:17:49.250299 INFO : Training has run successfully!
1038 02:17:49.250856
1039 02:17:49.251319 channel==0
1040 02:17:49.255673 RxClkDly_Margin_A0==88 ps 9
1041 02:17:49.256224 TxDqDly_Margin_A0==98 ps 10
1042 02:17:49.258948 RxClkDly_Margin_A1==88 ps 9
1043 02:17:49.259426 TxDqDly_Margin_A1==88 ps 9
1044 02:17:49.264475 TrainedVREFDQ_A0==74
1045 02:17:49.264985 TrainedVREFDQ_A1==74
1046 02:17:49.265442 VrefDac_Margin_A0==24
1047 02:17:49.270307 DeviceVref_Margin_A0==40
1048 02:17:49.270818 VrefDac_Margin_A1==25
1049 02:17:49.275760 DeviceVref_Margin_A1==40
1050 02:17:49.276292
1051 02:17:49.276745
1052 02:17:49.277186 channel==1
1053 02:17:49.277628 RxClkDly_Margin_A0==98 ps 10
1054 02:17:49.281376 TxDqDly_Margin_A0==88 ps 9
1055 02:17:49.281896 RxClkDly_Margin_A1==88 ps 9
1056 02:17:49.286948 TxDqDly_Margin_A1==88 ps 9
1057 02:17:49.287465 TrainedVREFDQ_A0==77
1058 02:17:49.287919 TrainedVREFDQ_A1==77
1059 02:17:49.292589 VrefDac_Margin_A0==22
1060 02:17:49.293093 DeviceVref_Margin_A0==37
1061 02:17:49.298102 VrefDac_Margin_A1==24
1062 02:17:49.298609 DeviceVref_Margin_A1==37
1063 02:17:49.299058
1064 02:17:49.303855 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1065 02:17:49.304398
1066 02:17:49.331815 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1067 02:17:49.337392 2D training succeed
1068 02:17:49.342867 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1069 02:17:49.343380 auto size-- 65535DDR cs0 size: 2048MB
1070 02:17:49.348499 DDR cs1 size: 2048MB
1071 02:17:49.349015 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1072 02:17:49.354113 cs0 DataBus test pass
1073 02:17:49.354625 cs1 DataBus test pass
1074 02:17:49.355079 cs0 AddrBus test pass
1075 02:17:49.359715 cs1 AddrBus test pass
1076 02:17:49.360268
1077 02:17:49.360725 100bdlr_step_size ps== 420
1078 02:17:49.361177 result report
1079 02:17:49.365389 boot times 0Enable ddr reg access
1080 02:17:49.372837 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1081 02:17:49.386226 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1082 02:17:49.958162 0.0;M3 CHK:0;cm4_sp_mode 0
1083 02:17:49.958800 MVN_1=0x00000000
1084 02:17:49.963789 MVN_2=0x00000000
1085 02:17:49.969520 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1086 02:17:49.970088 OPS=0x10
1087 02:17:49.970563 ring efuse init
1088 02:17:49.971017 chipver efuse init
1089 02:17:49.975062 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1090 02:17:49.980837 [0.018960 Inits done]
1091 02:17:49.981450 secure task start!
1092 02:17:49.981920 high task start!
1093 02:17:49.985281 low task start!
1094 02:17:49.986146 run into bl31
1095 02:17:49.992006 NOTICE: BL31: v1.3(release):4fc40b1
1096 02:17:49.998767 NOTICE: BL31: Built : 15:58:17, May 22 2019
1097 02:17:49.999642 NOTICE: BL31: G12A normal boot!
1098 02:17:50.025952 NOTICE: BL31: BL33 decompress pass
1099 02:17:50.030351 ERROR: Error initializing runtime service opteed_fast
1100 02:17:51.264162
1101 02:17:51.264844
1102 02:17:51.272571 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1103 02:17:51.273111
1104 02:17:51.273576 Model: Libre Computer AML-A311D-CC Alta
1105 02:17:51.481013 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1106 02:17:51.504414 DRAM: 2 GiB (effective 3.8 GiB)
1107 02:17:51.647352 Core: 408 devices, 31 uclasses, devicetree: separate
1108 02:17:51.653309 WDT: Not starting watchdog@f0d0
1109 02:17:51.685504 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1110 02:17:51.697949 Loading Environment from FAT... Card did not respond to voltage select! : -110
1111 02:17:51.703075 ** Bad device specification mmc 0 **
1112 02:17:51.713269 Card did not respond to voltage select! : -110
1113 02:17:51.720947 ** Bad device specification mmc 0 **
1114 02:17:51.721464 Couldn't find partition mmc 0
1115 02:17:51.729284 Card did not respond to voltage select! : -110
1116 02:17:51.734775 ** Bad device specification mmc 0 **
1117 02:17:51.735292 Couldn't find partition mmc 0
1118 02:17:51.739829 Error: could not access storage.
1119 02:17:52.083340 Net: eth0: ethernet@ff3f0000
1120 02:17:52.084045 starting USB...
1121 02:17:52.335173 Bus usb@ff500000: Register 3000140 NbrPorts 3
1122 02:17:52.335783 Starting the controller
1123 02:17:52.341245 USB XHCI 1.10
1124 02:17:53.899196 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1125 02:17:53.907630 scanning usb for storage devices... 0 Storage Device(s) found
1127 02:17:53.959428 Hit any key to stop autoboot: 1
1128 02:17:53.960415 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1129 02:17:53.961094 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1130 02:17:53.961658 Setting prompt string to ['=>']
1131 02:17:53.962183 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1132 02:17:53.975041 0
1133 02:17:53.976032 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1134 02:17:53.976582 Sending with 10 millisecond of delay
1136 02:17:55.111724 => setenv autoload no
1137 02:17:55.122619 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1138 02:17:55.128020 setenv autoload no
1139 02:17:55.128816 Sending with 10 millisecond of delay
1141 02:17:56.926167 => setenv initrd_high 0xffffffff
1142 02:17:56.936998 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1143 02:17:56.937930 setenv initrd_high 0xffffffff
1144 02:17:56.938699 Sending with 10 millisecond of delay
1146 02:17:58.556104 => setenv fdt_high 0xffffffff
1147 02:17:58.566909 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1148 02:17:58.567754 setenv fdt_high 0xffffffff
1149 02:17:58.568530 Sending with 10 millisecond of delay
1151 02:17:58.860360 => dhcp
1152 02:17:58.871124 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1153 02:17:58.871970 dhcp
1154 02:17:58.872482 Speed: 1000, full duplex
1155 02:17:58.872897 BOOTP broadcast 1
1156 02:17:58.880244 DHCP client bound to address 192.168.6.27 (9 ms)
1157 02:17:58.880951 Sending with 10 millisecond of delay
1159 02:18:00.557787 => setenv serverip 192.168.6.2
1160 02:18:00.568641 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1161 02:18:00.569219 setenv serverip 192.168.6.2
1162 02:18:00.569704 Sending with 10 millisecond of delay
1164 02:18:04.293562 => tftpboot 0x01080000 964271/tftp-deploy-4cjq8gop/kernel/uImage
1165 02:18:04.304299 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1166 02:18:04.305044 tftpboot 0x01080000 964271/tftp-deploy-4cjq8gop/kernel/uImage
1167 02:18:04.305397 Speed: 1000, full duplex
1168 02:18:04.305746 Using ethernet@ff3f0000 device
1169 02:18:04.306937 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1170 02:18:04.312637 Filename '964271/tftp-deploy-4cjq8gop/kernel/uImage'.
1171 02:18:04.316376 Load address: 0x1080000
1172 02:18:07.487353 Loading: *################################################## 43.6 MiB
1173 02:18:07.488039 13.7 MiB/s
1174 02:18:07.488504 done
1175 02:18:07.490738 Bytes transferred = 45713984 (2b98a40 hex)
1176 02:18:07.491498 Sending with 10 millisecond of delay
1178 02:18:12.179365 => tftpboot 0x08000000 964271/tftp-deploy-4cjq8gop/ramdisk/ramdisk.cpio.gz.uboot
1179 02:18:12.190256 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1180 02:18:12.191165 tftpboot 0x08000000 964271/tftp-deploy-4cjq8gop/ramdisk/ramdisk.cpio.gz.uboot
1181 02:18:12.191663 Speed: 1000, full duplex
1182 02:18:12.192161 Using ethernet@ff3f0000 device
1183 02:18:12.193377 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1184 02:18:12.201823 Filename '964271/tftp-deploy-4cjq8gop/ramdisk/ramdisk.cpio.gz.uboot'.
1185 02:18:12.202375 Load address: 0x8000000
1186 02:18:18.992972 Loading: *###########T ####################################### 22.3 MiB
1187 02:18:18.993617 3.3 MiB/s
1188 02:18:18.994095 done
1189 02:18:18.997301 Bytes transferred = 23432100 (1658ba4 hex)
1190 02:18:18.998098 Sending with 10 millisecond of delay
1192 02:18:24.172175 => tftpboot 0x01070000 964271/tftp-deploy-4cjq8gop/dtb/meson-g12b-a311d-libretech-cc.dtb
1193 02:18:24.182985 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:52)
1194 02:18:24.183816 tftpboot 0x01070000 964271/tftp-deploy-4cjq8gop/dtb/meson-g12b-a311d-libretech-cc.dtb
1195 02:18:24.184349 Speed: 1000, full duplex
1196 02:18:24.184798 Using ethernet@ff3f0000 device
1197 02:18:24.187794 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1198 02:18:24.195279 Filename '964271/tftp-deploy-4cjq8gop/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1199 02:18:24.206762 Load address: 0x1070000
1200 02:18:24.214856 Loading: *################################################## 53.4 KiB
1201 02:18:24.222261 2.9 MiB/s
1202 02:18:24.222805 done
1203 02:18:24.223258 Bytes transferred = 54703 (d5af hex)
1204 02:18:24.224008 Sending with 10 millisecond of delay
1206 02:18:37.526587 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/964271/extract-nfsrootfs-gb3yb0qe,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1207 02:18:37.537453 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:38)
1208 02:18:37.538417 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/964271/extract-nfsrootfs-gb3yb0qe,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1209 02:18:37.539190 Sending with 10 millisecond of delay
1211 02:18:39.878471 => bootm 0x01080000 0x08000000 0x01070000
1212 02:18:39.889318 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1213 02:18:39.889930 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:36)
1214 02:18:39.891041 bootm 0x01080000 0x08000000 0x01070000
1215 02:18:39.891552 ## Booting kernel from Legacy Image at 01080000 ...
1216 02:18:39.893890 Image Name:
1217 02:18:39.899432 Image Type: AArch64 Linux Kernel Image (uncompressed)
1218 02:18:39.899962 Data Size: 45713920 Bytes = 43.6 MiB
1219 02:18:39.904870 Load Address: 01080000
1220 02:18:39.905348 Entry Point: 01080000
1221 02:18:40.100254 Verifying Checksum ... OK
1222 02:18:40.100864 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1223 02:18:40.105600 Image Name:
1224 02:18:40.111112 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1225 02:18:40.111591 Data Size: 23432036 Bytes = 22.3 MiB
1226 02:18:40.113382 Load Address: 00000000
1227 02:18:40.119733 Entry Point: 00000000
1228 02:18:40.218862 Verifying Checksum ... OK
1229 02:18:40.219414 ## Flattened Device Tree blob at 01070000
1230 02:18:40.224293 Booting using the fdt blob at 0x1070000
1231 02:18:40.224779 Working FDT set to 1070000
1232 02:18:40.228727 Loading Kernel Image
1233 02:18:40.379753 Loading Ramdisk to 7e9a7000, end 7ffffb64 ... OK
1234 02:18:40.385367 Loading Device Tree to 000000007e996000, end 000000007e9a65ae ... OK
1235 02:18:40.385857 Working FDT set to 7e996000
1236 02:18:40.390328
1237 02:18:40.390822 Starting kernel ...
1238 02:18:40.391275
1239 02:18:40.392242 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1240 02:18:40.392895 start: 2.4.4 auto-login-action (timeout 00:03:36) [common]
1241 02:18:40.393407 Setting prompt string to ['Linux version [0-9]']
1242 02:18:40.393909 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1243 02:18:40.394420 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1244 02:18:40.428201 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1245 02:18:40.429263 start: 2.4.4.1 login-action (timeout 00:03:36) [common]
1246 02:18:40.429828 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1247 02:18:40.430334 Setting prompt string to []
1248 02:18:40.430863 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1249 02:18:40.431360 Using line separator: #'\n'#
1250 02:18:40.431808 No login prompt set.
1251 02:18:40.432336 Parsing kernel messages
1252 02:18:40.432779 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1253 02:18:40.433651 [login-action] Waiting for messages, (timeout 00:03:35)
1254 02:18:40.434152 Waiting using forced prompt support (timeout 00:01:48)
1255 02:18:40.448242 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j370460-arm64-gcc-12-defconfig-hbf6r) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Sat Nov 9 01:39:14 UTC 2024
1256 02:18:40.448806 [ 0.000000] KASLR disabled due to lack of seed
1257 02:18:40.453738 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1258 02:18:40.457317 [ 0.000000] efi: UEFI not found.
1259 02:18:40.468279 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1260 02:18:40.473812 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1261 02:18:40.484916 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1262 02:18:40.490357 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1263 02:18:40.501407 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1264 02:18:40.512503 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1265 02:18:40.517956 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1266 02:18:40.523506 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1267 02:18:40.534666 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1268 02:18:40.540090 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1269 02:18:40.540584 [ 0.000000] Zone ranges:
1270 02:18:40.545638 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1271 02:18:40.551131 [ 0.000000] DMA32 empty
1272 02:18:40.551605 [ 0.000000] Normal empty
1273 02:18:40.556625 [ 0.000000] Movable zone start for each node
1274 02:18:40.562169 [ 0.000000] Early memory node ranges
1275 02:18:40.567651 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1276 02:18:40.573114 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1277 02:18:40.578669 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1278 02:18:40.585745 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1279 02:18:40.610083 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1280 02:18:40.615646 [ 0.000000] psci: probing for conduit method from DT.
1281 02:18:40.616163 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1282 02:18:40.624663 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1283 02:18:40.630058 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1284 02:18:40.630543 [ 0.000000] psci: SMC Calling Convention v1.1
1285 02:18:40.635620 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1286 02:18:40.641125 [ 0.000000] Detected VIPT I-cache on CPU0
1287 02:18:40.646623 [ 0.000000] CPU features: detected: ARM erratum 845719
1288 02:18:40.652152 [ 0.000000] alternatives: applying boot alternatives
1289 02:18:40.674199 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/964271/extract-nfsrootfs-gb3yb0qe,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1290 02:18:40.679731 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1291 02:18:40.690770 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1292 02:18:40.691269 <6>[ 0.000000] Fallback order for Node 0: 0
1293 02:18:40.701780 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1294 02:18:40.702260 <6>[ 0.000000] Policy zone: DMA
1295 02:18:40.712862 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1296 02:18:40.718410 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1297 02:18:40.718902 <6>[ 0.000000] software IO TLB: area num 8.
1298 02:18:40.729426 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1299 02:18:40.776181 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1300 02:18:40.781667 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1301 02:18:40.785191 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1302 02:18:40.790711 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1303 02:18:40.796205 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1304 02:18:40.801751 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1305 02:18:40.812804 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1306 02:18:40.818348 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1307 02:18:40.823870 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1308 02:18:40.834876 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1309 02:18:40.840412 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1310 02:18:40.845898 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1311 02:18:40.851414 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1312 02:18:40.857776 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1313 02:18:40.870413 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1314 02:18:40.881466 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1315 02:18:40.886989 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1316 02:18:40.892498 <6>[ 0.008798] Console: colour dummy device 80x25
1317 02:18:40.903547 <6>[ 0.012936] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1318 02:18:40.909030 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1319 02:18:40.914671 <6>[ 0.028189] LSM: initializing lsm=capability
1320 02:18:40.920166 <6>[ 0.032728] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1321 02:18:40.925656 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1322 02:18:40.931100 <6>[ 0.052297] rcu: Hierarchical SRCU implementation.
1323 02:18:40.936659 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1324 02:18:40.947658 <6>[ 0.058876] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1325 02:18:40.956182 <6>[ 0.071616] EFI services will not be available.
1326 02:18:40.956664 <6>[ 0.075261] smp: Bringing up secondary CPUs ...
1327 02:18:40.968416 <6>[ 0.077131] Detected VIPT I-cache on CPU1
1328 02:18:40.973862 <6>[ 0.077250] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1329 02:18:40.979385 <6>[ 0.078578] CPU features: detected: Spectre-v2
1330 02:18:40.984898 <6>[ 0.078593] CPU features: detected: Spectre-v4
1331 02:18:40.990492 <6>[ 0.078599] CPU features: detected: Spectre-BHB
1332 02:18:40.996011 <6>[ 0.078604] CPU features: detected: ARM erratum 858921
1333 02:18:41.001461 <6>[ 0.078612] Detected VIPT I-cache on CPU2
1334 02:18:41.007025 <6>[ 0.078685] arch_timer: Enabling local workaround for ARM erratum 858921
1335 02:18:41.012668 <6>[ 0.078702] arch_timer: CPU2: Trapping CNTVCT access
1336 02:18:41.018069 <6>[ 0.078712] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1337 02:18:41.023654 <6>[ 0.083532] Detected VIPT I-cache on CPU3
1338 02:18:41.029067 <6>[ 0.083578] arch_timer: Enabling local workaround for ARM erratum 858921
1339 02:18:41.034707 <6>[ 0.083588] arch_timer: CPU3: Trapping CNTVCT access
1340 02:18:41.040142 <6>[ 0.083595] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1341 02:18:41.045657 <6>[ 0.087649] Detected VIPT I-cache on CPU4
1342 02:18:41.051152 <6>[ 0.087695] arch_timer: Enabling local workaround for ARM erratum 858921
1343 02:18:41.056702 <6>[ 0.087705] arch_timer: CPU4: Trapping CNTVCT access
1344 02:18:41.067730 <6>[ 0.087712] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1345 02:18:41.068250 <6>[ 0.091644] Detected VIPT I-cache on CPU5
1346 02:18:41.078743 <6>[ 0.091691] arch_timer: Enabling local workaround for ARM erratum 858921
1347 02:18:41.079224 <6>[ 0.091701] arch_timer: CPU5: Trapping CNTVCT access
1348 02:18:41.089826 <6>[ 0.091708] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1349 02:18:41.090308 <6>[ 0.091820] smp: Brought up 1 node, 6 CPUs
1350 02:18:41.095319 <6>[ 0.213047] SMP: Total of 6 processors activated.
1351 02:18:41.100835 <6>[ 0.217951] CPU: All CPU(s) started at EL2
1352 02:18:41.106425 <6>[ 0.222302] CPU features: detected: 32-bit EL0 Support
1353 02:18:41.111868 <6>[ 0.227613] CPU features: detected: 32-bit EL1 Support
1354 02:18:41.117459 <6>[ 0.232959] CPU features: detected: CRC32 instructions
1355 02:18:41.122919 <6>[ 0.238363] alternatives: applying system-wide alternatives
1356 02:18:41.140870 <6>[ 0.245542] Memory: 3557436K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187796K reserved, 262144K cma-reserved)
1357 02:18:41.141357 <6>[ 0.259894] devtmpfs: initialized
1358 02:18:41.151913 <6>[ 0.269066] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1359 02:18:41.157439 <6>[ 0.273419] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1360 02:18:41.162950 <6>[ 0.284217] 21392 pages in range for non-PLT usage
1361 02:18:41.168464 <6>[ 0.284226] 512912 pages in range for PLT usage
1362 02:18:41.174045 <6>[ 0.285773] pinctrl core: initialized pinctrl subsystem
1363 02:18:41.179485 <6>[ 0.297882] DMI not present or invalid.
1364 02:18:41.185014 <6>[ 0.302134] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1365 02:18:41.190574 <6>[ 0.306883] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1366 02:18:41.201755 <6>[ 0.313654] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1367 02:18:41.207228 <6>[ 0.321770] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1368 02:18:41.212766 <6>[ 0.329252] audit: initializing netlink subsys (disabled)
1369 02:18:41.223748 <5>[ 0.334981] audit: type=2000 audit(0.256:1): state=initialized audit_enabled=0 res=1
1370 02:18:41.229276 <6>[ 0.336406] thermal_sys: Registered thermal governor 'step_wise'
1371 02:18:41.235144 <6>[ 0.342758] thermal_sys: Registered thermal governor 'power_allocator'
1372 02:18:41.240268 <6>[ 0.349019] cpuidle: using governor menu
1373 02:18:41.245789 <6>[ 0.360056] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1374 02:18:41.251323 <6>[ 0.366935] ASID allocator initialised with 65536 entries
1375 02:18:41.259565 <6>[ 0.374415] Serial: AMBA PL011 UART driver
1376 02:18:41.267372 <6>[ 0.385011] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1377 02:18:41.282741 <6>[ 0.400533] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1378 02:18:41.291778 <6>[ 0.403197] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1379 02:18:41.297219 <6>[ 0.416364] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1380 02:18:41.308229 <6>[ 0.419581] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1381 02:18:41.313811 <6>[ 0.428001] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1382 02:18:41.324848 <6>[ 0.435626] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1383 02:18:41.330348 <6>[ 0.449212] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1384 02:18:41.335836 <6>[ 0.451447] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1385 02:18:41.346865 <6>[ 0.457927] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1386 02:18:41.352380 <6>[ 0.464906] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1387 02:18:41.357874 <6>[ 0.471375] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1388 02:18:41.363486 <6>[ 0.478359] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1389 02:18:41.368940 <6>[ 0.484829] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1390 02:18:41.380187 <6>[ 0.491814] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1391 02:18:41.380707 <6>[ 0.499826] ACPI: Interpreter disabled.
1392 02:18:41.385486 <6>[ 0.505306] iommu: Default domain type: Translated
1393 02:18:41.391067 <6>[ 0.507347] iommu: DMA domain TLB invalidation policy: strict mode
1394 02:18:41.396524 <5>[ 0.514064] SCSI subsystem initialized
1395 02:18:41.402122 <6>[ 0.517979] usbcore: registered new interface driver usbfs
1396 02:18:41.407644 <6>[ 0.523405] usbcore: registered new interface driver hub
1397 02:18:41.413117 <6>[ 0.528921] usbcore: registered new device driver usb
1398 02:18:41.418753 <6>[ 0.535184] pps_core: LinuxPPS API ver. 1 registered
1399 02:18:41.429741 <6>[ 0.539341] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1400 02:18:41.430240 <6>[ 0.548662] PTP clock support registered
1401 02:18:41.435188 <6>[ 0.552901] EDAC MC: Ver: 3.0.0
1402 02:18:41.440778 <6>[ 0.556551] scmi_core: SCMI protocol bus registered
1403 02:18:41.446232 <6>[ 0.562203] FPGA manager framework
1404 02:18:41.451811 <6>[ 0.564922] Advanced Linux Sound Architecture Driver Initialized.
1405 02:18:41.452331 <6>[ 0.571885] vgaarb: loaded
1406 02:18:41.457302 <6>[ 0.574426] clocksource: Switched to clocksource arch_sys_counter
1407 02:18:41.462823 <5>[ 0.580563] VFS: Disk quotas dquot_6.6.0
1408 02:18:41.468352 <6>[ 0.584554] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1409 02:18:41.473870 <6>[ 0.591769] pnp: PnP ACPI: disabled
1410 02:18:41.479344 <6>[ 0.600282] NET: Registered PF_INET protocol family
1411 02:18:41.484893 <6>[ 0.600591] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1412 02:18:41.495905 <6>[ 0.610737] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1413 02:18:41.501463 <6>[ 0.616758] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1414 02:18:41.512471 <6>[ 0.624653] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1415 02:18:41.518000 <6>[ 0.632891] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1416 02:18:41.529080 <6>[ 0.640691] TCP: Hash tables configured (established 32768 bind 32768)
1417 02:18:41.534539 <6>[ 0.647165] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1418 02:18:41.540086 <6>[ 0.654010] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1419 02:18:41.545669 <6>[ 0.661431] NET: Registered PF_UNIX/PF_LOCAL protocol family
1420 02:18:41.551205 <6>[ 0.667517] RPC: Registered named UNIX socket transport module.
1421 02:18:41.556800 <6>[ 0.673297] RPC: Registered udp transport module.
1422 02:18:41.562143 <6>[ 0.678204] RPC: Registered tcp transport module.
1423 02:18:41.567809 <6>[ 0.683118] RPC: Registered tcp-with-tls transport module.
1424 02:18:41.573202 <6>[ 0.688812] RPC: Registered tcp NFSv4.1 backchannel transport module.
1425 02:18:41.578772 <6>[ 0.695460] PCI: CLS 0 bytes, default 64
1426 02:18:41.584591 <6>[ 0.699781] Unpacking initramfs...
1427 02:18:41.590088 <6>[ 0.709137] kvm [1]: nv: 554 coarse grained trap handlers
1428 02:18:41.595627 <6>[ 0.709439] kvm [1]: IPA Size Limit: 40 bits
1429 02:18:41.596152 <6>[ 0.715134] kvm [1]: vgic interrupt IRQ9
1430 02:18:41.601166 <6>[ 0.717815] kvm [1]: Hyp nVHE mode initialized successfully
1431 02:18:41.606793 <5>[ 0.724897] Initialise system trusted keyrings
1432 02:18:41.612242 <6>[ 0.728451] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1433 02:18:41.617749 <6>[ 0.735108] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1434 02:18:41.623224 <5>[ 0.741203] NFS: Registering the id_resolver key type
1435 02:18:41.628806 <5>[ 0.746193] Key type id_resolver registered
1436 02:18:41.634288 <5>[ 0.750569] Key type id_legacy registered
1437 02:18:41.639756 <6>[ 0.754805] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1438 02:18:41.650836 <6>[ 0.761694] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1439 02:18:41.653648 <6>[ 0.769529] 9p: Installing v9fs 9p2000 file system support
1440 02:18:41.692861 <5>[ 0.816170] Key type asymmetric registered
1441 02:18:41.698266 <5>[ 0.816208] Asymmetric key parser 'x509' registered
1442 02:18:41.707327 <6>[ 0.820078] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1443 02:18:41.712811 <6>[ 0.827598] io scheduler mq-deadline registered
1444 02:18:41.718322 <6>[ 0.832335] io scheduler kyber registered
1445 02:18:41.718798 <6>[ 0.836608] io scheduler bfq registered
1446 02:18:41.726822 <6>[ 0.842541] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1447 02:18:41.745959 <6>[ 0.866516] ledtrig-cpu: registered to indicate activity on CPUs
1448 02:18:41.779378 <6>[ 0.897838] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1449 02:18:41.799233 <6>[ 0.911462] Serial: 8250/16550 driver, 4 ports<<6>[ 0.916154] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1450 02:18:41.804758 <6>[ 0.925781] printk: legacy console [ttyAML0] enabled
1451 02:18:41.810268 <6>[ 0.925781] printk: legacy console [ttyAML0] enabled
1452 02:18:41.815850 <6>[ 0.930578] printk: legacy bootconsole [meson0] disabled
1453 02:18:41.821460 <6>[ 0.930578] printk: legacy bootconsole [meson0] disabled
1454 02:18:41.827006 <6>[ 0.943215] msm_serial: driver initialized
1455 02:18:41.832612 <6>[ 0.946610] SuperH (H)SCI(F) driver initialized
1456 02:18:41.833102 <6>[ 0.951037] STM32 USART driver initialized
1457 02:18:41.838139 <5>[ 0.957243] random: crng init done
1458 02:18:41.845232 <6>[ 0.962948] loop: module loaded
1459 02:18:41.845716 <6>[ 0.964216] megasas: 07.727.03.00-rc1
1460 02:18:41.850854 <6>[ 0.973184] tun: Universal TUN/TAP device driver, 1.6
1461 02:18:41.856302 <6>[ 0.974397] thunder_xcv, ver 1.0
1462 02:18:41.861865 <6>[ 0.976370] thunder_bgx, ver 1.0
1463 02:18:41.862344 <6>[ 0.979833] nicpf, ver 1.0
1464 02:18:41.867405 <6>[ 0.984381] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1465 02:18:41.872977 <6>[ 0.990210] hns3: Copyright (c) 2017 Huawei Corporation.
1466 02:18:41.878518 <6>[ 0.995800] hclge is initializing
1467 02:18:41.884084 <6>[ 0.999347] e1000: Intel(R) PRO/1000 Network Driver
1468 02:18:41.889638 <6>[ 1.004417] e1000: Copyright (c) 1999-2006 Intel Corporation.
1469 02:18:41.895138 <6>[ 1.010461] e1000e: Intel(R) PRO/1000 Network Driver
1470 02:18:41.900712 <6>[ 1.015597] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1471 02:18:41.906230 <6>[ 1.021780] igb: Intel(R) Gigabit Ethernet Network Driver
1472 02:18:41.911851 <6>[ 1.027386] igb: Copyright (c) 2007-2014 Intel Corporation.
1473 02:18:41.917309 <6>[ 1.033219] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1474 02:18:41.922910 <6>[ 1.039689] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1475 02:18:41.928367 <6>[ 1.046458] sky2: driver version 1.30
1476 02:18:41.933989 <6>[ 1.051568] VFIO - User Level meta-driver version: 0.3
1477 02:18:41.939505 <6>[ 1.059078] usbcore: registered new interface driver usb-storage
1478 02:18:41.945653 <6>[ 1.065288] i2c_dev: i2c /dev entries driver
1479 02:18:41.958483 <6>[ 1.076333] sdhci: Secure Digital Host Controller Interface driver
1480 02:18:41.958969 <6>[ 1.077132] sdhci: Copyright(c) Pierre Ossman
1481 02:18:41.969559 <6>[ 1.082882] Synopsys Designware Multimedia Card Interface Driver
1482 02:18:41.975081 <6>[ 1.089389] sdhci-pltfm: SDHCI platform and OF driver helper
1483 02:18:41.975562 <6>[ 1.097059] meson-sm: secure-monitor enabled
1484 02:18:41.987939 <6>[ 1.099631] usbcore: registered new interface driver usbhid
1485 02:18:41.988454 <6>[ 1.104194] usbhid: USB HID core driver
1486 02:18:41.995544 <6>[ 1.118993] NET: Registered PF_PACKET protocol family
1487 02:18:42.001096 <6>[ 1.119084] 9pnet: Installing 9P2000 support
1488 02:18:42.008295 <5>[ 1.123246] Key type dns_resolver registered
1489 02:18:42.015819 <6>[ 1.134947] registered taskstats version 1
1490 02:18:42.016334 <5>[ 1.135101] Loading compiled-in X.509 certificates
1491 02:18:42.023027 <6>[ 1.143770] Demotion targets for Node 0: null
1492 02:18:42.063428 <6>[ 1.186794] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1493 02:18:42.068933 <6>[ 1.186839] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1494 02:18:42.077928 <4>[ 1.196988] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1495 02:18:42.083468 <4>[ 1.199616] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1496 02:18:42.094542 <6>[ 1.207159] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1497 02:18:42.100132 <6>[ 1.216440] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1498 02:18:42.105727 <6>[ 1.219878] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1499 02:18:42.116908 <6>[ 1.227866] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1500 02:18:42.122350 <6>[ 1.237395] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1501 02:18:42.127928 <6>[ 1.243622] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1502 02:18:42.138991 <6>[ 1.249244] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1503 02:18:42.144539 <6>[ 1.257128] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1504 02:18:42.145021 <6>[ 1.264408] hub 1-0:1.0: USB hub found
1505 02:18:42.150089 <6>[ 1.267898] hub 1-0:1.0: 2 ports detected
1506 02:18:42.161148 <6>[ 1.273952] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1507 02:18:42.161631 <6>[ 1.280854] hub 2-0:1.0: USB hub found
1508 02:18:42.168335 <6>[ 1.284446] hub 2-0:1.0: 1 port detected
1509 02:18:42.188390 <6>[ 1.309221] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1510 02:18:42.199617 <6>[ 1.319749] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1511 02:18:42.232390 <6>[ 1.353126] Trying to probe devices needed for running init ...
1512 02:18:42.403388 <6>[ 1.522465] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1513 02:18:42.539945 <6>[ 1.657734] mmc0: new ultra high speed SDR104 SDXC card at address e624
1514 02:18:42.546257 <6>[ 1.659675] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1515 02:18:42.546833 <6>[ 1.669281] mmcblk0: p1
1516 02:18:42.555918 <6>[ 1.677440] Freeing initrd memory: 22880K
1517 02:18:42.589005 <6>[ 1.712224] hub 1-1:1.0: USB hub found
1518 02:18:42.594556 <6>[ 1.712538] hub 1-1:1.0: 4 ports detected
1519 02:18:42.663395 <6>[ 1.782565] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1520 02:18:42.701532 <6>[ 1.824879] hub 2-1:1.0: USB hub found
1521 02:18:42.707207 <6>[ 1.825700] hub 2-1:1.0: 4 ports detected
1522 02:18:54.527517 <6>[ 13.650523] clk: Disabling unused clocks
1523 02:18:54.532738 <6>[ 13.650767] PM: genpd: Disabling unused power domains
1524 02:18:54.541108 <6>[ 13.654402] ALSA device list:
1525 02:18:54.541610 <6>[ 13.657595] No soundcards found.
1526 02:18:54.548173 <6>[ 13.671479] Freeing unused kernel memory: 10432K
1527 02:18:54.554634 <6>[ 13.671610] Run /init as init process
1528 02:18:54.561503 Loading, please wait...
1529 02:18:54.595212 Starting systemd-udevd version 252.22-1~deb12u1
1530 02:18:55.048112 <6>[ 14.169655] mc: Linux media interface: v0.10
1531 02:18:55.058886 <4>[ 14.175612] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1532 02:18:55.066583 <6>[ 14.181388] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1533 02:18:55.072077 <6>[ 14.186829] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1534 02:18:55.077654 <6>[ 14.191924] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1535 02:18:55.081178 <6>[ 14.198212] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1536 02:18:55.086713 <6>[ 14.198601] panfrost ffe40000.gpu: clock rate = 24000000
1537 02:18:55.092246 <6>[ 14.200764] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1538 02:18:55.101441 <3>[ 14.215745] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1539 02:18:55.112529 <6>[ 14.217361] videodev: Linux video capture interface: v2.00
1540 02:18:55.118004 <6>[ 14.217811] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1541 02:18:55.121639 <6>[ 14.217823] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1542 02:18:55.132678 <6>[ 14.217828] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1543 02:18:55.138280 <6>[ 14.217833] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1544 02:18:55.141850 <6>[ 14.217837] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1545 02:18:55.152806 <6>[ 14.217842] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1546 02:18:55.158347 <6>[ 14.217846] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1547 02:18:55.163852 <6>[ 14.217927] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1548 02:18:55.169489 <6>[ 14.217931] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1549 02:18:55.174966 <6>[ 14.217935] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1550 02:18:55.186044 <6>[ 14.237628] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1551 02:18:55.191616 <6>[ 14.256158] meson-vrtc ff8000a8.rtc: registered as rtc0
1552 02:18:55.197136 <6>[ 14.260766] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1553 02:18:55.208243 <6>[ 14.264001] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1554 02:18:55.219389 <6>[ 14.271258] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1555 02:18:55.230569 <3>[ 14.271409] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1556 02:18:55.236037 <6>[ 14.335936] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1557 02:18:55.249960 <6>[ 14.340665] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1558 02:18:55.250449 <6>[ 14.373679] Registered IR keymap rc-empty
1559 02:18:55.261112 <6>[ 14.373826] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1560 02:18:55.266608 <6>[ 14.380225] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1561 02:18:55.277673 <6>[ 14.391204] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1562 02:18:55.288838 <4>[ 14.391302] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1563 02:18:55.294448 <6>[ 14.393945] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1564 02:18:55.299933 <6>[ 14.398651] usbcore: registered new device driver onboard-usb-dev
1565 02:18:55.311001 <6>[ 14.399683] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1566 02:18:55.316570 <3>[ 14.399819] meson-drm ff900000.vpu: DSI transceiver device is disabled
1567 02:18:55.317050 <6>[ 14.406073] rc rc0: sw decoder init
1568 02:18:55.322095 <6>[ 14.406151] meson-ir ff808000.ir: receiver initialized
1569 02:18:55.333172 <6>[ 14.413213] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1570 02:18:55.338140 <6>[ 14.426074] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1571 02:18:55.511109 <4>[ 14.510458] rc rc0: two consecutive events of type space
1572 02:18:55.521924 <6>[ 14.615209] Console: switching to colour frame buffer device 128x48
1573 02:18:55.525771 <6>[ 14.641030] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1574 02:18:55.572858 <6>[ 14.687764] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1575 02:18:55.741008 <6>[ 14.864252] hub 1-1:1.0: USB hub found
1576 02:18:55.746572 <6>[ 14.864549] hub 1-1:1.0: 4 ports detected
1577 02:18:55.752880 <6>[ 14.869381] onboard-usb-dev 1-1: USB disconnect, device number 2
1578 02:18:55.881103 Begin: Loading essential drivers ... done.
1579 02:18:55.886560 Begin: Running /scripts/init-premount ... done.
1580 02:18:55.892099 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1581 02:18:55.905824 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1582 02:18:55.906322 Device /sys/class/net/end0 found
1583 02:18:55.906786 done.
1584 02:18:55.920518 Begin: Waiting up to 180 secs for any network device to become available ... done.
1585 02:18:55.966228 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.079964] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1586 02:18:55.966740
1587 02:18:56.050407 <6>[ 15.168213] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1588 02:18:56.060017 <6>[ 15.170539] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=30)
1589 02:18:56.072699 <6>[ 15.190475] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1590 02:18:56.078204 <6>[ 15.192678] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1591 02:18:56.087527 <6>[ 15.200292] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1592 02:18:56.187434 <6>[ 15.306471] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1593 02:18:56.381119 <6>[ 15.504322] hub 1-1:1.0: USB hub found
1594 02:18:56.386861 <6>[ 15.504691] hub 1-1:1.0: 4 ports detected
1595 02:18:57.642581 IP-Config: no response after 2 secs - giving up
1596 02:18:57.686317 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1597 02:18:59.053687 <6>[ 18.170740] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1598 02:18:59.801258 IP-Config: end0 guessed broadcast address 192.168.6.255
1599 02:18:59.806664 IP-Config: end0 complete (dhcp from 192.168.6.1):
1600 02:18:59.812295 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1601 02:18:59.821365 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1602 02:18:59.825797 rootserver: 192.168.6.1 rootpath:
1603 02:18:59.826327 filename :
1604 02:18:59.918827 done.
1605 02:18:59.929035 Begin: Running /scripts/nfs-bottom ... done.
1606 02:18:59.940825 Begin: Running /scripts/init-bottom ... done.
1607 02:19:00.258882 <30>[ 19.377658] systemd[1]: System time before build time, advancing clock.
1608 02:19:00.310043 <6>[ 19.433180] NET: Registered PF_INET6 protocol family
1609 02:19:00.315487 <6>[ 19.435453] Segment Routing with IPv6
1610 02:19:00.320785 <6>[ 19.436680] In-situ OAM (IOAM) with IPv6
1611 02:19:00.399224 <30>[ 19.491128] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1612 02:19:00.402687 <30>[ 19.518563] systemd[1]: Detected architecture arm64.
1613 02:19:00.403206
1614 02:19:00.408516 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1615 02:19:00.409023
1616 02:19:00.420822 <30>[ 19.540267] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1617 02:19:01.097506 <30>[ 20.215673] systemd[1]: Queued start job for default target graphical.target.
1618 02:19:01.147055 <30>[ 20.264808] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1619 02:19:01.154688 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1620 02:19:01.165736 <30>[ 20.283489] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1621 02:19:01.174210 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1622 02:19:01.185685 <30>[ 20.303429] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1623 02:19:01.194693 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1624 02:19:01.205669 <30>[ 20.323177] systemd[1]: Created slice user.slice - User and Session Slice.
1625 02:19:01.212126 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1626 02:19:01.223435 <30>[ 20.338701] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1627 02:19:01.234783 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1628 02:19:01.246027 <30>[ 20.358621] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1629 02:19:01.252505 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1630 02:19:01.274629 <30>[ 20.378613] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1631 02:19:01.280218 <30>[ 20.392675] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1632 02:19:01.287860 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1633 02:19:01.298923 <30>[ 20.414527] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1634 02:19:01.304385 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1635 02:19:01.320840 <30>[ 20.438551] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1636 02:19:01.334606 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1637 02:19:01.340111 <30>[ 20.458573] systemd[1]: Reached target paths.target - Path Units.
1638 02:19:01.348576 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1639 02:19:01.354037 <30>[ 20.474537] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1640 02:19:01.365731 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1641 02:19:01.371537 <30>[ 20.490521] systemd[1]: Reached target slices.target - Slice Units.
1642 02:19:01.379522 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1643 02:19:01.384939 <30>[ 20.506537] systemd[1]: Reached target swap.target - Swaps.
1644 02:19:01.391895 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1645 02:19:01.404885 <30>[ 20.522556] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1646 02:19:01.413739 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1647 02:19:01.428965 <30>[ 20.546709] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1648 02:19:01.438227 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1649 02:19:01.450148 <30>[ 20.567973] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1650 02:19:01.464049 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1651 02:19:01.469559 <30>[ 20.587514] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1652 02:19:01.482580 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1653 02:19:01.488386 <30>[ 20.606865] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1654 02:19:01.495105 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1655 02:19:01.506091 <30>[ 20.623550] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1656 02:19:01.514979 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1657 02:19:01.527488 <30>[ 20.644404] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1658 02:19:01.532262 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1659 02:19:01.544922 <30>[ 20.662765] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1660 02:19:01.554307 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1661 02:19:01.592882 <30>[ 20.710637] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1662 02:19:01.599587 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1663 02:19:01.611611 <30>[ 20.729126] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1664 02:19:01.619206 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1665 02:19:01.630793 <30>[ 20.748515] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1666 02:19:01.639247 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1667 02:19:01.655744 <30>[ 20.766814] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1668 02:19:01.666869 <30>[ 20.779975] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1669 02:19:01.672728 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1670 02:19:01.687466 <30>[ 20.805286] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1671 02:19:01.695459 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1672 02:19:01.707256 <30>[ 20.825051] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1673 02:19:01.715166 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1674 02:19:01.729705 <6>[ 20.847438] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1675 02:19:01.738636 <30>[ 20.848742] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1676 02:19:01.745648 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1677 02:19:01.759616 <30>[ 20.877396] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1678 02:19:01.767977 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1679 02:19:01.779043 <30>[ 20.896431] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1680 02:19:01.785941 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1681 02:19:01.793704 <6>[ 20.917039] fuse: init (API version 7.41)
1682 02:19:01.804810 <30>[ 20.917109] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1683 02:19:01.808713 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1684 02:19:01.825558 <30>[ 20.943237] systemd[1]: Starting systemd-journald.service - Journal Service...
1685 02:19:01.831851 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1686 02:19:01.846549 <30>[ 20.964260] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1687 02:19:01.853960 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1688 02:19:01.867058 <30>[ 20.984886] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1689 02:19:01.876421 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1690 02:19:01.892415 <30>[ 21.010139] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1691 02:19:01.901064 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1692 02:19:01.921154 <30>[ 21.038954] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1693 02:19:01.929188 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1694 02:19:01.948968 <30>[ 21.066747] systemd[1]: Started systemd-journald.service - Journal Service.
1695 02:19:01.955811 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1696 02:19:01.969987 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1697 02:19:01.976972 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1698 02:19:01.992993 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1699 02:19:02.010550 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1700 02:19:02.023601 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1701 02:19:02.035611 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1702 02:19:02.047257 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1703 02:19:02.059704 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1704 02:19:02.071801 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1705 02:19:02.086575 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1706 02:19:02.093832 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1707 02:19:02.106695 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1708 02:19:02.119105 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1709 02:19:02.132497 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1710 02:19:02.172721 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1711 02:19:02.192694 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1712 02:19:02.213165 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1713 02:19:02.230635 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1714 02:19:02.245382 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1715 02:19:02.252811 <46>[ 21.366490] systemd-journald[227]: Received client request to flush runtime journal.
1716 02:19:02.272238 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1717 02:19:02.288781 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1718 02:19:02.305765 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1719 02:19:02.317746 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1720 02:19:02.333278 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1721 02:19:02.377685 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1722 02:19:02.401684 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1723 02:19:02.452796 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1724 02:19:02.531207 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1725 02:19:02.593083 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1726 02:19:02.609291 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1727 02:19:02.624464 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1728 02:19:02.668514 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1729 02:19:02.679054 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1730 02:19:02.899292 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1731 02:19:02.939662 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1732 02:19:02.994678 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1733 02:19:03.006182 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1734 02:19:03.081702 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1735 02:19:03.094687 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1736 02:19:03.126233 <5>[ 22.244172] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1737 02:19:03.150741 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1738 02:19:03.173940 <5>[ 22.291749] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1739 02:19:03.179442 <5>[ 22.292421] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1740 02:19:03.185116 <4>[ 22.301083] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1741 02:19:03.193216 <6>[ 22.309103] cfg80211: failed to load regulatory.db
1742 02:19:03.257157 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1743 02:19:03.263871 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1744 02:19:03.281648 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1745 02:19:03.297342 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1746 02:19:03.325216 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1747 02:19:03.332345 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1748 02:19:03.344920 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1749 02:19:03.361544 <46>[ 22.469083] systemd-journald[227]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1750 02:19:03.377258 <46>[ 22.482605] systemd-journald[227]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1751 02:19:03.394901 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1752 02:19:03.413148 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1753 02:19:03.420821 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1754 02:19:03.495301 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1755 02:19:03.513649 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1756 02:19:03.528032 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1757 02:19:03.556547 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1758 02:19:03.568031 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1759 02:19:03.581498 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1760 02:19:03.591893 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1761 02:19:03.635892 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1762 02:19:03.654766 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1763 02:19:03.689529 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1764 02:19:03.706098 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1765 02:19:03.734619 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1766 02:19:03.750508 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1767 02:19:03.761201 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1768 02:19:03.781247 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1769 02:19:03.788725 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1770 02:19:03.804180 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1771 02:19:03.839604 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1772 02:19:03.852872 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1773 02:19:03.859920 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1774 02:19:03.869290 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1775 02:19:03.885710 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1776 02:19:03.897483 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1777 02:19:03.953015 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1778 02:19:04.013639 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1779 02:19:04.065675
1780 02:19:04.066231 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1781 02:19:04.066503
1782 02:19:04.072777 debian-bookworm-arm64 login: root (automatic login)
1783 02:19:04.073363
1784 02:19:04.209680 Linux debian-bookworm-arm64 6.12.0-rc2 #1 SMP PREEMPT Sat Nov 9 01:39:14 UTC 2024 aarch64
1785 02:19:04.210367
1786 02:19:04.215234 The programs included with the Debian GNU/Linux system are free software;
1787 02:19:04.220787 the exact distribution terms for each program are described in the
1788 02:19:04.226333 individual files in /usr/share/doc/*/copyright.
1789 02:19:04.226931
1790 02:19:04.231948 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1791 02:19:04.235032 permitted by applicable law.
1792 02:19:04.934335 Matched prompt #10: / #
1794 02:19:04.935279 Setting prompt string to ['/ #']
1795 02:19:04.935598 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1797 02:19:04.936394 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1798 02:19:04.936691 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
1799 02:19:04.936951 Setting prompt string to ['/ #']
1800 02:19:04.937173 Forcing a shell prompt, looking for ['/ #']
1802 02:19:04.987732 / #
1803 02:19:04.988507 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1804 02:19:04.988819 Waiting using forced prompt support (timeout 00:02:30)
1805 02:19:04.993781
1806 02:19:04.994394 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1807 02:19:04.994745 start: 2.4.6 export-device-env (timeout 00:03:11) [common]
1808 02:19:04.995011 Sending with 10 millisecond of delay
1810 02:19:09.984749 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/964271/extract-nfsrootfs-gb3yb0qe'
1811 02:19:09.996870 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/964271/extract-nfsrootfs-gb3yb0qe'
1812 02:19:09.997901 Sending with 10 millisecond of delay
1814 02:19:12.097718 / # export NFS_SERVER_IP='192.168.6.2'
1815 02:19:12.108698 export NFS_SERVER_IP='192.168.6.2'
1816 02:19:12.109626 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1817 02:19:12.110218 end: 2.4 uboot-commands (duration 00:01:56) [common]
1818 02:19:12.110853 end: 2 uboot-action (duration 00:01:56) [common]
1819 02:19:12.111450 start: 3 lava-test-retry (timeout 00:06:45) [common]
1820 02:19:12.112083 start: 3.1 lava-test-shell (timeout 00:06:45) [common]
1821 02:19:12.112575 Using namespace: common
1823 02:19:12.213797 / # #
1824 02:19:12.214582 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1825 02:19:12.220196 #
1826 02:19:12.221103 Using /lava-964271
1828 02:19:12.322341 / # export SHELL=/bin/bash
1829 02:19:12.329209 export SHELL=/bin/bash
1831 02:19:12.430704 / # . /lava-964271/environment
1832 02:19:12.435489 . /lava-964271/environment
1834 02:19:12.541111 / # /lava-964271/bin/lava-test-runner /lava-964271/0
1835 02:19:12.541918 Test shell timeout: 10s (minimum of the action and connection timeout)
1836 02:19:12.545794 /lava-964271/bin/lava-test-runner /lava-964271/0
1837 02:19:12.729339 + export TESTRUN_ID=0_timesync-off
1838 02:19:12.737131 + TESTRUN_ID=0_timesync-off
1839 02:19:12.737664 + cd /lava-964271/0/tests/0_timesync-off
1840 02:19:12.738091 ++ cat uuid
1841 02:19:12.744668 + UUID=964271_1.6.2.4.1
1842 02:19:12.745187 + set +x
1843 02:19:12.753234 <LAVA_SIGNAL_STARTRUN 0_timesync-off 964271_1.6.2.4.1>
1844 02:19:12.753744 + systemctl stop systemd-timesyncd
1845 02:19:12.754446 Received signal: <STARTRUN> 0_timesync-off 964271_1.6.2.4.1
1846 02:19:12.754884 Starting test lava.0_timesync-off (964271_1.6.2.4.1)
1847 02:19:12.755399 Skipping test definition patterns.
1848 02:19:12.806879 + set +x
1849 02:19:12.807489 <LAVA_SIGNAL_ENDRUN 0_timesync-off 964271_1.6.2.4.1>
1850 02:19:12.808220 Received signal: <ENDRUN> 0_timesync-off 964271_1.6.2.4.1
1851 02:19:12.808955 Ending use of test pattern.
1852 02:19:12.809539 Ending test lava.0_timesync-off (964271_1.6.2.4.1), duration 0.05
1854 02:19:12.876912 + export TESTRUN_ID=1_kselftest-alsa
1855 02:19:12.883559 + TESTRUN_ID=1_kselftest-alsa
1856 02:19:12.884327 + cd /lava-964271/0/tests/1_kselftest-alsa
1857 02:19:12.884881 ++ cat uuid
1858 02:19:12.889088 + UUID=964271_1.6.2.4.5
1859 02:19:12.889693 + set +x
1860 02:19:12.891565 Received signal: <STARTRUN> 1_kselftest-alsa 964271_1.6.2.4.5
1861 02:19:12.892189 Starting test lava.1_kselftest-alsa (964271_1.6.2.4.5)
1862 02:19:12.892828 Skipping test definition patterns.
1863 02:19:12.896915 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 964271_1.6.2.4.5>
1864 02:19:12.897526 + cd ./automated/linux/kselftest/
1865 02:19:12.925042 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1866 02:19:12.957335 INFO: install_deps skipped
1867 02:19:13.079499 --2024-11-09 02:19:13-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm64/defconfig/gcc-12/kselftest.tar.xz
1868 02:19:13.101443 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1869 02:19:13.245256 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1870 02:19:13.389938 HTTP request sent, awaiting response... 200 OK
1871 02:19:13.390703 Length: 6925628 (6.6M) [application/octet-stream]
1872 02:19:13.395359 Saving to: 'kselftest_armhf.tar.gz'
1873 02:19:13.396094
1874 02:19:14.707135
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 47.54K 167KB/s
kselftest_armhf.tar 3%[ ] 218.67K 383KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.02MB/s
kselftest_armhf.tar 50%[=========> ] 3.34M 2.87MB/s
kselftest_armhf.tar 100%[===================>] 6.60M 5.03MB/s in 1.3s
1875 02:19:14.708056
1876 02:19:14.803013 2024-11-09 02:19:14 (5.03 MB/s) - 'kselftest_armhf.tar.gz' saved [6925628/6925628]
1877 02:19:14.803847
1878 02:19:23.873078 skiplist:
1879 02:19:23.873509 ========================================
1880 02:19:23.878567 ========================================
1881 02:19:23.918039 alsa:mixer-test
1882 02:19:23.918457 alsa:pcm-test
1883 02:19:23.918680 alsa:test-pcmtest-driver
1884 02:19:23.922021 alsa:utimer-test
1885 02:19:23.931155 ============== Tests to run ===============
1886 02:19:23.931490 alsa:mixer-test
1887 02:19:23.936727 alsa:pcm-test
1888 02:19:23.937030 alsa:test-pcmtest-driver
1889 02:19:23.937247 alsa:utimer-test
1890 02:19:23.945102 ===========End Tests to run ===============
1891 02:19:23.945422 shardfile-alsa pass
1892 02:19:24.064756 <12>[ 43.185936] kselftest: Running tests in alsa
1893 02:19:24.068098 TAP version 13
1894 02:19:24.080821 1..4
1895 02:19:24.100355 # timeout set to 45
1896 02:19:24.100821 # selftests: alsa: mixer-test
1897 02:19:24.304523 # TAP version 13
1898 02:19:24.304971 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1899 02:19:24.310016 # 1..427
1900 02:19:24.310480 # ok 1 get_value.LCALTA.60
1901 02:19:24.310711 # # LCALTA.60 TDMOUT_A SRC SEL
1902 02:19:24.315506 # ok 2 name.LCALTA.60
1903 02:19:24.315919 # ok 3 write_default.LCALTA.60
1904 02:19:24.318978 # ok 4 write_valid.LCALTA.60
1905 02:19:24.324573 # ok 5 write_invalid.LCALTA.60
1906 02:19:24.324891 # ok 6 event_missing.LCALTA.60
1907 02:19:24.330056 # ok 7 event_spurious.LCALTA.60
1908 02:19:24.330520 # ok 8 get_value.LCALTA.59
1909 02:19:24.335684 # # LCALTA.59 TDMOUT_B SRC SEL
1910 02:19:24.336050 # ok 9 name.LCALTA.59
1911 02:19:24.336274 # ok 10 write_default.LCALTA.59
1912 02:19:24.341119 # ok 11 write_valid.LCALTA.59
1913 02:19:24.341440 # ok 12 write_invalid.LCALTA.59
1914 02:19:24.346679 # ok 13 event_missing.LCALTA.59
1915 02:19:24.352242 # ok 14 event_spurious.LCALTA.59
1916 02:19:24.352709 # ok 15 get_value.LCALTA.58
1917 02:19:24.352954 # # LCALTA.58 TDMOUT_C SRC SEL
1918 02:19:24.357774 # ok 16 name.LCALTA.58
1919 02:19:24.358095 # ok 17 write_default.LCALTA.58
1920 02:19:24.363363 # ok 18 write_valid.LCALTA.58
1921 02:19:24.363690 # ok 19 write_invalid.LCALTA.58
1922 02:19:24.370324 # ok 20 event_missing.LCALTA.58
1923 02:19:24.370803 # ok 21 event_spurious.LCALTA.58
1924 02:19:24.374443 # ok 22 get_value.LCALTA.57
1925 02:19:24.374767 # # LCALTA.57 TDMIN_A SRC SEL
1926 02:19:24.380028 # ok 23 name.LCALTA.57
1927 02:19:24.380367 # ok 24 write_default.LCALTA.57
1928 02:19:24.385526 # ok 25 write_valid.LCALTA.57
1929 02:19:24.385848 # ok 26 write_invalid.LCALTA.57
1930 02:19:24.390451 # ok 27 event_missing.LCALTA.57
1931 02:19:24.390778 # ok 28 event_spurious.LCALTA.57
1932 02:19:24.395941 # ok 29 get_value.LCALTA.56
1933 02:19:24.396420 # # LCALTA.56 TDMIN_B SRC SEL
1934 02:19:24.401487 # ok 30 name.LCALTA.56
1935 02:19:24.401807 # ok 31 write_default.LCALTA.56
1936 02:19:24.407049 # ok 32 write_valid.LCALTA.56
1937 02:19:24.407378 # ok 33 write_invalid.LCALTA.56
1938 02:19:24.412611 # ok 34 event_missing.LCALTA.56
1939 02:19:24.413107 # ok 35 event_spurious.LCALTA.56
1940 02:19:24.418174 # ok 36 get_value.LCALTA.55
1941 02:19:24.429345 # # LCAL<3>[ 43.539921] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1942 02:19:24.430132 TA.55 TDMIN_C SRC SEL
1943 02:19:24.434672 # ok 37 name.LCALTA.55
1944 02:19:24.435003 # ok 38 write_default.LCALTA.55
1945 02:19:24.440262 # ok 39 write_valid.LCALTA.55
1946 02:19:24.440818 # ok 40 write_invalid.LCALTA.55
1947 02:19:24.445760 # ok 41 event_missing.LCALTA.55
1948 02:19:24.446144 # ok 42 event_spurious.LCALTA.55
1949 02:19:24.451303 # ok 43 get_value.LCALTA.54
1950 02:19:24.451621 # # LCALTA.54 ACODEC Left DAC Sel
1951 02:19:24.456882 # ok 44 name.LCALTA.54
1952 02:19:24.457215 # ok 45 write_default.LCALTA.54
1953 02:19:24.462403 # ok 46 write_valid.LCALTA.54
1954 02:19:24.462723 # ok 47 write_invalid.LCALTA.54
1955 02:19:24.467947 # ok 48 event_missing.LCALTA.54
1956 02:19:24.468302 # ok 49 event_spurious.LCALTA.54
1957 02:19:24.473483 # ok 50 get_value.LCALTA.53
1958 02:19:24.473799 # # LCALTA.53 ACODEC Right DAC Sel
1959 02:19:24.479030 # ok 51 name.LCALTA.53
1960 02:19:24.479400 # ok 52 write_default.LCALTA.53
1961 02:19:24.484625 # ok 53 write_valid.LCALTA.53
1962 02:19:24.484949 # ok 54 write_invalid.LCALTA.53
1963 02:19:24.490146 # ok 55 event_missing.LCALTA.53
1964 02:19:24.490472 # ok 56 event_spurious.LCALTA.53
1965 02:19:24.495679 # ok 57 get_value.LCALTA.52
1966 02:19:24.496031 # # LCALTA.52 TOACODEC OUT EN Switch
1967 02:19:24.501253 # ok 58 name.LCALTA.52
1968 02:19:24.501639 # ok 59 write_default.LCALTA.52
1969 02:19:24.506808 # ok 60 write_valid.LCALTA.52
1970 02:19:24.507220 # ok 61 write_invalid.LCALTA.52
1971 02:19:24.512348 # ok 62 event_missing.LCALTA.52
1972 02:19:24.512740 # ok 63 event_spurious.LCALTA.52
1973 02:19:24.517910 # ok 64 get_value.LCALTA.51
1974 02:19:24.518306 # # LCALTA.51 TOACODEC SRC
1975 02:19:24.523444 # ok 65 name.LCALTA.51
1976 02:19:24.523788 # ok 66 write_default.LCALTA.51
1977 02:19:24.528987 # ok 67 write_valid.LCALTA.51
1978 02:19:24.529333 # ok 68 write_invalid.LCALTA.51
1979 02:19:24.534679 # ok 69 event_missing.LCALTA.51
1980 02:19:24.535041 # ok 70 event_spurious.LCALTA.51
1981 02:19:24.540143 # ok 71 get_value.LCALTA.50
1982 02:19:24.540507 # # LCALTA.50 TOHDMITX SPDIF SRC
1983 02:19:24.540815 # ok 72 name.LCALTA.50
1984 02:19:24.545665 # ok 73 write_default.LCALTA.50
1985 02:19:24.546019 # ok 74 write_valid.LCALTA.50
1986 02:19:24.551159 # ok 75 write_invalid.LCALTA.50
1987 02:19:24.551518 # ok 76 event_missing.LCALTA.50
1988 02:19:24.556706 # ok 77 event_spurious.LCALTA.50
1989 02:19:24.557055 # ok 78 get_value.LCALTA.49
1990 02:19:24.562316 # # LCALTA.49 TOHDMITX Switch
1991 02:19:24.562719 # ok 79 name.LCALTA.49
1992 02:19:24.567869 # ok 80 write_default.LCALTA.49
1993 02:19:24.568349 # ok 81 write_valid.LCALTA.49
1994 02:19:24.573391 # ok 82 write_invalid.LCALTA.49
1995 02:19:24.573784 # ok 83 event_missing.LCALTA.49
1996 02:19:24.578883 # ok 84 event_spurious.LCALTA.49
1997 02:19:24.579211 # ok 85 get_value.LCALTA.48
1998 02:19:24.584508 # # LCALTA.48 TOHDMITX I2S SRC
1999 02:19:24.584902 # ok 86 name.LCALTA.48
2000 02:19:24.589980 # ok 87 write_default.LCALTA.48
2001 02:19:24.590312 # ok 88 write_valid.LCALTA.48
2002 02:19:24.595635 # ok 89 write_invalid.LCALTA.48
2003 02:19:24.595961 # ok 90 event_missing.LCALTA.48
2004 02:19:24.601064 # ok 91 event_spurious.LCALTA.48
2005 02:19:24.601390 # ok 92 get_value.LCALTA.47
2006 02:19:24.606643 # # LCALTA.47 TODDR_C SRC SEL
2007 02:19:24.606971 # ok 93 name.LCALTA.47
2008 02:19:24.612199 # ok 94 write_default.LCALTA.47
2009 02:19:24.612525 # ok 95 write_valid.LCALTA.47
2010 02:19:24.617690 # ok 96 write_invalid.LCALTA.47
2011 02:19:24.618017 # ok 97 event_missing.LCALTA.47
2012 02:19:24.623251 # ok 98 event_spurious.LCALTA.47
2013 02:19:24.623589 # ok 99 get_value.LCALTA.46
2014 02:19:24.628779 # # LCALTA.46 TODDR_B SRC SEL
2015 02:19:24.629139 # ok 100 name.LCALTA.46
2016 02:19:24.634349 # ok 101 write_default.LCALTA.46
2017 02:19:24.634677 # ok 102 write_valid.LCALTA.46
2018 02:19:24.639891 # ok 103 write_invalid.LCALTA.46
2019 02:19:24.640228 # ok 104 event_missing.LCALTA.46
2020 02:19:24.645438 # ok 105 event_spurious.LCALTA.46
2021 02:19:24.645765 # ok 106 get_value.LCALTA.45
2022 02:19:24.650988 # # LCALTA.45 TODDR_A SRC SEL
2023 02:19:24.651301 # ok 107 name.LCALTA.45
2024 02:19:24.651519 # ok 108 write_default.LCALTA.45
2025 02:19:24.656645 # ok 109 write_valid.LCALTA.45
2026 02:19:24.662071 # ok 110 write_invalid.LCALTA.45
2027 02:19:24.662381 # ok 111 event_missing.LCALTA.45
2028 02:19:24.667634 # ok 112 event_spurious.LCALTA.45
2029 02:19:24.667944 # ok 113 get_value.LCALTA.44
2030 02:19:24.673207 # # LCALTA.44 FRDDR_C SINK 3 SEL
2031 02:19:24.673552 # ok 114 name.LCALTA.44
2032 02:19:24.678691 # ok 115 write_default.LCALTA.44
2033 02:19:24.679011 # ok 116 write_valid.LCALTA.44
2034 02:19:24.684265 # ok 117 write_invalid.LCALTA.44
2035 02:19:24.684585 # ok 118 event_missing.LCALTA.44
2036 02:19:24.689812 # ok 119 event_spurious.LCALTA.44
2037 02:19:24.690136 # ok 120 get_value.LCALTA.43
2038 02:19:24.695357 # # LCALTA.43 FRDDR_C SINK 2 SEL
2039 02:19:24.695694 # ok 121 name.LCALTA.43
2040 02:19:24.700900 # ok 122 write_default.LCALTA.43
2041 02:19:24.701239 # ok 123 write_valid.LCALTA.43
2042 02:19:24.706541 # ok 124 write_invalid.LCALTA.43
2043 02:19:24.706897 # ok 125 event_missing.LCALTA.43
2044 02:19:24.712044 # ok 126 event_spurious.LCALTA.43
2045 02:19:24.712411 # ok 127 get_value.LCALTA.42
2046 02:19:24.717664 # # LCALTA.42 FRDDR_C SINK 1 SEL
2047 02:19:24.718019 # ok 128 name.LCALTA.42
2048 02:19:24.723103 # ok 129 write_default.LCALTA.42
2049 02:19:24.723457 # ok 130 write_valid.LCALTA.42
2050 02:19:24.728675 # ok 131 write_invalid.LCALTA.42
2051 02:19:24.729038 # ok 132 event_missing.LCALTA.42
2052 02:19:24.734247 # ok 133 event_spurious.LCALTA.42
2053 02:19:24.734640 # ok 134 get_value.LCALTA.41
2054 02:19:24.739723 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
2055 02:19:24.740119 # ok 135 name.LCALTA.41
2056 02:19:24.745268 # ok 136 write_default.LCALTA.41
2057 02:19:24.745629 # ok 137 write_valid.LCALTA.41
2058 02:19:24.750798 # ok 138 write_invalid.LCALTA.41
2059 02:19:24.751162 # ok 139 event_missing.LCALTA.41
2060 02:19:24.756351 # ok 140 event_spurious.LCALTA.41
2061 02:19:24.756721 # ok 141 get_value.LCALTA.40
2062 02:19:24.761893 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
2063 02:19:24.762251 # ok 142 name.LCALTA.40
2064 02:19:24.767509 # ok 143 write_default.LCALTA.40
2065 02:19:24.767874 # ok 144 write_valid.LCALTA.40
2066 02:19:24.773036 # ok 145 write_invalid.LCALTA.40
2067 02:19:24.773394 # ok 146 event_missing.LCALTA.40
2068 02:19:24.778675 # ok 147 event_spurious.LCALTA.40
2069 02:19:24.779027 # ok 148 get_value.LCALTA.39
2070 02:19:24.784257 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
2071 02:19:24.784619 # ok 149 name.LCALTA.39
2072 02:19:24.789682 # ok 150 write_default.LCALTA.39
2073 02:19:24.790030 # ok 151 write_valid.LCALTA.39
2074 02:19:24.795219 # ok 152 write_invalid.LCALTA.39
2075 02:19:24.795559 # ok 153 event_missing.LCALTA.39
2076 02:19:24.800723 # ok 154 event_spurious.LCALTA.39
2077 02:19:24.801070 # ok 155 get_value.LCALTA.38
2078 02:19:24.806291 # # LCALTA.38 FRDDR_B SINK 3 SEL
2079 02:19:24.806630 # ok 156 name.LCALTA.38
2080 02:19:24.811871 # ok 157 write_default.LCALTA.38
2081 02:19:24.812229 # ok 158 write_valid.LCALTA.38
2082 02:19:24.817371 # ok 159 write_invalid.LCALTA.38
2083 02:19:24.822912 # ok 160 event_missing.LCALTA.38
2084 02:19:24.823238 # ok 161 event_spurious.LCALTA.38
2085 02:19:24.828534 # ok 162 get_value.LCALTA.37
2086 02:19:24.828869 # # LCALTA.37 FRDDR_B SINK 2 SEL
2087 02:19:24.829095 # ok 163 name.LCALTA.37
2088 02:19:24.834831 # ok 164 write_default.LCALTA.37
2089 02:19:24.835206 # ok 165 write_valid.LCALTA.37
2090 02:19:24.839681 # ok 166 write_invalid.LCALTA.37
2091 02:19:24.845136 # ok 167 event_missing.LCALTA.37
2092 02:19:24.845497 # ok 168 event_spurious.LCALTA.37
2093 02:19:24.850640 # ok 169 get_value.LCALTA.36
2094 02:19:24.850999 # # LCALTA.36 FRDDR_B SINK 1 SEL
2095 02:19:24.851226 # ok 170 name.LCALTA.36
2096 02:19:24.856214 # ok 171 write_default.LCALTA.36
2097 02:19:24.861760 # ok 172 write_valid.LCALTA.36
2098 02:19:24.862117 # ok 173 write_invalid.LCALTA.36
2099 02:19:24.867337 # ok 174 event_missing.LCALTA.36
2100 02:19:24.867698 # ok 175 event_spurious.LCALTA.36
2101 02:19:24.872879 # ok 176 get_value.LCALTA.35
2102 02:19:24.873237 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
2103 02:19:24.878431 # ok 177 name.LCALTA.35
2104 02:19:24.878788 # ok 178 write_default.LCALTA.35
2105 02:19:24.883948 # ok 179 write_valid.LCALTA.35
2106 02:19:24.884334 # ok 180 write_invalid.LCALTA.35
2107 02:19:24.889535 # ok 181 event_missing.LCALTA.35
2108 02:19:24.889887 # ok 182 event_spurious.LCALTA.35
2109 02:19:24.895060 # ok 183 get_value.LCALTA.34
2110 02:19:24.895417 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
2111 02:19:24.900687 # ok 184 name.LCALTA.34
2112 02:19:24.901043 # ok 185 write_default.LCALTA.34
2113 02:19:24.906153 # ok 186 write_valid.LCALTA.34
2114 02:19:24.906517 # ok 187 write_invalid.LCALTA.34
2115 02:19:24.911969 # ok 188 event_missing.LCALTA.34
2116 02:19:24.912343 # ok 189 event_spurious.LCALTA.34
2117 02:19:24.917241 # ok 190 get_value.LCALTA.33
2118 02:19:24.917599 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
2119 02:19:24.922904 # ok 191 name.LCALTA.33
2120 02:19:24.923542 # ok 192 write_default.LCALTA.33
2121 02:19:24.928446 # ok 193 write_valid.LCALTA.33
2122 02:19:24.929040 # ok 194 write_invalid.LCALTA.33
2123 02:19:24.933962 # ok 195 event_missing.LCALTA.33
2124 02:19:24.934531 # ok 196 event_spurious.LCALTA.33
2125 02:19:24.939542 # ok 197 get_value.LCALTA.32
2126 02:19:24.940148 # # LCALTA.32 FRDDR_A SINK 3 SEL
2127 02:19:24.945103 # ok 198 name.LCALTA.32
2128 02:19:24.945679 # ok 199 write_default.LCALTA.32
2129 02:19:24.950642 # ok 200 write_valid.LCALTA.32
2130 02:19:24.951217 # ok 201 write_invalid.LCALTA.32
2131 02:19:24.956240 # ok 202 event_missing.LCALTA.32
2132 02:19:24.956818 # ok 203 event_spurious.LCALTA.32
2133 02:19:24.961810 # ok 204 get_value.LCALTA.31
2134 02:19:24.962378 # # LCALTA.31 FRDDR_A SINK 2 SEL
2135 02:19:24.967277 # ok 205 name.LCALTA.31
2136 02:19:24.967838 # ok 206 write_default.LCALTA.31
2137 02:19:24.972856 # ok 207 write_valid.LCALTA.31
2138 02:19:24.973412 # ok 208 write_invalid.LCALTA.31
2139 02:19:24.978359 # ok 209 event_missing.LCALTA.31
2140 02:19:24.983904 # ok 210 event_spurious.LCALTA.31
2141 02:19:24.984500 # ok 211 get_value.LCALTA.30
2142 02:19:24.989460 # # LCALTA.30 FRDDR_A SINK 1 SEL
2143 02:19:24.990022 # ok 212 name.LCALTA.30
2144 02:19:24.990469 # ok 213 write_default.LCALTA.30
2145 02:19:24.995011 # ok 214 write_valid.LCALTA.30
2146 02:19:24.995572 # ok 215 write_invalid.LCALTA.30
2147 02:19:25.000566 # ok 216 event_missing.LCALTA.30
2148 02:19:25.006096 # ok 217 event_spurious.LCALTA.30
2149 02:19:25.006667 # ok 218 get_value.LCALTA.29
2150 02:19:25.011681 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2151 02:19:25.012281 # ok 219 name.LCALTA.29
2152 02:19:25.017176 # ok 220 write_default.LCALTA.29
2153 02:19:25.017738 # ok 221 write_valid.LCALTA.29
2154 02:19:25.022862 # ok 222 write_invalid.LCALTA.29
2155 02:19:25.023437 # ok 223 event_missing.LCALTA.29
2156 02:19:25.028320 # ok 224 event_spurious.LCALTA.29
2157 02:19:25.028901 # ok 225 get_value.LCALTA.28
2158 02:19:25.033881 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2159 02:19:25.034448 # ok 226 name.LCALTA.28
2160 02:19:25.039379 # ok 227 write_default.LCALTA.28
2161 02:19:25.039942 # ok 228 write_valid.LCALTA.28
2162 02:19:25.044916 # ok 229 write_invalid.LCALTA.28
2163 02:19:25.045472 # ok 230 event_missing.LCALTA.28
2164 02:19:25.050473 # ok 231 event_spurious.LCALTA.28
2165 02:19:25.051037 # ok 232 get_value.LCALTA.27
2166 02:19:25.056038 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2167 02:19:25.056606 # ok 233 name.LCALTA.27
2168 02:19:25.061556 # ok 234 write_default.LCALTA.27
2169 02:19:25.062105 # ok 235 write_valid.LCALTA.27
2170 02:19:25.067088 # ok 236 write_invalid.LCALTA.27
2171 02:19:25.067647 # ok 237 event_missing.LCALTA.27
2172 02:19:25.072694 # ok 238 event_spurious.LCALTA.27
2173 02:19:25.073244 # ok 239 get_value.LCALTA.26
2174 02:19:25.078185 # # LCALTA.26 ELD
2175 02:19:25.078738 # ok 240 name.LCALTA.26
2176 02:19:25.079184 # # ELD is not writeable
2177 02:19:25.083806 # ok 241 # SKIP write_default.LCALTA.26
2178 02:19:25.084415 # # ELD is not writeable
2179 02:19:25.089281 # ok 242 # SKIP write_valid.LCALTA.26
2180 02:19:25.089836 # # ELD is not writeable
2181 02:19:25.094828 # ok 243 # SKIP write_invalid.LCALTA.26
2182 02:19:25.100363 # ok 244 event_missing.LCALTA.26
2183 02:19:25.100924 # ok 245 event_spurious.LCALTA.26
2184 02:19:25.105916 # ok 246 get_value.LCALTA.25
2185 02:19:25.106468 # # LCALTA.25 IEC958 Playback Default
2186 02:19:25.111486 # ok 247 name.LCALTA.25
2187 02:19:25.112063 # ok 248 write_default.LCALTA.25
2188 02:19:25.117011 # ok 249 # SKIP write_valid.LCALTA.25
2189 02:19:25.117553 # ok 250 # SKIP write_invalid.LCALTA.25
2190 02:19:25.122652 # ok 251 event_missing.LCALTA.25
2191 02:19:25.128103 # ok 252 event_spurious.LCALTA.25
2192 02:19:25.128655 # ok 253 get_value.LCALTA.24
2193 02:19:25.133682 # # LCALTA.24 IEC958 Playback Mask
2194 02:19:25.134224 # ok 254 name.LCALTA.24
2195 02:19:25.139207 # # IEC958 Playback Mask is not writeable
2196 02:19:25.139758 # ok 255 # SKIP write_default.LCALTA.24
2197 02:19:25.144819 # # IEC958 Playback Mask is not writeable
2198 02:19:25.150301 # ok 256 # SKIP write_valid.LCALTA.24
2199 02:19:25.150851 # # IEC958 Playback Mask is not writeable
2200 02:19:25.155871 # ok 257 # SKIP write_invalid.LCALTA.24
2201 02:19:25.156444 # ok 258 event_missing.LCALTA.24
2202 02:19:25.161472 # ok 259 event_spurious.LCALTA.24
2203 02:19:25.162034 # ok 260 get_value.LCALTA.23
2204 02:19:25.166975 # # LCALTA.23 Playback Channel Map
2205 02:19:25.167518 # ok 261 name.LCALTA.23
2206 02:19:25.172491 # # Playback Channel Map is not writeable
2207 02:19:25.178047 # ok 262 # SKIP write_default.LCALTA.23
2208 02:19:25.178598 # # Playback Channel Map is not writeable
2209 02:19:25.183585 # ok 263 # SKIP write_valid.LCALTA.23
2210 02:19:25.189117 # # Playback Channel Map is not writeable
2211 02:19:25.189664 # ok 264 # SKIP write_invalid.LCALTA.23
2212 02:19:25.194699 # ok 265 event_missing.LCALTA.23
2213 02:19:25.195239 # ok 266 event_spurious.LCALTA.23
2214 02:19:25.200271 # ok 267 get_value.LCALTA.22
2215 02:19:25.200822 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2216 02:19:25.205846 # ok 268 name.LCALTA.22
2217 02:19:25.206387 # ok 269 write_default.LCALTA.22
2218 02:19:25.211315 # ok 270 write_valid.LCALTA.22
2219 02:19:25.211860 # ok 271 write_invalid.LCALTA.22
2220 02:19:25.216884 # ok 272 event_missing.LCALTA.22
2221 02:19:25.222403 # ok 273 event_spurious.LCALTA.22
2222 02:19:25.222949 # ok 274 get_value.LCALTA.21
2223 02:19:25.227970 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2224 02:19:25.228546 # ok 275 name.LCALTA.21
2225 02:19:25.233538 # ok 276 write_default.LCALTA.21
2226 02:19:25.234076 # ok 277 write_valid.LCALTA.21
2227 02:19:25.239111 # ok 278 write_invalid.LCALTA.21
2228 02:19:25.239671 # ok 279 event_missing.LCALTA.21
2229 02:19:25.244574 # ok 280 event_spurious.LCALTA.21
2230 02:19:25.245120 # ok 281 get_value.LCALTA.20
2231 02:19:25.250114 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2232 02:19:25.250666 # ok 282 name.LCALTA.20
2233 02:19:25.255670 # ok 283 write_default.LCALTA.20
2234 02:19:25.256254 # ok 284 write_valid.LCALTA.20
2235 02:19:25.261229 # ok 285 write_invalid.LCALTA.20
2236 02:19:25.261773 # ok 286 event_missing.LCALTA.20
2237 02:19:25.266830 # ok 287 event_spurious.LCALTA.20
2238 02:19:25.267372 # ok 288 get_value.LCALTA.19
2239 02:19:25.272316 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2240 02:19:25.272857 # ok 289 name.LCALTA.19
2241 02:19:25.277869 # ok 290 write_default.LCALTA.19
2242 02:19:25.278412 # ok 291 write_valid.LCALTA.19
2243 02:19:25.283399 # ok 292 write_invalid.LCALTA.19
2244 02:19:25.283938 # ok 293 event_missing.LCALTA.19
2245 02:19:25.288955 # ok 294 event_spurious.LCALTA.19
2246 02:19:25.289506 # ok 295 get_value.LCALTA.18
2247 02:19:25.294546 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2248 02:19:25.295122 # ok 296 name.LCALTA.18
2249 02:19:25.300083 # ok 297 write_default.LCALTA.18
2250 02:19:25.300636 # ok 298 write_valid.LCALTA.18
2251 02:19:25.305607 # ok 299 write_invalid.LCALTA.18
2252 02:19:25.306149 # ok 300 event_missing.LCALTA.18
2253 02:19:25.311142 # ok 301 event_spurious.LCALTA.18
2254 02:19:25.311686 # ok 302 get_value.LCALTA.17
2255 02:19:25.316701 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2256 02:19:25.317248 # ok 303 name.LCALTA.17
2257 02:19:25.322236 # ok 304 write_default.LCALTA.17
2258 02:19:25.322779 # ok 305 write_valid.LCALTA.17
2259 02:19:25.327852 # ok 306 write_invalid.LCALTA.17
2260 02:19:25.333346 # ok 307 event_missing.LCALTA.17
2261 02:19:25.333881 # ok 308 event_spurious.LCALTA.17
2262 02:19:25.338895 # ok 309 get_value.LCALTA.16
2263 02:19:25.339439 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2264 02:19:25.344431 # ok 310 name.LCALTA.16
2265 02:19:25.344974 # ok 311 write_default.LCALTA.16
2266 02:19:25.349941 # ok 312 write_valid.LCALTA.16
2267 02:19:25.350476 # ok 313 write_invalid.LCALTA.16
2268 02:19:25.355497 # ok 314 event_missing.LCALTA.16
2269 02:19:25.356073 # ok 315 event_spurious.LCALTA.16
2270 02:19:25.361071 # ok 316 get_value.LCALTA.15
2271 02:19:25.361611 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2272 02:19:25.366628 # ok 317 name.LCALTA.15
2273 02:19:25.367163 # ok 318 write_default.LCALTA.15
2274 02:19:25.372215 # ok 319 write_valid.LCALTA.15
2275 02:19:25.372765 # ok 320 write_invalid.LCALTA.15
2276 02:19:25.377743 # ok 321 event_missing.LCALTA.15
2277 02:19:25.378290 # ok 322 event_spurious.LCALTA.15
2278 02:19:25.383254 # ok 323 get_value.LCALTA.14
2279 02:19:25.383793 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2280 02:19:25.388850 # ok 324 name.LCALTA.14
2281 02:19:25.389391 # ok 325 write_default.LCALTA.14
2282 02:19:25.394359 # ok 326 write_valid.LCALTA.14
2283 02:19:25.394905 # ok 327 write_invalid.LCALTA.14
2284 02:19:25.399906 # ok 328 event_missing.LCALTA.14
2285 02:19:25.400481 # ok 329 event_spurious.LCALTA.14
2286 02:19:25.405414 # ok 330 get_value.LCALTA.13
2287 02:19:25.405952 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2288 02:19:25.410964 # ok 331 name.LCALTA.13
2289 02:19:25.411512 # ok 332 write_default.LCALTA.13
2290 02:19:25.416512 # ok 333 write_valid.LCALTA.13
2291 02:19:25.417062 # ok 334 write_invalid.LCALTA.13
2292 02:19:25.422090 # ok 335 event_missing.LCALTA.13
2293 02:19:25.422634 # ok 336 event_spurious.LCALTA.13
2294 02:19:25.427603 # ok 337 get_value.LCALTA.12
2295 02:19:25.433163 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2296 02:19:25.433712 # ok 338 name.LCALTA.12
2297 02:19:25.438720 # ok 339 write_default.LCALTA.12
2298 02:19:25.439256 # ok 340 write_valid.LCALTA.12
2299 02:19:25.444322 # ok 341 write_invalid.LCALTA.12
2300 02:19:25.444881 # ok 342 event_missing.LCALTA.12
2301 02:19:25.449871 # ok 343 event_spurious.LCALTA.12
2302 02:19:25.450405 # ok 344 get_value.LCALTA.11
2303 02:19:25.455367 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2304 02:19:25.455897 # ok 345 name.LCALTA.11
2305 02:19:25.460897 # ok 346 write_default.LCALTA.11
2306 02:19:25.461435 # ok 347 write_valid.LCALTA.11
2307 02:19:25.466449 # ok 348 write_invalid.LCALTA.11
2308 02:19:25.466981 # ok 349 event_missing.LCALTA.11
2309 02:19:25.472028 # ok 350 event_spurious.LCALTA.11
2310 02:19:25.472563 # ok 351 get_value.LCALTA.10
2311 02:19:25.477544 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2312 02:19:25.478073 # ok 352 name.LCALTA.10
2313 02:19:25.483095 # ok 353 write_default.LCALTA.10
2314 02:19:25.483622 # ok 354 write_valid.LCALTA.10
2315 02:19:25.488647 # ok 355 write_invalid.LCALTA.10
2316 02:19:25.489181 # ok 356 event_missing.LCALTA.10
2317 02:19:25.494167 # ok 357 event_spurious.LCALTA.10
2318 02:19:25.494716 # ok 358 get_value.LCALTA.9
2319 02:19:25.499739 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2320 02:19:25.500321 # ok 359 name.LCALTA.9
2321 02:19:25.505305 # ok 360 write_default.LCALTA.9
2322 02:19:25.505845 # ok 361 write_valid.LCALTA.9
2323 02:19:25.510891 # ok 362 write_invalid.LCALTA.9
2324 02:19:25.511430 # ok 363 event_missing.LCALTA.9
2325 02:19:25.516362 # ok 364 event_spurious.LCALTA.9
2326 02:19:25.516891 # ok 365 get_value.LCALTA.8
2327 02:19:25.521923 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2328 02:19:25.522467 # ok 366 name.LCALTA.8
2329 02:19:25.527492 # ok 367 write_default.LCALTA.8
2330 02:19:25.528069 # ok 368 write_valid.LCALTA.8
2331 02:19:25.533030 # ok 369 write_invalid.LCALTA.8
2332 02:19:25.533580 # ok 370 event_missing.LCALTA.8
2333 02:19:25.538583 # ok 371 event_spurious.LCALTA.8
2334 02:19:25.539133 # ok 372 get_value.LCALTA.7
2335 02:19:25.544129 # # LCALTA.7 ACODEC Unmute Ramp Switch
2336 02:19:25.544674 # ok 373 name.LCALTA.7
2337 02:19:25.549683 # ok 374 write_default.LCALTA.7
2338 02:19:25.550225 # ok 375 write_valid.LCALTA.7
2339 02:19:25.555208 # ok 376 write_invalid.LCALTA.7
2340 02:19:25.555742 # ok 377 event_missing.LCALTA.7
2341 02:19:25.560734 # ok 378 event_spurious.LCALTA.7
2342 02:19:25.561274 # ok 379 get_value.LCALTA.6
2343 02:19:25.566428 # # LCALTA.6 ACODEC Mute Ramp Switch
2344 02:19:25.567051 # ok 380 name.LCALTA.6
2345 02:19:25.571888 # ok 381 write_default.LCALTA.6
2346 02:19:25.572510 # ok 382 write_valid.LCALTA.6
2347 02:19:25.577381 # ok 383 write_invalid.LCALTA.6
2348 02:19:25.577945 # ok 384 event_missing.LCALTA.6
2349 02:19:25.582942 # ok 385 event_spurious.LCALTA.6
2350 02:19:25.583512 # ok 386 get_value.LCALTA.5
2351 02:19:25.588476 # # LCALTA.5 ACODEC Volume Ramp Switch
2352 02:19:25.589041 # ok 387 name.LCALTA.5
2353 02:19:25.594042 # ok 388 write_default.LCALTA.5
2354 02:19:25.594607 # ok 389 write_valid.LCALTA.5
2355 02:19:25.599611 # ok 390 write_invalid.LCALTA.5
2356 02:19:25.600192 # ok 391 event_missing.LCALTA.5
2357 02:19:25.605156 # ok 392 event_spurious.LCALTA.5
2358 02:19:25.605710 # ok 393 get_value.LCALTA.4
2359 02:19:25.610693 # # LCALTA.4 ACODEC Ramp Rate
2360 02:19:25.611256 # ok 394 name.LCALTA.4
2361 02:19:25.616316 # ok 395 write_default.LCALTA.4
2362 02:19:25.616894 # ok 396 write_valid.LCALTA.4
2363 02:19:25.621751 # ok 397 write_invalid.LCALTA.4
2364 02:19:25.622309 # ok 398 event_missing.LCALTA.4
2365 02:19:25.627327 # ok 399 event_spurious.LCALTA.4
2366 02:19:25.627891 # ok 400 get_value.LCALTA.3
2367 02:19:25.632903 # # LCALTA.3 ACODEC Playback Volume
2368 02:19:25.633454 # ok 401 name.LCALTA.3
2369 02:19:25.638466 # ok 402 write_default.LCALTA.3
2370 02:19:25.639037 # ok 403 write_valid.LCALTA.3
2371 02:19:25.643928 # ok 404 write_invalid.LCALTA.3
2372 02:19:25.644509 # ok 405 event_missing.LCALTA.3
2373 02:19:25.649477 # ok 406 event_spurious.LCALTA.3
2374 02:19:25.650037 # ok 407 get_value.LCALTA.2
2375 02:19:25.655020 # # LCALTA.2 ACODEC Playback Switch
2376 02:19:25.655593 # ok 408 name.LCALTA.2
2377 02:19:25.660605 # ok 409 write_default.LCALTA.2
2378 02:19:25.661160 # ok 410 write_valid.LCALTA.2
2379 02:19:25.666134 # ok 411 write_invalid.LCALTA.2
2380 02:19:25.666705 # ok 412 event_missing.LCALTA.2
2381 02:19:25.672209 # ok 413 event_spurious.LCALTA.2
2382 02:19:25.672818 # ok 414 get_value.LCALTA.1
2383 02:19:25.677256 # # LCALTA.1 ACODEC Playback Channel Mode
2384 02:19:25.677772 # ok 415 name.LCALTA.1
2385 02:19:25.682967 # ok 416 write_default.LCALTA.1
2386 02:19:25.683556 # ok 417 write_valid.LCALTA.1
2387 02:19:25.688338 # ok 418 write_invalid.LCALTA.1
2388 02:19:25.688860 # ok 419 event_missing.LCALTA.1
2389 02:19:25.693860 # ok 420 event_spurious.LCALTA.1
2390 02:19:25.694360 # ok 421 get_value.LCALTA.0
2391 02:19:25.699359 # # LCALTA.0 TOACODEC Lane Select
2392 02:19:25.699864 # ok 422 name.LCALTA.0
2393 02:19:25.705058 # ok 423 write_default.LCALTA.0
2394 02:19:25.705654 # ok 424 write_valid.LCALTA.0
2395 02:19:25.710510 # ok 425 write_invalid.LCALTA.0
2396 02:19:25.711009 # ok 426 event_missing.LCALTA.0
2397 02:19:25.716029 # ok 427 event_spurious.LCALTA.0
2398 02:19:25.721536 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2399 02:19:25.722039 ok 1 selftests: alsa: mixer-test
2400 02:19:25.722491 # timeout set to 45
2401 02:19:25.727058 # selftests: alsa: pcm-test
2402 02:19:25.727583 # TAP version 13
2403 02:19:25.732801 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2404 02:19:25.733395 # # LCALTA.0 - fe.dai-link-0 (*)
2405 02:19:25.738157 # # LCALTA.0 - fe.dai-link-1 (*)
2406 02:19:25.738655 # # LCALTA.0 - fe.dai-link-2 (*)
2407 02:19:25.743920 # # LCALTA.0 - fe.dai-link-3 (*)
2408 02:19:25.744557 # # LCALTA.0 - fe.dai-link-4 (*)
2409 02:19:25.749263 # # LCALTA.0 - fe.dai-link-5 (*)
2410 02:19:25.749768 # 1..42
2411 02:19:25.754790 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2412 02:19:25.760334 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2413 02:19:25.760837 # # snd_pcm_hw_params: Invalid argument
2414 02:19:25.765906 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2415 02:19:25.771480 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2416 02:19:25.777021 # # snd_pcm_hw_params: Invalid argument
2417 02:19:25.782472 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2418 02:19:25.788095 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2419 02:19:25.788687 # # snd_pcm_hw_params: Invalid argument
2420 02:19:25.793746 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2421 02:19:25.799231 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2422 02:19:25.804907 # # snd_pcm_hw_params: Invalid argument
2423 02:19:25.810262 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2424 02:19:25.815806 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2425 02:19:25.816378 # # snd_pcm_hw_params: Invalid argument
2426 02:19:25.821339 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2427 02:19:25.826898 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2428 02:19:25.832418 # # snd_pcm_hw_params: Invalid argument
2429 02:19:25.837977 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2430 02:19:25.838540 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2431 02:19:25.843538 # # snd_pcm_hw_params: Invalid argument
2432 02:19:25.849078 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2433 02:19:25.854659 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2434 02:19:25.860208 # # snd_pcm_hw_params: Invalid argument
2435 02:19:25.865883 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2436 02:19:25.866492 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2437 02:19:25.871279 # # snd_pcm_hw_params: Invalid argument
2438 02:19:25.876837 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2439 02:19:25.882394 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2440 02:19:25.882997 # # snd_pcm_hw_params: Invalid argument
2441 02:19:25.887911 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2442 02:19:25.893457 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2443 02:19:25.898959 # # snd_pcm_hw_params: Invalid argument
2444 02:19:25.904533 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2445 02:19:25.910103 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2446 02:19:25.910679 # # snd_pcm_hw_params: Invalid argument
2447 02:19:25.915680 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2448 02:19:25.921188 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2449 02:19:25.926861 # # snd_pcm_hw_params: Invalid argument
2450 02:19:25.932280 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2451 02:19:25.937837 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2452 02:19:25.938419 # # snd_pcm_hw_params: Invalid argument
2453 02:19:25.943383 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2454 02:19:25.948915 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2455 02:19:25.954453 # # snd_pcm_hw_params: Invalid argument
2456 02:19:25.960030 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2457 02:19:25.960607 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2458 02:19:25.965586 # # snd_pcm_hw_params: Invalid argument
2459 02:19:25.971101 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2460 02:19:25.976718 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2461 02:19:25.982210 # # snd_pcm_hw_params: Invalid argument
2462 02:19:25.987903 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2463 02:19:25.988517 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2464 02:19:25.993388 # # snd_pcm_hw_params: Invalid argument
2465 02:19:25.998834 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2466 02:19:26.004380 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2467 02:19:26.009963 # # snd_pcm_hw_params: Invalid argument
2468 02:19:26.015499 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2469 02:19:26.016140 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2470 02:19:26.021047 # # snd_pcm_hw_params: Invalid argument
2471 02:19:26.026595 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2472 02:19:26.032218 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2473 02:19:26.032837 # # snd_pcm_hw_params: Invalid argument
2474 02:19:26.037767 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2475 02:19:26.043216 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2476 02:19:26.048904 # # snd_pcm_hw_params: Invalid argument
2477 02:19:26.054325 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2478 02:19:26.059896 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2479 02:19:26.060421 # # snd_pcm_hw_params: Invalid argument
2480 02:19:26.065425 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2481 02:19:26.071074 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2482 02:19:26.076524 # # snd_pcm_hw_params: Invalid argument
2483 02:19:26.082057 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2484 02:19:26.087645 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2485 02:19:26.088205 # # snd_pcm_hw_params: Invalid argument
2486 02:19:26.093270 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2487 02:19:26.098818 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2488 02:19:26.104320 # # snd_pcm_hw_params: Invalid argument
2489 02:19:26.109891 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2490 02:19:26.115353 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2491 02:19:26.115864 # # snd_pcm_hw_params: Invalid argument
2492 02:19:26.120910 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2493 02:19:26.126421 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2494 02:19:26.132030 # # snd_pcm_hw_params: Invalid argument
2495 02:19:26.137544 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2496 02:19:26.143076 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2497 02:19:26.143580 # # snd_pcm_hw_params: Invalid argument
2498 02:19:26.148636 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2499 02:19:26.154168 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2500 02:19:26.159715 # # snd_pcm_hw_params: Invalid argument
2501 02:19:26.165346 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2502 02:19:26.170902 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2503 02:19:26.171423 # # snd_pcm_hw_params: Invalid argument
2504 02:19:26.176382 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2505 02:19:26.181939 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2506 02:19:26.187441 # # snd_pcm_hw_params: Invalid argument
2507 02:19:26.193021 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2508 02:19:26.198563 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2509 02:19:26.199066 # # snd_pcm_hw_params: Invalid argument
2510 02:19:26.204127 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2511 02:19:26.209688 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2512 02:19:26.215173 # # snd_pcm_hw_params: Invalid argument
2513 02:19:26.220768 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2514 02:19:26.226266 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2515 02:19:26.226768 # # snd_pcm_hw_params: Invalid argument
2516 02:19:26.231927 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2517 02:19:26.237358 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2518 02:19:26.242897 # # snd_pcm_hw_params: Invalid argument
2519 02:19:26.248522 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2520 02:19:26.254036 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2521 02:19:26.254553 # # snd_pcm_hw_params: Invalid argument
2522 02:19:26.259548 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2523 02:19:26.265083 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2524 02:19:26.270632 # # snd_pcm_hw_params: Invalid argument
2525 02:19:26.276263 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2526 02:19:26.281763 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2527 02:19:26.282265 # # snd_pcm_hw_params: Invalid argument
2528 02:19:26.287273 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2529 02:19:26.292913 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2530 02:19:26.298502 # # snd_pcm_hw_params: Invalid argument
2531 02:19:26.304130 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2532 02:19:26.309489 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2533 02:19:26.310022 # # snd_pcm_hw_params: Invalid argument
2534 02:19:26.315034 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2535 02:19:26.320568 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2536 02:19:26.326173 # # snd_pcm_hw_params: Invalid argument
2537 02:19:26.331670 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2538 02:19:26.332237 ok 2 selftests: alsa: pcm-test
2539 02:19:26.332710 # timeout set to 45
2540 02:19:26.337224 # selftests: alsa: test-pcmtest-driver
2541 02:19:26.337761 # TAP version 13
2542 02:19:26.338230 # 1..5
2543 02:19:26.342792 # # Starting 5 tests from 1 test cases.
2544 02:19:26.348301 # # RUN pcmtest.playback ...
2545 02:19:26.353926 # # SKIP Can't read patterns. Probably, module isn't loaded
2546 02:19:26.354492 # # OK pcmtest.playback
2547 02:19:26.364971 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2548 02:19:26.365508 # # RUN pcmtest.capture ...
2549 02:19:26.370555 # # SKIP Can't read patterns. Probably, module isn't loaded
2550 02:19:26.376136 # # OK pcmtest.capture
2551 02:19:26.381656 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2552 02:19:26.387188 # # RUN pcmtest.ni_capture ...
2553 02:19:26.392670 # # SKIP Can't read patterns. Probably, module isn't loaded
2554 02:19:26.398209 # # OK pcmtest.ni_capture
2555 02:19:26.403799 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2556 02:19:26.409294 # # RUN pcmtest.ni_playback ...
2557 02:19:26.415041 # # SKIP Can't read patterns. Probably, module isn't loaded
2558 02:19:26.415671 # # OK pcmtest.ni_playback
2559 02:19:26.426014 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2560 02:19:26.426616 # # RUN pcmtest.reset_ioctl ...
2561 02:19:26.437094 # # SKIP Can't read patterns. Probably, module isn't loaded
2562 02:19:26.437634 # # OK pcmtest.reset_ioctl
2563 02:19:26.448235 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2564 02:19:26.448770 # # PASSED: 5 / 5 tests passed.
2565 02:19:26.453776 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2566 02:19:26.459299 ok 3 selftests: alsa: test-pcmtest-driver
2567 02:19:26.459827 # timeout set to 45
2568 02:19:26.460358 # selftests: alsa: utimer-test
2569 02:19:26.464839 # TAP version 13
2570 02:19:26.465352 # 1..2
2571 02:19:26.470379 # # Starting 2 tests from 2 test cases.
2572 02:19:26.470886 # # RUN global.wrong_timers_test ...
2573 02:19:26.475999 # # OK global.wrong_timers_test
2574 02:19:26.481444 # ok 1 global.wrong_timers_test
2575 02:19:26.481955 # # RUN timer_f.utimer ...
2576 02:19:26.492544 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2577 02:19:26.498085 # # utimer: Test terminated by assertion
2578 02:19:26.498596 # # FAIL timer_f.utimer
2579 02:19:26.503763 # not ok 2 timer_f.utimer
2580 02:19:26.504310 # # FAILED: 1 / 2 tests passed.
2581 02:19:26.509183 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2582 02:19:26.513754 not ok 4 selftests: alsa: utimer-test # exit=1
2583 02:19:27.018919 alsa_mixer-test_get_value_LCALTA_60 pass
2584 02:19:27.025190 alsa_mixer-test_name_LCALTA_60 pass
2585 02:19:27.025804 alsa_mixer-test_write_default_LCALTA_60 pass
2586 02:19:27.029908 alsa_mixer-test_write_valid_LCALTA_60 pass
2587 02:19:27.033298 alsa_mixer-test_write_invalid_LCALTA_60 pass
2588 02:19:27.038870 alsa_mixer-test_event_missing_LCALTA_60 pass
2589 02:19:27.044413 alsa_mixer-test_event_spurious_LCALTA_60 pass
2590 02:19:27.044988 alsa_mixer-test_get_value_LCALTA_59 pass
2591 02:19:27.050012 alsa_mixer-test_name_LCALTA_59 pass
2592 02:19:27.053429 alsa_mixer-test_write_default_LCALTA_59 pass
2593 02:19:27.059000 alsa_mixer-test_write_valid_LCALTA_59 pass
2594 02:19:27.059554 alsa_mixer-test_write_invalid_LCALTA_59 pass
2595 02:19:27.064517 alsa_mixer-test_event_missing_LCALTA_59 pass
2596 02:19:27.070057 alsa_mixer-test_event_spurious_LCALTA_59 pass
2597 02:19:27.075573 alsa_mixer-test_get_value_LCALTA_58 pass
2598 02:19:27.076160 alsa_mixer-test_name_LCALTA_58 pass
2599 02:19:27.081154 alsa_mixer-test_write_default_LCALTA_58 pass
2600 02:19:27.086691 alsa_mixer-test_write_valid_LCALTA_58 pass
2601 02:19:27.087248 alsa_mixer-test_write_invalid_LCALTA_58 pass
2602 02:19:27.092256 alsa_mixer-test_event_missing_LCALTA_58 pass
2603 02:19:27.097882 alsa_mixer-test_event_spurious_LCALTA_58 pass
2604 02:19:27.098229 alsa_mixer-test_get_value_LCALTA_57 pass
2605 02:19:27.103345 alsa_mixer-test_name_LCALTA_57 pass
2606 02:19:27.108937 alsa_mixer-test_write_default_LCALTA_57 pass
2607 02:19:27.109280 alsa_mixer-test_write_valid_LCALTA_57 pass
2608 02:19:27.114460 alsa_mixer-test_write_invalid_LCALTA_57 pass
2609 02:19:27.120008 alsa_mixer-test_event_missing_LCALTA_57 pass
2610 02:19:27.120359 alsa_mixer-test_event_spurious_LCALTA_57 pass
2611 02:19:27.125586 alsa_mixer-test_get_value_LCALTA_56 pass
2612 02:19:27.131209 alsa_mixer-test_name_LCALTA_56 pass
2613 02:19:27.131812 alsa_mixer-test_write_default_LCALTA_56 pass
2614 02:19:27.136714 alsa_mixer-test_write_valid_LCALTA_56 pass
2615 02:19:27.142263 alsa_mixer-test_write_invalid_LCALTA_56 pass
2616 02:19:27.147785 alsa_mixer-test_event_missing_LCALTA_56 pass
2617 02:19:27.148399 alsa_mixer-test_event_spurious_LCALTA_56 pass
2618 02:19:27.153379 alsa_mixer-test_get_value_LCALTA_55 pass
2619 02:19:27.158911 alsa_mixer-test_name_LCALTA_55 pass
2620 02:19:27.159500 alsa_mixer-test_write_default_LCALTA_55 pass
2621 02:19:27.164437 alsa_mixer-test_write_valid_LCALTA_55 pass
2622 02:19:27.169969 alsa_mixer-test_write_invalid_LCALTA_55 pass
2623 02:19:27.170552 alsa_mixer-test_event_missing_LCALTA_55 pass
2624 02:19:27.175550 alsa_mixer-test_event_spurious_LCALTA_55 pass
2625 02:19:27.181099 alsa_mixer-test_get_value_LCALTA_54 pass
2626 02:19:27.181676 alsa_mixer-test_name_LCALTA_54 pass
2627 02:19:27.186620 alsa_mixer-test_write_default_LCALTA_54 pass
2628 02:19:27.192200 alsa_mixer-test_write_valid_LCALTA_54 pass
2629 02:19:27.192774 alsa_mixer-test_write_invalid_LCALTA_54 pass
2630 02:19:27.197832 alsa_mixer-test_event_missing_LCALTA_54 pass
2631 02:19:27.203354 alsa_mixer-test_event_spurious_LCALTA_54 pass
2632 02:19:27.208869 alsa_mixer-test_get_value_LCALTA_53 pass
2633 02:19:27.209519 alsa_mixer-test_name_LCALTA_53 pass
2634 02:19:27.214395 alsa_mixer-test_write_default_LCALTA_53 pass
2635 02:19:27.219905 alsa_mixer-test_write_valid_LCALTA_53 pass
2636 02:19:27.220303 alsa_mixer-test_write_invalid_LCALTA_53 pass
2637 02:19:27.225492 alsa_mixer-test_event_missing_LCALTA_53 pass
2638 02:19:27.231041 alsa_mixer-test_event_spurious_LCALTA_53 pass
2639 02:19:27.231897 alsa_mixer-test_get_value_LCALTA_52 pass
2640 02:19:27.236607 alsa_mixer-test_name_LCALTA_52 pass
2641 02:19:27.242180 alsa_mixer-test_write_default_LCALTA_52 pass
2642 02:19:27.242825 alsa_mixer-test_write_valid_LCALTA_52 pass
2643 02:19:27.247642 alsa_mixer-test_write_invalid_LCALTA_52 pass
2644 02:19:27.253058 alsa_mixer-test_event_missing_LCALTA_52 pass
2645 02:19:27.258613 alsa_mixer-test_event_spurious_LCALTA_52 pass
2646 02:19:27.258987 alsa_mixer-test_get_value_LCALTA_51 pass
2647 02:19:27.264160 alsa_mixer-test_name_LCALTA_51 pass
2648 02:19:27.269700 alsa_mixer-test_write_default_LCALTA_51 pass
2649 02:19:27.270231 alsa_mixer-test_write_valid_LCALTA_51 pass
2650 02:19:27.275268 alsa_mixer-test_write_invalid_LCALTA_51 pass
2651 02:19:27.280805 alsa_mixer-test_event_missing_LCALTA_51 pass
2652 02:19:27.281200 alsa_mixer-test_event_spurious_LCALTA_51 pass
2653 02:19:27.286365 alsa_mixer-test_get_value_LCALTA_50 pass
2654 02:19:27.291885 alsa_mixer-test_name_LCALTA_50 pass
2655 02:19:27.293280 alsa_mixer-test_write_default_LCALTA_50 pass
2656 02:19:27.297494 alsa_mixer-test_write_valid_LCALTA_50 pass
2657 02:19:27.303029 alsa_mixer-test_write_invalid_LCALTA_50 pass
2658 02:19:27.303665 alsa_mixer-test_event_missing_LCALTA_50 pass
2659 02:19:27.308886 alsa_mixer-test_event_spurious_LCALTA_50 pass
2660 02:19:27.314084 alsa_mixer-test_get_value_LCALTA_49 pass
2661 02:19:27.314720 alsa_mixer-test_name_LCALTA_49 pass
2662 02:19:27.319674 alsa_mixer-test_write_default_LCALTA_49 pass
2663 02:19:27.325188 alsa_mixer-test_write_valid_LCALTA_49 pass
2664 02:19:27.330770 alsa_mixer-test_write_invalid_LCALTA_49 pass
2665 02:19:27.331406 alsa_mixer-test_event_missing_LCALTA_49 pass
2666 02:19:27.336292 alsa_mixer-test_event_spurious_LCALTA_49 pass
2667 02:19:27.341859 alsa_mixer-test_get_value_LCALTA_48 pass
2668 02:19:27.342512 alsa_mixer-test_name_LCALTA_48 pass
2669 02:19:27.347384 alsa_mixer-test_write_default_LCALTA_48 pass
2670 02:19:27.353044 alsa_mixer-test_write_valid_LCALTA_48 pass
2671 02:19:27.353671 alsa_mixer-test_write_invalid_LCALTA_48 pass
2672 02:19:27.358471 alsa_mixer-test_event_missing_LCALTA_48 pass
2673 02:19:27.364117 alsa_mixer-test_event_spurious_LCALTA_48 pass
2674 02:19:27.364787 alsa_mixer-test_get_value_LCALTA_47 pass
2675 02:19:27.369630 alsa_mixer-test_name_LCALTA_47 pass
2676 02:19:27.375150 alsa_mixer-test_write_default_LCALTA_47 pass
2677 02:19:27.375825 alsa_mixer-test_write_valid_LCALTA_47 pass
2678 02:19:27.380732 alsa_mixer-test_write_invalid_LCALTA_47 pass
2679 02:19:27.386215 alsa_mixer-test_event_missing_LCALTA_47 pass
2680 02:19:27.391732 alsa_mixer-test_event_spurious_LCALTA_47 pass
2681 02:19:27.392442 alsa_mixer-test_get_value_LCALTA_46 pass
2682 02:19:27.397317 alsa_mixer-test_name_LCALTA_46 pass
2683 02:19:27.402909 alsa_mixer-test_write_default_LCALTA_46 pass
2684 02:19:27.403582 alsa_mixer-test_write_valid_LCALTA_46 pass
2685 02:19:27.408385 alsa_mixer-test_write_invalid_LCALTA_46 pass
2686 02:19:27.414170 alsa_mixer-test_event_missing_LCALTA_46 pass
2687 02:19:27.414916 alsa_mixer-test_event_spurious_LCALTA_46 pass
2688 02:19:27.419492 alsa_mixer-test_get_value_LCALTA_45 pass
2689 02:19:27.425047 alsa_mixer-test_name_LCALTA_45 pass
2690 02:19:27.425683 alsa_mixer-test_write_default_LCALTA_45 pass
2691 02:19:27.430602 alsa_mixer-test_write_valid_LCALTA_45 pass
2692 02:19:27.436146 alsa_mixer-test_write_invalid_LCALTA_45 pass
2693 02:19:27.441676 alsa_mixer-test_event_missing_LCALTA_45 pass
2694 02:19:27.442313 alsa_mixer-test_event_spurious_LCALTA_45 pass
2695 02:19:27.447221 alsa_mixer-test_get_value_LCALTA_44 pass
2696 02:19:27.447854 alsa_mixer-test_name_LCALTA_44 pass
2697 02:19:27.452828 alsa_mixer-test_write_default_LCALTA_44 pass
2698 02:19:27.459274 alsa_mixer-test_write_valid_LCALTA_44 pass
2699 02:19:27.464061 alsa_mixer-test_write_invalid_LCALTA_44 pass
2700 02:19:27.464811 alsa_mixer-test_event_missing_LCALTA_44 pass
2701 02:19:27.469431 alsa_mixer-test_event_spurious_LCALTA_44 pass
2702 02:19:27.475092 alsa_mixer-test_get_value_LCALTA_43 pass
2703 02:19:27.475744 alsa_mixer-test_name_LCALTA_43 pass
2704 02:19:27.480486 alsa_mixer-test_write_default_LCALTA_43 pass
2705 02:19:27.486038 alsa_mixer-test_write_valid_LCALTA_43 pass
2706 02:19:27.486671 alsa_mixer-test_write_invalid_LCALTA_43 pass
2707 02:19:27.491561 alsa_mixer-test_event_missing_LCALTA_43 pass
2708 02:19:27.497118 alsa_mixer-test_event_spurious_LCALTA_43 pass
2709 02:19:27.502701 alsa_mixer-test_get_value_LCALTA_42 pass
2710 02:19:27.503317 alsa_mixer-test_name_LCALTA_42 pass
2711 02:19:27.508263 alsa_mixer-test_write_default_LCALTA_42 pass
2712 02:19:27.513975 alsa_mixer-test_write_valid_LCALTA_42 pass
2713 02:19:27.514681 alsa_mixer-test_write_invalid_LCALTA_42 pass
2714 02:19:27.519332 alsa_mixer-test_event_missing_LCALTA_42 pass
2715 02:19:27.524958 alsa_mixer-test_event_spurious_LCALTA_42 pass
2716 02:19:27.525590 alsa_mixer-test_get_value_LCALTA_41 pass
2717 02:19:27.530424 alsa_mixer-test_name_LCALTA_41 pass
2718 02:19:27.536099 alsa_mixer-test_write_default_LCALTA_41 pass
2719 02:19:27.536732 alsa_mixer-test_write_valid_LCALTA_41 pass
2720 02:19:27.541679 alsa_mixer-test_write_invalid_LCALTA_41 pass
2721 02:19:27.547062 alsa_mixer-test_event_missing_LCALTA_41 pass
2722 02:19:27.547697 alsa_mixer-test_event_spurious_LCALTA_41 pass
2723 02:19:27.552622 alsa_mixer-test_get_value_LCALTA_40 pass
2724 02:19:27.558172 alsa_mixer-test_name_LCALTA_40 pass
2725 02:19:27.558809 alsa_mixer-test_write_default_LCALTA_40 pass
2726 02:19:27.563702 alsa_mixer-test_write_valid_LCALTA_40 pass
2727 02:19:27.569262 alsa_mixer-test_write_invalid_LCALTA_40 pass
2728 02:19:27.574919 alsa_mixer-test_event_missing_LCALTA_40 pass
2729 02:19:27.575548 alsa_mixer-test_event_spurious_LCALTA_40 pass
2730 02:19:27.580327 alsa_mixer-test_get_value_LCALTA_39 pass
2731 02:19:27.585930 alsa_mixer-test_name_LCALTA_39 pass
2732 02:19:27.586551 alsa_mixer-test_write_default_LCALTA_39 pass
2733 02:19:27.591418 alsa_mixer-test_write_valid_LCALTA_39 pass
2734 02:19:27.597244 alsa_mixer-test_write_invalid_LCALTA_39 pass
2735 02:19:27.597855 alsa_mixer-test_event_missing_LCALTA_39 pass
2736 02:19:27.602581 alsa_mixer-test_event_spurious_LCALTA_39 pass
2737 02:19:27.608105 alsa_mixer-test_get_value_LCALTA_38 pass
2738 02:19:27.608741 alsa_mixer-test_name_LCALTA_38 pass
2739 02:19:27.613632 alsa_mixer-test_write_default_LCALTA_38 pass
2740 02:19:27.619152 alsa_mixer-test_write_valid_LCALTA_38 pass
2741 02:19:27.619811 alsa_mixer-test_write_invalid_LCALTA_38 pass
2742 02:19:27.624708 alsa_mixer-test_event_missing_LCALTA_38 pass
2743 02:19:27.630268 alsa_mixer-test_event_spurious_LCALTA_38 pass
2744 02:19:27.636018 alsa_mixer-test_get_value_LCALTA_37 pass
2745 02:19:27.636644 alsa_mixer-test_name_LCALTA_37 pass
2746 02:19:27.641328 alsa_mixer-test_write_default_LCALTA_37 pass
2747 02:19:27.646937 alsa_mixer-test_write_valid_LCALTA_37 pass
2748 02:19:27.647558 alsa_mixer-test_write_invalid_LCALTA_37 pass
2749 02:19:27.652458 alsa_mixer-test_event_missing_LCALTA_37 pass
2750 02:19:27.658069 alsa_mixer-test_event_spurious_LCALTA_37 pass
2751 02:19:27.658692 alsa_mixer-test_get_value_LCALTA_36 pass
2752 02:19:27.663502 alsa_mixer-test_name_LCALTA_36 pass
2753 02:19:27.669076 alsa_mixer-test_write_default_LCALTA_36 pass
2754 02:19:27.669687 alsa_mixer-test_write_valid_LCALTA_36 pass
2755 02:19:27.674614 alsa_mixer-test_write_invalid_LCALTA_36 pass
2756 02:19:27.680278 alsa_mixer-test_event_missing_LCALTA_36 pass
2757 02:19:27.685827 alsa_mixer-test_event_spurious_LCALTA_36 pass
2758 02:19:27.686311 alsa_mixer-test_get_value_LCALTA_35 pass
2759 02:19:27.691236 alsa_mixer-test_name_LCALTA_35 pass
2760 02:19:27.696817 alsa_mixer-test_write_default_LCALTA_35 pass
2761 02:19:27.697305 alsa_mixer-test_write_valid_LCALTA_35 pass
2762 02:19:27.702323 alsa_mixer-test_write_invalid_LCALTA_35 pass
2763 02:19:27.707955 alsa_mixer-test_event_missing_LCALTA_35 pass
2764 02:19:27.708467 alsa_mixer-test_event_spurious_LCALTA_35 pass
2765 02:19:27.713447 alsa_mixer-test_get_value_LCALTA_34 pass
2766 02:19:27.719068 alsa_mixer-test_name_LCALTA_34 pass
2767 02:19:27.719545 alsa_mixer-test_write_default_LCALTA_34 pass
2768 02:19:27.724546 alsa_mixer-test_write_valid_LCALTA_34 pass
2769 02:19:27.730073 alsa_mixer-test_write_invalid_LCALTA_34 pass
2770 02:19:27.730550 alsa_mixer-test_event_missing_LCALTA_34 pass
2771 02:19:27.735874 alsa_mixer-test_event_spurious_LCALTA_34 pass
2772 02:19:27.741189 alsa_mixer-test_get_value_LCALTA_33 pass
2773 02:19:27.741665 alsa_mixer-test_name_LCALTA_33 pass
2774 02:19:27.746697 alsa_mixer-test_write_default_LCALTA_33 pass
2775 02:19:27.752236 alsa_mixer-test_write_valid_LCALTA_33 pass
2776 02:19:27.757815 alsa_mixer-test_write_invalid_LCALTA_33 pass
2777 02:19:27.758302 alsa_mixer-test_event_missing_LCALTA_33 pass
2778 02:19:27.763390 alsa_mixer-test_event_spurious_LCALTA_33 pass
2779 02:19:27.768991 alsa_mixer-test_get_value_LCALTA_32 pass
2780 02:19:27.769496 alsa_mixer-test_name_LCALTA_32 pass
2781 02:19:27.774490 alsa_mixer-test_write_default_LCALTA_32 pass
2782 02:19:27.780170 alsa_mixer-test_write_valid_LCALTA_32 pass
2783 02:19:27.780688 alsa_mixer-test_write_invalid_LCALTA_32 pass
2784 02:19:27.785594 alsa_mixer-test_event_missing_LCALTA_32 pass
2785 02:19:27.791185 alsa_mixer-test_event_spurious_LCALTA_32 pass
2786 02:19:27.791686 alsa_mixer-test_get_value_LCALTA_31 pass
2787 02:19:27.796680 alsa_mixer-test_name_LCALTA_31 pass
2788 02:19:27.802327 alsa_mixer-test_write_default_LCALTA_31 pass
2789 02:19:27.802836 alsa_mixer-test_write_valid_LCALTA_31 pass
2790 02:19:27.807803 alsa_mixer-test_write_invalid_LCALTA_31 pass
2791 02:19:27.813348 alsa_mixer-test_event_missing_LCALTA_31 pass
2792 02:19:27.819174 alsa_mixer-test_event_spurious_LCALTA_31 pass
2793 02:19:27.819679 alsa_mixer-test_get_value_LCALTA_30 pass
2794 02:19:27.824366 alsa_mixer-test_name_LCALTA_30 pass
2795 02:19:27.829964 alsa_mixer-test_write_default_LCALTA_30 pass
2796 02:19:27.830456 alsa_mixer-test_write_valid_LCALTA_30 pass
2797 02:19:27.835469 alsa_mixer-test_write_invalid_LCALTA_30 pass
2798 02:19:27.841340 alsa_mixer-test_event_missing_LCALTA_30 pass
2799 02:19:27.842068 alsa_mixer-test_event_spurious_LCALTA_30 pass
2800 02:19:27.846756 alsa_mixer-test_get_value_LCALTA_29 pass
2801 02:19:27.852383 alsa_mixer-test_name_LCALTA_29 pass
2802 02:19:27.853100 alsa_mixer-test_write_default_LCALTA_29 pass
2803 02:19:27.857835 alsa_mixer-test_write_valid_LCALTA_29 pass
2804 02:19:27.863389 alsa_mixer-test_write_invalid_LCALTA_29 pass
2805 02:19:27.868918 alsa_mixer-test_event_missing_LCALTA_29 pass
2806 02:19:27.869610 alsa_mixer-test_event_spurious_LCALTA_29 pass
2807 02:19:27.874637 alsa_mixer-test_get_value_LCALTA_28 pass
2808 02:19:27.875216 alsa_mixer-test_name_LCALTA_28 pass
2809 02:19:27.880077 alsa_mixer-test_write_default_LCALTA_28 pass
2810 02:19:27.885564 alsa_mixer-test_write_valid_LCALTA_28 pass
2811 02:19:27.891149 alsa_mixer-test_write_invalid_LCALTA_28 pass
2812 02:19:27.891844 alsa_mixer-test_event_missing_LCALTA_28 pass
2813 02:19:27.896639 alsa_mixer-test_event_spurious_LCALTA_28 pass
2814 02:19:27.902339 alsa_mixer-test_get_value_LCALTA_27 pass
2815 02:19:27.902978 alsa_mixer-test_name_LCALTA_27 pass
2816 02:19:27.907593 alsa_mixer-test_write_default_LCALTA_27 pass
2817 02:19:27.913149 alsa_mixer-test_write_valid_LCALTA_27 pass
2818 02:19:27.913763 alsa_mixer-test_write_invalid_LCALTA_27 pass
2819 02:19:27.918666 alsa_mixer-test_event_missing_LCALTA_27 pass
2820 02:19:27.924257 alsa_mixer-test_event_spurious_LCALTA_27 pass
2821 02:19:27.929855 alsa_mixer-test_get_value_LCALTA_26 pass
2822 02:19:27.930343 alsa_mixer-test_name_LCALTA_26 pass
2823 02:19:27.935278 alsa_mixer-test_write_default_LCALTA_26 skip
2824 02:19:27.940837 alsa_mixer-test_write_valid_LCALTA_26 skip
2825 02:19:27.941315 alsa_mixer-test_write_invalid_LCALTA_26 skip
2826 02:19:27.946390 alsa_mixer-test_event_missing_LCALTA_26 pass
2827 02:19:27.952018 alsa_mixer-test_event_spurious_LCALTA_26 pass
2828 02:19:27.952567 alsa_mixer-test_get_value_LCALTA_25 pass
2829 02:19:27.957455 alsa_mixer-test_name_LCALTA_25 pass
2830 02:19:27.963103 alsa_mixer-test_write_default_LCALTA_25 pass
2831 02:19:27.963580 alsa_mixer-test_write_valid_LCALTA_25 skip
2832 02:19:27.968568 alsa_mixer-test_write_invalid_LCALTA_25 skip
2833 02:19:27.974162 alsa_mixer-test_event_missing_LCALTA_25 pass
2834 02:19:27.974632 alsa_mixer-test_event_spurious_LCALTA_25 pass
2835 02:19:27.979667 alsa_mixer-test_get_value_LCALTA_24 pass
2836 02:19:27.985331 alsa_mixer-test_name_LCALTA_24 pass
2837 02:19:27.985799 alsa_mixer-test_write_default_LCALTA_24 skip
2838 02:19:27.990739 alsa_mixer-test_write_valid_LCALTA_24 skip
2839 02:19:27.996314 alsa_mixer-test_write_invalid_LCALTA_24 skip
2840 02:19:28.001869 alsa_mixer-test_event_missing_LCALTA_24 pass
2841 02:19:28.002330 alsa_mixer-test_event_spurious_LCALTA_24 pass
2842 02:19:28.007368 alsa_mixer-test_get_value_LCALTA_23 pass
2843 02:19:28.012952 alsa_mixer-test_name_LCALTA_23 pass
2844 02:19:28.013414 alsa_mixer-test_write_default_LCALTA_23 skip
2845 02:19:28.018497 alsa_mixer-test_write_valid_LCALTA_23 skip
2846 02:19:28.024172 alsa_mixer-test_write_invalid_LCALTA_23 skip
2847 02:19:28.024645 alsa_mixer-test_event_missing_LCALTA_23 pass
2848 02:19:28.029660 alsa_mixer-test_event_spurious_LCALTA_23 pass
2849 02:19:28.035171 alsa_mixer-test_get_value_LCALTA_22 pass
2850 02:19:28.035682 alsa_mixer-test_name_LCALTA_22 pass
2851 02:19:28.040673 alsa_mixer-test_write_default_LCALTA_22 pass
2852 02:19:28.046219 alsa_mixer-test_write_valid_LCALTA_22 pass
2853 02:19:28.046693 alsa_mixer-test_write_invalid_LCALTA_22 pass
2854 02:19:28.051767 alsa_mixer-test_event_missing_LCALTA_22 pass
2855 02:19:28.057347 alsa_mixer-test_event_spurious_LCALTA_22 pass
2856 02:19:28.062865 alsa_mixer-test_get_value_LCALTA_21 pass
2857 02:19:28.063343 alsa_mixer-test_name_LCALTA_21 pass
2858 02:19:28.068406 alsa_mixer-test_write_default_LCALTA_21 pass
2859 02:19:28.073975 alsa_mixer-test_write_valid_LCALTA_21 pass
2860 02:19:28.074448 alsa_mixer-test_write_invalid_LCALTA_21 pass
2861 02:19:28.079511 alsa_mixer-test_event_missing_LCALTA_21 pass
2862 02:19:28.085479 alsa_mixer-test_event_spurious_LCALTA_21 pass
2863 02:19:28.086099 alsa_mixer-test_get_value_LCALTA_20 pass
2864 02:19:28.090732 alsa_mixer-test_name_LCALTA_20 pass
2865 02:19:28.096356 alsa_mixer-test_write_default_LCALTA_20 pass
2866 02:19:28.096963 alsa_mixer-test_write_valid_LCALTA_20 pass
2867 02:19:28.101804 alsa_mixer-test_write_invalid_LCALTA_20 pass
2868 02:19:28.107524 alsa_mixer-test_event_missing_LCALTA_20 pass
2869 02:19:28.112810 alsa_mixer-test_event_spurious_LCALTA_20 pass
2870 02:19:28.113387 alsa_mixer-test_get_value_LCALTA_19 pass
2871 02:19:28.118352 alsa_mixer-test_name_LCALTA_19 pass
2872 02:19:28.123934 alsa_mixer-test_write_default_LCALTA_19 pass
2873 02:19:28.124573 alsa_mixer-test_write_valid_LCALTA_19 pass
2874 02:19:28.129572 alsa_mixer-test_write_invalid_LCALTA_19 pass
2875 02:19:28.135012 alsa_mixer-test_event_missing_LCALTA_19 pass
2876 02:19:28.135607 alsa_mixer-test_event_spurious_LCALTA_19 pass
2877 02:19:28.140574 alsa_mixer-test_get_value_LCALTA_18 pass
2878 02:19:28.146183 alsa_mixer-test_name_LCALTA_18 pass
2879 02:19:28.146769 alsa_mixer-test_write_default_LCALTA_18 pass
2880 02:19:28.151675 alsa_mixer-test_write_valid_LCALTA_18 pass
2881 02:19:28.157392 alsa_mixer-test_write_invalid_LCALTA_18 pass
2882 02:19:28.157997 alsa_mixer-test_event_missing_LCALTA_18 pass
2883 02:19:28.162780 alsa_mixer-test_event_spurious_LCALTA_18 pass
2884 02:19:28.168335 alsa_mixer-test_get_value_LCALTA_17 pass
2885 02:19:28.168959 alsa_mixer-test_name_LCALTA_17 pass
2886 02:19:28.173865 alsa_mixer-test_write_default_LCALTA_17 pass
2887 02:19:28.179451 alsa_mixer-test_write_valid_LCALTA_17 pass
2888 02:19:28.184917 alsa_mixer-test_write_invalid_LCALTA_17 pass
2889 02:19:28.185509 alsa_mixer-test_event_missing_LCALTA_17 pass
2890 02:19:28.190463 alsa_mixer-test_event_spurious_LCALTA_17 pass
2891 02:19:28.196066 alsa_mixer-test_get_value_LCALTA_16 pass
2892 02:19:28.196678 alsa_mixer-test_name_LCALTA_16 pass
2893 02:19:28.201658 alsa_mixer-test_write_default_LCALTA_16 pass
2894 02:19:28.207209 alsa_mixer-test_write_valid_LCALTA_16 pass
2895 02:19:28.207823 alsa_mixer-test_write_invalid_LCALTA_16 pass
2896 02:19:28.212683 alsa_mixer-test_event_missing_LCALTA_16 pass
2897 02:19:28.218244 alsa_mixer-test_event_spurious_LCALTA_16 pass
2898 02:19:28.218820 alsa_mixer-test_get_value_LCALTA_15 pass
2899 02:19:28.223819 alsa_mixer-test_name_LCALTA_15 pass
2900 02:19:28.229336 alsa_mixer-test_write_default_LCALTA_15 pass
2901 02:19:28.229934 alsa_mixer-test_write_valid_LCALTA_15 pass
2902 02:19:28.234868 alsa_mixer-test_write_invalid_LCALTA_15 pass
2903 02:19:28.240567 alsa_mixer-test_event_missing_LCALTA_15 pass
2904 02:19:28.245989 alsa_mixer-test_event_spurious_LCALTA_15 pass
2905 02:19:28.246586 alsa_mixer-test_get_value_LCALTA_14 pass
2906 02:19:28.251564 alsa_mixer-test_name_LCALTA_14 pass
2907 02:19:28.257129 alsa_mixer-test_write_default_LCALTA_14 pass
2908 02:19:28.257651 alsa_mixer-test_write_valid_LCALTA_14 pass
2909 02:19:28.262636 alsa_mixer-test_write_invalid_LCALTA_14 pass
2910 02:19:28.268292 alsa_mixer-test_event_missing_LCALTA_14 pass
2911 02:19:28.268811 alsa_mixer-test_event_spurious_LCALTA_14 pass
2912 02:19:28.273744 alsa_mixer-test_get_value_LCALTA_13 pass
2913 02:19:28.279250 alsa_mixer-test_name_LCALTA_13 pass
2914 02:19:28.279756 alsa_mixer-test_write_default_LCALTA_13 pass
2915 02:19:28.284812 alsa_mixer-test_write_valid_LCALTA_13 pass
2916 02:19:28.290338 alsa_mixer-test_write_invalid_LCALTA_13 pass
2917 02:19:28.295917 alsa_mixer-test_event_missing_LCALTA_13 pass
2918 02:19:28.296455 alsa_mixer-test_event_spurious_LCALTA_13 pass
2919 02:19:28.301488 alsa_mixer-test_get_value_LCALTA_12 pass
2920 02:19:28.301999 alsa_mixer-test_name_LCALTA_12 pass
2921 02:19:28.307005 alsa_mixer-test_write_default_LCALTA_12 pass
2922 02:19:28.312570 alsa_mixer-test_write_valid_LCALTA_12 pass
2923 02:19:28.318119 alsa_mixer-test_write_invalid_LCALTA_12 pass
2924 02:19:28.318622 alsa_mixer-test_event_missing_LCALTA_12 pass
2925 02:19:28.323622 alsa_mixer-test_event_spurious_LCALTA_12 pass
2926 02:19:28.329254 alsa_mixer-test_get_value_LCALTA_11 pass
2927 02:19:28.329776 alsa_mixer-test_name_LCALTA_11 pass
2928 02:19:28.334706 alsa_mixer-test_write_default_LCALTA_11 pass
2929 02:19:28.340358 alsa_mixer-test_write_valid_LCALTA_11 pass
2930 02:19:28.340884 alsa_mixer-test_write_invalid_LCALTA_11 pass
2931 02:19:28.345774 alsa_mixer-test_event_missing_LCALTA_11 pass
2932 02:19:28.351388 alsa_mixer-test_event_spurious_LCALTA_11 pass
2933 02:19:28.356920 alsa_mixer-test_get_value_LCALTA_10 pass
2934 02:19:28.357480 alsa_mixer-test_name_LCALTA_10 pass
2935 02:19:28.362514 alsa_mixer-test_write_default_LCALTA_10 pass
2936 02:19:28.368070 alsa_mixer-test_write_valid_LCALTA_10 pass
2937 02:19:28.368597 alsa_mixer-test_write_invalid_LCALTA_10 pass
2938 02:19:28.373609 alsa_mixer-test_event_missing_LCALTA_10 pass
2939 02:19:28.379234 alsa_mixer-test_event_spurious_LCALTA_10 pass
2940 02:19:28.379839 alsa_mixer-test_get_value_LCALTA_9 pass
2941 02:19:28.384708 alsa_mixer-test_name_LCALTA_9 pass
2942 02:19:28.390256 alsa_mixer-test_write_default_LCALTA_9 pass
2943 02:19:28.390768 alsa_mixer-test_write_valid_LCALTA_9 pass
2944 02:19:28.395758 alsa_mixer-test_write_invalid_LCALTA_9 pass
2945 02:19:28.401818 alsa_mixer-test_event_missing_LCALTA_9 pass
2946 02:19:28.402321 alsa_mixer-test_event_spurious_LCALTA_9 pass
2947 02:19:28.406807 alsa_mixer-test_get_value_LCALTA_8 pass
2948 02:19:28.412388 alsa_mixer-test_name_LCALTA_8 pass
2949 02:19:28.412882 alsa_mixer-test_write_default_LCALTA_8 pass
2950 02:19:28.417905 alsa_mixer-test_write_valid_LCALTA_8 pass
2951 02:19:28.423443 alsa_mixer-test_write_invalid_LCALTA_8 pass
2952 02:19:28.423940 alsa_mixer-test_event_missing_LCALTA_8 pass
2953 02:19:28.429144 alsa_mixer-test_event_spurious_LCALTA_8 pass
2954 02:19:28.434620 alsa_mixer-test_get_value_LCALTA_7 pass
2955 02:19:28.435130 alsa_mixer-test_name_LCALTA_7 pass
2956 02:19:28.440132 alsa_mixer-test_write_default_LCALTA_7 pass
2957 02:19:28.445709 alsa_mixer-test_write_valid_LCALTA_7 pass
2958 02:19:28.446207 alsa_mixer-test_write_invalid_LCALTA_7 pass
2959 02:19:28.451270 alsa_mixer-test_event_missing_LCALTA_7 pass
2960 02:19:28.456974 alsa_mixer-test_event_spurious_LCALTA_7 pass
2961 02:19:28.457516 alsa_mixer-test_get_value_LCALTA_6 pass
2962 02:19:28.462279 alsa_mixer-test_name_LCALTA_6 pass
2963 02:19:28.467807 alsa_mixer-test_write_default_LCALTA_6 pass
2964 02:19:28.468359 alsa_mixer-test_write_valid_LCALTA_6 pass
2965 02:19:28.473380 alsa_mixer-test_write_invalid_LCALTA_6 pass
2966 02:19:28.478906 alsa_mixer-test_event_missing_LCALTA_6 pass
2967 02:19:28.479416 alsa_mixer-test_event_spurious_LCALTA_6 pass
2968 02:19:28.484464 alsa_mixer-test_get_value_LCALTA_5 pass
2969 02:19:28.490079 alsa_mixer-test_name_LCALTA_5 pass
2970 02:19:28.490585 alsa_mixer-test_write_default_LCALTA_5 pass
2971 02:19:28.495586 alsa_mixer-test_write_valid_LCALTA_5 pass
2972 02:19:28.501280 alsa_mixer-test_write_invalid_LCALTA_5 pass
2973 02:19:28.501797 alsa_mixer-test_event_missing_LCALTA_5 pass
2974 02:19:28.506741 alsa_mixer-test_event_spurious_LCALTA_5 pass
2975 02:19:28.512318 alsa_mixer-test_get_value_LCALTA_4 pass
2976 02:19:28.512837 alsa_mixer-test_name_LCALTA_4 pass
2977 02:19:28.517792 alsa_mixer-test_write_default_LCALTA_4 pass
2978 02:19:28.523302 alsa_mixer-test_write_valid_LCALTA_4 pass
2979 02:19:28.523836 alsa_mixer-test_write_invalid_LCALTA_4 pass
2980 02:19:28.528865 alsa_mixer-test_event_missing_LCALTA_4 pass
2981 02:19:28.534436 alsa_mixer-test_event_spurious_LCALTA_4 pass
2982 02:19:28.540017 alsa_mixer-test_get_value_LCALTA_3 pass
2983 02:19:28.540553 alsa_mixer-test_name_LCALTA_3 pass
2984 02:19:28.545544 alsa_mixer-test_write_default_LCALTA_3 pass
2985 02:19:28.546122 alsa_mixer-test_write_valid_LCALTA_3 pass
2986 02:19:28.551158 alsa_mixer-test_write_invalid_LCALTA_3 pass
2987 02:19:28.556613 alsa_mixer-test_event_missing_LCALTA_3 pass
2988 02:19:28.562310 alsa_mixer-test_event_spurious_LCALTA_3 pass
2989 02:19:28.562850 alsa_mixer-test_get_value_LCALTA_2 pass
2990 02:19:28.567715 alsa_mixer-test_name_LCALTA_2 pass
2991 02:19:28.573234 alsa_mixer-test_write_default_LCALTA_2 pass
2992 02:19:28.573770 alsa_mixer-test_write_valid_LCALTA_2 pass
2993 02:19:28.578766 alsa_mixer-test_write_invalid_LCALTA_2 pass
2994 02:19:28.584301 alsa_mixer-test_event_missing_LCALTA_2 pass
2995 02:19:28.584820 alsa_mixer-test_event_spurious_LCALTA_2 pass
2996 02:19:28.589919 alsa_mixer-test_get_value_LCALTA_1 pass
2997 02:19:28.595407 alsa_mixer-test_name_LCALTA_1 pass
2998 02:19:28.595925 alsa_mixer-test_write_default_LCALTA_1 pass
2999 02:19:28.600960 alsa_mixer-test_write_valid_LCALTA_1 pass
3000 02:19:28.606495 alsa_mixer-test_write_invalid_LCALTA_1 pass
3001 02:19:28.607003 alsa_mixer-test_event_missing_LCALTA_1 pass
3002 02:19:28.612436 alsa_mixer-test_event_spurious_LCALTA_1 pass
3003 02:19:28.617686 alsa_mixer-test_get_value_LCALTA_0 pass
3004 02:19:28.618202 alsa_mixer-test_name_LCALTA_0 pass
3005 02:19:28.623320 alsa_mixer-test_write_default_LCALTA_0 pass
3006 02:19:28.628737 alsa_mixer-test_write_valid_LCALTA_0 pass
3007 02:19:28.629279 alsa_mixer-test_write_invalid_LCALTA_0 pass
3008 02:19:28.634363 alsa_mixer-test_event_missing_LCALTA_0 pass
3009 02:19:28.639816 alsa_mixer-test_event_spurious_LCALTA_0 pass
3010 02:19:28.640372 alsa_mixer-test pass
3011 02:19:28.645425 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
3012 02:19:28.650852 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
3013 02:19:28.656421 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
3014 02:19:28.656954 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
3015 02:19:28.662027 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
3016 02:19:28.667543 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
3017 02:19:28.673222 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
3018 02:19:28.678652 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
3019 02:19:28.684264 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
3020 02:19:28.684822 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
3021 02:19:28.689753 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
3022 02:19:28.695298 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
3023 02:19:28.700786 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
3024 02:19:28.706369 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
3025 02:19:28.706892 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
3026 02:19:28.711865 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
3027 02:19:28.717457 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
3028 02:19:28.723076 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
3029 02:19:28.728550 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
3030 02:19:28.734123 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
3031 02:19:28.734635 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
3032 02:19:28.739638 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
3033 02:19:28.745354 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
3034 02:19:28.750787 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
3035 02:19:28.756351 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
3036 02:19:28.761909 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
3037 02:19:28.767411 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
3038 02:19:28.768084 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
3039 02:19:28.772974 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
3040 02:19:28.778535 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
3041 02:19:28.784105 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
3042 02:19:28.789611 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
3043 02:19:28.795212 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
3044 02:19:28.795841 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
3045 02:19:28.800707 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
3046 02:19:28.806345 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
3047 02:19:28.811781 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
3048 02:19:28.817368 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
3049 02:19:28.822910 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
3050 02:19:28.823522 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
3051 02:19:28.828488 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
3052 02:19:28.833992 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
3053 02:19:28.834622 alsa_pcm-test pass
3054 02:19:28.845115 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3055 02:19:28.850665 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3056 02:19:28.861740 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3057 02:19:28.872890 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3058 02:19:28.878307 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3059 02:19:28.883791 alsa_test-pcmtest-driver pass
3060 02:19:28.884219 alsa_utimer-test_global_wrong_timers_test pass
3061 02:19:28.889329 alsa_utimer-test_timer_f_utimer fail
3062 02:19:28.889710 alsa_utimer-test fail
3063 02:19:28.894861 + ../../utils/send-to-lava.sh ./output/result.txt
3064 02:19:28.900619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
3065 02:19:28.901350 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
3067 02:19:28.906007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
3068 02:19:28.906612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
3070 02:19:28.915876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
3071 02:19:28.916532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
3073 02:19:28.938796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
3074 02:19:28.939459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
3076 02:19:28.990057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
3077 02:19:28.990725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
3079 02:19:29.041562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
3080 02:19:29.042221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
3082 02:19:29.086786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
3083 02:19:29.087690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
3085 02:19:29.131671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
3086 02:19:29.132501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
3088 02:19:29.180443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
3089 02:19:29.181207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
3091 02:19:29.223974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
3092 02:19:29.224771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
3094 02:19:29.270513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
3095 02:19:29.271265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
3097 02:19:29.316516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
3098 02:19:29.317280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
3100 02:19:29.363538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
3101 02:19:29.364391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
3103 02:19:29.413819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
3104 02:19:29.414812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
3106 02:19:29.500291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
3107 02:19:29.501249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
3109 02:19:29.544907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
3110 02:19:29.545741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
3112 02:19:29.591371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
3113 02:19:29.592187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
3115 02:19:29.662536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
3116 02:19:29.663316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
3118 02:19:29.709360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
3119 02:19:29.710116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
3121 02:19:29.775929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
3122 02:19:29.776820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
3124 02:19:29.830761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
3125 02:19:29.831442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
3127 02:19:29.877917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
3128 02:19:29.878631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
3130 02:19:29.940071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
3131 02:19:29.940806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
3133 02:19:29.990314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
3134 02:19:29.991052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
3136 02:19:30.046806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
3137 02:19:30.047529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
3139 02:19:30.140983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3140 02:19:30.141708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3142 02:19:30.241617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3143 02:19:30.242281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3145 02:19:30.322659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3146 02:19:30.323343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3148 02:19:30.377933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3149 02:19:30.382799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3151 02:19:30.445476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3152 02:19:30.446502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3154 02:19:30.499653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3155 02:19:30.500693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3157 02:19:30.556911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3158 02:19:30.557860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3160 02:19:30.603060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3161 02:19:30.603745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3163 02:19:30.646928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3164 02:19:30.647859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3166 02:19:30.704983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3167 02:19:30.705940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3169 02:19:30.764284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3170 02:19:30.765196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3172 02:19:30.818484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3173 02:19:30.819408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3175 02:19:30.870722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3176 02:19:30.871378 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3178 02:19:30.917315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3179 02:19:30.918314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3181 02:19:30.966970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3182 02:19:30.967964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3184 02:19:31.020685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3185 02:19:31.021562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3187 02:19:31.066291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3188 02:19:31.067248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3190 02:19:31.116824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3191 02:19:31.117676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3193 02:19:31.161686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3194 02:19:31.162625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3196 02:19:31.212044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3197 02:19:31.212965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3199 02:19:31.268833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3200 02:19:31.269801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3202 02:19:31.332694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3203 02:19:31.333554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3205 02:19:31.378496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3206 02:19:31.379328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3208 02:19:31.434542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3209 02:19:31.435389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3211 02:19:31.486208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3212 02:19:31.487058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3214 02:19:31.531918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3215 02:19:31.532582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3217 02:19:31.580273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3218 02:19:31.580908 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3220 02:19:31.630247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3221 02:19:31.631098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3223 02:19:31.673898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3224 02:19:31.674748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3226 02:19:31.728202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3227 02:19:31.729057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3229 02:19:31.780129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3230 02:19:31.780986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3232 02:19:31.829619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3233 02:19:31.830440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3235 02:19:31.872263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3236 02:19:31.873194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3238 02:19:31.928035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3239 02:19:31.928897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3241 02:19:31.986811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3242 02:19:31.987732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3244 02:19:32.038871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3245 02:19:32.039652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3247 02:19:32.085394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3248 02:19:32.086242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3250 02:19:32.139325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3251 02:19:32.140145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3253 02:19:32.183753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3254 02:19:32.184631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3256 02:19:32.236117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3257 02:19:32.236924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3259 02:19:32.285156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3260 02:19:32.285991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3262 02:19:32.333151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3263 02:19:32.333889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3265 02:19:32.378100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3266 02:19:32.378989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3268 02:19:32.430283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3269 02:19:32.431100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3271 02:19:32.481086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3272 02:19:32.481938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3274 02:19:32.538276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3275 02:19:32.539166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3277 02:19:32.588013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3278 02:19:32.588806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3280 02:19:32.633998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3281 02:19:32.634789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3283 02:19:32.681307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3284 02:19:32.682082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3286 02:19:32.733524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3287 02:19:32.734290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3289 02:19:32.780584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3290 02:19:32.781351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3292 02:19:32.826738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3293 02:19:32.827493 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3295 02:19:32.881662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3296 02:19:32.882424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3298 02:19:32.935030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3299 02:19:32.935792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3301 02:19:32.988595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3302 02:19:32.989474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3304 02:19:33.046034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3305 02:19:33.046901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3307 02:19:33.091050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3308 02:19:33.091824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3310 02:19:33.136926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3311 02:19:33.137715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3313 02:19:33.184093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3314 02:19:33.184862 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3316 02:19:33.230533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3317 02:19:33.231292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3319 02:19:33.276861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3320 02:19:33.277608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3322 02:19:33.321565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3323 02:19:33.322330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3325 02:19:33.368759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3326 02:19:33.369509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3328 02:19:33.417148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3329 02:19:33.417899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3331 02:19:33.467148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3332 02:19:33.467959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3334 02:19:33.515092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3335 02:19:33.515971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3337 02:19:33.568088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3338 02:19:33.568875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3340 02:19:33.612354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3341 02:19:33.613124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3343 02:19:33.667655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3344 02:19:33.668515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3346 02:19:33.713165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3347 02:19:33.713932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3349 02:19:33.762077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3350 02:19:33.762826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3352 02:19:33.823871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3353 02:19:33.824668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3355 02:19:33.868288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3356 02:19:33.869194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3358 02:19:33.921289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3359 02:19:33.922152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3361 02:19:33.965428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3362 02:19:33.966276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3364 02:19:34.014544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3365 02:19:34.015467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3367 02:19:34.069323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3368 02:19:34.070272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3370 02:19:34.126674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3371 02:19:34.127594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3373 02:19:34.179249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3374 02:19:34.180150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3376 02:19:34.240200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3377 02:19:34.241092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3379 02:19:34.287502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3380 02:19:34.288434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3382 02:19:34.336721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3383 02:19:34.337610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3385 02:19:34.396100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3386 02:19:34.397038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3388 02:19:34.448384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3389 02:19:34.449313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3391 02:19:34.498657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3392 02:19:34.499580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3394 02:19:34.544515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3395 02:19:34.545387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3397 02:19:34.597761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3398 02:19:34.598610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3400 02:19:34.649692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3401 02:19:34.650545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3403 02:19:34.699442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3404 02:19:34.700349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3406 02:19:34.793734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3407 02:19:34.794605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3409 02:19:34.838695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3410 02:19:34.839529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3412 02:19:34.882136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3413 02:19:34.882965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3415 02:19:34.928719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3416 02:19:34.929537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3418 02:19:34.989378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3419 02:19:34.990210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3421 02:19:35.040366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3422 02:19:35.041264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3424 02:19:35.093442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3425 02:19:35.094294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3427 02:19:35.138462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3428 02:19:35.139286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3430 02:19:35.194463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3431 02:19:35.195299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3433 02:19:35.242381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3434 02:19:35.243219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3436 02:19:35.287195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3437 02:19:35.288062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3439 02:19:35.341699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3440 02:19:35.342541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3442 02:19:35.386712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3443 02:19:35.387644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3445 02:19:35.440904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3446 02:19:35.441777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3448 02:19:35.484299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3449 02:19:35.485193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3451 02:19:35.544106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3452 02:19:35.544978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3454 02:19:35.592564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3455 02:19:35.593419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3457 02:19:35.641443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3458 02:19:35.642338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3460 02:19:35.693648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3461 02:19:35.694517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3463 02:19:35.739147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3464 02:19:35.740050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3466 02:19:35.794300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3467 02:19:35.795158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3469 02:19:35.854870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3470 02:19:35.855725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3472 02:19:35.909498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3473 02:19:35.910381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3475 02:19:35.961306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3476 02:19:35.962188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3478 02:19:36.012380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3479 02:19:36.013250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3481 02:19:36.084362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3482 02:19:36.085231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3484 02:19:36.130273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3485 02:19:36.131143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3487 02:19:36.186552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3488 02:19:36.187416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3490 02:19:36.238952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3491 02:19:36.239821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3493 02:19:36.291542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3494 02:19:36.292445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3496 02:19:36.344029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3497 02:19:36.344978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3499 02:19:36.400202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3500 02:19:36.401062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3502 02:19:36.452533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3503 02:19:36.453371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3505 02:19:36.505020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3506 02:19:36.505983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3508 02:19:36.556584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3509 02:19:36.557568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3511 02:19:36.609290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3512 02:19:36.610275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3514 02:19:36.660717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3515 02:19:36.661670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3517 02:19:36.713932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3518 02:19:36.714858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3520 02:19:36.761169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3521 02:19:36.762164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3523 02:19:36.814545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3524 02:19:36.815413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3526 02:19:36.866385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3527 02:19:36.867303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3529 02:19:36.917794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3530 02:19:36.918662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3532 02:19:36.969586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3533 02:19:36.970508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3535 02:19:37.016896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3536 02:19:37.017575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3538 02:19:37.075511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3539 02:19:37.076500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3541 02:19:37.129678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3542 02:19:37.130585 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3544 02:19:37.172962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3545 02:19:37.173839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3547 02:19:37.226224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3548 02:19:37.227171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3550 02:19:37.282233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3551 02:19:37.283139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3553 02:19:37.334888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3554 02:19:37.335823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3556 02:19:37.380981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3557 02:19:37.381919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3559 02:19:37.437036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3560 02:19:37.437957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3562 02:19:37.489224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3563 02:19:37.490149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3565 02:19:37.536780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3566 02:19:37.537606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3568 02:19:37.593549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3569 02:19:37.594234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3571 02:19:37.650813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3572 02:19:37.651494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3574 02:19:37.705354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3575 02:19:37.706027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3577 02:19:37.760710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3578 02:19:37.761385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3580 02:19:37.805318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3581 02:19:37.805970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3583 02:19:37.857018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3584 02:19:37.857695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3586 02:19:37.906928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3587 02:19:37.907689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3589 02:19:37.954385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3590 02:19:37.955691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3592 02:19:38.013224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3593 02:19:38.013975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3595 02:19:38.057270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3596 02:19:38.057964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3598 02:19:38.104729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3599 02:19:38.105421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3601 02:19:38.149267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3602 02:19:38.149947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3604 02:19:38.193942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3605 02:19:38.194621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3607 02:19:38.244709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3608 02:19:38.245398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3610 02:19:38.296329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3611 02:19:38.297021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3613 02:19:38.341851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3614 02:19:38.342545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3616 02:19:38.391265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3617 02:19:38.391935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3619 02:19:38.440735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3620 02:19:38.441426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3622 02:19:38.485084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3623 02:19:38.485868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3625 02:19:38.542820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3626 02:19:38.543514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3628 02:19:38.589240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3629 02:19:38.589955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3631 02:19:38.636823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3632 02:19:38.637539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3634 02:19:38.689914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3635 02:19:38.690572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3637 02:19:38.741033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3638 02:19:38.741667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3640 02:19:38.786337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3641 02:19:38.786987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3643 02:19:38.835378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3644 02:19:38.836061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3646 02:19:38.891008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3647 02:19:38.891659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3649 02:19:38.945000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3650 02:19:38.945640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3652 02:19:38.996504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3653 02:19:38.997135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3655 02:19:39.043403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3656 02:19:39.044061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3658 02:19:39.098598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3659 02:19:39.099253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3661 02:19:39.147562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3662 02:19:39.148539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3664 02:19:39.192419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3665 02:19:39.193333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3667 02:19:39.239140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3668 02:19:39.240068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3670 02:19:39.287823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3671 02:19:39.288739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3673 02:19:39.339480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3674 02:19:39.340155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3676 02:19:39.391375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3677 02:19:39.392076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3679 02:19:39.442630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3680 02:19:39.443304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3682 02:19:39.494027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3683 02:19:39.494727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3685 02:19:39.558217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3686 02:19:39.558910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3688 02:19:39.607505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3689 02:19:39.608534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3691 02:19:39.666755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3692 02:19:39.667614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3694 02:19:39.710278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3695 02:19:39.711129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3697 02:19:39.764992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3698 02:19:39.765871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3700 02:19:39.814431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3701 02:19:39.815262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3703 02:19:39.876098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3704 02:19:39.877003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3706 02:19:39.939859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3707 02:19:39.940539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3709 02:19:39.982933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3710 02:19:39.983616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3712 02:19:40.031262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3713 02:19:40.031938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3715 02:19:40.081830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3716 02:19:40.082696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3718 02:19:40.135093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3719 02:19:40.135895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3721 02:19:40.192486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3722 02:19:40.193367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3724 02:19:40.246298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3725 02:19:40.247131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3727 02:19:40.296344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3728 02:19:40.297209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3730 02:19:40.342515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3731 02:19:40.343316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3733 02:19:40.393758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3734 02:19:40.394635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3736 02:19:40.445008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3737 02:19:40.445856 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3739 02:19:40.490917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3740 02:19:40.491892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3742 02:19:40.544515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3743 02:19:40.545189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3745 02:19:40.608655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3746 02:19:40.609336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3748 02:19:40.662174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3749 02:19:40.663305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3751 02:19:40.719542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3752 02:19:40.720191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3754 02:19:40.766593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3755 02:19:40.767225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3757 02:19:40.821579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3758 02:19:40.822228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3760 02:19:40.870021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3761 02:19:40.870695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3763 02:19:40.916351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3764 02:19:40.917003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3766 02:19:40.973250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3767 02:19:40.973976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3769 02:19:41.049265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3770 02:19:41.049973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3772 02:19:41.105738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3773 02:19:41.106494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3775 02:19:41.182968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3776 02:19:41.183650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3778 02:19:41.251912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3779 02:19:41.252682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3781 02:19:41.307076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3782 02:19:41.307781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3784 02:19:41.367622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3785 02:19:41.368320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3787 02:19:41.430953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3788 02:19:41.431653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3790 02:19:41.483251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3791 02:19:41.483916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3793 02:19:41.535188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3794 02:19:41.536119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3796 02:19:41.582849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3797 02:19:41.583777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3799 02:19:41.637693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3800 02:19:41.638604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3802 02:19:41.697665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3803 02:19:41.698525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3805 02:19:41.759474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3806 02:19:41.760133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3808 02:19:41.807550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3809 02:19:41.808258 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3811 02:19:41.868798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3812 02:19:41.869490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3814 02:19:41.932967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3815 02:19:41.936282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3817 02:19:42.011643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3818 02:19:42.012630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3820 02:19:42.056319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3821 02:19:42.057217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3823 02:19:42.108746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3824 02:19:42.109701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3826 02:19:42.165428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3827 02:19:42.166420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3829 02:19:42.225452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3830 02:19:42.226131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3832 02:19:42.288942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3833 02:19:42.289688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3835 02:19:42.340009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3836 02:19:42.340670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3838 02:19:42.405372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3839 02:19:42.406181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3841 02:19:42.474569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3842 02:19:42.475236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3844 02:19:42.521643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3845 02:19:42.522313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3847 02:19:42.585211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3848 02:19:42.585855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3850 02:19:42.656763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3851 02:19:42.657514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3853 02:19:42.717552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3854 02:19:42.718434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3856 02:19:42.772445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3857 02:19:42.773551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3859 02:19:42.829179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3860 02:19:42.830065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3862 02:19:42.945265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3863 02:19:42.946208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3865 02:19:42.974529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3866 02:19:42.975422 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3868 02:19:43.013209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3869 02:19:43.013929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3871 02:19:43.072732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3872 02:19:43.073658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3874 02:19:43.126122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3875 02:19:43.127016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3877 02:19:43.177332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3878 02:19:43.178243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3880 02:19:43.237990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3881 02:19:43.238984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3883 02:19:43.299071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3884 02:19:43.300144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3886 02:19:43.362367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3887 02:19:43.363026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3889 02:19:43.412890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3890 02:19:43.413538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3892 02:19:43.461808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3893 02:19:43.462477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3895 02:19:43.522074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3896 02:19:43.522777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3898 02:19:43.585535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3899 02:19:43.586210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3901 02:19:43.639487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3902 02:19:43.640120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3904 02:19:43.687703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3905 02:19:43.688367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3907 02:19:43.738378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3908 02:19:43.739019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3910 02:19:43.795525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3911 02:19:43.796171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3913 02:19:43.847180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3914 02:19:43.847845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3916 02:19:43.894291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3917 02:19:43.894968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3919 02:19:43.948954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3920 02:19:43.949638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3922 02:19:43.995768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3923 02:19:43.996454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3925 02:19:44.051853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3926 02:19:44.052538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3928 02:19:44.098979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3929 02:19:44.099621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3931 02:19:44.141343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3932 02:19:44.141994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3934 02:19:44.192196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3935 02:19:44.192838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3937 02:19:44.246529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3938 02:19:44.247169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3940 02:19:44.286404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3941 02:19:44.287047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3943 02:19:44.335323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3944 02:19:44.335973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3946 02:19:44.379873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3947 02:19:44.380820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3949 02:19:44.427850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3950 02:19:44.428745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3952 02:19:44.472826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3953 02:19:44.473489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3955 02:19:44.530965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3956 02:19:44.531627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3958 02:19:44.583901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3959 02:19:44.584589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3961 02:19:44.641219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3962 02:19:44.641873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3964 02:19:44.689495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3965 02:19:44.690189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3967 02:19:44.756038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3968 02:19:44.756715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3970 02:19:44.801037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3971 02:19:44.801713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3973 02:19:44.855463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3974 02:19:44.856167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3976 02:19:44.904769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3977 02:19:44.905445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3979 02:19:44.950770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3980 02:19:44.951433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3982 02:19:45.004118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3983 02:19:45.004782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3985 02:19:45.062364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3986 02:19:45.063025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3988 02:19:45.107241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3989 02:19:45.107975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3991 02:19:45.159457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3992 02:19:45.160108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3994 02:19:45.212213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3995 02:19:45.213168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3997 02:19:45.276645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3998 02:19:45.277509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
4000 02:19:45.321033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
4001 02:19:45.321779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
4003 02:19:45.383338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
4004 02:19:45.384189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
4006 02:19:45.437505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
4007 02:19:45.438357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
4009 02:19:45.490116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
4010 02:19:45.490853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
4012 02:19:45.538030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
4013 02:19:45.538835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
4015 02:19:45.590490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
4016 02:19:45.591238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
4018 02:19:45.641682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
4019 02:19:45.642569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
4021 02:19:45.695446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
4022 02:19:45.696353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
4024 02:19:45.753750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
4025 02:19:45.756195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
4027 02:19:45.802583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
4028 02:19:45.803248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
4030 02:19:45.856254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
4031 02:19:45.856903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
4033 02:19:45.926239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
4034 02:19:45.926878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
4036 02:19:45.993149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
4037 02:19:45.994056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
4039 02:19:46.042283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
4040 02:19:46.042935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
4042 02:19:46.098851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
4043 02:19:46.099504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
4045 02:19:46.150888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
4046 02:19:46.151811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
4048 02:19:46.195119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
4049 02:19:46.196079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
4051 02:19:46.249129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
4052 02:19:46.250105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
4054 02:19:46.306238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
4055 02:19:46.307263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
4057 02:19:46.365743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
4058 02:19:46.366668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
4060 02:19:46.416195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
4061 02:19:46.417140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
4063 02:19:46.469497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
4064 02:19:46.470404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
4066 02:19:46.514995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
4067 02:19:46.515927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
4069 02:19:46.565510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
4070 02:19:46.566449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
4072 02:19:46.608999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
4073 02:19:46.609923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
4075 02:19:46.662869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
4076 02:19:46.663807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
4078 02:19:46.706591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
4079 02:19:46.707502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
4081 02:19:46.772421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
4082 02:19:46.773328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
4084 02:19:46.829687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
4085 02:19:46.830574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
4087 02:19:46.881766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
4088 02:19:46.882648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
4090 02:19:46.932366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
4091 02:19:46.933386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
4093 02:19:46.976620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
4094 02:19:46.977470 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
4096 02:19:47.031235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
4097 02:19:47.032109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
4099 02:19:47.078390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
4100 02:19:47.079250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
4102 02:19:47.135081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
4103 02:19:47.135965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
4105 02:19:47.187578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
4106 02:19:47.188472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
4108 02:19:47.246311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
4109 02:19:47.247034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
4111 02:19:47.290615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
4112 02:19:47.291260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
4114 02:19:47.345608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
4115 02:19:47.346272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
4117 02:19:47.396789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
4118 02:19:47.397811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
4120 02:19:47.457230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
4121 02:19:47.458177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
4123 02:19:47.505552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
4124 02:19:47.506468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
4126 02:19:47.554551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
4127 02:19:47.555521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
4129 02:19:47.603112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
4130 02:19:47.604059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
4132 02:19:47.661102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
4133 02:19:47.662025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
4135 02:19:47.708741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
4136 02:19:47.709674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
4138 02:19:47.754328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
4139 02:19:47.755268 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4141 02:19:47.811419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4142 02:19:47.812343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4144 02:19:47.859463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4145 02:19:47.860613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4147 02:19:47.915427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4148 02:19:47.916373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4150 02:19:47.964198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4151 02:19:47.965072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4153 02:19:48.009064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4154 02:19:48.009825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4156 02:19:48.057338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4157 02:19:48.058202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4159 02:19:48.114236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4160 02:19:48.115109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4162 02:19:48.164812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4163 02:19:48.165570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4165 02:19:48.220172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4166 02:19:48.220914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4168 02:19:48.268834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4169 02:19:48.269571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4171 02:19:48.320707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4172 02:19:48.321564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4174 02:19:48.366774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4175 02:19:48.367534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4177 02:19:48.414279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4178 02:19:48.415323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4180 02:19:48.466171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4181 02:19:48.466996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4183 02:19:48.520857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4184 02:19:48.521709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4186 02:19:48.567822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4187 02:19:48.568637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4189 02:19:48.615380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4190 02:19:48.616382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4192 02:19:48.660922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4193 02:19:48.662049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4195 02:19:48.707945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4196 02:19:48.709059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4198 02:19:48.759654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4199 02:19:48.760632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4201 02:19:48.818268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4202 02:19:48.819198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4204 02:19:48.872652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4205 02:19:48.873334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4207 02:19:48.926217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4208 02:19:48.926886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4210 02:19:48.971361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4211 02:19:48.972062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4213 02:19:49.025628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4214 02:19:49.026295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4216 02:19:49.068954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4217 02:19:49.069601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4219 02:19:49.121318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4220 02:19:49.122621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4222 02:19:49.179303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4223 02:19:49.180148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4225 02:19:49.223910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4226 02:19:49.224704 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4228 02:19:49.277305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4229 02:19:49.278022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4231 02:19:49.332289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4232 02:19:49.333004 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4234 02:19:49.376832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4235 02:19:49.377689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4237 02:19:49.436822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4238 02:19:49.437682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4240 02:19:49.487394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4241 02:19:49.489017 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4243 02:19:49.531808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4244 02:19:49.532655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4246 02:19:49.582249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4247 02:19:49.583249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4249 02:19:49.630787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4250 02:19:49.631652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4252 02:19:49.685489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4253 02:19:49.686323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4255 02:19:49.735813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4256 02:19:49.736753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4258 02:19:49.794679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4259 02:19:49.795565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4261 02:19:49.849082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4262 02:19:49.849918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4264 02:19:49.892432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4265 02:19:49.893314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4267 02:19:49.949028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4268 02:19:49.949881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4270 02:19:50.001930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4271 02:19:50.002806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4273 02:19:50.047088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4274 02:19:50.047977 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4276 02:19:50.097716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4277 02:19:50.098574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4279 02:19:50.150719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4280 02:19:50.151598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4282 02:19:50.201650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4283 02:19:50.202517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4285 02:19:50.244629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4286 02:19:50.245497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4288 02:19:50.298329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4289 02:19:50.299343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4291 02:19:50.352812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4292 02:19:50.353766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4294 02:19:50.402611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4295 02:19:50.403266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4297 02:19:50.464204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4298 02:19:50.464847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4300 02:19:50.516143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4301 02:19:50.516799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4303 02:19:50.566118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4304 02:19:50.566735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4306 02:19:50.614246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4307 02:19:50.614936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4309 02:19:50.657248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4310 02:19:50.658087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4312 02:19:50.710004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4313 02:19:50.710759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4315 02:19:50.754828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4316 02:19:50.755586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4318 02:19:50.799926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4319 02:19:50.800762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4321 02:19:50.845894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4322 02:19:50.846704 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4324 02:19:50.923604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4325 02:19:50.924447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4327 02:19:50.956554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4328 02:19:50.957185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4330 02:19:51.002331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4331 02:19:51.002983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4333 02:19:51.047427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4334 02:19:51.048084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4336 02:19:51.098232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4337 02:19:51.098975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4339 02:19:51.143924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4340 02:19:51.144711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4342 02:19:51.202521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4343 02:19:51.203258 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4345 02:19:51.250399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4346 02:19:51.251138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4348 02:19:51.292747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4350 02:19:51.295640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4351 02:19:51.349238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4352 02:19:51.349958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4354 02:19:51.411568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4355 02:19:51.412357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4357 02:19:51.457679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4359 02:19:51.460758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4360 02:19:51.512868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4361 02:19:51.513694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4363 02:19:51.562820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4364 02:19:51.563674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4366 02:19:51.605737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4367 02:19:51.606509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4369 02:19:51.654722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4370 02:19:51.655479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4372 02:19:51.704799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4373 02:19:51.705549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4375 02:19:51.753156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4376 02:19:51.753894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4378 02:19:51.810498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4379 02:19:51.811260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4381 02:19:51.858735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4382 02:19:51.859464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4384 02:19:51.909665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4385 02:19:51.910385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4387 02:19:51.965888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4388 02:19:51.966674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4390 02:19:52.019216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4391 02:19:52.020234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4393 02:19:52.066503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4394 02:19:52.067285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4396 02:19:52.121044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4397 02:19:52.121828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4399 02:19:52.166377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4400 02:19:52.167159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4402 02:19:52.217883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4403 02:19:52.218734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4405 02:19:52.270585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4406 02:19:52.271376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4408 02:19:52.320713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4409 02:19:52.321480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4411 02:19:52.372609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4412 02:19:52.373359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4414 02:19:52.431817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4415 02:19:52.432738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4417 02:19:52.479134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4418 02:19:52.479903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4420 02:19:52.537711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4421 02:19:52.538473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4423 02:19:52.581612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4424 02:19:52.582311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4426 02:19:52.623728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4427 02:19:52.624613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4429 02:19:52.678444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4430 02:19:52.679202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4432 02:19:52.732334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4433 02:19:52.733122 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4435 02:19:52.782350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4436 02:19:52.783117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4438 02:19:52.832462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4439 02:19:52.833247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4441 02:19:52.893592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4442 02:19:52.894283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4444 02:19:52.945504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4445 02:19:52.946352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4447 02:19:52.989852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4448 02:19:52.990638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4450 02:19:53.038862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4451 02:19:53.039630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4453 02:19:53.090015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4454 02:19:53.090776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4456 02:19:53.137371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4457 02:19:53.138120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4459 02:19:53.182904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4460 02:19:53.183666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4462 02:19:53.243851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4463 02:19:53.244860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4465 02:19:53.295812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4466 02:19:53.296753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4468 02:19:53.340780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4469 02:19:53.341782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4471 02:19:53.390190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4472 02:19:53.391069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4474 02:19:53.433669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4475 02:19:53.434545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4477 02:19:53.483093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4478 02:19:53.484027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4480 02:19:53.545684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4481 02:19:53.546567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4483 02:19:53.598192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4484 02:19:53.599067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4486 02:19:53.644058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4487 02:19:53.644933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4489 02:19:53.690779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4490 02:19:53.691633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4492 02:19:53.743782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4493 02:19:53.744682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4495 02:19:53.789109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4496 02:19:53.790026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4498 02:19:53.850388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4499 02:19:53.851184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4501 02:19:53.901283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4502 02:19:53.902133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4504 02:19:53.948211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4506 02:19:53.953382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4507 02:19:53.953847 + set +x
4508 02:19:53.959370 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 964271_1.6.2.4.5>
4509 02:19:53.959830 <LAVA_TEST_RUNNER EXIT>
4510 02:19:53.960540 Received signal: <ENDRUN> 1_kselftest-alsa 964271_1.6.2.4.5
4511 02:19:53.960995 Ending use of test pattern.
4512 02:19:53.961403 Ending test lava.1_kselftest-alsa (964271_1.6.2.4.5), duration 41.07
4514 02:19:53.962917 ok: lava_test_shell seems to have completed
4515 02:19:53.985881 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4516 02:19:53.987648 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4517 02:19:53.988253 end: 3 lava-test-retry (duration 00:00:42) [common]
4518 02:19:53.988833 start: 4 finalize (timeout 00:06:03) [common]
4519 02:19:53.989424 start: 4.1 power-off (timeout 00:00:30) [common]
4520 02:19:53.990379 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4521 02:19:54.049039 >> OK - accepted request
4522 02:19:54.050984 Returned 0 in 0 seconds
4523 02:19:54.152240 end: 4.1 power-off (duration 00:00:00) [common]
4525 02:19:54.154060 start: 4.2 read-feedback (timeout 00:06:03) [common]
4526 02:19:54.155203 Listened to connection for namespace 'common' for up to 1s
4527 02:19:55.155959 Finalising connection for namespace 'common'
4528 02:19:55.156505 Disconnecting from shell: Finalise
4529 02:19:55.156792 / #
4530 02:19:55.257596 end: 4.2 read-feedback (duration 00:00:01) [common]
4531 02:19:55.258389 end: 4 finalize (duration 00:00:01) [common]
4532 02:19:55.259077 Cleaning after the job
4533 02:19:55.259668 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/ramdisk
4534 02:19:55.267118 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/kernel
4535 02:19:55.275651 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/dtb
4536 02:19:55.277062 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/nfsrootfs
4537 02:19:55.401693 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964271/tftp-deploy-4cjq8gop/modules
4538 02:19:55.421644 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/964271
4539 02:19:59.184349 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/964271
4540 02:19:59.184899 Job finished correctly