Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:12:16.613712 lava-dispatcher, installed at version: 2024.01
2 02:12:16.614854 start: 0 validate
3 02:12:16.615356 Start time: 2024-11-09 02:12:16.615324+00:00 (UTC)
4 02:12:16.615923 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:12:16.616500 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:12:16.660544 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:12:16.661101 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-246-gdbbaaaa6179b%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:12:16.693868 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:12:16.694499 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-246-gdbbaaaa6179b%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:12:16.731173 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:12:16.731717 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:12:16.764904 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:12:16.765418 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-246-gdbbaaaa6179b%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 02:12:16.805700 validate duration: 0.19
16 02:12:16.807175 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:12:16.807787 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:12:16.808424 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:12:16.809411 Not decompressing ramdisk as can be used compressed.
20 02:12:16.810202 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 02:12:16.810719 saving as /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/ramdisk/initrd.cpio.gz
22 02:12:16.811223 total size: 5628169 (5 MB)
23 02:12:16.855541 progress 0 % (0 MB)
24 02:12:16.864264 progress 5 % (0 MB)
25 02:12:16.873307 progress 10 % (0 MB)
26 02:12:16.881234 progress 15 % (0 MB)
27 02:12:16.889419 progress 20 % (1 MB)
28 02:12:16.894315 progress 25 % (1 MB)
29 02:12:16.898535 progress 30 % (1 MB)
30 02:12:16.902687 progress 35 % (1 MB)
31 02:12:16.906439 progress 40 % (2 MB)
32 02:12:16.910528 progress 45 % (2 MB)
33 02:12:16.914260 progress 50 % (2 MB)
34 02:12:16.918426 progress 55 % (2 MB)
35 02:12:16.922497 progress 60 % (3 MB)
36 02:12:16.926293 progress 65 % (3 MB)
37 02:12:16.930409 progress 70 % (3 MB)
38 02:12:16.934079 progress 75 % (4 MB)
39 02:12:16.938160 progress 80 % (4 MB)
40 02:12:16.941814 progress 85 % (4 MB)
41 02:12:16.945821 progress 90 % (4 MB)
42 02:12:16.949785 progress 95 % (5 MB)
43 02:12:16.953131 progress 100 % (5 MB)
44 02:12:16.953789 5 MB downloaded in 0.14 s (37.65 MB/s)
45 02:12:16.954314 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:12:16.955201 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:12:16.955492 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:12:16.955761 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:12:16.956297 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm64/defconfig/gcc-12/kernel/Image
51 02:12:16.956558 saving as /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/kernel/Image
52 02:12:16.956766 total size: 45713920 (43 MB)
53 02:12:16.956976 No compression specified
54 02:12:16.996448 progress 0 % (0 MB)
55 02:12:17.026103 progress 5 % (2 MB)
56 02:12:17.055351 progress 10 % (4 MB)
57 02:12:17.084384 progress 15 % (6 MB)
58 02:12:17.114160 progress 20 % (8 MB)
59 02:12:17.144587 progress 25 % (10 MB)
60 02:12:17.174192 progress 30 % (13 MB)
61 02:12:17.202827 progress 35 % (15 MB)
62 02:12:17.231164 progress 40 % (17 MB)
63 02:12:17.259832 progress 45 % (19 MB)
64 02:12:17.288184 progress 50 % (21 MB)
65 02:12:17.317040 progress 55 % (24 MB)
66 02:12:17.346116 progress 60 % (26 MB)
67 02:12:17.374068 progress 65 % (28 MB)
68 02:12:17.402683 progress 70 % (30 MB)
69 02:12:17.431126 progress 75 % (32 MB)
70 02:12:17.460260 progress 80 % (34 MB)
71 02:12:17.488857 progress 85 % (37 MB)
72 02:12:17.519166 progress 90 % (39 MB)
73 02:12:17.548414 progress 95 % (41 MB)
74 02:12:17.576794 progress 100 % (43 MB)
75 02:12:17.577324 43 MB downloaded in 0.62 s (70.25 MB/s)
76 02:12:17.577793 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:12:17.578607 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:12:17.578879 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:12:17.579142 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:12:17.579617 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 02:12:17.579885 saving as /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/dtb/meson-g12b-a311d-libretech-cc.dtb
83 02:12:17.580120 total size: 54703 (0 MB)
84 02:12:17.580328 No compression specified
85 02:12:17.622568 progress 59 % (0 MB)
86 02:12:17.623391 progress 100 % (0 MB)
87 02:12:17.623936 0 MB downloaded in 0.04 s (1.19 MB/s)
88 02:12:17.624425 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:12:17.625231 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:12:17.625491 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:12:17.625751 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:12:17.626212 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 02:12:17.626455 saving as /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/nfsrootfs/full.rootfs.tar
95 02:12:17.626658 total size: 120894716 (115 MB)
96 02:12:17.626866 Using unxz to decompress xz
97 02:12:17.665117 progress 0 % (0 MB)
98 02:12:18.460078 progress 5 % (5 MB)
99 02:12:19.303853 progress 10 % (11 MB)
100 02:12:20.091731 progress 15 % (17 MB)
101 02:12:20.822332 progress 20 % (23 MB)
102 02:12:21.413486 progress 25 % (28 MB)
103 02:12:22.234962 progress 30 % (34 MB)
104 02:12:23.027059 progress 35 % (40 MB)
105 02:12:23.398804 progress 40 % (46 MB)
106 02:12:23.789552 progress 45 % (51 MB)
107 02:12:24.500433 progress 50 % (57 MB)
108 02:12:25.394833 progress 55 % (63 MB)
109 02:12:26.176046 progress 60 % (69 MB)
110 02:12:26.929751 progress 65 % (74 MB)
111 02:12:27.707173 progress 70 % (80 MB)
112 02:12:28.534891 progress 75 % (86 MB)
113 02:12:29.318452 progress 80 % (92 MB)
114 02:12:30.075479 progress 85 % (98 MB)
115 02:12:30.920570 progress 90 % (103 MB)
116 02:12:31.689126 progress 95 % (109 MB)
117 02:12:32.517641 progress 100 % (115 MB)
118 02:12:32.530259 115 MB downloaded in 14.90 s (7.74 MB/s)
119 02:12:32.530876 end: 1.4.1 http-download (duration 00:00:15) [common]
121 02:12:32.531706 end: 1.4 download-retry (duration 00:00:15) [common]
122 02:12:32.531973 start: 1.5 download-retry (timeout 00:09:44) [common]
123 02:12:32.532795 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 02:12:32.533643 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm64/defconfig/gcc-12/modules.tar.xz
125 02:12:32.534165 saving as /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/modules/modules.tar
126 02:12:32.534580 total size: 11610740 (11 MB)
127 02:12:32.535002 Using unxz to decompress xz
128 02:12:32.578941 progress 0 % (0 MB)
129 02:12:32.645294 progress 5 % (0 MB)
130 02:12:32.718526 progress 10 % (1 MB)
131 02:12:32.814903 progress 15 % (1 MB)
132 02:12:32.905748 progress 20 % (2 MB)
133 02:12:32.985317 progress 25 % (2 MB)
134 02:12:33.060963 progress 30 % (3 MB)
135 02:12:33.139252 progress 35 % (3 MB)
136 02:12:33.211191 progress 40 % (4 MB)
137 02:12:33.286218 progress 45 % (5 MB)
138 02:12:33.369666 progress 50 % (5 MB)
139 02:12:33.448525 progress 55 % (6 MB)
140 02:12:33.533723 progress 60 % (6 MB)
141 02:12:33.614413 progress 65 % (7 MB)
142 02:12:33.694328 progress 70 % (7 MB)
143 02:12:33.771482 progress 75 % (8 MB)
144 02:12:33.854623 progress 80 % (8 MB)
145 02:12:33.934226 progress 85 % (9 MB)
146 02:12:34.013286 progress 90 % (9 MB)
147 02:12:34.093231 progress 95 % (10 MB)
148 02:12:34.170543 progress 100 % (11 MB)
149 02:12:34.182227 11 MB downloaded in 1.65 s (6.72 MB/s)
150 02:12:34.182788 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:12:34.183624 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:12:34.183895 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 02:12:34.184457 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 02:12:51.847288 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/964261/extract-nfsrootfs-ms1e5r2r
156 02:12:51.847893 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
157 02:12:51.848234 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 02:12:51.848993 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0
159 02:12:51.849621 makedir: /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin
160 02:12:51.850005 makedir: /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/tests
161 02:12:51.850414 makedir: /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/results
162 02:12:51.850865 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-add-keys
163 02:12:51.851531 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-add-sources
164 02:12:51.852162 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-background-process-start
165 02:12:51.853456 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-background-process-stop
166 02:12:51.854111 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-common-functions
167 02:12:51.854691 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-echo-ipv4
168 02:12:51.855260 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-install-packages
169 02:12:51.855852 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-installed-packages
170 02:12:51.856463 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-os-build
171 02:12:51.857084 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-probe-channel
172 02:12:51.857617 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-probe-ip
173 02:12:51.858334 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-target-ip
174 02:12:51.858903 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-target-mac
175 02:12:51.859404 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-target-storage
176 02:12:51.859928 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-test-case
177 02:12:51.860540 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-test-event
178 02:12:51.861050 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-test-feedback
179 02:12:51.861863 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-test-raise
180 02:12:51.862404 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-test-reference
181 02:12:51.862932 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-test-runner
182 02:12:51.863453 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-test-set
183 02:12:51.863947 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-test-shell
184 02:12:51.864583 Updating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-add-keys (debian)
185 02:12:51.865429 Updating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-add-sources (debian)
186 02:12:51.866180 Updating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-install-packages (debian)
187 02:12:51.866819 Updating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-installed-packages (debian)
188 02:12:51.867393 Updating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/bin/lava-os-build (debian)
189 02:12:51.867868 Creating /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/environment
190 02:12:51.868501 LAVA metadata
191 02:12:51.868804 - LAVA_JOB_ID=964261
192 02:12:51.869024 - LAVA_DISPATCHER_IP=192.168.6.2
193 02:12:51.869424 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 02:12:51.871446 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 02:12:51.871812 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 02:12:51.872051 skipped lava-vland-overlay
197 02:12:51.872300 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 02:12:51.872557 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 02:12:51.872786 skipped lava-multinode-overlay
200 02:12:51.873030 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 02:12:51.873282 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 02:12:51.873540 Loading test definitions
203 02:12:51.873826 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 02:12:51.874048 Using /lava-964261 at stage 0
205 02:12:51.877607 uuid=964261_1.6.2.4.1 testdef=None
206 02:12:51.878304 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 02:12:51.878879 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 02:12:51.882112 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 02:12:51.882971 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 02:12:51.886716 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 02:12:51.887618 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 02:12:51.890172 runner path: /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/0/tests/0_timesync-off test_uuid 964261_1.6.2.4.1
215 02:12:51.891262 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 02:12:51.892214 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 02:12:51.892454 Using /lava-964261 at stage 0
219 02:12:51.892909 Fetching tests from https://github.com/kernelci/test-definitions.git
220 02:12:51.893235 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/0/tests/1_kselftest-rtc'
221 02:12:55.357142 Running '/usr/bin/git checkout kernelci.org
222 02:12:55.682965 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 02:12:55.685631 uuid=964261_1.6.2.4.5 testdef=None
224 02:12:55.686435 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 02:12:55.688025 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 02:12:55.693730 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 02:12:55.695371 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 02:12:55.702908 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 02:12:55.704698 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 02:12:55.711970 runner path: /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/0/tests/1_kselftest-rtc test_uuid 964261_1.6.2.4.5
234 02:12:55.712597 BOARD='meson-g12b-a311d-libretech-cc'
235 02:12:55.713004 BRANCH='broonie-sound'
236 02:12:55.713396 SKIPFILE='/dev/null'
237 02:12:55.713792 SKIP_INSTALL='True'
238 02:12:55.714182 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-246-gdbbaaaa6179b/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 02:12:55.714580 TST_CASENAME=''
240 02:12:55.714968 TST_CMDFILES='rtc'
241 02:12:55.716100 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 02:12:55.717689 Creating lava-test-runner.conf files
244 02:12:55.718096 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/964261/lava-overlay-sgbpb2d0/lava-964261/0 for stage 0
245 02:12:55.718785 - 0_timesync-off
246 02:12:55.719264 - 1_kselftest-rtc
247 02:12:55.719940 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 02:12:55.720628 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 02:13:18.969899 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 02:13:18.970353 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 02:13:18.970619 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 02:13:18.970891 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 02:13:18.971154 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 02:13:19.606734 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 02:13:19.607215 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 02:13:19.607469 extracting modules file /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964261/extract-nfsrootfs-ms1e5r2r
257 02:13:20.966818 extracting modules file /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964261/extract-overlay-ramdisk-04b9oy1l/ramdisk
258 02:13:22.351910 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 02:13:22.352419 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 02:13:22.352700 [common] Applying overlay to NFS
261 02:13:22.352915 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964261/compress-overlay-qvuc1rtw/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/964261/extract-nfsrootfs-ms1e5r2r
262 02:13:25.114003 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 02:13:25.114462 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 02:13:25.114735 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 02:13:25.114965 Converting downloaded kernel to a uImage
266 02:13:25.115275 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/kernel/Image /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/kernel/uImage
267 02:13:25.592546 output: Image Name:
268 02:13:25.592975 output: Created: Sat Nov 9 02:13:25 2024
269 02:13:25.593186 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 02:13:25.593392 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 02:13:25.593595 output: Load Address: 01080000
272 02:13:25.593796 output: Entry Point: 01080000
273 02:13:25.593995 output:
274 02:13:25.594328 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 02:13:25.594599 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 02:13:25.594869 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 02:13:25.595123 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 02:13:25.595380 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 02:13:25.595637 Building ramdisk /var/lib/lava/dispatcher/tmp/964261/extract-overlay-ramdisk-04b9oy1l/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/964261/extract-overlay-ramdisk-04b9oy1l/ramdisk
280 02:13:27.729397 >> 166792 blocks
281 02:13:35.407630 Adding RAMdisk u-boot header.
282 02:13:35.408424 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/964261/extract-overlay-ramdisk-04b9oy1l/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/964261/extract-overlay-ramdisk-04b9oy1l/ramdisk.cpio.gz.uboot
283 02:13:35.660161 output: Image Name:
284 02:13:35.660801 output: Created: Sat Nov 9 02:13:35 2024
285 02:13:35.661259 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 02:13:35.661677 output: Data Size: 23432455 Bytes = 22883.26 KiB = 22.35 MiB
287 02:13:35.662103 output: Load Address: 00000000
288 02:13:35.662509 output: Entry Point: 00000000
289 02:13:35.662915 output:
290 02:13:35.663934 rename /var/lib/lava/dispatcher/tmp/964261/extract-overlay-ramdisk-04b9oy1l/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/ramdisk/ramdisk.cpio.gz.uboot
291 02:13:35.664694 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 02:13:35.665250 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 02:13:35.665786 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 02:13:35.666252 No LXC device requested
295 02:13:35.666761 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 02:13:35.667279 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 02:13:35.667782 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 02:13:35.668232 Checking files for TFTP limit of 4294967296 bytes.
299 02:13:35.670876 end: 1 tftp-deploy (duration 00:01:19) [common]
300 02:13:35.671457 start: 2 uboot-action (timeout 00:05:00) [common]
301 02:13:35.672026 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 02:13:35.672549 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 02:13:35.673066 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 02:13:35.673606 Using kernel file from prepare-kernel: 964261/tftp-deploy-wqquv6vj/kernel/uImage
305 02:13:35.674242 substitutions:
306 02:13:35.674661 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 02:13:35.675072 - {DTB_ADDR}: 0x01070000
308 02:13:35.675478 - {DTB}: 964261/tftp-deploy-wqquv6vj/dtb/meson-g12b-a311d-libretech-cc.dtb
309 02:13:35.675884 - {INITRD}: 964261/tftp-deploy-wqquv6vj/ramdisk/ramdisk.cpio.gz.uboot
310 02:13:35.676329 - {KERNEL_ADDR}: 0x01080000
311 02:13:35.676732 - {KERNEL}: 964261/tftp-deploy-wqquv6vj/kernel/uImage
312 02:13:35.677136 - {LAVA_MAC}: None
313 02:13:35.677576 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/964261/extract-nfsrootfs-ms1e5r2r
314 02:13:35.677984 - {NFS_SERVER_IP}: 192.168.6.2
315 02:13:35.678382 - {PRESEED_CONFIG}: None
316 02:13:35.678782 - {PRESEED_LOCAL}: None
317 02:13:35.679176 - {RAMDISK_ADDR}: 0x08000000
318 02:13:35.679567 - {RAMDISK}: 964261/tftp-deploy-wqquv6vj/ramdisk/ramdisk.cpio.gz.uboot
319 02:13:35.679964 - {ROOT_PART}: None
320 02:13:35.680389 - {ROOT}: None
321 02:13:35.680784 - {SERVER_IP}: 192.168.6.2
322 02:13:35.681177 - {TEE_ADDR}: 0x83000000
323 02:13:35.681567 - {TEE}: None
324 02:13:35.681961 Parsed boot commands:
325 02:13:35.682345 - setenv autoload no
326 02:13:35.682736 - setenv initrd_high 0xffffffff
327 02:13:35.683124 - setenv fdt_high 0xffffffff
328 02:13:35.683509 - dhcp
329 02:13:35.683895 - setenv serverip 192.168.6.2
330 02:13:35.684320 - tftpboot 0x01080000 964261/tftp-deploy-wqquv6vj/kernel/uImage
331 02:13:35.684717 - tftpboot 0x08000000 964261/tftp-deploy-wqquv6vj/ramdisk/ramdisk.cpio.gz.uboot
332 02:13:35.685112 - tftpboot 0x01070000 964261/tftp-deploy-wqquv6vj/dtb/meson-g12b-a311d-libretech-cc.dtb
333 02:13:35.685505 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/964261/extract-nfsrootfs-ms1e5r2r,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 02:13:35.685909 - bootm 0x01080000 0x08000000 0x01070000
335 02:13:35.686410 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 02:13:35.687905 start: 2.3 connect-device (timeout 00:05:00) [common]
338 02:13:35.688364 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 02:13:35.703093 Setting prompt string to ['lava-test: # ']
340 02:13:35.704636 end: 2.3 connect-device (duration 00:00:00) [common]
341 02:13:35.705285 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 02:13:35.705883 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 02:13:35.706437 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 02:13:35.707600 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 02:13:35.744398 >> OK - accepted request
346 02:13:35.746559 Returned 0 in 0 seconds
347 02:13:35.847624 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 02:13:35.849283 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 02:13:35.849865 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 02:13:35.850388 Setting prompt string to ['Hit any key to stop autoboot']
352 02:13:35.850853 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 02:13:35.852451 Trying 192.168.56.21...
354 02:13:35.852936 Connected to conserv1.
355 02:13:35.853357 Escape character is '^]'.
356 02:13:35.853784
357 02:13:35.854201 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 02:13:35.854628
359 02:13:46.892891 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 02:13:46.893717 bl2_stage_init 0x01
361 02:13:46.894322 bl2_stage_init 0x81
362 02:13:46.898605 hw id: 0x0000 - pwm id 0x01
363 02:13:46.899286 bl2_stage_init 0xc1
364 02:13:46.899831 bl2_stage_init 0x02
365 02:13:46.900436
366 02:13:46.904139 L0:00000000
367 02:13:46.904797 L1:20000703
368 02:13:46.905319 L2:00008067
369 02:13:46.905851 L3:14000000
370 02:13:46.909697 B2:00402000
371 02:13:46.910287 B1:e0f83180
372 02:13:46.910804
373 02:13:46.911312 TE: 58124
374 02:13:46.911816
375 02:13:46.915316 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 02:13:46.915877
377 02:13:46.916438 Board ID = 1
378 02:13:46.920818 Set A53 clk to 24M
379 02:13:46.921392 Set A73 clk to 24M
380 02:13:46.921906 Set clk81 to 24M
381 02:13:46.926390 A53 clk: 1200 MHz
382 02:13:46.926840 A73 clk: 1200 MHz
383 02:13:46.927242 CLK81: 166.6M
384 02:13:46.927632 smccc: 00012a92
385 02:13:46.932143 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 02:13:46.937672 board id: 1
387 02:13:46.943623 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 02:13:46.954172 fw parse done
389 02:13:46.960025 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 02:13:47.002637 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 02:13:47.013563 PIEI prepare done
392 02:13:47.014152 fastboot data load
393 02:13:47.014665 fastboot data verify
394 02:13:47.019312 verify result: 266
395 02:13:47.024952 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 02:13:47.025607 LPDDR4 probe
397 02:13:47.026140 ddr clk to 1584MHz
398 02:13:47.032844 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 02:13:47.070184
400 02:13:47.070931 dmc_version 0001
401 02:13:47.076791 Check phy result
402 02:13:47.082700 INFO : End of CA training
403 02:13:47.083313 INFO : End of initialization
404 02:13:47.088355 INFO : Training has run successfully!
405 02:13:47.088952 Check phy result
406 02:13:47.093876 INFO : End of initialization
407 02:13:47.094467 INFO : End of read enable training
408 02:13:47.097193 INFO : End of fine write leveling
409 02:13:47.102801 INFO : End of Write leveling coarse delay
410 02:13:47.108407 INFO : Training has run successfully!
411 02:13:47.109003 Check phy result
412 02:13:47.109544 INFO : End of initialization
413 02:13:47.113991 INFO : End of read dq deskew training
414 02:13:47.117312 INFO : End of MPR read delay center optimization
415 02:13:47.122894 INFO : End of write delay center optimization
416 02:13:47.128493 INFO : End of read delay center optimization
417 02:13:47.129102 INFO : End of max read latency training
418 02:13:47.134176 INFO : Training has run successfully!
419 02:13:47.134768 1D training succeed
420 02:13:47.142264 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 02:13:47.189856 Check phy result
422 02:13:47.190491 INFO : End of initialization
423 02:13:47.212433 INFO : End of 2D read delay Voltage center optimization
424 02:13:47.232487 INFO : End of 2D read delay Voltage center optimization
425 02:13:47.284462 INFO : End of 2D write delay Voltage center optimization
426 02:13:47.333632 INFO : End of 2D write delay Voltage center optimization
427 02:13:47.339218 INFO : Training has run successfully!
428 02:13:47.339844
429 02:13:47.340445 channel==0
430 02:13:47.344731 RxClkDly_Margin_A0==88 ps 9
431 02:13:47.345347 TxDqDly_Margin_A0==98 ps 10
432 02:13:47.350336 RxClkDly_Margin_A1==78 ps 8
433 02:13:47.350952 TxDqDly_Margin_A1==98 ps 10
434 02:13:47.351480 TrainedVREFDQ_A0==74
435 02:13:47.356001 TrainedVREFDQ_A1==74
436 02:13:47.356628 VrefDac_Margin_A0==25
437 02:13:47.357166 DeviceVref_Margin_A0==40
438 02:13:47.361566 VrefDac_Margin_A1==25
439 02:13:47.362174 DeviceVref_Margin_A1==40
440 02:13:47.362709
441 02:13:47.363230
442 02:13:47.367195 channel==1
443 02:13:47.367810 RxClkDly_Margin_A0==98 ps 10
444 02:13:47.368402 TxDqDly_Margin_A0==98 ps 10
445 02:13:47.372792 RxClkDly_Margin_A1==88 ps 9
446 02:13:47.373431 TxDqDly_Margin_A1==88 ps 9
447 02:13:47.378380 TrainedVREFDQ_A0==77
448 02:13:47.379024 TrainedVREFDQ_A1==77
449 02:13:47.379564 VrefDac_Margin_A0==22
450 02:13:47.384005 DeviceVref_Margin_A0==37
451 02:13:47.384636 VrefDac_Margin_A1==24
452 02:13:47.389546 DeviceVref_Margin_A1==37
453 02:13:47.390164
454 02:13:47.390702 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 02:13:47.391217
456 02:13:47.423138 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000017 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 02:13:47.424036 2D training succeed
458 02:13:47.428810 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 02:13:47.434187 auto size-- 65535DDR cs0 size: 2048MB
460 02:13:47.434573 DDR cs1 size: 2048MB
461 02:13:47.439738 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 02:13:47.440082 cs0 DataBus test pass
463 02:13:47.445366 cs1 DataBus test pass
464 02:13:47.445684 cs0 AddrBus test pass
465 02:13:47.445944 cs1 AddrBus test pass
466 02:13:47.446193
467 02:13:47.450968 100bdlr_step_size ps== 420
468 02:13:47.451282 result report
469 02:13:47.456607 boot times 0Enable ddr reg access
470 02:13:47.461916 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 02:13:47.475570 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 02:13:48.047511 0.0;M3 CHK:0;cm4_sp_mode 0
473 02:13:48.048385 MVN_1=0x00000000
474 02:13:48.052945 MVN_2=0x00000000
475 02:13:48.058717 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 02:13:48.059318 OPS=0x10
477 02:13:48.059867 ring efuse init
478 02:13:48.060457 chipver efuse init
479 02:13:48.064274 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 02:13:48.069990 [0.018961 Inits done]
481 02:13:48.070643 secure task start!
482 02:13:48.071195 high task start!
483 02:13:48.076918 low task start!
484 02:13:48.077585 run into bl31
485 02:13:48.081202 NOTICE: BL31: v1.3(release):4fc40b1
486 02:13:48.088969 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 02:13:48.089667 NOTICE: BL31: G12A normal boot!
488 02:13:48.117753 NOTICE: BL31: BL33 decompress pass
489 02:13:48.120483 ERROR: Error initializing runtime service opteed_fast
490 02:13:49.353471
491 02:13:49.354084
492 02:13:49.361778 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 02:13:49.362240
494 02:13:49.362660 Model: Libre Computer AML-A311D-CC Alta
495 02:13:49.570135 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 02:13:49.593596 DRAM: 2 GiB (effective 3.8 GiB)
497 02:13:49.737338 Core: 408 devices, 31 uclasses, devicetree: separate
498 02:13:49.742458 WDT: Not starting watchdog@f0d0
499 02:13:49.774839 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 02:13:49.787148 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 02:13:49.792098 ** Bad device specification mmc 0 **
502 02:13:49.802494 Card did not respond to voltage select! : -110
503 02:13:49.810062 ** Bad device specification mmc 0 **
504 02:13:49.810353 Couldn't find partition mmc 0
505 02:13:49.818474 Card did not respond to voltage select! : -110
506 02:13:49.823905 ** Bad device specification mmc 0 **
507 02:13:49.824242 Couldn't find partition mmc 0
508 02:13:49.829023 Error: could not access storage.
509 02:13:51.093532 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 02:13:51.093968 bl2_stage_init 0x01
511 02:13:51.094197 bl2_stage_init 0x81
512 02:13:51.099032 hw id: 0x0000 - pwm id 0x01
513 02:13:51.099317 bl2_stage_init 0xc1
514 02:13:51.099537 bl2_stage_init 0x02
515 02:13:51.099744
516 02:13:51.104664 L0:00000000
517 02:13:51.105059 L1:20000703
518 02:13:51.105306 L2:00008067
519 02:13:51.105517 L3:14000000
520 02:13:51.107532 B2:00402000
521 02:13:51.107896 B1:e0f83180
522 02:13:51.108261
523 02:13:51.108587 TE: 58124
524 02:13:51.108908
525 02:13:51.118703 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 02:13:51.119033
527 02:13:51.119249 Board ID = 1
528 02:13:51.119452 Set A53 clk to 24M
529 02:13:51.119654 Set A73 clk to 24M
530 02:13:51.124364 Set clk81 to 24M
531 02:13:51.124891 A53 clk: 1200 MHz
532 02:13:51.125321 A73 clk: 1200 MHz
533 02:13:51.127683 CLK81: 166.6M
534 02:13:51.128164 smccc: 00012a92
535 02:13:51.133253 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 02:13:51.138868 board id: 1
537 02:13:51.144161 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 02:13:51.154802 fw parse done
539 02:13:51.160764 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 02:13:51.203422 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 02:13:51.214433 PIEI prepare done
542 02:13:51.214915 fastboot data load
543 02:13:51.215348 fastboot data verify
544 02:13:51.220033 verify result: 266
545 02:13:51.225598 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 02:13:51.226098 LPDDR4 probe
547 02:13:51.226524 ddr clk to 1584MHz
548 02:13:51.233552 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 02:13:51.270932
550 02:13:51.271488 dmc_version 0001
551 02:13:51.277492 Check phy result
552 02:13:51.283348 INFO : End of CA training
553 02:13:51.283809 INFO : End of initialization
554 02:13:51.288939 INFO : Training has run successfully!
555 02:13:51.289395 Check phy result
556 02:13:51.294543 INFO : End of initialization
557 02:13:51.294995 INFO : End of read enable training
558 02:13:51.300193 INFO : End of fine write leveling
559 02:13:51.305782 INFO : End of Write leveling coarse delay
560 02:13:51.306253 INFO : Training has run successfully!
561 02:13:51.306670 Check phy result
562 02:13:51.311302 INFO : End of initialization
563 02:13:51.311749 INFO : End of read dq deskew training
564 02:13:51.316945 INFO : End of MPR read delay center optimization
565 02:13:51.322540 INFO : End of write delay center optimization
566 02:13:51.328146 INFO : End of read delay center optimization
567 02:13:51.328597 INFO : End of max read latency training
568 02:13:51.333819 INFO : Training has run successfully!
569 02:13:51.334272 1D training succeed
570 02:13:51.342943 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 02:13:51.390622 Check phy result
572 02:13:51.391228 INFO : End of initialization
573 02:13:51.412249 INFO : End of 2D read delay Voltage center optimization
574 02:13:51.432252 INFO : End of 2D read delay Voltage center optimization
575 02:13:51.484224 INFO : End of 2D write delay Voltage center optimization
576 02:13:51.533430 INFO : End of 2D write delay Voltage center optimization
577 02:13:51.538967 INFO : Training has run successfully!
578 02:13:51.539477
579 02:13:51.539914 channel==0
580 02:13:51.544541 RxClkDly_Margin_A0==88 ps 9
581 02:13:51.545037 TxDqDly_Margin_A0==98 ps 10
582 02:13:51.547837 RxClkDly_Margin_A1==88 ps 9
583 02:13:51.548344 TxDqDly_Margin_A1==98 ps 10
584 02:13:51.553404 TrainedVREFDQ_A0==74
585 02:13:51.554001 TrainedVREFDQ_A1==74
586 02:13:51.558970 VrefDac_Margin_A0==25
587 02:13:51.559452 DeviceVref_Margin_A0==40
588 02:13:51.559873 VrefDac_Margin_A1==25
589 02:13:51.564580 DeviceVref_Margin_A1==40
590 02:13:51.565054
591 02:13:51.565473
592 02:13:51.565884 channel==1
593 02:13:51.566291 RxClkDly_Margin_A0==98 ps 10
594 02:13:51.570164 TxDqDly_Margin_A0==98 ps 10
595 02:13:51.570632 RxClkDly_Margin_A1==98 ps 10
596 02:13:51.575862 TxDqDly_Margin_A1==88 ps 9
597 02:13:51.576369 TrainedVREFDQ_A0==77
598 02:13:51.576792 TrainedVREFDQ_A1==77
599 02:13:51.581350 VrefDac_Margin_A0==22
600 02:13:51.581806 DeviceVref_Margin_A0==37
601 02:13:51.586972 VrefDac_Margin_A1==22
602 02:13:51.587453 DeviceVref_Margin_A1==37
603 02:13:51.587868
604 02:13:51.592586 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 02:13:51.593060
606 02:13:51.620624 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 02:13:51.626183 2D training succeed
608 02:13:51.631808 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 02:13:51.632325 auto size-- 65535DDR cs0 size: 2048MB
610 02:13:51.637324 DDR cs1 size: 2048MB
611 02:13:51.637790 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 02:13:51.642955 cs0 DataBus test pass
613 02:13:51.643453 cs1 DataBus test pass
614 02:13:51.643883 cs0 AddrBus test pass
615 02:13:51.648572 cs1 AddrBus test pass
616 02:13:51.649038
617 02:13:51.649455 100bdlr_step_size ps== 420
618 02:13:51.649870 result report
619 02:13:51.654132 boot times 0Enable ddr reg access
620 02:13:51.661949 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 02:13:51.675443 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 02:13:52.247834 0.0;M3 CHK:0;cm4_sp_mode 0
623 02:13:52.248364 MVN_1=0x00000000
624 02:13:52.253265 MVN_2=0x00000000
625 02:13:52.259043 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 02:13:52.259633 OPS=0x10
627 02:13:52.260345 ring efuse init
628 02:13:52.260919 chipver efuse init
629 02:13:52.267250 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 02:13:52.267812 [0.018961 Inits done]
631 02:13:52.268300 secure task start!
632 02:13:52.274680 high task start!
633 02:13:52.275197 low task start!
634 02:13:52.275644 run into bl31
635 02:13:52.281340 NOTICE: BL31: v1.3(release):4fc40b1
636 02:13:52.289182 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 02:13:52.289701 NOTICE: BL31: G12A normal boot!
638 02:13:52.315149 NOTICE: BL31: BL33 decompress pass
639 02:13:52.320664 ERROR: Error initializing runtime service opteed_fast
640 02:13:53.553602
641 02:13:53.554046
642 02:13:53.562011 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 02:13:53.562369
644 02:13:53.562621 Model: Libre Computer AML-A311D-CC Alta
645 02:13:53.770452 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 02:13:53.793805 DRAM: 2 GiB (effective 3.8 GiB)
647 02:13:53.936786 Core: 408 devices, 31 uclasses, devicetree: separate
648 02:13:53.942542 WDT: Not starting watchdog@f0d0
649 02:13:53.974834 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 02:13:53.987298 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 02:13:53.992392 ** Bad device specification mmc 0 **
652 02:13:54.002518 Card did not respond to voltage select! : -110
653 02:13:54.010384 ** Bad device specification mmc 0 **
654 02:13:54.010869 Couldn't find partition mmc 0
655 02:13:54.018539 Card did not respond to voltage select! : -110
656 02:13:54.024074 ** Bad device specification mmc 0 **
657 02:13:54.024576 Couldn't find partition mmc 0
658 02:13:54.029105 Error: could not access storage.
659 02:13:54.372720 Net: eth0: ethernet@ff3f0000
660 02:13:54.373310 starting USB...
661 02:13:54.624509 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 02:13:54.624920 Starting the controller
663 02:13:54.631553 USB XHCI 1.10
664 02:13:56.342409 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 02:13:56.343087 bl2_stage_init 0x01
666 02:13:56.343569 bl2_stage_init 0x81
667 02:13:56.347873 hw id: 0x0000 - pwm id 0x01
668 02:13:56.348432 bl2_stage_init 0xc1
669 02:13:56.348899 bl2_stage_init 0x02
670 02:13:56.349354
671 02:13:56.353641 L0:00000000
672 02:13:56.354139 L1:20000703
673 02:13:56.354594 L2:00008067
674 02:13:56.355036 L3:14000000
675 02:13:56.356508 B2:00402000
676 02:13:56.356990 B1:e0f83180
677 02:13:56.357439
678 02:13:56.357885 TE: 58167
679 02:13:56.358329
680 02:13:56.367532 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 02:13:56.368073
682 02:13:56.368536 Board ID = 1
683 02:13:56.368978 Set A53 clk to 24M
684 02:13:56.369416 Set A73 clk to 24M
685 02:13:56.373229 Set clk81 to 24M
686 02:13:56.373741 A53 clk: 1200 MHz
687 02:13:56.374204 A73 clk: 1200 MHz
688 02:13:56.376783 CLK81: 166.6M
689 02:13:56.377282 smccc: 00012abe
690 02:13:56.382325 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 02:13:56.387871 board id: 1
692 02:13:56.392868 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 02:13:56.403510 fw parse done
694 02:13:56.409569 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 02:13:56.452181 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 02:13:56.463098 PIEI prepare done
697 02:13:56.463596 fastboot data load
698 02:13:56.464093 fastboot data verify
699 02:13:56.468708 verify result: 266
700 02:13:56.474302 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 02:13:56.474789 LPDDR4 probe
702 02:13:56.475239 ddr clk to 1584MHz
703 02:13:56.482262 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 02:13:56.519743
705 02:13:56.520198 dmc_version 0001
706 02:13:56.526231 Check phy result
707 02:13:56.532056 INFO : End of CA training
708 02:13:56.532491 INFO : End of initialization
709 02:13:56.537666 INFO : Training has run successfully!
710 02:13:56.537998 Check phy result
711 02:13:56.543312 INFO : End of initialization
712 02:13:56.543771 INFO : End of read enable training
713 02:13:56.546560 INFO : End of fine write leveling
714 02:13:56.552108 INFO : End of Write leveling coarse delay
715 02:13:56.557699 INFO : Training has run successfully!
716 02:13:56.558015 Check phy result
717 02:13:56.558237 INFO : End of initialization
718 02:13:56.563264 INFO : End of read dq deskew training
719 02:13:56.566684 INFO : End of MPR read delay center optimization
720 02:13:56.572287 INFO : End of write delay center optimization
721 02:13:56.577948 INFO : End of read delay center optimization
722 02:13:56.578498 INFO : End of max read latency training
723 02:13:56.583665 INFO : Training has run successfully!
724 02:13:56.584237 1D training succeed
725 02:13:56.591827 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 02:13:56.639428 Check phy result
727 02:13:56.640177 INFO : End of initialization
728 02:13:56.662048 INFO : End of 2D read delay Voltage center optimization
729 02:13:56.682309 INFO : End of 2D read delay Voltage center optimization
730 02:13:56.734381 INFO : End of 2D write delay Voltage center optimization
731 02:13:56.783875 INFO : End of 2D write delay Voltage center optimization
732 02:13:56.789288 INFO : Training has run successfully!
733 02:13:56.789857
734 02:13:56.790334 channel==0
735 02:13:56.794884 RxClkDly_Margin_A0==88 ps 9
736 02:13:56.795453 TxDqDly_Margin_A0==98 ps 10
737 02:13:56.798245 RxClkDly_Margin_A1==88 ps 9
738 02:13:56.798792 TxDqDly_Margin_A1==98 ps 10
739 02:13:56.804563 TrainedVREFDQ_A0==74
740 02:13:56.805190 TrainedVREFDQ_A1==74
741 02:13:56.805652 VrefDac_Margin_A0==24
742 02:13:56.810585 DeviceVref_Margin_A0==40
743 02:13:56.811175 VrefDac_Margin_A1==25
744 02:13:56.815028 DeviceVref_Margin_A1==40
745 02:13:56.815598
746 02:13:56.816116
747 02:13:56.816590 channel==1
748 02:13:56.817051 RxClkDly_Margin_A0==98 ps 10
749 02:13:56.820598 TxDqDly_Margin_A0==88 ps 9
750 02:13:56.821171 RxClkDly_Margin_A1==88 ps 9
751 02:13:56.826177 TxDqDly_Margin_A1==88 ps 9
752 02:13:56.826745 TrainedVREFDQ_A0==76
753 02:13:56.827216 TrainedVREFDQ_A1==77
754 02:13:56.831741 VrefDac_Margin_A0==22
755 02:13:56.832318 DeviceVref_Margin_A0==38
756 02:13:56.837366 VrefDac_Margin_A1==24
757 02:13:56.837915 DeviceVref_Margin_A1==37
758 02:13:56.838376
759 02:13:56.842989 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 02:13:56.843548
761 02:13:56.870861 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
762 02:13:56.876634 2D training succeed
763 02:13:56.882046 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 02:13:56.882593 auto size-- 65535DDR cs0 size: 2048MB
765 02:13:56.887622 DDR cs1 size: 2048MB
766 02:13:56.888221 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 02:13:56.893359 cs0 DataBus test pass
768 02:13:56.893923 cs1 DataBus test pass
769 02:13:56.894385 cs0 AddrBus test pass
770 02:13:56.898844 cs1 AddrBus test pass
771 02:13:56.899381
772 02:13:56.899846 100bdlr_step_size ps== 420
773 02:13:56.900367 result report
774 02:13:56.904502 boot times 0Enable ddr reg access
775 02:13:56.912013 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 02:13:56.925440 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 02:13:57.500137 0.0;M3 CHK:0;cm4_sp_mode 0
778 02:13:57.500840 MVN_1=0x00000000
779 02:13:57.504504 MVN_2=0x00000000
780 02:13:57.510274 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 02:13:57.510856 OPS=0x10
782 02:13:57.511359 ring efuse init
783 02:13:57.513025 chipver efuse init
784 02:13:57.515856 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 02:13:57.521598 [0.018961 Inits done]
786 02:13:57.522147 secure task start!
787 02:13:57.522587 high task start!
788 02:13:57.526022 low task start!
789 02:13:57.526520 run into bl31
790 02:13:57.532707 NOTICE: BL31: v1.3(release):4fc40b1
791 02:13:57.540550 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 02:13:57.541113 NOTICE: BL31: G12A normal boot!
793 02:13:57.566529 NOTICE: BL31: BL33 decompress pass
794 02:13:57.571550 ERROR: Error initializing runtime service opteed_fast
795 02:13:58.804393
796 02:13:58.805060
797 02:13:58.812865 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 02:13:58.813382
799 02:13:58.813849 Model: Libre Computer AML-A311D-CC Alta
800 02:13:59.021264 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 02:13:59.044600 DRAM: 2 GiB (effective 3.8 GiB)
802 02:13:59.187654 Core: 408 devices, 31 uclasses, devicetree: separate
803 02:13:59.193274 WDT: Not starting watchdog@f0d0
804 02:13:59.225721 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 02:13:59.238178 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 02:13:59.243141 ** Bad device specification mmc 0 **
807 02:13:59.253508 Card did not respond to voltage select! : -110
808 02:13:59.261155 ** Bad device specification mmc 0 **
809 02:13:59.261667 Couldn't find partition mmc 0
810 02:13:59.269473 Card did not respond to voltage select! : -110
811 02:13:59.275009 ** Bad device specification mmc 0 **
812 02:13:59.275505 Couldn't find partition mmc 0
813 02:13:59.280082 Error: could not access storage.
814 02:13:59.621934 Net: eth0: ethernet@ff3f0000
815 02:13:59.622561 starting USB...
816 02:13:59.874342 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 02:13:59.874936 Starting the controller
818 02:13:59.880998 USB XHCI 1.10
819 02:14:02.042718 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 02:14:02.043394 bl2_stage_init 0x01
821 02:14:02.043869 bl2_stage_init 0x81
822 02:14:02.048236 hw id: 0x0000 - pwm id 0x01
823 02:14:02.048765 bl2_stage_init 0xc1
824 02:14:02.049225 bl2_stage_init 0x02
825 02:14:02.049675
826 02:14:02.053739 L0:00000000
827 02:14:02.054253 L1:20000703
828 02:14:02.054706 L2:00008067
829 02:14:02.055151 L3:14000000
830 02:14:02.059463 B2:00402000
831 02:14:02.060012 B1:e0f83180
832 02:14:02.060474
833 02:14:02.060926 TE: 58124
834 02:14:02.061376
835 02:14:02.065037 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 02:14:02.065550
837 02:14:02.066007 Board ID = 1
838 02:14:02.070619 Set A53 clk to 24M
839 02:14:02.071132 Set A73 clk to 24M
840 02:14:02.071583 Set clk81 to 24M
841 02:14:02.076270 A53 clk: 1200 MHz
842 02:14:02.076781 A73 clk: 1200 MHz
843 02:14:02.077234 CLK81: 166.6M
844 02:14:02.077673 smccc: 00012a91
845 02:14:02.081706 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 02:14:02.087342 board id: 1
847 02:14:02.093096 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 02:14:02.103922 fw parse done
849 02:14:02.109099 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 02:14:02.152300 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 02:14:02.163389 PIEI prepare done
852 02:14:02.163905 fastboot data load
853 02:14:02.164407 fastboot data verify
854 02:14:02.168929 verify result: 266
855 02:14:02.174551 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 02:14:02.175069 LPDDR4 probe
857 02:14:02.175526 ddr clk to 1584MHz
858 02:14:02.181939 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 02:14:02.219711
860 02:14:02.220303 dmc_version 0001
861 02:14:02.226473 Check phy result
862 02:14:02.232432 INFO : End of CA training
863 02:14:02.232938 INFO : End of initialization
864 02:14:02.237976 INFO : Training has run successfully!
865 02:14:02.238529 Check phy result
866 02:14:02.243620 INFO : End of initialization
867 02:14:02.244181 INFO : End of read enable training
868 02:14:02.246850 INFO : End of fine write leveling
869 02:14:02.252431 INFO : End of Write leveling coarse delay
870 02:14:02.258053 INFO : Training has run successfully!
871 02:14:02.258567 Check phy result
872 02:14:02.259020 INFO : End of initialization
873 02:14:02.263614 INFO : End of read dq deskew training
874 02:14:02.269203 INFO : End of MPR read delay center optimization
875 02:14:02.269719 INFO : End of write delay center optimization
876 02:14:02.274802 INFO : End of read delay center optimization
877 02:14:02.280438 INFO : End of max read latency training
878 02:14:02.280948 INFO : Training has run successfully!
879 02:14:02.285920 1D training succeed
880 02:14:02.291054 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 02:14:02.338595 Check phy result
882 02:14:02.339170 INFO : End of initialization
883 02:14:02.360614 INFO : End of 2D read delay Voltage center optimization
884 02:14:02.380655 INFO : End of 2D read delay Voltage center optimization
885 02:14:02.432674 INFO : End of 2D write delay Voltage center optimization
886 02:14:02.482076 INFO : End of 2D write delay Voltage center optimization
887 02:14:02.487630 INFO : Training has run successfully!
888 02:14:02.488174
889 02:14:02.488641 channel==0
890 02:14:02.493284 RxClkDly_Margin_A0==88 ps 9
891 02:14:02.493790 TxDqDly_Margin_A0==98 ps 10
892 02:14:02.498827 RxClkDly_Margin_A1==88 ps 9
893 02:14:02.499334 TxDqDly_Margin_A1==98 ps 10
894 02:14:02.499792 TrainedVREFDQ_A0==74
895 02:14:02.504463 TrainedVREFDQ_A1==74
896 02:14:02.504979 VrefDac_Margin_A0==25
897 02:14:02.505439 DeviceVref_Margin_A0==40
898 02:14:02.510068 VrefDac_Margin_A1==25
899 02:14:02.510605 DeviceVref_Margin_A1==40
900 02:14:02.511054
901 02:14:02.511503
902 02:14:02.515591 channel==1
903 02:14:02.516192 RxClkDly_Margin_A0==78 ps 8
904 02:14:02.516637 TxDqDly_Margin_A0==98 ps 10
905 02:14:02.521306 RxClkDly_Margin_A1==98 ps 10
906 02:14:02.521802 TxDqDly_Margin_A1==88 ps 9
907 02:14:02.526819 TrainedVREFDQ_A0==77
908 02:14:02.527316 TrainedVREFDQ_A1==77
909 02:14:02.527749 VrefDac_Margin_A0==23
910 02:14:02.532449 DeviceVref_Margin_A0==37
911 02:14:02.532949 VrefDac_Margin_A1==23
912 02:14:02.538034 DeviceVref_Margin_A1==37
913 02:14:02.538542
914 02:14:02.538975 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 02:14:02.539413
916 02:14:02.571604 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
917 02:14:02.572254 2D training succeed
918 02:14:02.577313 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 02:14:02.582810 auto size-- 65535DDR cs0 size: 2048MB
920 02:14:02.583301 DDR cs1 size: 2048MB
921 02:14:02.588398 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 02:14:02.588894 cs0 DataBus test pass
923 02:14:02.594035 cs1 DataBus test pass
924 02:14:02.594525 cs0 AddrBus test pass
925 02:14:02.594954 cs1 AddrBus test pass
926 02:14:02.595375
927 02:14:02.599620 100bdlr_step_size ps== 420
928 02:14:02.600155 result report
929 02:14:02.605283 boot times 0Enable ddr reg access
930 02:14:02.610563 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 02:14:02.624027 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 02:14:03.197788 0.0;M3 CHK:0;cm4_sp_mode 0
933 02:14:03.198428 MVN_1=0x00000000
934 02:14:03.203288 MVN_2=0x00000000
935 02:14:03.209051 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 02:14:03.209572 OPS=0x10
937 02:14:03.210025 ring efuse init
938 02:14:03.210472 chipver efuse init
939 02:14:03.214645 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 02:14:03.220240 [0.018961 Inits done]
941 02:14:03.220747 secure task start!
942 02:14:03.221196 high task start!
943 02:14:03.224795 low task start!
944 02:14:03.225298 run into bl31
945 02:14:03.231474 NOTICE: BL31: v1.3(release):4fc40b1
946 02:14:03.239293 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 02:14:03.239837 NOTICE: BL31: G12A normal boot!
948 02:14:03.264815 NOTICE: BL31: BL33 decompress pass
949 02:14:03.270505 ERROR: Error initializing runtime service opteed_fast
950 02:14:04.503311
951 02:14:04.503967
952 02:14:04.511821 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 02:14:04.512420
954 02:14:04.512887 Model: Libre Computer AML-A311D-CC Alta
955 02:14:04.720146 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 02:14:04.743504 DRAM: 2 GiB (effective 3.8 GiB)
957 02:14:04.886537 Core: 408 devices, 31 uclasses, devicetree: separate
958 02:14:04.892354 WDT: Not starting watchdog@f0d0
959 02:14:04.924653 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 02:14:04.937102 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 02:14:04.942097 ** Bad device specification mmc 0 **
962 02:14:04.952387 Card did not respond to voltage select! : -110
963 02:14:04.960091 ** Bad device specification mmc 0 **
964 02:14:04.960625 Couldn't find partition mmc 0
965 02:14:04.968383 Card did not respond to voltage select! : -110
966 02:14:04.973904 ** Bad device specification mmc 0 **
967 02:14:04.974407 Couldn't find partition mmc 0
968 02:14:04.978961 Error: could not access storage.
969 02:14:05.321384 Net: eth0: ethernet@ff3f0000
970 02:14:05.322021 starting USB...
971 02:14:05.573225 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 02:14:05.573812 Starting the controller
973 02:14:05.580218 USB XHCI 1.10
974 02:14:07.442495 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
975 02:14:07.443175 bl2_stage_init 0x81
976 02:14:07.448344 hw id: 0x0000 - pwm id 0x01
977 02:14:07.448870 bl2_stage_init 0xc1
978 02:14:07.449334 bl2_stage_init 0x02
979 02:14:07.449787
980 02:14:07.453768 L0:00000000
981 02:14:07.454280 L1:20000703
982 02:14:07.454734 L2:00008067
983 02:14:07.455182 L3:14000000
984 02:14:07.455620 B2:00402000
985 02:14:07.456584 B1:e0f83180
986 02:14:07.457083
987 02:14:07.457542 TE: 58150
988 02:14:07.457994
989 02:14:07.467509 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 02:14:07.468094
991 02:14:07.468572 Board ID = 1
992 02:14:07.469028 Set A53 clk to 24M
993 02:14:07.469477 Set A73 clk to 24M
994 02:14:07.473201 Set clk81 to 24M
995 02:14:07.473722 A53 clk: 1200 MHz
996 02:14:07.474178 A73 clk: 1200 MHz
997 02:14:07.478720 CLK81: 166.6M
998 02:14:07.479233 smccc: 00012aac
999 02:14:07.484503 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 02:14:07.485023 board id: 1
1001 02:14:07.490026 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 02:14:07.503529 fw parse done
1003 02:14:07.509469 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 02:14:07.552247 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 02:14:07.563152 PIEI prepare done
1006 02:14:07.564130 fastboot data load
1007 02:14:07.564980 fastboot data verify
1008 02:14:07.568806 verify result: 266
1009 02:14:07.574310 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 02:14:07.575178 LPDDR4 probe
1011 02:14:07.575893 ddr clk to 1584MHz
1012 02:14:07.582332 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 02:14:07.619671
1014 02:14:07.620700 dmc_version 0001
1015 02:14:07.626192 Check phy result
1016 02:14:07.632180 INFO : End of CA training
1017 02:14:07.632981 INFO : End of initialization
1018 02:14:07.637823 INFO : Training has run successfully!
1019 02:14:07.638686 Check phy result
1020 02:14:07.643305 INFO : End of initialization
1021 02:14:07.643839 INFO : End of read enable training
1022 02:14:07.648977 INFO : End of fine write leveling
1023 02:14:07.654534 INFO : End of Write leveling coarse delay
1024 02:14:07.655423 INFO : Training has run successfully!
1025 02:14:07.656179 Check phy result
1026 02:14:07.660170 INFO : End of initialization
1027 02:14:07.661057 INFO : End of read dq deskew training
1028 02:14:07.665738 INFO : End of MPR read delay center optimization
1029 02:14:07.671241 INFO : End of write delay center optimization
1030 02:14:07.676906 INFO : End of read delay center optimization
1031 02:14:07.677427 INFO : End of max read latency training
1032 02:14:07.682461 INFO : Training has run successfully!
1033 02:14:07.682978 1D training succeed
1034 02:14:07.691636 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 02:14:07.739285 Check phy result
1036 02:14:07.739864 INFO : End of initialization
1037 02:14:07.761681 INFO : End of 2D read delay Voltage center optimization
1038 02:14:07.781894 INFO : End of 2D read delay Voltage center optimization
1039 02:14:07.833721 INFO : End of 2D write delay Voltage center optimization
1040 02:14:07.883038 INFO : End of 2D write delay Voltage center optimization
1041 02:14:07.888494 INFO : Training has run successfully!
1042 02:14:07.889020
1043 02:14:07.889476 channel==0
1044 02:14:07.894127 RxClkDly_Margin_A0==88 ps 9
1045 02:14:07.894643 TxDqDly_Margin_A0==98 ps 10
1046 02:14:07.899689 RxClkDly_Margin_A1==98 ps 10
1047 02:14:07.900238 TxDqDly_Margin_A1==98 ps 10
1048 02:14:07.900695 TrainedVREFDQ_A0==74
1049 02:14:07.905284 TrainedVREFDQ_A1==74
1050 02:14:07.905801 VrefDac_Margin_A0==25
1051 02:14:07.910945 DeviceVref_Margin_A0==40
1052 02:14:07.911448 VrefDac_Margin_A1==25
1053 02:14:07.911899 DeviceVref_Margin_A1==40
1054 02:14:07.912384
1055 02:14:07.912826
1056 02:14:07.916493 channel==1
1057 02:14:07.916991 RxClkDly_Margin_A0==98 ps 10
1058 02:14:07.917438 TxDqDly_Margin_A0==88 ps 9
1059 02:14:07.922122 RxClkDly_Margin_A1==88 ps 9
1060 02:14:07.922625 TxDqDly_Margin_A1==88 ps 9
1061 02:14:07.927710 TrainedVREFDQ_A0==77
1062 02:14:07.928255 TrainedVREFDQ_A1==77
1063 02:14:07.928713 VrefDac_Margin_A0==22
1064 02:14:07.933276 DeviceVref_Margin_A0==37
1065 02:14:07.933772 VrefDac_Margin_A1==24
1066 02:14:07.938961 DeviceVref_Margin_A1==37
1067 02:14:07.939477
1068 02:14:07.939930 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 02:14:07.940408
1070 02:14:07.972540 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000017 00000017 00000016 00000018 00000015 00000018 00000018 00000018 00000018 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1071 02:14:07.973158 2D training succeed
1072 02:14:07.978130 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 02:14:07.983767 auto size-- 65535DDR cs0 size: 2048MB
1074 02:14:07.984702 DDR cs1 size: 2048MB
1075 02:14:07.989283 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 02:14:07.989794 cs0 DataBus test pass
1077 02:14:07.994939 cs1 DataBus test pass
1078 02:14:07.995435 cs0 AddrBus test pass
1079 02:14:07.995883 cs1 AddrBus test pass
1080 02:14:07.996357
1081 02:14:08.000607 100bdlr_step_size ps== 420
1082 02:14:08.001540 result report
1083 02:14:08.006047 boot times 0Enable ddr reg access
1084 02:14:08.011485 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 02:14:08.024926 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 02:14:08.596900 0.0;M3 CHK:0;cm4_sp_mode 0
1087 02:14:08.597545 MVN_1=0x00000000
1088 02:14:08.602357 MVN_2=0x00000000
1089 02:14:08.608181 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 02:14:08.608691 OPS=0x10
1091 02:14:08.609143 ring efuse init
1092 02:14:08.609583 chipver efuse init
1093 02:14:08.616462 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 02:14:08.616985 [0.018960 Inits done]
1095 02:14:08.617421 secure task start!
1096 02:14:08.623908 high task start!
1097 02:14:08.624464 low task start!
1098 02:14:08.624892 run into bl31
1099 02:14:08.630595 NOTICE: BL31: v1.3(release):4fc40b1
1100 02:14:08.638380 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 02:14:08.638885 NOTICE: BL31: G12A normal boot!
1102 02:14:08.663742 NOTICE: BL31: BL33 decompress pass
1103 02:14:08.669414 ERROR: Error initializing runtime service opteed_fast
1104 02:14:09.902302
1105 02:14:09.902928
1106 02:14:09.910615 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 02:14:09.911097
1108 02:14:09.911513 Model: Libre Computer AML-A311D-CC Alta
1109 02:14:10.119082 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 02:14:10.142439 DRAM: 2 GiB (effective 3.8 GiB)
1111 02:14:10.285425 Core: 408 devices, 31 uclasses, devicetree: separate
1112 02:14:10.291287 WDT: Not starting watchdog@f0d0
1113 02:14:10.323513 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 02:14:10.335965 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 02:14:10.340954 ** Bad device specification mmc 0 **
1116 02:14:10.351308 Card did not respond to voltage select! : -110
1117 02:14:10.358957 ** Bad device specification mmc 0 **
1118 02:14:10.359413 Couldn't find partition mmc 0
1119 02:14:10.367332 Card did not respond to voltage select! : -110
1120 02:14:10.372815 ** Bad device specification mmc 0 **
1121 02:14:10.373278 Couldn't find partition mmc 0
1122 02:14:10.377871 Error: could not access storage.
1123 02:14:10.721543 Net: eth0: ethernet@ff3f0000
1124 02:14:10.722170 starting USB...
1125 02:14:10.973270 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 02:14:10.973886 Starting the controller
1127 02:14:10.980172 USB XHCI 1.10
1128 02:14:12.537339 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 02:14:12.543131 scanning usb for storage devices... 0 Storage Device(s) found
1131 02:14:12.594539 Hit any key to stop autoboot: 1
1132 02:14:12.595238 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1133 02:14:12.595616 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1134 02:14:12.595904 Setting prompt string to ['=>']
1135 02:14:12.596230 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1136 02:14:12.610640 0
1137 02:14:12.611691 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 02:14:12.612285 Sending with 10 millisecond of delay
1140 02:14:13.747575 => setenv autoload no
1141 02:14:13.758572 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1142 02:14:13.764137 setenv autoload no
1143 02:14:13.765072 Sending with 10 millisecond of delay
1145 02:14:15.562478 => setenv initrd_high 0xffffffff
1146 02:14:15.573343 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1147 02:14:15.574339 setenv initrd_high 0xffffffff
1148 02:14:15.575118 Sending with 10 millisecond of delay
1150 02:14:17.191953 => setenv fdt_high 0xffffffff
1151 02:14:17.202827 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1152 02:14:17.203835 setenv fdt_high 0xffffffff
1153 02:14:17.204662 Sending with 10 millisecond of delay
1155 02:14:17.499177 => dhcp
1156 02:14:17.509794 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1157 02:14:17.510355 dhcp
1158 02:14:17.510598 Speed: 1000, full duplex
1159 02:14:17.510811 BOOTP broadcast 1
1160 02:14:17.519125 DHCP client bound to address 192.168.6.27 (10 ms)
1161 02:14:17.519667 Sending with 10 millisecond of delay
1163 02:14:19.201011 => setenv serverip 192.168.6.2
1164 02:14:19.211853 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1165 02:14:19.212820 setenv serverip 192.168.6.2
1166 02:14:19.213567 Sending with 10 millisecond of delay
1168 02:14:22.938080 => tftpboot 0x01080000 964261/tftp-deploy-wqquv6vj/kernel/uImage
1169 02:14:22.948660 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1170 02:14:22.949182 tftpboot 0x01080000 964261/tftp-deploy-wqquv6vj/kernel/uImage
1171 02:14:22.949430 Speed: 1000, full duplex
1172 02:14:22.949646 Using ethernet@ff3f0000 device
1173 02:14:22.951196 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1174 02:14:22.956723 Filename '964261/tftp-deploy-wqquv6vj/kernel/uImage'.
1175 02:14:22.960736 Load address: 0x1080000
1176 02:14:25.834392 Loading: *################################################## 43.6 MiB
1177 02:14:25.834775 15.2 MiB/s
1178 02:14:25.834987 done
1179 02:14:25.838731 Bytes transferred = 45713984 (2b98a40 hex)
1180 02:14:25.839226 Sending with 10 millisecond of delay
1182 02:14:30.527068 => tftpboot 0x08000000 964261/tftp-deploy-wqquv6vj/ramdisk/ramdisk.cpio.gz.uboot
1183 02:14:30.537878 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1184 02:14:30.538706 tftpboot 0x08000000 964261/tftp-deploy-wqquv6vj/ramdisk/ramdisk.cpio.gz.uboot
1185 02:14:30.539156 Speed: 1000, full duplex
1186 02:14:30.539569 Using ethernet@ff3f0000 device
1187 02:14:30.540603 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1188 02:14:30.549182 Filename '964261/tftp-deploy-wqquv6vj/ramdisk/ramdisk.cpio.gz.uboot'.
1189 02:14:30.549713 Load address: 0x8000000
1190 02:14:36.983316 Loading: *###################T ############################## UDP wrong checksum 00000005 00003be0
1191 02:14:41.984370 T UDP wrong checksum 00000005 00003be0
1192 02:14:47.364956 T UDP wrong checksum 000000ff 00005cb3
1193 02:14:47.412712 UDP wrong checksum 000000ff 0000f8a5
1194 02:14:51.987417 T UDP wrong checksum 00000005 00003be0
1195 02:15:11.991300 T T T T UDP wrong checksum 00000005 00003be0
1196 02:15:18.784308 T UDP wrong checksum 000000ff 0000252f
1197 02:15:18.823284 UDP wrong checksum 000000ff 00007db0
1198 02:15:23.685579 T UDP wrong checksum 000000ff 000082bd
1199 02:15:23.705483 UDP wrong checksum 000000ff 000017b0
1200 02:15:26.995499
1201 02:15:26.995930 Retry count exceeded; starting again
1203 02:15:26.996849 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1206 02:15:26.997782 end: 2.4 uboot-commands (duration 00:01:51) [common]
1208 02:15:26.998488 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1210 02:15:26.999035 end: 2 uboot-action (duration 00:01:51) [common]
1212 02:15:26.999856 Cleaning after the job
1213 02:15:27.000306 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/ramdisk
1214 02:15:27.001838 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/kernel
1215 02:15:27.048800 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/dtb
1216 02:15:27.049691 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/nfsrootfs
1217 02:15:27.218628 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964261/tftp-deploy-wqquv6vj/modules
1218 02:15:27.241087 start: 4.1 power-off (timeout 00:00:30) [common]
1219 02:15:27.241779 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1220 02:15:27.274818 >> OK - accepted request
1221 02:15:27.276897 Returned 0 in 0 seconds
1222 02:15:27.377708 end: 4.1 power-off (duration 00:00:00) [common]
1224 02:15:27.378722 start: 4.2 read-feedback (timeout 00:10:00) [common]
1225 02:15:27.379408 Listened to connection for namespace 'common' for up to 1s
1226 02:15:28.379519 Finalising connection for namespace 'common'
1227 02:15:28.380066 Disconnecting from shell: Finalise
1228 02:15:28.380375 =>
1229 02:15:28.481225 end: 4.2 read-feedback (duration 00:00:01) [common]
1230 02:15:28.481933 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/964261
1231 02:15:31.796032 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/964261
1232 02:15:31.796679 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.