Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 02:51:40.078810 lava-dispatcher, installed at version: 2024.01
2 02:51:40.079634 start: 0 validate
3 02:51:40.080127 Start time: 2024-11-09 02:51:40.080096+00:00 (UTC)
4 02:51:40.080671 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 02:51:40.081205 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 02:51:40.114704 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 02:51:40.115679 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-247-gbf99f9b489d8e%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 02:51:41.149299 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 02:51:41.150010 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-247-gbf99f9b489d8e%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 02:51:41.179356 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 02:51:41.179937 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 02:51:41.211104 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 02:51:41.211675 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-247-gbf99f9b489d8e%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 02:51:42.250500 validate duration: 2.17
16 02:51:42.251422 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:51:42.251748 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:51:42.252031 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:51:42.252623 Not decompressing ramdisk as can be used compressed.
20 02:51:42.253177 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 02:51:42.253478 saving as /var/lib/lava/dispatcher/tmp/964515/tftp-deploy-bvnnvfbu/ramdisk/initrd.cpio.gz
22 02:51:42.253750 total size: 4775763 (4 MB)
23 02:51:42.288328 progress 0 % (0 MB)
24 02:51:42.293694 progress 5 % (0 MB)
25 02:51:42.297717 progress 10 % (0 MB)
26 02:51:42.301216 progress 15 % (0 MB)
27 02:51:42.305457 progress 20 % (0 MB)
28 02:51:42.308904 progress 25 % (1 MB)
29 02:51:42.312416 progress 30 % (1 MB)
30 02:51:42.316252 progress 35 % (1 MB)
31 02:51:42.319654 progress 40 % (1 MB)
32 02:51:42.323171 progress 45 % (2 MB)
33 02:51:42.326598 progress 50 % (2 MB)
34 02:51:42.330328 progress 55 % (2 MB)
35 02:51:42.333690 progress 60 % (2 MB)
36 02:51:42.337047 progress 65 % (2 MB)
37 02:51:42.341084 progress 70 % (3 MB)
38 02:51:42.344439 progress 75 % (3 MB)
39 02:51:42.347894 progress 80 % (3 MB)
40 02:51:42.351697 progress 85 % (3 MB)
41 02:51:42.355687 progress 90 % (4 MB)
42 02:51:42.359045 progress 95 % (4 MB)
43 02:51:42.361975 progress 100 % (4 MB)
44 02:51:42.362611 4 MB downloaded in 0.11 s (41.85 MB/s)
45 02:51:42.363156 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:51:42.364021 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:51:42.364322 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:51:42.364598 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:51:42.365078 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 02:51:42.365342 saving as /var/lib/lava/dispatcher/tmp/964515/tftp-deploy-bvnnvfbu/kernel/zImage
52 02:51:42.365558 total size: 11440640 (10 MB)
53 02:51:42.365776 No compression specified
54 02:51:43.361181 progress 0 % (0 MB)
55 02:51:43.368862 progress 5 % (0 MB)
56 02:51:43.376574 progress 10 % (1 MB)
57 02:51:43.384746 progress 15 % (1 MB)
58 02:51:43.392523 progress 20 % (2 MB)
59 02:51:43.400293 progress 25 % (2 MB)
60 02:51:43.407935 progress 30 % (3 MB)
61 02:51:43.415797 progress 35 % (3 MB)
62 02:51:43.423422 progress 40 % (4 MB)
63 02:51:43.431312 progress 45 % (4 MB)
64 02:51:43.438883 progress 50 % (5 MB)
65 02:51:43.446732 progress 55 % (6 MB)
66 02:51:43.454248 progress 60 % (6 MB)
67 02:51:43.461635 progress 65 % (7 MB)
68 02:51:43.469768 progress 70 % (7 MB)
69 02:51:43.478317 progress 75 % (8 MB)
70 02:51:43.486636 progress 80 % (8 MB)
71 02:51:43.494640 progress 85 % (9 MB)
72 02:51:43.502878 progress 90 % (9 MB)
73 02:51:43.510629 progress 95 % (10 MB)
74 02:51:43.518279 progress 100 % (10 MB)
75 02:51:43.518848 10 MB downloaded in 1.15 s (9.46 MB/s)
76 02:51:43.519353 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:51:43.520230 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:51:43.520511 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:51:43.520783 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:51:43.521274 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 02:51:43.521520 saving as /var/lib/lava/dispatcher/tmp/964515/tftp-deploy-bvnnvfbu/dtb/am335x-boneblack.dtb
83 02:51:43.521724 total size: 70568 (0 MB)
84 02:51:43.522042 No compression specified
85 02:51:43.557132 progress 46 % (0 MB)
86 02:51:43.557999 progress 92 % (0 MB)
87 02:51:43.558695 progress 100 % (0 MB)
88 02:51:43.559088 0 MB downloaded in 0.04 s (1.80 MB/s)
89 02:51:43.559549 end: 1.3.1 http-download (duration 00:00:00) [common]
91 02:51:43.560381 end: 1.3 download-retry (duration 00:00:00) [common]
92 02:51:43.560663 start: 1.4 download-retry (timeout 00:09:59) [common]
93 02:51:43.560936 start: 1.4.1 http-download (timeout 00:09:59) [common]
94 02:51:43.561418 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 02:51:43.561673 saving as /var/lib/lava/dispatcher/tmp/964515/tftp-deploy-bvnnvfbu/nfsrootfs/full.rootfs.tar
96 02:51:43.561905 total size: 117747780 (112 MB)
97 02:51:43.562122 Using unxz to decompress xz
98 02:51:43.594122 progress 0 % (0 MB)
99 02:51:44.382043 progress 5 % (5 MB)
100 02:51:45.143333 progress 10 % (11 MB)
101 02:51:45.915409 progress 15 % (16 MB)
102 02:51:46.657087 progress 20 % (22 MB)
103 02:51:47.236242 progress 25 % (28 MB)
104 02:51:48.053214 progress 30 % (33 MB)
105 02:51:48.898341 progress 35 % (39 MB)
106 02:51:49.235547 progress 40 % (44 MB)
107 02:51:49.587242 progress 45 % (50 MB)
108 02:51:50.287787 progress 50 % (56 MB)
109 02:51:51.141533 progress 55 % (61 MB)
110 02:51:51.898256 progress 60 % (67 MB)
111 02:51:52.650047 progress 65 % (73 MB)
112 02:51:53.429675 progress 70 % (78 MB)
113 02:51:54.214391 progress 75 % (84 MB)
114 02:51:54.991870 progress 80 % (89 MB)
115 02:51:55.803880 progress 85 % (95 MB)
116 02:51:56.651486 progress 90 % (101 MB)
117 02:51:57.456468 progress 95 % (106 MB)
118 02:51:58.294715 progress 100 % (112 MB)
119 02:51:58.308400 112 MB downloaded in 14.75 s (7.61 MB/s)
120 02:51:58.309448 end: 1.4.1 http-download (duration 00:00:15) [common]
122 02:51:58.310534 end: 1.4 download-retry (duration 00:00:15) [common]
123 02:51:58.310978 start: 1.5 download-retry (timeout 00:09:44) [common]
124 02:51:58.311519 start: 1.5.1 http-download (timeout 00:09:44) [common]
125 02:51:58.312606 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 02:51:58.312914 saving as /var/lib/lava/dispatcher/tmp/964515/tftp-deploy-bvnnvfbu/modules/modules.tar
127 02:51:58.313130 total size: 6607460 (6 MB)
128 02:51:58.313350 Using unxz to decompress xz
129 02:51:58.344733 progress 0 % (0 MB)
130 02:51:58.382655 progress 5 % (0 MB)
131 02:51:58.431434 progress 10 % (0 MB)
132 02:51:58.481755 progress 15 % (0 MB)
133 02:51:58.529556 progress 20 % (1 MB)
134 02:51:58.579771 progress 25 % (1 MB)
135 02:51:58.627560 progress 30 % (1 MB)
136 02:51:58.673025 progress 35 % (2 MB)
137 02:51:58.718778 progress 40 % (2 MB)
138 02:51:58.763379 progress 45 % (2 MB)
139 02:51:58.807065 progress 50 % (3 MB)
140 02:51:58.852648 progress 55 % (3 MB)
141 02:51:58.907331 progress 60 % (3 MB)
142 02:51:58.959949 progress 65 % (4 MB)
143 02:51:59.011105 progress 70 % (4 MB)
144 02:51:59.065766 progress 75 % (4 MB)
145 02:51:59.115821 progress 80 % (5 MB)
146 02:51:59.166440 progress 85 % (5 MB)
147 02:51:59.213239 progress 90 % (5 MB)
148 02:51:59.266744 progress 95 % (6 MB)
149 02:51:59.317474 progress 100 % (6 MB)
150 02:51:59.334506 6 MB downloaded in 1.02 s (6.17 MB/s)
151 02:51:59.335118 end: 1.5.1 http-download (duration 00:00:01) [common]
153 02:51:59.336073 end: 1.5 download-retry (duration 00:00:01) [common]
154 02:51:59.336411 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
155 02:51:59.336727 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
156 02:52:16.969862 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/964515/extract-nfsrootfs-h9pj447g
157 02:52:16.970542 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
158 02:52:16.970877 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
159 02:52:16.971627 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb
160 02:52:16.972135 makedir: /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin
161 02:52:16.972620 makedir: /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/tests
162 02:52:16.973614 makedir: /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/results
163 02:52:16.974039 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-add-keys
164 02:52:16.974705 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-add-sources
165 02:52:16.975247 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-background-process-start
166 02:52:16.975746 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-background-process-stop
167 02:52:16.976376 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-common-functions
168 02:52:16.976935 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-echo-ipv4
169 02:52:16.977439 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-install-packages
170 02:52:16.978045 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-installed-packages
171 02:52:16.978567 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-os-build
172 02:52:16.979060 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-probe-channel
173 02:52:16.979546 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-probe-ip
174 02:52:16.980027 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-target-ip
175 02:52:16.980520 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-target-mac
176 02:52:16.981076 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-target-storage
177 02:52:16.981619 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-test-case
178 02:52:16.982220 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-test-event
179 02:52:16.982747 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-test-feedback
180 02:52:16.983309 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-test-raise
181 02:52:16.983827 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-test-reference
182 02:52:16.984391 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-test-runner
183 02:52:16.984904 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-test-set
184 02:52:16.985449 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-test-shell
185 02:52:16.985994 Updating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-add-keys (debian)
186 02:52:16.986551 Updating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-add-sources (debian)
187 02:52:16.987198 Updating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-install-packages (debian)
188 02:52:16.987732 Updating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-installed-packages (debian)
189 02:52:16.988280 Updating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/bin/lava-os-build (debian)
190 02:52:16.988733 Creating /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/environment
191 02:52:16.989106 LAVA metadata
192 02:52:16.989365 - LAVA_JOB_ID=964515
193 02:52:16.989576 - LAVA_DISPATCHER_IP=192.168.6.3
194 02:52:16.989955 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
195 02:52:16.990912 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 02:52:16.991223 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
197 02:52:16.991487 skipped lava-vland-overlay
198 02:52:16.991735 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 02:52:16.991991 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
200 02:52:16.992210 skipped lava-multinode-overlay
201 02:52:16.992494 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 02:52:16.992752 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
203 02:52:16.993001 Loading test definitions
204 02:52:16.993321 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
205 02:52:16.993565 Using /lava-964515 at stage 0
206 02:52:16.994784 uuid=964515_1.6.2.4.1 testdef=None
207 02:52:16.995093 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 02:52:16.995356 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
209 02:52:16.997089 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 02:52:16.997900 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
212 02:52:16.999854 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 02:52:17.000673 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
215 02:52:17.002605 runner path: /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/0/tests/0_timesync-off test_uuid 964515_1.6.2.4.1
216 02:52:17.003279 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 02:52:17.004155 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
219 02:52:17.004377 Using /lava-964515 at stage 0
220 02:52:17.004786 Fetching tests from https://github.com/kernelci/test-definitions.git
221 02:52:17.005090 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/0/tests/1_kselftest-dt'
222 02:52:20.697513 Running '/usr/bin/git checkout kernelci.org
223 02:52:21.168865 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 02:52:21.170347 uuid=964515_1.6.2.4.5 testdef=None
225 02:52:21.170696 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 02:52:21.171442 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
228 02:52:21.174347 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 02:52:21.175175 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
231 02:52:21.179051 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 02:52:21.179920 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
234 02:52:21.183637 runner path: /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/0/tests/1_kselftest-dt test_uuid 964515_1.6.2.4.5
235 02:52:21.183947 BOARD='beaglebone-black'
236 02:52:21.184150 BRANCH='broonie-sound'
237 02:52:21.184344 SKIPFILE='/dev/null'
238 02:52:21.184539 SKIP_INSTALL='True'
239 02:52:21.184731 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 02:52:21.184927 TST_CASENAME=''
241 02:52:21.185119 TST_CMDFILES='dt'
242 02:52:21.185715 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 02:52:21.186558 Creating lava-test-runner.conf files
245 02:52:21.186762 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/964515/lava-overlay-s1und1vb/lava-964515/0 for stage 0
246 02:52:21.187156 - 0_timesync-off
247 02:52:21.187412 - 1_kselftest-dt
248 02:52:21.187752 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 02:52:21.188032 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
250 02:52:44.673905 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 02:52:44.674365 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
252 02:52:44.674628 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 02:52:44.674898 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 02:52:44.675162 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
255 02:52:45.098021 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 02:52:45.098496 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
257 02:52:45.098767 extracting modules file /var/lib/lava/dispatcher/tmp/964515/tftp-deploy-bvnnvfbu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964515/extract-nfsrootfs-h9pj447g
258 02:52:46.021671 extracting modules file /var/lib/lava/dispatcher/tmp/964515/tftp-deploy-bvnnvfbu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964515/extract-overlay-ramdisk-nbef02qp/ramdisk
259 02:52:46.978702 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 02:52:46.979183 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
261 02:52:46.979432 [common] Applying overlay to NFS
262 02:52:46.979643 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964515/compress-overlay-91gkeatp/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/964515/extract-nfsrootfs-h9pj447g
263 02:52:49.852734 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 02:52:49.853231 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
265 02:52:49.853516 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
266 02:52:49.853835 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 02:52:49.854107 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 02:52:49.854365 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
269 02:52:49.854611 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 02:52:49.854877 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
271 02:52:49.855101 Building ramdisk /var/lib/lava/dispatcher/tmp/964515/extract-overlay-ramdisk-nbef02qp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/964515/extract-overlay-ramdisk-nbef02qp/ramdisk
272 02:52:50.944668 >> 74896 blocks
273 02:52:55.551593 Adding RAMdisk u-boot header.
274 02:52:55.552042 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/964515/extract-overlay-ramdisk-nbef02qp/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/964515/extract-overlay-ramdisk-nbef02qp/ramdisk.cpio.gz.uboot
275 02:52:55.716297 output: Image Name:
276 02:52:55.716720 output: Created: Sat Nov 9 02:52:55 2024
277 02:52:55.716969 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 02:52:55.717210 output: Data Size: 14788689 Bytes = 14442.08 KiB = 14.10 MiB
279 02:52:55.717447 output: Load Address: 00000000
280 02:52:55.717678 output: Entry Point: 00000000
281 02:52:55.717956 output:
282 02:52:55.718567 rename /var/lib/lava/dispatcher/tmp/964515/extract-overlay-ramdisk-nbef02qp/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/964515/tftp-deploy-bvnnvfbu/ramdisk/ramdisk.cpio.gz.uboot
283 02:52:55.719014 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 02:52:55.719356 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 02:52:55.719687 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:47) [common]
286 02:52:55.719973 No LXC device requested
287 02:52:55.720280 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 02:52:55.720595 start: 1.8 deploy-device-env (timeout 00:08:47) [common]
289 02:52:55.720898 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 02:52:55.721149 Checking files for TFTP limit of 4294967296 bytes.
291 02:52:55.722822 end: 1 tftp-deploy (duration 00:01:13) [common]
292 02:52:55.723189 start: 2 uboot-action (timeout 00:05:00) [common]
293 02:52:55.723513 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 02:52:55.723816 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 02:52:55.724125 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 02:52:55.724577 substitutions:
297 02:52:55.724841 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 02:52:55.725082 - {DTB_ADDR}: 0x88000000
299 02:52:55.725311 - {DTB}: 964515/tftp-deploy-bvnnvfbu/dtb/am335x-boneblack.dtb
300 02:52:55.725542 - {INITRD}: 964515/tftp-deploy-bvnnvfbu/ramdisk/ramdisk.cpio.gz.uboot
301 02:52:55.725771 - {KERNEL_ADDR}: 0x82000000
302 02:52:55.726026 - {KERNEL}: 964515/tftp-deploy-bvnnvfbu/kernel/zImage
303 02:52:55.726253 - {LAVA_MAC}: None
304 02:52:55.726511 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/964515/extract-nfsrootfs-h9pj447g
305 02:52:55.726749 - {NFS_SERVER_IP}: 192.168.6.3
306 02:52:55.726972 - {PRESEED_CONFIG}: None
307 02:52:55.727193 - {PRESEED_LOCAL}: None
308 02:52:55.727417 - {RAMDISK_ADDR}: 0x83000000
309 02:52:55.727639 - {RAMDISK}: 964515/tftp-deploy-bvnnvfbu/ramdisk/ramdisk.cpio.gz.uboot
310 02:52:55.727863 - {ROOT_PART}: None
311 02:52:55.728086 - {ROOT}: None
312 02:52:55.728308 - {SERVER_IP}: 192.168.6.3
313 02:52:55.728529 - {TEE_ADDR}: 0x83000000
314 02:52:55.728749 - {TEE}: None
315 02:52:55.728966 Parsed boot commands:
316 02:52:55.729182 - setenv autoload no
317 02:52:55.729406 - setenv initrd_high 0xffffffff
318 02:52:55.729624 - setenv fdt_high 0xffffffff
319 02:52:55.729866 - dhcp
320 02:52:55.730095 - setenv serverip 192.168.6.3
321 02:52:55.730317 - tftp 0x82000000 964515/tftp-deploy-bvnnvfbu/kernel/zImage
322 02:52:55.730541 - tftp 0x83000000 964515/tftp-deploy-bvnnvfbu/ramdisk/ramdisk.cpio.gz.uboot
323 02:52:55.730763 - setenv initrd_size ${filesize}
324 02:52:55.730982 - tftp 0x88000000 964515/tftp-deploy-bvnnvfbu/dtb/am335x-boneblack.dtb
325 02:52:55.731204 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/964515/extract-nfsrootfs-h9pj447g,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 02:52:55.731433 - bootz 0x82000000 0x83000000 0x88000000
327 02:52:55.731730 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 02:52:55.732587 start: 2.3 connect-device (timeout 00:05:00) [common]
330 02:52:55.732842 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 02:52:55.745015 Setting prompt string to ['lava-test: # ']
332 02:52:55.746002 end: 2.3 connect-device (duration 00:00:00) [common]
333 02:52:55.746477 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 02:52:55.746837 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 02:52:55.747168 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 02:52:55.747961 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 02:52:55.779621 >> OK - accepted request
338 02:52:55.781607 Returned 0 in 0 seconds
339 02:52:55.882490 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 02:52:55.883607 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 02:52:55.883990 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 02:52:55.884332 Setting prompt string to ['Hit any key to stop autoboot']
344 02:52:55.884626 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 02:52:55.885653 Trying 192.168.56.22...
346 02:52:55.886038 Connected to conserv3.
347 02:52:55.886310 Escape character is '^]'.
348 02:52:55.886565
349 02:52:55.886821 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 02:52:55.887073
351 02:53:04.877121
352 02:53:04.884172 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 02:53:04.885208 Trying to boot from MMC1
354 02:53:08.939599
355 02:53:08.946414 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 02:53:08.946819 Trying to boot from MMC1
357 02:53:11.622705
358 02:53:11.629749 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 02:53:11.630121 Trying to boot from MMC1
360 02:53:12.213159
361 02:53:12.213603
362 02:53:12.218819 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 02:53:12.219356
364 02:53:12.219834 CPU : AM335X-GP rev 2.0
365 02:53:12.223850 Model: TI AM335x BeagleBone Black
366 02:53:12.224349 DRAM: 512 MiB
367 02:53:12.303857 Core: 160 devices, 18 uclasses, devicetree: separate
368 02:53:12.317473 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 02:53:12.719335 NAND: 0 MiB
370 02:53:12.728608 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 02:53:12.855255 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 02:53:12.877401 <ethaddr> not set. Validating first E-fuse MAC
373 02:53:12.907789 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 02:53:12.966005 Hit any key to stop autoboot: 2
376 02:53:12.967025 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
377 02:53:12.967410 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
378 02:53:12.967686 Setting prompt string to ['=>']
379 02:53:12.967956 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
380 02:53:12.975569 0
381 02:53:12.976216 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 02:53:12.976527 Sending with 10 millisecond of delay
384 02:53:14.111536 => setenv autoload no
385 02:53:14.122471 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
386 02:53:14.127921 setenv autoload no
387 02:53:14.128700 Sending with 10 millisecond of delay
389 02:53:15.928285 => setenv initrd_high 0xffffffff
390 02:53:15.939064 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
391 02:53:15.939671 setenv initrd_high 0xffffffff
392 02:53:15.940151 Sending with 10 millisecond of delay
394 02:53:17.556957 => setenv fdt_high 0xffffffff
395 02:53:17.567834 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
396 02:53:17.568793 setenv fdt_high 0xffffffff
397 02:53:17.569573 Sending with 10 millisecond of delay
399 02:53:17.861629 => dhcp
400 02:53:17.872451 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
401 02:53:17.873355 dhcp
402 02:53:17.873885 link up on port 0, speed 100, full duplex
403 02:53:17.874342 BOOTP broadcast 1
404 02:53:18.127607 BOOTP broadcast 2
405 02:53:18.628920 BOOTP broadcast 3
406 02:53:19.631609 BOOTP broadcast 4
407 02:53:21.634260 BOOTP broadcast 5
408 02:53:21.733780 DHCP client bound to address 192.168.6.8 (3856 ms)
409 02:53:21.734480 Sending with 10 millisecond of delay
411 02:53:23.414717 => setenv serverip 192.168.6.3
412 02:53:23.425594 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
413 02:53:23.426652 setenv serverip 192.168.6.3
414 02:53:23.427481 Sending with 10 millisecond of delay
416 02:53:26.912325 => tftp 0x82000000 964515/tftp-deploy-bvnnvfbu/kernel/zImage
417 02:53:26.923207 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
418 02:53:26.924351 tftp 0x82000000 964515/tftp-deploy-bvnnvfbu/kernel/zImage
419 02:53:26.924883 link up on port 0, speed 100, full duplex
420 02:53:26.928151 Using ethernet@4a100000 device
421 02:53:26.934533 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
422 02:53:26.935089 Filename '964515/tftp-deploy-bvnnvfbu/kernel/zImage'.
423 02:53:26.937063 Load address: 0x82000000
424 02:53:29.006177 Loading: *################################################## 10.9 MiB
425 02:53:29.006586 5.3 MiB/s
426 02:53:29.006795 done
427 02:53:29.009766 Bytes transferred = 11440640 (ae9200 hex)
428 02:53:29.010293 Sending with 10 millisecond of delay
430 02:53:33.457434 => tftp 0x83000000 964515/tftp-deploy-bvnnvfbu/ramdisk/ramdisk.cpio.gz.uboot
431 02:53:33.468350 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
432 02:53:33.469324 tftp 0x83000000 964515/tftp-deploy-bvnnvfbu/ramdisk/ramdisk.cpio.gz.uboot
433 02:53:33.469794 link up on port 0, speed 100, full duplex
434 02:53:33.473059 Using ethernet@4a100000 device
435 02:53:33.478851 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
436 02:53:33.487444 Filename '964515/tftp-deploy-bvnnvfbu/ramdisk/ramdisk.cpio.gz.uboot'.
437 02:53:33.488061 Load address: 0x83000000
438 02:53:36.220298 Loading: *################################################## 14.1 MiB
439 02:53:36.220937 5.2 MiB/s
440 02:53:36.221392 done
441 02:53:36.224682 Bytes transferred = 14788753 (e1a891 hex)
442 02:53:36.225493 Sending with 10 millisecond of delay
444 02:53:38.085353 => setenv initrd_size ${filesize}
445 02:53:38.096142 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
446 02:53:38.096981 setenv initrd_size ${filesize}
447 02:53:38.097686 Sending with 10 millisecond of delay
449 02:53:42.249546 => tftp 0x88000000 964515/tftp-deploy-bvnnvfbu/dtb/am335x-boneblack.dtb
450 02:53:42.260877 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
451 02:53:42.261543 tftp 0x88000000 964515/tftp-deploy-bvnnvfbu/dtb/am335x-boneblack.dtb
452 02:53:42.261788 link up on port 0, speed 100, full duplex
453 02:53:42.264841 Using ethernet@4a100000 device
454 02:53:42.270377 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
455 02:53:42.278953 Filename '964515/tftp-deploy-bvnnvfbu/dtb/am335x-boneblack.dtb'.
456 02:53:42.279357 Load address: 0x88000000
457 02:53:42.297903 Loading: *################################################## 68.9 KiB
458 02:53:42.298977 3.1 MiB/s
459 02:53:42.307685 done
460 02:53:42.308056 Bytes transferred = 70568 (113a8 hex)
461 02:53:42.308515 Sending with 10 millisecond of delay
463 02:53:55.496303 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/964515/extract-nfsrootfs-h9pj447g,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
464 02:53:55.509185 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
465 02:53:55.509767 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/964515/extract-nfsrootfs-h9pj447g,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
466 02:53:55.510281 Sending with 10 millisecond of delay
468 02:53:57.852404 => bootz 0x82000000 0x83000000 0x88000000
469 02:53:57.863105 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
470 02:53:57.863447 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
471 02:53:57.864011 bootz 0x82000000 0x83000000 0x88000000
472 02:53:57.864252 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
473 02:53:57.864701 ## Loading init Ramdisk from Legacy Image at 83000000 ...
474 02:53:57.870275 Image Name:
475 02:53:57.870533 Created: 2024-11-09 2:52:55 UTC
476 02:53:57.875874 Image Type: ARM Linux RAMDisk Image (uncompressed)
477 02:53:57.881415 Data Size: 14788689 Bytes = 14.1 MiB
478 02:53:57.881662 Load Address: 00000000
479 02:53:57.887581 Entry Point: 00000000
480 02:53:58.056129 Verifying Checksum ... OK
481 02:53:58.056773 ## Flattened Device Tree blob at 88000000
482 02:53:58.062900 Booting using the fdt blob at 0x88000000
483 02:53:58.063524 Working FDT set to 88000000
484 02:53:58.068147 Using Device Tree in place at 88000000, end 880143a7
485 02:53:58.071544 Working FDT set to 88000000
486 02:53:58.085334
487 02:53:58.086055 Starting kernel ...
488 02:53:58.086474
489 02:53:58.087379 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
490 02:53:58.088013 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
491 02:53:58.088484 Setting prompt string to ['Linux version [0-9]']
492 02:53:58.088935 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
493 02:53:58.089402 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
494 02:53:58.929414 [ 0.000000] Booting Linux on physical CPU 0x0
495 02:53:58.935378 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
496 02:53:58.935955 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
497 02:53:58.936420 Setting prompt string to []
498 02:53:58.936906 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
499 02:53:58.937363 Using line separator: #'\n'#
500 02:53:58.937771 No login prompt set.
501 02:53:58.938250 Parsing kernel messages
502 02:53:58.938641 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
503 02:53:58.939416 [login-action] Waiting for messages, (timeout 00:03:57)
504 02:53:58.939837 Waiting using forced prompt support (timeout 00:01:58)
505 02:53:58.952060 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j370473-arm-gcc-12-multi-v7-defconfig-8p7xw) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Sat Nov 9 02:39:56 UTC 2024
506 02:53:58.957796 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
507 02:53:58.963497 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
508 02:53:58.975076 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
509 02:53:58.980679 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
510 02:53:58.986431 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
511 02:53:58.986888 [ 0.000000] Memory policy: Data cache writeback
512 02:53:58.993092 [ 0.000000] efi: UEFI not found.
513 02:53:58.997583 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
514 02:53:59.004301 [ 0.000000] Zone ranges:
515 02:53:59.010067 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
516 02:53:59.015807 [ 0.000000] Normal empty
517 02:53:59.016244 [ 0.000000] HighMem empty
518 02:53:59.018619 [ 0.000000] Movable zone start for each node
519 02:53:59.024346 [ 0.000000] Early memory node ranges
520 02:53:59.030119 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
521 02:53:59.037338 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
522 02:53:59.063686 [ 0.000000] CPU: All CPU(s) started in SVC mode.
523 02:53:59.068258 [ 0.000000] AM335X ES2.0 (sgx neon)
524 02:53:59.080853 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
525 02:53:59.101345 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/964515/extract-nfsrootfs-h9pj447g,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
526 02:53:59.107161 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
527 02:53:59.118582 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
528 02:53:59.124375 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
529 02:53:59.130739 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
530 02:53:59.160540 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
531 02:53:59.166468 <6>[ 0.000000] trace event string verifier disabled
532 02:53:59.166979 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
533 02:53:59.174459 <6>[ 0.000000] rcu: RCU event tracing is enabled.
534 02:53:59.180175 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
535 02:53:59.191574 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
536 02:53:59.196630 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
537 02:53:59.211502 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
538 02:53:59.228627 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
539 02:53:59.234660 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
540 02:53:59.327123 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
541 02:53:59.338543 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
542 02:53:59.345327 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
543 02:53:59.358368 <6>[ 0.019147] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
544 02:53:59.365618 <6>[ 0.033938] Console: colour dummy device 80x30
545 02:53:59.371754 Matched prompt #6: WARNING:
546 02:53:59.372303 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
547 02:53:59.377168 <3>[ 0.038836] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
548 02:53:59.382889 <3>[ 0.045907] This ensures that you still see kernel messages. Please
549 02:53:59.386154 <3>[ 0.052633] update your kernel commandline.
550 02:53:59.426884 <6>[ 0.057247] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
551 02:53:59.432571 <6>[ 0.096161] CPU: Testing write buffer coherency: ok
552 02:53:59.438516 <6>[ 0.101531] CPU0: Spectre v2: using BPIALL workaround
553 02:53:59.438998 <6>[ 0.106994] pid_max: default: 32768 minimum: 301
554 02:53:59.450060 <6>[ 0.112184] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
555 02:53:59.457061 <6>[ 0.120010] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
556 02:53:59.464096 <6>[ 0.129370] CPU0: thread -1, cpu 0, socket -1, mpidr 0
557 02:53:59.472487 <6>[ 0.136374] Setting up static identity map for 0x80300000 - 0x803000ac
558 02:53:59.478244 <6>[ 0.146000] rcu: Hierarchical SRCU implementation.
559 02:53:59.485912 <6>[ 0.151287] rcu: Max phase no-delay instances is 1000.
560 02:53:59.494400 <6>[ 0.162405] EFI services will not be available.
561 02:53:59.500361 <6>[ 0.167688] smp: Bringing up secondary CPUs ...
562 02:53:59.506094 <6>[ 0.172734] smp: Brought up 1 node, 1 CPU
563 02:53:59.514209 <6>[ 0.177135] SMP: Total of 1 processors activated (996.14 BogoMIPS).
564 02:53:59.520135 <6>[ 0.183909] CPU: All CPU(s) started in SVC mode.
565 02:53:59.532280 <6>[ 0.189088] Memory: 406000K/522240K available (16384K kernel code, 2542K rwdata, 6784K rodata, 2048K init, 431K bss, 49048K reserved, 65536K cma-reserved, 0K highmem)
566 02:53:59.537139 <6>[ 0.205369] devtmpfs: initialized
567 02:53:59.560214 <6>[ 0.222420] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
568 02:53:59.571798 <6>[ 0.231002] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
569 02:53:59.577659 <6>[ 0.241458] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
570 02:53:59.587538 <6>[ 0.253812] pinctrl core: initialized pinctrl subsystem
571 02:53:59.597704 <6>[ 0.264422] DMI not present or invalid.
572 02:53:59.604660 <6>[ 0.270271] NET: Registered PF_NETLINK/PF_ROUTE protocol family
573 02:53:59.614520 <6>[ 0.279148] DMA: preallocated 256 KiB pool for atomic coherent allocations
574 02:53:59.629719 <6>[ 0.290664] thermal_sys: Registered thermal governor 'step_wise'
575 02:53:59.630288 <6>[ 0.290828] cpuidle: using governor menu
576 02:53:59.658224 <6>[ 0.326415] No ATAGs?
577 02:53:59.663537 <6>[ 0.329057] hw-breakpoint: debug architecture 0x4 unsupported.
578 02:53:59.673725 <6>[ 0.341108] Serial: AMBA PL011 UART driver
579 02:53:59.707212 <6>[ 0.375283] iommu: Default domain type: Translated
580 02:53:59.716324 <6>[ 0.380630] iommu: DMA domain TLB invalidation policy: strict mode
581 02:53:59.743223 <5>[ 0.410689] SCSI subsystem initialized
582 02:53:59.749147 <6>[ 0.415573] usbcore: registered new interface driver usbfs
583 02:53:59.754869 <6>[ 0.421632] usbcore: registered new interface driver hub
584 02:53:59.761699 <6>[ 0.427411] usbcore: registered new device driver usb
585 02:53:59.767354 <6>[ 0.433919] pps_core: LinuxPPS API ver. 1 registered
586 02:53:59.778861 <6>[ 0.439309] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
587 02:53:59.786083 <6>[ 0.449034] PTP clock support registered
588 02:53:59.786601 <6>[ 0.453490] EDAC MC: Ver: 3.0.0
589 02:53:59.833770 <6>[ 0.500409] scmi_core: SCMI protocol bus registered
590 02:53:59.848892 <6>[ 0.517757] vgaarb: loaded
591 02:53:59.862422 <6>[ 0.530775] clocksource: Switched to clocksource dmtimer
592 02:53:59.899035 <6>[ 0.566943] NET: Registered PF_INET protocol family
593 02:53:59.911622 <6>[ 0.572630] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
594 02:53:59.918710 <6>[ 0.581438] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
595 02:53:59.930173 <6>[ 0.590368] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
596 02:53:59.933055 <6>[ 0.598629] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
597 02:53:59.944637 <6>[ 0.606916] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
598 02:53:59.950332 <6>[ 0.614644] TCP: Hash tables configured (established 4096 bind 4096)
599 02:53:59.958838 <6>[ 0.621575] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
600 02:53:59.964732 <6>[ 0.628589] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
601 02:53:59.970415 <6>[ 0.636190] NET: Registered PF_UNIX/PF_LOCAL protocol family
602 02:54:00.062405 <6>[ 0.724923] RPC: Registered named UNIX socket transport module.
603 02:54:00.063063 <6>[ 0.731315] RPC: Registered udp transport module.
604 02:54:00.068249 <6>[ 0.736474] RPC: Registered tcp transport module.
605 02:54:00.074064 <6>[ 0.741596] RPC: Registered tcp-with-tls transport module.
606 02:54:00.086933 <6>[ 0.747505] RPC: Registered tcp NFSv4.1 backchannel transport module.
607 02:54:00.087540 <6>[ 0.754425] PCI: CLS 0 bytes, default 64
608 02:54:00.093201 <5>[ 0.760187] Initialise system trusted keyrings
609 02:54:00.113658 <6>[ 0.778754] Trying to unpack rootfs image as initramfs...
610 02:54:00.199283 <6>[ 0.861101] workingset: timestamp_bits=30 max_order=17 bucket_order=0
611 02:54:00.203113 <6>[ 0.868650] squashfs: version 4.0 (2009/01/31) Phillip Lougher
612 02:54:00.224442 <5>[ 0.892583] NFS: Registering the id_resolver key type
613 02:54:00.230272 <5>[ 0.898191] Key type id_resolver registered
614 02:54:00.236009 <5>[ 0.902880] Key type id_legacy registered
615 02:54:00.241899 <6>[ 0.907319] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
616 02:54:00.250336 <6>[ 0.914521] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
617 02:54:00.320294 <5>[ 0.988437] Key type asymmetric registered
618 02:54:00.326024 <5>[ 0.993019] Asymmetric key parser 'x509' registered
619 02:54:00.334750 <6>[ 0.998443] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
620 02:54:00.340226 <6>[ 1.006362] io scheduler mq-deadline registered
621 02:54:00.349040 <6>[ 1.011293] io scheduler kyber registered
622 02:54:00.349655 <6>[ 1.015777] io scheduler bfq registered
623 02:54:00.457791 <6>[ 1.122207] ledtrig-cpu: registered to indicate activity on CPUs
624 02:54:00.722831 <6>[ 1.386926] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
625 02:54:00.768747 <6>[ 1.436397] msm_serial: driver initialized
626 02:54:00.774743 <6>[ 1.441182] SuperH (H)SCI(F) driver initialized
627 02:54:00.782129 <6>[ 1.446477] STMicroelectronics ASC driver initialized
628 02:54:00.785932 <6>[ 1.452160] STM32 USART driver initialized
629 02:54:00.887087 <6>[ 1.554448] brd: module loaded
630 02:54:00.918720 <6>[ 1.586042] loop: module loaded
631 02:54:00.969486 <6>[ 1.629464] CAN device driver interface
632 02:54:00.970590 <6>[ 1.634635] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
633 02:54:00.974679 <6>[ 1.641543] e1000e: Intel(R) PRO/1000 Network Driver
634 02:54:00.981418 <6>[ 1.646990] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
635 02:54:00.987256 <6>[ 1.653421] igb: Intel(R) Gigabit Ethernet Network Driver
636 02:54:00.994438 <6>[ 1.659245] igb: Copyright (c) 2007-2014 Intel Corporation.
637 02:54:01.006798 <6>[ 1.668373] pegasus: Pegasus/Pegasus II USB Ethernet driver
638 02:54:01.012058 <6>[ 1.674549] usbcore: registered new interface driver pegasus
639 02:54:01.015015 <6>[ 1.680679] usbcore: registered new interface driver asix
640 02:54:01.020541 <6>[ 1.686565] usbcore: registered new interface driver ax88179_178a
641 02:54:01.026239 <6>[ 1.693156] usbcore: registered new interface driver cdc_ether
642 02:54:01.031954 <6>[ 1.699454] usbcore: registered new interface driver smsc75xx
643 02:54:01.043689 <6>[ 1.705682] usbcore: registered new interface driver smsc95xx
644 02:54:01.051939 <6>[ 1.711913] usbcore: registered new interface driver net1080
645 02:54:01.055138 <6>[ 1.718043] usbcore: registered new interface driver cdc_subset
646 02:54:01.060936 <6>[ 1.724464] usbcore: registered new interface driver zaurus
647 02:54:01.065740 <6>[ 1.730511] usbcore: registered new interface driver cdc_ncm
648 02:54:01.075524 <6>[ 1.739877] usbcore: registered new interface driver usb-storage
649 02:54:01.347979 <6>[ 2.013692] i2c_dev: i2c /dev entries driver
650 02:54:01.407941 <5>[ 2.067728] cpuidle: enable-method property 'ti,am3352' found operations
651 02:54:01.413708 <6>[ 2.077294] sdhci: Secure Digital Host Controller Interface driver
652 02:54:01.420958 <6>[ 2.084068] sdhci: Copyright(c) Pierre Ossman
653 02:54:01.428068 <6>[ 2.090421] Synopsys Designware Multimedia Card Interface Driver
654 02:54:01.433750 <6>[ 2.098287] sdhci-pltfm: SDHCI platform and OF driver helper
655 02:54:01.564181 <6>[ 2.222698] usbcore: registered new interface driver usbhid
656 02:54:01.564608 <6>[ 2.228741] usbhid: USB HID core driver
657 02:54:01.612366 <6>[ 2.277685] NET: Registered PF_INET6 protocol family
658 02:54:01.635924 <6>[ 2.303989] Segment Routing with IPv6
659 02:54:01.641757 <6>[ 2.308137] In-situ OAM (IOAM) with IPv6
660 02:54:01.648458 <6>[ 2.312680] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
661 02:54:01.655873 <6>[ 2.319933] NET: Registered PF_PACKET protocol family
662 02:54:01.661828 <6>[ 2.325498] can: controller area network core
663 02:54:01.662370 <6>[ 2.330319] NET: Registered PF_CAN protocol family
664 02:54:01.667641 <6>[ 2.335560] can: raw protocol
665 02:54:01.673403 <6>[ 2.338886] can: broadcast manager protocol
666 02:54:01.680325 <6>[ 2.343483] can: netlink gateway - max_hops=1
667 02:54:01.680862 <5>[ 2.348975] Key type dns_resolver registered
668 02:54:01.686032 <6>[ 2.354045] ThumbEE CPU extension supported.
669 02:54:01.692332 <5>[ 2.358729] Registering SWP/SWPB emulation handler
670 02:54:01.700445 <3>[ 2.364432] omap_voltage_late_init: Voltage driver support not added
671 02:54:01.896109 <5>[ 2.562274] Loading compiled-in X.509 certificates
672 02:54:02.025877 <6>[ 2.680891] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
673 02:54:02.033199 <6>[ 2.697574] pinctrl-single 44e10800.pinmux: 142 pins, size 568
674 02:54:02.059467 <3>[ 2.721280] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
675 02:54:02.269289 <3>[ 2.931183] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
676 02:54:02.465806 <6>[ 3.132012] OMAP GPIO hardware version 0.1
677 02:54:02.486293 <6>[ 3.150614] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
678 02:54:02.578997 <4>[ 3.243849] at24 2-0054: supply vcc not found, using dummy regulator
679 02:54:02.620749 <4>[ 3.285522] at24 2-0055: supply vcc not found, using dummy regulator
680 02:54:02.662715 <4>[ 3.327566] at24 2-0056: supply vcc not found, using dummy regulator
681 02:54:02.705854 <4>[ 3.369930] at24 2-0057: supply vcc not found, using dummy regulator
682 02:54:02.740062 <6>[ 3.405605] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
683 02:54:02.817272 <3>[ 3.478202] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
684 02:54:02.841843 <6>[ 3.499068] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
685 02:54:02.863775 <4>[ 3.525303] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
686 02:54:02.871564 <4>[ 3.534461] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
687 02:54:03.027022 <6>[ 3.692012] omap_rng 48310000.rng: Random Number Generator ver. 20
688 02:54:03.051040 <5>[ 3.718136] random: crng init done
689 02:54:03.111878 <6>[ 3.779818] Freeing initrd memory: 14444K
690 02:54:03.121675 <6>[ 3.784521] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
691 02:54:03.172180 <6>[ 3.834081] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
692 02:54:03.177922 <6>[ 3.844388] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
693 02:54:03.189780 <6>[ 3.851745] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
694 02:54:03.195548 <6>[ 3.859186] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
695 02:54:03.207019 <6>[ 3.867318] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
696 02:54:03.214305 <6>[ 3.878958] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
697 02:54:03.227523 <5>[ 3.887975] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
698 02:54:03.255348 <3>[ 3.917734] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
699 02:54:03.260155 <6>[ 3.926326] edma 49000000.dma: TI EDMA DMA engine driver
700 02:54:03.332226 <3>[ 3.993957] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
701 02:54:03.346975 <6>[ 4.008316] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
702 02:54:03.359889 <3>[ 4.025446] l3-aon-clkctrl:0000:0: failed to disable
703 02:54:03.413067 <6>[ 4.075448] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
704 02:54:03.418771 <6>[ 4.084949] printk: legacy console [ttyS0] enabled
705 02:54:03.424592 <6>[ 4.084949] printk: legacy console [ttyS0] enabled
706 02:54:03.430330 <6>[ 4.095282] printk: legacy bootconsole [omap8250] disabled
707 02:54:03.436016 <6>[ 4.095282] printk: legacy bootconsole [omap8250] disabled
708 02:54:03.471024 <4>[ 4.132426] tps65217-pmic: Failed to locate of_node [id: -1]
709 02:54:03.474652 <4>[ 4.139825] tps65217-bl: Failed to locate of_node [id: -1]
710 02:54:03.491070 <6>[ 4.159428] tps65217 0-0024: TPS65217 ID 0xe version 1.2
711 02:54:03.511388 <6>[ 4.166378] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
712 02:54:03.523125 <6>[ 4.180063] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
713 02:54:03.525986 <6>[ 4.191948] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
714 02:54:03.549103 <6>[ 4.211966] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
715 02:54:03.555080 <6>[ 4.221021] sdhci-omap 48060000.mmc: Got CD GPIO
716 02:54:03.563125 <4>[ 4.226222] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
717 02:54:03.577743 <4>[ 4.239766] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
718 02:54:03.584075 <4>[ 4.248524] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
719 02:54:03.594014 <4>[ 4.257122] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
720 02:54:03.717550 <6>[ 4.381431] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
721 02:54:03.766809 <6>[ 4.428843] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
722 02:54:03.773010 <6>[ 4.437532] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
723 02:54:03.782081 <6>[ 4.446448] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
724 02:54:03.844549 <6>[ 4.509791] mmc1: new high speed MMC card at address 0001
725 02:54:03.852425 <6>[ 4.518642] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
726 02:54:03.868186 <6>[ 4.534022] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
727 02:54:03.874919 <6>[ 4.541779] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
728 02:54:03.886960 <6>[ 4.548145] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
729 02:54:03.896446 <6>[ 4.561082] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
730 02:54:03.952558 <6>[ 4.611219] mmc0: new high speed SDHC card at address aaaa
731 02:54:03.953170 <6>[ 4.618863] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
732 02:54:03.984070 <6>[ 4.650297] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
733 02:54:06.020059 <6>[ 6.682667] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
734 02:54:06.163358 <5>[ 6.711630] Sending DHCP requests ., OK
735 02:54:06.174726 <6>[ 6.836060] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
736 02:54:06.175238 <6>[ 6.844190] IP-Config: Complete:
737 02:54:06.186023 <6>[ 6.847730] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
738 02:54:06.191775 <6>[ 6.858156] host=192.168.6.8, domain=, nis-domain=(none)
739 02:54:06.197427 <6>[ 6.864277] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
740 02:54:06.204487 <6>[ 6.864310] nameserver0=10.255.253.1
741 02:54:06.210315 <6>[ 6.876970] clk: Disabling unused clocks
742 02:54:06.215836 <6>[ 6.881743] PM: genpd: Disabling unused power domains
743 02:54:06.234304 <6>[ 6.900123] Freeing unused kernel image (initmem) memory: 2048K
744 02:54:06.241764 <6>[ 6.909887] Run /init as init process
745 02:54:06.268172 Loading, please wait...
746 02:54:06.343579 Starting systemd-udevd version 252.22-1~deb12u1
747 02:54:09.398477 <4>[ 10.060756] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 02:54:09.538343 <4>[ 10.199626] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 02:54:09.683860 <6>[ 10.352577] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
750 02:54:09.694590 <6>[ 10.358250] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
751 02:54:09.904825 <6>[ 10.572051] hub 1-0:1.0: USB hub found
752 02:54:09.995593 <6>[ 10.662721] hub 1-0:1.0: 1 port detected
753 02:54:10.156943 <6>[ 10.823804] tda998x 0-0070: found TDA19988
754 02:54:13.069672 Begin: Loading essential drivers ... done.
755 02:54:13.075161 Begin: Running /scripts/init-premount ... done.
756 02:54:13.080797 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
757 02:54:13.094631 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
758 02:54:13.095204 Device /sys/class/net/eth0 found
759 02:54:13.095617 done.
760 02:54:13.168073 Begin: Waiting up to 180 secs for any network device to become available ... done.
761 02:54:13.266449 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
762 02:54:13.381785 IP-Config: eth0 guessed broadcast address 192.168.6.255
763 02:54:13.387359 IP-Config: eth0 complete (dhcp from 192.168.6.1):
764 02:54:13.392873 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
765 02:54:13.401869 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
766 02:54:13.407610 rootserver: 192.168.6.1 rootpath:
767 02:54:13.408064 filename :
768 02:54:13.469886 done.
769 02:54:13.482630 Begin: Running /scripts/nfs-bottom ... done.
770 02:54:13.558841 Begin: Running /scripts/init-bottom ... done.
771 02:54:14.800155 <30>[ 15.465488] systemd[1]: System time before build time, advancing clock.
772 02:54:14.978603 <30>[ 15.616945] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
773 02:54:14.987776 <30>[ 15.654096] systemd[1]: Detected architecture arm.
774 02:54:15.000404
775 02:54:15.000883 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
776 02:54:15.001304
777 02:54:15.025409 <30>[ 15.691267] systemd[1]: Hostname set to <debian-bookworm-armhf>.
778 02:54:17.161307 <30>[ 17.825235] systemd[1]: Queued start job for default target graphical.target.
779 02:54:17.178142 <30>[ 17.839923] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
780 02:54:17.186350 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
781 02:54:17.213280 <30>[ 17.874046] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
782 02:54:17.219582 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
783 02:54:17.245708 <30>[ 17.907829] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
784 02:54:17.258655 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
785 02:54:17.280820 <30>[ 17.943432] systemd[1]: Created slice user.slice - User and Session Slice.
786 02:54:17.286551 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
787 02:54:17.317378 <30>[ 17.973012] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
788 02:54:17.323408 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
789 02:54:17.352112 <30>[ 18.013745] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
790 02:54:17.363112 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
791 02:54:17.401133 <30>[ 18.052537] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
792 02:54:17.407443 <30>[ 18.072989] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
793 02:54:17.415916 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
794 02:54:17.439358 <30>[ 18.102068] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
795 02:54:17.447758 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
796 02:54:17.471420 <30>[ 18.133583] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
797 02:54:17.482818 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
798 02:54:17.509789 <30>[ 18.172403] systemd[1]: Reached target paths.target - Path Units.
799 02:54:17.514243 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
800 02:54:17.539964 <30>[ 18.202491] systemd[1]: Reached target remote-fs.target - Remote File Systems.
801 02:54:17.547429 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
802 02:54:17.569625 <30>[ 18.232154] systemd[1]: Reached target slices.target - Slice Units.
803 02:54:17.575090 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
804 02:54:17.599794 <30>[ 18.262375] systemd[1]: Reached target swap.target - Swaps.
805 02:54:17.603892 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
806 02:54:17.630401 <30>[ 18.292464] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
807 02:54:17.639678 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
808 02:54:17.660972 <30>[ 18.323145] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
809 02:54:17.669300 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
810 02:54:17.750227 <30>[ 18.407557] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
811 02:54:17.762770 <30>[ 18.424924] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
812 02:54:17.771138 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
813 02:54:17.792594 <30>[ 18.456042] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
814 02:54:17.804739 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
815 02:54:17.833562 <30>[ 18.494650] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
816 02:54:17.840756 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
817 02:54:17.876795 <30>[ 18.539484] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
818 02:54:17.889929 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
819 02:54:17.911767 <30>[ 18.573606] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
820 02:54:17.920065 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
821 02:54:17.947096 <30>[ 18.603358] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
822 02:54:17.963898 <30>[ 18.619992] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
823 02:54:18.013726 <30>[ 18.676881] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
824 02:54:18.043993 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
825 02:54:18.100816 <30>[ 18.764899] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
826 02:54:18.124553 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
827 02:54:18.220804 <30>[ 18.882946] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
828 02:54:18.240758 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
829 02:54:18.269304 <30>[ 18.931966] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
830 02:54:18.276553 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
831 02:54:18.319834 <30>[ 18.982988] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
832 02:54:18.334762 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
833 02:54:18.373773 <30>[ 19.037448] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
834 02:54:18.390002 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
835 02:54:18.451140 <30>[ 19.114454] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
836 02:54:18.477600 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
837 02:54:18.529188 <30>[ 19.193540] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
838 02:54:18.549328 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
839 02:54:18.584865 <30>[ 19.248380] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
840 02:54:18.605188 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
841 02:54:18.637174 <28>[ 19.293986] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
842 02:54:18.645716 <28>[ 19.308300] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
843 02:54:18.689195 <30>[ 19.353033] systemd[1]: Starting systemd-journald.service - Journal Service...
844 02:54:18.707868 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
845 02:54:18.790627 <30>[ 19.453814] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
846 02:54:18.803732 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
847 02:54:18.836891 <30>[ 19.500337] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
848 02:54:18.878631 Starting [0;1;39msystemd-network-g… units from Kernel command line...
849 02:54:18.934200 <30>[ 19.596172] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
850 02:54:18.999709 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
851 02:54:19.072670 <30>[ 19.735429] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
852 02:54:19.110654 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
853 02:54:19.198762 <30>[ 19.863275] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
854 02:54:19.238807 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
855 02:54:19.259941 <30>[ 19.923425] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
856 02:54:19.290867 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
857 02:54:19.312572 <30>[ 19.975583] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
858 02:54:19.348882 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
859 02:54:19.472361 <30>[ 20.137205] systemd[1]: modprobe@configfs.service: Deactivated successfully.
860 02:54:19.510452 <30>[ 20.173304] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
861 02:54:19.539635 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
862 02:54:19.570403 <30>[ 20.234564] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
863 02:54:19.600083 <30>[ 20.263305] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
864 02:54:19.627111 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
865 02:54:19.653617 <30>[ 20.317713] systemd[1]: Started systemd-journald.service - Journal Service.
866 02:54:19.668787 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
867 02:54:19.709591 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
868 02:54:19.741977 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
869 02:54:19.771297 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
870 02:54:19.795258 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
871 02:54:19.829724 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
872 02:54:19.852363 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
873 02:54:19.872009 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
874 02:54:19.894206 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
875 02:54:19.959924 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
876 02:54:20.001651 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
877 02:54:20.072552 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
878 02:54:20.153349 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
879 02:54:20.264359 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
880 02:54:20.353922 <46>[ 21.017245] systemd-journald[164]: Received client request to flush runtime journal.
881 02:54:20.401918 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
882 02:54:20.539579 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
883 02:54:21.345707 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
884 02:54:21.688769 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
885 02:54:21.750894 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
886 02:54:22.056626 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
887 02:54:22.273122 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
888 02:54:22.310291 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
889 02:54:22.329018 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
890 02:54:22.419525 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
891 02:54:22.462142 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
892 02:54:23.232197 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
893 02:54:24.769897 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
894 02:54:24.863286 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
895 02:54:25.000319 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
896 02:54:25.158339 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
897 02:54:25.216312 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
898 02:54:27.142637 [[0m[0;31m* [0m] (1 of 4) Job dev-ttyS0.device/start running (9s / 1min 30s)
899 02:54:27.190171 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
900 02:54:27.811038 [K<5>[ 28.474541] cfg80211: Loading compiled-in X.509 certificates for regulatory database
901 02:54:27.952784 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
902 02:54:29.288533 <5>[ 29.954309] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
903 02:54:29.348583 <5>[ 30.012785] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
904 02:54:29.362663 <4>[ 30.026127] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
905 02:54:29.368525 <6>[ 30.035280] cfg80211: failed to load regulatory.db
906 02:54:29.834334 <46>[ 30.487911] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
907 02:54:29.986562 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
908 02:54:30.085272 <46>[ 30.741973] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
909 02:54:30.621380 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
910 02:54:38.985327 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
911 02:54:39.009315 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
912 02:54:39.033057 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
913 02:54:39.075685 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
914 02:54:39.143559 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
915 02:54:39.190852 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
916 02:54:39.241044 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
917 02:54:39.310918 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
918 02:54:39.350260 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
919 02:54:39.377434 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
920 02:54:39.405584 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
921 02:54:39.434838 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
922 02:54:39.475482 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
923 02:54:39.507383 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
924 02:54:39.539707 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
925 02:54:39.572852 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
926 02:54:39.605314 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
927 02:54:39.633418 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
928 02:54:39.666033 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
929 02:54:39.688869 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
930 02:54:39.717041 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
931 02:54:39.739045 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
932 02:54:39.761977 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
933 02:54:39.829171 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
934 02:54:39.867302 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
935 02:54:39.967505 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
936 02:54:40.046330 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
937 02:54:40.129137 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
938 02:54:40.171391 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
939 02:54:40.211600 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
940 02:54:40.388758 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
941 02:54:40.450192 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
942 02:54:40.520386 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
943 02:54:40.548491 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
944 02:54:40.569997 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
945 02:54:40.766355 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
946 02:54:41.128644 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
947 02:54:41.177951 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
948 02:54:41.202539 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
949 02:54:41.296960 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
950 02:54:41.486088 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
951 02:54:41.618847
952 02:54:41.621112 Debian GNU/Linux 12 worm-armhf login: root (automatic login)
953 02:54:41.621669
954 02:54:41.932966 Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Sat Nov 9 02:39:56 UTC 2024 armv7l
955 02:54:41.933618
956 02:54:41.938649 The programs included with the Debian GNU/Linux system are free software;
957 02:54:41.941906 the exact distribution terms for each program are described in the
958 02:54:41.947418 individual files in /usr/share/doc/*/copyright.
959 02:54:41.947944
960 02:54:41.953039 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
961 02:54:41.957715 permitted by applicable law.
962 02:54:47.034724 Unable to match end of the kernel message
964 02:54:47.035621 Setting prompt string to ['/ #']
965 02:54:47.035928 end: 2.4.4.1 login-action (duration 00:00:48) [common]
967 02:54:47.036758 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
968 02:54:47.037097 start: 2.4.5 expect-shell-connection (timeout 00:03:09) [common]
969 02:54:47.037325 Setting prompt string to ['/ #']
970 02:54:47.037535 Forcing a shell prompt, looking for ['/ #']
972 02:54:47.088127 / #
973 02:54:47.088591 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
974 02:54:47.088852 Waiting using forced prompt support (timeout 00:02:30)
975 02:54:47.093444
976 02:54:47.098350 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
977 02:54:47.098704 start: 2.4.6 export-device-env (timeout 00:03:09) [common]
978 02:54:47.098974 Sending with 10 millisecond of delay
980 02:54:52.088921 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/964515/extract-nfsrootfs-h9pj447g'
981 02:54:52.100201 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/964515/extract-nfsrootfs-h9pj447g'
982 02:54:52.101042 Sending with 10 millisecond of delay
984 02:54:54.199777 / # export NFS_SERVER_IP='192.168.6.3'
985 02:54:54.210654 export NFS_SERVER_IP='192.168.6.3'
986 02:54:54.211921 end: 2.4.6 export-device-env (duration 00:00:07) [common]
987 02:54:54.212525 end: 2.4 uboot-commands (duration 00:01:58) [common]
988 02:54:54.213125 end: 2 uboot-action (duration 00:01:58) [common]
989 02:54:54.213683 start: 3 lava-test-retry (timeout 00:06:48) [common]
990 02:54:54.214311 start: 3.1 lava-test-shell (timeout 00:06:48) [common]
991 02:54:54.214777 Using namespace: common
993 02:54:54.315936 / # #
994 02:54:54.316616 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
995 02:54:54.320385 #
996 02:54:54.327040 Using /lava-964515
998 02:54:54.428223 / # export SHELL=/bin/bash
999 02:54:54.433749 export SHELL=/bin/bash
1001 02:54:54.540330 / # . /lava-964515/environment
1002 02:54:54.545839 . /lava-964515/environment
1004 02:54:54.658203 / # /lava-964515/bin/lava-test-runner /lava-964515/0
1005 02:54:54.659109 Test shell timeout: 10s (minimum of the action and connection timeout)
1006 02:54:54.663668 /lava-964515/bin/lava-test-runner /lava-964515/0
1007 02:54:55.079923 + export TESTRUN_ID=0_timesync-off
1008 02:54:55.088015 + TESTRUN_ID=0_timesync-off
1009 02:54:55.088650 + cd /lava-964515/0/tests/0_timesync-off
1010 02:54:55.089121 ++ cat uuid
1011 02:54:55.133378 + UUID=964515_1.6.2.4.1
1012 02:54:55.134065 + set +x
1013 02:54:55.140938 <LAVA_SIGNAL_STARTRUN 0_timesync-off 964515_1.6.2.4.1>
1014 02:54:55.141545 + systemctl stop systemd-timesyncd
1015 02:54:55.142318 Received signal: <STARTRUN> 0_timesync-off 964515_1.6.2.4.1
1016 02:54:55.142801 Starting test lava.0_timesync-off (964515_1.6.2.4.1)
1017 02:54:55.143402 Skipping test definition patterns.
1018 02:54:55.435979 + set +x
1019 02:54:55.436586 <LAVA_SIGNAL_ENDRUN 0_timesync-off 964515_1.6.2.4.1>
1020 02:54:55.437282 Received signal: <ENDRUN> 0_timesync-off 964515_1.6.2.4.1
1021 02:54:55.437786 Ending use of test pattern.
1022 02:54:55.438260 Ending test lava.0_timesync-off (964515_1.6.2.4.1), duration 0.30
1024 02:54:55.608719 + export TESTRUN_ID=1_kselftest-dt
1025 02:54:55.616671 + TESTRUN_ID=1_kselftest-dt
1026 02:54:55.617188 + cd /lava-964515/0/tests/1_kselftest-dt
1027 02:54:55.617638 ++ cat uuid
1028 02:54:55.632125 + UUID=964515_1.6.2.4.5
1029 02:54:55.632615 + set +x
1030 02:54:55.637719 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 964515_1.6.2.4.5>
1031 02:54:55.638222 + cd ./automated/linux/kselftest/
1032 02:54:55.638892 Received signal: <STARTRUN> 1_kselftest-dt 964515_1.6.2.4.5
1033 02:54:55.639318 Starting test lava.1_kselftest-dt (964515_1.6.2.4.5)
1034 02:54:55.639803 Skipping test definition patterns.
1035 02:54:55.667742 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1036 02:54:55.775869 INFO: install_deps skipped
1037 02:54:56.429874 --2024-11-09 02:54:56-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1038 02:54:56.462860 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1039 02:54:56.604865 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1040 02:54:56.744918 HTTP request sent, awaiting response... 200 OK
1041 02:54:56.745509 Length: 4099964 (3.9M) [application/octet-stream]
1042 02:54:56.750413 Saving to: 'kselftest_armhf.tar.gz'
1043 02:54:56.750869
1044 02:54:58.485868
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 181KB/s
kselftest_armhf.tar 5%[> ] 218.67K 395KB/s
kselftest_armhf.tar 17%[==> ] 718.85K 930KB/s
kselftest_armhf.tar 21%[===> ] 846.29K 870KB/s
kselftest_armhf.tar 56%[==========> ] 2.21M 1.88MB/s
kselftest_armhf.tar 73%[=============> ] 2.87M 2.09MB/s
kselftest_armhf.tar 88%[================> ] 3.47M 2.18MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.25MB/s in 1.7s
1045 02:54:58.486594
1046 02:54:59.209742 2024-11-09 02:54:58 (2.25 MB/s) - 'kselftest_armhf.tar.gz' saved [4099964/4099964]
1047 02:54:59.210458
1048 02:55:13.939348 skiplist:
1049 02:55:13.939998 ========================================
1050 02:55:13.943960 ========================================
1051 02:55:14.048683 dt:test_unprobed_devices.sh
1052 02:55:14.084709 ============== Tests to run ===============
1053 02:55:14.092807 dt:test_unprobed_devices.sh
1054 02:55:14.096732 ===========End Tests to run ===============
1055 02:55:14.107140 shardfile-dt pass
1056 02:55:14.344490 <12>[ 75.013346] kselftest: Running tests in dt
1057 02:55:14.371564 TAP version 13
1058 02:55:14.395264 1..1
1059 02:55:14.448773 # timeout set to 45
1060 02:55:14.449124 # selftests: dt: test_unprobed_devices.sh
1061 02:55:15.218405 # TAP version 13
1062 02:55:40.069001 # 1..257
1063 02:55:40.242729 # ok 1 / # SKIP
1064 02:55:40.266434 # ok 2 /clk_mcasp0
1065 02:55:40.338110 # ok 3 /clk_mcasp0_fixed # SKIP
1066 02:55:40.410413 # ok 4 /cpus/cpu@0 # SKIP
1067 02:55:40.482061 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1068 02:55:40.506569 # ok 6 /fixedregulator0
1069 02:55:40.522702 # ok 7 /leds
1070 02:55:40.548035 # ok 8 /ocp
1071 02:55:40.566873 # ok 9 /ocp/interconnect@44c00000
1072 02:55:40.590565 # ok 10 /ocp/interconnect@44c00000/segment@0
1073 02:55:40.618148 # ok 11 /ocp/interconnect@44c00000/segment@100000
1074 02:55:40.638364 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1075 02:55:40.712440 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1076 02:55:40.732238 # ok 14 /ocp/interconnect@44c00000/segment@200000
1077 02:55:40.753133 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1078 02:55:40.858289 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1079 02:55:40.930176 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1080 02:55:41.002068 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1081 02:55:41.072993 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1082 02:55:41.150938 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1083 02:55:41.222659 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1084 02:55:41.290674 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1085 02:55:41.362093 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1086 02:55:41.433104 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1087 02:55:41.505191 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1088 02:55:41.579760 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1089 02:55:41.648096 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1090 02:55:41.723651 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1091 02:55:41.794879 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1092 02:55:41.865230 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1093 02:55:41.936225 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1094 02:55:42.002175 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1095 02:55:42.073946 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1096 02:55:42.144123 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1097 02:55:42.218398 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1098 02:55:42.287949 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1099 02:55:42.359736 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1100 02:55:42.431791 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1101 02:55:42.503281 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1102 02:55:42.574556 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1103 02:55:42.645332 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1104 02:55:42.715935 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1105 02:55:42.790761 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1106 02:55:42.858785 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1107 02:55:42.929923 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1108 02:55:43.000364 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1109 02:55:43.071448 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1110 02:55:43.142113 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1111 02:55:43.213404 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1112 02:55:43.283683 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1113 02:55:43.355140 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1114 02:55:43.428349 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1115 02:55:43.500315 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1116 02:55:43.576196 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1117 02:55:43.647246 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1118 02:55:43.714989 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1119 02:55:43.786301 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1120 02:55:43.857331 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1121 02:55:43.929925 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1122 02:55:44.001669 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1123 02:55:44.073639 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1124 02:55:44.145249 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1125 02:55:44.218817 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1126 02:55:44.288359 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1127 02:55:44.359199 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1128 02:55:44.431349 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1129 02:55:44.503690 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1130 02:55:44.574132 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1131 02:55:44.645977 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1132 02:55:44.719049 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1133 02:55:44.793531 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1134 02:55:44.866276 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1135 02:55:44.941318 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1136 02:55:45.008415 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1137 02:55:45.081277 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1138 02:55:45.153121 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1139 02:55:45.224655 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1140 02:55:45.295753 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1141 02:55:45.370955 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1142 02:55:45.439924 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1143 02:55:45.511777 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1144 02:55:45.583755 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1145 02:55:45.654566 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1146 02:55:45.733391 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1147 02:55:45.799370 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1148 02:55:45.871013 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1149 02:55:45.942195 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1150 02:55:46.013070 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1151 02:55:46.088381 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1152 02:55:46.159589 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1153 02:55:46.235834 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1154 02:55:46.304699 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1155 02:55:46.375819 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1156 02:55:46.450688 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1157 02:55:46.468128 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1158 02:55:46.492386 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1159 02:55:46.521021 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1160 02:55:46.544736 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1161 02:55:46.564751 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1162 02:55:46.592086 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1163 02:55:46.614777 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1164 02:55:46.636250 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1165 02:55:46.737553 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1166 02:55:46.762940 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1167 02:55:46.787463 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1168 02:55:46.811305 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1169 02:55:46.917866 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1170 02:55:46.989455 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1171 02:55:47.062046 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1172 02:55:47.133980 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1173 02:55:47.207152 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1174 02:55:47.283431 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1175 02:55:47.351286 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1176 02:55:47.422792 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1177 02:55:47.494605 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1178 02:55:47.567472 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1179 02:55:47.645372 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1180 02:55:47.711840 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1181 02:55:47.781670 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1182 02:55:47.854376 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1183 02:55:47.927226 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1184 02:55:48.002846 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1185 02:55:48.021611 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1186 02:55:48.091569 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1187 02:55:48.160807 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1188 02:55:48.233038 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1189 02:55:48.255356 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1190 02:55:48.327092 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1191 02:55:48.353267 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1192 02:55:48.423710 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1193 02:55:48.443752 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1194 02:55:48.470620 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1195 02:55:48.493171 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1196 02:55:48.513402 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1197 02:55:48.535938 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1198 02:55:48.564033 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1199 02:55:48.586091 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1200 02:55:48.663178 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1201 02:55:48.684368 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1202 02:55:48.704721 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1203 02:55:48.774680 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1204 02:55:48.845195 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1205 02:55:48.866512 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1206 02:55:48.965471 # not ok 144 /ocp/interconnect@47c00000
1207 02:55:49.040868 # not ok 145 /ocp/interconnect@47c00000/segment@0
1208 02:55:49.060613 # ok 146 /ocp/interconnect@48000000
1209 02:55:49.080569 # ok 147 /ocp/interconnect@48000000/segment@0
1210 02:55:49.105668 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1211 02:55:49.128399 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1212 02:55:49.151492 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1213 02:55:49.179511 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1214 02:55:49.202458 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1215 02:55:49.224106 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1216 02:55:49.249445 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1217 02:55:49.321763 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1218 02:55:49.394615 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1219 02:55:49.413357 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1220 02:55:49.436037 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1221 02:55:49.462386 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1222 02:55:49.484041 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1223 02:55:49.509163 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1224 02:55:49.533435 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1225 02:55:49.553451 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1226 02:55:49.575215 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1227 02:55:49.602370 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1228 02:55:49.623293 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1229 02:55:49.644739 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1230 02:55:49.668645 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1231 02:55:49.692648 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1232 02:55:49.719927 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1233 02:55:49.741615 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1234 02:55:49.764257 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1235 02:55:49.784308 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1236 02:55:49.809885 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1237 02:55:49.831302 # ok 175 /ocp/interconnect@48000000/segment@100000
1238 02:55:49.854830 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1239 02:55:49.879813 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1240 02:55:49.955991 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1241 02:55:50.024598 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1242 02:55:50.094783 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1243 02:55:50.168456 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1244 02:55:50.237908 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1245 02:55:50.311732 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1246 02:55:50.381405 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1247 02:55:50.454005 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1248 02:55:50.476245 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1249 02:55:50.495589 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1250 02:55:50.519531 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1251 02:55:50.550447 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1252 02:55:50.567386 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1253 02:55:50.592098 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1254 02:55:50.619666 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1255 02:55:50.642917 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1256 02:55:50.661312 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1257 02:55:50.688650 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1258 02:55:50.712829 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1259 02:55:50.733508 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1260 02:55:50.753644 # ok 198 /ocp/interconnect@48000000/segment@200000
1261 02:55:50.782214 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1262 02:55:50.854600 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1263 02:55:50.874744 # ok 201 /ocp/interconnect@48000000/segment@300000
1264 02:55:50.899525 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1265 02:55:50.923737 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1266 02:55:50.950352 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1267 02:55:50.967241 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1268 02:55:50.990246 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1269 02:55:51.016866 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1270 02:55:51.082946 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1271 02:55:51.103140 # ok 209 /ocp/interconnect@4a000000
1272 02:55:51.126259 # ok 210 /ocp/interconnect@4a000000/segment@0
1273 02:55:51.153224 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1274 02:55:51.179439 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1275 02:55:51.204888 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1276 02:55:51.225969 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1277 02:55:51.297305 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1278 02:55:51.402448 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1279 02:55:51.474185 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1280 02:55:51.581011 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1281 02:55:51.646160 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1282 02:55:51.719848 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1283 02:55:51.814755 # not ok 221 /ocp/interconnect@4b140000
1284 02:55:51.889936 # not ok 222 /ocp/interconnect@4b140000/segment@0
1285 02:55:51.961043 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1286 02:55:51.977598 # ok 224 /ocp/target-module@40300000
1287 02:55:52.001357 # ok 225 /ocp/target-module@40300000/sram@0
1288 02:55:52.073519 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1289 02:55:52.144351 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1290 02:55:52.168051 # ok 228 /ocp/target-module@47400000
1291 02:55:52.192414 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1292 02:55:52.210135 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1293 02:55:52.232593 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1294 02:55:52.259276 # ok 232 /ocp/target-module@47400000/usb@1400
1295 02:55:52.281624 # ok 233 /ocp/target-module@47400000/usb@1800
1296 02:55:52.299208 # ok 234 /ocp/target-module@47810000
1297 02:55:52.325898 # ok 235 /ocp/target-module@49000000
1298 02:55:52.345604 # ok 236 /ocp/target-module@49000000/dma@0
1299 02:55:52.370919 # ok 237 /ocp/target-module@49800000
1300 02:55:52.398109 # ok 238 /ocp/target-module@49800000/dma@0
1301 02:55:52.413516 # ok 239 /ocp/target-module@49900000
1302 02:55:52.436080 # ok 240 /ocp/target-module@49900000/dma@0
1303 02:55:52.460713 # ok 241 /ocp/target-module@49a00000
1304 02:55:52.485335 # ok 242 /ocp/target-module@49a00000/dma@0
1305 02:55:52.502550 # ok 243 /ocp/target-module@4c000000
1306 02:55:52.577730 # not ok 244 /ocp/target-module@4c000000/emif@0
1307 02:55:52.598477 # ok 245 /ocp/target-module@50000000
1308 02:55:52.617119 # ok 246 /ocp/target-module@53100000
1309 02:55:52.691092 # not ok 247 /ocp/target-module@53100000/sham@0
1310 02:55:52.708993 # ok 248 /ocp/target-module@53500000
1311 02:55:52.781227 # not ok 249 /ocp/target-module@53500000/aes@0
1312 02:55:52.807253 # ok 250 /ocp/target-module@56000000
1313 02:55:52.909840 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1314 02:55:52.973157 # ok 252 /opp-table # SKIP
1315 02:55:53.046301 # ok 253 /soc # SKIP
1316 02:55:53.063536 # ok 254 /sound
1317 02:55:53.090499 # ok 255 /target-module@4b000000
1318 02:55:53.110411 # ok 256 /target-module@4b000000/target-module@140000
1319 02:55:53.132349 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1320 02:55:53.140707 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1321 02:55:53.150062 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1322 02:55:55.334778 dt_test_unprobed_devices_sh_ skip
1323 02:55:55.340372 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1324 02:55:55.345952 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1325 02:55:55.346476 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1326 02:55:55.351547 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1327 02:55:55.357144 dt_test_unprobed_devices_sh_fixedregulator0 pass
1328 02:55:55.362771 dt_test_unprobed_devices_sh_leds pass
1329 02:55:55.363279 dt_test_unprobed_devices_sh_ocp pass
1330 02:55:55.368382 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1331 02:55:55.373963 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1332 02:55:55.379562 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1333 02:55:55.390835 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1334 02:55:55.396429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1335 02:55:55.402046 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1336 02:55:55.413179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1337 02:55:55.418868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1338 02:55:55.430052 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1339 02:55:55.441220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1340 02:55:55.452429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1341 02:55:55.458121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1342 02:55:55.469215 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1343 02:55:55.480480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1344 02:55:55.491747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1345 02:55:55.503002 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1346 02:55:55.508448 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1347 02:55:55.519726 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1348 02:55:55.530854 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1349 02:55:55.542024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1350 02:55:55.553235 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1351 02:55:55.558857 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1352 02:55:55.570108 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1353 02:55:55.581369 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1354 02:55:55.592563 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1355 02:55:55.598159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1356 02:55:55.609408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1357 02:55:55.620586 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1358 02:55:55.631804 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1359 02:55:55.643006 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1360 02:55:55.648664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1361 02:55:55.659918 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1362 02:55:55.671105 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1363 02:55:55.682322 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1364 02:55:55.693528 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1365 02:55:55.704714 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1366 02:55:55.715881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1367 02:55:55.727037 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1368 02:55:55.738304 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1369 02:55:55.749442 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1370 02:55:55.760624 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1371 02:55:55.771818 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1372 02:55:55.783013 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1373 02:55:55.794201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1374 02:55:55.805364 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1375 02:55:55.816639 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1376 02:55:55.827856 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1377 02:55:55.838985 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1378 02:55:55.850171 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1379 02:55:55.861342 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1380 02:55:55.872550 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1381 02:55:55.883771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1382 02:55:55.895035 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1383 02:55:55.906143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1384 02:55:55.917339 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1385 02:55:55.928524 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1386 02:55:55.934113 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1387 02:55:55.945306 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1388 02:55:55.956493 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1389 02:55:55.967703 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1390 02:55:55.979133 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1391 02:55:55.990141 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1392 02:55:56.001291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1393 02:55:56.012433 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1394 02:55:56.023713 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1395 02:55:56.034944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1396 02:55:56.046188 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1397 02:55:56.057396 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1398 02:55:56.068455 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1399 02:55:56.079647 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1400 02:55:56.090920 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1401 02:55:56.102041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1402 02:55:56.113210 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1403 02:55:56.124452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1404 02:55:56.130072 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1405 02:55:56.141248 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1406 02:55:56.152367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1407 02:55:56.163580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1408 02:55:56.174878 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1409 02:55:56.180396 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1410 02:55:56.197258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1411 02:55:56.208518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1412 02:55:56.214146 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1413 02:55:56.231003 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1414 02:55:56.242190 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1415 02:55:56.253365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1416 02:55:56.258938 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1417 02:55:56.270140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1418 02:55:56.281327 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1419 02:55:56.286961 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1420 02:55:56.298377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1421 02:55:56.309388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1422 02:55:56.315030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1423 02:55:56.326149 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1424 02:55:56.331739 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1425 02:55:56.342947 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1426 02:55:56.354242 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1427 02:55:56.365348 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1428 02:55:56.376696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1429 02:55:56.387833 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1430 02:55:56.398967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1431 02:55:56.410252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1432 02:55:56.421324 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1433 02:55:56.432506 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1434 02:55:56.443637 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1435 02:55:56.455378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1436 02:55:56.466228 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1437 02:55:56.482927 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1438 02:55:56.494041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1439 02:55:56.505276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1440 02:55:56.516472 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1441 02:55:56.527668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1442 02:55:56.544501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1443 02:55:56.555736 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1444 02:55:56.566906 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1445 02:55:56.578026 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1446 02:55:56.583568 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1447 02:55:56.594768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1448 02:55:56.606047 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1449 02:55:56.611560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1450 02:55:56.622822 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1451 02:55:56.628362 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1452 02:55:56.639560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1453 02:55:56.645211 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1454 02:55:56.656349 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1455 02:55:56.662007 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1456 02:55:56.673181 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1457 02:55:56.678763 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1458 02:55:56.690068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1459 02:55:56.701279 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1460 02:55:56.712486 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1461 02:55:56.723653 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1462 02:55:56.734827 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1463 02:55:56.740436 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1464 02:55:56.751644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1465 02:55:56.757236 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1466 02:55:56.762964 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1467 02:55:56.768391 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1468 02:55:56.774049 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1469 02:55:56.779614 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1470 02:55:56.790765 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1471 02:55:56.796342 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1472 02:55:56.802072 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1473 02:55:56.813146 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1474 02:55:56.818773 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1475 02:55:56.830017 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1476 02:55:56.835541 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1477 02:55:56.846729 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1478 02:55:56.852362 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1479 02:55:56.863545 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1480 02:55:56.869124 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1481 02:55:56.880339 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1482 02:55:56.885992 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1483 02:55:56.897078 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1484 02:55:56.902668 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1485 02:55:56.913984 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1486 02:55:56.919489 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1487 02:55:56.925106 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1488 02:55:56.936334 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1489 02:55:56.942091 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1490 02:55:56.953082 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1491 02:55:56.958624 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1492 02:55:56.969836 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1493 02:55:56.975440 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1494 02:55:56.986588 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1495 02:55:56.992196 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1496 02:55:56.997852 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1497 02:55:57.009011 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1498 02:55:57.014649 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1499 02:55:57.025906 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1500 02:55:57.037064 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1501 02:55:57.048170 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1502 02:55:57.059405 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1503 02:55:57.070510 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1504 02:55:57.081767 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1505 02:55:57.093048 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1506 02:55:57.104192 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1507 02:55:57.109780 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1508 02:55:57.120933 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1509 02:55:57.126492 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1510 02:55:57.137738 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1511 02:55:57.143346 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1512 02:55:57.154576 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1513 02:55:57.160143 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1514 02:55:57.171318 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1515 02:55:57.176932 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1516 02:55:57.188158 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1517 02:55:57.193668 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1518 02:55:57.204837 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1519 02:55:57.210467 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1520 02:55:57.221616 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1521 02:55:57.227210 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1522 02:55:57.232832 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1523 02:55:57.243977 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1524 02:55:57.249709 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1525 02:55:57.260905 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1526 02:55:57.266411 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1527 02:55:57.277644 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1528 02:55:57.283225 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1529 02:55:57.294420 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1530 02:55:57.300054 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1531 02:55:57.305614 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1532 02:55:57.311266 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1533 02:55:57.322360 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1534 02:55:57.333605 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1535 02:55:57.339131 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1536 02:55:57.344791 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1537 02:55:57.356083 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1538 02:55:57.367231 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1539 02:55:57.378443 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1540 02:55:57.389664 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1541 02:55:57.395303 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1542 02:55:57.400910 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1543 02:55:57.406504 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1544 02:55:57.412126 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1545 02:55:57.417725 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1546 02:55:57.423295 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1547 02:55:57.434504 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1548 02:55:57.440145 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1549 02:55:57.445749 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1550 02:55:57.451342 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1551 02:55:57.456962 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1552 02:55:57.468113 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1553 02:55:57.473752 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1554 02:55:57.479384 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1555 02:55:57.485085 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1556 02:55:57.490631 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1557 02:55:57.496260 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1558 02:55:57.502017 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1559 02:55:57.507540 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1560 02:55:57.513239 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1561 02:55:57.518756 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1562 02:55:57.524316 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1563 02:55:57.529967 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1564 02:55:57.535574 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1565 02:55:57.541172 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1566 02:55:57.546750 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1567 02:55:57.552366 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1568 02:55:57.557954 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1569 02:55:57.563547 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1570 02:55:57.569230 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1571 02:55:57.574814 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1572 02:55:57.580387 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1573 02:55:57.580933 dt_test_unprobed_devices_sh_opp-table skip
1574 02:55:57.586014 dt_test_unprobed_devices_sh_soc skip
1575 02:55:57.591590 dt_test_unprobed_devices_sh_sound pass
1576 02:55:57.597216 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1577 02:55:57.602769 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1578 02:55:57.608372 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1579 02:55:57.614043 dt_test_unprobed_devices_sh fail
1580 02:55:57.614595 + ../../utils/send-to-lava.sh ./output/result.txt
1581 02:55:57.619599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1582 02:55:57.620581 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1584 02:55:57.628683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1585 02:55:57.629496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1587 02:55:57.710749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1588 02:55:57.711711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1590 02:55:57.802412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1591 02:55:57.803288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1593 02:55:57.892230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1594 02:55:57.893103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1596 02:55:57.985665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1597 02:55:57.986536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1599 02:55:58.076014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1600 02:55:58.076902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1602 02:55:58.166245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1603 02:55:58.167101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1605 02:55:58.256947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1606 02:55:58.257770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1608 02:55:58.350628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1609 02:55:58.351558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1611 02:55:58.440784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1612 02:55:58.441657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1614 02:55:58.527069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1615 02:55:58.527708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1617 02:55:58.619773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1618 02:55:58.620365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1620 02:55:58.711099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1621 02:55:58.711687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1623 02:55:58.801486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1624 02:55:58.802352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1626 02:55:58.893650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1627 02:55:58.894505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1629 02:55:58.988155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1630 02:55:58.988956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1632 02:55:59.082707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1633 02:55:59.083552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1635 02:55:59.174306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1636 02:55:59.175297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1638 02:55:59.265943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1639 02:55:59.266514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1641 02:55:59.358368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1642 02:55:59.359460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1644 02:55:59.452175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1645 02:55:59.453269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1647 02:55:59.544577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1648 02:55:59.545692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1650 02:55:59.636026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1651 02:55:59.637335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1653 02:55:59.728759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1654 02:55:59.729859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1656 02:55:59.821717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1657 02:55:59.822812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1659 02:55:59.913902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1660 02:55:59.915007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1662 02:56:00.005115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1663 02:56:00.006276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1665 02:56:00.100154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1666 02:56:00.101243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1668 02:56:00.192981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1669 02:56:00.194077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1671 02:56:00.292816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1672 02:56:00.294011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1674 02:56:00.395028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1675 02:56:00.396042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1677 02:56:00.494649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1678 02:56:00.495305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1680 02:56:00.590037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1681 02:56:00.590775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1683 02:56:00.679926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1684 02:56:00.680657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1686 02:56:00.774499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1687 02:56:00.775420 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1689 02:56:00.863675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1690 02:56:00.864586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1692 02:56:00.967452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1693 02:56:00.968373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1695 02:56:01.069301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1696 02:56:01.070258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1698 02:56:01.161374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1699 02:56:01.162306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1701 02:56:01.486831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1702 02:56:01.488504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1703 02:56:01.489550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1705 02:56:01.491353 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1707 02:56:01.492882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1708 02:56:01.493671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1710 02:56:01.542748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1711 02:56:01.543690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1713 02:56:01.637350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1714 02:56:01.638010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1716 02:56:01.730915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1717 02:56:01.731573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1719 02:56:01.823694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1720 02:56:01.824377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1722 02:56:01.917994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1723 02:56:01.918695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1725 02:56:02.018920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1726 02:56:02.019597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1728 02:56:02.114425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1729 02:56:02.115097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1731 02:56:02.205096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1732 02:56:02.205733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1734 02:56:02.295922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1735 02:56:02.296577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1737 02:56:02.387437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1738 02:56:02.388070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1740 02:56:02.479642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1741 02:56:02.480338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1743 02:56:02.692220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1744 02:56:02.692897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1746 02:56:02.794585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1747 02:56:02.795309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1749 02:56:02.887955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1750 02:56:02.888673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1752 02:56:02.982790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1753 02:56:02.983731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1755 02:56:03.073193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1756 02:56:03.074139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1758 02:56:03.163335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1759 02:56:03.163940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1761 02:56:03.256150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1762 02:56:03.256799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1764 02:56:03.347170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1765 02:56:03.348111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1767 02:56:03.439729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1768 02:56:03.440652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1770 02:56:03.535275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1771 02:56:03.535993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1773 02:56:03.626064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1774 02:56:03.627013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1776 02:56:03.715958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1777 02:56:03.716864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1779 02:56:03.808557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1780 02:56:03.809495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1782 02:56:03.901280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1783 02:56:03.902274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1785 02:56:03.993720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1786 02:56:03.994719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1788 02:56:04.085365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1789 02:56:04.086326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1791 02:56:04.178137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1792 02:56:04.179047 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1794 02:56:04.269406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1795 02:56:04.270328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1797 02:56:04.364085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1798 02:56:04.364720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1800 02:56:04.456527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1801 02:56:04.457435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1803 02:56:04.548302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1804 02:56:04.549216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1806 02:56:04.641478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1807 02:56:04.642348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1809 02:56:04.733404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1810 02:56:04.734351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1812 02:56:04.826084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1813 02:56:04.826983 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1815 02:56:05.102098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1816 02:56:05.103020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1818 02:56:05.104416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1819 02:56:05.105149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1821 02:56:05.106585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1822 02:56:05.107318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1824 02:56:05.195571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1825 02:56:05.196475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1827 02:56:05.282415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1828 02:56:05.283515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1830 02:56:05.374084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1831 02:56:05.375160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1833 02:56:05.466068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1834 02:56:05.466722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1836 02:56:05.557918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1837 02:56:05.558839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1839 02:56:05.650222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1840 02:56:05.651144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1842 02:56:05.745014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1843 02:56:05.745916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1845 02:56:05.837405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1846 02:56:05.838558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1848 02:56:05.940398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1849 02:56:05.941460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1851 02:56:06.036168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1852 02:56:06.037071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1854 02:56:06.134789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1855 02:56:06.135741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1857 02:56:06.229842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1858 02:56:06.230548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1860 02:56:06.325295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1861 02:56:06.326170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1863 02:56:06.419068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1864 02:56:06.419705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1866 02:56:06.508442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1867 02:56:06.509306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1869 02:56:06.599121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1870 02:56:06.599941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1872 02:56:06.690353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1873 02:56:06.690993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1875 02:56:06.782303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1876 02:56:06.783161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1878 02:56:06.876266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1879 02:56:06.877096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1881 02:56:06.968221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1882 02:56:06.968965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1884 02:56:07.060755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1885 02:56:07.061557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1887 02:56:07.151730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1888 02:56:07.152538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1890 02:56:07.243799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1891 02:56:07.244718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1893 02:56:07.345963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1894 02:56:07.346924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1896 02:56:07.439304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1897 02:56:07.440389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1899 02:56:07.531953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1900 02:56:07.532928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1902 02:56:07.656542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1903 02:56:07.657479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1905 02:56:07.753681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1906 02:56:07.754815 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1908 02:56:07.854084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1909 02:56:07.855165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1911 02:56:07.946947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1912 02:56:07.947979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1914 02:56:08.040899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1915 02:56:08.041848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1917 02:56:08.133318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1918 02:56:08.134228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1920 02:56:08.229426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1921 02:56:08.230391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1923 02:56:08.323999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1924 02:56:08.325085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1926 02:56:08.416566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1927 02:56:08.417464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1929 02:56:08.509616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1930 02:56:08.510733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1932 02:56:08.602514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1933 02:56:08.603415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1935 02:56:08.694579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1936 02:56:08.695452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1938 02:56:08.785350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1939 02:56:08.786244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1941 02:56:08.874010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1943 02:56:08.877247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1944 02:56:08.965451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1946 02:56:08.968542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1947 02:56:09.058430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1949 02:56:09.061477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1950 02:56:09.152282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1951 02:56:09.152959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1953 02:56:09.246082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1954 02:56:09.247045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1956 02:56:09.336487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1957 02:56:09.337979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1959 02:56:09.429970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1960 02:56:09.430850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1962 02:56:09.522050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1963 02:56:09.522946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1965 02:56:09.613643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1966 02:56:09.614586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1968 02:56:09.705751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1969 02:56:09.706676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1971 02:56:09.800345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1972 02:56:09.801239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1974 02:56:09.891714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1975 02:56:09.892647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1977 02:56:09.984997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1978 02:56:09.985918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1980 02:56:10.077149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1981 02:56:10.078179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1983 02:56:10.171479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1984 02:56:10.172409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1986 02:56:10.263166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1987 02:56:10.264002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1989 02:56:10.355692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1990 02:56:10.356653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1992 02:56:10.451764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1993 02:56:10.452708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1995 02:56:10.545440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1996 02:56:10.546294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
1998 02:56:10.635606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1999 02:56:10.636539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2001 02:56:10.729337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2002 02:56:10.730343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2004 02:56:10.825960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2005 02:56:10.826984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2007 02:56:10.919690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2008 02:56:10.920586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2010 02:56:11.008346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2011 02:56:11.009305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2013 02:56:11.096736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2014 02:56:11.097599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2016 02:56:11.188242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2017 02:56:11.189098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2019 02:56:11.278774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2020 02:56:11.279634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2022 02:56:11.369907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2023 02:56:11.370831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2025 02:56:11.457885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2026 02:56:11.458788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2028 02:56:11.549761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2029 02:56:11.551355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2031 02:56:11.641123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2032 02:56:11.641758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2034 02:56:11.731943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2035 02:56:11.732547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2037 02:56:11.823132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2038 02:56:11.823929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2040 02:56:11.915766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2041 02:56:11.916682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2043 02:56:12.006692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2044 02:56:12.007372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2046 02:56:12.099978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2047 02:56:12.100875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2049 02:56:12.194370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2050 02:56:12.195265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2052 02:56:12.284990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2053 02:56:12.285615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2055 02:56:12.382652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2056 02:56:12.383309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2058 02:56:12.491346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2059 02:56:12.492022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2061 02:56:12.605892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2062 02:56:12.606535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2064 02:56:12.699590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2065 02:56:12.700240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2067 02:56:12.791880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2068 02:56:12.792529 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2070 02:56:12.885293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2071 02:56:12.885909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2073 02:56:12.982613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2074 02:56:12.983236 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2076 02:56:13.074820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2077 02:56:13.075442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2079 02:56:13.168294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2080 02:56:13.168918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2082 02:56:13.259356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2083 02:56:13.259975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2085 02:56:13.351431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2086 02:56:13.352072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2088 02:56:13.445343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2089 02:56:13.446326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2091 02:56:13.539202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2092 02:56:13.540131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2094 02:56:13.630109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2095 02:56:13.631044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2097 02:56:13.723602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2098 02:56:13.724484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2100 02:56:13.814054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2101 02:56:13.814941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2103 02:56:13.907417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2104 02:56:13.908289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2106 02:56:13.998291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2107 02:56:13.999190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2109 02:56:14.092202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2110 02:56:14.093071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2112 02:56:14.185168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2113 02:56:14.186063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2115 02:56:14.279160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2116 02:56:14.280040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2118 02:56:14.373698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2119 02:56:14.374667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2121 02:56:14.465191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2122 02:56:14.466053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2124 02:56:14.559347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2125 02:56:14.560196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2127 02:56:14.649754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2128 02:56:14.650625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2130 02:56:14.742283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2131 02:56:14.743147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2133 02:56:14.832672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2134 02:56:14.833543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2136 02:56:14.924585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2137 02:56:14.925423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2139 02:56:15.011949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2140 02:56:15.012813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2142 02:56:15.101557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2143 02:56:15.102547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2145 02:56:15.186740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2146 02:56:15.187650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2148 02:56:15.279530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2149 02:56:15.280402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2151 02:56:15.371429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2152 02:56:15.372301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2154 02:56:15.463265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2155 02:56:15.464199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2157 02:56:15.554815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2158 02:56:15.555694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2160 02:56:15.647506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2161 02:56:15.648338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2163 02:56:15.741181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2164 02:56:15.741940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2166 02:56:15.832326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2167 02:56:15.833115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2169 02:56:15.922585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2170 02:56:15.923344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2172 02:56:16.008717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2173 02:56:16.009476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2175 02:56:16.097793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2176 02:56:16.098661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2178 02:56:16.191080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2179 02:56:16.191882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2181 02:56:16.282993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2182 02:56:16.283754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2184 02:56:16.369978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2185 02:56:16.370716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2187 02:56:16.460929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2188 02:56:16.461758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2190 02:56:16.550842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2191 02:56:16.551669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2193 02:56:16.643099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2194 02:56:16.643825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2196 02:56:16.732285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2197 02:56:16.733017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2199 02:56:16.821647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2200 02:56:16.823572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2202 02:56:16.913764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2203 02:56:16.914356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2205 02:56:17.006640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2206 02:56:17.007390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2208 02:56:17.095176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2209 02:56:17.095996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2211 02:56:17.188136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2212 02:56:17.188986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2214 02:56:17.281897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2215 02:56:17.282686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2217 02:56:17.373515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2218 02:56:17.374381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2220 02:56:17.467988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2221 02:56:17.468928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2223 02:56:17.560274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2224 02:56:17.561139 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2226 02:56:17.651469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2227 02:56:17.652323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2229 02:56:17.743181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2230 02:56:17.744048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2232 02:56:17.834370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2233 02:56:17.835242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2235 02:56:17.920195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2236 02:56:17.920783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2238 02:56:18.013069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2239 02:56:18.013706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2241 02:56:18.104896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2242 02:56:18.105525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2244 02:56:18.192831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2245 02:56:18.193577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2247 02:56:18.295283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2248 02:56:18.295903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2250 02:56:18.389363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2251 02:56:18.389994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2253 02:56:18.480317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2254 02:56:18.480929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2256 02:56:18.574498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2257 02:56:18.575114 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2259 02:56:18.666221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2260 02:56:18.666837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2262 02:56:18.757855 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2264 02:56:18.760892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2265 02:56:18.849628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2266 02:56:18.850551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2268 02:56:18.944999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2269 02:56:18.946235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2271 02:56:19.039116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2272 02:56:19.040273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2274 02:56:19.129425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2275 02:56:19.130544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2277 02:56:19.222045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2278 02:56:19.223075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2280 02:56:19.322670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2281 02:56:19.323683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2283 02:56:19.423145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2284 02:56:19.424377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2286 02:56:19.524160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2287 02:56:19.525223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2289 02:56:19.618638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2290 02:56:19.619581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2292 02:56:19.708372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2293 02:56:19.709466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2295 02:56:19.802178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2296 02:56:19.803138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2298 02:56:19.902288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2299 02:56:19.903196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2301 02:56:19.996326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2302 02:56:19.997226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2304 02:56:20.088445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2305 02:56:20.089540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2307 02:56:20.182855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2308 02:56:20.183968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2310 02:56:20.275270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2311 02:56:20.276432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2313 02:56:20.368300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2314 02:56:20.369355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2316 02:56:20.461166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2317 02:56:20.461784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2319 02:56:20.553041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2320 02:56:20.553733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2322 02:56:20.648532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2323 02:56:20.649172 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2325 02:56:20.740556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2326 02:56:20.741162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2328 02:56:20.834281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2329 02:56:20.834893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2331 02:56:20.926199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2332 02:56:20.927141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2334 02:56:21.019346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2335 02:56:21.020272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2337 02:56:21.110672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2338 02:56:21.111601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2340 02:56:21.203056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2341 02:56:21.203978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2343 02:56:21.297155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2344 02:56:21.298052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2346 02:56:21.389618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2347 02:56:21.391010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2349 02:56:21.483680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2350 02:56:21.484323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2352 02:56:21.576194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2353 02:56:21.576912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2355 02:56:21.663237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2356 02:56:21.663606 + set +x
2357 02:56:21.664025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2359 02:56:21.667544 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 964515_1.6.2.4.5>
2360 02:56:21.668007 Received signal: <ENDRUN> 1_kselftest-dt 964515_1.6.2.4.5
2361 02:56:21.668241 Ending use of test pattern.
2362 02:56:21.668441 Ending test lava.1_kselftest-dt (964515_1.6.2.4.5), duration 86.03
2364 02:56:21.674043 <LAVA_TEST_RUNNER EXIT>
2365 02:56:21.674504 ok: lava_test_shell seems to have completed
2366 02:56:21.686074 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2367 02:56:21.687982 end: 3.1 lava-test-shell (duration 00:01:27) [common]
2368 02:56:21.688622 end: 3 lava-test-retry (duration 00:01:27) [common]
2369 02:56:21.689176 start: 4 finalize (timeout 00:05:21) [common]
2370 02:56:21.689713 start: 4.1 power-off (timeout 00:00:30) [common]
2371 02:56:21.690697 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2372 02:56:21.726252 >> OK - accepted request
2373 02:56:21.728537 Returned 0 in 0 seconds
2374 02:56:21.829626 end: 4.1 power-off (duration 00:00:00) [common]
2376 02:56:21.831291 start: 4.2 read-feedback (timeout 00:05:20) [common]
2377 02:56:21.832405 Listened to connection for namespace 'common' for up to 1s
2378 02:56:21.833232 Listened to connection for namespace 'common' for up to 1s
2379 02:56:22.832563 Finalising connection for namespace 'common'
2380 02:56:22.833302 Disconnecting from shell: Finalise
2381 02:56:22.833877 / #
2382 02:56:22.934988 end: 4.2 read-feedback (duration 00:00:01) [common]
2383 02:56:22.935801 end: 4 finalize (duration 00:00:01) [common]
2384 02:56:22.936490 Cleaning after the job
2385 02:56:22.937166 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964515/tftp-deploy-bvnnvfbu/ramdisk
2386 02:56:22.939812 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964515/tftp-deploy-bvnnvfbu/kernel
2387 02:56:22.947013 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964515/tftp-deploy-bvnnvfbu/dtb
2388 02:56:22.948254 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964515/tftp-deploy-bvnnvfbu/nfsrootfs
2389 02:56:22.996424 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964515/tftp-deploy-bvnnvfbu/modules
2390 02:56:23.000369 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/964515
2391 02:56:26.194966 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/964515
2392 02:56:26.195520 Job finished correctly