Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 03:03:38.790666 lava-dispatcher, installed at version: 2024.01
2 03:03:38.791487 start: 0 validate
3 03:03:38.792007 Start time: 2024-11-09 03:03:38.791957+00:00 (UTC)
4 03:03:38.792564 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:03:38.793106 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 03:03:38.833410 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:03:38.833986 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-247-gbf99f9b489d8e%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 03:03:38.863230 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:03:38.863858 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-247-gbf99f9b489d8e%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 03:03:39.915610 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:03:39.916192 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-247-gbf99f9b489d8e%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 03:03:39.953243 validate duration: 1.16
14 03:03:39.954109 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 03:03:39.954455 start: 1.1 download-retry (timeout 00:10:00) [common]
16 03:03:39.954768 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 03:03:39.955351 Not decompressing ramdisk as can be used compressed.
18 03:03:39.955785 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 03:03:39.956051 saving as /var/lib/lava/dispatcher/tmp/964609/tftp-deploy-x58gtmr_/ramdisk/rootfs.cpio.gz
20 03:03:39.956320 total size: 8181887 (7 MB)
21 03:03:39.998399 progress 0 % (0 MB)
22 03:03:40.005338 progress 5 % (0 MB)
23 03:03:40.015390 progress 10 % (0 MB)
24 03:03:40.025553 progress 15 % (1 MB)
25 03:03:40.031182 progress 20 % (1 MB)
26 03:03:40.037090 progress 25 % (1 MB)
27 03:03:40.042448 progress 30 % (2 MB)
28 03:03:40.048369 progress 35 % (2 MB)
29 03:03:40.053765 progress 40 % (3 MB)
30 03:03:40.059628 progress 45 % (3 MB)
31 03:03:40.065150 progress 50 % (3 MB)
32 03:03:40.071034 progress 55 % (4 MB)
33 03:03:40.076728 progress 60 % (4 MB)
34 03:03:40.082588 progress 65 % (5 MB)
35 03:03:40.088123 progress 70 % (5 MB)
36 03:03:40.093853 progress 75 % (5 MB)
37 03:03:40.099215 progress 80 % (6 MB)
38 03:03:40.105023 progress 85 % (6 MB)
39 03:03:40.110436 progress 90 % (7 MB)
40 03:03:40.116183 progress 95 % (7 MB)
41 03:03:40.121091 progress 100 % (7 MB)
42 03:03:40.121781 7 MB downloaded in 0.17 s (47.17 MB/s)
43 03:03:40.122338 end: 1.1.1 http-download (duration 00:00:00) [common]
45 03:03:40.123225 end: 1.1 download-retry (duration 00:00:00) [common]
46 03:03:40.123516 start: 1.2 download-retry (timeout 00:10:00) [common]
47 03:03:40.123787 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 03:03:40.124351 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm64/defconfig/gcc-12/kernel/Image
49 03:03:40.124642 saving as /var/lib/lava/dispatcher/tmp/964609/tftp-deploy-x58gtmr_/kernel/Image
50 03:03:40.124857 total size: 45713920 (43 MB)
51 03:03:40.125071 No compression specified
52 03:03:40.158970 progress 0 % (0 MB)
53 03:03:40.189705 progress 5 % (2 MB)
54 03:03:40.218949 progress 10 % (4 MB)
55 03:03:40.247731 progress 15 % (6 MB)
56 03:03:40.276443 progress 20 % (8 MB)
57 03:03:40.305138 progress 25 % (10 MB)
58 03:03:40.333562 progress 30 % (13 MB)
59 03:03:40.362681 progress 35 % (15 MB)
60 03:03:40.390892 progress 40 % (17 MB)
61 03:03:40.418887 progress 45 % (19 MB)
62 03:03:40.448067 progress 50 % (21 MB)
63 03:03:40.476345 progress 55 % (24 MB)
64 03:03:40.505139 progress 60 % (26 MB)
65 03:03:40.533125 progress 65 % (28 MB)
66 03:03:40.562200 progress 70 % (30 MB)
67 03:03:40.591217 progress 75 % (32 MB)
68 03:03:40.619829 progress 80 % (34 MB)
69 03:03:40.648656 progress 85 % (37 MB)
70 03:03:40.677655 progress 90 % (39 MB)
71 03:03:40.706496 progress 95 % (41 MB)
72 03:03:40.735117 progress 100 % (43 MB)
73 03:03:40.735669 43 MB downloaded in 0.61 s (71.38 MB/s)
74 03:03:40.736181 end: 1.2.1 http-download (duration 00:00:01) [common]
76 03:03:40.737021 end: 1.2 download-retry (duration 00:00:01) [common]
77 03:03:40.737300 start: 1.3 download-retry (timeout 00:09:59) [common]
78 03:03:40.737567 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 03:03:40.738043 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 03:03:40.738317 saving as /var/lib/lava/dispatcher/tmp/964609/tftp-deploy-x58gtmr_/dtb/meson-g12b-a311d-libretech-cc.dtb
81 03:03:40.738528 total size: 54703 (0 MB)
82 03:03:40.738738 No compression specified
83 03:03:40.775204 progress 59 % (0 MB)
84 03:03:40.776156 progress 100 % (0 MB)
85 03:03:40.776783 0 MB downloaded in 0.04 s (1.36 MB/s)
86 03:03:40.777269 end: 1.3.1 http-download (duration 00:00:00) [common]
88 03:03:40.778089 end: 1.3 download-retry (duration 00:00:00) [common]
89 03:03:40.778355 start: 1.4 download-retry (timeout 00:09:59) [common]
90 03:03:40.778621 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 03:03:40.779070 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm64/defconfig/gcc-12/modules.tar.xz
92 03:03:40.779309 saving as /var/lib/lava/dispatcher/tmp/964609/tftp-deploy-x58gtmr_/modules/modules.tar
93 03:03:40.779516 total size: 11612756 (11 MB)
94 03:03:40.779726 Using unxz to decompress xz
95 03:03:40.813422 progress 0 % (0 MB)
96 03:03:40.880775 progress 5 % (0 MB)
97 03:03:40.956123 progress 10 % (1 MB)
98 03:03:41.053352 progress 15 % (1 MB)
99 03:03:41.145865 progress 20 % (2 MB)
100 03:03:41.227221 progress 25 % (2 MB)
101 03:03:41.303961 progress 30 % (3 MB)
102 03:03:41.383858 progress 35 % (3 MB)
103 03:03:41.457646 progress 40 % (4 MB)
104 03:03:41.534192 progress 45 % (5 MB)
105 03:03:41.619658 progress 50 % (5 MB)
106 03:03:41.698210 progress 55 % (6 MB)
107 03:03:41.784556 progress 60 % (6 MB)
108 03:03:41.867121 progress 65 % (7 MB)
109 03:03:41.949031 progress 70 % (7 MB)
110 03:03:42.027929 progress 75 % (8 MB)
111 03:03:42.116094 progress 80 % (8 MB)
112 03:03:42.197708 progress 85 % (9 MB)
113 03:03:42.278809 progress 90 % (9 MB)
114 03:03:42.377896 progress 95 % (10 MB)
115 03:03:42.473759 progress 100 % (11 MB)
116 03:03:42.488708 11 MB downloaded in 1.71 s (6.48 MB/s)
117 03:03:42.489430 end: 1.4.1 http-download (duration 00:00:02) [common]
119 03:03:42.490469 end: 1.4 download-retry (duration 00:00:02) [common]
120 03:03:42.490832 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 03:03:42.491186 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 03:03:42.491515 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 03:03:42.491847 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 03:03:42.492569 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv
125 03:03:42.493181 makedir: /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin
126 03:03:42.493585 makedir: /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/tests
127 03:03:42.493976 makedir: /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/results
128 03:03:42.494382 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-add-keys
129 03:03:42.495016 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-add-sources
130 03:03:42.495707 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-background-process-start
131 03:03:42.496408 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-background-process-stop
132 03:03:42.497064 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-common-functions
133 03:03:42.497678 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-echo-ipv4
134 03:03:42.498259 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-install-packages
135 03:03:42.499139 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-installed-packages
136 03:03:42.499750 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-os-build
137 03:03:42.500752 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-probe-channel
138 03:03:42.501391 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-probe-ip
139 03:03:42.502022 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-target-ip
140 03:03:42.502617 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-target-mac
141 03:03:42.503195 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-target-storage
142 03:03:42.503811 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-test-case
143 03:03:42.504450 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-test-event
144 03:03:42.505037 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-test-feedback
145 03:03:42.505616 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-test-raise
146 03:03:42.506473 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-test-reference
147 03:03:42.507106 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-test-runner
148 03:03:42.507728 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-test-set
149 03:03:42.508346 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-test-shell
150 03:03:42.508948 Updating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-install-packages (oe)
151 03:03:42.509632 Updating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/bin/lava-installed-packages (oe)
152 03:03:42.510182 Creating /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/environment
153 03:03:42.510653 LAVA metadata
154 03:03:42.510991 - LAVA_JOB_ID=964609
155 03:03:42.511274 - LAVA_DISPATCHER_IP=192.168.6.2
156 03:03:42.511733 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 03:03:42.513092 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 03:03:42.513526 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 03:03:42.513803 skipped lava-vland-overlay
160 03:03:42.514124 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 03:03:42.514475 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 03:03:42.514776 skipped lava-multinode-overlay
163 03:03:42.515109 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 03:03:42.515452 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 03:03:42.515774 Loading test definitions
166 03:03:42.516613 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 03:03:42.516958 Using /lava-964609 at stage 0
168 03:03:42.518395 uuid=964609_1.5.2.4.1 testdef=None
169 03:03:42.518835 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 03:03:42.519203 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 03:03:42.521403 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 03:03:42.522427 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 03:03:42.525281 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 03:03:42.526404 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 03:03:42.529162 runner path: /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/0/tests/0_dmesg test_uuid 964609_1.5.2.4.1
178 03:03:42.530044 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 03:03:42.531005 Creating lava-test-runner.conf files
181 03:03:42.531278 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/964609/lava-overlay-4g_hh6cv/lava-964609/0 for stage 0
182 03:03:42.531906 - 0_dmesg
183 03:03:42.532428 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 03:03:42.532807 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 03:03:42.562580 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 03:03:42.563098 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 03:03:42.563485 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 03:03:42.563849 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 03:03:42.564235 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 03:03:43.710186 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 03:03:43.710780 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 03:03:43.711158 extracting modules file /var/lib/lava/dispatcher/tmp/964609/tftp-deploy-x58gtmr_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964609/extract-overlay-ramdisk-jvasi3rz/ramdisk
193 03:03:45.342844 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 03:03:45.343355 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 03:03:45.343640 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964609/compress-overlay-sh2lv169/overlay-1.5.2.5.tar.gz to ramdisk
196 03:03:45.343858 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964609/compress-overlay-sh2lv169/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/964609/extract-overlay-ramdisk-jvasi3rz/ramdisk
197 03:03:45.377136 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 03:03:45.377599 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 03:03:45.377876 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 03:03:45.378116 Converting downloaded kernel to a uImage
201 03:03:45.378443 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/964609/tftp-deploy-x58gtmr_/kernel/Image /var/lib/lava/dispatcher/tmp/964609/tftp-deploy-x58gtmr_/kernel/uImage
202 03:03:45.845374 output: Image Name:
203 03:03:45.845803 output: Created: Sat Nov 9 03:03:45 2024
204 03:03:45.846037 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 03:03:45.846259 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 03:03:45.846473 output: Load Address: 01080000
207 03:03:45.846684 output: Entry Point: 01080000
208 03:03:45.846892 output:
209 03:03:45.847244 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 03:03:45.847546 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 03:03:45.847842 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 03:03:45.848164 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 03:03:45.848456 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 03:03:45.848733 Building ramdisk /var/lib/lava/dispatcher/tmp/964609/extract-overlay-ramdisk-jvasi3rz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/964609/extract-overlay-ramdisk-jvasi3rz/ramdisk
215 03:03:48.520570 >> 181576 blocks
216 03:03:57.248706 Adding RAMdisk u-boot header.
217 03:03:57.249156 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/964609/extract-overlay-ramdisk-jvasi3rz/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/964609/extract-overlay-ramdisk-jvasi3rz/ramdisk.cpio.gz.uboot
218 03:03:57.523193 output: Image Name:
219 03:03:57.523615 output: Created: Sat Nov 9 03:03:57 2024
220 03:03:57.524130 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 03:03:57.524610 output: Data Size: 26053669 Bytes = 25443.04 KiB = 24.85 MiB
222 03:03:57.525063 output: Load Address: 00000000
223 03:03:57.525510 output: Entry Point: 00000000
224 03:03:57.525951 output:
225 03:03:57.527197 rename /var/lib/lava/dispatcher/tmp/964609/extract-overlay-ramdisk-jvasi3rz/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/964609/tftp-deploy-x58gtmr_/ramdisk/ramdisk.cpio.gz.uboot
226 03:03:57.528022 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 03:03:57.528656 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 03:03:57.529259 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
229 03:03:57.529772 No LXC device requested
230 03:03:57.530339 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 03:03:57.530915 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
232 03:03:57.531470 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 03:03:57.531932 Checking files for TFTP limit of 4294967296 bytes.
234 03:03:57.534925 end: 1 tftp-deploy (duration 00:00:18) [common]
235 03:03:57.535600 start: 2 uboot-action (timeout 00:05:00) [common]
236 03:03:57.536240 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 03:03:57.536829 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 03:03:57.537416 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 03:03:57.538025 Using kernel file from prepare-kernel: 964609/tftp-deploy-x58gtmr_/kernel/uImage
240 03:03:57.538753 substitutions:
241 03:03:57.539232 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 03:03:57.539693 - {DTB_ADDR}: 0x01070000
243 03:03:57.540184 - {DTB}: 964609/tftp-deploy-x58gtmr_/dtb/meson-g12b-a311d-libretech-cc.dtb
244 03:03:57.540647 - {INITRD}: 964609/tftp-deploy-x58gtmr_/ramdisk/ramdisk.cpio.gz.uboot
245 03:03:57.541096 - {KERNEL_ADDR}: 0x01080000
246 03:03:57.541542 - {KERNEL}: 964609/tftp-deploy-x58gtmr_/kernel/uImage
247 03:03:57.541989 - {LAVA_MAC}: None
248 03:03:57.542483 - {PRESEED_CONFIG}: None
249 03:03:57.542936 - {PRESEED_LOCAL}: None
250 03:03:57.543379 - {RAMDISK_ADDR}: 0x08000000
251 03:03:57.543817 - {RAMDISK}: 964609/tftp-deploy-x58gtmr_/ramdisk/ramdisk.cpio.gz.uboot
252 03:03:57.544342 - {ROOT_PART}: None
253 03:03:57.544821 - {ROOT}: None
254 03:03:57.545295 - {SERVER_IP}: 192.168.6.2
255 03:03:57.545763 - {TEE_ADDR}: 0x83000000
256 03:03:57.546224 - {TEE}: None
257 03:03:57.546673 Parsed boot commands:
258 03:03:57.547117 - setenv autoload no
259 03:03:57.547587 - setenv initrd_high 0xffffffff
260 03:03:57.548113 - setenv fdt_high 0xffffffff
261 03:03:57.548576 - dhcp
262 03:03:57.549054 - setenv serverip 192.168.6.2
263 03:03:57.549538 - tftpboot 0x01080000 964609/tftp-deploy-x58gtmr_/kernel/uImage
264 03:03:57.550038 - tftpboot 0x08000000 964609/tftp-deploy-x58gtmr_/ramdisk/ramdisk.cpio.gz.uboot
265 03:03:57.550508 - tftpboot 0x01070000 964609/tftp-deploy-x58gtmr_/dtb/meson-g12b-a311d-libretech-cc.dtb
266 03:03:57.550951 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 03:03:57.551400 - bootm 0x01080000 0x08000000 0x01070000
268 03:03:57.552076 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 03:03:57.553817 start: 2.3 connect-device (timeout 00:05:00) [common]
271 03:03:57.554318 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 03:03:57.570343 Setting prompt string to ['lava-test: # ']
273 03:03:57.572135 end: 2.3 connect-device (duration 00:00:00) [common]
274 03:03:57.572827 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 03:03:57.573431 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 03:03:57.574020 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 03:03:57.575292 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 03:03:57.617995 >> OK - accepted request
279 03:03:57.620191 Returned 0 in 0 seconds
280 03:03:57.721477 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 03:03:57.723366 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 03:03:57.724047 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 03:03:57.724628 Setting prompt string to ['Hit any key to stop autoboot']
285 03:03:57.725122 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 03:03:57.726925 Trying 192.168.56.21...
287 03:03:57.727467 Connected to conserv1.
288 03:03:57.727911 Escape character is '^]'.
289 03:03:57.728411
290 03:03:57.728881 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 03:03:57.729365
292 03:04:08.981483 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 03:04:08.982148 bl2_stage_init 0x01
294 03:04:08.982621 bl2_stage_init 0x81
295 03:04:08.987042 hw id: 0x0000 - pwm id 0x01
296 03:04:08.987563 bl2_stage_init 0xc1
297 03:04:08.988058 bl2_stage_init 0x02
298 03:04:08.988518
299 03:04:08.992544 L0:00000000
300 03:04:08.993065 L1:20000703
301 03:04:08.993562 L2:00008067
302 03:04:08.993996 L3:14000000
303 03:04:08.998163 B2:00402000
304 03:04:08.998651 B1:e0f83180
305 03:04:08.999081
306 03:04:08.999511 TE: 58124
307 03:04:08.999934
308 03:04:09.003651 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 03:04:09.004210
310 03:04:09.004758 Board ID = 1
311 03:04:09.009340 Set A53 clk to 24M
312 03:04:09.009824 Set A73 clk to 24M
313 03:04:09.010253 Set clk81 to 24M
314 03:04:09.014926 A53 clk: 1200 MHz
315 03:04:09.015382 A73 clk: 1200 MHz
316 03:04:09.015806 CLK81: 166.6M
317 03:04:09.016265 smccc: 00012a92
318 03:04:09.020547 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 03:04:09.026141 board id: 1
320 03:04:09.032020 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 03:04:09.042763 fw parse done
322 03:04:09.047807 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 03:04:09.091144 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 03:04:09.102123 PIEI prepare done
325 03:04:09.102737 fastboot data load
326 03:04:09.103315 fastboot data verify
327 03:04:09.107680 verify result: 266
328 03:04:09.113296 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 03:04:09.113875 LPDDR4 probe
330 03:04:09.114349 ddr clk to 1584MHz
331 03:04:09.121171 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 03:04:09.158592
333 03:04:09.159202 dmc_version 0001
334 03:04:09.164400 Check phy result
335 03:04:09.171117 INFO : End of CA training
336 03:04:09.171682 INFO : End of initialization
337 03:04:09.176702 INFO : Training has run successfully!
338 03:04:09.177237 Check phy result
339 03:04:09.182280 INFO : End of initialization
340 03:04:09.182814 INFO : End of read enable training
341 03:04:09.187897 INFO : End of fine write leveling
342 03:04:09.193483 INFO : End of Write leveling coarse delay
343 03:04:09.194017 INFO : Training has run successfully!
344 03:04:09.194476 Check phy result
345 03:04:09.199242 INFO : End of initialization
346 03:04:09.199808 INFO : End of read dq deskew training
347 03:04:09.204889 INFO : End of MPR read delay center optimization
348 03:04:09.210471 INFO : End of write delay center optimization
349 03:04:09.215975 INFO : End of read delay center optimization
350 03:04:09.216591 INFO : End of max read latency training
351 03:04:09.221604 INFO : Training has run successfully!
352 03:04:09.222161 1D training succeed
353 03:04:09.230760 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 03:04:09.278350 Check phy result
355 03:04:09.278974 INFO : End of initialization
356 03:04:09.300174 INFO : End of 2D read delay Voltage center optimization
357 03:04:09.320262 INFO : End of 2D read delay Voltage center optimization
358 03:04:09.372315 INFO : End of 2D write delay Voltage center optimization
359 03:04:09.421624 INFO : End of 2D write delay Voltage center optimization
360 03:04:09.427132 INFO : Training has run successfully!
361 03:04:09.427680
362 03:04:09.428245 channel==0
363 03:04:09.432729 RxClkDly_Margin_A0==88 ps 9
364 03:04:09.433251 TxDqDly_Margin_A0==98 ps 10
365 03:04:09.438292 RxClkDly_Margin_A1==88 ps 9
366 03:04:09.438823 TxDqDly_Margin_A1==98 ps 10
367 03:04:09.439309 TrainedVREFDQ_A0==74
368 03:04:09.443974 TrainedVREFDQ_A1==75
369 03:04:09.444627 VrefDac_Margin_A0==25
370 03:04:09.445116 DeviceVref_Margin_A0==40
371 03:04:09.449534 VrefDac_Margin_A1==25
372 03:04:09.450113 DeviceVref_Margin_A1==39
373 03:04:09.450636
374 03:04:09.451114
375 03:04:09.455124 channel==1
376 03:04:09.455690 RxClkDly_Margin_A0==98 ps 10
377 03:04:09.456261 TxDqDly_Margin_A0==98 ps 10
378 03:04:09.460691 RxClkDly_Margin_A1==88 ps 9
379 03:04:09.461242 TxDqDly_Margin_A1==88 ps 9
380 03:04:09.466367 TrainedVREFDQ_A0==77
381 03:04:09.466928 TrainedVREFDQ_A1==77
382 03:04:09.467372 VrefDac_Margin_A0==22
383 03:04:09.471927 DeviceVref_Margin_A0==37
384 03:04:09.472522 VrefDac_Margin_A1==24
385 03:04:09.477524 DeviceVref_Margin_A1==37
386 03:04:09.478102
387 03:04:09.478616 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 03:04:09.479074
389 03:04:09.511128 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
390 03:04:09.511591 2D training succeed
391 03:04:09.516667 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 03:04:09.522284 auto size-- 65535DDR cs0 size: 2048MB
393 03:04:09.522679 DDR cs1 size: 2048MB
394 03:04:09.527874 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 03:04:09.528287 cs0 DataBus test pass
396 03:04:09.533476 cs1 DataBus test pass
397 03:04:09.533804 cs0 AddrBus test pass
398 03:04:09.534040 cs1 AddrBus test pass
399 03:04:09.534264
400 03:04:09.539089 100bdlr_step_size ps== 432
401 03:04:09.539500 result report
402 03:04:09.544682 boot times 0Enable ddr reg access
403 03:04:09.550066 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 03:04:09.563787 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 03:04:10.136884 0.0;M3 CHK:0;cm4_sp_mode 0
406 03:04:10.137576 MVN_1=0x00000000
407 03:04:10.144292 MVN_2=0x00000000
408 03:04:10.147853 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 03:04:10.148299 OPS=0x10
410 03:04:10.148578 ring efuse init
411 03:04:10.148827 chipver efuse init
412 03:04:10.156110 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 03:04:10.156776 [0.018961 Inits done]
414 03:04:10.163639 secure task start!
415 03:04:10.164183 high task start!
416 03:04:10.164627 low task start!
417 03:04:10.165061 run into bl31
418 03:04:10.170329 NOTICE: BL31: v1.3(release):4fc40b1
419 03:04:10.178119 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 03:04:10.178719 NOTICE: BL31: G12A normal boot!
421 03:04:10.203441 NOTICE: BL31: BL33 decompress pass
422 03:04:10.209149 ERROR: Error initializing runtime service opteed_fast
423 03:04:11.442033
424 03:04:11.442468
425 03:04:11.450478 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 03:04:11.451013
427 03:04:11.451355 Model: Libre Computer AML-A311D-CC Alta
428 03:04:11.658973 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 03:04:11.682370 DRAM: 2 GiB (effective 3.8 GiB)
430 03:04:11.825338 Core: 408 devices, 31 uclasses, devicetree: separate
431 03:04:11.830495 WDT: Not starting watchdog@f0d0
432 03:04:11.863459 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 03:04:11.875876 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 03:04:11.880927 ** Bad device specification mmc 0 **
435 03:04:11.891213 Card did not respond to voltage select! : -110
436 03:04:11.898920 ** Bad device specification mmc 0 **
437 03:04:11.899353 Couldn't find partition mmc 0
438 03:04:11.907089 Card did not respond to voltage select! : -110
439 03:04:11.912692 ** Bad device specification mmc 0 **
440 03:04:11.913280 Couldn't find partition mmc 0
441 03:04:11.917743 Error: could not access storage.
442 03:04:13.181631 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 03:04:13.182324 bl2_stage_init 0x01
444 03:04:13.182804 bl2_stage_init 0x81
445 03:04:13.187224 hw id: 0x0000 - pwm id 0x01
446 03:04:13.187732 bl2_stage_init 0xc1
447 03:04:13.188246 bl2_stage_init 0x02
448 03:04:13.188698
449 03:04:13.192833 L0:00000000
450 03:04:13.193347 L1:20000703
451 03:04:13.193796 L2:00008067
452 03:04:13.194235 L3:14000000
453 03:04:13.198393 B2:00402000
454 03:04:13.198900 B1:e0f83180
455 03:04:13.199343
456 03:04:13.199786 TE: 58167
457 03:04:13.200272
458 03:04:13.204017 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 03:04:13.204523
460 03:04:13.204970 Board ID = 1
461 03:04:13.209570 Set A53 clk to 24M
462 03:04:13.210066 Set A73 clk to 24M
463 03:04:13.210510 Set clk81 to 24M
464 03:04:13.215196 A53 clk: 1200 MHz
465 03:04:13.215695 A73 clk: 1200 MHz
466 03:04:13.216182 CLK81: 166.6M
467 03:04:13.216628 smccc: 00012abe
468 03:04:13.220817 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 03:04:13.226384 board id: 1
470 03:04:13.231864 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 03:04:13.242993 fw parse done
472 03:04:13.248900 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 03:04:13.291892 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 03:04:13.302402 PIEI prepare done
475 03:04:13.302939 fastboot data load
476 03:04:13.303399 fastboot data verify
477 03:04:13.308231 verify result: 266
478 03:04:13.313703 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 03:04:13.314209 LPDDR4 probe
480 03:04:13.314656 ddr clk to 1584MHz
481 03:04:13.321004 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 03:04:13.358538
483 03:04:13.359074 dmc_version 0001
484 03:04:13.365716 Check phy result
485 03:04:13.371520 INFO : End of CA training
486 03:04:13.372059 INFO : End of initialization
487 03:04:13.377144 INFO : Training has run successfully!
488 03:04:13.377660 Check phy result
489 03:04:13.382713 INFO : End of initialization
490 03:04:13.383211 INFO : End of read enable training
491 03:04:13.386084 INFO : End of fine write leveling
492 03:04:13.391608 INFO : End of Write leveling coarse delay
493 03:04:13.397214 INFO : Training has run successfully!
494 03:04:13.397716 Check phy result
495 03:04:13.398159 INFO : End of initialization
496 03:04:13.402821 INFO : End of read dq deskew training
497 03:04:13.408478 INFO : End of MPR read delay center optimization
498 03:04:13.409046 INFO : End of write delay center optimization
499 03:04:13.414178 INFO : End of read delay center optimization
500 03:04:13.419731 INFO : End of max read latency training
501 03:04:13.420322 INFO : Training has run successfully!
502 03:04:13.425261 1D training succeed
503 03:04:13.430315 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 03:04:13.477822 Check phy result
505 03:04:13.478343 INFO : End of initialization
506 03:04:13.499936 INFO : End of 2D read delay Voltage center optimization
507 03:04:13.520125 INFO : End of 2D read delay Voltage center optimization
508 03:04:13.572650 INFO : End of 2D write delay Voltage center optimization
509 03:04:13.622189 INFO : End of 2D write delay Voltage center optimization
510 03:04:13.627634 INFO : Training has run successfully!
511 03:04:13.628194
512 03:04:13.628655 channel==0
513 03:04:13.633263 RxClkDly_Margin_A0==88 ps 9
514 03:04:13.633774 TxDqDly_Margin_A0==98 ps 10
515 03:04:13.638849 RxClkDly_Margin_A1==88 ps 9
516 03:04:13.639355 TxDqDly_Margin_A1==98 ps 10
517 03:04:13.639811 TrainedVREFDQ_A0==74
518 03:04:13.644475 TrainedVREFDQ_A1==74
519 03:04:13.644993 VrefDac_Margin_A0==25
520 03:04:13.645439 DeviceVref_Margin_A0==40
521 03:04:13.650136 VrefDac_Margin_A1==25
522 03:04:13.650648 DeviceVref_Margin_A1==40
523 03:04:13.651097
524 03:04:13.651536
525 03:04:13.655624 channel==1
526 03:04:13.656165 RxClkDly_Margin_A0==98 ps 10
527 03:04:13.656619 TxDqDly_Margin_A0==88 ps 9
528 03:04:13.661254 RxClkDly_Margin_A1==98 ps 10
529 03:04:13.661766 TxDqDly_Margin_A1==88 ps 9
530 03:04:13.666853 TrainedVREFDQ_A0==76
531 03:04:13.667370 TrainedVREFDQ_A1==77
532 03:04:13.667823 VrefDac_Margin_A0==22
533 03:04:13.672372 DeviceVref_Margin_A0==38
534 03:04:13.672847 VrefDac_Margin_A1==22
535 03:04:13.678050 DeviceVref_Margin_A1==37
536 03:04:13.678520
537 03:04:13.678992 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 03:04:13.679436
539 03:04:13.711577 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
540 03:04:13.712171 2D training succeed
541 03:04:13.717200 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 03:04:13.722844 auto size-- 65535DDR cs0 size: 2048MB
543 03:04:13.723333 DDR cs1 size: 2048MB
544 03:04:13.728305 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 03:04:13.728791 cs0 DataBus test pass
546 03:04:13.734053 cs1 DataBus test pass
547 03:04:13.734532 cs0 AddrBus test pass
548 03:04:13.734974 cs1 AddrBus test pass
549 03:04:13.735417
550 03:04:13.739565 100bdlr_step_size ps== 420
551 03:04:13.740103 result report
552 03:04:13.745187 boot times 0Enable ddr reg access
553 03:04:13.749976 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 03:04:13.763790 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 03:04:14.337739 0.0;M3 CHK:0;cm4_sp_mode 0
556 03:04:14.338362 MVN_1=0x00000000
557 03:04:14.343205 MVN_2=0x00000000
558 03:04:14.349008 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 03:04:14.349528 OPS=0x10
560 03:04:14.349990 ring efuse init
561 03:04:14.350456 chipver efuse init
562 03:04:14.357222 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 03:04:14.357744 [0.018961 Inits done]
564 03:04:14.364233 secure task start!
565 03:04:14.364693 high task start!
566 03:04:14.365117 low task start!
567 03:04:14.365536 run into bl31
568 03:04:14.371439 NOTICE: BL31: v1.3(release):4fc40b1
569 03:04:14.379197 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 03:04:14.379673 NOTICE: BL31: G12A normal boot!
571 03:04:14.405175 NOTICE: BL31: BL33 decompress pass
572 03:04:14.410666 ERROR: Error initializing runtime service opteed_fast
573 03:04:15.643843
574 03:04:15.644536
575 03:04:15.651528 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 03:04:15.652043
577 03:04:15.652497 Model: Libre Computer AML-A311D-CC Alta
578 03:04:15.860642 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 03:04:15.883389 DRAM: 2 GiB (effective 3.8 GiB)
580 03:04:16.027088 Core: 408 devices, 31 uclasses, devicetree: separate
581 03:04:16.032502 WDT: Not starting watchdog@f0d0
582 03:04:16.066014 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 03:04:16.077590 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 03:04:16.081701 ** Bad device specification mmc 0 **
585 03:04:16.092886 Card did not respond to voltage select! : -110
586 03:04:16.101010 ** Bad device specification mmc 0 **
587 03:04:16.101517 Couldn't find partition mmc 0
588 03:04:16.108792 Card did not respond to voltage select! : -110
589 03:04:16.114384 ** Bad device specification mmc 0 **
590 03:04:16.114746 Couldn't find partition mmc 0
591 03:04:16.119337 Error: could not access storage.
592 03:04:16.461555 Net: eth0: ethernet@ff3f0000
593 03:04:16.462142 starting USB...
594 03:04:16.713664 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 03:04:16.714212 Starting the controller
596 03:04:16.720368 USB XHCI 1.10
597 03:04:18.433471 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 03:04:18.434073 bl2_stage_init 0x01
599 03:04:18.434496 bl2_stage_init 0x81
600 03:04:18.438960 hw id: 0x0000 - pwm id 0x01
601 03:04:18.439442 bl2_stage_init 0xc1
602 03:04:18.439858 bl2_stage_init 0x02
603 03:04:18.440318
604 03:04:18.444595 L0:00000000
605 03:04:18.445211 L1:20000703
606 03:04:18.445755 L2:00008067
607 03:04:18.446286 L3:14000000
608 03:04:18.450137 B2:00402000
609 03:04:18.450732 B1:e0f83180
610 03:04:18.451268
611 03:04:18.451793 TE: 58167
612 03:04:18.452371
613 03:04:18.455899 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 03:04:18.456418
615 03:04:18.456840 Board ID = 1
616 03:04:18.461249 Set A53 clk to 24M
617 03:04:18.461725 Set A73 clk to 24M
618 03:04:18.462137 Set clk81 to 24M
619 03:04:18.466870 A53 clk: 1200 MHz
620 03:04:18.467345 A73 clk: 1200 MHz
621 03:04:18.467754 CLK81: 166.6M
622 03:04:18.468194 smccc: 00012abd
623 03:04:18.472390 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 03:04:18.477938 board id: 1
625 03:04:18.483895 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 03:04:18.494580 fw parse done
627 03:04:18.500559 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 03:04:18.543205 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 03:04:18.554120 PIEI prepare done
630 03:04:18.554599 fastboot data load
631 03:04:18.555013 fastboot data verify
632 03:04:18.559849 verify result: 266
633 03:04:18.565442 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 03:04:18.565948 LPDDR4 probe
635 03:04:18.566357 ddr clk to 1584MHz
636 03:04:18.573463 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 03:04:18.610668
638 03:04:18.611214 dmc_version 0001
639 03:04:18.617377 Check phy result
640 03:04:18.623220 INFO : End of CA training
641 03:04:18.623742 INFO : End of initialization
642 03:04:18.628886 INFO : Training has run successfully!
643 03:04:18.629387 Check phy result
644 03:04:18.634394 INFO : End of initialization
645 03:04:18.634895 INFO : End of read enable training
646 03:04:18.637727 INFO : End of fine write leveling
647 03:04:18.643272 INFO : End of Write leveling coarse delay
648 03:04:18.648845 INFO : Training has run successfully!
649 03:04:18.649324 Check phy result
650 03:04:18.649732 INFO : End of initialization
651 03:04:18.654491 INFO : End of read dq deskew training
652 03:04:18.660100 INFO : End of MPR read delay center optimization
653 03:04:18.660590 INFO : End of write delay center optimization
654 03:04:18.665682 INFO : End of read delay center optimization
655 03:04:18.671237 INFO : End of max read latency training
656 03:04:18.671709 INFO : Training has run successfully!
657 03:04:18.676840 1D training succeed
658 03:04:18.682800 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 03:04:18.730368 Check phy result
660 03:04:18.730915 INFO : End of initialization
661 03:04:18.753003 INFO : End of 2D read delay Voltage center optimization
662 03:04:18.772426 INFO : End of 2D read delay Voltage center optimization
663 03:04:18.824412 INFO : End of 2D write delay Voltage center optimization
664 03:04:18.873876 INFO : End of 2D write delay Voltage center optimization
665 03:04:18.879323 INFO : Training has run successfully!
666 03:04:18.879813
667 03:04:18.880276 channel==0
668 03:04:18.885012 RxClkDly_Margin_A0==88 ps 9
669 03:04:18.885497 TxDqDly_Margin_A0==98 ps 10
670 03:04:18.888291 RxClkDly_Margin_A1==88 ps 9
671 03:04:18.888766 TxDqDly_Margin_A1==88 ps 9
672 03:04:18.893975 TrainedVREFDQ_A0==74
673 03:04:18.894459 TrainedVREFDQ_A1==74
674 03:04:18.894868 VrefDac_Margin_A0==24
675 03:04:18.899503 DeviceVref_Margin_A0==40
676 03:04:18.900011 VrefDac_Margin_A1==24
677 03:04:18.905030 DeviceVref_Margin_A1==40
678 03:04:18.905345
679 03:04:18.905561
680 03:04:18.905869 channel==1
681 03:04:18.906272 RxClkDly_Margin_A0==88 ps 9
682 03:04:18.910742 TxDqDly_Margin_A0==98 ps 10
683 03:04:18.911214 RxClkDly_Margin_A1==88 ps 9
684 03:04:18.916331 TxDqDly_Margin_A1==88 ps 9
685 03:04:18.916810 TrainedVREFDQ_A0==77
686 03:04:18.917219 TrainedVREFDQ_A1==77
687 03:04:18.921983 VrefDac_Margin_A0==23
688 03:04:18.922442 DeviceVref_Margin_A0==37
689 03:04:18.927377 VrefDac_Margin_A1==24
690 03:04:18.927830 DeviceVref_Margin_A1==37
691 03:04:18.928272
692 03:04:18.933076 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 03:04:18.933541
694 03:04:18.961087 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 03:04:18.966656 2D training succeed
696 03:04:18.972174 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 03:04:18.972685 auto size-- 65535DDR cs0 size: 2048MB
698 03:04:18.977840 DDR cs1 size: 2048MB
699 03:04:18.978354 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 03:04:18.983364 cs0 DataBus test pass
701 03:04:18.983894 cs1 DataBus test pass
702 03:04:18.984361 cs0 AddrBus test pass
703 03:04:18.988934 cs1 AddrBus test pass
704 03:04:18.989455
705 03:04:18.989867 100bdlr_step_size ps== 420
706 03:04:18.990277 result report
707 03:04:18.994553 boot times 0Enable ddr reg access
708 03:04:19.002037 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 03:04:19.015443 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 03:04:19.589681 0.0;M3 CHK:0;cm4_sp_mode 0
711 03:04:19.590186 MVN_1=0x00000000
712 03:04:19.594593 MVN_2=0x00000000
713 03:04:19.600271 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 03:04:19.600869 OPS=0x10
715 03:04:19.601397 ring efuse init
716 03:04:19.601903 chipver efuse init
717 03:04:19.605887 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 03:04:19.611467 [0.018960 Inits done]
719 03:04:19.612070 secure task start!
720 03:04:19.612585 high task start!
721 03:04:19.616075 low task start!
722 03:04:19.616644 run into bl31
723 03:04:19.622737 NOTICE: BL31: v1.3(release):4fc40b1
724 03:04:19.630545 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 03:04:19.631194 NOTICE: BL31: G12A normal boot!
726 03:04:19.655889 NOTICE: BL31: BL33 decompress pass
727 03:04:19.661521 ERROR: Error initializing runtime service opteed_fast
728 03:04:20.894493
729 03:04:20.895265
730 03:04:20.902820 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 03:04:20.903428
732 03:04:20.904028 Model: Libre Computer AML-A311D-CC Alta
733 03:04:21.111217 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 03:04:21.134609 DRAM: 2 GiB (effective 3.8 GiB)
735 03:04:21.277630 Core: 408 devices, 31 uclasses, devicetree: separate
736 03:04:21.283471 WDT: Not starting watchdog@f0d0
737 03:04:21.315749 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 03:04:21.328139 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 03:04:21.333183 ** Bad device specification mmc 0 **
740 03:04:21.343485 Card did not respond to voltage select! : -110
741 03:04:21.351136 ** Bad device specification mmc 0 **
742 03:04:21.351495 Couldn't find partition mmc 0
743 03:04:21.359463 Card did not respond to voltage select! : -110
744 03:04:21.365060 ** Bad device specification mmc 0 **
745 03:04:21.365674 Couldn't find partition mmc 0
746 03:04:21.370150 Error: could not access storage.
747 03:04:21.713590 Net: eth0: ethernet@ff3f0000
748 03:04:21.714072 starting USB...
749 03:04:21.965427 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 03:04:21.966227 Starting the controller
751 03:04:21.972318 USB XHCI 1.10
752 03:04:24.142180 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 03:04:24.142589 bl2_stage_init 0x01
754 03:04:24.142815 bl2_stage_init 0x81
755 03:04:24.147576 hw id: 0x0000 - pwm id 0x01
756 03:04:24.148030 bl2_stage_init 0xc1
757 03:04:24.148380 bl2_stage_init 0x02
758 03:04:24.148723
759 03:04:24.153352 L0:00000000
760 03:04:24.153754 L1:20000703
761 03:04:24.154002 L2:00008067
762 03:04:24.154220 L3:14000000
763 03:04:24.158987 B2:00402000
764 03:04:24.159396 B1:e0f83180
765 03:04:24.159735
766 03:04:24.160298 TE: 58124
767 03:04:24.160563
768 03:04:24.164728 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 03:04:24.165018
770 03:04:24.165236 Board ID = 1
771 03:04:24.170101 Set A53 clk to 24M
772 03:04:24.170396 Set A73 clk to 24M
773 03:04:24.170627 Set clk81 to 24M
774 03:04:24.175734 A53 clk: 1200 MHz
775 03:04:24.176065 A73 clk: 1200 MHz
776 03:04:24.176299 CLK81: 166.6M
777 03:04:24.176525 smccc: 00012a92
778 03:04:24.180993 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 03:04:24.186599 board id: 1
780 03:04:24.191775 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 03:04:24.203280 fw parse done
782 03:04:24.209232 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 03:04:24.250711 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 03:04:24.262647 PIEI prepare done
785 03:04:24.262978 fastboot data load
786 03:04:24.263202 fastboot data verify
787 03:04:24.268180 verify result: 266
788 03:04:24.273797 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 03:04:24.274250 LPDDR4 probe
790 03:04:24.274621 ddr clk to 1584MHz
791 03:04:24.281767 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 03:04:24.318071
793 03:04:24.318450 dmc_version 0001
794 03:04:24.324730 Check phy result
795 03:04:24.331581 INFO : End of CA training
796 03:04:24.331896 INFO : End of initialization
797 03:04:24.337148 INFO : Training has run successfully!
798 03:04:24.337442 Check phy result
799 03:04:24.342786 INFO : End of initialization
800 03:04:24.343222 INFO : End of read enable training
801 03:04:24.348399 INFO : End of fine write leveling
802 03:04:24.353994 INFO : End of Write leveling coarse delay
803 03:04:24.354302 INFO : Training has run successfully!
804 03:04:24.354538 Check phy result
805 03:04:24.359584 INFO : End of initialization
806 03:04:24.360048 INFO : End of read dq deskew training
807 03:04:24.365235 INFO : End of MPR read delay center optimization
808 03:04:24.370762 INFO : End of write delay center optimization
809 03:04:24.376376 INFO : End of read delay center optimization
810 03:04:24.376692 INFO : End of max read latency training
811 03:04:24.381981 INFO : Training has run successfully!
812 03:04:24.382426 1D training succeed
813 03:04:24.391250 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 03:04:24.439545 Check phy result
815 03:04:24.439955 INFO : End of initialization
816 03:04:24.460350 INFO : End of 2D read delay Voltage center optimization
817 03:04:24.481621 INFO : End of 2D read delay Voltage center optimization
818 03:04:24.533678 INFO : End of 2D write delay Voltage center optimization
819 03:04:24.582989 INFO : End of 2D write delay Voltage center optimization
820 03:04:24.588602 INFO : Training has run successfully!
821 03:04:24.589178
822 03:04:24.589605 channel==0
823 03:04:24.594138 RxClkDly_Margin_A0==88 ps 9
824 03:04:24.594668 TxDqDly_Margin_A0==98 ps 10
825 03:04:24.599795 RxClkDly_Margin_A1==88 ps 9
826 03:04:24.600439 TxDqDly_Margin_A1==98 ps 10
827 03:04:24.600869 TrainedVREFDQ_A0==74
828 03:04:24.605347 TrainedVREFDQ_A1==74
829 03:04:24.605931 VrefDac_Margin_A0==24
830 03:04:24.606325 DeviceVref_Margin_A0==40
831 03:04:24.611012 VrefDac_Margin_A1==24
832 03:04:24.611575 DeviceVref_Margin_A1==40
833 03:04:24.611965
834 03:04:24.612425
835 03:04:24.616602 channel==1
836 03:04:24.617139 RxClkDly_Margin_A0==98 ps 10
837 03:04:24.617531 TxDqDly_Margin_A0==88 ps 9
838 03:04:24.622205 RxClkDly_Margin_A1==88 ps 9
839 03:04:24.622739 TxDqDly_Margin_A1==88 ps 9
840 03:04:24.627849 TrainedVREFDQ_A0==76
841 03:04:24.628443 TrainedVREFDQ_A1==77
842 03:04:24.628855 VrefDac_Margin_A0==22
843 03:04:24.633450 DeviceVref_Margin_A0==38
844 03:04:24.633963 VrefDac_Margin_A1==24
845 03:04:24.638986 DeviceVref_Margin_A1==37
846 03:04:24.639507
847 03:04:24.639913 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 03:04:24.640344
849 03:04:24.672591 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
850 03:04:24.673196 2D training succeed
851 03:04:24.678145 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 03:04:24.683861 auto size-- 65535DDR cs0 size: 2048MB
853 03:04:24.684415 DDR cs1 size: 2048MB
854 03:04:24.689406 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 03:04:24.689877 cs0 DataBus test pass
856 03:04:24.694916 cs1 DataBus test pass
857 03:04:24.695398 cs0 AddrBus test pass
858 03:04:24.695798 cs1 AddrBus test pass
859 03:04:24.696221
860 03:04:24.700629 100bdlr_step_size ps== 420
861 03:04:24.701104 result report
862 03:04:24.706119 boot times 0Enable ddr reg access
863 03:04:24.710547 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 03:04:24.724878 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 03:04:25.298697 0.0;M3 CHK:0;cm4_sp_mode 0
866 03:04:25.299292 MVN_1=0x00000000
867 03:04:25.304088 MVN_2=0x00000000
868 03:04:25.309890 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 03:04:25.310365 OPS=0x10
870 03:04:25.310714 ring efuse init
871 03:04:25.310932 chipver efuse init
872 03:04:25.315456 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 03:04:25.321086 [0.018961 Inits done]
874 03:04:25.321560 secure task start!
875 03:04:25.321969 high task start!
876 03:04:25.325664 low task start!
877 03:04:25.325930 run into bl31
878 03:04:25.332309 NOTICE: BL31: v1.3(release):4fc40b1
879 03:04:25.340032 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 03:04:25.340549 NOTICE: BL31: G12A normal boot!
881 03:04:25.365507 NOTICE: BL31: BL33 decompress pass
882 03:04:25.370280 ERROR: Error initializing runtime service opteed_fast
883 03:04:26.604202
884 03:04:26.604838
885 03:04:26.612455 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 03:04:26.612971
887 03:04:26.613393 Model: Libre Computer AML-A311D-CC Alta
888 03:04:26.820838 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 03:04:26.844218 DRAM: 2 GiB (effective 3.8 GiB)
890 03:04:26.987404 Core: 408 devices, 31 uclasses, devicetree: separate
891 03:04:26.993089 WDT: Not starting watchdog@f0d0
892 03:04:27.025370 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 03:04:27.037973 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 03:04:27.042839 ** Bad device specification mmc 0 **
895 03:04:27.053146 Card did not respond to voltage select! : -110
896 03:04:27.060876 ** Bad device specification mmc 0 **
897 03:04:27.061398 Couldn't find partition mmc 0
898 03:04:27.069224 Card did not respond to voltage select! : -110
899 03:04:27.074702 ** Bad device specification mmc 0 **
900 03:04:27.075235 Couldn't find partition mmc 0
901 03:04:27.079762 Error: could not access storage.
902 03:04:27.423216 Net: eth0: ethernet@ff3f0000
903 03:04:27.423833 starting USB...
904 03:04:27.675120 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 03:04:27.675730 Starting the controller
906 03:04:27.682071 USB XHCI 1.10
907 03:04:29.541702 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 03:04:29.542324 bl2_stage_init 0x01
909 03:04:29.542778 bl2_stage_init 0x81
910 03:04:29.547357 hw id: 0x0000 - pwm id 0x01
911 03:04:29.547867 bl2_stage_init 0xc1
912 03:04:29.548343 bl2_stage_init 0x02
913 03:04:29.548752
914 03:04:29.552893 L0:00000000
915 03:04:29.553341 L1:20000703
916 03:04:29.553753 L2:00008067
917 03:04:29.554156 L3:14000000
918 03:04:29.558339 B2:00402000
919 03:04:29.558790 B1:e0f83180
920 03:04:29.559138
921 03:04:29.559361 TE: 58124
922 03:04:29.559571
923 03:04:29.563972 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 03:04:29.564465
925 03:04:29.564878 Board ID = 1
926 03:04:29.569695 Set A53 clk to 24M
927 03:04:29.570152 Set A73 clk to 24M
928 03:04:29.570564 Set clk81 to 24M
929 03:04:29.575283 A53 clk: 1200 MHz
930 03:04:29.575705 A73 clk: 1200 MHz
931 03:04:29.576160 CLK81: 166.6M
932 03:04:29.576593 smccc: 00012a92
933 03:04:29.580813 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 03:04:29.586444 board id: 1
935 03:04:29.592382 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 03:04:29.602861 fw parse done
937 03:04:29.608020 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 03:04:29.651564 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 03:04:29.662449 PIEI prepare done
940 03:04:29.662903 fastboot data load
941 03:04:29.663305 fastboot data verify
942 03:04:29.668006 verify result: 266
943 03:04:29.674136 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 03:04:29.674570 LPDDR4 probe
945 03:04:29.674960 ddr clk to 1584MHz
946 03:04:29.681539 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 03:04:29.719286
948 03:04:29.719724 dmc_version 0001
949 03:04:29.725628 Check phy result
950 03:04:29.731334 INFO : End of CA training
951 03:04:29.731816 INFO : End of initialization
952 03:04:29.736971 INFO : Training has run successfully!
953 03:04:29.737242 Check phy result
954 03:04:29.742673 INFO : End of initialization
955 03:04:29.743166 INFO : End of read enable training
956 03:04:29.748269 INFO : End of fine write leveling
957 03:04:29.753803 INFO : End of Write leveling coarse delay
958 03:04:29.754241 INFO : Training has run successfully!
959 03:04:29.754650 Check phy result
960 03:04:29.759348 INFO : End of initialization
961 03:04:29.759788 INFO : End of read dq deskew training
962 03:04:29.765029 INFO : End of MPR read delay center optimization
963 03:04:29.770564 INFO : End of write delay center optimization
964 03:04:29.776468 INFO : End of read delay center optimization
965 03:04:29.776922 INFO : End of max read latency training
966 03:04:29.781914 INFO : Training has run successfully!
967 03:04:29.782352 1D training succeed
968 03:04:29.790971 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 03:04:29.838686 Check phy result
970 03:04:29.839176 INFO : End of initialization
971 03:04:29.860169 INFO : End of 2D read delay Voltage center optimization
972 03:04:29.880355 INFO : End of 2D read delay Voltage center optimization
973 03:04:29.931204 INFO : End of 2D write delay Voltage center optimization
974 03:04:29.981505 INFO : End of 2D write delay Voltage center optimization
975 03:04:29.987006 INFO : Training has run successfully!
976 03:04:29.987325
977 03:04:29.987564 channel==0
978 03:04:29.992587 RxClkDly_Margin_A0==88 ps 9
979 03:04:29.993044 TxDqDly_Margin_A0==98 ps 10
980 03:04:29.995895 RxClkDly_Margin_A1==88 ps 9
981 03:04:29.996375 TxDqDly_Margin_A1==88 ps 9
982 03:04:30.001494 TrainedVREFDQ_A0==74
983 03:04:30.001939 TrainedVREFDQ_A1==74
984 03:04:30.002352 VrefDac_Margin_A0==25
985 03:04:30.007183 DeviceVref_Margin_A0==40
986 03:04:30.007620 VrefDac_Margin_A1==25
987 03:04:30.012700 DeviceVref_Margin_A1==40
988 03:04:30.013026
989 03:04:30.013253
990 03:04:30.013469 channel==1
991 03:04:30.013689 RxClkDly_Margin_A0==98 ps 10
992 03:04:30.018479 TxDqDly_Margin_A0==88 ps 9
993 03:04:30.018958 RxClkDly_Margin_A1==98 ps 10
994 03:04:30.023945 TxDqDly_Margin_A1==98 ps 10
995 03:04:30.024311 TrainedVREFDQ_A0==77
996 03:04:30.024526 TrainedVREFDQ_A1==77
997 03:04:30.029644 VrefDac_Margin_A0==22
998 03:04:30.030179 DeviceVref_Margin_A0==37
999 03:04:30.035154 VrefDac_Margin_A1==22
1000 03:04:30.035662 DeviceVref_Margin_A1==37
1001 03:04:30.036171
1002 03:04:30.040735 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 03:04:30.041229
1004 03:04:30.068770 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1005 03:04:30.074416 2D training succeed
1006 03:04:30.079883 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 03:04:30.080425 auto size-- 65535DDR cs0 size: 2048MB
1008 03:04:30.085398 DDR cs1 size: 2048MB
1009 03:04:30.085911 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 03:04:30.091053 cs0 DataBus test pass
1011 03:04:30.091560 cs1 DataBus test pass
1012 03:04:30.092046 cs0 AddrBus test pass
1013 03:04:30.096528 cs1 AddrBus test pass
1014 03:04:30.097027
1015 03:04:30.097484 100bdlr_step_size ps== 420
1016 03:04:30.097945 result report
1017 03:04:30.102302 boot times 0Enable ddr reg access
1018 03:04:30.109817 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 03:04:30.123360 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 03:04:30.695365 0.0;M3 CHK:0;cm4_sp_mode 0
1021 03:04:30.696136 MVN_1=0x00000000
1022 03:04:30.700780 MVN_2=0x00000000
1023 03:04:30.706488 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 03:04:30.706974 OPS=0x10
1025 03:04:30.707430 ring efuse init
1026 03:04:30.707873 chipver efuse init
1027 03:04:30.714824 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 03:04:30.715341 [0.018961 Inits done]
1029 03:04:30.721476 secure task start!
1030 03:04:30.721959 high task start!
1031 03:04:30.722412 low task start!
1032 03:04:30.722856 run into bl31
1033 03:04:30.729181 NOTICE: BL31: v1.3(release):4fc40b1
1034 03:04:30.735902 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 03:04:30.736426 NOTICE: BL31: G12A normal boot!
1036 03:04:30.762232 NOTICE: BL31: BL33 decompress pass
1037 03:04:30.767022 ERROR: Error initializing runtime service opteed_fast
1038 03:04:32.000824
1039 03:04:32.001470
1040 03:04:32.008273 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 03:04:32.008772
1042 03:04:32.009228 Model: Libre Computer AML-A311D-CC Alta
1043 03:04:32.217604 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 03:04:32.240951 DRAM: 2 GiB (effective 3.8 GiB)
1045 03:04:32.383961 Core: 408 devices, 31 uclasses, devicetree: separate
1046 03:04:32.389753 WDT: Not starting watchdog@f0d0
1047 03:04:32.422103 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 03:04:32.434657 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 03:04:32.439565 ** Bad device specification mmc 0 **
1050 03:04:32.449944 Card did not respond to voltage select! : -110
1051 03:04:32.458595 ** Bad device specification mmc 0 **
1052 03:04:32.459099 Couldn't find partition mmc 0
1053 03:04:32.465799 Card did not respond to voltage select! : -110
1054 03:04:32.471304 ** Bad device specification mmc 0 **
1055 03:04:32.471790 Couldn't find partition mmc 0
1056 03:04:32.476369 Error: could not access storage.
1057 03:04:32.818902 Net: eth0: ethernet@ff3f0000
1058 03:04:32.819514 starting USB...
1059 03:04:33.071490 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 03:04:33.072461 Starting the controller
1061 03:04:33.077645 USB XHCI 1.10
1062 03:04:34.633786 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 03:04:34.642176 scanning usb for storage devices... 0 Storage Device(s) found
1065 03:04:34.693773 Hit any key to stop autoboot: 1
1066 03:04:34.694628 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 03:04:34.695260 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 03:04:34.695760 Setting prompt string to ['=>']
1069 03:04:34.696326 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 03:04:34.709598 0
1071 03:04:34.710584 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 03:04:34.711150 Sending with 10 millisecond of delay
1074 03:04:35.846283 => setenv autoload no
1075 03:04:35.857099 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1076 03:04:35.861460 setenv autoload no
1077 03:04:35.862253 Sending with 10 millisecond of delay
1079 03:04:37.660309 => setenv initrd_high 0xffffffff
1080 03:04:37.671063 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 03:04:37.671771 setenv initrd_high 0xffffffff
1082 03:04:37.672471 Sending with 10 millisecond of delay
1084 03:04:39.289475 => setenv fdt_high 0xffffffff
1085 03:04:39.300315 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 03:04:39.301179 setenv fdt_high 0xffffffff
1087 03:04:39.301947 Sending with 10 millisecond of delay
1089 03:04:39.593952 => dhcp
1090 03:04:39.604762 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 03:04:39.605639 dhcp
1092 03:04:39.606122 Speed: 1000, full duplex
1093 03:04:39.606575 BOOTP broadcast 1
1094 03:04:39.613818 DHCP client bound to address 192.168.6.27 (10 ms)
1095 03:04:39.614576 Sending with 10 millisecond of delay
1097 03:04:41.295256 => setenv serverip 192.168.6.2
1098 03:04:41.305794 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 03:04:41.306330 setenv serverip 192.168.6.2
1100 03:04:41.306806 Sending with 10 millisecond of delay
1102 03:04:45.033760 => tftpboot 0x01080000 964609/tftp-deploy-x58gtmr_/kernel/uImage
1103 03:04:45.044357 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 03:04:45.044902 tftpboot 0x01080000 964609/tftp-deploy-x58gtmr_/kernel/uImage
1105 03:04:45.045171 Speed: 1000, full duplex
1106 03:04:45.045409 Using ethernet@ff3f0000 device
1107 03:04:45.046989 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 03:04:45.052507 Filename '964609/tftp-deploy-x58gtmr_/kernel/uImage'.
1109 03:04:45.056402 Load address: 0x1080000
1110 03:04:47.829125 Loading: *################################################## 43.6 MiB
1111 03:04:47.829774 15.7 MiB/s
1112 03:04:47.830203 done
1113 03:04:47.833668 Bytes transferred = 45713984 (2b98a40 hex)
1114 03:04:47.834467 Sending with 10 millisecond of delay
1116 03:04:52.521401 => tftpboot 0x08000000 964609/tftp-deploy-x58gtmr_/ramdisk/ramdisk.cpio.gz.uboot
1117 03:04:52.532187 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1118 03:04:52.533038 tftpboot 0x08000000 964609/tftp-deploy-x58gtmr_/ramdisk/ramdisk.cpio.gz.uboot
1119 03:04:52.533483 Speed: 1000, full duplex
1120 03:04:52.533896 Using ethernet@ff3f0000 device
1121 03:04:52.535551 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 03:04:52.546909 Filename '964609/tftp-deploy-x58gtmr_/ramdisk/ramdisk.cpio.gz.uboot'.
1123 03:04:52.547436 Load address: 0x8000000
1124 03:04:59.387723 Loading: *#################T ################################ UDP wrong checksum 00000005 0000e178
1125 03:05:02.969141 UDP wrong checksum 000000ff 0000fdcf
1126 03:05:03.027731 UDP wrong checksum 000000ff 00005649
1127 03:05:04.365602 UDP wrong checksum 000000ff 0000cd44
1128 03:05:04.389726 T UDP wrong checksum 00000005 0000e178
1129 03:05:04.409220 UDP wrong checksum 000000ff 00006837
1130 03:05:08.475803 UDP wrong checksum 000000ff 000052bc
1131 03:05:08.489137 UDP wrong checksum 000000ff 0000dbae
1132 03:05:14.391866 T T UDP wrong checksum 00000005 0000e178
1133 03:05:34.395739 T T T T UDP wrong checksum 00000005 0000e178
1134 03:05:49.399747 T T
1135 03:05:49.400209 Retry count exceeded; starting again
1137 03:05:49.403077 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1140 03:05:49.405153 end: 2.4 uboot-commands (duration 00:01:52) [common]
1142 03:05:49.406644 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1144 03:05:49.407756 end: 2 uboot-action (duration 00:01:52) [common]
1146 03:05:49.409500 Cleaning after the job
1147 03:05:49.410113 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964609/tftp-deploy-x58gtmr_/ramdisk
1148 03:05:49.411793 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964609/tftp-deploy-x58gtmr_/kernel
1149 03:05:49.457408 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964609/tftp-deploy-x58gtmr_/dtb
1150 03:05:49.458276 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964609/tftp-deploy-x58gtmr_/modules
1151 03:05:49.478307 start: 4.1 power-off (timeout 00:00:30) [common]
1152 03:05:49.478964 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1153 03:05:49.516161 >> OK - accepted request
1154 03:05:49.518330 Returned 0 in 0 seconds
1155 03:05:49.619411 end: 4.1 power-off (duration 00:00:00) [common]
1157 03:05:49.621285 start: 4.2 read-feedback (timeout 00:10:00) [common]
1158 03:05:49.622002 Listened to connection for namespace 'common' for up to 1s
1159 03:05:50.622428 Finalising connection for namespace 'common'
1160 03:05:50.623204 Disconnecting from shell: Finalise
1161 03:05:50.623770 =>
1162 03:05:50.724949 end: 4.2 read-feedback (duration 00:00:01) [common]
1163 03:05:50.725714 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/964609
1164 03:05:51.027830 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/964609
1165 03:05:51.028501 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.