Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 7
- Errors: 0
- Boot result: PASS
- Kernel Errors: 6
1 03:31:19.668459 lava-dispatcher, installed at version: 2024.01
2 03:31:19.669415 start: 0 validate
3 03:31:19.669952 Start time: 2024-11-09 03:31:19.669920+00:00 (UTC)
4 03:31:19.670546 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:31:19.671115 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 03:31:19.717563 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:31:19.718177 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-247-gbf99f9b489d8e%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 03:31:19.754248 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:31:19.755319 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-247-gbf99f9b489d8e%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 03:31:19.792073 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:31:19.792619 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 03:31:19.828171 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 03:31:19.828717 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-247-gbf99f9b489d8e%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 03:31:19.874611 validate duration: 0.20
16 03:31:19.876226 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 03:31:19.876875 start: 1.1 download-retry (timeout 00:10:00) [common]
18 03:31:19.877503 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 03:31:19.878684 Not decompressing ramdisk as can be used compressed.
20 03:31:19.879180 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 03:31:19.879493 saving as /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/ramdisk/initrd.cpio.gz
22 03:31:19.879782 total size: 5628169 (5 MB)
23 03:31:19.922726 progress 0 % (0 MB)
24 03:31:19.931177 progress 5 % (0 MB)
25 03:31:19.939966 progress 10 % (0 MB)
26 03:31:19.947924 progress 15 % (0 MB)
27 03:31:19.956284 progress 20 % (1 MB)
28 03:31:19.960140 progress 25 % (1 MB)
29 03:31:19.964286 progress 30 % (1 MB)
30 03:31:19.968480 progress 35 % (1 MB)
31 03:31:19.972188 progress 40 % (2 MB)
32 03:31:19.976336 progress 45 % (2 MB)
33 03:31:19.980109 progress 50 % (2 MB)
34 03:31:19.984178 progress 55 % (2 MB)
35 03:31:19.988300 progress 60 % (3 MB)
36 03:31:19.992032 progress 65 % (3 MB)
37 03:31:19.996107 progress 70 % (3 MB)
38 03:31:19.999803 progress 75 % (4 MB)
39 03:31:20.003950 progress 80 % (4 MB)
40 03:31:20.007667 progress 85 % (4 MB)
41 03:31:20.011743 progress 90 % (4 MB)
42 03:31:20.015577 progress 95 % (5 MB)
43 03:31:20.019045 progress 100 % (5 MB)
44 03:31:20.019782 5 MB downloaded in 0.14 s (38.35 MB/s)
45 03:31:20.020363 end: 1.1.1 http-download (duration 00:00:00) [common]
47 03:31:20.021293 end: 1.1 download-retry (duration 00:00:00) [common]
48 03:31:20.021596 start: 1.2 download-retry (timeout 00:10:00) [common]
49 03:31:20.021876 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 03:31:20.022381 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm64/defconfig/gcc-12/kernel/Image
51 03:31:20.022662 saving as /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/kernel/Image
52 03:31:20.022880 total size: 45713920 (43 MB)
53 03:31:20.023095 No compression specified
54 03:31:20.063169 progress 0 % (0 MB)
55 03:31:20.092341 progress 5 % (2 MB)
56 03:31:20.122253 progress 10 % (4 MB)
57 03:31:20.153141 progress 15 % (6 MB)
58 03:31:20.183548 progress 20 % (8 MB)
59 03:31:20.212809 progress 25 % (10 MB)
60 03:31:20.242842 progress 30 % (13 MB)
61 03:31:20.272603 progress 35 % (15 MB)
62 03:31:20.301887 progress 40 % (17 MB)
63 03:31:20.331283 progress 45 % (19 MB)
64 03:31:20.360909 progress 50 % (21 MB)
65 03:31:20.390335 progress 55 % (24 MB)
66 03:31:20.419600 progress 60 % (26 MB)
67 03:31:20.448346 progress 65 % (28 MB)
68 03:31:20.477417 progress 70 % (30 MB)
69 03:31:20.507718 progress 75 % (32 MB)
70 03:31:20.539019 progress 80 % (34 MB)
71 03:31:20.567829 progress 85 % (37 MB)
72 03:31:20.596832 progress 90 % (39 MB)
73 03:31:20.626070 progress 95 % (41 MB)
74 03:31:20.654705 progress 100 % (43 MB)
75 03:31:20.655225 43 MB downloaded in 0.63 s (68.95 MB/s)
76 03:31:20.655728 end: 1.2.1 http-download (duration 00:00:01) [common]
78 03:31:20.656643 end: 1.2 download-retry (duration 00:00:01) [common]
79 03:31:20.656941 start: 1.3 download-retry (timeout 00:09:59) [common]
80 03:31:20.657224 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 03:31:20.657708 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 03:31:20.657988 saving as /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/dtb/meson-g12b-a311d-libretech-cc.dtb
83 03:31:20.658207 total size: 54703 (0 MB)
84 03:31:20.658425 No compression specified
85 03:31:20.698044 progress 59 % (0 MB)
86 03:31:20.698903 progress 100 % (0 MB)
87 03:31:20.699455 0 MB downloaded in 0.04 s (1.27 MB/s)
88 03:31:20.699926 end: 1.3.1 http-download (duration 00:00:00) [common]
90 03:31:20.700782 end: 1.3 download-retry (duration 00:00:00) [common]
91 03:31:20.701049 start: 1.4 download-retry (timeout 00:09:59) [common]
92 03:31:20.701313 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 03:31:20.701768 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 03:31:20.702010 saving as /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/nfsrootfs/full.rootfs.tar
95 03:31:20.702219 total size: 120894716 (115 MB)
96 03:31:20.702430 Using unxz to decompress xz
97 03:31:20.738676 progress 0 % (0 MB)
98 03:31:21.524828 progress 5 % (5 MB)
99 03:31:22.362195 progress 10 % (11 MB)
100 03:31:23.156102 progress 15 % (17 MB)
101 03:31:23.899439 progress 20 % (23 MB)
102 03:31:24.495750 progress 25 % (28 MB)
103 03:31:25.324161 progress 30 % (34 MB)
104 03:31:26.115525 progress 35 % (40 MB)
105 03:31:26.462442 progress 40 % (46 MB)
106 03:31:26.843010 progress 45 % (51 MB)
107 03:31:27.562686 progress 50 % (57 MB)
108 03:31:28.445820 progress 55 % (63 MB)
109 03:31:29.242489 progress 60 % (69 MB)
110 03:31:29.994357 progress 65 % (74 MB)
111 03:31:30.767268 progress 70 % (80 MB)
112 03:31:31.585626 progress 75 % (86 MB)
113 03:31:32.367823 progress 80 % (92 MB)
114 03:31:33.125343 progress 85 % (98 MB)
115 03:31:33.972844 progress 90 % (103 MB)
116 03:31:34.746439 progress 95 % (109 MB)
117 03:31:35.587197 progress 100 % (115 MB)
118 03:31:35.599929 115 MB downloaded in 14.90 s (7.74 MB/s)
119 03:31:35.600669 end: 1.4.1 http-download (duration 00:00:15) [common]
121 03:31:35.601657 end: 1.4 download-retry (duration 00:00:15) [common]
122 03:31:35.601997 start: 1.5 download-retry (timeout 00:09:44) [common]
123 03:31:35.602311 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 03:31:35.605110 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm64/defconfig/gcc-12/modules.tar.xz
125 03:31:35.605463 saving as /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/modules/modules.tar
126 03:31:35.605672 total size: 11612756 (11 MB)
127 03:31:35.605886 Using unxz to decompress xz
128 03:31:35.649731 progress 0 % (0 MB)
129 03:31:35.715748 progress 5 % (0 MB)
130 03:31:35.789215 progress 10 % (1 MB)
131 03:31:35.884800 progress 15 % (1 MB)
132 03:31:35.975116 progress 20 % (2 MB)
133 03:31:36.055010 progress 25 % (2 MB)
134 03:31:36.130409 progress 30 % (3 MB)
135 03:31:36.208519 progress 35 % (3 MB)
136 03:31:36.280816 progress 40 % (4 MB)
137 03:31:36.356198 progress 45 % (5 MB)
138 03:31:36.441951 progress 50 % (5 MB)
139 03:31:36.518984 progress 55 % (6 MB)
140 03:31:36.604450 progress 60 % (6 MB)
141 03:31:36.684742 progress 65 % (7 MB)
142 03:31:36.765867 progress 70 % (7 MB)
143 03:31:36.843554 progress 75 % (8 MB)
144 03:31:36.926666 progress 80 % (8 MB)
145 03:31:37.005987 progress 85 % (9 MB)
146 03:31:37.084363 progress 90 % (9 MB)
147 03:31:37.161578 progress 95 % (10 MB)
148 03:31:37.238183 progress 100 % (11 MB)
149 03:31:37.249801 11 MB downloaded in 1.64 s (6.74 MB/s)
150 03:31:37.250365 end: 1.5.1 http-download (duration 00:00:02) [common]
152 03:31:37.251194 end: 1.5 download-retry (duration 00:00:02) [common]
153 03:31:37.251467 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 03:31:37.251737 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 03:31:53.545483 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/964641/extract-nfsrootfs-zln5lm9w
156 03:31:53.546101 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 03:31:53.546394 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 03:31:53.547171 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk
159 03:31:53.547635 makedir: /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin
160 03:31:53.547969 makedir: /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/tests
161 03:31:53.548324 makedir: /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/results
162 03:31:53.548658 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-add-keys
163 03:31:53.549201 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-add-sources
164 03:31:53.549722 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-background-process-start
165 03:31:53.550236 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-background-process-stop
166 03:31:53.550799 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-common-functions
167 03:31:53.551302 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-echo-ipv4
168 03:31:53.551809 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-install-packages
169 03:31:53.552355 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-installed-packages
170 03:31:53.552835 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-os-build
171 03:31:53.553314 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-probe-channel
172 03:31:53.553786 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-probe-ip
173 03:31:53.554258 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-target-ip
174 03:31:53.554731 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-target-mac
175 03:31:53.555205 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-target-storage
176 03:31:53.555712 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-test-case
177 03:31:53.556247 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-test-event
178 03:31:53.556734 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-test-feedback
179 03:31:53.557214 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-test-raise
180 03:31:53.557689 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-test-reference
181 03:31:53.558164 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-test-runner
182 03:31:53.558640 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-test-set
183 03:31:53.559115 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-test-shell
184 03:31:53.559628 Updating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-add-keys (debian)
185 03:31:53.560207 Updating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-add-sources (debian)
186 03:31:53.560741 Updating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-install-packages (debian)
187 03:31:53.561246 Updating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-installed-packages (debian)
188 03:31:53.561800 Updating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/bin/lava-os-build (debian)
189 03:31:53.562253 Creating /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/environment
190 03:31:53.562621 LAVA metadata
191 03:31:53.562881 - LAVA_JOB_ID=964641
192 03:31:53.563100 - LAVA_DISPATCHER_IP=192.168.6.2
193 03:31:53.563470 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 03:31:53.564450 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 03:31:53.564776 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 03:31:53.564986 skipped lava-vland-overlay
197 03:31:53.565228 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 03:31:53.565484 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 03:31:53.565704 skipped lava-multinode-overlay
200 03:31:53.565949 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 03:31:53.566201 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 03:31:53.566452 Loading test definitions
203 03:31:53.566737 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 03:31:53.566956 Using /lava-964641 at stage 0
205 03:31:53.568124 uuid=964641_1.6.2.4.1 testdef=None
206 03:31:53.568457 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 03:31:53.568727 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 03:31:53.570340 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 03:31:53.571129 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 03:31:53.573109 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 03:31:53.573928 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 03:31:53.575740 runner path: /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/0/tests/0_timesync-off test_uuid 964641_1.6.2.4.1
215 03:31:53.576307 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 03:31:53.577119 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 03:31:53.577357 Using /lava-964641 at stage 0
219 03:31:53.577716 Fetching tests from https://github.com/kernelci/test-definitions.git
220 03:31:53.578004 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/0/tests/1_kselftest-alsa'
221 03:31:56.983996 Running '/usr/bin/git checkout kernelci.org
222 03:31:57.434448 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 03:31:57.435912 uuid=964641_1.6.2.4.5 testdef=None
224 03:31:57.436527 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 03:31:57.438140 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 03:31:57.444146 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 03:31:57.445899 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 03:31:57.453929 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 03:31:57.455759 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 03:31:57.463536 runner path: /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/0/tests/1_kselftest-alsa test_uuid 964641_1.6.2.4.5
234 03:31:57.464148 BOARD='meson-g12b-a311d-libretech-cc'
235 03:31:57.464601 BRANCH='broonie-sound'
236 03:31:57.465037 SKIPFILE='/dev/null'
237 03:31:57.465471 SKIP_INSTALL='True'
238 03:31:57.465901 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 03:31:57.466344 TST_CASENAME=''
240 03:31:57.466776 TST_CMDFILES='alsa'
241 03:31:57.467859 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 03:31:57.469579 Creating lava-test-runner.conf files
244 03:31:57.470025 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/964641/lava-overlay-1q6i66zk/lava-964641/0 for stage 0
245 03:31:57.470763 - 0_timesync-off
246 03:31:57.471271 - 1_kselftest-alsa
247 03:31:57.471961 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 03:31:57.472590 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 03:32:20.705728 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 03:32:20.706182 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 03:32:20.706449 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 03:32:20.706723 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 03:32:20.706991 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 03:32:21.370808 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 03:32:21.371291 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
256 03:32:21.371547 extracting modules file /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964641/extract-nfsrootfs-zln5lm9w
257 03:32:22.746017 extracting modules file /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964641/extract-overlay-ramdisk-ojf2rlrh/ramdisk
258 03:32:24.219213 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 03:32:24.219714 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
260 03:32:24.220025 [common] Applying overlay to NFS
261 03:32:24.220249 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964641/compress-overlay-uxdq1sft/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/964641/extract-nfsrootfs-zln5lm9w
262 03:32:26.961063 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 03:32:26.961533 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 03:32:26.961808 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 03:32:26.962040 Converting downloaded kernel to a uImage
266 03:32:26.962354 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/kernel/Image /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/kernel/uImage
267 03:32:27.517818 output: Image Name:
268 03:32:27.518249 output: Created: Sat Nov 9 03:32:26 2024
269 03:32:27.518464 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 03:32:27.518673 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 03:32:27.518877 output: Load Address: 01080000
272 03:32:27.519080 output: Entry Point: 01080000
273 03:32:27.519281 output:
274 03:32:27.519620 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 03:32:27.519891 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 03:32:27.520209 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 03:32:27.520470 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 03:32:27.520732 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 03:32:27.521000 Building ramdisk /var/lib/lava/dispatcher/tmp/964641/extract-overlay-ramdisk-ojf2rlrh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/964641/extract-overlay-ramdisk-ojf2rlrh/ramdisk
280 03:32:29.699041 >> 166792 blocks
281 03:32:37.495860 Adding RAMdisk u-boot header.
282 03:32:37.496591 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/964641/extract-overlay-ramdisk-ojf2rlrh/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/964641/extract-overlay-ramdisk-ojf2rlrh/ramdisk.cpio.gz.uboot
283 03:32:37.761197 output: Image Name:
284 03:32:37.761614 output: Created: Sat Nov 9 03:32:37 2024
285 03:32:37.762089 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 03:32:37.762559 output: Data Size: 23432134 Bytes = 22882.94 KiB = 22.35 MiB
287 03:32:37.763014 output: Load Address: 00000000
288 03:32:37.763461 output: Entry Point: 00000000
289 03:32:37.763911 output:
290 03:32:37.765199 rename /var/lib/lava/dispatcher/tmp/964641/extract-overlay-ramdisk-ojf2rlrh/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/ramdisk/ramdisk.cpio.gz.uboot
291 03:32:37.765996 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 03:32:37.766613 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 03:32:37.767213 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 03:32:37.767728 No LXC device requested
295 03:32:37.768352 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 03:32:37.768942 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 03:32:37.769504 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 03:32:37.769968 Checking files for TFTP limit of 4294967296 bytes.
299 03:32:37.772966 end: 1 tftp-deploy (duration 00:01:18) [common]
300 03:32:37.773602 start: 2 uboot-action (timeout 00:05:00) [common]
301 03:32:37.774198 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 03:32:37.774763 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 03:32:37.775336 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 03:32:37.775930 Using kernel file from prepare-kernel: 964641/tftp-deploy-ard2i2kr/kernel/uImage
305 03:32:37.776680 substitutions:
306 03:32:37.777146 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 03:32:37.777604 - {DTB_ADDR}: 0x01070000
308 03:32:37.778058 - {DTB}: 964641/tftp-deploy-ard2i2kr/dtb/meson-g12b-a311d-libretech-cc.dtb
309 03:32:37.778516 - {INITRD}: 964641/tftp-deploy-ard2i2kr/ramdisk/ramdisk.cpio.gz.uboot
310 03:32:37.778965 - {KERNEL_ADDR}: 0x01080000
311 03:32:37.779410 - {KERNEL}: 964641/tftp-deploy-ard2i2kr/kernel/uImage
312 03:32:37.779852 - {LAVA_MAC}: None
313 03:32:37.780386 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/964641/extract-nfsrootfs-zln5lm9w
314 03:32:37.780844 - {NFS_SERVER_IP}: 192.168.6.2
315 03:32:37.781286 - {PRESEED_CONFIG}: None
316 03:32:37.781729 - {PRESEED_LOCAL}: None
317 03:32:37.782171 - {RAMDISK_ADDR}: 0x08000000
318 03:32:37.782612 - {RAMDISK}: 964641/tftp-deploy-ard2i2kr/ramdisk/ramdisk.cpio.gz.uboot
319 03:32:37.783055 - {ROOT_PART}: None
320 03:32:37.783494 - {ROOT}: None
321 03:32:37.783931 - {SERVER_IP}: 192.168.6.2
322 03:32:37.784596 - {TEE_ADDR}: 0x83000000
323 03:32:37.785028 - {TEE}: None
324 03:32:37.785436 Parsed boot commands:
325 03:32:37.785828 - setenv autoload no
326 03:32:37.786227 - setenv initrd_high 0xffffffff
327 03:32:37.786621 - setenv fdt_high 0xffffffff
328 03:32:37.787014 - dhcp
329 03:32:37.787404 - setenv serverip 192.168.6.2
330 03:32:37.787796 - tftpboot 0x01080000 964641/tftp-deploy-ard2i2kr/kernel/uImage
331 03:32:37.788291 - tftpboot 0x08000000 964641/tftp-deploy-ard2i2kr/ramdisk/ramdisk.cpio.gz.uboot
332 03:32:37.788696 - tftpboot 0x01070000 964641/tftp-deploy-ard2i2kr/dtb/meson-g12b-a311d-libretech-cc.dtb
333 03:32:37.789094 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/964641/extract-nfsrootfs-zln5lm9w,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 03:32:37.789501 - bootm 0x01080000 0x08000000 0x01070000
335 03:32:37.790010 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 03:32:37.791499 start: 2.3 connect-device (timeout 00:05:00) [common]
338 03:32:37.791922 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 03:32:37.806875 Setting prompt string to ['lava-test: # ']
340 03:32:37.808439 end: 2.3 connect-device (duration 00:00:00) [common]
341 03:32:37.809078 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 03:32:37.809640 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 03:32:37.810184 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 03:32:37.811503 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 03:32:37.848567 >> OK - accepted request
346 03:32:37.850738 Returned 0 in 0 seconds
347 03:32:37.951846 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 03:32:37.953486 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 03:32:37.954033 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 03:32:37.954540 Setting prompt string to ['Hit any key to stop autoboot']
352 03:32:37.954991 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 03:32:37.956541 Trying 192.168.56.21...
354 03:32:37.957053 Connected to conserv1.
355 03:32:37.957464 Escape character is '^]'.
356 03:32:37.957877
357 03:32:37.958294 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 03:32:37.958721
359 03:32:48.802993 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 03:32:48.803593 bl2_stage_init 0x01
361 03:32:48.804050 bl2_stage_init 0x81
362 03:32:48.808624 hw id: 0x0000 - pwm id 0x01
363 03:32:48.809070 bl2_stage_init 0xc1
364 03:32:48.809497 bl2_stage_init 0x02
365 03:32:48.809907
366 03:32:48.814233 L0:00000000
367 03:32:48.814695 L1:20000703
368 03:32:48.815111 L2:00008067
369 03:32:48.815515 L3:14000000
370 03:32:48.817163 B2:00402000
371 03:32:48.817604 B1:e0f83180
372 03:32:48.818009
373 03:32:48.818401 TE: 58124
374 03:32:48.818792
375 03:32:48.828459 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 03:32:48.828887
377 03:32:48.829278 Board ID = 1
378 03:32:48.829665 Set A53 clk to 24M
379 03:32:48.830050 Set A73 clk to 24M
380 03:32:48.833968 Set clk81 to 24M
381 03:32:48.834386 A53 clk: 1200 MHz
382 03:32:48.834776 A73 clk: 1200 MHz
383 03:32:48.839624 CLK81: 166.6M
384 03:32:48.840075 smccc: 00012a91
385 03:32:48.844989 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 03:32:48.845411 board id: 1
387 03:32:48.853539 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 03:32:48.864215 fw parse done
389 03:32:48.870165 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 03:32:48.912815 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 03:32:48.923677 PIEI prepare done
392 03:32:48.924145 fastboot data load
393 03:32:48.924540 fastboot data verify
394 03:32:48.929363 verify result: 266
395 03:32:48.934953 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 03:32:48.935397 LPDDR4 probe
397 03:32:48.935813 ddr clk to 1584MHz
398 03:32:48.942945 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 03:32:48.980193
400 03:32:48.980633 dmc_version 0001
401 03:32:48.986874 Check phy result
402 03:32:48.992742 INFO : End of CA training
403 03:32:48.993174 INFO : End of initialization
404 03:32:48.998275 INFO : Training has run successfully!
405 03:32:48.998703 Check phy result
406 03:32:49.003927 INFO : End of initialization
407 03:32:49.004395 INFO : End of read enable training
408 03:32:49.007311 INFO : End of fine write leveling
409 03:32:49.012833 INFO : End of Write leveling coarse delay
410 03:32:49.018509 INFO : Training has run successfully!
411 03:32:49.018945 Check phy result
412 03:32:49.019361 INFO : End of initialization
413 03:32:49.024195 INFO : End of read dq deskew training
414 03:32:49.029701 INFO : End of MPR read delay center optimization
415 03:32:49.030137 INFO : End of write delay center optimization
416 03:32:49.035305 INFO : End of read delay center optimization
417 03:32:49.040860 INFO : End of max read latency training
418 03:32:49.041298 INFO : Training has run successfully!
419 03:32:49.046604 1D training succeed
420 03:32:49.052417 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 03:32:49.099917 Check phy result
422 03:32:49.100383 INFO : End of initialization
423 03:32:49.121692 INFO : End of 2D read delay Voltage center optimization
424 03:32:49.141944 INFO : End of 2D read delay Voltage center optimization
425 03:32:49.194051 INFO : End of 2D write delay Voltage center optimization
426 03:32:49.243450 INFO : End of 2D write delay Voltage center optimization
427 03:32:49.249003 INFO : Training has run successfully!
428 03:32:49.249447
429 03:32:49.249863 channel==0
430 03:32:49.254655 RxClkDly_Margin_A0==88 ps 9
431 03:32:49.255085 TxDqDly_Margin_A0==98 ps 10
432 03:32:49.260236 RxClkDly_Margin_A1==88 ps 9
433 03:32:49.260661 TxDqDly_Margin_A1==98 ps 10
434 03:32:49.261072 TrainedVREFDQ_A0==74
435 03:32:49.265767 TrainedVREFDQ_A1==74
436 03:32:49.266200 VrefDac_Margin_A0==25
437 03:32:49.266606 DeviceVref_Margin_A0==40
438 03:32:49.271415 VrefDac_Margin_A1==25
439 03:32:49.271842 DeviceVref_Margin_A1==40
440 03:32:49.272313
441 03:32:49.272725
442 03:32:49.276934 channel==1
443 03:32:49.277361 RxClkDly_Margin_A0==98 ps 10
444 03:32:49.277769 TxDqDly_Margin_A0==98 ps 10
445 03:32:49.285048 RxClkDly_Margin_A1==88 ps 9
446 03:32:49.285488 TxDqDly_Margin_A1==98 ps 10
447 03:32:49.288835 TrainedVREFDQ_A0==77
448 03:32:49.289266 TrainedVREFDQ_A1==78
449 03:32:49.289675 VrefDac_Margin_A0==22
450 03:32:49.293725 DeviceVref_Margin_A0==37
451 03:32:49.294161 VrefDac_Margin_A1==24
452 03:32:49.299373 DeviceVref_Margin_A1==36
453 03:32:49.299802
454 03:32:49.300256 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 03:32:49.304863
456 03:32:49.333169 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 03:32:49.333674 2D training succeed
458 03:32:49.338839 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 03:32:49.344398 auto size-- 65535DDR cs0 size: 2048MB
460 03:32:49.344827 DDR cs1 size: 2048MB
461 03:32:49.349875 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 03:32:49.350311 cs0 DataBus test pass
463 03:32:49.355530 cs1 DataBus test pass
464 03:32:49.355960 cs0 AddrBus test pass
465 03:32:49.356398 cs1 AddrBus test pass
466 03:32:49.356802
467 03:32:49.361060 100bdlr_step_size ps== 420
468 03:32:49.361497 result report
469 03:32:49.366677 boot times 0Enable ddr reg access
470 03:32:49.371923 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 03:32:49.385400 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 03:32:49.958266 0.0;M3 CHK:0;cm4_sp_mode 0
473 03:32:49.958854 MVN_1=0x00000000
474 03:32:49.963764 MVN_2=0x00000000
475 03:32:49.969640 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 03:32:49.970126 OPS=0x10
477 03:32:49.970556 ring efuse init
478 03:32:49.970966 chipver efuse init
479 03:32:49.975097 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 03:32:49.980752 [0.018961 Inits done]
481 03:32:49.981191 secure task start!
482 03:32:49.981606 high task start!
483 03:32:49.985305 low task start!
484 03:32:49.985739 run into bl31
485 03:32:49.991952 NOTICE: BL31: v1.3(release):4fc40b1
486 03:32:49.999913 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 03:32:50.000432 NOTICE: BL31: G12A normal boot!
488 03:32:50.025249 NOTICE: BL31: BL33 decompress pass
489 03:32:50.030881 ERROR: Error initializing runtime service opteed_fast
490 03:32:51.263863
491 03:32:51.264532
492 03:32:51.272108 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 03:32:51.272560
494 03:32:51.272979 Model: Libre Computer AML-A311D-CC Alta
495 03:32:51.480629 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 03:32:51.503943 DRAM: 2 GiB (effective 3.8 GiB)
497 03:32:51.646911 Core: 408 devices, 31 uclasses, devicetree: separate
498 03:32:51.652027 WDT: Not starting watchdog@f0d0
499 03:32:51.685030 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 03:32:51.697557 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 03:32:51.702473 ** Bad device specification mmc 0 **
502 03:32:51.712802 Card did not respond to voltage select! : -110
503 03:32:51.720510 ** Bad device specification mmc 0 **
504 03:32:51.720951 Couldn't find partition mmc 0
505 03:32:51.728818 Card did not respond to voltage select! : -110
506 03:32:51.734326 ** Bad device specification mmc 0 **
507 03:32:51.734763 Couldn't find partition mmc 0
508 03:32:51.739383 Error: could not access storage.
509 03:32:53.003401 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 03:32:53.004064 bl2_stage_init 0x01
511 03:32:53.004544 bl2_stage_init 0x81
512 03:32:53.008991 hw id: 0x0000 - pwm id 0x01
513 03:32:53.009436 bl2_stage_init 0xc1
514 03:32:53.009852 bl2_stage_init 0x02
515 03:32:53.010259
516 03:32:53.014576 L0:00000000
517 03:32:53.015010 L1:20000703
518 03:32:53.015418 L2:00008067
519 03:32:53.015823 L3:14000000
520 03:32:53.017450 B2:00402000
521 03:32:53.017910 B1:e0f83180
522 03:32:53.018321
523 03:32:53.018969 TE: 58124
524 03:32:53.019399
525 03:32:53.028640 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 03:32:53.029115
527 03:32:53.029534 Board ID = 1
528 03:32:53.029937 Set A53 clk to 24M
529 03:32:53.030338 Set A73 clk to 24M
530 03:32:53.034299 Set clk81 to 24M
531 03:32:53.034739 A53 clk: 1200 MHz
532 03:32:53.035147 A73 clk: 1200 MHz
533 03:32:53.040023 CLK81: 166.6M
534 03:32:53.040458 smccc: 00012a91
535 03:32:53.045434 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 03:32:53.045878 board id: 1
537 03:32:53.054104 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 03:32:53.064782 fw parse done
539 03:32:53.070950 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 03:32:53.113285 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 03:32:53.124265 PIEI prepare done
542 03:32:53.124766 fastboot data load
543 03:32:53.125188 fastboot data verify
544 03:32:53.129888 verify result: 266
545 03:32:53.135429 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 03:32:53.135914 LPDDR4 probe
547 03:32:53.136373 ddr clk to 1584MHz
548 03:32:53.143396 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 03:32:53.180667
550 03:32:53.181230 dmc_version 0001
551 03:32:53.187365 Check phy result
552 03:32:53.193445 INFO : End of CA training
553 03:32:53.194014 INFO : End of initialization
554 03:32:53.198981 INFO : Training has run successfully!
555 03:32:53.199525 Check phy result
556 03:32:53.204463 INFO : End of initialization
557 03:32:53.204965 INFO : End of read enable training
558 03:32:53.207738 INFO : End of fine write leveling
559 03:32:53.213337 INFO : End of Write leveling coarse delay
560 03:32:53.218915 INFO : Training has run successfully!
561 03:32:53.219398 Check phy result
562 03:32:53.219811 INFO : End of initialization
563 03:32:53.224511 INFO : End of read dq deskew training
564 03:32:53.230166 INFO : End of MPR read delay center optimization
565 03:32:53.230762 INFO : End of write delay center optimization
566 03:32:53.235713 INFO : End of read delay center optimization
567 03:32:53.241503 INFO : End of max read latency training
568 03:32:53.242214 INFO : Training has run successfully!
569 03:32:53.247157 1D training succeed
570 03:32:53.260079 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 03:32:53.300515 Check phy result
572 03:32:53.301126 INFO : End of initialization
573 03:32:53.322039 INFO : End of 2D read delay Voltage center optimization
574 03:32:53.342642 INFO : End of 2D read delay Voltage center optimization
575 03:32:53.394130 INFO : End of 2D write delay Voltage center optimization
576 03:32:53.443433 INFO : End of 2D write delay Voltage center optimization
577 03:32:53.449037 INFO : Training has run successfully!
578 03:32:53.449432
579 03:32:53.449647 channel==0
580 03:32:53.454516 RxClkDly_Margin_A0==78 ps 8
581 03:32:53.454877 TxDqDly_Margin_A0==98 ps 10
582 03:32:53.460290 RxClkDly_Margin_A1==88 ps 9
583 03:32:53.460644 TxDqDly_Margin_A1==98 ps 10
584 03:32:53.460857 TrainedVREFDQ_A0==74
585 03:32:53.465869 TrainedVREFDQ_A1==76
586 03:32:53.466467 VrefDac_Margin_A0==25
587 03:32:53.466913 DeviceVref_Margin_A0==40
588 03:32:53.471439 VrefDac_Margin_A1==25
589 03:32:53.472059 DeviceVref_Margin_A1==38
590 03:32:53.472476
591 03:32:53.472884
592 03:32:53.477008 channel==1
593 03:32:53.477455 RxClkDly_Margin_A0==98 ps 10
594 03:32:53.477706 TxDqDly_Margin_A0==88 ps 9
595 03:32:53.482662 RxClkDly_Margin_A1==88 ps 9
596 03:32:53.483257 TxDqDly_Margin_A1==88 ps 9
597 03:32:53.488292 TrainedVREFDQ_A0==76
598 03:32:53.488842 TrainedVREFDQ_A1==77
599 03:32:53.489257 VrefDac_Margin_A0==22
600 03:32:53.493836 DeviceVref_Margin_A0==38
601 03:32:53.494995 VrefDac_Margin_A1==24
602 03:32:53.499283 DeviceVref_Margin_A1==37
603 03:32:53.499653
604 03:32:53.499865 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 03:32:53.500257
606 03:32:53.534452 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 03:32:53.534901 2D training succeed
608 03:32:53.539456 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 03:32:53.544340 auto size-- 65535DDR cs0 size: 2048MB
610 03:32:53.544954 DDR cs1 size: 2048MB
611 03:32:53.550843 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 03:32:53.551465 cs0 DataBus test pass
613 03:32:53.555344 cs1 DataBus test pass
614 03:32:53.555905 cs0 AddrBus test pass
615 03:32:53.556397 cs1 AddrBus test pass
616 03:32:53.556845
617 03:32:53.561263 100bdlr_step_size ps== 420
618 03:32:53.561892 result report
619 03:32:53.566884 boot times 0Enable ddr reg access
620 03:32:53.571911 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 03:32:53.588469 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 03:32:54.157271 0.0;M3 CHK:0;cm4_sp_mode 0
623 03:32:54.157964 MVN_1=0x00000000
624 03:32:54.162679 MVN_2=0x00000000
625 03:32:54.168463 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 03:32:54.168981 OPS=0x10
627 03:32:54.169431 ring efuse init
628 03:32:54.169868 chipver efuse init
629 03:32:54.176712 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 03:32:54.177246 [0.018961 Inits done]
631 03:32:54.177685 secure task start!
632 03:32:54.184278 high task start!
633 03:32:54.184792 low task start!
634 03:32:54.185231 run into bl31
635 03:32:54.190858 NOTICE: BL31: v1.3(release):4fc40b1
636 03:32:54.198649 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 03:32:54.199159 NOTICE: BL31: G12A normal boot!
638 03:32:54.224119 NOTICE: BL31: BL33 decompress pass
639 03:32:54.229762 ERROR: Error initializing runtime service opteed_fast
640 03:32:55.462885
641 03:32:55.463558
642 03:32:55.471219 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 03:32:55.471739
644 03:32:55.472231 Model: Libre Computer AML-A311D-CC Alta
645 03:32:55.679449 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 03:32:55.702981 DRAM: 2 GiB (effective 3.8 GiB)
647 03:32:55.845882 Core: 408 devices, 31 uclasses, devicetree: separate
648 03:32:55.851840 WDT: Not starting watchdog@f0d0
649 03:32:55.884173 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 03:32:55.896538 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 03:32:55.901705 ** Bad device specification mmc 0 **
652 03:32:55.911878 Card did not respond to voltage select! : -110
653 03:32:55.919810 ** Bad device specification mmc 0 **
654 03:32:55.920343 Couldn't find partition mmc 0
655 03:32:55.927903 Card did not respond to voltage select! : -110
656 03:32:55.933320 ** Bad device specification mmc 0 **
657 03:32:55.933827 Couldn't find partition mmc 0
658 03:32:55.938417 Error: could not access storage.
659 03:32:56.282006 Net: eth0: ethernet@ff3f0000
660 03:32:56.282564 starting USB...
661 03:32:56.533774 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 03:32:56.534355 Starting the controller
663 03:32:56.540790 USB XHCI 1.10
664 03:32:58.252111 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 03:32:58.252771 bl2_stage_init 0x01
666 03:32:58.253251 bl2_stage_init 0x81
667 03:32:58.257905 hw id: 0x0000 - pwm id 0x01
668 03:32:58.258416 bl2_stage_init 0xc1
669 03:32:58.258877 bl2_stage_init 0x02
670 03:32:58.259330
671 03:32:58.263437 L0:00000000
672 03:32:58.263940 L1:20000703
673 03:32:58.264440 L2:00008067
674 03:32:58.264892 L3:14000000
675 03:32:58.268999 B2:00402000
676 03:32:58.269502 B1:e0f83180
677 03:32:58.269959
678 03:32:58.270411 TE: 58159
679 03:32:58.270863
680 03:32:58.274618 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 03:32:58.275127
682 03:32:58.275586 Board ID = 1
683 03:32:58.280190 Set A53 clk to 24M
684 03:32:58.280694 Set A73 clk to 24M
685 03:32:58.281146 Set clk81 to 24M
686 03:32:58.285892 A53 clk: 1200 MHz
687 03:32:58.286390 A73 clk: 1200 MHz
688 03:32:58.286845 CLK81: 166.6M
689 03:32:58.287293 smccc: 00012ab5
690 03:32:58.291404 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 03:32:58.296974 board id: 1
692 03:32:58.303011 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 03:32:58.313483 fw parse done
694 03:32:58.319409 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 03:32:58.362006 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 03:32:58.372945 PIEI prepare done
697 03:32:58.373457 fastboot data load
698 03:32:58.373924 fastboot data verify
699 03:32:58.378658 verify result: 266
700 03:32:58.384226 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 03:32:58.384740 LPDDR4 probe
702 03:32:58.385200 ddr clk to 1584MHz
703 03:32:58.392199 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 03:32:58.429477
705 03:32:58.430015 dmc_version 0001
706 03:32:58.436197 Check phy result
707 03:32:58.442018 INFO : End of CA training
708 03:32:58.442512 INFO : End of initialization
709 03:32:58.447595 INFO : Training has run successfully!
710 03:32:58.448139 Check phy result
711 03:32:58.453221 INFO : End of initialization
712 03:32:58.453716 INFO : End of read enable training
713 03:32:58.458915 INFO : End of fine write leveling
714 03:32:58.464388 INFO : End of Write leveling coarse delay
715 03:32:58.464886 INFO : Training has run successfully!
716 03:32:58.465341 Check phy result
717 03:32:58.470041 INFO : End of initialization
718 03:32:58.470537 INFO : End of read dq deskew training
719 03:32:58.475678 INFO : End of MPR read delay center optimization
720 03:32:58.481120 INFO : End of write delay center optimization
721 03:32:58.486882 INFO : End of read delay center optimization
722 03:32:58.487377 INFO : End of max read latency training
723 03:32:58.492407 INFO : Training has run successfully!
724 03:32:58.492908 1D training succeed
725 03:32:58.501588 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 03:32:58.549204 Check phy result
727 03:32:58.549754 INFO : End of initialization
728 03:32:58.571795 INFO : End of 2D read delay Voltage center optimization
729 03:32:58.592032 INFO : End of 2D read delay Voltage center optimization
730 03:32:58.644144 INFO : End of 2D write delay Voltage center optimization
731 03:32:58.693499 INFO : End of 2D write delay Voltage center optimization
732 03:32:58.698984 INFO : Training has run successfully!
733 03:32:58.699490
734 03:32:58.699949 channel==0
735 03:32:58.704639 RxClkDly_Margin_A0==88 ps 9
736 03:32:58.705141 TxDqDly_Margin_A0==98 ps 10
737 03:32:58.707969 RxClkDly_Margin_A1==88 ps 9
738 03:32:58.708502 TxDqDly_Margin_A1==98 ps 10
739 03:32:58.713405 TrainedVREFDQ_A0==74
740 03:32:58.713904 TrainedVREFDQ_A1==74
741 03:32:58.719015 VrefDac_Margin_A0==24
742 03:32:58.719512 DeviceVref_Margin_A0==40
743 03:32:58.719967 VrefDac_Margin_A1==25
744 03:32:58.724691 DeviceVref_Margin_A1==40
745 03:32:58.725189
746 03:32:58.725648
747 03:32:58.726097 channel==1
748 03:32:58.726537 RxClkDly_Margin_A0==98 ps 10
749 03:32:58.730273 TxDqDly_Margin_A0==98 ps 10
750 03:32:58.730776 RxClkDly_Margin_A1==98 ps 10
751 03:32:58.736024 TxDqDly_Margin_A1==88 ps 9
752 03:32:58.736545 TrainedVREFDQ_A0==77
753 03:32:58.737002 TrainedVREFDQ_A1==77
754 03:32:58.741412 VrefDac_Margin_A0==22
755 03:32:58.741907 DeviceVref_Margin_A0==37
756 03:32:58.747027 VrefDac_Margin_A1==22
757 03:32:58.747520 DeviceVref_Margin_A1==37
758 03:32:58.747974
759 03:32:58.752635 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 03:32:58.753090
761 03:32:58.780546 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
762 03:32:58.786176 2D training succeed
763 03:32:58.791750 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 03:32:58.792218 auto size-- 65535DDR cs0 size: 2048MB
765 03:32:58.797335 DDR cs1 size: 2048MB
766 03:32:58.797767 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 03:32:58.802906 cs0 DataBus test pass
768 03:32:58.803331 cs1 DataBus test pass
769 03:32:58.803728 cs0 AddrBus test pass
770 03:32:58.808569 cs1 AddrBus test pass
771 03:32:58.808994
772 03:32:58.809390 100bdlr_step_size ps== 420
773 03:32:58.809794 result report
774 03:32:58.814196 boot times 0Enable ddr reg access
775 03:32:58.821994 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 03:32:58.834493 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 03:32:59.408674 0.0;M3 CHK:0;cm4_sp_mode 0
778 03:32:59.409324 MVN_1=0x00000000
779 03:32:59.414153 MVN_2=0x00000000
780 03:32:59.419761 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 03:32:59.420336 OPS=0x10
782 03:32:59.420747 ring efuse init
783 03:32:59.421142 chipver efuse init
784 03:32:59.427969 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 03:32:59.428457 [0.018961 Inits done]
786 03:32:59.428856 secure task start!
787 03:32:59.435527 high task start!
788 03:32:59.435964 low task start!
789 03:32:59.436386 run into bl31
790 03:32:59.442098 NOTICE: BL31: v1.3(release):4fc40b1
791 03:32:59.450120 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 03:32:59.450567 NOTICE: BL31: G12A normal boot!
793 03:32:59.476109 NOTICE: BL31: BL33 decompress pass
794 03:32:59.481607 ERROR: Error initializing runtime service opteed_fast
795 03:33:00.714633
796 03:33:00.715226
797 03:33:00.722928 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 03:33:00.723418
799 03:33:00.723842 Model: Libre Computer AML-A311D-CC Alta
800 03:33:00.931507 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 03:33:00.954661 DRAM: 2 GiB (effective 3.8 GiB)
802 03:33:01.097982 Core: 408 devices, 31 uclasses, devicetree: separate
803 03:33:01.103656 WDT: Not starting watchdog@f0d0
804 03:33:01.135826 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 03:33:01.148284 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 03:33:01.153330 ** Bad device specification mmc 0 **
807 03:33:01.163714 Card did not respond to voltage select! : -110
808 03:33:01.171331 ** Bad device specification mmc 0 **
809 03:33:01.171792 Couldn't find partition mmc 0
810 03:33:01.179547 Card did not respond to voltage select! : -110
811 03:33:01.185000 ** Bad device specification mmc 0 **
812 03:33:01.185465 Couldn't find partition mmc 0
813 03:33:01.190066 Error: could not access storage.
814 03:33:01.533823 Net: eth0: ethernet@ff3f0000
815 03:33:01.534799 starting USB...
816 03:33:01.785571 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 03:33:01.786197 Starting the controller
818 03:33:01.792464 USB XHCI 1.10
819 03:33:03.952491 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 03:33:03.953081 bl2_stage_init 0x01
821 03:33:03.953515 bl2_stage_init 0x81
822 03:33:03.958026 hw id: 0x0000 - pwm id 0x01
823 03:33:03.958483 bl2_stage_init 0xc1
824 03:33:03.958896 bl2_stage_init 0x02
825 03:33:03.959299
826 03:33:03.963643 L0:00000000
827 03:33:03.964122 L1:20000703
828 03:33:03.964535 L2:00008067
829 03:33:03.964945 L3:14000000
830 03:33:03.966728 B2:00402000
831 03:33:03.967173 B1:e0f83180
832 03:33:03.967580
833 03:33:03.968021 TE: 58159
834 03:33:03.968440
835 03:33:03.977757 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 03:33:03.978211
837 03:33:03.978623 Board ID = 1
838 03:33:03.979030 Set A53 clk to 24M
839 03:33:03.979428 Set A73 clk to 24M
840 03:33:03.983368 Set clk81 to 24M
841 03:33:03.983815 A53 clk: 1200 MHz
842 03:33:03.984264 A73 clk: 1200 MHz
843 03:33:03.986912 CLK81: 166.6M
844 03:33:03.987353 smccc: 00012ab5
845 03:33:03.992447 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 03:33:03.998046 board id: 1
847 03:33:04.003114 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 03:33:04.013766 fw parse done
849 03:33:04.019677 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 03:33:04.062370 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 03:33:04.073442 PIEI prepare done
852 03:33:04.073909 fastboot data load
853 03:33:04.074328 fastboot data verify
854 03:33:04.078909 verify result: 266
855 03:33:04.084658 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 03:33:04.085119 LPDDR4 probe
857 03:33:04.085528 ddr clk to 1584MHz
858 03:33:04.092442 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 03:33:04.129096
860 03:33:04.129641 dmc_version 0001
861 03:33:04.135675 Check phy result
862 03:33:04.142374 INFO : End of CA training
863 03:33:04.142837 INFO : End of initialization
864 03:33:04.148023 INFO : Training has run successfully!
865 03:33:04.148487 Check phy result
866 03:33:04.153590 INFO : End of initialization
867 03:33:04.154048 INFO : End of read enable training
868 03:33:04.159145 INFO : End of fine write leveling
869 03:33:04.164711 INFO : End of Write leveling coarse delay
870 03:33:04.165186 INFO : Training has run successfully!
871 03:33:04.165607 Check phy result
872 03:33:04.170439 INFO : End of initialization
873 03:33:04.170911 INFO : End of read dq deskew training
874 03:33:04.176035 INFO : End of MPR read delay center optimization
875 03:33:04.181598 INFO : End of write delay center optimization
876 03:33:04.187200 INFO : End of read delay center optimization
877 03:33:04.187674 INFO : End of max read latency training
878 03:33:04.192728 INFO : Training has run successfully!
879 03:33:04.193196 1D training succeed
880 03:33:04.201934 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 03:33:04.249558 Check phy result
882 03:33:04.250052 INFO : End of initialization
883 03:33:04.271146 INFO : End of 2D read delay Voltage center optimization
884 03:33:04.291218 INFO : End of 2D read delay Voltage center optimization
885 03:33:04.343345 INFO : End of 2D write delay Voltage center optimization
886 03:33:04.392497 INFO : End of 2D write delay Voltage center optimization
887 03:33:04.398006 INFO : Training has run successfully!
888 03:33:04.398473
889 03:33:04.398887 channel==0
890 03:33:04.403676 RxClkDly_Margin_A0==88 ps 9
891 03:33:04.404185 TxDqDly_Margin_A0==98 ps 10
892 03:33:04.407002 RxClkDly_Margin_A1==88 ps 9
893 03:33:04.407459 TxDqDly_Margin_A1==88 ps 9
894 03:33:04.412538 TrainedVREFDQ_A0==74
895 03:33:04.413013 TrainedVREFDQ_A1==74
896 03:33:04.413444 VrefDac_Margin_A0==25
897 03:33:04.418226 DeviceVref_Margin_A0==40
898 03:33:04.418726 VrefDac_Margin_A1==26
899 03:33:04.423757 DeviceVref_Margin_A1==40
900 03:33:04.424263
901 03:33:04.424657
902 03:33:04.425044 channel==1
903 03:33:04.425427 RxClkDly_Margin_A0==98 ps 10
904 03:33:04.427174 TxDqDly_Margin_A0==98 ps 10
905 03:33:04.432746 RxClkDly_Margin_A1==98 ps 10
906 03:33:04.433197 TxDqDly_Margin_A1==88 ps 9
907 03:33:04.433589 TrainedVREFDQ_A0==77
908 03:33:04.438328 TrainedVREFDQ_A1==77
909 03:33:04.438776 VrefDac_Margin_A0==22
910 03:33:04.443893 DeviceVref_Margin_A0==37
911 03:33:04.444375 VrefDac_Margin_A1==22
912 03:33:04.444761 DeviceVref_Margin_A1==37
913 03:33:04.445144
914 03:33:04.449521 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 03:33:04.449983
916 03:33:04.483104 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
917 03:33:04.483590 2D training succeed
918 03:33:04.488776 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 03:33:04.494237 auto size-- 65535DDR cs0 size: 2048MB
920 03:33:04.494707 DDR cs1 size: 2048MB
921 03:33:04.499939 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 03:33:04.500445 cs0 DataBus test pass
923 03:33:04.500836 cs1 DataBus test pass
924 03:33:04.505512 cs0 AddrBus test pass
925 03:33:04.505995 cs1 AddrBus test pass
926 03:33:04.506405
927 03:33:04.511123 100bdlr_step_size ps== 420
928 03:33:04.511608 result report
929 03:33:04.512038 boot times 0Enable ddr reg access
930 03:33:04.520799 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 03:33:04.534310 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 03:33:05.106266 0.0;M3 CHK:0;cm4_sp_mode 0
933 03:33:05.106860 MVN_1=0x00000000
934 03:33:05.111755 MVN_2=0x00000000
935 03:33:05.117475 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 03:33:05.117926 OPS=0x10
937 03:33:05.118335 ring efuse init
938 03:33:05.118733 chipver efuse init
939 03:33:05.123106 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 03:33:05.128725 [0.018961 Inits done]
941 03:33:05.129179 secure task start!
942 03:33:05.129589 high task start!
943 03:33:05.133258 low task start!
944 03:33:05.133701 run into bl31
945 03:33:05.139969 NOTICE: BL31: v1.3(release):4fc40b1
946 03:33:05.147731 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 03:33:05.148214 NOTICE: BL31: G12A normal boot!
948 03:33:05.173208 NOTICE: BL31: BL33 decompress pass
949 03:33:05.178868 ERROR: Error initializing runtime service opteed_fast
950 03:33:06.411820
951 03:33:06.412496
952 03:33:06.420223 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 03:33:06.420759
954 03:33:06.421181 Model: Libre Computer AML-A311D-CC Alta
955 03:33:06.628601 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 03:33:06.652023 DRAM: 2 GiB (effective 3.8 GiB)
957 03:33:06.794958 Core: 408 devices, 31 uclasses, devicetree: separate
958 03:33:06.800985 WDT: Not starting watchdog@f0d0
959 03:33:06.833096 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 03:33:06.845566 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 03:33:06.850566 ** Bad device specification mmc 0 **
962 03:33:06.860912 Card did not respond to voltage select! : -110
963 03:33:06.868549 ** Bad device specification mmc 0 **
964 03:33:06.868995 Couldn't find partition mmc 0
965 03:33:06.876921 Card did not respond to voltage select! : -110
966 03:33:06.882413 ** Bad device specification mmc 0 **
967 03:33:06.882872 Couldn't find partition mmc 0
968 03:33:06.887478 Error: could not access storage.
969 03:33:07.229936 Net: eth0: ethernet@ff3f0000
970 03:33:07.230541 starting USB...
971 03:33:07.481767 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 03:33:07.482329 Starting the controller
973 03:33:07.488688 USB XHCI 1.10
974 03:33:09.042863 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 03:33:09.051086 scanning usb for storage devices... 0 Storage Device(s) found
977 03:33:09.102644 Hit any key to stop autoboot: 1
978 03:33:09.103707 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
979 03:33:09.104388 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
980 03:33:09.104879 Setting prompt string to ['=>']
981 03:33:09.105371 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
982 03:33:09.118614 0
983 03:33:09.119564 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 03:33:09.120101 Sending with 10 millisecond of delay
986 03:33:10.255063 => setenv autoload no
987 03:33:10.265857 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:28)
988 03:33:10.270789 setenv autoload no
989 03:33:10.271496 Sending with 10 millisecond of delay
991 03:33:12.068508 => setenv initrd_high 0xffffffff
992 03:33:12.079299 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
993 03:33:12.080226 setenv initrd_high 0xffffffff
994 03:33:12.080941 Sending with 10 millisecond of delay
996 03:33:13.697767 => setenv fdt_high 0xffffffff
997 03:33:13.708877 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
998 03:33:13.709805 setenv fdt_high 0xffffffff
999 03:33:13.710554 Sending with 10 millisecond of delay
1001 03:33:14.002492 => dhcp
1002 03:33:14.013326 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
1003 03:33:14.014221 dhcp
1004 03:33:14.014690 Speed: 1000, full duplex
1005 03:33:14.015130 BOOTP broadcast 1
1006 03:33:14.022361 DHCP client bound to address 192.168.6.27 (8 ms)
1007 03:33:14.023197 Sending with 10 millisecond of delay
1009 03:33:15.700009 => setenv serverip 192.168.6.2
1010 03:33:15.710877 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1011 03:33:15.711835 setenv serverip 192.168.6.2
1012 03:33:15.712634 Sending with 10 millisecond of delay
1014 03:33:19.437608 => tftpboot 0x01080000 964641/tftp-deploy-ard2i2kr/kernel/uImage
1015 03:33:19.448573 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1016 03:33:19.449517 tftpboot 0x01080000 964641/tftp-deploy-ard2i2kr/kernel/uImage
1017 03:33:19.450011 Speed: 1000, full duplex
1018 03:33:19.450474 Using ethernet@ff3f0000 device
1019 03:33:19.451248 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1020 03:33:19.456939 Filename '964641/tftp-deploy-ard2i2kr/kernel/uImage'.
1021 03:33:19.460790 Load address: 0x1080000
1022 03:33:22.327760 Loading: *################################################## 43.6 MiB
1023 03:33:22.328451 15.2 MiB/s
1024 03:33:22.328904 done
1025 03:33:22.332498 Bytes transferred = 45713984 (2b98a40 hex)
1026 03:33:22.333303 Sending with 10 millisecond of delay
1028 03:33:27.020129 => tftpboot 0x08000000 964641/tftp-deploy-ard2i2kr/ramdisk/ramdisk.cpio.gz.uboot
1029 03:33:27.031009 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1030 03:33:27.031968 tftpboot 0x08000000 964641/tftp-deploy-ard2i2kr/ramdisk/ramdisk.cpio.gz.uboot
1031 03:33:27.032526 Speed: 1000, full duplex
1032 03:33:27.032995 Using ethernet@ff3f0000 device
1033 03:33:27.034066 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1034 03:33:27.045827 Filename '964641/tftp-deploy-ard2i2kr/ramdisk/ramdisk.cpio.gz.uboot'.
1035 03:33:27.046386 Load address: 0x8000000
1036 03:33:33.837276 Loading: *###################T ############################### 22.3 MiB
1037 03:33:33.837948 3.3 MiB/s
1038 03:33:33.838421 done
1039 03:33:33.841837 Bytes transferred = 23432198 (1658c06 hex)
1040 03:33:33.842667 Sending with 10 millisecond of delay
1042 03:33:39.011051 => tftpboot 0x01070000 964641/tftp-deploy-ard2i2kr/dtb/meson-g12b-a311d-libretech-cc.dtb
1043 03:33:39.021867 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
1044 03:33:39.022777 tftpboot 0x01070000 964641/tftp-deploy-ard2i2kr/dtb/meson-g12b-a311d-libretech-cc.dtb
1045 03:33:39.023289 Speed: 1000, full duplex
1046 03:33:39.023752 Using ethernet@ff3f0000 device
1047 03:33:39.026930 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1048 03:33:39.035053 Filename '964641/tftp-deploy-ard2i2kr/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1049 03:33:39.047631 Load address: 0x1070000
1050 03:33:39.055389 Loading: *################################################## 53.4 KiB
1051 03:33:39.055932 3.1 MiB/s
1052 03:33:39.056440 done
1053 03:33:39.061781 Bytes transferred = 54703 (d5af hex)
1054 03:33:39.062584 Sending with 10 millisecond of delay
1056 03:33:52.359592 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/964641/extract-nfsrootfs-zln5lm9w,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1057 03:33:52.370555 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:45)
1058 03:33:52.371502 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/964641/extract-nfsrootfs-zln5lm9w,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1059 03:33:52.372304 Sending with 10 millisecond of delay
1061 03:33:54.711307 => bootm 0x01080000 0x08000000 0x01070000
1062 03:33:54.722178 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1063 03:33:54.722840 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:43)
1064 03:33:54.723955 bootm 0x01080000 0x08000000 0x01070000
1065 03:33:54.724493 ## Booting kernel from Legacy Image at 01080000 ...
1066 03:33:54.727447 Image Name:
1067 03:33:54.732973 Image Type: AArch64 Linux Kernel Image (uncompressed)
1068 03:33:54.733520 Data Size: 45713920 Bytes = 43.6 MiB
1069 03:33:54.738298 Load Address: 01080000
1070 03:33:54.738838 Entry Point: 01080000
1071 03:33:54.933703 Verifying Checksum ... OK
1072 03:33:54.934358 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1073 03:33:54.939098 Image Name:
1074 03:33:54.944540 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1075 03:33:54.945051 Data Size: 23432134 Bytes = 22.3 MiB
1076 03:33:54.946912 Load Address: 00000000
1077 03:33:54.954119 Entry Point: 00000000
1078 03:33:55.052397 Verifying Checksum ... OK
1079 03:33:55.053051 ## Flattened Device Tree blob at 01070000
1080 03:33:55.057821 Booting using the fdt blob at 0x1070000
1081 03:33:55.058358 Working FDT set to 1070000
1082 03:33:55.062261 Loading Kernel Image
1083 03:33:55.212971 Loading Ramdisk to 7e9a7000, end 7ffffbc6 ... OK
1084 03:33:55.221337 Loading Device Tree to 000000007e996000, end 000000007e9a65ae ... OK
1085 03:33:55.221877 Working FDT set to 7e996000
1086 03:33:55.222345
1087 03:33:55.223315 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1088 03:33:55.224021 start: 2.4.4 auto-login-action (timeout 00:03:43) [common]
1089 03:33:55.224608 Setting prompt string to ['Linux version [0-9]']
1090 03:33:55.225156 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1091 03:33:55.225682 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1092 03:33:55.226833 Starting kernel ...
1093 03:33:55.227349
1094 03:33:55.261590 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1095 03:33:55.262695 start: 2.4.4.1 login-action (timeout 00:03:43) [common]
1096 03:33:55.263273 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1097 03:33:55.263789 Setting prompt string to []
1098 03:33:55.264368 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1099 03:33:55.264880 Using line separator: #'\n'#
1100 03:33:55.265337 No login prompt set.
1101 03:33:55.265823 Parsing kernel messages
1102 03:33:55.266269 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1103 03:33:55.267352 [login-action] Waiting for messages, (timeout 00:03:43)
1104 03:33:55.267886 Waiting using forced prompt support (timeout 00:01:51)
1105 03:33:55.278108 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j370469-arm64-gcc-12-defconfig-2sk45) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Sat Nov 9 02:41:39 UTC 2024
1106 03:33:55.283669 [ 0.000000] KASLR disabled due to lack of seed
1107 03:33:55.289204 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1108 03:33:55.294630 [ 0.000000] efi: UEFI not found.
1109 03:33:55.300268 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1110 03:33:55.305676 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1111 03:33:55.316737 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1112 03:33:55.327701 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1113 03:33:55.333214 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1114 03:33:55.344217 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1115 03:33:55.355243 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1116 03:33:55.360826 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1117 03:33:55.366352 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1118 03:33:55.371842 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1119 03:33:55.372395 [ 0.000000] Zone ranges:
1120 03:33:55.377385 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1121 03:33:55.382918 [ 0.000000] DMA32 empty
1122 03:33:55.383451 [ 0.000000] Normal empty
1123 03:33:55.388469 [ 0.000000] Movable zone start for each node
1124 03:33:55.393940 [ 0.000000] Early memory node ranges
1125 03:33:55.399457 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1126 03:33:55.404966 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1127 03:33:55.410552 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1128 03:33:55.416084 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1129 03:33:55.443277 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1130 03:33:55.448857 [ 0.000000] psci: probing for conduit method from DT.
1131 03:33:55.449395 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1132 03:33:55.454371 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1133 03:33:55.459885 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1134 03:33:55.465392 [ 0.000000] psci: SMC Calling Convention v1.1
1135 03:33:55.470945 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1136 03:33:55.476428 [ 0.000000] Detected VIPT I-cache on CPU0
1137 03:33:55.481980 [ 0.000000] CPU features: detected: ARM erratum 845719
1138 03:33:55.487560 [ 0.000000] alternatives: applying boot alternatives
1139 03:33:55.504059 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/964641/extract-nfsrootfs-zln5lm9w,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1140 03:33:55.515054 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1141 03:33:55.521651 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1142 03:33:55.526148 <6>[ 0.000000] Fallback order for Node 0: 0
1143 03:33:55.532303 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1144 03:33:55.537215 <6>[ 0.000000] Policy zone: DMA
1145 03:33:55.542834 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1146 03:33:55.548279 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1147 03:33:55.553906 <6>[ 0.000000] software IO TLB: area num 8.
1148 03:33:55.562931 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1149 03:33:55.609354 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1150 03:33:55.614927 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1151 03:33:55.620435 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1152 03:33:55.625971 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1153 03:33:55.631460 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1154 03:33:55.636986 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1155 03:33:55.642492 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1156 03:33:55.647963 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1157 03:33:55.659014 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1158 03:33:55.670047 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1159 03:33:55.675633 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1160 03:33:55.681142 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1161 03:33:55.681662 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1162 03:33:55.690984 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1163 03:33:55.703675 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1164 03:33:55.714841 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1165 03:33:55.720273 <6>[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1166 03:33:55.725858 <6>[ 0.008797] Console: colour dummy device 80x25
1167 03:33:55.736776 <6>[ 0.012936] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1168 03:33:55.742296 <6>[ 0.023295] pid_max: default: 32768 minimum: 301
1169 03:33:55.747832 <6>[ 0.028189] LSM: initializing lsm=capability
1170 03:33:55.753368 <6>[ 0.032728] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1171 03:33:55.758883 <6>[ 0.040210] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1172 03:33:55.764381 <6>[ 0.052299] rcu: Hierarchical SRCU implementation.
1173 03:33:55.769926 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1174 03:33:55.780896 <6>[ 0.058879] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1175 03:33:55.789388 <6>[ 0.071595] EFI services will not be available.
1176 03:33:55.789915 <6>[ 0.075241] smp: Bringing up secondary CPUs ...
1177 03:33:55.801659 <6>[ 0.077136] Detected VIPT I-cache on CPU1
1178 03:33:56.096248 <6>[ 0.077258] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1179 03:33:56.096897 <6>[ 0.078592] CPU features: detected: Spectre-v2
1180 03:33:56.098036 <6>[ 0.078606] CPU features: detected: Spectre-v4
1181 03:33:56.098494 <6>[ 0.078612] CPU features: detected: Spectre-BHB
1182 03:33:56.098916 <6>[ 0.078617] CPU features: detected: ARM erratum 858921
1183 03:33:56.099337 <6>[ 0.078626] Detected VIPT I-cache on CPU2
1184 03:33:56.099754 <6>[ 0.078700] arch_timer: Enabling local workaround for ARM erratum 858921
1185 03:33:56.100219 <6>[ 0.078717] arch_timer: CPU2: Trapping CNTVCT access
1186 03:33:56.100634 <6>[ 0.078726] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1187 03:33:56.101044 <6>[ 0.083587] Detected VIPT I-cache on CPU3
1188 03:33:56.101450 <6>[ 0.083633] arch_timer: Enabling local workaround for ARM erratum 858921
1189 03:33:56.101855 <6>[ 0.083643] arch_timer: CPU3: Trapping CNTVCT access
1190 03:33:56.102257 <6>[ 0.083650] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1191 03:33:56.102660 <6>[ 0.087629] Detected VIPT I-cache on CPU4
1192 03:33:56.103060 <6>[ 0.087675] arch_timer: Enabling local workaround for ARM erratum 858921
1193 03:33:56.103458 <6>[ 0.087684] arch_timer: CPU4: Trapping CNTVCT access
1194 03:33:56.103854 <6>[ 0.087691] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1195 03:33:56.104291 <6>[ 0.091625] Detected VIPT I-cache on CPU5
1196 03:33:56.104695 <6>[ 0.091672] arch_timer: Enabling local workaround for ARM erratum 858921
1197 03:33:56.105096 <6>[ 0.091682] arch_timer: CPU5: Trapping CNTVCT access
1198 03:33:56.105493 <6>[ 0.091690] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1199 03:33:56.105890 <6>[ 0.091802] smp: Brought up 1 node, 6 CPUs
1200 03:33:56.106285 <6>[ 0.213029] SMP: Total of 6 processors activated.
1201 03:33:56.106682 <6>[ 0.217934] CPU: All CPU(s) started at EL2
1202 03:33:56.107079 <6>[ 0.222285] CPU features: detected: 32-bit EL0 Support
1203 03:33:56.107477 <6>[ 0.227595] CPU features: detected: 32-bit EL1 Support
1204 03:33:56.107871 <6>[ 0.232942] CPU features: detected: CRC32 instructions
1205 03:33:56.108298 <6>[ 0.238345] alternatives: applying system-wide alternatives
1206 03:33:56.108851 <6>[ 0.245525] Memory: 3557436K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187796K reserved, 262144K cma-reserved)
1207 03:33:56.109294 <6>[ 0.259872] devtmpfs: initialized
1208 03:33:56.109697 <6>[ 0.269047] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1209 03:33:56.110099 <6>[ 0.273402] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1210 03:33:56.110501 <6>[ 0.284199] 21392 pages in range for non-PLT usage
1211 03:33:56.110897 <6>[ 0.284209] 512912 pages in range for PLT usage
1212 03:33:56.111296 <6>[ 0.285755] pinctrl core: initialized pinctrl subsystem
1213 03:33:56.111695 <6>[ 0.297850] DMI not present or invalid.
1214 03:33:56.112121 <6>[ 0.302116] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1215 03:33:56.112526 <6>[ 0.306866] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1216 03:33:56.112925 <6>[ 0.313637] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1217 03:33:56.113324 <6>[ 0.321740] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1218 03:33:56.113721 <6>[ 0.329236] audit: initializing netlink subsys (disabled)
1219 03:33:56.114120 <5>[ 0.334976] audit: type=2000 audit(0.256:1): state=initialized audit_enabled=0 res=1
1220 03:33:56.114515 <6>[ 0.336471] thermal_sys: Registered thermal governor 'step_wise'
1221 03:33:56.114910 <6>[ 0.342737] thermal_sys: Registered thermal governor 'power_allocator'
1222 03:33:56.115306 <6>[ 0.349000] cpuidle: using governor menu
1223 03:33:56.115695 <6>[ 0.359980] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1224 03:33:56.116118 <6>[ 0.366916] ASID allocator initialised with 65536 entries
1225 03:33:56.116518 <6>[ 0.374428] Serial: AMBA PL011 UART driver
1226 03:33:56.116912 <6>[ 0.385011] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1227 03:33:56.385242 <6>[ 0.400527] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1228 03:33:56.385891 <6>[ 0.403191] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1229 03:33:56.386334 <6>[ 0.416344] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1230 03:33:56.386758 <6>[ 0.419570] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1231 03:33:56.387172 <6>[ 0.427994] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1232 03:33:56.387581 <6>[ 0.435619] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1233 03:33:56.388071 <6>[ 0.449203] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1234 03:33:56.388505 <6>[ 0.451438] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1235 03:33:56.388917 <6>[ 0.457918] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1236 03:33:56.389323 <6>[ 0.464896] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1237 03:33:56.389732 <6>[ 0.471366] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1238 03:33:56.390140 <6>[ 0.478351] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1239 03:33:56.390544 <6>[ 0.484820] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1240 03:33:56.390948 <6>[ 0.491805] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1241 03:33:56.391563 <6>[ 0.499799] ACPI: Interpreter disabled.
1242 03:33:56.392118 <6>[ 0.505306] iommu: Default domain type: Translated
1243 03:33:56.392554 <6>[ 0.507339] iommu: DMA domain TLB invalidation policy: strict mode
1244 03:33:56.392968 <5>[ 0.514022] SCSI subsystem initialized
1245 03:33:56.393375 <6>[ 0.517901] usbcore: registered new interface driver usbfs
1246 03:33:56.393777 <6>[ 0.523394] usbcore: registered new interface driver hub
1247 03:33:56.394181 <6>[ 0.528920] usbcore: registered new device driver usb
1248 03:33:56.394583 <6>[ 0.535186] pps_core: LinuxPPS API ver. 1 registered
1249 03:33:56.394988 <6>[ 0.539332] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1250 03:33:56.395392 <6>[ 0.548652] PTP clock support registered
1251 03:33:56.395791 <6>[ 0.552888] EDAC MC: Ver: 3.0.0
1252 03:33:56.396229 <6>[ 0.556531] scmi_core: SCMI protocol bus registered
1253 03:33:56.396639 <6>[ 0.562124] FPGA manager framework
1254 03:33:56.397044 <6>[ 0.564914] Advanced Linux Sound Architecture Driver Initialized.
1255 03:33:56.397447 <6>[ 0.571855] vgaarb: loaded
1256 03:33:56.397845 <6>[ 0.574412] clocksource: Switched to clocksource arch_sys_counter
1257 03:33:56.398243 <5>[ 0.580570] VFS: Disk quotas dquot_6.6.0
1258 03:33:56.398639 <6>[ 0.584549] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1259 03:33:56.399040 <6>[ 0.591752] pnp: PnP ACPI: disabled
1260 03:33:56.399441 <6>[ 0.600333] NET: Registered PF_INET protocol family
1261 03:33:56.399839 <6>[ 0.600580] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1262 03:33:56.400283 <6>[ 0.610742] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1263 03:33:56.400697 <6>[ 0.616751] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1264 03:33:56.401102 <6>[ 0.624647] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1265 03:33:56.401510 <6>[ 0.632880] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1266 03:33:56.401919 <6>[ 0.640678] TCP: Hash tables configured (established 32768 bind 32768)
1267 03:33:56.402321 <6>[ 0.647153] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1268 03:33:56.402722 <6>[ 0.654004] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1269 03:33:56.403119 <6>[ 0.661434] NET: Registered PF_UNIX/PF_LOCAL protocol family
1270 03:33:56.404423 <6>[ 0.667540] RPC: Registered named UNIX socket transport module.
1271 03:33:56.404903 <6>[ 0.673288] RPC: Registered udp transport module.
1272 03:33:56.405319 <6>[ 0.678196] RPC: Registered tcp transport module.
1273 03:33:56.405726 <6>[ 0.683110] RPC: Registered tcp-with-tls transport module.
1274 03:33:56.409883 <6>[ 0.688803] RPC: Registered tcp NFSv4.1 backchannel transport module.
1275 03:33:56.410411 <6>[ 0.695451] PCI: CLS 0 bytes, default 64
1276 03:33:56.415403 <6>[ 0.699716] Unpacking initramfs...
1277 03:33:56.420921 <6>[ 0.705864] kvm [1]: nv: 554 coarse grained trap handlers
1278 03:33:56.426430 <6>[ 0.709130] kvm [1]: IPA Size Limit: 40 bits
1279 03:33:56.431959 <6>[ 0.714744] kvm [1]: vgic interrupt IRQ9
1280 03:33:56.437546 <6>[ 0.717460] kvm [1]: Hyp nVHE mode initialized successfully
1281 03:33:56.442997 <5>[ 0.724517] Initialise system trusted keyrings
1282 03:33:56.448619 <6>[ 0.728092] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1283 03:33:56.454041 <6>[ 0.734786] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1284 03:33:56.459583 <5>[ 0.740826] NFS: Registering the id_resolver key type
1285 03:33:56.465072 <5>[ 0.745854] Key type id_resolver registered
1286 03:33:56.465571 <5>[ 0.750217] Key type id_legacy registered
1287 03:33:56.476104 <6>[ 0.754469] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1288 03:33:56.481633 <6>[ 0.761342] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1289 03:33:56.487452 <6>[ 0.769133] 9p: Installing v9fs 9p2000 file system support
1290 03:33:56.525721 <5>[ 0.815811] Key type asymmetric registered
1291 03:33:56.531064 <5>[ 0.815858] Asymmetric key parser 'x509' registered
1292 03:33:56.540141 <6>[ 0.819710] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1293 03:33:56.545665 <6>[ 0.827233] io scheduler mq-deadline registered
1294 03:33:56.551144 <6>[ 0.831976] io scheduler kyber registered
1295 03:33:56.551656 <6>[ 0.836238] io scheduler bfq registered
1296 03:33:56.559602 <6>[ 0.842119] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1297 03:33:56.576075 <6>[ 0.862466] ledtrig-cpu: registered to indicate activity on CPUs
1298 03:33:56.608772 <6>[ 0.894046] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1299 03:33:56.628249 <6>[ 0.907239] Serial: 8250/16550 driver, 4 ports<6>[ 0.911865] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1300 03:33:56.633742 <6>[ 0.921492] printk: legacy console [ttyAML0] enabled
1301 03:33:56.639295 <6>[ 0.921492] printk: legacy console [ttyAML0] enabled
1302 03:33:56.644852 <6>[ 0.926291] printk: legacy bootconsole [meson0] disabled
1303 03:33:56.650411 <6>[ 0.926291] printk: legacy bootconsole [meson0] disabled
1304 03:33:56.655903 <6>[ 0.939186] msm_serial: driver initialized
1305 03:33:56.661496 <6>[ 0.942249] SuperH (H)SCI(F) driver initialized
1306 03:33:56.662028 <6>[ 0.946785] STM32 USART driver initialized
1307 03:33:56.667019 <5>[ 0.952916] random: crng init done
1308 03:33:56.674219 <6>[ 0.958505] loop: module loaded
1309 03:33:56.674726 <6>[ 0.959766] megasas: 07.727.03.00-rc1
1310 03:33:56.679744 <6>[ 0.968962] tun: Universal TUN/TAP device driver, 1.6
1311 03:33:56.685266 <6>[ 0.970190] thunder_xcv, ver 1.0
1312 03:33:56.690840 <6>[ 0.972152] thunder_bgx, ver 1.0
1313 03:33:56.691341 <6>[ 0.975596] nicpf, ver 1.0
1314 03:33:56.696360 <6>[ 0.980168] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1315 03:33:56.701915 <6>[ 0.985983] hns3: Copyright (c) 2017 Huawei Corporation.
1316 03:33:56.707451 <6>[ 0.991571] hclge is initializing
1317 03:33:56.713017 <6>[ 0.995125] e1000: Intel(R) PRO/1000 Network Driver
1318 03:33:56.718673 <6>[ 1.000192] e1000: Copyright (c) 1999-2006 Intel Corporation.
1319 03:33:56.724122 <6>[ 1.006208] e1000e: Intel(R) PRO/1000 Network Driver
1320 03:33:56.729670 <6>[ 1.011370] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1321 03:33:56.735208 <6>[ 1.017555] igb: Intel(R) Gigabit Ethernet Network Driver
1322 03:33:56.740787 <6>[ 1.023156] igb: Copyright (c) 2007-2014 Intel Corporation.
1323 03:33:56.746442 <6>[ 1.028990] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1324 03:33:56.751971 <6>[ 1.035462] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1325 03:33:56.757493 <6>[ 1.042234] sky2: driver version 1.30
1326 03:33:56.763018 <6>[ 1.047360] VFIO - User Level meta-driver version: 0.3
1327 03:33:56.768598 <6>[ 1.054865] usbcore: registered new interface driver usb-storage
1328 03:33:56.774681 <6>[ 1.061043] i2c_dev: i2c /dev entries driver
1329 03:33:56.787554 <6>[ 1.072196] sdhci: Secure Digital Host Controller Interface driver
1330 03:33:56.788149 <6>[ 1.073001] sdhci: Copyright(c) Pierre Ossman
1331 03:33:56.798691 <6>[ 1.078754] Synopsys Designware Multimedia Card Interface Driver
1332 03:33:56.804269 <6>[ 1.085253] sdhci-pltfm: SDHCI platform and OF driver helper
1333 03:33:56.804833 <6>[ 1.092905] meson-sm: secure-monitor enabled
1334 03:33:56.817038 <6>[ 1.095518] usbcore: registered new interface driver usbhid
1335 03:33:56.817604 <6>[ 1.100063] usbhid: USB HID core driver
1336 03:33:56.824759 <6>[ 1.114914] NET: Registered PF_PACKET protocol family
1337 03:33:56.830283 <6>[ 1.115002] 9pnet: Installing 9P2000 support
1338 03:33:56.837354 <5>[ 1.119160] Key type dns_resolver registered
1339 03:33:56.842875 <6>[ 1.130716] registered taskstats version 1
1340 03:33:56.848444 <5>[ 1.130873] Loading compiled-in X.509 certificates
1341 03:33:56.852064 <6>[ 1.139527] Demotion targets for Node 0: null
1342 03:33:56.892318 <6>[ 1.182388] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1343 03:33:56.897809 <6>[ 1.182487] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1344 03:33:56.908843 <4>[ 1.192676] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1345 03:33:56.914456 <4>[ 1.195232] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1346 03:33:56.920028 <6>[ 1.202783] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1347 03:33:56.925539 <6>[ 1.212042] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1348 03:33:56.936584 <6>[ 1.215492] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1349 03:33:56.947713 <6>[ 1.223488] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1350 03:33:56.953270 <6>[ 1.233018] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1351 03:33:56.958820 <6>[ 1.239232] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1352 03:33:56.964391 <6>[ 1.244861] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1353 03:33:56.969918 <6>[ 1.252748] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1354 03:33:56.975458 <6>[ 1.259995] hub 1-0:1.0: USB hub found
1355 03:33:56.981018 <6>[ 1.263516] hub 1-0:1.0: 2 ports detected
1356 03:33:56.986556 <6>[ 1.269576] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1357 03:33:56.992098 <6>[ 1.276477] hub 2-0:1.0: USB hub found
1358 03:33:56.997186 <6>[ 1.280059] hub 2-0:1.0: 1 port detected
1359 03:33:57.018167 <6>[ 1.305741] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1360 03:33:57.030295 <6>[ 1.317157] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1361 03:33:57.063080 <6>[ 1.349594] Trying to probe devices needed for running init ...
1362 03:33:57.228541 <6>[ 1.514445] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1363 03:33:57.377143 <6>[ 1.661785] mmc0: new ultra high speed SDR104 SDXC card at address e624
1364 03:33:57.382705 <6>[ 1.663531] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1365 03:33:57.383185 <6>[ 1.669257] mmcblk0: p1
1366 03:33:57.386519 <6>[ 1.670738] Freeing initrd memory: 22880K
1367 03:33:57.417702 <6>[ 1.707847] hub 1-1:1.0: USB hub found
1368 03:33:57.423328 <6>[ 1.708163] hub 1-1:1.0: 4 ports detected
1369 03:33:57.492554 <6>[ 1.778551] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1370 03:33:57.530225 <6>[ 1.820506] hub 2-1:1.0: USB hub found
1371 03:33:57.535973 <6>[ 1.821328] hub 2-1:1.0: 4 ports detected
1372 03:34:09.356763 <6>[ 13.646475] clk: Disabling unused clocks
1373 03:34:09.362260 <6>[ 13.646641] PM: genpd: Disabling unused power domains
1374 03:34:09.370262 <6>[ 13.650333] ALSA device list:
1375 03:34:09.370866 <6>[ 13.653531] No soundcards found.
1376 03:34:09.375718 <6>[ 13.665854] Freeing unused kernel memory: 10432K
1377 03:34:09.382029 <6>[ 13.665953] Run /init as init process
1378 03:34:09.387275 Loading, please wait...
1379 03:34:09.424607 Starting systemd-udevd version 252.22-1~deb12u1
1380 03:34:09.860714 <6>[ 14.149325] mc: Linux media interface: v0.10
1381 03:34:09.865975 <6>[ 14.155041] meson-vrtc ff8000a8.rtc: registered as rtc0
1382 03:34:09.874381 <6>[ 14.155098] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1383 03:34:09.887408 <4>[ 14.172082] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1384 03:34:09.893729 <6>[ 14.173213] videodev: Linux video capture interface: v2.00
1385 03:34:09.929621 <6>[ 14.214292] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1386 03:34:09.935215 <6>[ 14.215699] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1387 03:34:09.938877 <6>[ 14.221993] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1388 03:34:09.944407 <6>[ 14.228246] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1389 03:34:09.955492 <6>[ 14.239611] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1390 03:34:09.959085 <6>[ 14.241718] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1391 03:34:09.970114 <6>[ 14.247187] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1392 03:34:09.975722 <6>[ 14.254891] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1393 03:34:09.979352 <6>[ 14.262602] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1394 03:34:09.990344 <6>[ 14.268058] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1395 03:34:09.995871 <6>[ 14.275338] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1396 03:34:10.001406 <6>[ 14.282121] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1397 03:34:10.006934 <6>[ 14.288183] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1398 03:34:10.012488 <6>[ 14.294240] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1399 03:34:10.023300 <3>[ 14.306459] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1400 03:34:10.039450 <6>[ 14.324167] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1401 03:34:10.040008 <6>[ 14.328360] Registered IR keymap rc-empty
1402 03:34:10.050543 <6>[ 14.328740] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1403 03:34:10.056080 <6>[ 14.333568] panfrost ffe40000.gpu: clock rate = 24000000
1404 03:34:10.061644 <6>[ 14.336989] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1405 03:34:10.072735 <3>[ 14.342954] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1406 03:34:10.078274 <6>[ 14.360007] rc rc0: sw decoder init
1407 03:34:10.083825 <6>[ 14.362958] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1408 03:34:10.089376 <6>[ 14.363653] meson-ir ff808000.ir: receiver initialized
1409 03:34:10.100463 <6>[ 14.371555] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1410 03:34:10.111541 <6>[ 14.385324] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1411 03:34:10.122624 <6>[ 14.388265] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1412 03:34:10.128219 <6>[ 14.397365] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1413 03:34:10.139277 <6>[ 14.416260] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1414 03:34:10.147737 <4>[ 14.426516] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1415 03:34:10.159630 <6>[ 14.444384] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1416 03:34:10.165192 <6>[ 14.448613] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1417 03:34:10.176277 <6>[ 14.456051] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1418 03:34:10.181827 <6>[ 14.459066] usbcore: registered new device driver onboard-usb-dev
1419 03:34:10.187368 <6>[ 14.461567] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1420 03:34:10.192883 <3>[ 14.463106] meson-drm ff900000.vpu: DSI transceiver device is disabled
1421 03:34:10.202055 <6>[ 14.482997] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1422 03:34:10.381282 <6>[ 14.647199] Console: switching to colour frame buffer device 128x48
1423 03:34:10.387159 <6>[ 14.666842] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1424 03:34:10.601745 <6>[ 14.891850] hub 1-1:1.0: USB hub found
1425 03:34:10.607442 <6>[ 14.892158] hub 1-1:1.0: 4 ports detected
1426 03:34:10.749772 <4>[ 15.034434] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1427 03:34:10.755357 <3>[ 15.036797] onboard-usb-dev 1-1: Failed to suspend device, error -32
1428 03:34:10.762261 <3>[ 15.043231] onboard-usb-dev 1-1: can't set config #1, error -71
1429 03:34:10.777684 <4>[ 15.062425] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1430 03:34:10.783244 <3>[ 15.064798] onboard-usb-dev 1-1: Failed to suspend device, error -32
1431 03:34:10.788795 <6>[ 15.066555] onboard-usb-dev 1-1: USB disconnect, device number 2
1432 03:34:10.794321 Begin: Loading essential drivers ... done.
1433 03:34:10.799867 Begin: Running /scripts/init-premount ... done.
1434 03:34:10.805442 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1435 03:34:10.810963 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1436 03:34:10.816554 Device /sys/class/net/end0 found
1437 03:34:10.817088 done.
1438 03:34:10.825071 Begin: Waiting up to 180 secs for any network device to become available ... done.
1439 03:34:10.887418 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.167469] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1440 03:34:10.888079
1441 03:34:10.976554 <6>[ 15.258527] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=31)
1442 03:34:10.990497 <6>[ 15.275172] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1443 03:34:10.996108 <6>[ 15.277359] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1444 03:34:11.005493 <6>[ 15.284704] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1445 03:34:11.040533 <6>[ 15.326461] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1446 03:34:11.209958 <6>[ 15.499932] hub 1-1:1.0: USB hub found
1447 03:34:11.215537 <6>[ 15.500277] hub 1-1:1.0: 4 ports detected
1448 03:34:11.374126 <6>[ 15.659801] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1449 03:34:11.629999 <6>[ 15.915788] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1450 03:34:12.176292 <4>[ 16.466423] rc rc0: two consecutive events of type space
1451 03:34:12.366806 IP-Config: no response after 2 secs - giving up
1452 03:34:12.423911 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1453 03:34:14.216257 <6>[ 18.500325] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1454 03:34:14.635796 IP-Config: end0 guessed broadcast address 192.168.6.255
1455 03:34:14.641225 IP-Config: end0 complete (dhcp from 192.168.6.1):
1456 03:34:14.646707 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1457 03:34:14.657781 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1458 03:34:14.658278 rootserver: 192.168.6.1 rootpath:
1459 03:34:14.661219 filename :
1460 03:34:14.771045 done.
1461 03:34:14.783217 Begin: Running /scripts/nfs-bottom ... done.
1462 03:34:14.802052 Begin: Running /scripts/init-bottom ... done.
1463 03:34:15.138083 <30>[ 19.423678] systemd[1]: System time before build time, advancing clock.
1464 03:34:15.196071 <6>[ 19.486136] NET: Registered PF_INET6 protocol family
1465 03:34:15.201532 <6>[ 19.488150] Segment Routing with IPv6
1466 03:34:15.206795 <6>[ 19.489638] In-situ OAM (IOAM) with IPv6
1467 03:34:15.281787 <30>[ 19.544277] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1468 03:34:15.287325 <30>[ 19.571645] systemd[1]: Detected architecture arm64.
1469 03:34:15.287835
1470 03:34:15.294826 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1471 03:34:15.295332
1472 03:34:15.305764 <30>[ 19.592101] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1473 03:34:15.991922 <30>[ 20.277028] systemd[1]: Queued start job for default target graphical.target.
1474 03:34:16.032081 <30>[ 20.316791] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1475 03:34:16.039682 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1476 03:34:16.050651 <30>[ 20.335398] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1477 03:34:16.059060 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1478 03:34:16.070745 <30>[ 20.355487] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1479 03:34:16.084171 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1480 03:34:16.089721 <30>[ 20.375171] systemd[1]: Created slice user.slice - User and Session Slice.
1481 03:34:16.096172 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1482 03:34:16.107270 <30>[ 20.390699] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1483 03:34:16.118715 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1484 03:34:16.129803 <30>[ 20.410620] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1485 03:34:16.136351 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1486 03:34:16.158485 <30>[ 20.430601] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1487 03:34:16.164036 <30>[ 20.444665] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1488 03:34:16.171830 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1489 03:34:16.182765 <30>[ 20.466514] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1490 03:34:16.189932 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1491 03:34:16.205771 <30>[ 20.490530] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1492 03:34:16.219468 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1493 03:34:16.225019 <30>[ 20.510562] systemd[1]: Reached target paths.target - Path Units.
1494 03:34:16.233432 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1495 03:34:16.238965 <30>[ 20.526524] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1496 03:34:16.250694 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1497 03:34:16.256269 <30>[ 20.542499] systemd[1]: Reached target slices.target - Slice Units.
1498 03:34:16.264395 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1499 03:34:16.269941 <30>[ 20.558534] systemd[1]: Reached target swap.target - Swaps.
1500 03:34:16.277767 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1501 03:34:16.289774 <30>[ 20.574547] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1502 03:34:16.298774 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1503 03:34:16.313922 <30>[ 20.598712] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1504 03:34:16.323148 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1505 03:34:16.334981 <30>[ 20.619782] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1506 03:34:16.344009 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1507 03:34:16.355073 <30>[ 20.639429] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1508 03:34:16.368225 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1509 03:34:16.373733 <30>[ 20.658869] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1510 03:34:16.380582 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1511 03:34:16.391675 <30>[ 20.675509] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1512 03:34:16.399895 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1513 03:34:16.411684 <30>[ 20.696473] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1514 03:34:16.417323 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1515 03:34:16.429976 <30>[ 20.714745] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1516 03:34:16.438438 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1517 03:34:16.469853 <30>[ 20.754608] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1518 03:34:16.476582 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1519 03:34:16.488376 <30>[ 20.773111] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1520 03:34:16.495863 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1521 03:34:16.508083 <30>[ 20.792644] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1522 03:34:16.516287 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1523 03:34:16.533545 <30>[ 20.810814] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1524 03:34:16.544581 <30>[ 20.823892] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1525 03:34:16.549731 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1526 03:34:16.568584 <30>[ 20.853325] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1527 03:34:16.576499 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1528 03:34:16.588178 <30>[ 20.872824] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1529 03:34:16.595656 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1530 03:34:16.608660 <30>[ 20.893394] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1531 03:34:16.614180 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1532 03:34:16.624602 <6>[ 20.905657] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1533 03:34:16.666071 <30>[ 20.950799] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1534 03:34:16.674335 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1535 03:34:16.688608 <30>[ 20.973385] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1536 03:34:16.695899 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1537 03:34:16.708328 <30>[ 20.993026] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1538 03:34:16.713851 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1539 03:34:16.717780 <6>[ 21.004099] fuse: init (API version 7.41)
1540 03:34:16.738798 <30>[ 21.023286] systemd[1]: Starting systemd-journald.service - Journal Service...
1541 03:34:16.744937 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1542 03:34:16.760236 <30>[ 21.044883] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1543 03:34:16.767659 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1544 03:34:16.779568 <30>[ 21.064304] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1545 03:34:16.788932 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1546 03:34:16.811669 <30>[ 21.096410] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1547 03:34:16.820449 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1548 03:34:16.833168 <30>[ 21.117894] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1549 03:34:16.841207 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1550 03:34:16.852768 <30>[ 21.137461] systemd[1]: Started systemd-journald.service - Journal Service.
1551 03:34:16.859543 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1552 03:34:16.873621 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1553 03:34:16.888744 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1554 03:34:16.903159 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1555 03:34:16.914677 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1556 03:34:16.927008 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1557 03:34:16.938941 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1558 03:34:16.950604 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1559 03:34:16.963141 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1560 03:34:16.974751 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1561 03:34:16.990798 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1562 03:34:17.006715 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1563 03:34:17.023286 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1564 03:34:17.038737 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1565 03:34:17.054920 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1566 03:34:17.120796 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1567 03:34:17.127218 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1568 03:34:17.139545 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1569 03:34:17.152309 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1570 03:34:17.166985 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1571 03:34:17.182728 <46>[ 21.467484] systemd-journald[230]: Received client request to flush runtime journal.
1572 03:34:17.190259 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1573 03:34:17.214100 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1574 03:34:17.222239 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1575 03:34:17.239574 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1576 03:34:17.255229 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1577 03:34:17.266797 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1578 03:34:17.338181 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1579 03:34:17.405570 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1580 03:34:17.486673 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1581 03:34:17.510641 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1582 03:34:17.522443 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1583 03:34:17.533483 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1584 03:34:17.581502 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1585 03:34:17.592236 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1586 03:34:17.818487 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1587 03:34:17.835254 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1588 03:34:17.893634 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1589 03:34:17.913907 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1590 03:34:17.935036 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1591 03:34:18.014806 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1592 03:34:18.031349 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1593 03:34:18.062387 <5>[ 22.347056] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1594 03:34:18.099844 <5>[ 22.384584] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1595 03:34:18.105383 <5>[ 22.385276] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1596 03:34:18.116457 [<4>[ 22.393148] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1597 03:34:18.116969 <6>[ 22.401464] cfg80211: failed to load regulatory.db
1598 03:34:18.127328 [0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1599 03:34:18.138100 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1600 03:34:18.154200 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1601 03:34:18.170838 <46>[ 22.445699] systemd-journald[230]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1602 03:34:18.187445 <46>[ 22.460119] systemd-journald[230]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1603 03:34:18.201424 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1604 03:34:18.222031 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1605 03:34:18.262652 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1606 03:34:18.274400 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1607 03:34:18.318314 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1608 03:34:18.337850 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1609 03:34:18.344708 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1610 03:34:18.359393 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1611 03:34:18.372977 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1612 03:34:18.384649 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1613 03:34:18.428747 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1614 03:34:18.470983 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1615 03:34:18.490096 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1616 03:34:18.503893 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1617 03:34:18.547440 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1618 03:34:18.554222 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1619 03:34:18.566328 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1620 03:34:18.645018 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1621 03:34:18.653477 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1622 03:34:18.661734 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1623 03:34:18.685911 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1624 03:34:18.706643 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1625 03:34:18.713030 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1626 03:34:18.729205 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1627 03:34:18.777737 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1628 03:34:18.795370 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1629 03:34:18.808323 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1630 03:34:18.815124 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1631 03:34:18.831198 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1632 03:34:18.837763 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1633 03:34:18.890897 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1634 03:34:18.939631 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1635 03:34:19.014951
1636 03:34:19.015480 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1637 03:34:19.015957
1638 03:34:19.021959 debian-bookworm-arm64 login: root (automatic login)
1639 03:34:19.022463
1640 03:34:19.155263 Linux debian-bookworm-arm64 6.12.0-rc2 #1 SMP PREEMPT Sat Nov 9 02:41:39 UTC 2024 aarch64
1641 03:34:19.155823
1642 03:34:19.160817 The programs included with the Debian GNU/Linux system are free software;
1643 03:34:19.166315 the exact distribution terms for each program are described in the
1644 03:34:19.171863 individual files in /usr/share/doc/*/copyright.
1645 03:34:19.172375
1646 03:34:19.177660 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1647 03:34:19.180557 permitted by applicable law.
1648 03:34:19.906906 Matched prompt #10: / #
1650 03:34:19.908633 Setting prompt string to ['/ #']
1651 03:34:19.909253 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1653 03:34:19.910730 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1654 03:34:19.911297 start: 2.4.5 expect-shell-connection (timeout 00:03:18) [common]
1655 03:34:19.911762 Setting prompt string to ['/ #']
1656 03:34:19.912253 Forcing a shell prompt, looking for ['/ #']
1658 03:34:19.963306 / #
1659 03:34:19.964061 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1660 03:34:19.964540 Waiting using forced prompt support (timeout 00:02:30)
1661 03:34:19.969275
1662 03:34:19.970301 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1663 03:34:19.970903 start: 2.4.6 export-device-env (timeout 00:03:18) [common]
1664 03:34:19.971386 Sending with 10 millisecond of delay
1666 03:34:24.962075 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/964641/extract-nfsrootfs-zln5lm9w'
1667 03:34:24.973265 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/964641/extract-nfsrootfs-zln5lm9w'
1668 03:34:24.974228 Sending with 10 millisecond of delay
1670 03:34:27.073553 / # export NFS_SERVER_IP='192.168.6.2'
1671 03:34:27.084614 export NFS_SERVER_IP='192.168.6.2'
1672 03:34:27.085629 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1673 03:34:27.086271 end: 2.4 uboot-commands (duration 00:01:49) [common]
1674 03:34:27.086891 end: 2 uboot-action (duration 00:01:49) [common]
1675 03:34:27.087502 start: 3 lava-test-retry (timeout 00:06:53) [common]
1676 03:34:27.088164 start: 3.1 lava-test-shell (timeout 00:06:53) [common]
1677 03:34:27.088694 Using namespace: common
1679 03:34:27.190005 / # #
1680 03:34:27.191149 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1681 03:34:27.196629 #
1682 03:34:27.197501 Using /lava-964641
1684 03:34:27.299218 / # export SHELL=/bin/bash
1685 03:34:27.305733 export SHELL=/bin/bash
1687 03:34:27.407282 / # . /lava-964641/environment
1688 03:34:27.412476 . /lava-964641/environment
1690 03:34:27.517703 / # /lava-964641/bin/lava-test-runner /lava-964641/0
1691 03:34:27.518265 Test shell timeout: 10s (minimum of the action and connection timeout)
1692 03:34:27.522852 /lava-964641/bin/lava-test-runner /lava-964641/0
1693 03:34:27.742409 + export TESTRUN_ID=0_timesync-off
1694 03:34:27.749836 + TESTRUN_ID=0_timesync-off
1695 03:34:27.750195 + cd /lava-964641/0/tests/0_timesync-off
1696 03:34:27.750448 ++ cat uuid
1697 03:34:27.755398 + UUID=964641_1.6.2.4.1
1698 03:34:27.755753 + set +x
1699 03:34:27.763321 <LAVA_SIGNAL_STARTRUN 0_timesync-off 964641_1.6.2.4.1>
1700 03:34:27.763860 + systemctl stop systemd-timesyncd
1701 03:34:27.764526 Received signal: <STARTRUN> 0_timesync-off 964641_1.6.2.4.1
1702 03:34:27.764800 Starting test lava.0_timesync-off (964641_1.6.2.4.1)
1703 03:34:27.765089 Skipping test definition patterns.
1704 03:34:27.820339 + set +x
1705 03:34:27.820958 <LAVA_SIGNAL_ENDRUN 0_timesync-off 964641_1.6.2.4.1>
1706 03:34:27.821633 Received signal: <ENDRUN> 0_timesync-off 964641_1.6.2.4.1
1707 03:34:27.822123 Ending use of test pattern.
1708 03:34:27.822524 Ending test lava.0_timesync-off (964641_1.6.2.4.1), duration 0.06
1710 03:34:27.906925 + export TESTRUN_ID=1_kselftest-alsa
1711 03:34:27.915158 + TESTRUN_ID=1_kselftest-alsa
1712 03:34:27.915681 + cd /lava-964641/0/tests/1_kselftest-alsa
1713 03:34:27.916202 ++ cat uuid
1714 03:34:27.924424 + UUID=964641_1.6.2.4.5
1715 03:34:27.925046 + set +x
1716 03:34:27.930181 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 964641_1.6.2.4.5>
1717 03:34:27.932255 + cd ./automated/linux/kselftest/
1718 03:34:27.933313 Received signal: <STARTRUN> 1_kselftest-alsa 964641_1.6.2.4.5
1719 03:34:27.933883 Starting test lava.1_kselftest-alsa (964641_1.6.2.4.5)
1720 03:34:27.934460 Skipping test definition patterns.
1721 03:34:27.961736 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1722 03:34:27.997131 INFO: install_deps skipped
1723 03:34:28.115608 --2024-11-09 03:34:28-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm64/defconfig/gcc-12/kselftest.tar.xz
1724 03:34:28.140022 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1725 03:34:28.285957 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1726 03:34:28.428614 HTTP request sent, awaiting response... 200 OK
1727 03:34:28.429035 Length: 6923836 (6.6M) [application/octet-stream]
1728 03:34:28.434066 Saving to: 'kselftest_armhf.tar.gz'
1729 03:34:28.434623
1730 03:34:29.894101
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 47.54K 166KB/s
kselftest_armhf.tar 3%[ ] 218.67K 382KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.02MB/s
kselftest_armhf.tar 53%[=========> ] 3.51M 3.07MB/s
kselftest_armhf.tar 97%[==================> ] 6.41M 4.41MB/s
kselftest_armhf.tar 100%[===================>] 6.60M 4.54MB/s in 1.5s
1731 03:34:29.894815
1732 03:34:29.979583 2024-11-09 03:34:29 (4.54 MB/s) - 'kselftest_armhf.tar.gz' saved [6923836/6923836]
1733 03:34:29.980306
1734 03:34:39.285998 skiplist:
1735 03:34:39.286673 ========================================
1736 03:34:39.291636 ========================================
1737 03:34:39.330311 alsa:mixer-test
1738 03:34:39.330865 alsa:pcm-test
1739 03:34:39.331326 alsa:test-pcmtest-driver
1740 03:34:39.334432 alsa:utimer-test
1741 03:34:39.348755 ============== Tests to run ===============
1742 03:34:39.349317 alsa:mixer-test
1743 03:34:39.354354 alsa:pcm-test
1744 03:34:39.354893 alsa:test-pcmtest-driver
1745 03:34:39.355348 alsa:utimer-test
1746 03:34:39.362462 ===========End Tests to run ===============
1747 03:34:39.363003 shardfile-alsa pass
1748 03:34:39.473940 <12>[ 43.761829] kselftest: Running tests in alsa
1749 03:34:39.480214 TAP version 13
1750 03:34:39.493527 1..4
1751 03:34:39.516681 # timeout set to 45
1752 03:34:39.517230 # selftests: alsa: mixer-test
1753 03:34:39.697337 # TAP version 13
1754 03:34:39.697925 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1755 03:34:39.702705 # 1..427
1756 03:34:39.703207 # ok 1 get_value.LCALTA.60
1757 03:34:39.703660 # # LCALTA.60 TDMOUT_A SRC SEL
1758 03:34:39.708316 # ok 2 name.LCALTA.60
1759 03:34:39.708818 # ok 3 write_default.LCALTA.60
1760 03:34:39.711872 # ok 4 write_valid.LCALTA.60
1761 03:34:39.717328 # ok 5 write_invalid.LCALTA.60
1762 03:34:39.717823 # ok 6 event_missing.LCALTA.60
1763 03:34:39.722935 # ok 7 event_spurious.LCALTA.60
1764 03:34:39.723428 # ok 8 get_value.LCALTA.59
1765 03:34:39.728471 # # LCALTA.59 TDMOUT_B SRC SEL
1766 03:34:39.728965 # ok 9 name.LCALTA.59
1767 03:34:39.732144 # ok 10 write_default.LCALTA.59
1768 03:34:39.732632 # ok 11 write_valid.LCALTA.59
1769 03:34:39.737624 # ok 12 write_invalid.LCALTA.59
1770 03:34:39.738114 # ok 13 event_missing.LCALTA.59
1771 03:34:39.743221 # ok 14 event_spurious.LCALTA.59
1772 03:34:39.743714 # ok 15 get_value.LCALTA.58
1773 03:34:39.748740 # # LCALTA.58 TDMOUT_C SRC SEL
1774 03:34:39.749233 # ok 16 name.LCALTA.58
1775 03:34:39.752316 # ok 17 write_default.LCALTA.58
1776 03:34:39.757832 # ok 18 write_valid.LCALTA.58
1777 03:34:39.758317 # ok 19 write_invalid.LCALTA.58
1778 03:34:39.763372 # ok 20 event_missing.LCALTA.58
1779 03:34:39.763859 # ok 21 event_spurious.LCALTA.58
1780 03:34:39.768924 # ok 22 get_value.LCALTA.57
1781 03:34:39.769421 # # LCALTA.57 TDMIN_A SRC SEL
1782 03:34:39.769875 # ok 23 name.LCALTA.57
1783 03:34:39.772491 # ok 24 write_default.LCALTA.57
1784 03:34:39.778008 # ok 25 write_valid.LCALTA.57
1785 03:34:39.778499 # ok 26 write_invalid.LCALTA.57
1786 03:34:39.783561 # ok 27 event_missing.LCALTA.57
1787 03:34:39.784081 # ok 28 event_spurious.LCALTA.57
1788 03:34:39.789110 # ok 29 get_value.LCALTA.56
1789 03:34:39.789597 # # LCALTA.56 TDMIN_B SRC SEL
1790 03:34:39.794613 # ok 30 name.LCALTA.56
1791 03:34:39.795098 # ok 31 write_default.LCALTA.56
1792 03:34:39.800183 # ok 32 write_valid.LCALTA.56
1793 03:34:39.800665 # ok 33 write_invalid.LCALTA.56
1794 03:34:39.805774 # ok 34 event_missing.LCALTA.56
1795 03:34:39.806266 # ok 35 event_spurious.LCALTA.56
1796 03:34:39.811309 # ok 36 get_value.LCALTA.55
1797 03:34:39.822273 # # LCALTA.55 TD<3>[ 44.100721] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1798 03:34:39.822784 MIN_C SRC SEL
1799 03:34:39.827853 # ok 37 name.LCALTA.55
1800 03:34:39.828382 # ok 38 write_default.LCALTA.55
1801 03:34:39.833373 # ok 39 write_valid.LCALTA.55
1802 03:34:39.833862 # ok 40 write_invalid.LCALTA.55
1803 03:34:39.838916 # ok 41 event_missing.LCALTA.55
1804 03:34:39.839400 # ok 42 event_spurious.LCALTA.55
1805 03:34:39.844552 # ok 43 get_value.LCALTA.54
1806 03:34:39.845045 # # LCALTA.54 ACODEC Left DAC Sel
1807 03:34:39.850007 # ok 44 name.LCALTA.54
1808 03:34:39.850495 # ok 45 write_default.LCALTA.54
1809 03:34:39.855553 # ok 46 write_valid.LCALTA.54
1810 03:34:39.856067 # ok 47 write_invalid.LCALTA.54
1811 03:34:39.861092 # ok 48 event_missing.LCALTA.54
1812 03:34:39.861575 # ok 49 event_spurious.LCALTA.54
1813 03:34:39.866648 # ok 50 get_value.LCALTA.53
1814 03:34:39.867132 # # LCALTA.53 ACODEC Right DAC Sel
1815 03:34:39.872185 # ok 51 name.LCALTA.53
1816 03:34:39.872678 # ok 52 write_default.LCALTA.53
1817 03:34:39.877729 # ok 53 write_valid.LCALTA.53
1818 03:34:39.878216 # ok 54 write_invalid.LCALTA.53
1819 03:34:39.883328 # ok 55 event_missing.LCALTA.53
1820 03:34:39.883815 # ok 56 event_spurious.LCALTA.53
1821 03:34:39.888853 # ok 57 get_value.LCALTA.52
1822 03:34:39.889341 # # LCALTA.52 TOACODEC OUT EN Switch
1823 03:34:39.894412 # ok 58 name.LCALTA.52
1824 03:34:39.894913 # ok 59 write_default.LCALTA.52
1825 03:34:39.899951 # ok 60 write_valid.LCALTA.52
1826 03:34:39.900484 # ok 61 write_invalid.LCALTA.52
1827 03:34:39.905486 # ok 62 event_missing.LCALTA.52
1828 03:34:39.905976 # ok 63 event_spurious.LCALTA.52
1829 03:34:39.911027 # ok 64 get_value.LCALTA.51
1830 03:34:39.911511 # # LCALTA.51 TOACODEC SRC
1831 03:34:39.911956 # ok 65 name.LCALTA.51
1832 03:34:39.916600 # ok 66 write_default.LCALTA.51
1833 03:34:39.917089 # ok 67 write_valid.LCALTA.51
1834 03:34:39.922119 # ok 68 write_invalid.LCALTA.51
1835 03:34:39.927661 # ok 69 event_missing.LCALTA.51
1836 03:34:39.928169 # ok 70 event_spurious.LCALTA.51
1837 03:34:39.928614 # ok 71 get_value.LCALTA.50
1838 03:34:39.933187 # # LCALTA.50 TOHDMITX SPDIF SRC
1839 03:34:39.933666 # ok 72 name.LCALTA.50
1840 03:34:39.938746 # ok 73 write_default.LCALTA.50
1841 03:34:39.939230 # ok 74 write_valid.LCALTA.50
1842 03:34:39.944458 # ok 75 write_invalid.LCALTA.50
1843 03:34:39.944966 # ok 76 event_missing.LCALTA.50
1844 03:34:39.949956 # ok 77 event_spurious.LCALTA.50
1845 03:34:39.950455 # ok 78 get_value.LCALTA.49
1846 03:34:39.955491 # # LCALTA.49 TOHDMITX Switch
1847 03:34:39.956013 # ok 79 name.LCALTA.49
1848 03:34:39.961069 # ok 80 write_default.LCALTA.49
1849 03:34:39.961570 # ok 81 write_valid.LCALTA.49
1850 03:34:39.966672 # ok 82 write_invalid.LCALTA.49
1851 03:34:39.967167 # ok 83 event_missing.LCALTA.49
1852 03:34:39.972163 # ok 84 event_spurious.LCALTA.49
1853 03:34:39.972660 # ok 85 get_value.LCALTA.48
1854 03:34:39.977704 # # LCALTA.48 TOHDMITX I2S SRC
1855 03:34:39.978195 # ok 86 name.LCALTA.48
1856 03:34:39.983271 # ok 87 write_default.LCALTA.48
1857 03:34:39.983773 # ok 88 write_valid.LCALTA.48
1858 03:34:39.988809 # ok 89 write_invalid.LCALTA.48
1859 03:34:39.989310 # ok 90 event_missing.LCALTA.48
1860 03:34:39.994321 # ok 91 event_spurious.LCALTA.48
1861 03:34:39.994817 # ok 92 get_value.LCALTA.47
1862 03:34:39.999866 # # LCALTA.47 TODDR_C SRC SEL
1863 03:34:40.000395 # ok 93 name.LCALTA.47
1864 03:34:40.005421 # ok 94 write_default.LCALTA.47
1865 03:34:40.005920 # ok 95 write_valid.LCALTA.47
1866 03:34:40.010979 # ok 96 write_invalid.LCALTA.47
1867 03:34:40.011483 # ok 97 event_missing.LCALTA.47
1868 03:34:40.016601 # ok 98 event_spurious.LCALTA.47
1869 03:34:40.017147 # ok 99 get_value.LCALTA.46
1870 03:34:40.022164 # # LCALTA.46 TODDR_B SRC SEL
1871 03:34:40.022713 # ok 100 name.LCALTA.46
1872 03:34:40.023166 # ok 101 write_default.LCALTA.46
1873 03:34:40.027764 # ok 102 write_valid.LCALTA.46
1874 03:34:40.028339 # ok 103 write_invalid.LCALTA.46
1875 03:34:40.033176 # ok 104 event_missing.LCALTA.46
1876 03:34:40.038751 # ok 105 event_spurious.LCALTA.46
1877 03:34:40.039254 # ok 106 get_value.LCALTA.45
1878 03:34:40.044255 # # LCALTA.45 TODDR_A SRC SEL
1879 03:34:40.044753 # ok 107 name.LCALTA.45
1880 03:34:40.045200 # ok 108 write_default.LCALTA.45
1881 03:34:40.049795 # ok 109 write_valid.LCALTA.45
1882 03:34:40.050293 # ok 110 write_invalid.LCALTA.45
1883 03:34:40.055376 # ok 111 event_missing.LCALTA.45
1884 03:34:40.060895 # ok 112 event_spurious.LCALTA.45
1885 03:34:40.061397 # ok 113 get_value.LCALTA.44
1886 03:34:40.066457 # # LCALTA.44 FRDDR_C SINK 3 SEL
1887 03:34:40.066958 # ok 114 name.LCALTA.44
1888 03:34:40.067402 # ok 115 write_default.LCALTA.44
1889 03:34:40.072021 # ok 116 write_valid.LCALTA.44
1890 03:34:40.077578 # ok 117 write_invalid.LCALTA.44
1891 03:34:40.078100 # ok 118 event_missing.LCALTA.44
1892 03:34:40.083102 # ok 119 event_spurious.LCALTA.44
1893 03:34:40.083616 # ok 120 get_value.LCALTA.43
1894 03:34:40.088699 # # LCALTA.43 FRDDR_C SINK 2 SEL
1895 03:34:40.089211 # ok 121 name.LCALTA.43
1896 03:34:40.094212 # ok 122 write_default.LCALTA.43
1897 03:34:40.094733 # ok 123 write_valid.LCALTA.43
1898 03:34:40.099784 # ok 124 write_invalid.LCALTA.43
1899 03:34:40.100344 # ok 125 event_missing.LCALTA.43
1900 03:34:40.105327 # ok 126 event_spurious.LCALTA.43
1901 03:34:40.105858 # ok 127 get_value.LCALTA.42
1902 03:34:40.110865 # # LCALTA.42 FRDDR_C SINK 1 SEL
1903 03:34:40.111400 # ok 128 name.LCALTA.42
1904 03:34:40.116377 # ok 129 write_default.LCALTA.42
1905 03:34:40.116900 # ok 130 write_valid.LCALTA.42
1906 03:34:40.122021 # ok 131 write_invalid.LCALTA.42
1907 03:34:40.122597 # ok 132 event_missing.LCALTA.42
1908 03:34:40.127466 # ok 133 event_spurious.LCALTA.42
1909 03:34:40.128063 # ok 134 get_value.LCALTA.41
1910 03:34:40.132984 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1911 03:34:40.133476 # ok 135 name.LCALTA.41
1912 03:34:40.138543 # ok 136 write_default.LCALTA.41
1913 03:34:40.139040 # ok 137 write_valid.LCALTA.41
1914 03:34:40.144104 # ok 138 write_invalid.LCALTA.41
1915 03:34:40.144608 # ok 139 event_missing.LCALTA.41
1916 03:34:40.149664 # ok 140 event_spurious.LCALTA.41
1917 03:34:40.150159 # ok 141 get_value.LCALTA.40
1918 03:34:40.155155 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1919 03:34:40.155660 # ok 142 name.LCALTA.40
1920 03:34:40.160751 # ok 143 write_default.LCALTA.40
1921 03:34:40.161244 # ok 144 write_valid.LCALTA.40
1922 03:34:40.166305 # ok 145 write_invalid.LCALTA.40
1923 03:34:40.166805 # ok 146 event_missing.LCALTA.40
1924 03:34:40.171815 # ok 147 event_spurious.LCALTA.40
1925 03:34:40.172337 # ok 148 get_value.LCALTA.39
1926 03:34:40.177347 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1927 03:34:40.177843 # ok 149 name.LCALTA.39
1928 03:34:40.182929 # ok 150 write_default.LCALTA.39
1929 03:34:40.183444 # ok 151 write_valid.LCALTA.39
1930 03:34:40.188516 # ok 152 write_invalid.LCALTA.39
1931 03:34:40.189041 # ok 153 event_missing.LCALTA.39
1932 03:34:40.193992 # ok 154 event_spurious.LCALTA.39
1933 03:34:40.194490 # ok 155 get_value.LCALTA.38
1934 03:34:40.199557 # # LCALTA.38 FRDDR_B SINK 3 SEL
1935 03:34:40.200073 # ok 156 name.LCALTA.38
1936 03:34:40.205091 # ok 157 write_default.LCALTA.38
1937 03:34:40.205584 # ok 158 write_valid.LCALTA.38
1938 03:34:40.210699 # ok 159 write_invalid.LCALTA.38
1939 03:34:40.211197 # ok 160 event_missing.LCALTA.38
1940 03:34:40.216235 # ok 161 event_spurious.LCALTA.38
1941 03:34:40.216766 # ok 162 get_value.LCALTA.37
1942 03:34:40.221776 # # LCALTA.37 FRDDR_B SINK 2 SEL
1943 03:34:40.222272 # ok 163 name.LCALTA.37
1944 03:34:40.227309 # ok 164 write_default.LCALTA.37
1945 03:34:40.227806 # ok 165 write_valid.LCALTA.37
1946 03:34:40.232873 # ok 166 write_invalid.LCALTA.37
1947 03:34:40.233385 # ok 167 event_missing.LCALTA.37
1948 03:34:40.238406 # ok 168 event_spurious.LCALTA.37
1949 03:34:40.243928 # ok 169 get_value.LCALTA.36
1950 03:34:40.244492 # # LCALTA.36 FRDDR_B SINK 1 SEL
1951 03:34:40.244938 # ok 170 name.LCALTA.36
1952 03:34:40.249565 # ok 171 write_default.LCALTA.36
1953 03:34:40.250099 # ok 172 write_valid.LCALTA.36
1954 03:34:40.255024 # ok 173 write_invalid.LCALTA.36
1955 03:34:40.260656 # ok 174 event_missing.LCALTA.36
1956 03:34:40.261206 # ok 175 event_spurious.LCALTA.36
1957 03:34:40.266152 # ok 176 get_value.LCALTA.35
1958 03:34:40.266677 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1959 03:34:40.271760 # ok 177 name.LCALTA.35
1960 03:34:40.272326 # ok 178 write_default.LCALTA.35
1961 03:34:40.277223 # ok 179 write_valid.LCALTA.35
1962 03:34:40.277737 # ok 180 write_invalid.LCALTA.35
1963 03:34:40.282774 # ok 181 event_missing.LCALTA.35
1964 03:34:40.283286 # ok 182 event_spurious.LCALTA.35
1965 03:34:40.288332 # ok 183 get_value.LCALTA.34
1966 03:34:40.288850 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1967 03:34:40.293857 # ok 184 name.LCALTA.34
1968 03:34:40.294367 # ok 185 write_default.LCALTA.34
1969 03:34:40.299427 # ok 186 write_valid.LCALTA.34
1970 03:34:40.299939 # ok 187 write_invalid.LCALTA.34
1971 03:34:40.304988 # ok 188 event_missing.LCALTA.34
1972 03:34:40.305504 # ok 189 event_spurious.LCALTA.34
1973 03:34:40.310502 # ok 190 get_value.LCALTA.33
1974 03:34:40.311013 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1975 03:34:40.316073 # ok 191 name.LCALTA.33
1976 03:34:40.316587 # ok 192 write_default.LCALTA.33
1977 03:34:40.321593 # ok 193 write_valid.LCALTA.33
1978 03:34:40.322097 # ok 194 write_invalid.LCALTA.33
1979 03:34:40.327129 # ok 195 event_missing.LCALTA.33
1980 03:34:40.327630 # ok 196 event_spurious.LCALTA.33
1981 03:34:40.332715 # ok 197 get_value.LCALTA.32
1982 03:34:40.333214 # # LCALTA.32 FRDDR_A SINK 3 SEL
1983 03:34:40.338231 # ok 198 name.LCALTA.32
1984 03:34:40.338731 # ok 199 write_default.LCALTA.32
1985 03:34:40.343753 # ok 200 write_valid.LCALTA.32
1986 03:34:40.344300 # ok 201 write_invalid.LCALTA.32
1987 03:34:40.349342 # ok 202 event_missing.LCALTA.32
1988 03:34:40.349865 # ok 203 event_spurious.LCALTA.32
1989 03:34:40.354903 # ok 204 get_value.LCALTA.31
1990 03:34:40.355408 # # LCALTA.31 FRDDR_A SINK 2 SEL
1991 03:34:40.360407 # ok 205 name.LCALTA.31
1992 03:34:40.360906 # ok 206 write_default.LCALTA.31
1993 03:34:40.366009 # ok 207 write_valid.LCALTA.31
1994 03:34:40.366507 # ok 208 write_invalid.LCALTA.31
1995 03:34:40.371541 # ok 209 event_missing.LCALTA.31
1996 03:34:40.372085 # ok 210 event_spurious.LCALTA.31
1997 03:34:40.377048 # ok 211 get_value.LCALTA.30
1998 03:34:40.377550 # # LCALTA.30 FRDDR_A SINK 1 SEL
1999 03:34:40.382630 # ok 212 name.LCALTA.30
2000 03:34:40.383137 # ok 213 write_default.LCALTA.30
2001 03:34:40.388217 # ok 214 write_valid.LCALTA.30
2002 03:34:40.388726 # ok 215 write_invalid.LCALTA.30
2003 03:34:40.393759 # ok 216 event_missing.LCALTA.30
2004 03:34:40.394257 # ok 217 event_spurious.LCALTA.30
2005 03:34:40.399235 # ok 218 get_value.LCALTA.29
2006 03:34:40.404821 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2007 03:34:40.405326 # ok 219 name.LCALTA.29
2008 03:34:40.405775 # ok 220 write_default.LCALTA.29
2009 03:34:40.410382 # ok 221 write_valid.LCALTA.29
2010 03:34:40.415936 # ok 222 write_invalid.LCALTA.29
2011 03:34:40.416508 # ok 223 event_missing.LCALTA.29
2012 03:34:40.421458 # ok 224 event_spurious.LCALTA.29
2013 03:34:40.421962 # ok 225 get_value.LCALTA.28
2014 03:34:40.426995 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2015 03:34:40.427500 # ok 226 name.LCALTA.28
2016 03:34:40.432519 # ok 227 write_default.LCALTA.28
2017 03:34:40.433024 # ok 228 write_valid.LCALTA.28
2018 03:34:40.438067 # ok 229 write_invalid.LCALTA.28
2019 03:34:40.438567 # ok 230 event_missing.LCALTA.28
2020 03:34:40.443629 # ok 231 event_spurious.LCALTA.28
2021 03:34:40.444176 # ok 232 get_value.LCALTA.27
2022 03:34:40.449184 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2023 03:34:40.449696 # ok 233 name.LCALTA.27
2024 03:34:40.454749 # ok 234 write_default.LCALTA.27
2025 03:34:40.455253 # ok 235 write_valid.LCALTA.27
2026 03:34:40.460275 # ok 236 write_invalid.LCALTA.27
2027 03:34:40.460779 # ok 237 event_missing.LCALTA.27
2028 03:34:40.465805 # ok 238 event_spurious.LCALTA.27
2029 03:34:40.466318 # ok 239 get_value.LCALTA.26
2030 03:34:40.471401 # # LCALTA.26 ELD
2031 03:34:40.471927 # ok 240 name.LCALTA.26
2032 03:34:40.472417 # # ELD is not writeable
2033 03:34:40.476885 # ok 241 # SKIP write_default.LCALTA.26
2034 03:34:40.477386 # # ELD is not writeable
2035 03:34:40.482412 # ok 242 # SKIP write_valid.LCALTA.26
2036 03:34:40.482911 # # ELD is not writeable
2037 03:34:40.488026 # ok 243 # SKIP write_invalid.LCALTA.26
2038 03:34:40.493537 # ok 244 event_missing.LCALTA.26
2039 03:34:40.494042 # ok 245 event_spurious.LCALTA.26
2040 03:34:40.499089 # ok 246 get_value.LCALTA.25
2041 03:34:40.499595 # # LCALTA.25 IEC958 Playback Default
2042 03:34:40.504633 # ok 247 name.LCALTA.25
2043 03:34:40.505169 # ok 248 write_default.LCALTA.25
2044 03:34:40.510188 # ok 249 # SKIP write_valid.LCALTA.25
2045 03:34:40.510707 # ok 250 # SKIP write_invalid.LCALTA.25
2046 03:34:40.515742 # ok 251 event_missing.LCALTA.25
2047 03:34:40.516288 # ok 252 event_spurious.LCALTA.25
2048 03:34:40.521297 # ok 253 get_value.LCALTA.24
2049 03:34:40.526858 # # LCALTA.24 IEC958 Playback Mask
2050 03:34:40.527376 # ok 254 name.LCALTA.24
2051 03:34:40.532422 # # IEC958 Playback Mask is not writeable
2052 03:34:40.532970 # ok 255 # SKIP write_default.LCALTA.24
2053 03:34:40.537947 # # IEC958 Playback Mask is not writeable
2054 03:34:40.543507 # ok 256 # SKIP write_valid.LCALTA.24
2055 03:34:40.544065 # # IEC958 Playback Mask is not writeable
2056 03:34:40.549030 # ok 257 # SKIP write_invalid.LCALTA.24
2057 03:34:40.549544 # ok 258 event_missing.LCALTA.24
2058 03:34:40.554580 # ok 259 event_spurious.LCALTA.24
2059 03:34:40.555100 # ok 260 get_value.LCALTA.23
2060 03:34:40.560134 # # LCALTA.23 Playback Channel Map
2061 03:34:40.560651 # ok 261 name.LCALTA.23
2062 03:34:40.565667 # # Playback Channel Map is not writeable
2063 03:34:40.571178 # ok 262 # SKIP write_default.LCALTA.23
2064 03:34:40.571687 # # Playback Channel Map is not writeable
2065 03:34:40.576815 # ok 263 # SKIP write_valid.LCALTA.23
2066 03:34:40.582313 # # Playback Channel Map is not writeable
2067 03:34:40.582822 # ok 264 # SKIP write_invalid.LCALTA.23
2068 03:34:40.587860 # ok 265 event_missing.LCALTA.23
2069 03:34:40.588400 # ok 266 event_spurious.LCALTA.23
2070 03:34:40.593374 # ok 267 get_value.LCALTA.22
2071 03:34:40.593877 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2072 03:34:40.598913 # ok 268 name.LCALTA.22
2073 03:34:40.599435 # ok 269 write_default.LCALTA.22
2074 03:34:40.604494 # ok 270 write_valid.LCALTA.22
2075 03:34:40.605001 # ok 271 write_invalid.LCALTA.22
2076 03:34:40.610062 # ok 272 event_missing.LCALTA.22
2077 03:34:40.610581 # ok 273 event_spurious.LCALTA.22
2078 03:34:40.615584 # ok 274 get_value.LCALTA.21
2079 03:34:40.621143 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2080 03:34:40.621659 # ok 275 name.LCALTA.21
2081 03:34:40.622109 # ok 276 write_default.LCALTA.21
2082 03:34:40.626696 # ok 277 write_valid.LCALTA.21
2083 03:34:40.627219 # ok 278 write_invalid.LCALTA.21
2084 03:34:40.632253 # ok 279 event_missing.LCALTA.21
2085 03:34:40.637752 # ok 280 event_spurious.LCALTA.21
2086 03:34:40.638259 # ok 281 get_value.LCALTA.20
2087 03:34:40.643311 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2088 03:34:40.643813 # ok 282 name.LCALTA.20
2089 03:34:40.648857 # ok 283 write_default.LCALTA.20
2090 03:34:40.649363 # ok 284 write_valid.LCALTA.20
2091 03:34:40.654386 # ok 285 write_invalid.LCALTA.20
2092 03:34:40.654890 # ok 286 event_missing.LCALTA.20
2093 03:34:40.659926 # ok 287 event_spurious.LCALTA.20
2094 03:34:40.660464 # ok 288 get_value.LCALTA.19
2095 03:34:40.665504 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2096 03:34:40.666011 # ok 289 name.LCALTA.19
2097 03:34:40.671017 # ok 290 write_default.LCALTA.19
2098 03:34:40.671520 # ok 291 write_valid.LCALTA.19
2099 03:34:40.676573 # ok 292 write_invalid.LCALTA.19
2100 03:34:40.677071 # ok 293 event_missing.LCALTA.19
2101 03:34:40.682138 # ok 294 event_spurious.LCALTA.19
2102 03:34:40.682645 # ok 295 get_value.LCALTA.18
2103 03:34:40.687689 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2104 03:34:40.688237 # ok 296 name.LCALTA.18
2105 03:34:40.693238 # ok 297 write_default.LCALTA.18
2106 03:34:40.693737 # ok 298 write_valid.LCALTA.18
2107 03:34:40.698774 # ok 299 write_invalid.LCALTA.18
2108 03:34:40.699274 # ok 300 event_missing.LCALTA.18
2109 03:34:40.704337 # ok 301 event_spurious.LCALTA.18
2110 03:34:40.704865 # ok 302 get_value.LCALTA.17
2111 03:34:40.709898 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2112 03:34:40.710408 # ok 303 name.LCALTA.17
2113 03:34:40.715425 # ok 304 write_default.LCALTA.17
2114 03:34:40.715929 # ok 305 write_valid.LCALTA.17
2115 03:34:40.720969 # ok 306 write_invalid.LCALTA.17
2116 03:34:40.721477 # ok 307 event_missing.LCALTA.17
2117 03:34:40.726536 # ok 308 event_spurious.LCALTA.17
2118 03:34:40.727049 # ok 309 get_value.LCALTA.16
2119 03:34:40.732083 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2120 03:34:40.732602 # ok 310 name.LCALTA.16
2121 03:34:40.737585 # ok 311 write_default.LCALTA.16
2122 03:34:40.743142 # ok 312 write_valid.LCALTA.16
2123 03:34:40.743653 # ok 313 write_invalid.LCALTA.16
2124 03:34:40.748724 # ok 314 event_missing.LCALTA.16
2125 03:34:40.749229 # ok 315 event_spurious.LCALTA.16
2126 03:34:40.754230 # ok 316 get_value.LCALTA.15
2127 03:34:40.754737 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2128 03:34:40.759778 # ok 317 name.LCALTA.15
2129 03:34:40.760314 # ok 318 write_default.LCALTA.15
2130 03:34:40.765352 # ok 319 write_valid.LCALTA.15
2131 03:34:40.765858 # ok 320 write_invalid.LCALTA.15
2132 03:34:40.770897 # ok 321 event_missing.LCALTA.15
2133 03:34:40.771402 # ok 322 event_spurious.LCALTA.15
2134 03:34:40.776400 # ok 323 get_value.LCALTA.14
2135 03:34:40.776903 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2136 03:34:40.781955 # ok 324 name.LCALTA.14
2137 03:34:40.782454 # ok 325 write_default.LCALTA.14
2138 03:34:40.787517 # ok 326 write_valid.LCALTA.14
2139 03:34:40.788062 # ok 327 write_invalid.LCALTA.14
2140 03:34:40.793066 # ok 328 event_missing.LCALTA.14
2141 03:34:40.793584 # ok 329 event_spurious.LCALTA.14
2142 03:34:40.798622 # ok 330 get_value.LCALTA.13
2143 03:34:40.799127 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2144 03:34:40.804188 # ok 331 name.LCALTA.13
2145 03:34:40.804697 # ok 332 write_default.LCALTA.13
2146 03:34:40.809739 # ok 333 write_valid.LCALTA.13
2147 03:34:40.810241 # ok 334 write_invalid.LCALTA.13
2148 03:34:40.815274 # ok 335 event_missing.LCALTA.13
2149 03:34:40.815774 # ok 336 event_spurious.LCALTA.13
2150 03:34:40.820777 # ok 337 get_value.LCALTA.12
2151 03:34:40.826335 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2152 03:34:40.826837 # ok 338 name.LCALTA.12
2153 03:34:40.827283 # ok 339 write_default.LCALTA.12
2154 03:34:40.831898 # ok 340 write_valid.LCALTA.12
2155 03:34:40.832425 # ok 341 write_invalid.LCALTA.12
2156 03:34:40.837416 # ok 342 event_missing.LCALTA.12
2157 03:34:40.842979 # ok 343 event_spurious.LCALTA.12
2158 03:34:40.843475 # ok 344 get_value.LCALTA.11
2159 03:34:40.848555 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2160 03:34:40.849062 # ok 345 name.LCALTA.11
2161 03:34:40.854085 # ok 346 write_default.LCALTA.11
2162 03:34:40.854585 # ok 347 write_valid.LCALTA.11
2163 03:34:40.859592 # ok 348 write_invalid.LCALTA.11
2164 03:34:40.860129 # ok 349 event_missing.LCALTA.11
2165 03:34:40.865180 # ok 350 event_spurious.LCALTA.11
2166 03:34:40.865676 # ok 351 get_value.LCALTA.10
2167 03:34:40.870725 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2168 03:34:40.871222 # ok 352 name.LCALTA.10
2169 03:34:40.876305 # ok 353 write_default.LCALTA.10
2170 03:34:40.876824 # ok 354 write_valid.LCALTA.10
2171 03:34:40.881792 # ok 355 write_invalid.LCALTA.10
2172 03:34:40.882289 # ok 356 event_missing.LCALTA.10
2173 03:34:40.887363 # ok 357 event_spurious.LCALTA.10
2174 03:34:40.887866 # ok 358 get_value.LCALTA.9
2175 03:34:40.892929 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2176 03:34:40.893430 # ok 359 name.LCALTA.9
2177 03:34:40.898430 # ok 360 write_default.LCALTA.9
2178 03:34:40.898930 # ok 361 write_valid.LCALTA.9
2179 03:34:40.904013 # ok 362 write_invalid.LCALTA.9
2180 03:34:40.904511 # ok 363 event_missing.LCALTA.9
2181 03:34:40.909560 # ok 364 event_spurious.LCALTA.9
2182 03:34:40.910059 # ok 365 get_value.LCALTA.8
2183 03:34:40.915076 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2184 03:34:40.915573 # ok 366 name.LCALTA.8
2185 03:34:40.920616 # ok 367 write_default.LCALTA.8
2186 03:34:40.921114 # ok 368 write_valid.LCALTA.8
2187 03:34:40.926186 # ok 369 write_invalid.LCALTA.8
2188 03:34:40.926681 # ok 370 event_missing.LCALTA.8
2189 03:34:40.931721 # ok 371 event_spurious.LCALTA.8
2190 03:34:40.932251 # ok 372 get_value.LCALTA.7
2191 03:34:40.937247 # # LCALTA.7 ACODEC Unmute Ramp Switch
2192 03:34:40.937748 # ok 373 name.LCALTA.7
2193 03:34:40.942828 # ok 374 write_default.LCALTA.7
2194 03:34:40.943321 # ok 375 write_valid.LCALTA.7
2195 03:34:40.948379 # ok 376 write_invalid.LCALTA.7
2196 03:34:40.948879 # ok 377 event_missing.LCALTA.7
2197 03:34:40.953914 # ok 378 event_spurious.LCALTA.7
2198 03:34:40.954413 # ok 379 get_value.LCALTA.6
2199 03:34:40.959430 # # LCALTA.6 ACODEC Mute Ramp Switch
2200 03:34:40.959928 # ok 380 name.LCALTA.6
2201 03:34:40.965014 # ok 381 write_default.LCALTA.6
2202 03:34:40.965515 # ok 382 write_valid.LCALTA.6
2203 03:34:40.970568 # ok 383 write_invalid.LCALTA.6
2204 03:34:40.971066 # ok 384 event_missing.LCALTA.6
2205 03:34:40.976102 # ok 385 event_spurious.LCALTA.6
2206 03:34:40.976600 # ok 386 get_value.LCALTA.5
2207 03:34:40.981622 # # LCALTA.5 ACODEC Volume Ramp Switch
2208 03:34:40.982115 # ok 387 name.LCALTA.5
2209 03:34:40.987212 # ok 388 write_default.LCALTA.5
2210 03:34:40.987712 # ok 389 write_valid.LCALTA.5
2211 03:34:40.992721 # ok 390 write_invalid.LCALTA.5
2212 03:34:40.993217 # ok 391 event_missing.LCALTA.5
2213 03:34:40.998263 # ok 392 event_spurious.LCALTA.5
2214 03:34:40.998756 # ok 393 get_value.LCALTA.4
2215 03:34:41.003833 # # LCALTA.4 ACODEC Ramp Rate
2216 03:34:41.004360 # ok 394 name.LCALTA.4
2217 03:34:41.009381 # ok 395 write_default.LCALTA.4
2218 03:34:41.009881 # ok 396 write_valid.LCALTA.4
2219 03:34:41.014957 # ok 397 write_invalid.LCALTA.4
2220 03:34:41.015453 # ok 398 event_missing.LCALTA.4
2221 03:34:41.020531 # ok 399 event_spurious.LCALTA.4
2222 03:34:41.021097 # ok 400 get_value.LCALTA.3
2223 03:34:41.026069 # # LCALTA.3 ACODEC Playback Volume
2224 03:34:41.026628 # ok 401 name.LCALTA.3
2225 03:34:41.031619 # ok 402 write_default.LCALTA.3
2226 03:34:41.032185 # ok 403 write_valid.LCALTA.3
2227 03:34:41.037106 # ok 404 write_invalid.LCALTA.3
2228 03:34:41.037608 # ok 405 event_missing.LCALTA.3
2229 03:34:41.042635 # ok 406 event_spurious.LCALTA.3
2230 03:34:41.043135 # ok 407 get_value.LCALTA.2
2231 03:34:41.048291 # # LCALTA.2 ACODEC Playback Switch
2232 03:34:41.048798 # ok 408 name.LCALTA.2
2233 03:34:41.049245 # ok 409 write_default.LCALTA.2
2234 03:34:41.053741 # ok 410 write_valid.LCALTA.2
2235 03:34:41.054238 # ok 411 write_invalid.LCALTA.2
2236 03:34:41.059277 # ok 412 event_missing.LCALTA.2
2237 03:34:41.064854 # ok 413 event_spurious.LCALTA.2
2238 03:34:41.065354 # ok 414 get_value.LCALTA.1
2239 03:34:41.070380 # # LCALTA.1 ACODEC Playback Channel Mode
2240 03:34:41.070882 # ok 415 name.LCALTA.1
2241 03:34:41.075928 # ok 416 write_default.LCALTA.1
2242 03:34:41.076451 # ok 417 write_valid.LCALTA.1
2243 03:34:41.081450 # ok 418 write_invalid.LCALTA.1
2244 03:34:41.081944 # ok 419 event_missing.LCALTA.1
2245 03:34:41.087005 # ok 420 event_spurious.LCALTA.1
2246 03:34:41.087501 # ok 421 get_value.LCALTA.0
2247 03:34:41.092581 # # LCALTA.0 TOACODEC Lane Select
2248 03:34:41.093085 # ok 422 name.LCALTA.0
2249 03:34:41.093532 # ok 423 write_default.LCALTA.0
2250 03:34:41.098108 # ok 424 write_valid.LCALTA.0
2251 03:34:41.098607 # ok 425 write_invalid.LCALTA.0
2252 03:34:41.103631 # ok 426 event_missing.LCALTA.0
2253 03:34:41.109298 # ok 427 event_spurious.LCALTA.0
2254 03:34:41.109800 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2255 03:34:41.114824 ok 1 selftests: alsa: mixer-test
2256 03:34:41.115325 # timeout set to 45
2257 03:34:41.120316 # selftests: alsa: pcm-test
2258 03:34:41.120817 # TAP version 13
2259 03:34:41.125866 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2260 03:34:41.126368 # # LCALTA.0 - fe.dai-link-0 (*)
2261 03:34:41.131419 # # LCALTA.0 - fe.dai-link-1 (*)
2262 03:34:41.131919 # # LCALTA.0 - fe.dai-link-2 (*)
2263 03:34:41.136959 # # LCALTA.0 - fe.dai-link-3 (*)
2264 03:34:41.137458 # # LCALTA.0 - fe.dai-link-4 (*)
2265 03:34:41.142521 # # LCALTA.0 - fe.dai-link-5 (*)
2266 03:34:41.143028 # 1..42
2267 03:34:41.148073 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2268 03:34:41.153609 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2269 03:34:41.154114 # # snd_pcm_hw_params: Invalid argument
2270 03:34:41.159127 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2271 03:34:41.164670 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2272 03:34:41.170241 # # snd_pcm_hw_params: Invalid argument
2273 03:34:41.175865 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2274 03:34:41.181324 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2275 03:34:41.181827 # # snd_pcm_hw_params: Invalid argument
2276 03:34:41.186918 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2277 03:34:41.192399 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2278 03:34:41.197964 # # snd_pcm_hw_params: Invalid argument
2279 03:34:41.203513 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2280 03:34:41.209075 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2281 03:34:41.209582 # # snd_pcm_hw_params: Invalid argument
2282 03:34:41.214597 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2283 03:34:41.220158 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2284 03:34:41.225712 # # snd_pcm_hw_params: Invalid argument
2285 03:34:41.231265 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2286 03:34:41.231769 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2287 03:34:41.236840 # # snd_pcm_hw_params: Invalid argument
2288 03:34:41.242322 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2289 03:34:41.247894 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2290 03:34:41.248422 # # snd_pcm_hw_params: Invalid argument
2291 03:34:41.258970 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2292 03:34:41.259488 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2293 03:34:41.264528 # # snd_pcm_hw_params: Invalid argument
2294 03:34:41.270076 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2295 03:34:41.275615 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2296 03:34:41.276156 # # snd_pcm_hw_params: Invalid argument
2297 03:34:41.281140 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2298 03:34:41.286696 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2299 03:34:41.292271 # # snd_pcm_hw_params: Invalid argument
2300 03:34:41.297843 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2301 03:34:41.303323 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2302 03:34:41.303820 # # snd_pcm_hw_params: Invalid argument
2303 03:34:41.308928 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2304 03:34:41.314464 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2305 03:34:41.320023 # # snd_pcm_hw_params: Invalid argument
2306 03:34:41.325546 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2307 03:34:41.331093 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2308 03:34:41.331594 # # snd_pcm_hw_params: Invalid argument
2309 03:34:41.336614 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2310 03:34:41.342151 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2311 03:34:41.347711 # # snd_pcm_hw_params: Invalid argument
2312 03:34:41.353274 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2313 03:34:41.353774 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2314 03:34:41.358852 # # snd_pcm_hw_params: Invalid argument
2315 03:34:41.364350 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2316 03:34:41.369918 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2317 03:34:41.375471 # # snd_pcm_hw_params: Invalid argument
2318 03:34:41.381022 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2319 03:34:41.381530 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2320 03:34:41.386553 # # snd_pcm_hw_params: Invalid argument
2321 03:34:41.392114 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2322 03:34:41.397644 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2323 03:34:41.398146 # # snd_pcm_hw_params: Invalid argument
2324 03:34:41.408711 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2325 03:34:41.409233 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2326 03:34:41.414300 # # snd_pcm_hw_params: Invalid argument
2327 03:34:41.419894 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2328 03:34:41.425354 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2329 03:34:41.425852 # # snd_pcm_hw_params: Invalid argument
2330 03:34:41.430945 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2331 03:34:41.436487 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2332 03:34:41.441988 # # snd_pcm_hw_params: Invalid argument
2333 03:34:41.447566 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2334 03:34:41.453136 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2335 03:34:41.453637 # # snd_pcm_hw_params: Invalid argument
2336 03:34:41.458647 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2337 03:34:41.464224 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2338 03:34:41.469759 # # snd_pcm_hw_params: Invalid argument
2339 03:34:41.475289 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2340 03:34:41.480859 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2341 03:34:41.481357 # # snd_pcm_hw_params: Invalid argument
2342 03:34:41.486402 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2343 03:34:41.491938 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2344 03:34:41.497500 # # snd_pcm_hw_params: Invalid argument
2345 03:34:41.503030 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2346 03:34:41.508598 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2347 03:34:41.509110 # # snd_pcm_hw_params: Invalid argument
2348 03:34:41.514167 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2349 03:34:41.519669 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2350 03:34:41.525232 # # snd_pcm_hw_params: Invalid argument
2351 03:34:41.530800 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2352 03:34:41.536325 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2353 03:34:41.536856 # # snd_pcm_hw_params: Invalid argument
2354 03:34:41.541907 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2355 03:34:41.547397 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2356 03:34:41.552978 # # snd_pcm_hw_params: Invalid argument
2357 03:34:41.558528 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2358 03:34:41.564101 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2359 03:34:41.564638 # # snd_pcm_hw_params: Invalid argument
2360 03:34:41.569614 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2361 03:34:41.575172 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2362 03:34:41.580713 # # snd_pcm_hw_params: Invalid argument
2363 03:34:41.586251 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2364 03:34:41.591773 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2365 03:34:41.592307 # # snd_pcm_hw_params: Invalid argument
2366 03:34:41.597345 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2367 03:34:41.602875 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2368 03:34:41.608411 # # snd_pcm_hw_params: Invalid argument
2369 03:34:41.613994 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2370 03:34:41.619525 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2371 03:34:41.620055 # # snd_pcm_hw_params: Invalid argument
2372 03:34:41.625062 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2373 03:34:41.630618 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2374 03:34:41.636194 # # snd_pcm_hw_params: Invalid argument
2375 03:34:41.641669 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2376 03:34:41.647249 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2377 03:34:41.647751 # # snd_pcm_hw_params: Invalid argument
2378 03:34:41.652809 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2379 03:34:41.658344 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2380 03:34:41.663878 # # snd_pcm_hw_params: Invalid argument
2381 03:34:41.669422 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2382 03:34:41.675004 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2383 03:34:41.675506 # # snd_pcm_hw_params: Invalid argument
2384 03:34:41.680525 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2385 03:34:41.686051 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2386 03:34:41.691629 # # snd_pcm_hw_params: Invalid argument
2387 03:34:41.697155 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2388 03:34:41.702677 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2389 03:34:41.703172 # # snd_pcm_hw_params: Invalid argument
2390 03:34:41.708253 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2391 03:34:41.713819 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2392 03:34:41.719344 # # snd_pcm_hw_params: Invalid argument
2393 03:34:41.724920 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2394 03:34:41.725419 ok 2 selftests: alsa: pcm-test
2395 03:34:41.725873 # timeout set to 45
2396 03:34:41.730457 # selftests: alsa: test-pcmtest-driver
2397 03:34:41.730955 # TAP version 13
2398 03:34:41.731409 # 1..5
2399 03:34:41.736051 # # Starting 5 tests from 1 test cases.
2400 03:34:41.741531 # # RUN pcmtest.playback ...
2401 03:34:41.747074 # # SKIP Can't read patterns. Probably, module isn't loaded
2402 03:34:41.747578 # # OK pcmtest.playback
2403 03:34:41.758114 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2404 03:34:41.758633 # # RUN pcmtest.capture ...
2405 03:34:41.763760 # # SKIP Can't read patterns. Probably, module isn't loaded
2406 03:34:41.769263 # # OK pcmtest.capture
2407 03:34:41.774842 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2408 03:34:41.780368 # # RUN pcmtest.ni_capture ...
2409 03:34:41.785929 # # SKIP Can't read patterns. Probably, module isn't loaded
2410 03:34:41.791455 # # OK pcmtest.ni_capture
2411 03:34:41.796991 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2412 03:34:41.802529 # # RUN pcmtest.ni_playback ...
2413 03:34:41.808120 # # SKIP Can't read patterns. Probably, module isn't loaded
2414 03:34:41.808638 # # OK pcmtest.ni_playback
2415 03:34:41.819145 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2416 03:34:41.819693 # # RUN pcmtest.reset_ioctl ...
2417 03:34:41.830225 # # SKIP Can't read patterns. Probably, module isn't loaded
2418 03:34:41.830774 # # OK pcmtest.reset_ioctl
2419 03:34:41.841297 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2420 03:34:41.841827 # # PASSED: 5 / 5 tests passed.
2421 03:34:41.846993 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2422 03:34:41.852567 ok 3 selftests: alsa: test-pcmtest-driver
2423 03:34:41.853143 # timeout set to 45
2424 03:34:41.853602 # selftests: alsa: utimer-test
2425 03:34:41.858078 # TAP version 13
2426 03:34:41.858622 # 1..2
2427 03:34:41.859074 # # Starting 2 tests from 2 test cases.
2428 03:34:41.863605 # # RUN global.wrong_timers_test ...
2429 03:34:41.869170 # # OK global.wrong_timers_test
2430 03:34:41.869756 # ok 1 global.wrong_timers_test
2431 03:34:41.874751 # # RUN timer_f.utimer ...
2432 03:34:41.885728 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2433 03:34:41.891372 # # utimer: Test terminated by assertion
2434 03:34:41.891950 # # FAIL timer_f.utimer
2435 03:34:41.896949 # not ok 2 timer_f.utimer
2436 03:34:41.897537 # # FAILED: 1 / 2 tests passed.
2437 03:34:41.902461 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2438 03:34:41.907528 not ok 4 selftests: alsa: utimer-test # exit=1
2439 03:34:42.407851 alsa_mixer-test_get_value_LCALTA_60 pass
2440 03:34:42.413556 alsa_mixer-test_name_LCALTA_60 pass
2441 03:34:42.414200 alsa_mixer-test_write_default_LCALTA_60 pass
2442 03:34:42.418952 alsa_mixer-test_write_valid_LCALTA_60 pass
2443 03:34:42.424402 alsa_mixer-test_write_invalid_LCALTA_60 pass
2444 03:34:42.429996 alsa_mixer-test_event_missing_LCALTA_60 pass
2445 03:34:42.430573 alsa_mixer-test_event_spurious_LCALTA_60 pass
2446 03:34:42.435501 alsa_mixer-test_get_value_LCALTA_59 pass
2447 03:34:42.441051 alsa_mixer-test_name_LCALTA_59 pass
2448 03:34:42.441624 alsa_mixer-test_write_default_LCALTA_59 pass
2449 03:34:42.446557 alsa_mixer-test_write_valid_LCALTA_59 pass
2450 03:34:42.452117 alsa_mixer-test_write_invalid_LCALTA_59 pass
2451 03:34:42.452690 alsa_mixer-test_event_missing_LCALTA_59 pass
2452 03:34:42.457658 alsa_mixer-test_event_spurious_LCALTA_59 pass
2453 03:34:42.463211 alsa_mixer-test_get_value_LCALTA_58 pass
2454 03:34:42.463781 alsa_mixer-test_name_LCALTA_58 pass
2455 03:34:42.468729 alsa_mixer-test_write_default_LCALTA_58 pass
2456 03:34:42.474287 alsa_mixer-test_write_valid_LCALTA_58 pass
2457 03:34:42.474856 alsa_mixer-test_write_invalid_LCALTA_58 pass
2458 03:34:42.479855 alsa_mixer-test_event_missing_LCALTA_58 pass
2459 03:34:42.485355 alsa_mixer-test_event_spurious_LCALTA_58 pass
2460 03:34:42.491000 alsa_mixer-test_get_value_LCALTA_57 pass
2461 03:34:42.491577 alsa_mixer-test_name_LCALTA_57 pass
2462 03:34:42.496607 alsa_mixer-test_write_default_LCALTA_57 pass
2463 03:34:42.502184 alsa_mixer-test_write_valid_LCALTA_57 pass
2464 03:34:42.502765 alsa_mixer-test_write_invalid_LCALTA_57 pass
2465 03:34:42.507662 alsa_mixer-test_event_missing_LCALTA_57 pass
2466 03:34:42.513217 alsa_mixer-test_event_spurious_LCALTA_57 pass
2467 03:34:42.513786 alsa_mixer-test_get_value_LCALTA_56 pass
2468 03:34:42.518746 alsa_mixer-test_name_LCALTA_56 pass
2469 03:34:42.524305 alsa_mixer-test_write_default_LCALTA_56 pass
2470 03:34:42.524831 alsa_mixer-test_write_valid_LCALTA_56 pass
2471 03:34:42.529824 alsa_mixer-test_write_invalid_LCALTA_56 pass
2472 03:34:42.535387 alsa_mixer-test_event_missing_LCALTA_56 pass
2473 03:34:42.540942 alsa_mixer-test_event_spurious_LCALTA_56 pass
2474 03:34:42.541469 alsa_mixer-test_get_value_LCALTA_55 pass
2475 03:34:42.546468 alsa_mixer-test_name_LCALTA_55 pass
2476 03:34:42.552080 alsa_mixer-test_write_default_LCALTA_55 pass
2477 03:34:42.552600 alsa_mixer-test_write_valid_LCALTA_55 pass
2478 03:34:42.557561 alsa_mixer-test_write_invalid_LCALTA_55 pass
2479 03:34:42.563118 alsa_mixer-test_event_missing_LCALTA_55 pass
2480 03:34:42.563657 alsa_mixer-test_event_spurious_LCALTA_55 pass
2481 03:34:42.568643 alsa_mixer-test_get_value_LCALTA_54 pass
2482 03:34:42.574188 alsa_mixer-test_name_LCALTA_54 pass
2483 03:34:42.574700 alsa_mixer-test_write_default_LCALTA_54 pass
2484 03:34:42.579729 alsa_mixer-test_write_valid_LCALTA_54 pass
2485 03:34:42.585292 alsa_mixer-test_write_invalid_LCALTA_54 pass
2486 03:34:42.585801 alsa_mixer-test_event_missing_LCALTA_54 pass
2487 03:34:42.590839 alsa_mixer-test_event_spurious_LCALTA_54 pass
2488 03:34:42.596370 alsa_mixer-test_get_value_LCALTA_53 pass
2489 03:34:42.596875 alsa_mixer-test_name_LCALTA_53 pass
2490 03:34:42.601924 alsa_mixer-test_write_default_LCALTA_53 pass
2491 03:34:42.607427 alsa_mixer-test_write_valid_LCALTA_53 pass
2492 03:34:42.613066 alsa_mixer-test_write_invalid_LCALTA_53 pass
2493 03:34:42.613574 alsa_mixer-test_event_missing_LCALTA_53 pass
2494 03:34:42.618580 alsa_mixer-test_event_spurious_LCALTA_53 pass
2495 03:34:42.624108 alsa_mixer-test_get_value_LCALTA_52 pass
2496 03:34:42.624615 alsa_mixer-test_name_LCALTA_52 pass
2497 03:34:42.629664 alsa_mixer-test_write_default_LCALTA_52 pass
2498 03:34:42.635219 alsa_mixer-test_write_valid_LCALTA_52 pass
2499 03:34:42.635736 alsa_mixer-test_write_invalid_LCALTA_52 pass
2500 03:34:42.640737 alsa_mixer-test_event_missing_LCALTA_52 pass
2501 03:34:42.646284 alsa_mixer-test_event_spurious_LCALTA_52 pass
2502 03:34:42.646793 alsa_mixer-test_get_value_LCALTA_51 pass
2503 03:34:42.651841 alsa_mixer-test_name_LCALTA_51 pass
2504 03:34:42.657386 alsa_mixer-test_write_default_LCALTA_51 pass
2505 03:34:42.657885 alsa_mixer-test_write_valid_LCALTA_51 pass
2506 03:34:42.662945 alsa_mixer-test_write_invalid_LCALTA_51 pass
2507 03:34:42.668473 alsa_mixer-test_event_missing_LCALTA_51 pass
2508 03:34:42.674044 alsa_mixer-test_event_spurious_LCALTA_51 pass
2509 03:34:42.674541 alsa_mixer-test_get_value_LCALTA_50 pass
2510 03:34:42.679580 alsa_mixer-test_name_LCALTA_50 pass
2511 03:34:42.685120 alsa_mixer-test_write_default_LCALTA_50 pass
2512 03:34:42.685622 alsa_mixer-test_write_valid_LCALTA_50 pass
2513 03:34:42.690673 alsa_mixer-test_write_invalid_LCALTA_50 pass
2514 03:34:42.696252 alsa_mixer-test_event_missing_LCALTA_50 pass
2515 03:34:42.696760 alsa_mixer-test_event_spurious_LCALTA_50 pass
2516 03:34:42.701766 alsa_mixer-test_get_value_LCALTA_49 pass
2517 03:34:42.707319 alsa_mixer-test_name_LCALTA_49 pass
2518 03:34:42.707824 alsa_mixer-test_write_default_LCALTA_49 pass
2519 03:34:42.712848 alsa_mixer-test_write_valid_LCALTA_49 pass
2520 03:34:42.718387 alsa_mixer-test_write_invalid_LCALTA_49 pass
2521 03:34:42.723959 alsa_mixer-test_event_missing_LCALTA_49 pass
2522 03:34:42.724491 alsa_mixer-test_event_spurious_LCALTA_49 pass
2523 03:34:42.729493 alsa_mixer-test_get_value_LCALTA_48 pass
2524 03:34:42.729996 alsa_mixer-test_name_LCALTA_48 pass
2525 03:34:42.735085 alsa_mixer-test_write_default_LCALTA_48 pass
2526 03:34:42.740572 alsa_mixer-test_write_valid_LCALTA_48 pass
2527 03:34:42.746137 alsa_mixer-test_write_invalid_LCALTA_48 pass
2528 03:34:42.746642 alsa_mixer-test_event_missing_LCALTA_48 pass
2529 03:34:42.751659 alsa_mixer-test_event_spurious_LCALTA_48 pass
2530 03:34:42.757229 alsa_mixer-test_get_value_LCALTA_47 pass
2531 03:34:42.757732 alsa_mixer-test_name_LCALTA_47 pass
2532 03:34:42.762784 alsa_mixer-test_write_default_LCALTA_47 pass
2533 03:34:42.768330 alsa_mixer-test_write_valid_LCALTA_47 pass
2534 03:34:42.768835 alsa_mixer-test_write_invalid_LCALTA_47 pass
2535 03:34:42.773864 alsa_mixer-test_event_missing_LCALTA_47 pass
2536 03:34:42.779417 alsa_mixer-test_event_spurious_LCALTA_47 pass
2537 03:34:42.784954 alsa_mixer-test_get_value_LCALTA_46 pass
2538 03:34:42.785459 alsa_mixer-test_name_LCALTA_46 pass
2539 03:34:42.790523 alsa_mixer-test_write_default_LCALTA_46 pass
2540 03:34:42.796095 alsa_mixer-test_write_valid_LCALTA_46 pass
2541 03:34:42.796605 alsa_mixer-test_write_invalid_LCALTA_46 pass
2542 03:34:42.801578 alsa_mixer-test_event_missing_LCALTA_46 pass
2543 03:34:42.807140 alsa_mixer-test_event_spurious_LCALTA_46 pass
2544 03:34:42.807643 alsa_mixer-test_get_value_LCALTA_45 pass
2545 03:34:42.812711 alsa_mixer-test_name_LCALTA_45 pass
2546 03:34:42.818235 alsa_mixer-test_write_default_LCALTA_45 pass
2547 03:34:42.818764 alsa_mixer-test_write_valid_LCALTA_45 pass
2548 03:34:42.823794 alsa_mixer-test_write_invalid_LCALTA_45 pass
2549 03:34:42.829345 alsa_mixer-test_event_missing_LCALTA_45 pass
2550 03:34:42.829848 alsa_mixer-test_event_spurious_LCALTA_45 pass
2551 03:34:42.834889 alsa_mixer-test_get_value_LCALTA_44 pass
2552 03:34:42.840402 alsa_mixer-test_name_LCALTA_44 pass
2553 03:34:42.840897 alsa_mixer-test_write_default_LCALTA_44 pass
2554 03:34:42.845974 alsa_mixer-test_write_valid_LCALTA_44 pass
2555 03:34:42.851510 alsa_mixer-test_write_invalid_LCALTA_44 pass
2556 03:34:42.857072 alsa_mixer-test_event_missing_LCALTA_44 pass
2557 03:34:42.857571 alsa_mixer-test_event_spurious_LCALTA_44 pass
2558 03:34:42.862615 alsa_mixer-test_get_value_LCALTA_43 pass
2559 03:34:42.868189 alsa_mixer-test_name_LCALTA_43 pass
2560 03:34:42.868690 alsa_mixer-test_write_default_LCALTA_43 pass
2561 03:34:42.873727 alsa_mixer-test_write_valid_LCALTA_43 pass
2562 03:34:42.879257 alsa_mixer-test_write_invalid_LCALTA_43 pass
2563 03:34:42.879763 alsa_mixer-test_event_missing_LCALTA_43 pass
2564 03:34:42.884798 alsa_mixer-test_event_spurious_LCALTA_43 pass
2565 03:34:42.890346 alsa_mixer-test_get_value_LCALTA_42 pass
2566 03:34:42.890852 alsa_mixer-test_name_LCALTA_42 pass
2567 03:34:42.895877 alsa_mixer-test_write_default_LCALTA_42 pass
2568 03:34:42.901441 alsa_mixer-test_write_valid_LCALTA_42 pass
2569 03:34:42.901942 alsa_mixer-test_write_invalid_LCALTA_42 pass
2570 03:34:42.906998 alsa_mixer-test_event_missing_LCALTA_42 pass
2571 03:34:42.912528 alsa_mixer-test_event_spurious_LCALTA_42 pass
2572 03:34:42.918091 alsa_mixer-test_get_value_LCALTA_41 pass
2573 03:34:42.918589 alsa_mixer-test_name_LCALTA_41 pass
2574 03:34:42.923635 alsa_mixer-test_write_default_LCALTA_41 pass
2575 03:34:42.929171 alsa_mixer-test_write_valid_LCALTA_41 pass
2576 03:34:42.929672 alsa_mixer-test_write_invalid_LCALTA_41 pass
2577 03:34:42.934720 alsa_mixer-test_event_missing_LCALTA_41 pass
2578 03:34:42.940281 alsa_mixer-test_event_spurious_LCALTA_41 pass
2579 03:34:42.940783 alsa_mixer-test_get_value_LCALTA_40 pass
2580 03:34:42.945818 alsa_mixer-test_name_LCALTA_40 pass
2581 03:34:42.951351 alsa_mixer-test_write_default_LCALTA_40 pass
2582 03:34:42.951858 alsa_mixer-test_write_valid_LCALTA_40 pass
2583 03:34:42.956912 alsa_mixer-test_write_invalid_LCALTA_40 pass
2584 03:34:42.962439 alsa_mixer-test_event_missing_LCALTA_40 pass
2585 03:34:42.968030 alsa_mixer-test_event_spurious_LCALTA_40 pass
2586 03:34:42.968533 alsa_mixer-test_get_value_LCALTA_39 pass
2587 03:34:42.973539 alsa_mixer-test_name_LCALTA_39 pass
2588 03:34:42.979105 alsa_mixer-test_write_default_LCALTA_39 pass
2589 03:34:42.979610 alsa_mixer-test_write_valid_LCALTA_39 pass
2590 03:34:42.984624 alsa_mixer-test_write_invalid_LCALTA_39 pass
2591 03:34:42.990192 alsa_mixer-test_event_missing_LCALTA_39 pass
2592 03:34:42.990695 alsa_mixer-test_event_spurious_LCALTA_39 pass
2593 03:34:42.995697 alsa_mixer-test_get_value_LCALTA_38 pass
2594 03:34:43.001244 alsa_mixer-test_name_LCALTA_38 pass
2595 03:34:43.001749 alsa_mixer-test_write_default_LCALTA_38 pass
2596 03:34:43.006797 alsa_mixer-test_write_valid_LCALTA_38 pass
2597 03:34:43.012333 alsa_mixer-test_write_invalid_LCALTA_38 pass
2598 03:34:43.012840 alsa_mixer-test_event_missing_LCALTA_38 pass
2599 03:34:43.017917 alsa_mixer-test_event_spurious_LCALTA_38 pass
2600 03:34:43.023563 alsa_mixer-test_get_value_LCALTA_37 pass
2601 03:34:43.024168 alsa_mixer-test_name_LCALTA_37 pass
2602 03:34:43.029055 alsa_mixer-test_write_default_LCALTA_37 pass
2603 03:34:43.034623 alsa_mixer-test_write_valid_LCALTA_37 pass
2604 03:34:43.040095 alsa_mixer-test_write_invalid_LCALTA_37 pass
2605 03:34:43.040595 alsa_mixer-test_event_missing_LCALTA_37 pass
2606 03:34:43.045600 alsa_mixer-test_event_spurious_LCALTA_37 pass
2607 03:34:43.051200 alsa_mixer-test_get_value_LCALTA_36 pass
2608 03:34:43.051707 alsa_mixer-test_name_LCALTA_36 pass
2609 03:34:43.056713 alsa_mixer-test_write_default_LCALTA_36 pass
2610 03:34:43.062243 alsa_mixer-test_write_valid_LCALTA_36 pass
2611 03:34:43.062742 alsa_mixer-test_write_invalid_LCALTA_36 pass
2612 03:34:43.067787 alsa_mixer-test_event_missing_LCALTA_36 pass
2613 03:34:43.073339 alsa_mixer-test_event_spurious_LCALTA_36 pass
2614 03:34:43.073844 alsa_mixer-test_get_value_LCALTA_35 pass
2615 03:34:43.078920 alsa_mixer-test_name_LCALTA_35 pass
2616 03:34:43.084437 alsa_mixer-test_write_default_LCALTA_35 pass
2617 03:34:43.084940 alsa_mixer-test_write_valid_LCALTA_35 pass
2618 03:34:43.089981 alsa_mixer-test_write_invalid_LCALTA_35 pass
2619 03:34:43.095514 alsa_mixer-test_event_missing_LCALTA_35 pass
2620 03:34:43.101127 alsa_mixer-test_event_spurious_LCALTA_35 pass
2621 03:34:43.101634 alsa_mixer-test_get_value_LCALTA_34 pass
2622 03:34:43.106660 alsa_mixer-test_name_LCALTA_34 pass
2623 03:34:43.112253 alsa_mixer-test_write_default_LCALTA_34 pass
2624 03:34:43.112760 alsa_mixer-test_write_valid_LCALTA_34 pass
2625 03:34:43.117747 alsa_mixer-test_write_invalid_LCALTA_34 pass
2626 03:34:43.123314 alsa_mixer-test_event_missing_LCALTA_34 pass
2627 03:34:43.123820 alsa_mixer-test_event_spurious_LCALTA_34 pass
2628 03:34:43.128845 alsa_mixer-test_get_value_LCALTA_33 pass
2629 03:34:43.134393 alsa_mixer-test_name_LCALTA_33 pass
2630 03:34:43.134897 alsa_mixer-test_write_default_LCALTA_33 pass
2631 03:34:43.139939 alsa_mixer-test_write_valid_LCALTA_33 pass
2632 03:34:43.145498 alsa_mixer-test_write_invalid_LCALTA_33 pass
2633 03:34:43.151011 alsa_mixer-test_event_missing_LCALTA_33 pass
2634 03:34:43.151512 alsa_mixer-test_event_spurious_LCALTA_33 pass
2635 03:34:43.156590 alsa_mixer-test_get_value_LCALTA_32 pass
2636 03:34:43.157096 alsa_mixer-test_name_LCALTA_32 pass
2637 03:34:43.162110 alsa_mixer-test_write_default_LCALTA_32 pass
2638 03:34:43.167633 alsa_mixer-test_write_valid_LCALTA_32 pass
2639 03:34:43.173167 alsa_mixer-test_write_invalid_LCALTA_32 pass
2640 03:34:43.173666 alsa_mixer-test_event_missing_LCALTA_32 pass
2641 03:34:43.178739 alsa_mixer-test_event_spurious_LCALTA_32 pass
2642 03:34:43.184302 alsa_mixer-test_get_value_LCALTA_31 pass
2643 03:34:43.184801 alsa_mixer-test_name_LCALTA_31 pass
2644 03:34:43.189860 alsa_mixer-test_write_default_LCALTA_31 pass
2645 03:34:43.195393 alsa_mixer-test_write_valid_LCALTA_31 pass
2646 03:34:43.195907 alsa_mixer-test_write_invalid_LCALTA_31 pass
2647 03:34:43.200943 alsa_mixer-test_event_missing_LCALTA_31 pass
2648 03:34:43.206494 alsa_mixer-test_event_spurious_LCALTA_31 pass
2649 03:34:43.212059 alsa_mixer-test_get_value_LCALTA_30 pass
2650 03:34:43.212555 alsa_mixer-test_name_LCALTA_30 pass
2651 03:34:43.217585 alsa_mixer-test_write_default_LCALTA_30 pass
2652 03:34:43.223120 alsa_mixer-test_write_valid_LCALTA_30 pass
2653 03:34:43.223612 alsa_mixer-test_write_invalid_LCALTA_30 pass
2654 03:34:43.228684 alsa_mixer-test_event_missing_LCALTA_30 pass
2655 03:34:43.234247 alsa_mixer-test_event_spurious_LCALTA_30 pass
2656 03:34:43.234751 alsa_mixer-test_get_value_LCALTA_29 pass
2657 03:34:43.239741 alsa_mixer-test_name_LCALTA_29 pass
2658 03:34:43.245272 alsa_mixer-test_write_default_LCALTA_29 pass
2659 03:34:43.245770 alsa_mixer-test_write_valid_LCALTA_29 pass
2660 03:34:43.250863 alsa_mixer-test_write_invalid_LCALTA_29 pass
2661 03:34:43.256457 alsa_mixer-test_event_missing_LCALTA_29 pass
2662 03:34:43.256977 alsa_mixer-test_event_spurious_LCALTA_29 pass
2663 03:34:43.261939 alsa_mixer-test_get_value_LCALTA_28 pass
2664 03:34:43.267503 alsa_mixer-test_name_LCALTA_28 pass
2665 03:34:43.268029 alsa_mixer-test_write_default_LCALTA_28 pass
2666 03:34:43.273035 alsa_mixer-test_write_valid_LCALTA_28 pass
2667 03:34:43.278578 alsa_mixer-test_write_invalid_LCALTA_28 pass
2668 03:34:43.284123 alsa_mixer-test_event_missing_LCALTA_28 pass
2669 03:34:43.284621 alsa_mixer-test_event_spurious_LCALTA_28 pass
2670 03:34:43.289672 alsa_mixer-test_get_value_LCALTA_27 pass
2671 03:34:43.295252 alsa_mixer-test_name_LCALTA_27 pass
2672 03:34:43.295770 alsa_mixer-test_write_default_LCALTA_27 pass
2673 03:34:43.300817 alsa_mixer-test_write_valid_LCALTA_27 pass
2674 03:34:43.306407 alsa_mixer-test_write_invalid_LCALTA_27 pass
2675 03:34:43.306948 alsa_mixer-test_event_missing_LCALTA_27 pass
2676 03:34:43.311923 alsa_mixer-test_event_spurious_LCALTA_27 pass
2677 03:34:43.317467 alsa_mixer-test_get_value_LCALTA_26 pass
2678 03:34:43.318024 alsa_mixer-test_name_LCALTA_26 pass
2679 03:34:43.322999 alsa_mixer-test_write_default_LCALTA_26 skip
2680 03:34:43.328523 alsa_mixer-test_write_valid_LCALTA_26 skip
2681 03:34:43.329033 alsa_mixer-test_write_invalid_LCALTA_26 skip
2682 03:34:43.334093 alsa_mixer-test_event_missing_LCALTA_26 pass
2683 03:34:43.339640 alsa_mixer-test_event_spurious_LCALTA_26 pass
2684 03:34:43.345222 alsa_mixer-test_get_value_LCALTA_25 pass
2685 03:34:43.345739 alsa_mixer-test_name_LCALTA_25 pass
2686 03:34:43.350728 alsa_mixer-test_write_default_LCALTA_25 pass
2687 03:34:43.356282 alsa_mixer-test_write_valid_LCALTA_25 skip
2688 03:34:43.356780 alsa_mixer-test_write_invalid_LCALTA_25 skip
2689 03:34:43.361789 alsa_mixer-test_event_missing_LCALTA_25 pass
2690 03:34:43.367331 alsa_mixer-test_event_spurious_LCALTA_25 pass
2691 03:34:43.367820 alsa_mixer-test_get_value_LCALTA_24 pass
2692 03:34:43.372884 alsa_mixer-test_name_LCALTA_24 pass
2693 03:34:43.378469 alsa_mixer-test_write_default_LCALTA_24 skip
2694 03:34:43.378988 alsa_mixer-test_write_valid_LCALTA_24 skip
2695 03:34:43.384023 alsa_mixer-test_write_invalid_LCALTA_24 skip
2696 03:34:43.389534 alsa_mixer-test_event_missing_LCALTA_24 pass
2697 03:34:43.395122 alsa_mixer-test_event_spurious_LCALTA_24 pass
2698 03:34:43.395616 alsa_mixer-test_get_value_LCALTA_23 pass
2699 03:34:43.400609 alsa_mixer-test_name_LCALTA_23 pass
2700 03:34:43.406176 alsa_mixer-test_write_default_LCALTA_23 skip
2701 03:34:43.406673 alsa_mixer-test_write_valid_LCALTA_23 skip
2702 03:34:43.411733 alsa_mixer-test_write_invalid_LCALTA_23 skip
2703 03:34:43.417375 alsa_mixer-test_event_missing_LCALTA_23 pass
2704 03:34:43.417935 alsa_mixer-test_event_spurious_LCALTA_23 pass
2705 03:34:43.422832 alsa_mixer-test_get_value_LCALTA_22 pass
2706 03:34:43.428374 alsa_mixer-test_name_LCALTA_22 pass
2707 03:34:43.428871 alsa_mixer-test_write_default_LCALTA_22 pass
2708 03:34:43.433922 alsa_mixer-test_write_valid_LCALTA_22 pass
2709 03:34:43.439459 alsa_mixer-test_write_invalid_LCALTA_22 pass
2710 03:34:43.439957 alsa_mixer-test_event_missing_LCALTA_22 pass
2711 03:34:43.445018 alsa_mixer-test_event_spurious_LCALTA_22 pass
2712 03:34:43.450553 alsa_mixer-test_get_value_LCALTA_21 pass
2713 03:34:43.451054 alsa_mixer-test_name_LCALTA_21 pass
2714 03:34:43.456195 alsa_mixer-test_write_default_LCALTA_21 pass
2715 03:34:43.461643 alsa_mixer-test_write_valid_LCALTA_21 pass
2716 03:34:43.467217 alsa_mixer-test_write_invalid_LCALTA_21 pass
2717 03:34:43.467710 alsa_mixer-test_event_missing_LCALTA_21 pass
2718 03:34:43.472725 alsa_mixer-test_event_spurious_LCALTA_21 pass
2719 03:34:43.478269 alsa_mixer-test_get_value_LCALTA_20 pass
2720 03:34:43.478772 alsa_mixer-test_name_LCALTA_20 pass
2721 03:34:43.483844 alsa_mixer-test_write_default_LCALTA_20 pass
2722 03:34:43.489423 alsa_mixer-test_write_valid_LCALTA_20 pass
2723 03:34:43.489973 alsa_mixer-test_write_invalid_LCALTA_20 pass
2724 03:34:43.494984 alsa_mixer-test_event_missing_LCALTA_20 pass
2725 03:34:43.500534 alsa_mixer-test_event_spurious_LCALTA_20 pass
2726 03:34:43.501086 alsa_mixer-test_get_value_LCALTA_19 pass
2727 03:34:43.506046 alsa_mixer-test_name_LCALTA_19 pass
2728 03:34:43.511555 alsa_mixer-test_write_default_LCALTA_19 pass
2729 03:34:43.512122 alsa_mixer-test_write_valid_LCALTA_19 pass
2730 03:34:43.517223 alsa_mixer-test_write_invalid_LCALTA_19 pass
2731 03:34:43.522729 alsa_mixer-test_event_missing_LCALTA_19 pass
2732 03:34:43.528290 alsa_mixer-test_event_spurious_LCALTA_19 pass
2733 03:34:43.528849 alsa_mixer-test_get_value_LCALTA_18 pass
2734 03:34:43.533811 alsa_mixer-test_name_LCALTA_18 pass
2735 03:34:43.539364 alsa_mixer-test_write_default_LCALTA_18 pass
2736 03:34:43.539921 alsa_mixer-test_write_valid_LCALTA_18 pass
2737 03:34:43.544917 alsa_mixer-test_write_invalid_LCALTA_18 pass
2738 03:34:43.550449 alsa_mixer-test_event_missing_LCALTA_18 pass
2739 03:34:43.550989 alsa_mixer-test_event_spurious_LCALTA_18 pass
2740 03:34:43.555970 alsa_mixer-test_get_value_LCALTA_17 pass
2741 03:34:43.561540 alsa_mixer-test_name_LCALTA_17 pass
2742 03:34:43.562091 alsa_mixer-test_write_default_LCALTA_17 pass
2743 03:34:43.567116 alsa_mixer-test_write_valid_LCALTA_17 pass
2744 03:34:43.572624 alsa_mixer-test_write_invalid_LCALTA_17 pass
2745 03:34:43.578250 alsa_mixer-test_event_missing_LCALTA_17 pass
2746 03:34:43.578804 alsa_mixer-test_event_spurious_LCALTA_17 pass
2747 03:34:43.583720 alsa_mixer-test_get_value_LCALTA_16 pass
2748 03:34:43.584304 alsa_mixer-test_name_LCALTA_16 pass
2749 03:34:43.589303 alsa_mixer-test_write_default_LCALTA_16 pass
2750 03:34:43.594811 alsa_mixer-test_write_valid_LCALTA_16 pass
2751 03:34:43.600361 alsa_mixer-test_write_invalid_LCALTA_16 pass
2752 03:34:43.600932 alsa_mixer-test_event_missing_LCALTA_16 pass
2753 03:34:43.605934 alsa_mixer-test_event_spurious_LCALTA_16 pass
2754 03:34:43.611480 alsa_mixer-test_get_value_LCALTA_15 pass
2755 03:34:43.612053 alsa_mixer-test_name_LCALTA_15 pass
2756 03:34:43.617005 alsa_mixer-test_write_default_LCALTA_15 pass
2757 03:34:43.622549 alsa_mixer-test_write_valid_LCALTA_15 pass
2758 03:34:43.623099 alsa_mixer-test_write_invalid_LCALTA_15 pass
2759 03:34:43.628108 alsa_mixer-test_event_missing_LCALTA_15 pass
2760 03:34:43.633650 alsa_mixer-test_event_spurious_LCALTA_15 pass
2761 03:34:43.639242 alsa_mixer-test_get_value_LCALTA_14 pass
2762 03:34:43.639783 alsa_mixer-test_name_LCALTA_14 pass
2763 03:34:43.644737 alsa_mixer-test_write_default_LCALTA_14 pass
2764 03:34:43.650280 alsa_mixer-test_write_valid_LCALTA_14 pass
2765 03:34:43.650813 alsa_mixer-test_write_invalid_LCALTA_14 pass
2766 03:34:43.655826 alsa_mixer-test_event_missing_LCALTA_14 pass
2767 03:34:43.661363 alsa_mixer-test_event_spurious_LCALTA_14 pass
2768 03:34:43.661906 alsa_mixer-test_get_value_LCALTA_13 pass
2769 03:34:43.666922 alsa_mixer-test_name_LCALTA_13 pass
2770 03:34:43.672479 alsa_mixer-test_write_default_LCALTA_13 pass
2771 03:34:43.673017 alsa_mixer-test_write_valid_LCALTA_13 pass
2772 03:34:43.678030 alsa_mixer-test_write_invalid_LCALTA_13 pass
2773 03:34:43.683556 alsa_mixer-test_event_missing_LCALTA_13 pass
2774 03:34:43.684134 alsa_mixer-test_event_spurious_LCALTA_13 pass
2775 03:34:43.689105 alsa_mixer-test_get_value_LCALTA_12 pass
2776 03:34:43.694648 alsa_mixer-test_name_LCALTA_12 pass
2777 03:34:43.695188 alsa_mixer-test_write_default_LCALTA_12 pass
2778 03:34:43.700277 alsa_mixer-test_write_valid_LCALTA_12 pass
2779 03:34:43.705737 alsa_mixer-test_write_invalid_LCALTA_12 pass
2780 03:34:43.711297 alsa_mixer-test_event_missing_LCALTA_12 pass
2781 03:34:43.711842 alsa_mixer-test_event_spurious_LCALTA_12 pass
2782 03:34:43.716842 alsa_mixer-test_get_value_LCALTA_11 pass
2783 03:34:43.722389 alsa_mixer-test_name_LCALTA_11 pass
2784 03:34:43.722946 alsa_mixer-test_write_default_LCALTA_11 pass
2785 03:34:43.727931 alsa_mixer-test_write_valid_LCALTA_11 pass
2786 03:34:43.733485 alsa_mixer-test_write_invalid_LCALTA_11 pass
2787 03:34:43.734016 alsa_mixer-test_event_missing_LCALTA_11 pass
2788 03:34:43.739051 alsa_mixer-test_event_spurious_LCALTA_11 pass
2789 03:34:43.744584 alsa_mixer-test_get_value_LCALTA_10 pass
2790 03:34:43.745133 alsa_mixer-test_name_LCALTA_10 pass
2791 03:34:43.750133 alsa_mixer-test_write_default_LCALTA_10 pass
2792 03:34:43.755670 alsa_mixer-test_write_valid_LCALTA_10 pass
2793 03:34:43.756244 alsa_mixer-test_write_invalid_LCALTA_10 pass
2794 03:34:43.761261 alsa_mixer-test_event_missing_LCALTA_10 pass
2795 03:34:43.766761 alsa_mixer-test_event_spurious_LCALTA_10 pass
2796 03:34:43.772326 alsa_mixer-test_get_value_LCALTA_9 pass
2797 03:34:43.772869 alsa_mixer-test_name_LCALTA_9 pass
2798 03:34:43.777861 alsa_mixer-test_write_default_LCALTA_9 pass
2799 03:34:43.783389 alsa_mixer-test_write_valid_LCALTA_9 pass
2800 03:34:43.783930 alsa_mixer-test_write_invalid_LCALTA_9 pass
2801 03:34:43.788920 alsa_mixer-test_event_missing_LCALTA_9 pass
2802 03:34:43.794466 alsa_mixer-test_event_spurious_LCALTA_9 pass
2803 03:34:43.794999 alsa_mixer-test_get_value_LCALTA_8 pass
2804 03:34:43.800029 alsa_mixer-test_name_LCALTA_8 pass
2805 03:34:43.805566 alsa_mixer-test_write_default_LCALTA_8 pass
2806 03:34:43.806108 alsa_mixer-test_write_valid_LCALTA_8 pass
2807 03:34:43.811164 alsa_mixer-test_write_invalid_LCALTA_8 pass
2808 03:34:43.816669 alsa_mixer-test_event_missing_LCALTA_8 pass
2809 03:34:43.817211 alsa_mixer-test_event_spurious_LCALTA_8 pass
2810 03:34:43.822274 alsa_mixer-test_get_value_LCALTA_7 pass
2811 03:34:43.827776 alsa_mixer-test_name_LCALTA_7 pass
2812 03:34:43.828348 alsa_mixer-test_write_default_LCALTA_7 pass
2813 03:34:43.833329 alsa_mixer-test_write_valid_LCALTA_7 pass
2814 03:34:43.838873 alsa_mixer-test_write_invalid_LCALTA_7 pass
2815 03:34:43.839415 alsa_mixer-test_event_missing_LCALTA_7 pass
2816 03:34:43.844423 alsa_mixer-test_event_spurious_LCALTA_7 pass
2817 03:34:43.849956 alsa_mixer-test_get_value_LCALTA_6 pass
2818 03:34:43.850497 alsa_mixer-test_name_LCALTA_6 pass
2819 03:34:43.855520 alsa_mixer-test_write_default_LCALTA_6 pass
2820 03:34:43.861057 alsa_mixer-test_write_valid_LCALTA_6 pass
2821 03:34:43.861600 alsa_mixer-test_write_invalid_LCALTA_6 pass
2822 03:34:43.866576 alsa_mixer-test_event_missing_LCALTA_6 pass
2823 03:34:43.872118 alsa_mixer-test_event_spurious_LCALTA_6 pass
2824 03:34:43.872644 alsa_mixer-test_get_value_LCALTA_5 pass
2825 03:34:43.877692 alsa_mixer-test_name_LCALTA_5 pass
2826 03:34:43.883223 alsa_mixer-test_write_default_LCALTA_5 pass
2827 03:34:43.883751 alsa_mixer-test_write_valid_LCALTA_5 pass
2828 03:34:43.888755 alsa_mixer-test_write_invalid_LCALTA_5 pass
2829 03:34:43.894373 alsa_mixer-test_event_missing_LCALTA_5 pass
2830 03:34:43.894972 alsa_mixer-test_event_spurious_LCALTA_5 pass
2831 03:34:43.899950 alsa_mixer-test_get_value_LCALTA_4 pass
2832 03:34:43.905394 alsa_mixer-test_name_LCALTA_4 pass
2833 03:34:43.905939 alsa_mixer-test_write_default_LCALTA_4 pass
2834 03:34:43.910979 alsa_mixer-test_write_valid_LCALTA_4 pass
2835 03:34:43.916513 alsa_mixer-test_write_invalid_LCALTA_4 pass
2836 03:34:43.917057 alsa_mixer-test_event_missing_LCALTA_4 pass
2837 03:34:43.922069 alsa_mixer-test_event_spurious_LCALTA_4 pass
2838 03:34:43.927618 alsa_mixer-test_get_value_LCALTA_3 pass
2839 03:34:43.928191 alsa_mixer-test_name_LCALTA_3 pass
2840 03:34:43.933134 alsa_mixer-test_write_default_LCALTA_3 pass
2841 03:34:43.938683 alsa_mixer-test_write_valid_LCALTA_3 pass
2842 03:34:43.939189 alsa_mixer-test_write_invalid_LCALTA_3 pass
2843 03:34:43.944279 alsa_mixer-test_event_missing_LCALTA_3 pass
2844 03:34:43.949762 alsa_mixer-test_event_spurious_LCALTA_3 pass
2845 03:34:43.950278 alsa_mixer-test_get_value_LCALTA_2 pass
2846 03:34:43.955308 alsa_mixer-test_name_LCALTA_2 pass
2847 03:34:43.960866 alsa_mixer-test_write_default_LCALTA_2 pass
2848 03:34:43.961372 alsa_mixer-test_write_valid_LCALTA_2 pass
2849 03:34:43.966420 alsa_mixer-test_write_invalid_LCALTA_2 pass
2850 03:34:43.971967 alsa_mixer-test_event_missing_LCALTA_2 pass
2851 03:34:43.977499 alsa_mixer-test_event_spurious_LCALTA_2 pass
2852 03:34:43.978016 alsa_mixer-test_get_value_LCALTA_1 pass
2853 03:34:43.983052 alsa_mixer-test_name_LCALTA_1 pass
2854 03:34:43.983565 alsa_mixer-test_write_default_LCALTA_1 pass
2855 03:34:43.988627 alsa_mixer-test_write_valid_LCALTA_1 pass
2856 03:34:43.994123 alsa_mixer-test_write_invalid_LCALTA_1 pass
2857 03:34:43.999640 alsa_mixer-test_event_missing_LCALTA_1 pass
2858 03:34:44.000171 alsa_mixer-test_event_spurious_LCALTA_1 pass
2859 03:34:44.005222 alsa_mixer-test_get_value_LCALTA_0 pass
2860 03:34:44.005727 alsa_mixer-test_name_LCALTA_0 pass
2861 03:34:44.010777 alsa_mixer-test_write_default_LCALTA_0 pass
2862 03:34:44.016301 alsa_mixer-test_write_valid_LCALTA_0 pass
2863 03:34:44.021931 alsa_mixer-test_write_invalid_LCALTA_0 pass
2864 03:34:44.022486 alsa_mixer-test_event_missing_LCALTA_0 pass
2865 03:34:44.027475 alsa_mixer-test_event_spurious_LCALTA_0 pass
2866 03:34:44.028058 alsa_mixer-test pass
2867 03:34:44.033013 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2868 03:34:44.038520 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2869 03:34:44.044081 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2870 03:34:44.049563 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2871 03:34:44.050071 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2872 03:34:44.055170 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2873 03:34:44.060713 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2874 03:34:44.066294 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2875 03:34:44.071769 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2876 03:34:44.077353 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2877 03:34:44.077881 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2878 03:34:44.082862 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2879 03:34:44.088398 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2880 03:34:44.093934 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2881 03:34:44.099477 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2882 03:34:44.105055 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2883 03:34:44.105578 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2884 03:34:44.110653 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2885 03:34:44.116244 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2886 03:34:44.121717 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2887 03:34:44.127248 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2888 03:34:44.132793 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2889 03:34:44.133304 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2890 03:34:44.138380 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2891 03:34:44.143921 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2892 03:34:44.149448 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2893 03:34:44.155010 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2894 03:34:44.160571 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2895 03:34:44.161113 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2896 03:34:44.166097 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2897 03:34:44.171651 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2898 03:34:44.177197 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2899 03:34:44.182727 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2900 03:34:44.188319 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2901 03:34:44.193835 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2902 03:34:44.194354 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2903 03:34:44.199375 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2904 03:34:44.204926 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2905 03:34:44.210539 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2906 03:34:44.216064 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2907 03:34:44.221565 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2908 03:34:44.222105 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2909 03:34:44.227116 alsa_pcm-test pass
2910 03:34:44.232745 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2911 03:34:44.243814 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2912 03:34:44.249324 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2913 03:34:44.260308 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2914 03:34:44.265868 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2915 03:34:44.271414 alsa_test-pcmtest-driver pass
2916 03:34:44.276967 alsa_utimer-test_global_wrong_timers_test pass
2917 03:34:44.277460 alsa_utimer-test_timer_f_utimer fail
2918 03:34:44.282502 alsa_utimer-test fail
2919 03:34:44.282993 + ../../utils/send-to-lava.sh ./output/result.txt
2920 03:34:44.288076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2921 03:34:44.289031 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2923 03:34:44.299112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2924 03:34:44.299886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2926 03:34:44.304939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2927 03:34:44.305677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2929 03:34:44.346307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2930 03:34:44.347109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2932 03:34:44.393618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2933 03:34:44.394403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2935 03:34:44.441499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2936 03:34:44.442371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2938 03:34:44.486005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2939 03:34:44.486797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2941 03:34:44.541039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2942 03:34:44.541870 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2944 03:34:44.588071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2945 03:34:44.588933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2947 03:34:44.639864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2948 03:34:44.640691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2950 03:34:44.687815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2951 03:34:44.688666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2953 03:34:44.741040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2954 03:34:44.741841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2956 03:34:44.786951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2957 03:34:44.787786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2959 03:34:44.836903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2960 03:34:44.837798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2962 03:34:44.892097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2963 03:34:44.893029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2965 03:34:44.944851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2966 03:34:44.945796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2968 03:34:44.991578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2969 03:34:44.992572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2971 03:34:45.042015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2972 03:34:45.042913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2974 03:34:45.102037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2975 03:34:45.102858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2977 03:34:45.155467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2978 03:34:45.156320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2980 03:34:45.208234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2981 03:34:45.209046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2983 03:34:45.259606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2984 03:34:45.260473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2986 03:34:45.306060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2987 03:34:45.306813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2989 03:34:45.351813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2990 03:34:45.352654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2992 03:34:45.401338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2993 03:34:45.402133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2995 03:34:45.459641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2996 03:34:45.460503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2998 03:34:45.511644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
2999 03:34:45.512562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3001 03:34:45.555869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3002 03:34:45.556887 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3004 03:34:45.604613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3005 03:34:45.605408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3007 03:34:45.658708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3008 03:34:45.659482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3010 03:34:45.711633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3011 03:34:45.712432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3013 03:34:45.757511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3014 03:34:45.758281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3016 03:34:45.811735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3017 03:34:45.812538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3019 03:34:45.862907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3020 03:34:45.863661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3022 03:34:45.907639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3023 03:34:45.908423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3025 03:34:45.958080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3026 03:34:45.958853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3028 03:34:46.008301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3029 03:34:46.009087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3031 03:34:46.059875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3032 03:34:46.060716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3034 03:34:46.119665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3035 03:34:46.120502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3037 03:34:46.172303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3038 03:34:46.173076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3040 03:34:46.217497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3041 03:34:46.218275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3043 03:34:46.269217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3044 03:34:46.269998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3046 03:34:46.323498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3047 03:34:46.324318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3049 03:34:46.376246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3050 03:34:46.377041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3052 03:34:46.423424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3053 03:34:46.424210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3055 03:34:46.486085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3056 03:34:46.486855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3058 03:34:46.529712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3059 03:34:46.530524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3061 03:34:46.588360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3062 03:34:46.589182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3064 03:34:46.638940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3065 03:34:46.639738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3067 03:34:46.688216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3068 03:34:46.689008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3070 03:34:46.737016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3071 03:34:46.737783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3073 03:34:46.800695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3074 03:34:46.801466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3076 03:34:46.843432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3077 03:34:46.844207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3079 03:34:46.899873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3080 03:34:46.900689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3082 03:34:46.944756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3083 03:34:46.945518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3085 03:34:46.993054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3086 03:34:46.993830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3088 03:34:47.047405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3089 03:34:47.048219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3091 03:34:47.095246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3092 03:34:47.096035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3094 03:34:47.146127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3095 03:34:47.146877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3097 03:34:47.192419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3098 03:34:47.193197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3100 03:34:47.242831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3101 03:34:47.243590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3103 03:34:47.294603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3104 03:34:47.295389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3106 03:34:47.344720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3107 03:34:47.345473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3109 03:34:47.398290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3110 03:34:47.399079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3112 03:34:47.449404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3113 03:34:47.450182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3115 03:34:47.501483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3116 03:34:47.502239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3118 03:34:47.554356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3119 03:34:47.555154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3121 03:34:47.616304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3122 03:34:47.617104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3124 03:34:47.665873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3125 03:34:47.666651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3127 03:34:47.718875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3128 03:34:47.719659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3130 03:34:47.771139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3131 03:34:47.771892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3133 03:34:47.827686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3134 03:34:47.828483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3136 03:34:47.872364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3137 03:34:47.873125 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3139 03:34:47.928777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3140 03:34:47.929549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3142 03:34:47.981904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3143 03:34:47.982685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3145 03:34:48.031183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3146 03:34:48.032001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3148 03:34:48.077889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3149 03:34:48.078682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3151 03:34:48.130771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3152 03:34:48.131562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3154 03:34:48.176725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3155 03:34:48.177504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3157 03:34:48.225033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3158 03:34:48.225826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3160 03:34:48.272231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3161 03:34:48.273008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3163 03:34:48.320997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3164 03:34:48.321782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3166 03:34:48.371627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3167 03:34:48.372471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3169 03:34:48.434338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3170 03:34:48.435108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3172 03:34:48.486813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3173 03:34:48.487578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3175 03:34:48.531967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3176 03:34:48.532800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3178 03:34:48.582253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3179 03:34:48.583016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3181 03:34:48.628685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3182 03:34:48.629445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3184 03:34:48.672119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3185 03:34:48.672873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3187 03:34:48.730962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3188 03:34:48.731713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3190 03:34:48.774824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3191 03:34:48.775583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3193 03:34:48.826067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3194 03:34:48.826858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3196 03:34:48.878119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3197 03:34:48.878888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3199 03:34:48.921672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3200 03:34:48.922438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3202 03:34:48.969515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3203 03:34:48.970263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3205 03:34:49.026584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3206 03:34:49.027365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3208 03:34:49.075620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3209 03:34:49.076407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3211 03:34:49.124281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3212 03:34:49.125035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3214 03:34:49.179824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3215 03:34:49.180656 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3217 03:34:49.224222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3218 03:34:49.225002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3220 03:34:49.276240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3221 03:34:49.277079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3223 03:34:49.328406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3224 03:34:49.329146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3226 03:34:49.378541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3227 03:34:49.379324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3229 03:34:49.431931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3230 03:34:49.432745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3232 03:34:49.480762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3233 03:34:49.481489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3235 03:34:49.533889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3236 03:34:49.534779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3238 03:34:49.590601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3239 03:34:49.591487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3241 03:34:49.643178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3242 03:34:49.644264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3244 03:34:49.689395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3245 03:34:49.690325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3247 03:34:49.734667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3248 03:34:49.735524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3250 03:34:49.791348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3251 03:34:49.792195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3253 03:34:49.837867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3254 03:34:49.838673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3256 03:34:49.894487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3257 03:34:49.895269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3259 03:34:49.938748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3260 03:34:49.939537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3262 03:34:49.982631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3263 03:34:49.983376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3265 03:34:50.037104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3266 03:34:50.037889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3268 03:34:50.091886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3269 03:34:50.092692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3271 03:34:50.142382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3272 03:34:50.143124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3274 03:34:50.192538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3275 03:34:50.193286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3277 03:34:50.236383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3278 03:34:50.237130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3280 03:34:50.299785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3281 03:34:50.300648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3283 03:34:50.352079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3284 03:34:50.352902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3286 03:34:50.397835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3287 03:34:50.398624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3289 03:34:50.443766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3290 03:34:50.444660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3292 03:34:50.489014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3293 03:34:50.489786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3295 03:34:50.547297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3296 03:34:50.548171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3298 03:34:50.603946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3299 03:34:50.604762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3301 03:34:50.651670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3302 03:34:50.652467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3304 03:34:50.702602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3305 03:34:50.703379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3307 03:34:50.753544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3308 03:34:50.754312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3310 03:34:50.801610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3311 03:34:50.802380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3313 03:34:50.846585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3314 03:34:50.847347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3316 03:34:50.901638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3317 03:34:50.902385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3319 03:34:50.946960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3320 03:34:50.947700 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3322 03:34:51.009559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3323 03:34:51.010159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3325 03:34:51.054293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3326 03:34:51.054886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3328 03:34:51.111606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3329 03:34:51.112168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3331 03:34:51.161765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3332 03:34:51.162327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3334 03:34:51.212077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3335 03:34:51.212695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3337 03:34:51.262393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3338 03:34:51.262986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3340 03:34:51.311473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3341 03:34:51.312109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3343 03:34:51.356730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3344 03:34:51.357309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3346 03:34:51.403467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3347 03:34:51.404069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3349 03:34:51.450383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3350 03:34:51.451017 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3352 03:34:51.496230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3353 03:34:51.496825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3355 03:34:51.541692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3356 03:34:51.542317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3358 03:34:51.590426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3359 03:34:51.591063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3361 03:34:51.640975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3362 03:34:51.641637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3364 03:34:51.695515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3365 03:34:51.696175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3367 03:34:51.743944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3368 03:34:51.744560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3370 03:34:51.795115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3371 03:34:51.795710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3373 03:34:51.849050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3374 03:34:51.849618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3376 03:34:51.907013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3377 03:34:51.907553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3379 03:34:51.952357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3380 03:34:51.953137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3382 03:34:52.015571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3383 03:34:52.016373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3385 03:34:52.065446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3386 03:34:52.066204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3388 03:34:52.117659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3389 03:34:52.118460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3391 03:34:52.168711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3392 03:34:52.169531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3394 03:34:52.222748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3395 03:34:52.223501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3397 03:34:52.268415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3398 03:34:52.269264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3400 03:34:52.314904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3401 03:34:52.315742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3403 03:34:52.369370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3404 03:34:52.370211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3406 03:34:52.417664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3407 03:34:52.418514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3409 03:34:52.464982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3410 03:34:52.465738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3412 03:34:52.520100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3413 03:34:52.520925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3415 03:34:52.566188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3416 03:34:52.566973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3418 03:34:52.620229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3419 03:34:52.620981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3421 03:34:52.672892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3422 03:34:52.673652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3424 03:34:52.722446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3425 03:34:52.723196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3427 03:34:52.774980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3428 03:34:52.775744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3430 03:34:52.820576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3431 03:34:52.821373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3433 03:34:52.930491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3434 03:34:52.932288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3436 03:34:53.040232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3437 03:34:53.041628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3439 03:34:53.182928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3440 03:34:53.183939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3442 03:34:53.236194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3443 03:34:53.237094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3445 03:34:53.298798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3446 03:34:53.299581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3448 03:34:53.354594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3449 03:34:53.356138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3451 03:34:53.417593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3452 03:34:53.418605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3454 03:34:53.475248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3455 03:34:53.476132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3457 03:34:53.528793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3458 03:34:53.529694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3460 03:34:53.586664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3461 03:34:53.587537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3463 03:34:53.642759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3464 03:34:53.643726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3466 03:34:53.692478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3467 03:34:53.693413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3469 03:34:53.750849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3470 03:34:53.751521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3472 03:34:53.826070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3473 03:34:53.827412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3475 03:34:53.893946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3476 03:34:53.894988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3478 03:34:53.951523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3479 03:34:53.952643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3481 03:34:54.007376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3482 03:34:54.008536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3484 03:34:54.074151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3485 03:34:54.075328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3487 03:34:54.127861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3488 03:34:54.128693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3490 03:34:54.176214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3491 03:34:54.177195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3493 03:34:54.235488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3494 03:34:54.236539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3496 03:34:54.287864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3497 03:34:54.288984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3499 03:34:54.358918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3500 03:34:54.359892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3502 03:34:54.419439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3503 03:34:54.420396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3505 03:34:54.486034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3506 03:34:54.486752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3508 03:34:54.542365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3509 03:34:54.542988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3511 03:34:54.597519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3512 03:34:54.598612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3514 03:34:54.912219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3515 03:34:54.912909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3517 03:34:54.963406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3518 03:34:54.964013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3520 03:34:55.014788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3521 03:34:55.015650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3523 03:34:55.066361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3524 03:34:55.067204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3526 03:34:55.126852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3527 03:34:55.127671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3529 03:34:55.178519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3530 03:34:55.179315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3532 03:34:55.228256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3533 03:34:55.229056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3535 03:34:55.280798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3536 03:34:55.281632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3538 03:34:55.332341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3539 03:34:55.333124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3541 03:34:55.376464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3542 03:34:55.377232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3544 03:34:55.433464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3545 03:34:55.434272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3547 03:34:55.485336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3548 03:34:55.486117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3550 03:34:55.528203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3551 03:34:55.529046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3553 03:34:55.572654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3554 03:34:55.573657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3556 03:34:55.625412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3557 03:34:55.626327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3559 03:34:55.677161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3560 03:34:55.678105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3562 03:34:55.733766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3563 03:34:55.734565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3565 03:34:55.777275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3566 03:34:55.778192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3568 03:34:55.833108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3569 03:34:55.833927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3571 03:34:55.884912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3572 03:34:55.885792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3574 03:34:55.934854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3575 03:34:55.935682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3577 03:34:55.992941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3578 03:34:55.993794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3580 03:34:56.053103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3581 03:34:56.053917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3583 03:34:56.098484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3584 03:34:56.099281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3586 03:34:56.151034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3587 03:34:56.151869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3589 03:34:56.205524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3590 03:34:56.206392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3592 03:34:56.262574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3593 03:34:56.263464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3595 03:34:56.310243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3596 03:34:56.311164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3598 03:34:56.360972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3599 03:34:56.361858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3601 03:34:56.410335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3602 03:34:56.411133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3604 03:34:56.460868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3605 03:34:56.461839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3607 03:34:56.515083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3608 03:34:56.515646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3610 03:34:56.567109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3611 03:34:56.567963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3613 03:34:56.612279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3614 03:34:56.613068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3616 03:34:56.664638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3617 03:34:56.665530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3619 03:34:56.716332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3620 03:34:56.717229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3622 03:34:56.767171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3623 03:34:56.768082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3625 03:34:56.818277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3626 03:34:56.819224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3628 03:34:56.875383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3629 03:34:56.876180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3631 03:34:56.922532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3632 03:34:56.923306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3634 03:34:56.974093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3635 03:34:56.974956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3637 03:34:57.024535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3638 03:34:57.025412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3640 03:34:57.074720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3641 03:34:57.075677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3643 03:34:57.121201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3644 03:34:57.122089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3646 03:34:57.181192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3647 03:34:57.182042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3649 03:34:57.233143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3650 03:34:57.234086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3652 03:34:57.286647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3653 03:34:57.287519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3655 03:34:57.342374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3656 03:34:57.343230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3658 03:34:57.391426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3659 03:34:57.392043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3661 03:34:57.440257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3662 03:34:57.440861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3664 03:34:57.493433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3665 03:34:57.494045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3667 03:34:57.547030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3668 03:34:57.547942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3670 03:34:57.591361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3671 03:34:57.592281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3673 03:34:57.642640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3674 03:34:57.643484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3676 03:34:57.693718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3677 03:34:57.694581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3679 03:34:57.746277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3680 03:34:57.747070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3682 03:34:57.803707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3683 03:34:57.804549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3685 03:34:57.849363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3686 03:34:57.850173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3688 03:34:57.907566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3689 03:34:57.908407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3691 03:34:57.964468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3692 03:34:57.965253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3694 03:34:58.021611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3695 03:34:58.022403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3697 03:34:58.073837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3698 03:34:58.074657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3700 03:34:58.133425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3701 03:34:58.134233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3703 03:34:58.176539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3704 03:34:58.177340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3706 03:34:58.236240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3707 03:34:58.237057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3709 03:34:58.289896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3710 03:34:58.290781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3712 03:34:58.337605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3713 03:34:58.338405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3715 03:34:58.382896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3716 03:34:58.383693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3718 03:34:58.441345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3719 03:34:58.442124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3721 03:34:58.494792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3722 03:34:58.495559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3724 03:34:58.551403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3725 03:34:58.552213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3727 03:34:58.600820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3728 03:34:58.601618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3730 03:34:58.652803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3731 03:34:58.653594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3733 03:34:58.698993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3734 03:34:58.699761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3736 03:34:58.753848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3737 03:34:58.754617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3739 03:34:58.797975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3740 03:34:58.798749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3742 03:34:58.863748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3743 03:34:58.864604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3745 03:34:58.914165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3746 03:34:58.914974 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3748 03:34:58.970221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3749 03:34:58.971019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3751 03:34:59.025460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3752 03:34:59.026229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3754 03:34:59.071819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3755 03:34:59.072613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3757 03:34:59.117113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3758 03:34:59.117866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3760 03:34:59.170457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3761 03:34:59.171220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3763 03:34:59.216906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3764 03:34:59.217643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3766 03:34:59.262660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3767 03:34:59.263398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3769 03:34:59.311866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3770 03:34:59.312747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3772 03:34:59.377649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3773 03:34:59.378579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3775 03:34:59.430012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3776 03:34:59.430818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3778 03:34:59.489713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3779 03:34:59.490464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3781 03:34:59.537827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3782 03:34:59.538781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3784 03:34:59.602420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3785 03:34:59.603024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3787 03:34:59.649018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3788 03:34:59.649983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3790 03:34:59.693979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3791 03:34:59.694878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3793 03:34:59.753808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3794 03:34:59.754659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3796 03:34:59.806552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3797 03:34:59.807356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3799 03:34:59.853274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3800 03:34:59.854058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3802 03:34:59.903786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3803 03:34:59.904607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3805 03:34:59.950550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3806 03:34:59.951331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3808 03:35:00.008301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3809 03:35:00.009150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3811 03:35:00.064548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3812 03:35:00.065459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3814 03:35:00.117527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3815 03:35:00.118454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3817 03:35:00.163081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3818 03:35:00.163888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3820 03:35:00.208408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3821 03:35:00.209275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3823 03:35:00.282845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3824 03:35:00.283706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3826 03:35:00.349022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3827 03:35:00.349857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3829 03:35:00.407680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3830 03:35:00.408597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3832 03:35:00.461234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3833 03:35:00.462067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3835 03:35:00.515001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3836 03:35:00.515880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3838 03:35:00.560272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3839 03:35:00.561159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3841 03:35:00.611822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3842 03:35:00.612845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3844 03:35:00.665132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3845 03:35:00.666005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3847 03:35:00.715240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3848 03:35:00.716099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3850 03:35:00.769266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3851 03:35:00.770099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3853 03:35:00.828538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3854 03:35:00.829399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3856 03:35:00.882086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3857 03:35:00.882909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3859 03:35:00.933048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3860 03:35:00.933708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3862 03:35:00.985219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3863 03:35:00.986180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3865 03:35:01.035959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3866 03:35:01.036939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3868 03:35:01.083809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3869 03:35:01.084736 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3871 03:35:01.137571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3872 03:35:01.138491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3874 03:35:01.196921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3875 03:35:01.197840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3877 03:35:01.247637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3878 03:35:01.248552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3880 03:35:01.290850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3881 03:35:01.291694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3883 03:35:01.342364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3884 03:35:01.343278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3886 03:35:01.387331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3887 03:35:01.388182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3889 03:35:01.439185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3890 03:35:01.440043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3892 03:35:01.491737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3893 03:35:01.492602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3895 03:35:01.547043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3896 03:35:01.547886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3898 03:35:01.599905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3899 03:35:01.600758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3901 03:35:01.646394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3902 03:35:01.647232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3904 03:35:01.692480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3905 03:35:01.693303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3907 03:35:01.745493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3908 03:35:01.746321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3910 03:35:01.801957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3911 03:35:01.802784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3913 03:35:01.853100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3914 03:35:01.853946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3916 03:35:01.905465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3917 03:35:01.906295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3919 03:35:01.959955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3920 03:35:01.960819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3922 03:35:02.008261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3923 03:35:02.009078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3925 03:35:02.058018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3926 03:35:02.058846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3928 03:35:02.104861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3929 03:35:02.105668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3931 03:35:02.158693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3932 03:35:02.159491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3934 03:35:02.209248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3935 03:35:02.210054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3937 03:35:02.259091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3938 03:35:02.259872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3940 03:35:02.308833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3941 03:35:02.309672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3943 03:35:02.360859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3944 03:35:02.361657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3946 03:35:02.419504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3947 03:35:02.420398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3949 03:35:02.465324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3950 03:35:02.466107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3952 03:35:02.519734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3953 03:35:02.520623 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3955 03:35:02.570841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3956 03:35:02.571681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3958 03:35:02.628753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3959 03:35:02.629555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3961 03:35:02.680255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3962 03:35:02.681036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3964 03:35:02.738750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3965 03:35:02.739518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3967 03:35:02.785401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3968 03:35:02.786173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3970 03:35:02.831565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3971 03:35:02.832367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3973 03:35:02.876677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3974 03:35:02.877444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3976 03:35:02.923040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3977 03:35:02.923814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3979 03:35:02.980451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3980 03:35:02.981213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3982 03:35:03.027444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3983 03:35:03.028284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3985 03:35:03.079048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3986 03:35:03.079834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3988 03:35:03.135024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3989 03:35:03.135841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3991 03:35:03.180242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3992 03:35:03.181063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3994 03:35:03.234052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3995 03:35:03.234863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3997 03:35:03.283304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3998 03:35:03.284183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4000 03:35:03.333634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4001 03:35:03.334447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4003 03:35:03.388322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4004 03:35:03.389134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4006 03:35:03.432294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4007 03:35:03.433123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4009 03:35:03.483783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4010 03:35:03.484663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4012 03:35:03.536141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4013 03:35:03.536994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4015 03:35:03.582401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4016 03:35:03.583246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4018 03:35:03.628173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4019 03:35:03.629047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4021 03:35:03.682917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4022 03:35:03.683749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4024 03:35:03.729433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4025 03:35:03.730281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4027 03:35:03.780646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4028 03:35:03.781447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4030 03:35:03.832276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4031 03:35:03.833101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4033 03:35:03.884594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4034 03:35:03.885406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4036 03:35:03.936507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4037 03:35:03.937309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4039 03:35:03.983345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4040 03:35:03.984149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4042 03:35:04.036252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4043 03:35:04.037088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4045 03:35:04.087402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4046 03:35:04.088216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4048 03:35:04.141771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4049 03:35:04.142594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4051 03:35:04.196261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4052 03:35:04.197079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4054 03:35:04.242806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4055 03:35:04.243686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4057 03:35:04.300133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4058 03:35:04.301673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4060 03:35:04.350535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4061 03:35:04.351349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4063 03:35:04.404365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4064 03:35:04.405216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4066 03:35:04.462784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4067 03:35:04.463546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4069 03:35:04.518748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4070 03:35:04.519383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4072 03:35:04.568678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4073 03:35:04.569268 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4075 03:35:04.623215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4076 03:35:04.623953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4078 03:35:04.683002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4079 03:35:04.683734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4081 03:35:04.726164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4082 03:35:04.726723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4084 03:35:04.774625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4085 03:35:04.775234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4087 03:35:04.819464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4088 03:35:04.820104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4090 03:35:04.879245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4091 03:35:04.879955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4093 03:35:04.930026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4094 03:35:04.930647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4096 03:35:04.973717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4097 03:35:04.974442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4099 03:35:05.031640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4100 03:35:05.032287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4102 03:35:05.075032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4103 03:35:05.075565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4105 03:35:05.127100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4106 03:35:05.127966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4108 03:35:05.180845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4109 03:35:05.181688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4111 03:35:05.244245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4112 03:35:05.245039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4114 03:35:05.291948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4115 03:35:05.292785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4117 03:35:05.349645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4118 03:35:05.350388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4120 03:35:05.396246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4121 03:35:05.397073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4123 03:35:05.448439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4124 03:35:05.449277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4126 03:35:05.495022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4127 03:35:05.495785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4129 03:35:05.549518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4130 03:35:05.550200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4132 03:35:05.595093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4133 03:35:05.595700 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4135 03:35:05.650866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4136 03:35:05.651618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4138 03:35:05.700520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4139 03:35:05.701276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4141 03:35:05.752518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4142 03:35:05.753407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4144 03:35:05.806705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4145 03:35:05.807468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4147 03:35:05.859876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4148 03:35:05.860747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4150 03:35:05.913246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4151 03:35:05.914151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4153 03:35:05.967377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4154 03:35:05.968188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4156 03:35:06.020387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4157 03:35:06.021366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4159 03:35:06.080635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4160 03:35:06.081436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4162 03:35:06.131955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4163 03:35:06.132715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4165 03:35:06.182318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4166 03:35:06.183037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4168 03:35:06.237382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4169 03:35:06.238123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4171 03:35:06.287041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4172 03:35:06.287757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4174 03:35:06.342611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4175 03:35:06.343330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4177 03:35:06.403518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4178 03:35:06.404394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4180 03:35:06.464384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4181 03:35:06.465149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4183 03:35:06.516108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4184 03:35:06.516732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4186 03:35:06.560917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4187 03:35:06.561536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4189 03:35:06.619254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4190 03:35:06.619855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4192 03:35:06.664094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4193 03:35:06.664802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4195 03:35:06.713379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4196 03:35:06.714066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4198 03:35:06.763757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4199 03:35:06.764519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4201 03:35:06.809484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4202 03:35:06.810187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4204 03:35:06.860629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4206 03:35:06.863116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4207 03:35:06.916642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4208 03:35:06.917331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4210 03:35:06.976067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4211 03:35:06.976828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4213 03:35:07.026045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4214 03:35:07.026877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4216 03:35:07.080048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4217 03:35:07.080833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4219 03:35:07.132628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4220 03:35:07.133198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4222 03:35:07.184806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4223 03:35:07.185671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4225 03:35:07.234454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4226 03:35:07.235051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4228 03:35:07.287538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4229 03:35:07.288416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4231 03:35:07.344549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4232 03:35:07.345361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4234 03:35:07.396106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4235 03:35:07.396909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4237 03:35:07.447748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4238 03:35:07.448638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4240 03:35:07.499080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4241 03:35:07.499884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4243 03:35:07.545959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4244 03:35:07.546797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4246 03:35:07.599634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4247 03:35:07.600479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4249 03:35:07.661604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4250 03:35:07.662443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4252 03:35:07.714753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4253 03:35:07.715537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4255 03:35:07.772762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4256 03:35:07.773596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4258 03:35:07.814501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4259 03:35:07.815278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4261 03:35:07.859251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4262 03:35:07.860068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4264 03:35:07.912801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4265 03:35:07.913620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4267 03:35:07.964186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4268 03:35:07.964992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4270 03:35:08.016577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4271 03:35:08.017387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4273 03:35:08.074907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4274 03:35:08.075735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4276 03:35:08.129573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4277 03:35:08.130361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4279 03:35:08.186722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4280 03:35:08.187565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4282 03:35:08.230715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4283 03:35:08.231542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4285 03:35:08.274674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4286 03:35:08.275494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4288 03:35:08.330128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4289 03:35:08.330923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4291 03:35:08.386676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4292 03:35:08.387502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4294 03:35:08.442886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4295 03:35:08.443943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4297 03:35:08.494621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4298 03:35:08.495651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4300 03:35:08.549760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4301 03:35:08.550598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4303 03:35:08.595559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4304 03:35:08.596187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4306 03:35:08.647182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4307 03:35:08.648088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4309 03:35:08.704368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4310 03:35:08.705233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4312 03:35:08.763457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4313 03:35:08.764392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4315 03:35:08.814117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4316 03:35:08.815037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4318 03:35:08.863221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4319 03:35:08.863921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4321 03:35:08.919624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4322 03:35:08.920219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4324 03:35:08.974910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4325 03:35:08.975728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4327 03:35:09.024302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4328 03:35:09.024936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4330 03:35:09.068830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4331 03:35:09.069705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4333 03:35:09.112798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4334 03:35:09.113603 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4336 03:35:09.170103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4337 03:35:09.170957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4339 03:35:09.219162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4340 03:35:09.220032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4342 03:35:09.265234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4343 03:35:09.266070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4345 03:35:09.320973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4346 03:35:09.321857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4348 03:35:09.366846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4349 03:35:09.367721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4351 03:35:09.415907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4352 03:35:09.416788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4354 03:35:09.467168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4355 03:35:09.467974 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4357 03:35:09.515949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4358 03:35:09.516809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4360 03:35:09.569272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4362 03:35:09.574495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4363 03:35:09.575036 + set +x
4364 03:35:09.580444 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 964641_1.6.2.4.5>
4365 03:35:09.580957 <LAVA_TEST_RUNNER EXIT>
4366 03:35:09.581650 Received signal: <ENDRUN> 1_kselftest-alsa 964641_1.6.2.4.5
4367 03:35:09.582131 Ending use of test pattern.
4368 03:35:09.582559 Ending test lava.1_kselftest-alsa (964641_1.6.2.4.5), duration 41.65
4370 03:35:09.584240 ok: lava_test_shell seems to have completed
4371 03:35:09.608963 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4372 03:35:09.610911 end: 3.1 lava-test-shell (duration 00:00:43) [common]
4373 03:35:09.611505 end: 3 lava-test-retry (duration 00:00:43) [common]
4374 03:35:09.612123 start: 4 finalize (timeout 00:06:10) [common]
4375 03:35:09.612713 start: 4.1 power-off (timeout 00:00:30) [common]
4376 03:35:09.613690 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4377 03:35:09.664954 >> OK - accepted request
4378 03:35:09.667457 Returned 0 in 0 seconds
4379 03:35:09.768788 end: 4.1 power-off (duration 00:00:00) [common]
4381 03:35:09.769906 start: 4.2 read-feedback (timeout 00:06:10) [common]
4382 03:35:09.770813 Listened to connection for namespace 'common' for up to 1s
4383 03:35:10.771554 Finalising connection for namespace 'common'
4384 03:35:10.772440 Disconnecting from shell: Finalise
4385 03:35:10.773090 / #
4386 03:35:10.874802 end: 4.2 read-feedback (duration 00:00:01) [common]
4387 03:35:10.875764 end: 4 finalize (duration 00:00:01) [common]
4388 03:35:10.876721 Cleaning after the job
4389 03:35:10.877439 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/ramdisk
4390 03:35:10.892695 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/kernel
4391 03:35:10.934087 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/dtb
4392 03:35:10.935065 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/nfsrootfs
4393 03:35:11.111495 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964641/tftp-deploy-ard2i2kr/modules
4394 03:35:11.133091 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/964641
4395 03:35:14.510749 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/964641
4396 03:35:14.511338 Job finished correctly