Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 03:27:39.698738 lava-dispatcher, installed at version: 2024.01
2 03:27:39.699520 start: 0 validate
3 03:27:39.700031 Start time: 2024-11-09 03:27:39.699969+00:00 (UTC)
4 03:27:39.700581 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:27:39.701114 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 03:27:39.741110 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:27:39.741632 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-247-gbf99f9b489d8e%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 03:27:39.773997 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:27:39.774597 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-247-gbf99f9b489d8e%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 03:27:39.811213 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:27:39.811708 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 03:27:39.845656 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 03:27:39.846226 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-247-gbf99f9b489d8e%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 03:27:39.899210 validate duration: 0.20
16 03:27:39.900141 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 03:27:39.900512 start: 1.1 download-retry (timeout 00:10:00) [common]
18 03:27:39.900828 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 03:27:39.901381 Not decompressing ramdisk as can be used compressed.
20 03:27:39.901845 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 03:27:39.902162 saving as /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/ramdisk/initrd.cpio.gz
22 03:27:39.902457 total size: 5628169 (5 MB)
23 03:27:39.943184 progress 0 % (0 MB)
24 03:27:39.947425 progress 5 % (0 MB)
25 03:27:39.954602 progress 10 % (0 MB)
26 03:27:39.961448 progress 15 % (0 MB)
27 03:27:39.968636 progress 20 % (1 MB)
28 03:27:39.972182 progress 25 % (1 MB)
29 03:27:39.976139 progress 30 % (1 MB)
30 03:27:39.980119 progress 35 % (1 MB)
31 03:27:39.983713 progress 40 % (2 MB)
32 03:27:39.987614 progress 45 % (2 MB)
33 03:27:39.991137 progress 50 % (2 MB)
34 03:27:39.995021 progress 55 % (2 MB)
35 03:27:39.998992 progress 60 % (3 MB)
36 03:27:40.002576 progress 65 % (3 MB)
37 03:27:40.006563 progress 70 % (3 MB)
38 03:27:40.010233 progress 75 % (4 MB)
39 03:27:40.014151 progress 80 % (4 MB)
40 03:27:40.017705 progress 85 % (4 MB)
41 03:27:40.021647 progress 90 % (4 MB)
42 03:27:40.025304 progress 95 % (5 MB)
43 03:27:40.028574 progress 100 % (5 MB)
44 03:27:40.029246 5 MB downloaded in 0.13 s (42.34 MB/s)
45 03:27:40.029784 end: 1.1.1 http-download (duration 00:00:00) [common]
47 03:27:40.030667 end: 1.1 download-retry (duration 00:00:00) [common]
48 03:27:40.030956 start: 1.2 download-retry (timeout 00:10:00) [common]
49 03:27:40.031223 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 03:27:40.031702 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm64/defconfig/gcc-12/kernel/Image
51 03:27:40.031970 saving as /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/kernel/Image
52 03:27:40.032208 total size: 45713920 (43 MB)
53 03:27:40.032419 No compression specified
54 03:27:40.072442 progress 0 % (0 MB)
55 03:27:40.100912 progress 5 % (2 MB)
56 03:27:40.129374 progress 10 % (4 MB)
57 03:27:40.157445 progress 15 % (6 MB)
58 03:27:40.185660 progress 20 % (8 MB)
59 03:27:40.213719 progress 25 % (10 MB)
60 03:27:40.241516 progress 30 % (13 MB)
61 03:27:40.269388 progress 35 % (15 MB)
62 03:27:40.297290 progress 40 % (17 MB)
63 03:27:40.324716 progress 45 % (19 MB)
64 03:27:40.352408 progress 50 % (21 MB)
65 03:27:40.380280 progress 55 % (24 MB)
66 03:27:40.408199 progress 60 % (26 MB)
67 03:27:40.435581 progress 65 % (28 MB)
68 03:27:40.463553 progress 70 % (30 MB)
69 03:27:40.491715 progress 75 % (32 MB)
70 03:27:40.519867 progress 80 % (34 MB)
71 03:27:40.547580 progress 85 % (37 MB)
72 03:27:40.575535 progress 90 % (39 MB)
73 03:27:40.603793 progress 95 % (41 MB)
74 03:27:40.631080 progress 100 % (43 MB)
75 03:27:40.631644 43 MB downloaded in 0.60 s (72.73 MB/s)
76 03:27:40.632134 end: 1.2.1 http-download (duration 00:00:01) [common]
78 03:27:40.632955 end: 1.2 download-retry (duration 00:00:01) [common]
79 03:27:40.633231 start: 1.3 download-retry (timeout 00:09:59) [common]
80 03:27:40.633495 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 03:27:40.633949 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 03:27:40.634219 saving as /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/dtb/meson-g12b-a311d-libretech-cc.dtb
83 03:27:40.634425 total size: 54703 (0 MB)
84 03:27:40.634633 No compression specified
85 03:27:40.674348 progress 59 % (0 MB)
86 03:27:40.675205 progress 100 % (0 MB)
87 03:27:40.675764 0 MB downloaded in 0.04 s (1.26 MB/s)
88 03:27:40.676277 end: 1.3.1 http-download (duration 00:00:00) [common]
90 03:27:40.677098 end: 1.3 download-retry (duration 00:00:00) [common]
91 03:27:40.677359 start: 1.4 download-retry (timeout 00:09:59) [common]
92 03:27:40.677685 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 03:27:40.678177 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 03:27:40.678420 saving as /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/nfsrootfs/full.rootfs.tar
95 03:27:40.678622 total size: 120894716 (115 MB)
96 03:27:40.678832 Using unxz to decompress xz
97 03:27:40.717592 progress 0 % (0 MB)
98 03:27:41.516429 progress 5 % (5 MB)
99 03:27:42.365154 progress 10 % (11 MB)
100 03:27:43.164969 progress 15 % (17 MB)
101 03:27:43.908184 progress 20 % (23 MB)
102 03:27:44.503639 progress 25 % (28 MB)
103 03:27:45.326993 progress 30 % (34 MB)
104 03:27:46.119945 progress 35 % (40 MB)
105 03:27:46.482024 progress 40 % (46 MB)
106 03:27:46.853745 progress 45 % (51 MB)
107 03:27:47.580083 progress 50 % (57 MB)
108 03:27:48.463782 progress 55 % (63 MB)
109 03:27:49.243218 progress 60 % (69 MB)
110 03:27:49.999286 progress 65 % (74 MB)
111 03:27:50.775163 progress 70 % (80 MB)
112 03:27:51.594619 progress 75 % (86 MB)
113 03:27:52.381283 progress 80 % (92 MB)
114 03:27:53.154867 progress 85 % (98 MB)
115 03:27:54.020672 progress 90 % (103 MB)
116 03:27:54.812752 progress 95 % (109 MB)
117 03:27:55.651286 progress 100 % (115 MB)
118 03:27:55.663898 115 MB downloaded in 14.99 s (7.69 MB/s)
119 03:27:55.664546 end: 1.4.1 http-download (duration 00:00:15) [common]
121 03:27:55.665396 end: 1.4 download-retry (duration 00:00:15) [common]
122 03:27:55.665692 start: 1.5 download-retry (timeout 00:09:44) [common]
123 03:27:55.665974 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 03:27:55.666450 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm64/defconfig/gcc-12/modules.tar.xz
125 03:27:55.666711 saving as /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/modules/modules.tar
126 03:27:55.666926 total size: 11612756 (11 MB)
127 03:27:55.667150 Using unxz to decompress xz
128 03:27:55.705100 progress 0 % (0 MB)
129 03:27:55.771942 progress 5 % (0 MB)
130 03:27:55.846491 progress 10 % (1 MB)
131 03:27:55.944371 progress 15 % (1 MB)
132 03:27:56.036167 progress 20 % (2 MB)
133 03:27:56.116952 progress 25 % (2 MB)
134 03:27:56.194669 progress 30 % (3 MB)
135 03:27:56.273619 progress 35 % (3 MB)
136 03:27:56.346756 progress 40 % (4 MB)
137 03:27:56.422799 progress 45 % (5 MB)
138 03:27:56.509461 progress 50 % (5 MB)
139 03:27:56.590060 progress 55 % (6 MB)
140 03:27:56.677179 progress 60 % (6 MB)
141 03:27:56.766067 progress 65 % (7 MB)
142 03:27:56.847173 progress 70 % (7 MB)
143 03:27:56.925030 progress 75 % (8 MB)
144 03:27:57.008728 progress 80 % (8 MB)
145 03:27:57.089219 progress 85 % (9 MB)
146 03:27:57.168315 progress 90 % (9 MB)
147 03:27:57.249191 progress 95 % (10 MB)
148 03:27:57.331953 progress 100 % (11 MB)
149 03:27:57.344056 11 MB downloaded in 1.68 s (6.60 MB/s)
150 03:27:57.345108 end: 1.5.1 http-download (duration 00:00:02) [common]
152 03:27:57.346777 end: 1.5 download-retry (duration 00:00:02) [common]
153 03:27:57.347302 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 03:27:57.347818 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 03:28:14.252708 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/964633/extract-nfsrootfs-9s95vfgz
156 03:28:14.253326 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 03:28:14.253613 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 03:28:14.254233 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44
159 03:28:14.254664 makedir: /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin
160 03:28:14.254992 makedir: /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/tests
161 03:28:14.255304 makedir: /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/results
162 03:28:14.255643 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-add-keys
163 03:28:14.256209 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-add-sources
164 03:28:14.256759 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-background-process-start
165 03:28:14.257388 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-background-process-stop
166 03:28:14.257969 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-common-functions
167 03:28:14.258479 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-echo-ipv4
168 03:28:14.258962 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-install-packages
169 03:28:14.259432 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-installed-packages
170 03:28:14.259906 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-os-build
171 03:28:14.260452 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-probe-channel
172 03:28:14.260950 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-probe-ip
173 03:28:14.261474 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-target-ip
174 03:28:14.261952 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-target-mac
175 03:28:14.262428 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-target-storage
176 03:28:14.262908 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-test-case
177 03:28:14.263386 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-test-event
178 03:28:14.263947 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-test-feedback
179 03:28:14.264471 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-test-raise
180 03:28:14.264966 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-test-reference
181 03:28:14.265481 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-test-runner
182 03:28:14.265966 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-test-set
183 03:28:14.266444 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-test-shell
184 03:28:14.266926 Updating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-add-keys (debian)
185 03:28:14.267451 Updating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-add-sources (debian)
186 03:28:14.267954 Updating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-install-packages (debian)
187 03:28:14.268506 Updating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-installed-packages (debian)
188 03:28:14.269002 Updating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/bin/lava-os-build (debian)
189 03:28:14.269432 Creating /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/environment
190 03:28:14.269797 LAVA metadata
191 03:28:14.270056 - LAVA_JOB_ID=964633
192 03:28:14.270269 - LAVA_DISPATCHER_IP=192.168.6.2
193 03:28:14.270632 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 03:28:14.271588 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 03:28:14.271900 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 03:28:14.272134 skipped lava-vland-overlay
197 03:28:14.272379 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 03:28:14.272632 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 03:28:14.272847 skipped lava-multinode-overlay
200 03:28:14.273086 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 03:28:14.273336 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 03:28:14.273579 Loading test definitions
203 03:28:14.273856 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 03:28:14.274079 Using /lava-964633 at stage 0
205 03:28:14.275174 uuid=964633_1.6.2.4.1 testdef=None
206 03:28:14.275480 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 03:28:14.275743 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 03:28:14.277345 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 03:28:14.278137 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 03:28:14.280077 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 03:28:14.280905 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 03:28:14.282729 runner path: /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/0/tests/0_timesync-off test_uuid 964633_1.6.2.4.1
215 03:28:14.283279 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 03:28:14.284151 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 03:28:14.284381 Using /lava-964633 at stage 0
219 03:28:14.284740 Fetching tests from https://github.com/kernelci/test-definitions.git
220 03:28:14.285031 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/0/tests/1_kselftest-rtc'
221 03:28:17.670019 Running '/usr/bin/git checkout kernelci.org
222 03:28:18.120078 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 03:28:18.121595 uuid=964633_1.6.2.4.5 testdef=None
224 03:28:18.121968 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 03:28:18.122723 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 03:28:18.125757 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 03:28:18.126630 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 03:28:18.130755 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 03:28:18.131698 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 03:28:18.135531 runner path: /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/0/tests/1_kselftest-rtc test_uuid 964633_1.6.2.4.5
234 03:28:18.135882 BOARD='meson-g12b-a311d-libretech-cc'
235 03:28:18.136121 BRANCH='broonie-sound'
236 03:28:18.136323 SKIPFILE='/dev/null'
237 03:28:18.136522 SKIP_INSTALL='True'
238 03:28:18.136718 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-247-gbf99f9b489d8e/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 03:28:18.136922 TST_CASENAME=''
240 03:28:18.137119 TST_CMDFILES='rtc'
241 03:28:18.137766 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 03:28:18.138596 Creating lava-test-runner.conf files
244 03:28:18.138806 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/964633/lava-overlay-tyz3jb44/lava-964633/0 for stage 0
245 03:28:18.139182 - 0_timesync-off
246 03:28:18.139437 - 1_kselftest-rtc
247 03:28:18.139797 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 03:28:18.140122 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 03:28:41.506509 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 03:28:41.506961 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 03:28:41.507223 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 03:28:41.507491 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 03:28:41.507754 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 03:28:42.123629 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 03:28:42.124147 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 03:28:42.124424 extracting modules file /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964633/extract-nfsrootfs-9s95vfgz
257 03:28:43.487643 extracting modules file /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964633/extract-overlay-ramdisk-r22ysjyi/ramdisk
258 03:28:44.887409 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 03:28:44.887890 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 03:28:44.888216 [common] Applying overlay to NFS
261 03:28:44.888446 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964633/compress-overlay-yrt_x6kr/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/964633/extract-nfsrootfs-9s95vfgz
262 03:28:47.631977 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 03:28:47.632484 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 03:28:47.632787 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 03:28:47.633048 Converting downloaded kernel to a uImage
266 03:28:47.633373 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/kernel/Image /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/kernel/uImage
267 03:28:48.112868 output: Image Name:
268 03:28:48.113313 output: Created: Sat Nov 9 03:28:47 2024
269 03:28:48.113542 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 03:28:48.113759 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 03:28:48.113967 output: Load Address: 01080000
272 03:28:48.114173 output: Entry Point: 01080000
273 03:28:48.114377 output:
274 03:28:48.114719 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 03:28:48.114998 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 03:28:48.115276 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 03:28:48.115537 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 03:28:48.115802 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 03:28:48.116123 Building ramdisk /var/lib/lava/dispatcher/tmp/964633/extract-overlay-ramdisk-r22ysjyi/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/964633/extract-overlay-ramdisk-r22ysjyi/ramdisk
280 03:28:50.275289 >> 166792 blocks
281 03:28:58.088370 Adding RAMdisk u-boot header.
282 03:28:58.088834 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/964633/extract-overlay-ramdisk-r22ysjyi/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/964633/extract-overlay-ramdisk-r22ysjyi/ramdisk.cpio.gz.uboot
283 03:28:58.341133 output: Image Name:
284 03:28:58.341610 output: Created: Sat Nov 9 03:28:58 2024
285 03:28:58.342105 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 03:28:58.342566 output: Data Size: 23431945 Bytes = 22882.76 KiB = 22.35 MiB
287 03:28:58.343043 output: Load Address: 00000000
288 03:28:58.343491 output: Entry Point: 00000000
289 03:28:58.343941 output:
290 03:28:58.345111 rename /var/lib/lava/dispatcher/tmp/964633/extract-overlay-ramdisk-r22ysjyi/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/ramdisk/ramdisk.cpio.gz.uboot
291 03:28:58.345902 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 03:28:58.346513 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 03:28:58.347100 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 03:28:58.347601 No LXC device requested
295 03:28:58.348202 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 03:28:58.348782 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 03:28:58.349336 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 03:28:58.349798 Checking files for TFTP limit of 4294967296 bytes.
299 03:28:58.352742 end: 1 tftp-deploy (duration 00:01:18) [common]
300 03:28:58.353378 start: 2 uboot-action (timeout 00:05:00) [common]
301 03:28:58.353971 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 03:28:58.354535 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 03:28:58.355100 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 03:28:58.355689 Using kernel file from prepare-kernel: 964633/tftp-deploy-7s8c2mjm/kernel/uImage
305 03:28:58.356430 substitutions:
306 03:28:58.356891 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 03:28:58.357347 - {DTB_ADDR}: 0x01070000
308 03:28:58.357797 - {DTB}: 964633/tftp-deploy-7s8c2mjm/dtb/meson-g12b-a311d-libretech-cc.dtb
309 03:28:58.358253 - {INITRD}: 964633/tftp-deploy-7s8c2mjm/ramdisk/ramdisk.cpio.gz.uboot
310 03:28:58.358702 - {KERNEL_ADDR}: 0x01080000
311 03:28:58.359139 - {KERNEL}: 964633/tftp-deploy-7s8c2mjm/kernel/uImage
312 03:28:58.359580 - {LAVA_MAC}: None
313 03:28:58.360297 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/964633/extract-nfsrootfs-9s95vfgz
314 03:28:58.360794 - {NFS_SERVER_IP}: 192.168.6.2
315 03:28:58.361244 - {PRESEED_CONFIG}: None
316 03:28:58.361691 - {PRESEED_LOCAL}: None
317 03:28:58.362134 - {RAMDISK_ADDR}: 0x08000000
318 03:28:58.362570 - {RAMDISK}: 964633/tftp-deploy-7s8c2mjm/ramdisk/ramdisk.cpio.gz.uboot
319 03:28:58.363011 - {ROOT_PART}: None
320 03:28:58.363450 - {ROOT}: None
321 03:28:58.363883 - {SERVER_IP}: 192.168.6.2
322 03:28:58.364354 - {TEE_ADDR}: 0x83000000
323 03:28:58.364791 - {TEE}: None
324 03:28:58.365223 Parsed boot commands:
325 03:28:58.365647 - setenv autoload no
326 03:28:58.366079 - setenv initrd_high 0xffffffff
327 03:28:58.366507 - setenv fdt_high 0xffffffff
328 03:28:58.366936 - dhcp
329 03:28:58.367364 - setenv serverip 192.168.6.2
330 03:28:58.367798 - tftpboot 0x01080000 964633/tftp-deploy-7s8c2mjm/kernel/uImage
331 03:28:58.368266 - tftpboot 0x08000000 964633/tftp-deploy-7s8c2mjm/ramdisk/ramdisk.cpio.gz.uboot
332 03:28:58.368707 - tftpboot 0x01070000 964633/tftp-deploy-7s8c2mjm/dtb/meson-g12b-a311d-libretech-cc.dtb
333 03:28:58.369143 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/964633/extract-nfsrootfs-9s95vfgz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 03:28:58.369589 - bootm 0x01080000 0x08000000 0x01070000
335 03:28:58.370144 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 03:28:58.371794 start: 2.3 connect-device (timeout 00:05:00) [common]
338 03:28:58.372297 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 03:28:58.388076 Setting prompt string to ['lava-test: # ']
340 03:28:58.389709 end: 2.3 connect-device (duration 00:00:00) [common]
341 03:28:58.390409 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 03:28:58.391047 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 03:28:58.391654 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 03:28:58.392724 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 03:28:58.426893 >> OK - accepted request
346 03:28:58.429069 Returned 0 in 0 seconds
347 03:28:58.530266 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 03:28:58.532167 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 03:28:58.532829 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 03:28:58.533405 Setting prompt string to ['Hit any key to stop autoboot']
352 03:28:58.533924 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 03:28:58.535651 Trying 192.168.56.21...
354 03:28:58.536244 Connected to conserv1.
355 03:28:58.536723 Escape character is '^]'.
356 03:28:58.537206
357 03:28:58.537675 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 03:28:58.538159
359 03:29:09.890140 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 03:29:09.890801 bl2_stage_init 0x01
361 03:29:09.891306 bl2_stage_init 0x81
362 03:29:09.895736 hw id: 0x0000 - pwm id 0x01
363 03:29:09.896348 bl2_stage_init 0xc1
364 03:29:09.896829 bl2_stage_init 0x02
365 03:29:09.897285
366 03:29:09.901300 L0:00000000
367 03:29:09.901817 L1:20000703
368 03:29:09.902277 L2:00008067
369 03:29:09.902730 L3:14000000
370 03:29:09.906920 B2:00402000
371 03:29:09.907423 B1:e0f83180
372 03:29:09.907860
373 03:29:09.908343 TE: 58124
374 03:29:09.908778
375 03:29:09.912512 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 03:29:09.912990
377 03:29:09.913428 Board ID = 1
378 03:29:09.918090 Set A53 clk to 24M
379 03:29:09.918558 Set A73 clk to 24M
380 03:29:09.918991 Set clk81 to 24M
381 03:29:09.923682 A53 clk: 1200 MHz
382 03:29:09.924182 A73 clk: 1200 MHz
383 03:29:09.924619 CLK81: 166.6M
384 03:29:09.925047 smccc: 00012a92
385 03:29:09.929290 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 03:29:09.934913 board id: 1
387 03:29:09.940757 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 03:29:09.951424 fw parse done
389 03:29:09.957380 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 03:29:10.000032 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 03:29:10.010912 PIEI prepare done
392 03:29:10.011386 fastboot data load
393 03:29:10.011829 fastboot data verify
394 03:29:10.016669 verify result: 266
395 03:29:10.022250 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 03:29:10.022770 LPDDR4 probe
397 03:29:10.023232 ddr clk to 1584MHz
398 03:29:10.030291 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 03:29:10.067502
400 03:29:10.068060 dmc_version 0001
401 03:29:10.074170 Check phy result
402 03:29:10.080070 INFO : End of CA training
403 03:29:10.080590 INFO : End of initialization
404 03:29:10.085641 INFO : Training has run successfully!
405 03:29:10.086137 Check phy result
406 03:29:10.091256 INFO : End of initialization
407 03:29:10.091750 INFO : End of read enable training
408 03:29:10.096846 INFO : End of fine write leveling
409 03:29:10.102423 INFO : End of Write leveling coarse delay
410 03:29:10.102923 INFO : Training has run successfully!
411 03:29:10.103379 Check phy result
412 03:29:10.108085 INFO : End of initialization
413 03:29:10.108602 INFO : End of read dq deskew training
414 03:29:10.113650 INFO : End of MPR read delay center optimization
415 03:29:10.119215 INFO : End of write delay center optimization
416 03:29:10.124834 INFO : End of read delay center optimization
417 03:29:10.125333 INFO : End of max read latency training
418 03:29:10.130434 INFO : Training has run successfully!
419 03:29:10.130942 1D training succeed
420 03:29:10.139588 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 03:29:10.187174 Check phy result
422 03:29:10.187687 INFO : End of initialization
423 03:29:10.209817 INFO : End of 2D read delay Voltage center optimization
424 03:29:10.230112 INFO : End of 2D read delay Voltage center optimization
425 03:29:10.282154 INFO : End of 2D write delay Voltage center optimization
426 03:29:10.331455 INFO : End of 2D write delay Voltage center optimization
427 03:29:10.337064 INFO : Training has run successfully!
428 03:29:10.337570
429 03:29:10.338028 channel==0
430 03:29:10.342624 RxClkDly_Margin_A0==88 ps 9
431 03:29:10.343121 TxDqDly_Margin_A0==98 ps 10
432 03:29:10.348286 RxClkDly_Margin_A1==88 ps 9
433 03:29:10.348779 TxDqDly_Margin_A1==98 ps 10
434 03:29:10.349232 TrainedVREFDQ_A0==74
435 03:29:10.353847 TrainedVREFDQ_A1==74
436 03:29:10.354348 VrefDac_Margin_A0==25
437 03:29:10.354806 DeviceVref_Margin_A0==40
438 03:29:10.359449 VrefDac_Margin_A1==25
439 03:29:10.359941 DeviceVref_Margin_A1==40
440 03:29:10.360440
441 03:29:10.360891
442 03:29:10.365070 channel==1
443 03:29:10.365563 RxClkDly_Margin_A0==88 ps 9
444 03:29:10.366012 TxDqDly_Margin_A0==88 ps 9
445 03:29:10.370656 RxClkDly_Margin_A1==88 ps 9
446 03:29:10.371154 TxDqDly_Margin_A1==88 ps 9
447 03:29:10.376265 TrainedVREFDQ_A0==76
448 03:29:10.376764 TrainedVREFDQ_A1==77
449 03:29:10.377219 VrefDac_Margin_A0==22
450 03:29:10.381906 DeviceVref_Margin_A0==38
451 03:29:10.382430 VrefDac_Margin_A1==24
452 03:29:10.387463 DeviceVref_Margin_A1==37
453 03:29:10.387968
454 03:29:10.388466 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 03:29:10.388919
456 03:29:10.421019 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 0000001a 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 03:29:10.421660 2D training succeed
458 03:29:10.426665 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 03:29:10.432275 auto size-- 65535DDR cs0 size: 2048MB
460 03:29:10.432788 DDR cs1 size: 2048MB
461 03:29:10.437836 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 03:29:10.438334 cs0 DataBus test pass
463 03:29:10.443454 cs1 DataBus test pass
464 03:29:10.443948 cs0 AddrBus test pass
465 03:29:10.444444 cs1 AddrBus test pass
466 03:29:10.444892
467 03:29:10.449079 100bdlr_step_size ps== 420
468 03:29:10.449586 result report
469 03:29:10.454635 boot times 0Enable ddr reg access
470 03:29:10.459831 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 03:29:10.473264 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 03:29:11.046901 0.0;M3 CHK:0;cm4_sp_mode 0
473 03:29:11.047559 MVN_1=0x00000000
474 03:29:11.052332 MVN_2=0x00000000
475 03:29:11.058102 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 03:29:11.058605 OPS=0x10
477 03:29:11.059072 ring efuse init
478 03:29:11.059522 chipver efuse init
479 03:29:11.063701 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 03:29:11.069265 [0.018961 Inits done]
481 03:29:11.069756 secure task start!
482 03:29:11.070209 high task start!
483 03:29:11.073023 low task start!
484 03:29:11.073511 run into bl31
485 03:29:11.080567 NOTICE: BL31: v1.3(release):4fc40b1
486 03:29:11.088351 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 03:29:11.088857 NOTICE: BL31: G12A normal boot!
488 03:29:11.113731 NOTICE: BL31: BL33 decompress pass
489 03:29:11.119383 ERROR: Error initializing runtime service opteed_fast
490 03:29:12.352480
491 03:29:12.353142
492 03:29:12.360834 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 03:29:12.361336
494 03:29:12.361803 Model: Libre Computer AML-A311D-CC Alta
495 03:29:12.569323 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 03:29:12.592688 DRAM: 2 GiB (effective 3.8 GiB)
497 03:29:12.735585 Core: 408 devices, 31 uclasses, devicetree: separate
498 03:29:12.741541 WDT: Not starting watchdog@f0d0
499 03:29:12.773764 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 03:29:12.786212 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 03:29:12.791242 ** Bad device specification mmc 0 **
502 03:29:12.801530 Card did not respond to voltage select! : -110
503 03:29:12.809133 ** Bad device specification mmc 0 **
504 03:29:12.809617 Couldn't find partition mmc 0
505 03:29:12.817521 Card did not respond to voltage select! : -110
506 03:29:12.823037 ** Bad device specification mmc 0 **
507 03:29:12.823529 Couldn't find partition mmc 0
508 03:29:12.828196 Error: could not access storage.
509 03:29:14.090597 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 03:29:14.091205 bl2_stage_init 0x01
511 03:29:14.091678 bl2_stage_init 0x81
512 03:29:14.096189 hw id: 0x0000 - pwm id 0x01
513 03:29:14.096688 bl2_stage_init 0xc1
514 03:29:14.097147 bl2_stage_init 0x02
515 03:29:14.097596
516 03:29:14.101749 L0:00000000
517 03:29:14.102226 L1:20000703
518 03:29:14.102676 L2:00008067
519 03:29:14.103120 L3:14000000
520 03:29:14.107346 B2:00402000
521 03:29:14.107831 B1:e0f83180
522 03:29:14.108320
523 03:29:14.108770 TE: 58124
524 03:29:14.109218
525 03:29:14.112966 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 03:29:14.113455
527 03:29:14.113908 Board ID = 1
528 03:29:14.118535 Set A53 clk to 24M
529 03:29:14.119018 Set A73 clk to 24M
530 03:29:14.119471 Set clk81 to 24M
531 03:29:14.124169 A53 clk: 1200 MHz
532 03:29:14.124680 A73 clk: 1200 MHz
533 03:29:14.125150 CLK81: 166.6M
534 03:29:14.125606 smccc: 00012a92
535 03:29:14.129747 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 03:29:14.135343 board id: 1
537 03:29:14.141203 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 03:29:14.151871 fw parse done
539 03:29:14.157836 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 03:29:14.200530 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 03:29:14.211360 PIEI prepare done
542 03:29:14.211842 fastboot data load
543 03:29:14.212336 fastboot data verify
544 03:29:14.217092 verify result: 266
545 03:29:14.222701 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 03:29:14.223200 LPDDR4 probe
547 03:29:14.223651 ddr clk to 1584MHz
548 03:29:14.230679 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 03:29:14.267897
550 03:29:14.268442 dmc_version 0001
551 03:29:14.274588 Check phy result
552 03:29:14.280492 INFO : End of CA training
553 03:29:14.280988 INFO : End of initialization
554 03:29:14.286082 INFO : Training has run successfully!
555 03:29:14.286594 Check phy result
556 03:29:14.291686 INFO : End of initialization
557 03:29:14.292214 INFO : End of read enable training
558 03:29:14.297275 INFO : End of fine write leveling
559 03:29:14.302860 INFO : End of Write leveling coarse delay
560 03:29:14.303356 INFO : Training has run successfully!
561 03:29:14.303812 Check phy result
562 03:29:14.308510 INFO : End of initialization
563 03:29:14.309015 INFO : End of read dq deskew training
564 03:29:14.314088 INFO : End of MPR read delay center optimization
565 03:29:14.319669 INFO : End of write delay center optimization
566 03:29:14.325277 INFO : End of read delay center optimization
567 03:29:14.325778 INFO : End of max read latency training
568 03:29:14.330872 INFO : Training has run successfully!
569 03:29:14.331373 1D training succeed
570 03:29:14.340045 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 03:29:14.387735 Check phy result
572 03:29:14.388308 INFO : End of initialization
573 03:29:14.410262 INFO : End of 2D read delay Voltage center optimization
574 03:29:14.430520 INFO : End of 2D read delay Voltage center optimization
575 03:29:14.482521 INFO : End of 2D write delay Voltage center optimization
576 03:29:14.531967 INFO : End of 2D write delay Voltage center optimization
577 03:29:14.537519 INFO : Training has run successfully!
578 03:29:14.538044
579 03:29:14.538510 channel==0
580 03:29:14.543104 RxClkDly_Margin_A0==88 ps 9
581 03:29:14.543625 TxDqDly_Margin_A0==98 ps 10
582 03:29:14.548716 RxClkDly_Margin_A1==78 ps 8
583 03:29:14.549251 TxDqDly_Margin_A1==88 ps 9
584 03:29:14.549712 TrainedVREFDQ_A0==74
585 03:29:14.554306 TrainedVREFDQ_A1==74
586 03:29:14.554821 VrefDac_Margin_A0==25
587 03:29:14.555275 DeviceVref_Margin_A0==40
588 03:29:14.559877 VrefDac_Margin_A1==26
589 03:29:14.560415 DeviceVref_Margin_A1==40
590 03:29:14.560873
591 03:29:14.561325
592 03:29:14.561772 channel==1
593 03:29:14.565520 RxClkDly_Margin_A0==98 ps 10
594 03:29:14.566049 TxDqDly_Margin_A0==98 ps 10
595 03:29:14.571108 RxClkDly_Margin_A1==88 ps 9
596 03:29:14.571622 TxDqDly_Margin_A1==88 ps 9
597 03:29:14.576712 TrainedVREFDQ_A0==77
598 03:29:14.577228 TrainedVREFDQ_A1==77
599 03:29:14.577692 VrefDac_Margin_A0==22
600 03:29:14.582301 DeviceVref_Margin_A0==37
601 03:29:14.582801 VrefDac_Margin_A1==24
602 03:29:14.587898 DeviceVref_Margin_A1==37
603 03:29:14.588428
604 03:29:14.588886 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 03:29:14.589336
606 03:29:14.621432 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
607 03:29:14.621998 2D training succeed
608 03:29:14.627115 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 03:29:14.632689 auto size-- 65535DDR cs0 size: 2048MB
610 03:29:14.633194 DDR cs1 size: 2048MB
611 03:29:14.638301 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 03:29:14.638807 cs0 DataBus test pass
613 03:29:14.643883 cs1 DataBus test pass
614 03:29:14.644432 cs0 AddrBus test pass
615 03:29:14.644888 cs1 AddrBus test pass
616 03:29:14.645336
617 03:29:14.649489 100bdlr_step_size ps== 420
618 03:29:14.650006 result report
619 03:29:14.655076 boot times 0Enable ddr reg access
620 03:29:14.660345 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 03:29:14.673808 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 03:29:15.247415 0.0;M3 CHK:0;cm4_sp_mode 0
623 03:29:15.248068 MVN_1=0x00000000
624 03:29:15.252889 MVN_2=0x00000000
625 03:29:15.258652 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 03:29:15.259176 OPS=0x10
627 03:29:15.259641 ring efuse init
628 03:29:15.260163 chipver efuse init
629 03:29:15.264232 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 03:29:15.269794 [0.018961 Inits done]
631 03:29:15.270266 secure task start!
632 03:29:15.270700 high task start!
633 03:29:15.274402 low task start!
634 03:29:15.274902 run into bl31
635 03:29:15.281054 NOTICE: BL31: v1.3(release):4fc40b1
636 03:29:15.288869 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 03:29:15.289346 NOTICE: BL31: G12A normal boot!
638 03:29:15.314788 NOTICE: BL31: BL33 decompress pass
639 03:29:15.320482 ERROR: Error initializing runtime service opteed_fast
640 03:29:16.553449
641 03:29:16.554134
642 03:29:16.561794 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 03:29:16.562308
644 03:29:16.562772 Model: Libre Computer AML-A311D-CC Alta
645 03:29:16.770112 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 03:29:16.793528 DRAM: 2 GiB (effective 3.8 GiB)
647 03:29:16.936485 Core: 408 devices, 31 uclasses, devicetree: separate
648 03:29:16.942443 WDT: Not starting watchdog@f0d0
649 03:29:16.974676 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 03:29:16.987146 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 03:29:16.992151 ** Bad device specification mmc 0 **
652 03:29:17.002445 Card did not respond to voltage select! : -110
653 03:29:17.010104 ** Bad device specification mmc 0 **
654 03:29:17.010595 Couldn't find partition mmc 0
655 03:29:17.018517 Card did not respond to voltage select! : -110
656 03:29:17.024059 ** Bad device specification mmc 0 **
657 03:29:17.024570 Couldn't find partition mmc 0
658 03:29:17.029070 Error: could not access storage.
659 03:29:17.371575 Net: eth0: ethernet@ff3f0000
660 03:29:17.372322 starting USB...
661 03:29:17.623364 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 03:29:17.624090 Starting the controller
663 03:29:17.630249 USB XHCI 1.10
664 03:29:19.340933 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 03:29:19.341613 bl2_stage_init 0x01
666 03:29:19.342095 bl2_stage_init 0x81
667 03:29:19.346618 hw id: 0x0000 - pwm id 0x01
668 03:29:19.347139 bl2_stage_init 0xc1
669 03:29:19.347603 bl2_stage_init 0x02
670 03:29:19.348110
671 03:29:19.352052 L0:00000000
672 03:29:19.352574 L1:20000703
673 03:29:19.353036 L2:00008067
674 03:29:19.353482 L3:14000000
675 03:29:19.357626 B2:00402000
676 03:29:19.358141 B1:e0f83180
677 03:29:19.358601
678 03:29:19.359056 TE: 58159
679 03:29:19.359506
680 03:29:19.363253 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 03:29:19.363783
682 03:29:19.364287 Board ID = 1
683 03:29:19.368904 Set A53 clk to 24M
684 03:29:19.369425 Set A73 clk to 24M
685 03:29:19.369882 Set clk81 to 24M
686 03:29:19.374527 A53 clk: 1200 MHz
687 03:29:19.375075 A73 clk: 1200 MHz
688 03:29:19.375554 CLK81: 166.6M
689 03:29:19.376050 smccc: 00012ab5
690 03:29:19.380068 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 03:29:19.385729 board id: 1
692 03:29:19.391269 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 03:29:19.402176 fw parse done
694 03:29:19.407333 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 03:29:19.449788 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 03:29:19.461553 PIEI prepare done
697 03:29:19.462082 fastboot data load
698 03:29:19.462551 fastboot data verify
699 03:29:19.467198 verify result: 266
700 03:29:19.472821 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 03:29:19.473395 LPDDR4 probe
702 03:29:19.473855 ddr clk to 1584MHz
703 03:29:19.480790 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 03:29:19.518029
705 03:29:19.518618 dmc_version 0001
706 03:29:19.524698 Check phy result
707 03:29:19.530528 INFO : End of CA training
708 03:29:19.531062 INFO : End of initialization
709 03:29:19.536144 INFO : Training has run successfully!
710 03:29:19.536681 Check phy result
711 03:29:19.541765 INFO : End of initialization
712 03:29:19.542308 INFO : End of read enable training
713 03:29:19.547384 INFO : End of fine write leveling
714 03:29:19.552967 INFO : End of Write leveling coarse delay
715 03:29:19.553534 INFO : Training has run successfully!
716 03:29:19.553998 Check phy result
717 03:29:19.558556 INFO : End of initialization
718 03:29:19.559102 INFO : End of read dq deskew training
719 03:29:19.564190 INFO : End of MPR read delay center optimization
720 03:29:19.569781 INFO : End of write delay center optimization
721 03:29:19.575368 INFO : End of read delay center optimization
722 03:29:19.575901 INFO : End of max read latency training
723 03:29:19.580940 INFO : Training has run successfully!
724 03:29:19.581460 1D training succeed
725 03:29:19.589889 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 03:29:19.637698 Check phy result
727 03:29:19.638271 INFO : End of initialization
728 03:29:19.659520 INFO : End of 2D read delay Voltage center optimization
729 03:29:19.678896 INFO : End of 2D read delay Voltage center optimization
730 03:29:19.730817 INFO : End of 2D write delay Voltage center optimization
731 03:29:19.780459 INFO : End of 2D write delay Voltage center optimization
732 03:29:19.785833 INFO : Training has run successfully!
733 03:29:19.786363
734 03:29:19.786837 channel==0
735 03:29:19.791437 RxClkDly_Margin_A0==88 ps 9
736 03:29:19.791958 TxDqDly_Margin_A0==98 ps 10
737 03:29:19.797002 RxClkDly_Margin_A1==88 ps 9
738 03:29:19.797532 TxDqDly_Margin_A1==98 ps 10
739 03:29:19.798001 TrainedVREFDQ_A0==74
740 03:29:19.802613 TrainedVREFDQ_A1==74
741 03:29:19.803121 VrefDac_Margin_A0==25
742 03:29:19.803574 DeviceVref_Margin_A0==40
743 03:29:19.808263 VrefDac_Margin_A1==25
744 03:29:19.808778 DeviceVref_Margin_A1==40
745 03:29:19.809235
746 03:29:19.809686
747 03:29:19.813783 channel==1
748 03:29:19.814294 RxClkDly_Margin_A0==88 ps 9
749 03:29:19.814747 TxDqDly_Margin_A0==88 ps 9
750 03:29:19.819414 RxClkDly_Margin_A1==88 ps 9
751 03:29:19.819942 TxDqDly_Margin_A1==88 ps 9
752 03:29:19.825027 TrainedVREFDQ_A0==77
753 03:29:19.825547 TrainedVREFDQ_A1==77
754 03:29:19.826013 VrefDac_Margin_A0==23
755 03:29:19.830636 DeviceVref_Margin_A0==37
756 03:29:19.831154 VrefDac_Margin_A1==24
757 03:29:19.836274 DeviceVref_Margin_A1==37
758 03:29:19.836792
759 03:29:19.837254 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 03:29:19.837707
761 03:29:19.869952 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000019 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 03:29:19.870587 2D training succeed
763 03:29:19.875505 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 03:29:19.881058 auto size-- 65535DDR cs0 size: 2048MB
765 03:29:19.881651 DDR cs1 size: 2048MB
766 03:29:19.886680 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 03:29:19.887294 cs0 DataBus test pass
768 03:29:19.892309 cs1 DataBus test pass
769 03:29:19.892908 cs0 AddrBus test pass
770 03:29:19.893406 cs1 AddrBus test pass
771 03:29:19.893919
772 03:29:19.897896 100bdlr_step_size ps== 420
773 03:29:19.898462 result report
774 03:29:19.903496 boot times 0Enable ddr reg access
775 03:29:19.908603 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 03:29:19.922061 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 03:29:20.495626 0.0;M3 CHK:0;cm4_sp_mode 0
778 03:29:20.496346 MVN_1=0x00000000
779 03:29:20.501156 MVN_2=0x00000000
780 03:29:20.506872 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 03:29:20.507452 OPS=0x10
782 03:29:20.507902 ring efuse init
783 03:29:20.508384 chipver efuse init
784 03:29:20.512414 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 03:29:20.518069 [0.018961 Inits done]
786 03:29:20.518549 secure task start!
787 03:29:20.518991 high task start!
788 03:29:20.522623 low task start!
789 03:29:20.523108 run into bl31
790 03:29:20.529276 NOTICE: BL31: v1.3(release):4fc40b1
791 03:29:20.537100 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 03:29:20.537597 NOTICE: BL31: G12A normal boot!
793 03:29:20.562489 NOTICE: BL31: BL33 decompress pass
794 03:29:20.567176 ERROR: Error initializing runtime service opteed_fast
795 03:29:21.801058
796 03:29:21.801456
797 03:29:21.809472 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 03:29:21.809765
799 03:29:21.809992 Model: Libre Computer AML-A311D-CC Alta
800 03:29:22.017950 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 03:29:22.041375 DRAM: 2 GiB (effective 3.8 GiB)
802 03:29:22.184323 Core: 408 devices, 31 uclasses, devicetree: separate
803 03:29:22.190108 WDT: Not starting watchdog@f0d0
804 03:29:22.222360 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 03:29:22.234838 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 03:29:22.240412 ** Bad device specification mmc 0 **
807 03:29:22.250132 Card did not respond to voltage select! : -110
808 03:29:22.257753 ** Bad device specification mmc 0 **
809 03:29:22.258032 Couldn't find partition mmc 0
810 03:29:22.266106 Card did not respond to voltage select! : -110
811 03:29:22.271629 ** Bad device specification mmc 0 **
812 03:29:22.271917 Couldn't find partition mmc 0
813 03:29:22.276778 Error: could not access storage.
814 03:29:22.619321 Net: eth0: ethernet@ff3f0000
815 03:29:22.619973 starting USB...
816 03:29:22.871158 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 03:29:22.871787 Starting the controller
818 03:29:22.878053 USB XHCI 1.10
819 03:29:25.042530 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 03:29:25.043200 bl2_stage_init 0x01
821 03:29:25.043679 bl2_stage_init 0x81
822 03:29:25.047904 hw id: 0x0000 - pwm id 0x01
823 03:29:25.048540 bl2_stage_init 0xc1
824 03:29:25.049010 bl2_stage_init 0x02
825 03:29:25.049462
826 03:29:25.053811 L0:00000000
827 03:29:25.054352 L1:20000703
828 03:29:25.054818 L2:00008067
829 03:29:25.055284 L3:14000000
830 03:29:25.056541 B2:00402000
831 03:29:25.057034 B1:e0f83180
832 03:29:25.057486
833 03:29:25.057931 TE: 58124
834 03:29:25.058381
835 03:29:25.067682 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 03:29:25.068212
837 03:29:25.068673 Board ID = 1
838 03:29:25.069116 Set A53 clk to 24M
839 03:29:25.069554 Set A73 clk to 24M
840 03:29:25.073281 Set clk81 to 24M
841 03:29:25.073766 A53 clk: 1200 MHz
842 03:29:25.074218 A73 clk: 1200 MHz
843 03:29:25.078806 CLK81: 166.6M
844 03:29:25.079300 smccc: 00012a92
845 03:29:25.084506 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 03:29:25.085076 board id: 1
847 03:29:25.093241 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 03:29:25.103724 fw parse done
849 03:29:25.109630 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 03:29:25.152317 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 03:29:25.163265 PIEI prepare done
852 03:29:25.163825 fastboot data load
853 03:29:25.164447 fastboot data verify
854 03:29:25.168835 verify result: 266
855 03:29:25.174421 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 03:29:25.174989 LPDDR4 probe
857 03:29:25.175462 ddr clk to 1584MHz
858 03:29:25.182477 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 03:29:25.218820
860 03:29:25.219453 dmc_version 0001
861 03:29:25.226354 Check phy result
862 03:29:25.232380 INFO : End of CA training
863 03:29:25.232918 INFO : End of initialization
864 03:29:25.237865 INFO : Training has run successfully!
865 03:29:25.238405 Check phy result
866 03:29:25.244183 INFO : End of initialization
867 03:29:25.244719 INFO : End of read enable training
868 03:29:25.249929 INFO : End of fine write leveling
869 03:29:25.254689 INFO : End of Write leveling coarse delay
870 03:29:25.255317 INFO : Training has run successfully!
871 03:29:25.255788 Check phy result
872 03:29:25.260266 INFO : End of initialization
873 03:29:25.260801 INFO : End of read dq deskew training
874 03:29:25.265767 INFO : End of MPR read delay center optimization
875 03:29:25.271404 INFO : End of write delay center optimization
876 03:29:25.277566 INFO : End of read delay center optimization
877 03:29:25.278198 INFO : End of max read latency training
878 03:29:25.282596 INFO : Training has run successfully!
879 03:29:25.283153 1D training succeed
880 03:29:25.291800 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 03:29:25.339405 Check phy result
882 03:29:25.339971 INFO : End of initialization
883 03:29:25.362007 INFO : End of 2D read delay Voltage center optimization
884 03:29:25.381407 INFO : End of 2D read delay Voltage center optimization
885 03:29:25.434341 INFO : End of 2D write delay Voltage center optimization
886 03:29:25.483654 INFO : End of 2D write delay Voltage center optimization
887 03:29:25.489230 INFO : Training has run successfully!
888 03:29:25.489729
889 03:29:25.490187 channel==0
890 03:29:25.494844 RxClkDly_Margin_A0==88 ps 9
891 03:29:25.495382 TxDqDly_Margin_A0==98 ps 10
892 03:29:25.498118 RxClkDly_Margin_A1==88 ps 9
893 03:29:25.498638 TxDqDly_Margin_A1==98 ps 10
894 03:29:25.503714 TrainedVREFDQ_A0==74
895 03:29:25.504310 TrainedVREFDQ_A1==75
896 03:29:25.504775 VrefDac_Margin_A0==24
897 03:29:25.509322 DeviceVref_Margin_A0==40
898 03:29:25.509860 VrefDac_Margin_A1==24
899 03:29:25.514868 DeviceVref_Margin_A1==39
900 03:29:25.515365
901 03:29:25.515805
902 03:29:25.516286 channel==1
903 03:29:25.516757 RxClkDly_Margin_A0==98 ps 10
904 03:29:25.520493 TxDqDly_Margin_A0==88 ps 9
905 03:29:25.521013 RxClkDly_Margin_A1==98 ps 10
906 03:29:25.526120 TxDqDly_Margin_A1==88 ps 9
907 03:29:25.526605 TrainedVREFDQ_A0==76
908 03:29:25.527040 TrainedVREFDQ_A1==77
909 03:29:25.531685 VrefDac_Margin_A0==22
910 03:29:25.532192 DeviceVref_Margin_A0==38
911 03:29:25.537308 VrefDac_Margin_A1==22
912 03:29:25.537779 DeviceVref_Margin_A1==37
913 03:29:25.538208
914 03:29:25.542918 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 03:29:25.543395
916 03:29:25.570931 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
917 03:29:25.576635 2D training succeed
918 03:29:25.582202 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 03:29:25.582762 auto size-- 65535DDR cs0 size: 2048MB
920 03:29:25.587774 DDR cs1 size: 2048MB
921 03:29:25.588395 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 03:29:25.593357 cs0 DataBus test pass
923 03:29:25.593903 cs1 DataBus test pass
924 03:29:25.594347 cs0 AddrBus test pass
925 03:29:25.598981 cs1 AddrBus test pass
926 03:29:25.599529
927 03:29:25.600058 100bdlr_step_size ps== 420
928 03:29:25.600541 result report
929 03:29:25.604576 boot times 0Enable ddr reg access
930 03:29:25.612244 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 03:29:25.625706 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 03:29:26.198675 0.0;M3 CHK:0;cm4_sp_mode 0
933 03:29:26.199374 MVN_1=0x00000000
934 03:29:26.204257 MVN_2=0x00000000
935 03:29:26.209932 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 03:29:26.210484 OPS=0x10
937 03:29:26.210961 ring efuse init
938 03:29:26.211419 chipver efuse init
939 03:29:26.215517 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 03:29:26.221201 [0.018961 Inits done]
941 03:29:26.221762 secure task start!
942 03:29:26.222264 high task start!
943 03:29:26.225728 low task start!
944 03:29:26.226281 run into bl31
945 03:29:26.232371 NOTICE: BL31: v1.3(release):4fc40b1
946 03:29:26.240244 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 03:29:26.240807 NOTICE: BL31: G12A normal boot!
948 03:29:26.265541 NOTICE: BL31: BL33 decompress pass
949 03:29:26.271278 ERROR: Error initializing runtime service opteed_fast
950 03:29:27.504119
951 03:29:27.504788
952 03:29:27.512586 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 03:29:27.513354
954 03:29:27.514003 Model: Libre Computer AML-A311D-CC Alta
955 03:29:27.721048 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 03:29:27.744412 DRAM: 2 GiB (effective 3.8 GiB)
957 03:29:27.887315 Core: 408 devices, 31 uclasses, devicetree: separate
958 03:29:27.893189 WDT: Not starting watchdog@f0d0
959 03:29:27.925467 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 03:29:27.937844 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 03:29:27.942847 ** Bad device specification mmc 0 **
962 03:29:27.953203 Card did not respond to voltage select! : -110
963 03:29:27.960841 ** Bad device specification mmc 0 **
964 03:29:27.961214 Couldn't find partition mmc 0
965 03:29:27.969154 Card did not respond to voltage select! : -110
966 03:29:27.974709 ** Bad device specification mmc 0 **
967 03:29:27.975069 Couldn't find partition mmc 0
968 03:29:27.979698 Error: could not access storage.
969 03:29:28.323354 Net: eth0: ethernet@ff3f0000
970 03:29:28.323787 starting USB...
971 03:29:28.575135 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 03:29:28.575773 Starting the controller
973 03:29:28.582041 USB XHCI 1.10
974 03:29:30.442404 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 03:29:30.442851 bl2_stage_init 0x01
976 03:29:30.443086 bl2_stage_init 0x81
977 03:29:30.447916 hw id: 0x0000 - pwm id 0x01
978 03:29:30.448249 bl2_stage_init 0xc1
979 03:29:30.448471 bl2_stage_init 0x02
980 03:29:30.448689
981 03:29:30.453542 L0:00000000
982 03:29:30.453834 L1:20000703
983 03:29:30.454071 L2:00008067
984 03:29:30.454315 L3:14000000
985 03:29:30.459094 B2:00402000
986 03:29:30.459398 B1:e0f83180
987 03:29:30.459630
988 03:29:30.459855 TE: 58159
989 03:29:30.460101
990 03:29:30.464651 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 03:29:30.464929
992 03:29:30.465147 Board ID = 1
993 03:29:30.470280 Set A53 clk to 24M
994 03:29:30.470567 Set A73 clk to 24M
995 03:29:30.470785 Set clk81 to 24M
996 03:29:30.475797 A53 clk: 1200 MHz
997 03:29:30.476102 A73 clk: 1200 MHz
998 03:29:30.476324 CLK81: 166.6M
999 03:29:30.476535 smccc: 00012ab5
1000 03:29:30.481404 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 03:29:30.487050 board id: 1
1002 03:29:30.492941 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 03:29:30.503556 fw parse done
1004 03:29:30.509521 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 03:29:30.552260 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 03:29:30.563114 PIEI prepare done
1007 03:29:30.563630 fastboot data load
1008 03:29:30.564035 fastboot data verify
1009 03:29:30.568682 verify result: 266
1010 03:29:30.574254 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 03:29:30.574715 LPDDR4 probe
1012 03:29:30.575090 ddr clk to 1584MHz
1013 03:29:30.582262 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 03:29:30.619572
1015 03:29:30.620225 dmc_version 0001
1016 03:29:30.626217 Check phy result
1017 03:29:30.632129 INFO : End of CA training
1018 03:29:30.632626 INFO : End of initialization
1019 03:29:30.637638 INFO : Training has run successfully!
1020 03:29:30.638022 Check phy result
1021 03:29:30.643290 INFO : End of initialization
1022 03:29:30.643803 INFO : End of read enable training
1023 03:29:30.648884 INFO : End of fine write leveling
1024 03:29:30.654484 INFO : End of Write leveling coarse delay
1025 03:29:30.654952 INFO : Training has run successfully!
1026 03:29:30.655331 Check phy result
1027 03:29:30.660144 INFO : End of initialization
1028 03:29:30.660609 INFO : End of read dq deskew training
1029 03:29:30.665656 INFO : End of MPR read delay center optimization
1030 03:29:30.671339 INFO : End of write delay center optimization
1031 03:29:30.676859 INFO : End of read delay center optimization
1032 03:29:30.677309 INFO : End of max read latency training
1033 03:29:30.682462 INFO : Training has run successfully!
1034 03:29:30.682912 1D training succeed
1035 03:29:30.691672 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 03:29:30.739288 Check phy result
1037 03:29:30.739855 INFO : End of initialization
1038 03:29:30.760929 INFO : End of 2D read delay Voltage center optimization
1039 03:29:30.780989 INFO : End of 2D read delay Voltage center optimization
1040 03:29:30.832829 INFO : End of 2D write delay Voltage center optimization
1041 03:29:30.882208 INFO : End of 2D write delay Voltage center optimization
1042 03:29:30.887616 INFO : Training has run successfully!
1043 03:29:30.888102
1044 03:29:30.888501 channel==0
1045 03:29:30.893317 RxClkDly_Margin_A0==88 ps 9
1046 03:29:30.893737 TxDqDly_Margin_A0==98 ps 10
1047 03:29:30.896582 RxClkDly_Margin_A1==88 ps 9
1048 03:29:30.897027 TxDqDly_Margin_A1==98 ps 10
1049 03:29:30.902176 TrainedVREFDQ_A0==74
1050 03:29:30.902634 TrainedVREFDQ_A1==74
1051 03:29:30.903288 VrefDac_Margin_A0==25
1052 03:29:30.907965 DeviceVref_Margin_A0==40
1053 03:29:30.908755 VrefDac_Margin_A1==25
1054 03:29:30.913473 DeviceVref_Margin_A1==40
1055 03:29:30.913930
1056 03:29:30.914307
1057 03:29:30.914648 channel==1
1058 03:29:30.915006 RxClkDly_Margin_A0==98 ps 10
1059 03:29:30.919073 TxDqDly_Margin_A0==98 ps 10
1060 03:29:30.919492 RxClkDly_Margin_A1==88 ps 9
1061 03:29:30.924650 TxDqDly_Margin_A1==88 ps 9
1062 03:29:30.925071 TrainedVREFDQ_A0==77
1063 03:29:30.925433 TrainedVREFDQ_A1==77
1064 03:29:30.930192 VrefDac_Margin_A0==22
1065 03:29:30.930599 DeviceVref_Margin_A0==37
1066 03:29:30.935894 VrefDac_Margin_A1==24
1067 03:29:30.936264 DeviceVref_Margin_A1==37
1068 03:29:30.936524
1069 03:29:30.941455 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 03:29:30.941904
1071 03:29:30.969484 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 03:29:30.975000 2D training succeed
1073 03:29:30.980520 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 03:29:30.980958 auto size-- 65535DDR cs0 size: 2048MB
1075 03:29:30.986056 DDR cs1 size: 2048MB
1076 03:29:30.986484 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 03:29:30.991683 cs0 DataBus test pass
1078 03:29:30.992094 cs1 DataBus test pass
1079 03:29:30.992499 cs0 AddrBus test pass
1080 03:29:30.997289 cs1 AddrBus test pass
1081 03:29:30.997686
1082 03:29:30.998048 100bdlr_step_size ps== 420
1083 03:29:30.998410 result report
1084 03:29:31.002902 boot times 0Enable ddr reg access
1085 03:29:31.010540 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 03:29:31.024053 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 03:29:31.596151 0.0;M3 CHK:0;cm4_sp_mode 0
1088 03:29:31.596757 MVN_1=0x00000000
1089 03:29:31.601730 MVN_2=0x00000000
1090 03:29:31.607450 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 03:29:31.608367 OPS=0x10
1092 03:29:31.609081 ring efuse init
1093 03:29:31.609803 chipver efuse init
1094 03:29:31.613035 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 03:29:31.618606 [0.018961 Inits done]
1096 03:29:31.619420 secure task start!
1097 03:29:31.620158 high task start!
1098 03:29:31.623202 low task start!
1099 03:29:31.623961 run into bl31
1100 03:29:31.629817 NOTICE: BL31: v1.3(release):4fc40b1
1101 03:29:31.637591 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 03:29:31.638017 NOTICE: BL31: G12A normal boot!
1103 03:29:31.663032 NOTICE: BL31: BL33 decompress pass
1104 03:29:31.668666 ERROR: Error initializing runtime service opteed_fast
1105 03:29:32.901540
1106 03:29:32.902174
1107 03:29:32.909883 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 03:29:32.910335
1109 03:29:32.910743 Model: Libre Computer AML-A311D-CC Alta
1110 03:29:33.118370 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 03:29:33.141735 DRAM: 2 GiB (effective 3.8 GiB)
1112 03:29:33.284722 Core: 408 devices, 31 uclasses, devicetree: separate
1113 03:29:33.289594 WDT: Not starting watchdog@f0d0
1114 03:29:33.322835 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 03:29:33.335307 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 03:29:33.339303 ** Bad device specification mmc 0 **
1117 03:29:33.350593 Card did not respond to voltage select! : -110
1118 03:29:33.357281 ** Bad device specification mmc 0 **
1119 03:29:33.357760 Couldn't find partition mmc 0
1120 03:29:33.366601 Card did not respond to voltage select! : -110
1121 03:29:33.372323 ** Bad device specification mmc 0 **
1122 03:29:33.372850 Couldn't find partition mmc 0
1123 03:29:33.376254 Error: could not access storage.
1124 03:29:33.718707 Net: eth0: ethernet@ff3f0000
1125 03:29:33.719320 starting USB...
1126 03:29:33.971454 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 03:29:33.972105 Starting the controller
1128 03:29:33.977471 USB XHCI 1.10
1129 03:29:35.532633 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 03:29:35.539877 scanning usb for storage devices... 0 Storage Device(s) found
1132 03:29:35.591594 Hit any key to stop autoboot: 1
1133 03:29:35.592639 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 03:29:35.593268 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 03:29:35.593729 Setting prompt string to ['=>']
1136 03:29:35.594205 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 03:29:35.598209 0
1138 03:29:35.599062 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 03:29:35.599551 Sending with 10 millisecond of delay
1141 03:29:36.734103 => setenv autoload no
1142 03:29:36.744853 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 03:29:36.749652 setenv autoload no
1144 03:29:36.750382 Sending with 10 millisecond of delay
1146 03:29:38.547459 => setenv initrd_high 0xffffffff
1147 03:29:38.558371 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 03:29:38.559402 setenv initrd_high 0xffffffff
1149 03:29:38.560159 Sending with 10 millisecond of delay
1151 03:29:40.176468 => setenv fdt_high 0xffffffff
1152 03:29:40.187251 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 03:29:40.188087 setenv fdt_high 0xffffffff
1154 03:29:40.188807 Sending with 10 millisecond of delay
1156 03:29:40.480657 => dhcp
1157 03:29:40.491441 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 03:29:40.492324 dhcp
1159 03:29:40.492769 Speed: 1000, full duplex
1160 03:29:40.493186 BOOTP broadcast 1
1161 03:29:40.501625 DHCP client bound to address 192.168.6.27 (10 ms)
1162 03:29:40.502343 Sending with 10 millisecond of delay
1164 03:29:42.179012 => setenv serverip 192.168.6.2
1165 03:29:42.190244 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 03:29:42.191347 setenv serverip 192.168.6.2
1167 03:29:42.192114 Sending with 10 millisecond of delay
1169 03:29:45.916577 => tftpboot 0x01080000 964633/tftp-deploy-7s8c2mjm/kernel/uImage
1170 03:29:45.927443 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 03:29:45.928424 tftpboot 0x01080000 964633/tftp-deploy-7s8c2mjm/kernel/uImage
1172 03:29:45.928927 Speed: 1000, full duplex
1173 03:29:45.929390 Using ethernet@ff3f0000 device
1174 03:29:45.930172 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 03:29:45.935643 Filename '964633/tftp-deploy-7s8c2mjm/kernel/uImage'.
1176 03:29:45.939547 Load address: 0x1080000
1177 03:29:48.837080 Loading: *################################################## 43.6 MiB
1178 03:29:48.837489 15 MiB/s
1179 03:29:48.837705 done
1180 03:29:48.841354 Bytes transferred = 45713984 (2b98a40 hex)
1181 03:29:48.841938 Sending with 10 millisecond of delay
1183 03:29:53.529948 => tftpboot 0x08000000 964633/tftp-deploy-7s8c2mjm/ramdisk/ramdisk.cpio.gz.uboot
1184 03:29:53.541001 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 03:29:53.541965 tftpboot 0x08000000 964633/tftp-deploy-7s8c2mjm/ramdisk/ramdisk.cpio.gz.uboot
1186 03:29:53.542425 Speed: 1000, full duplex
1187 03:29:53.542851 Using ethernet@ff3f0000 device
1188 03:29:53.543383 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 03:29:53.554891 Filename '964633/tftp-deploy-7s8c2mjm/ramdisk/ramdisk.cpio.gz.uboot'.
1190 03:29:53.555409 Load address: 0x8000000
1191 03:30:00.938900 Loading: *########T ######################################### UDP wrong checksum 00000005 00007b18
1192 03:30:05.939400 T UDP wrong checksum 00000005 00007b18
1193 03:30:15.942795 T T UDP wrong checksum 00000005 00007b18
1194 03:30:35.946938 T T T T UDP wrong checksum 00000005 00007b18
1195 03:30:50.950945 T T
1196 03:30:50.951623 Retry count exceeded; starting again
1198 03:30:50.953233 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1201 03:30:50.955312 end: 2.4 uboot-commands (duration 00:01:53) [common]
1203 03:30:50.956910 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1205 03:30:50.958013 end: 2 uboot-action (duration 00:01:53) [common]
1207 03:30:50.959675 Cleaning after the job
1208 03:30:50.960307 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/ramdisk
1209 03:30:50.961609 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/kernel
1210 03:30:51.011018 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/dtb
1211 03:30:51.011800 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/nfsrootfs
1212 03:30:51.171156 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964633/tftp-deploy-7s8c2mjm/modules
1213 03:30:51.190251 start: 4.1 power-off (timeout 00:00:30) [common]
1214 03:30:51.190884 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1215 03:30:51.223796 >> OK - accepted request
1216 03:30:51.225595 Returned 0 in 0 seconds
1217 03:30:51.326310 end: 4.1 power-off (duration 00:00:00) [common]
1219 03:30:51.327246 start: 4.2 read-feedback (timeout 00:10:00) [common]
1220 03:30:51.327886 Listened to connection for namespace 'common' for up to 1s
1221 03:30:52.328786 Finalising connection for namespace 'common'
1222 03:30:52.329220 Disconnecting from shell: Finalise
1223 03:30:52.329507 =>
1224 03:30:52.430252 end: 4.2 read-feedback (duration 00:00:01) [common]
1225 03:30:52.430698 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/964633
1226 03:30:55.357429 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/964633
1227 03:30:55.358053 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.