Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 05:27:45.675719 lava-dispatcher, installed at version: 2024.01
2 05:27:45.676602 start: 0 validate
3 05:27:45.677126 Start time: 2024-11-09 05:27:45.677095+00:00 (UTC)
4 05:27:45.677720 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 05:27:45.678369 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 05:27:45.716139 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 05:27:45.716710 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-256-gebd9c70be2b2%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 05:27:45.743949 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 05:27:45.744588 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-256-gebd9c70be2b2%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 05:27:45.766831 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 05:27:45.767409 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 05:27:45.794596 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 05:27:45.795124 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-256-gebd9c70be2b2%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 05:27:45.829529 validate duration: 0.15
16 05:27:45.830631 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:27:45.831140 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:27:45.831584 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:27:45.832382 Not decompressing ramdisk as can be used compressed.
20 05:27:45.832872 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 05:27:45.833273 saving as /var/lib/lava/dispatcher/tmp/965201/tftp-deploy-870n_78c/ramdisk/initrd.cpio.gz
22 05:27:45.833590 total size: 4775763 (4 MB)
23 05:27:45.868794 progress 0 % (0 MB)
24 05:27:45.873896 progress 5 % (0 MB)
25 05:27:45.877635 progress 10 % (0 MB)
26 05:27:45.881662 progress 15 % (0 MB)
27 05:27:45.886644 progress 20 % (0 MB)
28 05:27:45.891468 progress 25 % (1 MB)
29 05:27:45.895204 progress 30 % (1 MB)
30 05:27:45.899633 progress 35 % (1 MB)
31 05:27:45.903917 progress 40 % (1 MB)
32 05:27:45.907709 progress 45 % (2 MB)
33 05:27:45.911624 progress 50 % (2 MB)
34 05:27:45.916276 progress 55 % (2 MB)
35 05:27:45.920204 progress 60 % (2 MB)
36 05:27:45.924314 progress 65 % (2 MB)
37 05:27:45.928922 progress 70 % (3 MB)
38 05:27:45.932690 progress 75 % (3 MB)
39 05:27:45.936679 progress 80 % (3 MB)
40 05:27:45.940814 progress 85 % (3 MB)
41 05:27:45.945443 progress 90 % (4 MB)
42 05:27:45.949044 progress 95 % (4 MB)
43 05:27:45.952574 progress 100 % (4 MB)
44 05:27:45.953361 4 MB downloaded in 0.12 s (38.05 MB/s)
45 05:27:45.954164 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:27:45.956136 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:27:45.956765 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:27:45.957352 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:27:45.958222 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-256-gebd9c70be2b2/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 05:27:45.958585 saving as /var/lib/lava/dispatcher/tmp/965201/tftp-deploy-870n_78c/kernel/zImage
52 05:27:45.958819 total size: 11440640 (10 MB)
53 05:27:45.959068 No compression specified
54 05:27:45.995725 progress 0 % (0 MB)
55 05:27:46.003148 progress 5 % (0 MB)
56 05:27:46.010467 progress 10 % (1 MB)
57 05:27:46.018311 progress 15 % (1 MB)
58 05:27:46.025533 progress 20 % (2 MB)
59 05:27:46.033109 progress 25 % (2 MB)
60 05:27:46.040360 progress 30 % (3 MB)
61 05:27:46.048206 progress 35 % (3 MB)
62 05:27:46.055485 progress 40 % (4 MB)
63 05:27:46.063094 progress 45 % (4 MB)
64 05:27:46.070263 progress 50 % (5 MB)
65 05:27:46.077899 progress 55 % (6 MB)
66 05:27:46.085138 progress 60 % (6 MB)
67 05:27:46.092314 progress 65 % (7 MB)
68 05:27:46.099915 progress 70 % (7 MB)
69 05:27:46.106944 progress 75 % (8 MB)
70 05:27:46.114504 progress 80 % (8 MB)
71 05:27:46.121658 progress 85 % (9 MB)
72 05:27:46.129125 progress 90 % (9 MB)
73 05:27:46.136182 progress 95 % (10 MB)
74 05:27:46.143357 progress 100 % (10 MB)
75 05:27:46.143855 10 MB downloaded in 0.19 s (58.97 MB/s)
76 05:27:46.144336 end: 1.2.1 http-download (duration 00:00:00) [common]
78 05:27:46.145168 end: 1.2 download-retry (duration 00:00:00) [common]
79 05:27:46.145442 start: 1.3 download-retry (timeout 00:10:00) [common]
80 05:27:46.145707 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 05:27:46.146201 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-256-gebd9c70be2b2/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 05:27:46.146462 saving as /var/lib/lava/dispatcher/tmp/965201/tftp-deploy-870n_78c/dtb/am335x-boneblack.dtb
83 05:27:46.146670 total size: 70568 (0 MB)
84 05:27:46.146883 No compression specified
85 05:27:46.178515 progress 46 % (0 MB)
86 05:27:46.179354 progress 92 % (0 MB)
87 05:27:46.180011 progress 100 % (0 MB)
88 05:27:46.180388 0 MB downloaded in 0.03 s (2.00 MB/s)
89 05:27:46.180848 end: 1.3.1 http-download (duration 00:00:00) [common]
91 05:27:46.181664 end: 1.3 download-retry (duration 00:00:00) [common]
92 05:27:46.181963 start: 1.4 download-retry (timeout 00:10:00) [common]
93 05:27:46.182232 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 05:27:46.182685 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 05:27:46.182934 saving as /var/lib/lava/dispatcher/tmp/965201/tftp-deploy-870n_78c/nfsrootfs/full.rootfs.tar
96 05:27:46.183138 total size: 117747780 (112 MB)
97 05:27:46.183348 Using unxz to decompress xz
98 05:27:46.214178 progress 0 % (0 MB)
99 05:27:46.939025 progress 5 % (5 MB)
100 05:27:47.685645 progress 10 % (11 MB)
101 05:27:48.454756 progress 15 % (16 MB)
102 05:27:49.168630 progress 20 % (22 MB)
103 05:27:49.744808 progress 25 % (28 MB)
104 05:27:50.541772 progress 30 % (33 MB)
105 05:27:51.337059 progress 35 % (39 MB)
106 05:27:51.688066 progress 40 % (44 MB)
107 05:27:52.035265 progress 45 % (50 MB)
108 05:27:52.686244 progress 50 % (56 MB)
109 05:27:53.493893 progress 55 % (61 MB)
110 05:27:54.217563 progress 60 % (67 MB)
111 05:27:54.930632 progress 65 % (73 MB)
112 05:27:55.715719 progress 70 % (78 MB)
113 05:27:56.496069 progress 75 % (84 MB)
114 05:27:57.228741 progress 80 % (89 MB)
115 05:27:57.934956 progress 85 % (95 MB)
116 05:27:58.716890 progress 90 % (101 MB)
117 05:27:59.471517 progress 95 % (106 MB)
118 05:28:00.278207 progress 100 % (112 MB)
119 05:28:00.290531 112 MB downloaded in 14.11 s (7.96 MB/s)
120 05:28:00.291102 end: 1.4.1 http-download (duration 00:00:14) [common]
122 05:28:00.291937 end: 1.4 download-retry (duration 00:00:14) [common]
123 05:28:00.292205 start: 1.5 download-retry (timeout 00:09:46) [common]
124 05:28:00.292468 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 05:28:00.292934 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-256-gebd9c70be2b2/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 05:28:00.293175 saving as /var/lib/lava/dispatcher/tmp/965201/tftp-deploy-870n_78c/modules/modules.tar
127 05:28:00.293383 total size: 6606700 (6 MB)
128 05:28:00.293593 Using unxz to decompress xz
129 05:28:00.332752 progress 0 % (0 MB)
130 05:28:00.367836 progress 5 % (0 MB)
131 05:28:00.411461 progress 10 % (0 MB)
132 05:28:00.454374 progress 15 % (0 MB)
133 05:28:00.498278 progress 20 % (1 MB)
134 05:28:00.545082 progress 25 % (1 MB)
135 05:28:00.588319 progress 30 % (1 MB)
136 05:28:00.630760 progress 35 % (2 MB)
137 05:28:00.674142 progress 40 % (2 MB)
138 05:28:00.717250 progress 45 % (2 MB)
139 05:28:00.760579 progress 50 % (3 MB)
140 05:28:00.803259 progress 55 % (3 MB)
141 05:28:00.848585 progress 60 % (3 MB)
142 05:28:00.895282 progress 65 % (4 MB)
143 05:28:00.938403 progress 70 % (4 MB)
144 05:28:00.984390 progress 75 % (4 MB)
145 05:28:01.026861 progress 80 % (5 MB)
146 05:28:01.069569 progress 85 % (5 MB)
147 05:28:01.113032 progress 90 % (5 MB)
148 05:28:01.156747 progress 95 % (6 MB)
149 05:28:01.200839 progress 100 % (6 MB)
150 05:28:01.213576 6 MB downloaded in 0.92 s (6.85 MB/s)
151 05:28:01.214375 end: 1.5.1 http-download (duration 00:00:01) [common]
153 05:28:01.215972 end: 1.5 download-retry (duration 00:00:01) [common]
154 05:28:01.216501 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 05:28:01.217018 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 05:28:18.571318 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/965201/extract-nfsrootfs-oha3c1lx
157 05:28:18.571938 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 05:28:18.572230 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 05:28:18.572849 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51
160 05:28:18.573283 makedir: /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin
161 05:28:18.573610 makedir: /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/tests
162 05:28:18.573998 makedir: /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/results
163 05:28:18.574361 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-add-keys
164 05:28:18.574933 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-add-sources
165 05:28:18.575514 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-background-process-start
166 05:28:18.576036 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-background-process-stop
167 05:28:18.576568 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-common-functions
168 05:28:18.577074 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-echo-ipv4
169 05:28:18.577568 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-install-packages
170 05:28:18.578112 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-installed-packages
171 05:28:18.578617 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-os-build
172 05:28:18.579109 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-probe-channel
173 05:28:18.579592 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-probe-ip
174 05:28:18.580071 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-target-ip
175 05:28:18.580560 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-target-mac
176 05:28:18.581075 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-target-storage
177 05:28:18.581593 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-test-case
178 05:28:18.582151 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-test-event
179 05:28:18.582655 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-test-feedback
180 05:28:18.583144 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-test-raise
181 05:28:18.583626 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-test-reference
182 05:28:18.584111 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-test-runner
183 05:28:18.584600 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-test-set
184 05:28:18.585114 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-test-shell
185 05:28:18.585644 Updating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-add-keys (debian)
186 05:28:18.586240 Updating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-add-sources (debian)
187 05:28:18.586829 Updating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-install-packages (debian)
188 05:28:18.587375 Updating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-installed-packages (debian)
189 05:28:18.587889 Updating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/bin/lava-os-build (debian)
190 05:28:18.588330 Creating /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/environment
191 05:28:18.588707 LAVA metadata
192 05:28:18.588964 - LAVA_JOB_ID=965201
193 05:28:18.589181 - LAVA_DISPATCHER_IP=192.168.6.3
194 05:28:18.589544 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 05:28:18.590511 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 05:28:18.590832 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 05:28:18.591041 skipped lava-vland-overlay
198 05:28:18.591283 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 05:28:18.591539 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 05:28:18.591743 skipped lava-multinode-overlay
201 05:28:18.591981 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 05:28:18.592233 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 05:28:18.592524 Loading test definitions
204 05:28:18.592840 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 05:28:18.593087 Using /lava-965201 at stage 0
206 05:28:18.594340 uuid=965201_1.6.2.4.1 testdef=None
207 05:28:18.594664 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 05:28:18.594935 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 05:28:18.596552 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 05:28:18.597350 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 05:28:18.599334 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 05:28:18.600172 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 05:28:18.602030 runner path: /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/0/tests/0_timesync-off test_uuid 965201_1.6.2.4.1
216 05:28:18.602605 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 05:28:18.603431 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 05:28:18.603655 Using /lava-965201 at stage 0
220 05:28:18.604016 Fetching tests from https://github.com/kernelci/test-definitions.git
221 05:28:18.604317 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/0/tests/1_kselftest-dt'
222 05:28:21.997861 Running '/usr/bin/git checkout kernelci.org
223 05:28:22.449583 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 05:28:22.451057 uuid=965201_1.6.2.4.5 testdef=None
225 05:28:22.451396 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 05:28:22.452155 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 05:28:22.455075 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 05:28:22.455905 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 05:28:22.459716 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 05:28:22.460581 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 05:28:22.464240 runner path: /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/0/tests/1_kselftest-dt test_uuid 965201_1.6.2.4.5
235 05:28:22.464555 BOARD='beaglebone-black'
236 05:28:22.464766 BRANCH='broonie-sound'
237 05:28:22.464967 SKIPFILE='/dev/null'
238 05:28:22.465165 SKIP_INSTALL='True'
239 05:28:22.465362 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-256-gebd9c70be2b2/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 05:28:22.465563 TST_CASENAME=''
241 05:28:22.465758 TST_CMDFILES='dt'
242 05:28:22.466351 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 05:28:22.467151 Creating lava-test-runner.conf files
245 05:28:22.467357 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/965201/lava-overlay-1cgg8t51/lava-965201/0 for stage 0
246 05:28:22.467712 - 0_timesync-off
247 05:28:22.467952 - 1_kselftest-dt
248 05:28:22.468283 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 05:28:22.468564 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 05:28:45.807235 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 05:28:45.807698 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 05:28:45.808008 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 05:28:45.808329 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 05:28:45.808636 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 05:28:46.175481 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 05:28:46.175935 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 05:28:46.176239 extracting modules file /var/lib/lava/dispatcher/tmp/965201/tftp-deploy-870n_78c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/965201/extract-nfsrootfs-oha3c1lx
258 05:28:47.094529 extracting modules file /var/lib/lava/dispatcher/tmp/965201/tftp-deploy-870n_78c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/965201/extract-overlay-ramdisk-tcrg_ptk/ramdisk
259 05:28:48.018721 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 05:28:48.019214 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 05:28:48.019517 [common] Applying overlay to NFS
262 05:28:48.019751 [common] Applying overlay /var/lib/lava/dispatcher/tmp/965201/compress-overlay-vz6rn97t/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/965201/extract-nfsrootfs-oha3c1lx
263 05:28:50.752449 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 05:28:50.752957 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 05:28:50.753267 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 05:28:50.753602 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 05:28:50.753909 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 05:28:50.754203 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 05:28:50.754475 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 05:28:50.754757 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 05:28:50.755003 Building ramdisk /var/lib/lava/dispatcher/tmp/965201/extract-overlay-ramdisk-tcrg_ptk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/965201/extract-overlay-ramdisk-tcrg_ptk/ramdisk
272 05:28:51.772765 >> 74905 blocks
273 05:28:56.545921 Adding RAMdisk u-boot header.
274 05:28:56.546412 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/965201/extract-overlay-ramdisk-tcrg_ptk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/965201/extract-overlay-ramdisk-tcrg_ptk/ramdisk.cpio.gz.uboot
275 05:28:56.702381 output: Image Name:
276 05:28:56.702794 output: Created: Sat Nov 9 05:28:56 2024
277 05:28:56.703010 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 05:28:56.703219 output: Data Size: 14790438 Bytes = 14443.79 KiB = 14.11 MiB
279 05:28:56.703427 output: Load Address: 00000000
280 05:28:56.703630 output: Entry Point: 00000000
281 05:28:56.703833 output:
282 05:28:56.704415 rename /var/lib/lava/dispatcher/tmp/965201/extract-overlay-ramdisk-tcrg_ptk/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/965201/tftp-deploy-870n_78c/ramdisk/ramdisk.cpio.gz.uboot
283 05:28:56.704827 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 05:28:56.705118 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 05:28:56.705395 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 05:28:56.705638 No LXC device requested
287 05:28:56.706087 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 05:28:56.706677 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 05:28:56.707254 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 05:28:56.707720 Checking files for TFTP limit of 4294967296 bytes.
291 05:28:56.710685 end: 1 tftp-deploy (duration 00:01:11) [common]
292 05:28:56.711318 start: 2 uboot-action (timeout 00:05:00) [common]
293 05:28:56.711902 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 05:28:56.712457 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 05:28:56.713016 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 05:28:56.713868 substitutions:
297 05:28:56.714347 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 05:28:56.714802 - {DTB_ADDR}: 0x88000000
299 05:28:56.715250 - {DTB}: 965201/tftp-deploy-870n_78c/dtb/am335x-boneblack.dtb
300 05:28:56.715693 - {INITRD}: 965201/tftp-deploy-870n_78c/ramdisk/ramdisk.cpio.gz.uboot
301 05:28:56.716133 - {KERNEL_ADDR}: 0x82000000
302 05:28:56.716573 - {KERNEL}: 965201/tftp-deploy-870n_78c/kernel/zImage
303 05:28:56.717015 - {LAVA_MAC}: None
304 05:28:56.717495 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/965201/extract-nfsrootfs-oha3c1lx
305 05:28:56.717966 - {NFS_SERVER_IP}: 192.168.6.3
306 05:28:56.718413 - {PRESEED_CONFIG}: None
307 05:28:56.718853 - {PRESEED_LOCAL}: None
308 05:28:56.719288 - {RAMDISK_ADDR}: 0x83000000
309 05:28:56.719723 - {RAMDISK}: 965201/tftp-deploy-870n_78c/ramdisk/ramdisk.cpio.gz.uboot
310 05:28:56.720163 - {ROOT_PART}: None
311 05:28:56.720597 - {ROOT}: None
312 05:28:56.721030 - {SERVER_IP}: 192.168.6.3
313 05:28:56.721460 - {TEE_ADDR}: 0x83000000
314 05:28:56.721910 - {TEE}: None
315 05:28:56.722345 Parsed boot commands:
316 05:28:56.722767 - setenv autoload no
317 05:28:56.723200 - setenv initrd_high 0xffffffff
318 05:28:56.723630 - setenv fdt_high 0xffffffff
319 05:28:56.724056 - dhcp
320 05:28:56.724484 - setenv serverip 192.168.6.3
321 05:28:56.724911 - tftp 0x82000000 965201/tftp-deploy-870n_78c/kernel/zImage
322 05:28:56.725345 - tftp 0x83000000 965201/tftp-deploy-870n_78c/ramdisk/ramdisk.cpio.gz.uboot
323 05:28:56.725776 - setenv initrd_size ${filesize}
324 05:28:56.726228 - tftp 0x88000000 965201/tftp-deploy-870n_78c/dtb/am335x-boneblack.dtb
325 05:28:56.726662 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/965201/extract-nfsrootfs-oha3c1lx,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 05:28:56.727106 - bootz 0x82000000 0x83000000 0x88000000
327 05:28:56.727646 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 05:28:56.729286 start: 2.3 connect-device (timeout 00:05:00) [common]
330 05:28:56.729751 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 05:28:56.745592 Setting prompt string to ['lava-test: # ']
332 05:28:56.747161 end: 2.3 connect-device (duration 00:00:00) [common]
333 05:28:56.747810 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 05:28:56.748399 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 05:28:56.748974 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 05:28:56.750327 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 05:28:56.790031 >> OK - accepted request
338 05:28:56.791895 Returned 0 in 0 seconds
339 05:28:56.893029 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 05:28:56.894783 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 05:28:56.895399 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 05:28:56.895963 Setting prompt string to ['Hit any key to stop autoboot']
344 05:28:56.896455 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 05:28:56.898131 Trying 192.168.56.22...
346 05:28:56.898658 Connected to conserv3.
347 05:28:56.899132 Escape character is '^]'.
348 05:28:56.899589
349 05:28:56.900049 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 05:28:56.900502
351 05:29:04.891547
352 05:29:04.898364 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 05:29:04.898915 Trying to boot from MMC1
354 05:29:08.959610
355 05:29:08.966453 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 05:29:08.966827 Trying to boot from MMC1
357 05:29:11.647796
358 05:29:11.654807 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 05:29:11.655405 Trying to boot from MMC1
360 05:29:12.239036
361 05:29:12.239722
362 05:29:12.244508 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 05:29:12.245089
364 05:29:12.245612 CPU : AM335X-GP rev 2.0
365 05:29:12.249699 Model: TI AM335x BeagleBone Black
366 05:29:12.250319 DRAM: 512 MiB
367 05:29:12.329588 Core: 160 devices, 18 uclasses, devicetree: separate
368 05:29:12.343571 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 05:29:12.744117 NAND: 0 MiB
370 05:29:12.754394 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 05:29:12.876949 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 05:29:12.898330 <ethaddr> not set. Validating first E-fuse MAC
373 05:29:12.928741 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 05:29:12.987583 Hit any key to stop autoboot: 2
376 05:29:12.988770 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
377 05:29:12.990003 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
378 05:29:12.991039 Setting prompt string to ['=>']
379 05:29:12.991978 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
380 05:29:12.997232 0
381 05:29:12.998864 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 05:29:12.999928 Sending with 10 millisecond of delay
384 05:29:14.137274 => setenv autoload no
385 05:29:14.148451 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
386 05:29:14.154917 setenv autoload no
387 05:29:14.155841 Sending with 10 millisecond of delay
389 05:29:15.954922 => setenv initrd_high 0xffffffff
390 05:29:15.965776 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
391 05:29:15.966775 setenv initrd_high 0xffffffff
392 05:29:15.967589 Sending with 10 millisecond of delay
394 05:29:17.585926 => setenv fdt_high 0xffffffff
395 05:29:17.596723 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
396 05:29:17.597570 setenv fdt_high 0xffffffff
397 05:29:17.598309 Sending with 10 millisecond of delay
399 05:29:17.890433 => dhcp
400 05:29:17.901207 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
401 05:29:17.902171 dhcp
402 05:29:17.902644 link up on port 0, speed 100, full duplex
403 05:29:17.903153 BOOTP broadcast 1
404 05:29:18.155535 BOOTP broadcast 2
405 05:29:18.237145 DHCP client bound to address 192.168.6.8 (330 ms)
406 05:29:18.237786 Sending with 10 millisecond of delay
408 05:29:19.914388 => setenv serverip 192.168.6.3
409 05:29:19.925951 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
410 05:29:19.926986 setenv serverip 192.168.6.3
411 05:29:19.927770 Sending with 10 millisecond of delay
413 05:29:23.413591 => tftp 0x82000000 965201/tftp-deploy-870n_78c/kernel/zImage
414 05:29:23.424439 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
415 05:29:23.425286 tftp 0x82000000 965201/tftp-deploy-870n_78c/kernel/zImage
416 05:29:23.425738 link up on port 0, speed 100, full duplex
417 05:29:23.429530 Using ethernet@4a100000 device
418 05:29:23.435924 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
419 05:29:23.436389 Filename '965201/tftp-deploy-870n_78c/kernel/zImage'.
420 05:29:23.442113 Load address: 0x82000000
421 05:29:25.390738 Loading: *################################################## 10.9 MiB
422 05:29:25.391355 5.6 MiB/s
423 05:29:25.391759 done
424 05:29:25.394751 Bytes transferred = 11440640 (ae9200 hex)
425 05:29:25.395533 Sending with 10 millisecond of delay
427 05:29:29.843046 => tftp 0x83000000 965201/tftp-deploy-870n_78c/ramdisk/ramdisk.cpio.gz.uboot
428 05:29:29.853939 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
429 05:29:29.854879 tftp 0x83000000 965201/tftp-deploy-870n_78c/ramdisk/ramdisk.cpio.gz.uboot
430 05:29:29.855377 link up on port 0, speed 100, full duplex
431 05:29:29.858680 Using ethernet@4a100000 device
432 05:29:29.864178 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
433 05:29:29.872799 Filename '965201/tftp-deploy-870n_78c/ramdisk/ramdisk.cpio.gz.uboot'.
434 05:29:29.873359 Load address: 0x83000000
435 05:29:32.832655 Loading: *################################################## 14.1 MiB
436 05:29:32.833113 4.8 MiB/s
437 05:29:32.833334 done
438 05:29:32.846814 Bytes transferred = 14790502 (e1af66 hex)
439 05:29:32.847533 Sending with 10 millisecond of delay
441 05:29:34.706202 => setenv initrd_size ${filesize}
442 05:29:34.717066 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
443 05:29:34.718071 setenv initrd_size ${filesize}
444 05:29:34.719014 Sending with 10 millisecond of delay
446 05:29:38.874820 => tftp 0x88000000 965201/tftp-deploy-870n_78c/dtb/am335x-boneblack.dtb
447 05:29:38.885423 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
448 05:29:38.886103 tftp 0x88000000 965201/tftp-deploy-870n_78c/dtb/am335x-boneblack.dtb
449 05:29:38.886359 link up on port 0, speed 100, full duplex
450 05:29:38.890217 Using ethernet@4a100000 device
451 05:29:38.895804 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
452 05:29:38.903979 Filename '965201/tftp-deploy-870n_78c/dtb/am335x-boneblack.dtb'.
453 05:29:38.904345 Load address: 0x88000000
454 05:29:38.918850 Loading: *################################################## 68.9 KiB
455 05:29:38.928156 4 MiB/s
456 05:29:38.928530 done
457 05:29:38.928751 Bytes transferred = 70568 (113a8 hex)
458 05:29:38.929206 Sending with 10 millisecond of delay
460 05:29:52.119342 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/965201/extract-nfsrootfs-oha3c1lx,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
461 05:29:52.129932 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
462 05:29:52.130510 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/965201/extract-nfsrootfs-oha3c1lx,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
463 05:29:52.130984 Sending with 10 millisecond of delay
465 05:29:54.470158 => bootz 0x82000000 0x83000000 0x88000000
466 05:29:54.480795 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
467 05:29:54.481121 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
468 05:29:54.481693 bootz 0x82000000 0x83000000 0x88000000
469 05:29:54.481971 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
470 05:29:54.482879 ## Loading init Ramdisk from Legacy Image at 83000000 ...
471 05:29:54.488507 Image Name:
472 05:29:54.488774 Created: 2024-11-09 5:28:56 UTC
473 05:29:54.497344 Image Type: ARM Linux RAMDisk Image (uncompressed)
474 05:29:54.497647 Data Size: 14790438 Bytes = 14.1 MiB
475 05:29:54.505770 Load Address: 00000000
476 05:29:54.506100 Entry Point: 00000000
477 05:29:54.674197 Verifying Checksum ... OK
478 05:29:54.674615 ## Flattened Device Tree blob at 88000000
479 05:29:54.680727 Booting using the fdt blob at 0x88000000
480 05:29:54.681077 Working FDT set to 88000000
481 05:29:54.686324 Using Device Tree in place at 88000000, end 880143a7
482 05:29:54.690772 Working FDT set to 88000000
483 05:29:54.704117
484 05:29:54.704382 Starting kernel ...
485 05:29:54.704589
486 05:29:54.705156 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
487 05:29:54.705478 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
488 05:29:54.705721 Setting prompt string to ['Linux version [0-9]']
489 05:29:54.705997 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
490 05:29:54.706234 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
491 05:29:55.548275 [ 0.000000] Booting Linux on physical CPU 0x0
492 05:29:55.554330 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
493 05:29:55.554966 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
494 05:29:55.555276 Setting prompt string to []
495 05:29:55.555555 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
496 05:29:55.555815 Using line separator: #'\n'#
497 05:29:55.556030 No login prompt set.
498 05:29:55.556253 Parsing kernel messages
499 05:29:55.556459 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
500 05:29:55.556905 [login-action] Waiting for messages, (timeout 00:04:01)
501 05:29:55.557151 Waiting using forced prompt support (timeout 00:02:01)
502 05:29:55.568334 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j370548-arm-gcc-12-multi-v7-defconfig-9djbw) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Sat Nov 9 04:32:22 UTC 2024
503 05:29:55.579874 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
504 05:29:55.585759 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
505 05:29:55.591137 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
506 05:29:55.596832 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
507 05:29:55.602809 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
508 05:29:55.609385 [ 0.000000] Memory policy: Data cache writeback
509 05:29:55.609798 [ 0.000000] efi: UEFI not found.
510 05:29:55.618001 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
511 05:29:55.623689 [ 0.000000] Zone ranges:
512 05:29:55.629576 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
513 05:29:55.629974 [ 0.000000] Normal empty
514 05:29:55.635229 [ 0.000000] HighMem empty
515 05:29:55.641131 [ 0.000000] Movable zone start for each node
516 05:29:55.641716 [ 0.000000] Early memory node ranges
517 05:29:55.652324 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
518 05:29:55.657131 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
519 05:29:55.682497 [ 0.000000] CPU: All CPU(s) started in SVC mode.
520 05:29:55.688008 [ 0.000000] AM335X ES2.0 (sgx neon)
521 05:29:55.699730 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
522 05:29:55.720156 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/965201/extract-nfsrootfs-oha3c1lx,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
523 05:29:55.726059 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
524 05:29:55.734047 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
525 05:29:55.745584 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
526 05:29:55.748502 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
527 05:29:55.781019 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
528 05:29:55.785580 <6>[ 0.000000] trace event string verifier disabled
529 05:29:55.785997 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
530 05:29:55.793789 <6>[ 0.000000] rcu: RCU event tracing is enabled.
531 05:29:55.799373 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
532 05:29:55.810799 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
533 05:29:55.815711 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
534 05:29:55.830668 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
535 05:29:55.847802 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
536 05:29:55.854371 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
537 05:29:55.946162 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
538 05:29:55.957598 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
539 05:29:55.964334 <6>[ 0.008335] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
540 05:29:55.977396 <6>[ 0.019143] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
541 05:29:55.984712 <6>[ 0.033919] Console: colour dummy device 80x30
542 05:29:55.990924 Matched prompt #6: WARNING:
543 05:29:55.991426 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
544 05:29:55.996241 <3>[ 0.038819] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
545 05:29:56.002028 <3>[ 0.045892] This ensures that you still see kernel messages. Please
546 05:29:56.005203 <3>[ 0.052618] update your kernel commandline.
547 05:29:56.046027 <6>[ 0.057232] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
548 05:29:56.051721 <6>[ 0.096147] CPU: Testing write buffer coherency: ok
549 05:29:56.057633 <6>[ 0.101512] CPU0: Spectre v2: using BPIALL workaround
550 05:29:56.058130 <6>[ 0.106977] pid_max: default: 32768 minimum: 301
551 05:29:56.069064 <6>[ 0.112173] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
552 05:29:56.076024 <6>[ 0.119995] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
553 05:29:56.083734 <6>[ 0.129367] CPU0: thread -1, cpu 0, socket -1, mpidr 0
554 05:29:56.091669 <6>[ 0.136373] Setting up static identity map for 0x80300000 - 0x803000ac
555 05:29:56.097346 <6>[ 0.146008] rcu: Hierarchical SRCU implementation.
556 05:29:56.104993 <6>[ 0.151295] rcu: Max phase no-delay instances is 1000.
557 05:29:56.113515 <6>[ 0.162404] EFI services will not be available.
558 05:29:56.119313 <6>[ 0.167684] smp: Bringing up secondary CPUs ...
559 05:29:56.125057 <6>[ 0.172728] smp: Brought up 1 node, 1 CPU
560 05:29:56.133249 <6>[ 0.177128] SMP: Total of 1 processors activated (996.14 BogoMIPS).
561 05:29:56.139177 <6>[ 0.183895] CPU: All CPU(s) started in SVC mode.
562 05:29:56.151365 <6>[ 0.189075] Memory: 406000K/522240K available (16384K kernel code, 2542K rwdata, 6784K rodata, 2048K init, 431K bss, 49048K reserved, 65536K cma-reserved, 0K highmem)
563 05:29:56.157088 <6>[ 0.205359] devtmpfs: initialized
564 05:29:56.179280 <6>[ 0.222400] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
565 05:29:56.187624 <6>[ 0.230987] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
566 05:29:56.196658 <6>[ 0.241446] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
567 05:29:56.207512 <6>[ 0.253773] pinctrl core: initialized pinctrl subsystem
568 05:29:56.216791 <6>[ 0.264404] DMI not present or invalid.
569 05:29:56.225039 <6>[ 0.270258] NET: Registered PF_NETLINK/PF_ROUTE protocol family
570 05:29:56.233705 <6>[ 0.279135] DMA: preallocated 256 KiB pool for atomic coherent allocations
571 05:29:56.249753 <6>[ 0.290673] thermal_sys: Registered thermal governor 'step_wise'
572 05:29:56.250241 <6>[ 0.290842] cpuidle: using governor menu
573 05:29:56.277225 <6>[ 0.326430] No ATAGs?
574 05:29:56.283329 <6>[ 0.329074] hw-breakpoint: debug architecture 0x4 unsupported.
575 05:29:56.292732 <6>[ 0.341100] Serial: AMBA PL011 UART driver
576 05:29:56.326123 <6>[ 0.375258] iommu: Default domain type: Translated
577 05:29:56.335185 <6>[ 0.380609] iommu: DMA domain TLB invalidation policy: strict mode
578 05:29:56.362084 <5>[ 0.410638] SCSI subsystem initialized
579 05:29:56.367973 <6>[ 0.415515] usbcore: registered new interface driver usbfs
580 05:29:56.373693 <6>[ 0.421577] usbcore: registered new interface driver hub
581 05:29:56.380506 <6>[ 0.427360] usbcore: registered new device driver usb
582 05:29:56.386235 <6>[ 0.433874] pps_core: LinuxPPS API ver. 1 registered
583 05:29:56.397750 <6>[ 0.439262] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
584 05:29:56.404955 <6>[ 0.448986] PTP clock support registered
585 05:29:56.405407 <6>[ 0.453445] EDAC MC: Ver: 3.0.0
586 05:29:56.453976 <6>[ 0.500369] scmi_core: SCMI protocol bus registered
587 05:29:56.468994 <6>[ 0.517680] vgaarb: loaded
588 05:29:56.481488 <6>[ 0.530695] clocksource: Switched to clocksource dmtimer
589 05:29:56.518248 <6>[ 0.566883] NET: Registered PF_INET protocol family
590 05:29:56.530663 <6>[ 0.572579] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
591 05:29:56.536376 <6>[ 0.581387] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
592 05:29:56.547907 <6>[ 0.590318] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
593 05:29:56.553725 <6>[ 0.598578] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
594 05:29:56.565188 <6>[ 0.606865] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
595 05:29:56.571122 <6>[ 0.614589] TCP: Hash tables configured (established 4096 bind 4096)
596 05:29:56.576832 <6>[ 0.621520] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
597 05:29:56.582885 <6>[ 0.628534] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
598 05:29:56.590412 <6>[ 0.636147] NET: Registered PF_UNIX/PF_LOCAL protocol family
599 05:29:56.681488 <6>[ 0.724880] RPC: Registered named UNIX socket transport module.
600 05:29:56.682241 <6>[ 0.731271] RPC: Registered udp transport module.
601 05:29:56.687331 <6>[ 0.736426] RPC: Registered tcp transport module.
602 05:29:56.693515 <6>[ 0.741549] RPC: Registered tcp-with-tls transport module.
603 05:29:56.706332 <6>[ 0.747460] RPC: Registered tcp NFSv4.1 backchannel transport module.
604 05:29:56.707023 <6>[ 0.754381] PCI: CLS 0 bytes, default 64
605 05:29:56.713161 <5>[ 0.760162] Initialise system trusted keyrings
606 05:29:56.732812 <6>[ 0.778760] Trying to unpack rootfs image as initramfs...
607 05:29:56.818231 <6>[ 0.861063] workingset: timestamp_bits=30 max_order=17 bucket_order=0
608 05:29:56.823021 <6>[ 0.868613] squashfs: version 4.0 (2009/01/31) Phillip Lougher
609 05:29:56.843590 <5>[ 0.892600] NFS: Registering the id_resolver key type
610 05:29:56.849375 <5>[ 0.898201] Key type id_resolver registered
611 05:29:56.855125 <5>[ 0.902884] Key type id_legacy registered
612 05:29:56.860914 <6>[ 0.907319] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
613 05:29:56.870445 <6>[ 0.914514] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
614 05:29:56.939540 <5>[ 0.988463] Key type asymmetric registered
615 05:29:56.945281 <5>[ 0.993044] Asymmetric key parser 'x509' registered
616 05:29:56.956709 <6>[ 0.998469] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
617 05:29:56.957298 <6>[ 1.006388] io scheduler mq-deadline registered
618 05:29:56.962597 <6>[ 1.011320] io scheduler kyber registered
619 05:29:56.968167 <6>[ 1.015804] io scheduler bfq registered
620 05:29:57.087416 <6>[ 1.132832] ledtrig-cpu: registered to indicate activity on CPUs
621 05:29:57.372593 <6>[ 1.417833] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
622 05:29:57.418165 <6>[ 1.466861] msm_serial: driver initialized
623 05:29:57.423961 <6>[ 1.471903] SuperH (H)SCI(F) driver initialized
624 05:29:57.429924 <6>[ 1.477021] STMicroelectronics ASC driver initialized
625 05:29:57.435187 <6>[ 1.482684] STM32 USART driver initialized
626 05:29:57.543632 <6>[ 1.592251] brd: module loaded
627 05:29:57.583844 <6>[ 1.632226] loop: module loaded
628 05:29:57.621099 <6>[ 1.669289] CAN device driver interface
629 05:29:57.627719 <6>[ 1.674581] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
630 05:29:57.633398 <6>[ 1.681595] e1000e: Intel(R) PRO/1000 Network Driver
631 05:29:57.640297 <6>[ 1.686981] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
632 05:29:57.645941 <6>[ 1.693415] igb: Intel(R) Gigabit Ethernet Network Driver
633 05:29:57.653187 <6>[ 1.699240] igb: Copyright (c) 2007-2014 Intel Corporation.
634 05:29:57.665032 <6>[ 1.708416] pegasus: Pegasus/Pegasus II USB Ethernet driver
635 05:29:57.670914 <6>[ 1.714569] usbcore: registered new interface driver pegasus
636 05:29:57.676594 <6>[ 1.720693] usbcore: registered new interface driver asix
637 05:29:57.682326 <6>[ 1.726588] usbcore: registered new interface driver ax88179_178a
638 05:29:57.688067 <6>[ 1.733178] usbcore: registered new interface driver cdc_ether
639 05:29:57.693783 <6>[ 1.739473] usbcore: registered new interface driver smsc75xx
640 05:29:57.699705 <6>[ 1.745705] usbcore: registered new interface driver smsc95xx
641 05:29:57.705490 <6>[ 1.751936] usbcore: registered new interface driver net1080
642 05:29:57.711224 <6>[ 1.758066] usbcore: registered new interface driver cdc_subset
643 05:29:57.716953 <6>[ 1.764476] usbcore: registered new interface driver zaurus
644 05:29:57.724147 <6>[ 1.770522] usbcore: registered new interface driver cdc_ncm
645 05:29:57.734412 <6>[ 1.779979] usbcore: registered new interface driver usb-storage
646 05:29:58.026372 <6>[ 2.073772] i2c_dev: i2c /dev entries driver
647 05:29:58.072041 <5>[ 2.117741] cpuidle: enable-method property 'ti,am3352' found operations
648 05:29:58.085545 <6>[ 2.127350] sdhci: Secure Digital Host Controller Interface driver
649 05:29:58.085929 <6>[ 2.134129] sdhci: Copyright(c) Pierre Ossman
650 05:29:58.092861 <6>[ 2.140561] Synopsys Designware Multimedia Card Interface Driver
651 05:29:58.102466 <6>[ 2.148503] sdhci-pltfm: SDHCI platform and OF driver helper
652 05:29:58.231061 <6>[ 2.272892] usbcore: registered new interface driver usbhid
653 05:29:58.231457 <6>[ 2.278933] usbhid: USB HID core driver
654 05:29:58.275980 <6>[ 2.322471] NET: Registered PF_INET6 protocol family
655 05:29:58.304044 <6>[ 2.353070] Segment Routing with IPv6
656 05:29:58.309804 <6>[ 2.357222] In-situ OAM (IOAM) with IPv6
657 05:29:58.316414 <6>[ 2.361760] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
658 05:29:58.322215 <6>[ 2.368996] NET: Registered PF_PACKET protocol family
659 05:29:58.328167 <6>[ 2.374562] can: controller area network core
660 05:29:58.333908 <6>[ 2.379388] NET: Registered PF_CAN protocol family
661 05:29:58.334477 <6>[ 2.384616] can: raw protocol
662 05:29:58.339631 <6>[ 2.387942] can: broadcast manager protocol
663 05:29:58.346146 <6>[ 2.392538] can: netlink gateway - max_hops=1
664 05:29:58.352315 <5>[ 2.398024] Key type dns_resolver registered
665 05:29:58.358595 <6>[ 2.403109] ThumbEE CPU extension supported.
666 05:29:58.359181 <5>[ 2.407801] Registering SWP/SWPB emulation handler
667 05:29:58.368326 <3>[ 2.413492] omap_voltage_late_init: Voltage driver support not added
668 05:29:58.565371 <5>[ 2.612715] Loading compiled-in X.509 certificates
669 05:29:58.692440 <6>[ 2.728473] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
670 05:29:58.699623 <6>[ 2.745141] pinctrl-single 44e10800.pinmux: 142 pins, size 568
671 05:29:58.725777 <3>[ 2.768851] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
672 05:29:58.937677 <3>[ 2.980779] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
673 05:29:59.125568 <6>[ 3.172936] OMAP GPIO hardware version 0.1
674 05:29:59.146217 <6>[ 3.191748] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
675 05:29:59.247782 <4>[ 3.293342] at24 2-0054: supply vcc not found, using dummy regulator
676 05:29:59.282651 <4>[ 3.327925] at24 2-0055: supply vcc not found, using dummy regulator
677 05:29:59.320830 <4>[ 3.366063] at24 2-0056: supply vcc not found, using dummy regulator
678 05:29:59.360253 <4>[ 3.406266] at24 2-0057: supply vcc not found, using dummy regulator
679 05:29:59.400486 <6>[ 3.446306] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
680 05:29:59.472216 <3>[ 3.514071] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
681 05:29:59.496770 <6>[ 3.535131] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
682 05:29:59.519001 <4>[ 3.561720] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
683 05:29:59.526674 <4>[ 3.570616] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
684 05:29:59.646438 <6>[ 3.691885] omap_rng 48310000.rng: Random Number Generator ver. 20
685 05:29:59.670080 <5>[ 3.718253] random: crng init done
686 05:29:59.732532 <6>[ 3.781401] Freeing initrd memory: 14444K
687 05:29:59.742232 <6>[ 3.786133] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
688 05:29:59.791053 <6>[ 3.833987] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
689 05:29:59.796895 <6>[ 3.844330] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
690 05:29:59.805048 <6>[ 3.851710] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
691 05:29:59.816571 <6>[ 3.859163] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
692 05:29:59.825143 <6>[ 3.867297] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
693 05:29:59.838197 <6>[ 3.878938] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
694 05:29:59.846570 <5>[ 3.887949] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
695 05:29:59.874439 <3>[ 3.917808] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
696 05:29:59.880163 <6>[ 3.926403] edma 49000000.dma: TI EDMA DMA engine driver
697 05:29:59.951108 <3>[ 3.994156] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
698 05:29:59.965440 <6>[ 4.008514] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
699 05:29:59.979020 <3>[ 4.025656] l3-aon-clkctrl:0000:0: failed to disable
700 05:30:00.029221 <6>[ 4.072647] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
701 05:30:00.034912 <6>[ 4.082119] printk: legacy console [ttyS0] enabled
702 05:30:00.040659 <6>[ 4.082119] printk: legacy console [ttyS0] enabled
703 05:30:00.046305 <6>[ 4.092450] printk: legacy bootconsole [omap8250] disabled
704 05:30:00.052155 <6>[ 4.092450] printk: legacy bootconsole [omap8250] disabled
705 05:30:00.090093 <4>[ 4.132339] tps65217-pmic: Failed to locate of_node [id: -1]
706 05:30:00.093553 <4>[ 4.139725] tps65217-bl: Failed to locate of_node [id: -1]
707 05:30:00.110174 <6>[ 4.159328] tps65217 0-0024: TPS65217 ID 0xe version 1.2
708 05:30:00.128365 <6>[ 4.166275] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
709 05:30:00.140052 <6>[ 4.179954] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
710 05:30:00.145741 <6>[ 4.191833] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
711 05:30:00.167868 <6>[ 4.211681] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
712 05:30:00.173724 <6>[ 4.220740] sdhci-omap 48060000.mmc: Got CD GPIO
713 05:30:00.181764 <4>[ 4.225938] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
714 05:30:00.196516 <4>[ 4.239516] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
715 05:30:00.202771 <4>[ 4.248234] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
716 05:30:00.212656 <4>[ 4.256811] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
717 05:30:00.336019 <6>[ 4.380923] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
718 05:30:00.372528 <6>[ 4.417216] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
719 05:30:00.384945 <6>[ 4.428073] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
720 05:30:00.390710 <6>[ 4.437011] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
721 05:30:00.463632 <6>[ 4.509948] mmc1: new high speed MMC card at address 0001
722 05:30:00.476336 <6>[ 4.519649] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
723 05:30:00.483753 <6>[ 4.531110] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
724 05:30:00.505714 <6>[ 4.552176] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
725 05:30:00.513410 <6>[ 4.560352] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
726 05:30:00.523006 <6>[ 4.568522] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
727 05:30:00.560961 <6>[ 4.601264] mmc0: new high speed SDHC card at address aaaa
728 05:30:00.561397 <6>[ 4.608383] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
729 05:30:00.591850 <6>[ 4.639168] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
730 05:30:02.639051 <6>[ 6.682569] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
731 05:30:02.752630 <5>[ 6.721612] Sending DHCP requests ., OK
732 05:30:02.763973 <6>[ 6.806076] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
733 05:30:02.764641 <6>[ 6.814153] IP-Config: Complete:
734 05:30:02.778088 <6>[ 6.817693] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
735 05:30:02.783888 <6>[ 6.828134] host=192.168.6.8, domain=, nis-domain=(none)
736 05:30:02.789676 <6>[ 6.834261] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
737 05:30:02.796786 <6>[ 6.834294] nameserver0=10.255.253.1
738 05:30:02.797082 <6>[ 6.846923] clk: Disabling unused clocks
739 05:30:02.805026 <6>[ 6.851672] PM: genpd: Disabling unused power domains
740 05:30:02.824339 <6>[ 6.870833] Freeing unused kernel image (initmem) memory: 2048K
741 05:30:02.832687 <6>[ 6.880677] Run /init as init process
742 05:30:02.857148 Loading, please wait...
743 05:30:02.932760 Starting systemd-udevd version 252.22-1~deb12u1
744 05:30:05.890211 <4>[ 9.933253] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
745 05:30:06.111647 <4>[ 10.154716] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
746 05:30:06.295006 <6>[ 10.344473] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
747 05:30:06.305762 <6>[ 10.350145] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
748 05:30:06.546366 <6>[ 10.594894] tda998x 0-0070: found TDA19988
749 05:30:06.581569 <6>[ 10.630533] hub 1-0:1.0: USB hub found
750 05:30:06.615052 <6>[ 10.662167] hub 1-0:1.0: 1 port detected
751 05:30:09.903700 Begin: Loading essential drivers ... done.
752 05:30:09.904143 Begin: Running /scripts/init-premount ... done.
753 05:30:09.904382 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
754 05:30:09.904606 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
755 05:30:09.904824 Device /sys/class/net/eth0 found
756 05:30:09.905036 done.
757 05:30:09.905247 Begin: Waiting up to 180 secs for any network device to become available ... done.
758 05:30:09.906150 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
759 05:30:10.004889 IP-Config: eth0 guessed broadcast address 192.168.6.255
760 05:30:10.010457 IP-Config: eth0 complete (dhcp from 192.168.6.1):
761 05:30:10.015977 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
762 05:30:10.027266 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
763 05:30:10.027630 rootserver: 192.168.6.1 rootpath:
764 05:30:10.030673 filename :
765 05:30:10.135717 done.
766 05:30:10.150024 Begin: Running /scripts/nfs-bottom ... done.
767 05:30:10.215672 Begin: Running /scripts/init-bottom ... done.
768 05:30:11.658906 <30>[ 15.704321] systemd[1]: System time before build time, advancing clock.
769 05:30:11.843119 <30>[ 15.862180] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
770 05:30:11.851001 <30>[ 15.898890] systemd[1]: Detected architecture arm.
771 05:30:11.865800
772 05:30:11.866368 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
773 05:30:11.866836
774 05:30:11.896080 <30>[ 15.942025] systemd[1]: Hostname set to <debian-bookworm-armhf>.
775 05:30:14.074237 <30>[ 18.119018] systemd[1]: Queued start job for default target graphical.target.
776 05:30:14.091754 <30>[ 18.134462] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
777 05:30:14.099370 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
778 05:30:14.121519 <30>[ 18.164558] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
779 05:30:14.129949 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
780 05:30:14.151966 <30>[ 18.194980] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
781 05:30:14.160368 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
782 05:30:14.180353 <30>[ 18.223516] systemd[1]: Created slice user.slice - User and Session Slice.
783 05:30:14.187067 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
784 05:30:14.215616 <30>[ 18.253075] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
785 05:30:14.221660 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
786 05:30:14.239423 <30>[ 18.282686] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
787 05:30:14.247379 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
788 05:30:14.280188 <30>[ 18.312556] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
789 05:30:14.286662 <30>[ 18.333056] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
790 05:30:14.295243 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
791 05:30:14.318456 <30>[ 18.362049] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
792 05:30:14.326723 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
793 05:30:14.349131 <30>[ 18.392481] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
794 05:30:14.357570 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
795 05:30:14.379094 <30>[ 18.422523] systemd[1]: Reached target paths.target - Path Units.
796 05:30:14.384173 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
797 05:30:14.411658 <30>[ 18.453246] systemd[1]: Reached target remote-fs.target - Remote File Systems.
798 05:30:14.418044 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
799 05:30:14.438415 <30>[ 18.482035] systemd[1]: Reached target slices.target - Slice Units.
800 05:30:14.443833 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
801 05:30:14.468701 <30>[ 18.512277] systemd[1]: Reached target swap.target - Swaps.
802 05:30:14.472782 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
803 05:30:14.499113 <30>[ 18.542384] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
804 05:30:14.507073 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
805 05:30:14.529920 <30>[ 18.573103] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
806 05:30:14.538235 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
807 05:30:14.618198 <30>[ 18.656899] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
808 05:30:14.631187 <30>[ 18.674472] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
809 05:30:14.639636 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
810 05:30:14.661851 <30>[ 18.704212] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
811 05:30:14.669237 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
812 05:30:14.691316 <30>[ 18.734587] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
813 05:30:14.699502 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
814 05:30:14.724415 <30>[ 18.766546] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
815 05:30:14.730019 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
816 05:30:14.761303 <30>[ 18.803307] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
817 05:30:14.768817 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
818 05:30:14.795947 <30>[ 18.833303] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
819 05:30:14.814573 <30>[ 18.851832] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
820 05:30:14.861871 <30>[ 18.906842] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
821 05:30:14.892886 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
822 05:30:14.950892 <30>[ 18.994804] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
823 05:30:14.981189 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
824 05:30:15.049774 <30>[ 19.092736] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
825 05:30:15.077108 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
826 05:30:15.129564 <30>[ 19.173298] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
827 05:30:15.158363 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
828 05:30:15.218803 <30>[ 19.262892] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
829 05:30:15.247657 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
830 05:30:15.299722 <30>[ 19.344275] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
831 05:30:15.324990 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
832 05:30:15.380216 <30>[ 19.423527] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
833 05:30:15.397856 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
834 05:30:15.458594 <30>[ 19.502999] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
835 05:30:15.478861 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
836 05:30:15.538575 <30>[ 19.582944] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
837 05:30:15.554855 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
838 05:30:15.575058 <28>[ 19.614259] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
839 05:30:15.594147 <28>[ 19.637645] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
840 05:30:15.640152 <30>[ 19.684971] systemd[1]: Starting systemd-journald.service - Journal Service...
841 05:30:15.657988 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
842 05:30:15.738844 <30>[ 19.782803] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
843 05:30:15.752815 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
844 05:30:15.788912 <30>[ 19.833263] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
845 05:30:15.849278 Starting [0;1;39msystemd-network-g… units from Kernel command line...
846 05:30:15.914096 <30>[ 19.956853] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
847 05:30:15.968043 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
848 05:30:16.013127 <30>[ 20.056769] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
849 05:30:16.073314 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
850 05:30:16.134156 <30>[ 20.178613] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
851 05:30:16.208384 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
852 05:30:16.230030 <30>[ 20.274413] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
853 05:30:16.268904 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
854 05:30:16.291185 <30>[ 20.334323] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
855 05:30:16.312202 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
856 05:30:16.491096 <30>[ 20.536053] systemd[1]: modprobe@configfs.service: Deactivated successfully.
857 05:30:16.529582 <30>[ 20.573419] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
858 05:30:16.558571 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
859 05:30:16.579588 <30>[ 20.623222] systemd[1]: Started systemd-journald.service - Journal Service.
860 05:30:16.586510 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
861 05:30:16.630031 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
862 05:30:16.660640 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
863 05:30:16.689889 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
864 05:30:16.714279 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
865 05:30:16.749797 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
866 05:30:16.778856 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
867 05:30:16.800896 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
868 05:30:16.838751 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
869 05:30:16.868576 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
870 05:30:16.918329 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
871 05:30:16.958523 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
872 05:30:17.034366 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
873 05:30:17.141511 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
874 05:30:17.228715 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
875 05:30:17.306136 <46>[ 21.350283] systemd-journald[164]: Received client request to flush runtime journal.
876 05:30:17.333262 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
877 05:30:17.435047 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
878 05:30:18.178717 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
879 05:30:18.580097 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
880 05:30:18.650737 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
881 05:30:19.061280 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
882 05:30:19.251490 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
883 05:30:19.280907 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
884 05:30:19.298384 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
885 05:30:19.398812 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
886 05:30:19.430403 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
887 05:30:20.440416 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
888 05:30:20.536199 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
889 05:30:21.294596 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
890 05:30:22.602428 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
891 05:30:23.184708 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
892 05:30:23.434906 <5>[ 27.479635] cfg80211: Loading compiled-in X.509 certificates for regulatory database
893 05:30:24.801978 <5>[ 28.848778] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
894 05:30:24.828432 <5>[ 28.873738] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
895 05:30:24.845458 <4>[ 28.890022] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
896 05:30:24.851542 <6>[ 28.899147] cfg80211: failed to load regulatory.db
897 05:30:25.889331 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
898 05:30:33.127238 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
899 05:30:33.156285 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
900 05:30:33.180535 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
901 05:30:33.241210 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
902 05:30:33.280455 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
903 05:30:33.319200 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
904 05:30:33.391400 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
905 05:30:33.478051 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
906 05:30:33.539826 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
907 05:30:33.593363 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
908 05:30:33.637997 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
909 05:30:33.672010 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
910 05:30:33.721565 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
911 05:30:33.879784 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
912 05:30:34.155723 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
913 05:30:34.179833 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
914 05:30:34.200677 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
915 05:30:34.222581 <46>[ 38.258368] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
916 05:30:34.235021 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
917 05:30:34.249380 <46>[ 38.285608] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
918 05:30:34.274016 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
919 05:30:34.307687 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
920 05:30:34.328950 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
921 05:30:34.965002 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
922 05:30:35.423225 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
923 05:30:35.447469 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
924 05:30:35.472924 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
925 05:30:35.498191 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
926 05:30:35.508739 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
927 05:30:35.978941 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
928 05:30:36.093189 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
929 05:30:36.640907 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
930 05:30:36.730691 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
931 05:30:36.806069 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
932 05:30:36.855138 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
933 05:30:36.889275 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
934 05:30:37.060873 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
935 05:30:37.138156 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
936 05:30:37.199494 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
937 05:30:37.217644 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
938 05:30:37.247032 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
939 05:30:37.491897 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
940 05:30:37.803101 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
941 05:30:37.859725 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
942 05:30:37.883917 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
943 05:30:37.967386 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
944 05:30:38.130175 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
945 05:30:38.251506
946 05:30:38.252165 Debian GNU/Linux 12 debian-bookworm-a
947 05:30:38.252627
948 05:30:38.257623 debian-bookworm-armhf login: root (automatic login)
949 05:30:38.258188
950 05:30:38.586635 Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Sat Nov 9 04:32:22 UTC 2024 armv7l
951 05:30:38.593712
952 05:30:38.599292 The programs included with the Debian GNU/Linux system are free software;
953 05:30:38.604894 the exact distribution terms for each program are described in the
954 05:30:38.610485 individual files in /usr/share/doc/*/copyright.
955 05:30:38.610766
956 05:30:38.616835 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
957 05:30:38.617120 permitted by applicable law.
958 05:30:43.689066 Unable to match end of the kernel message
960 05:30:43.690053 Setting prompt string to ['/ #']
961 05:30:43.690651 end: 2.4.4.1 login-action (duration 00:00:48) [common]
963 05:30:43.692115 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
964 05:30:43.692687 start: 2.4.5 expect-shell-connection (timeout 00:03:13) [common]
965 05:30:43.693169 Setting prompt string to ['/ #']
966 05:30:43.693608 Forcing a shell prompt, looking for ['/ #']
968 05:30:43.744645 / #
969 05:30:43.745231 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
970 05:30:43.745500 Waiting using forced prompt support (timeout 00:02:30)
971 05:30:43.748892
972 05:30:43.755075 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
973 05:30:43.755724 start: 2.4.6 export-device-env (timeout 00:03:13) [common]
974 05:30:43.756272 Sending with 10 millisecond of delay
976 05:30:48.747314 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/965201/extract-nfsrootfs-oha3c1lx'
977 05:30:48.760173 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/965201/extract-nfsrootfs-oha3c1lx'
978 05:30:48.761021 Sending with 10 millisecond of delay
980 05:30:50.858862 / # export NFS_SERVER_IP='192.168.6.3'
981 05:30:50.869883 export NFS_SERVER_IP='192.168.6.3'
982 05:30:50.871227 end: 2.4.6 export-device-env (duration 00:00:07) [common]
983 05:30:50.871858 end: 2.4 uboot-commands (duration 00:01:54) [common]
984 05:30:50.872479 end: 2 uboot-action (duration 00:01:54) [common]
985 05:30:50.873087 start: 3 lava-test-retry (timeout 00:06:55) [common]
986 05:30:50.873718 start: 3.1 lava-test-shell (timeout 00:06:55) [common]
987 05:30:50.874269 Using namespace: common
989 05:30:50.975430 / # #
990 05:30:50.975835 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
991 05:30:50.980561 #
992 05:30:50.986614 Using /lava-965201
994 05:30:51.087883 / # export SHELL=/bin/bash
995 05:30:51.092757 export SHELL=/bin/bash
997 05:30:51.199735 / # . /lava-965201/environment
998 05:30:51.205128 . /lava-965201/environment
1000 05:30:51.318160 / # /lava-965201/bin/lava-test-runner /lava-965201/0
1001 05:30:51.318797 Test shell timeout: 10s (minimum of the action and connection timeout)
1002 05:30:51.323539 /lava-965201/bin/lava-test-runner /lava-965201/0
1003 05:30:51.712527 + export TESTRUN_ID=0_timesync-off
1004 05:30:51.720307 + TESTRUN_ID=0_timesync-off
1005 05:30:51.720861 + cd /lava-965201/0/tests/0_timesync-off
1006 05:30:51.721356 ++ cat uuid
1007 05:30:51.736024 + UUID=965201_1.6.2.4.1
1008 05:30:51.736585 + set +x
1009 05:30:51.744674 <LAVA_SIGNAL_STARTRUN 0_timesync-off 965201_1.6.2.4.1>
1010 05:30:51.745204 + systemctl stop systemd-timesyncd
1011 05:30:51.745979 Received signal: <STARTRUN> 0_timesync-off 965201_1.6.2.4.1
1012 05:30:51.746497 Starting test lava.0_timesync-off (965201_1.6.2.4.1)
1013 05:30:51.747068 Skipping test definition patterns.
1014 05:30:52.074954 + set +x
1015 05:30:52.075614 <LAVA_SIGNAL_ENDRUN 0_timesync-off 965201_1.6.2.4.1>
1016 05:30:52.076368 Received signal: <ENDRUN> 0_timesync-off 965201_1.6.2.4.1
1017 05:30:52.076924 Ending use of test pattern.
1018 05:30:52.077379 Ending test lava.0_timesync-off (965201_1.6.2.4.1), duration 0.33
1020 05:30:52.239902 + export TESTRUN_ID=1_kselftest-dt
1021 05:30:52.247637 + TESTRUN_ID=1_kselftest-dt
1022 05:30:52.247942 + cd /lava-965201/0/tests/1_kselftest-dt
1023 05:30:52.248166 ++ cat uuid
1024 05:30:52.263366 + UUID=965201_1.6.2.4.5
1025 05:30:52.263685 + set +x
1026 05:30:52.268973 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 965201_1.6.2.4.5>
1027 05:30:52.269275 + cd ./automated/linux/kselftest/
1028 05:30:52.269723 Received signal: <STARTRUN> 1_kselftest-dt 965201_1.6.2.4.5
1029 05:30:52.270000 Starting test lava.1_kselftest-dt (965201_1.6.2.4.5)
1030 05:30:52.270273 Skipping test definition patterns.
1031 05:30:52.298768 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-256-gebd9c70be2b2/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1032 05:30:52.415244 INFO: install_deps skipped
1033 05:30:53.060166 --2024-11-09 05:30:53-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-256-gebd9c70be2b2/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1034 05:30:53.085643 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1035 05:30:53.227169 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1036 05:30:53.367243 HTTP request sent, awaiting response... 200 OK
1037 05:30:53.367838 Length: 4097980 (3.9M) [application/octet-stream]
1038 05:30:53.372776 Saving to: 'kselftest_armhf.tar.gz'
1039 05:30:53.373297
1040 05:30:54.922281
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 181KB/s
kselftest_armhf.tar 4%[ ] 194.76K 346KB/s
kselftest_armhf.tar 19%[==> ] 794.26K 959KB/s
kselftest_armhf.tar 29%[====> ] 1.14M 1002KB/s
kselftest_armhf.tar 82%[===============> ] 3.22M 2.11MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.52MB/s in 1.5s
1041 05:30:54.922974
1042 05:30:55.517786 2024-11-09 05:30:54 (2.52 MB/s) - 'kselftest_armhf.tar.gz' saved [4097980/4097980]
1043 05:30:55.518509
1044 05:31:10.012160 skiplist:
1045 05:31:10.012557 ========================================
1046 05:31:10.017937 ========================================
1047 05:31:10.123662 dt:test_unprobed_devices.sh
1048 05:31:10.159270 ============== Tests to run ===============
1049 05:31:10.168037 dt:test_unprobed_devices.sh
1050 05:31:10.170980 ===========End Tests to run ===============
1051 05:31:10.182518 shardfile-dt pass
1052 05:31:10.429963 <12>[ 74.480083] kselftest: Running tests in dt
1053 05:31:10.459481 TAP version 13
1054 05:31:10.484858 1..1
1055 05:31:10.545111 # timeout set to 45
1056 05:31:10.545962 # selftests: dt: test_unprobed_devices.sh
1057 05:31:11.374538 # TAP version 13
1058 05:31:36.190794 # 1..257
1059 05:31:36.377295 # ok 1 / # SKIP
1060 05:31:36.393696 # ok 2 /clk_mcasp0
1061 05:31:36.465539 # ok 3 /clk_mcasp0_fixed # SKIP
1062 05:31:36.538003 # ok 4 /cpus/cpu@0 # SKIP
1063 05:31:36.604467 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1064 05:31:36.625311 # ok 6 /fixedregulator0
1065 05:31:36.648328 # ok 7 /leds
1066 05:31:36.667811 # ok 8 /ocp
1067 05:31:36.695505 # ok 9 /ocp/interconnect@44c00000
1068 05:31:36.719205 # ok 10 /ocp/interconnect@44c00000/segment@0
1069 05:31:36.741581 # ok 11 /ocp/interconnect@44c00000/segment@100000
1070 05:31:36.767942 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1071 05:31:36.838969 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1072 05:31:36.859047 # ok 14 /ocp/interconnect@44c00000/segment@200000
1073 05:31:36.883055 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1074 05:31:36.989448 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1075 05:31:37.062893 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1076 05:31:37.135136 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1077 05:31:37.202268 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1078 05:31:37.276026 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1079 05:31:37.349901 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1080 05:31:37.417543 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1081 05:31:37.488705 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1082 05:31:37.560832 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1083 05:31:37.632261 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1084 05:31:37.703031 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1085 05:31:37.823509 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1086 05:31:37.975385 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1087 05:31:38.068174 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1088 05:31:38.139202 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1089 05:31:38.211338 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1090 05:31:38.283077 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1091 05:31:38.391011 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1092 05:31:38.469948 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1093 05:31:38.542223 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1094 05:31:38.613334 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1095 05:31:38.699818 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1096 05:31:38.771510 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1097 05:31:38.842986 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1098 05:31:38.915971 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1099 05:31:38.984823 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1100 05:31:39.063471 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1101 05:31:39.146407 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1102 05:31:39.221428 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1103 05:31:39.293043 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1104 05:31:39.364807 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1105 05:31:39.436988 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1106 05:31:39.503599 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1107 05:31:39.611157 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1108 05:31:39.679014 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1109 05:31:39.752290 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1110 05:31:39.824412 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1111 05:31:39.904311 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1112 05:31:39.975833 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1113 05:31:40.042996 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1114 05:31:40.115366 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1115 05:31:40.205624 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1116 05:31:40.305038 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1117 05:31:40.414285 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1118 05:31:40.498358 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1119 05:31:40.570526 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1120 05:31:40.642040 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1121 05:31:40.713710 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1122 05:31:40.853424 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1123 05:31:40.934233 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1124 05:31:41.004582 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1125 05:31:41.075868 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1126 05:31:41.158025 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1127 05:31:41.267130 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1128 05:31:41.335627 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1129 05:31:41.423245 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1130 05:31:41.496400 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1131 05:31:41.585390 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1132 05:31:41.705313 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1133 05:31:41.774964 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1134 05:31:41.847523 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1135 05:31:41.924058 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1136 05:31:42.062410 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1137 05:31:42.204947 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1138 05:31:42.280947 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1139 05:31:42.349381 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1140 05:31:42.445532 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1141 05:31:42.517316 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1142 05:31:42.588332 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1143 05:31:42.659858 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1144 05:31:42.730471 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1145 05:31:42.802274 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1146 05:31:42.874021 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1147 05:31:42.952945 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1148 05:31:43.021371 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1149 05:31:43.093464 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1150 05:31:43.186146 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1151 05:31:43.258000 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1152 05:31:43.330818 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1153 05:31:43.351112 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1154 05:31:43.379522 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1155 05:31:43.403993 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1156 05:31:43.426094 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1157 05:31:43.462096 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1158 05:31:43.490545 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1159 05:31:43.521715 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1160 05:31:43.537727 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1161 05:31:43.643481 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1162 05:31:43.672773 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1163 05:31:43.695004 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1164 05:31:43.716072 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1165 05:31:43.841301 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1166 05:31:43.915325 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1167 05:31:43.986791 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1168 05:31:44.054493 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1169 05:31:44.166012 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1170 05:31:44.275637 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1171 05:31:44.342229 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1172 05:31:44.414501 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1173 05:31:44.487733 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1174 05:31:44.586432 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1175 05:31:44.674294 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1176 05:31:44.746952 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1177 05:31:44.818260 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1178 05:31:44.902678 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1179 05:31:44.982303 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1180 05:31:45.054623 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1181 05:31:45.077968 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1182 05:31:45.147996 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1183 05:31:45.217198 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1184 05:31:45.289295 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1185 05:31:45.331376 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1186 05:31:45.409232 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1187 05:31:45.431573 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1188 05:31:45.504109 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1189 05:31:45.525052 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1190 05:31:45.549484 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1191 05:31:45.573052 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1192 05:31:45.601801 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1193 05:31:45.622933 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1194 05:31:45.649346 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1195 05:31:45.674992 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1196 05:31:45.746389 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1197 05:31:45.768109 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1198 05:31:45.790810 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1199 05:31:45.863156 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1200 05:31:45.934178 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1201 05:31:45.955638 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1202 05:31:46.055323 # not ok 144 /ocp/interconnect@47c00000
1203 05:31:46.126487 # not ok 145 /ocp/interconnect@47c00000/segment@0
1204 05:31:46.147258 # ok 146 /ocp/interconnect@48000000
1205 05:31:46.175323 # ok 147 /ocp/interconnect@48000000/segment@0
1206 05:31:46.195330 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1207 05:31:46.222065 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1208 05:31:46.243327 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1209 05:31:46.269634 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1210 05:31:46.291696 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1211 05:31:46.313219 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1212 05:31:46.335829 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1213 05:31:46.408223 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1214 05:31:46.480456 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1215 05:31:46.503312 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1216 05:31:46.532104 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1217 05:31:46.552401 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1218 05:31:46.578310 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1219 05:31:46.601884 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1220 05:31:46.623149 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1221 05:31:46.643823 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1222 05:31:46.673187 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1223 05:31:46.692430 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1224 05:31:46.715650 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1225 05:31:46.741963 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1226 05:31:46.763152 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1227 05:31:46.784872 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1228 05:31:46.813055 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1229 05:31:46.832522 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1230 05:31:46.855823 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1231 05:31:46.882070 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1232 05:31:46.903442 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1233 05:31:46.923285 # ok 175 /ocp/interconnect@48000000/segment@100000
1234 05:31:46.952107 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1235 05:31:46.973460 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1236 05:31:47.046451 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1237 05:31:47.116833 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1238 05:31:47.188790 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1239 05:31:47.261941 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1240 05:31:47.331512 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1241 05:31:47.404668 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1242 05:31:47.474666 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1243 05:31:47.548805 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1244 05:31:47.571708 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1245 05:31:47.592980 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1246 05:31:47.614804 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1247 05:31:47.638173 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1248 05:31:47.660968 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1249 05:31:47.685721 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1250 05:31:47.708181 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1251 05:31:47.732170 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1252 05:31:47.755396 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1253 05:31:47.778315 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1254 05:31:47.802829 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1255 05:31:47.826024 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1256 05:31:47.846111 # ok 198 /ocp/interconnect@48000000/segment@200000
1257 05:31:47.872500 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1258 05:31:47.942421 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1259 05:31:47.967128 # ok 201 /ocp/interconnect@48000000/segment@300000
1260 05:31:47.991878 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1261 05:31:48.012919 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1262 05:31:48.039659 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1263 05:31:48.062766 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1264 05:31:48.088231 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1265 05:31:48.107379 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1266 05:31:48.183248 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1267 05:31:48.199811 # ok 209 /ocp/interconnect@4a000000
1268 05:31:48.228512 # ok 210 /ocp/interconnect@4a000000/segment@0
1269 05:31:48.246041 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1270 05:31:48.271030 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1271 05:31:48.296313 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1272 05:31:48.317331 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1273 05:31:48.391959 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1274 05:31:48.493791 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1275 05:31:48.564263 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1276 05:31:48.669052 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1277 05:31:48.739325 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1278 05:31:48.809493 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1279 05:31:48.908397 # not ok 221 /ocp/interconnect@4b140000
1280 05:31:48.981018 # not ok 222 /ocp/interconnect@4b140000/segment@0
1281 05:31:49.055322 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1282 05:31:49.077645 # ok 224 /ocp/target-module@40300000
1283 05:31:49.096308 # ok 225 /ocp/target-module@40300000/sram@0
1284 05:31:49.172416 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1285 05:31:49.240153 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1286 05:31:49.265128 # ok 228 /ocp/target-module@47400000
1287 05:31:49.290640 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1288 05:31:49.311028 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1289 05:31:49.335905 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1290 05:31:49.358005 # ok 232 /ocp/target-module@47400000/usb@1400
1291 05:31:49.376428 # ok 233 /ocp/target-module@47400000/usb@1800
1292 05:31:49.400035 # ok 234 /ocp/target-module@47810000
1293 05:31:49.420548 # ok 235 /ocp/target-module@49000000
1294 05:31:49.443461 # ok 236 /ocp/target-module@49000000/dma@0
1295 05:31:49.464397 # ok 237 /ocp/target-module@49800000
1296 05:31:49.490520 # ok 238 /ocp/target-module@49800000/dma@0
1297 05:31:49.516445 # ok 239 /ocp/target-module@49900000
1298 05:31:49.532771 # ok 240 /ocp/target-module@49900000/dma@0
1299 05:31:49.559510 # ok 241 /ocp/target-module@49a00000
1300 05:31:49.586182 # ok 242 /ocp/target-module@49a00000/dma@0
1301 05:31:49.603565 # ok 243 /ocp/target-module@4c000000
1302 05:31:49.679023 # not ok 244 /ocp/target-module@4c000000/emif@0
1303 05:31:49.699938 # ok 245 /ocp/target-module@50000000
1304 05:31:49.726087 # ok 246 /ocp/target-module@53100000
1305 05:31:49.791605 # not ok 247 /ocp/target-module@53100000/sham@0
1306 05:31:49.813189 # ok 248 /ocp/target-module@53500000
1307 05:31:49.884277 # not ok 249 /ocp/target-module@53500000/aes@0
1308 05:31:49.909870 # ok 250 /ocp/target-module@56000000
1309 05:31:50.010577 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1310 05:31:50.079455 # ok 252 /opp-table # SKIP
1311 05:31:50.148899 # ok 253 /soc # SKIP
1312 05:31:50.174485 # ok 254 /sound
1313 05:31:50.192790 # ok 255 /target-module@4b000000
1314 05:31:50.221460 # ok 256 /target-module@4b000000/target-module@140000
1315 05:31:50.238916 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1316 05:31:50.247058 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1317 05:31:50.255779 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1318 05:31:52.543479 dt_test_unprobed_devices_sh_ skip
1319 05:31:52.549052 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1320 05:31:52.554702 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1321 05:31:52.555196 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1322 05:31:52.563407 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1323 05:31:52.563882 dt_test_unprobed_devices_sh_fixedregulator0 pass
1324 05:31:52.569187 dt_test_unprobed_devices_sh_leds pass
1325 05:31:52.574698 dt_test_unprobed_devices_sh_ocp pass
1326 05:31:52.580293 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1327 05:31:52.586013 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1328 05:31:52.591660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1329 05:31:52.597201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1330 05:31:52.608297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1331 05:31:52.614172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1332 05:31:52.619610 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1333 05:31:52.630548 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1334 05:31:52.641805 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1335 05:31:52.647440 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1336 05:31:52.658583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1337 05:31:52.669886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1338 05:31:52.681068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1339 05:31:52.692280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1340 05:31:52.697967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1341 05:31:52.709052 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1342 05:31:52.720285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1343 05:31:52.731502 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1344 05:31:52.737169 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1345 05:31:52.748266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1346 05:31:52.759530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1347 05:31:52.770689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1348 05:31:52.781900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1349 05:31:52.787364 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1350 05:31:52.798635 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1351 05:31:52.809843 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1352 05:31:52.821053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1353 05:31:52.826616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1354 05:31:52.837782 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1355 05:31:52.848972 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1356 05:31:52.860215 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1357 05:31:52.871528 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1358 05:31:52.882680 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1359 05:31:52.893901 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1360 05:31:52.905025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1361 05:31:52.916204 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1362 05:31:52.927461 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1363 05:31:52.938629 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1364 05:31:52.949879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1365 05:31:52.960988 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1366 05:31:52.972194 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1367 05:31:52.983373 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1368 05:31:52.994641 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1369 05:31:53.005731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1370 05:31:53.017026 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1371 05:31:53.028218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1372 05:31:53.039365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1373 05:31:53.050579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1374 05:31:53.062119 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1375 05:31:53.072960 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1376 05:31:53.078560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1377 05:31:53.089741 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1378 05:31:53.100915 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1379 05:31:53.112124 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1380 05:31:53.123313 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1381 05:31:53.134562 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1382 05:31:53.145714 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1383 05:31:53.156862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1384 05:31:53.168209 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1385 05:31:53.179254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1386 05:31:53.190476 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1387 05:31:53.196043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1388 05:31:53.207234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1389 05:31:53.218453 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1390 05:31:53.229676 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1391 05:31:53.240862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1392 05:31:53.252029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1393 05:31:53.263348 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1394 05:31:53.274426 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1395 05:31:53.285594 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1396 05:31:53.296743 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1397 05:31:53.307985 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1398 05:31:53.319131 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1399 05:31:53.330385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1400 05:31:53.341546 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1401 05:31:53.352742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1402 05:31:53.358345 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1403 05:31:53.369666 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1404 05:31:53.380661 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1405 05:31:53.391871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1406 05:31:53.403138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1407 05:31:53.414275 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1408 05:31:53.425526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1409 05:31:53.436713 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1410 05:31:53.447864 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1411 05:31:53.459073 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1412 05:31:53.470247 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1413 05:31:53.481477 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1414 05:31:53.487059 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1415 05:31:53.498246 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1416 05:31:53.509417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1417 05:31:53.515096 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1418 05:31:53.526124 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1419 05:31:53.531812 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1420 05:31:53.542948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1421 05:31:53.554186 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1422 05:31:53.559842 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1423 05:31:53.571014 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1424 05:31:53.582184 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1425 05:31:53.593432 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1426 05:31:53.604570 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1427 05:31:53.615852 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1428 05:31:53.627015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1429 05:31:53.643731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1430 05:31:53.654905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1431 05:31:53.666132 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1432 05:31:53.677295 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1433 05:31:53.688580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1434 05:31:53.699724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1435 05:31:53.716539 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1436 05:31:53.727687 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1437 05:31:53.739064 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1438 05:31:53.750133 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1439 05:31:53.767007 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1440 05:31:53.778170 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1441 05:31:53.783759 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1442 05:31:53.794902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1443 05:31:53.800549 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1444 05:31:53.811715 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1445 05:31:53.822909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1446 05:31:53.828503 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1447 05:31:53.839611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1448 05:31:53.845320 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1449 05:31:53.856550 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1450 05:31:53.862105 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1451 05:31:53.873291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1452 05:31:53.878927 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1453 05:31:53.890094 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1454 05:31:53.901315 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1455 05:31:53.912550 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1456 05:31:53.918104 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1457 05:31:53.929372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1458 05:31:53.940400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1459 05:31:53.951727 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1460 05:31:53.957232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1461 05:31:53.962842 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1462 05:31:53.968417 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1463 05:31:53.974120 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1464 05:31:53.979649 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1465 05:31:53.990885 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1466 05:31:53.996444 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1467 05:31:54.007710 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1468 05:31:54.013308 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1469 05:31:54.018973 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1470 05:31:54.030151 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1471 05:31:54.035622 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1472 05:31:54.046802 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1473 05:31:54.052393 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1474 05:31:54.063640 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1475 05:31:54.069298 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1476 05:31:54.080392 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1477 05:31:54.085984 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1478 05:31:54.091563 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1479 05:31:54.102755 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1480 05:31:54.108361 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1481 05:31:54.119516 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1482 05:31:54.125145 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1483 05:31:54.136317 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1484 05:31:54.141954 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1485 05:31:54.153096 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1486 05:31:54.158712 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1487 05:31:54.169992 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1488 05:31:54.175504 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1489 05:31:54.186757 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1490 05:31:54.192349 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1491 05:31:54.203516 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1492 05:31:54.209098 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1493 05:31:54.214690 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1494 05:31:54.225910 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1495 05:31:54.237234 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1496 05:31:54.248263 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1497 05:31:54.259460 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1498 05:31:54.270628 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1499 05:31:54.276354 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1500 05:31:54.287456 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1501 05:31:54.298629 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1502 05:31:54.309946 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1503 05:31:54.321594 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1504 05:31:54.326679 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1505 05:31:54.337747 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1506 05:31:54.343371 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1507 05:31:54.354597 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1508 05:31:54.360253 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1509 05:31:54.371518 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1510 05:31:54.377034 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1511 05:31:54.388221 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1512 05:31:54.393921 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1513 05:31:54.405111 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1514 05:31:54.410677 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1515 05:31:54.421936 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1516 05:31:54.427589 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1517 05:31:54.438756 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1518 05:31:54.444391 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1519 05:31:54.449884 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1520 05:31:54.461068 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1521 05:31:54.467159 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1522 05:31:54.478041 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1523 05:31:54.483547 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1524 05:31:54.494693 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1525 05:31:54.500245 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1526 05:31:54.505767 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1527 05:31:54.511409 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1528 05:31:54.522554 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1529 05:31:54.528123 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1530 05:31:54.539339 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1531 05:31:54.544997 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1532 05:31:54.556219 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1533 05:31:54.567382 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1534 05:31:54.578658 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1535 05:31:54.584307 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1536 05:31:54.595408 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1537 05:31:54.606851 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1538 05:31:54.612447 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1539 05:31:54.617902 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1540 05:31:54.623468 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1541 05:31:54.629069 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1542 05:31:54.634690 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1543 05:31:54.640294 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1544 05:31:54.651465 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1545 05:31:54.651920 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1546 05:31:54.662723 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1547 05:31:54.668333 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1548 05:31:54.674280 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1549 05:31:54.679545 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1550 05:31:54.685135 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1551 05:31:54.690742 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1552 05:31:54.696393 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1553 05:31:54.702044 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1554 05:31:54.707638 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1555 05:31:54.713145 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1556 05:31:54.718767 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1557 05:31:54.724388 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1558 05:31:54.730050 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1559 05:31:54.735588 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1560 05:31:54.741165 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1561 05:31:54.746802 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1562 05:31:54.752388 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1563 05:31:54.758025 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1564 05:31:54.763604 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1565 05:31:54.769173 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1566 05:31:54.774800 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1567 05:31:54.780413 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1568 05:31:54.786074 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1569 05:31:54.791740 dt_test_unprobed_devices_sh_opp-table skip
1570 05:31:54.792191 dt_test_unprobed_devices_sh_soc skip
1571 05:31:54.797305 dt_test_unprobed_devices_sh_sound pass
1572 05:31:54.802791 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1573 05:31:54.808491 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1574 05:31:54.814120 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1575 05:31:54.819612 dt_test_unprobed_devices_sh fail
1576 05:31:54.825209 + ../../utils/send-to-lava.sh ./output/result.txt
1577 05:31:54.829176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1578 05:31:54.830053 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1580 05:31:54.844529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1581 05:31:54.845229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1583 05:31:54.938824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1584 05:31:54.939617 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1586 05:31:55.031887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1587 05:31:55.032698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1589 05:31:55.122597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1590 05:31:55.123391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1592 05:31:55.214771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1593 05:31:55.215549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1595 05:31:55.304738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1596 05:31:55.305621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1598 05:31:55.395146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1599 05:31:55.396074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1601 05:31:55.487975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1602 05:31:55.488637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1604 05:31:55.582041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1605 05:31:55.582934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1607 05:31:55.676740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1608 05:31:55.677619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1610 05:31:55.768927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1611 05:31:55.769842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1613 05:31:55.862536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1614 05:31:55.863378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1616 05:31:55.955382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1617 05:31:55.956223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1619 05:31:56.055108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1620 05:31:56.056006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1622 05:31:56.157557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1623 05:31:56.158452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1625 05:31:56.260247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1626 05:31:56.261116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1628 05:31:56.362145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1629 05:31:56.363097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1631 05:31:56.459935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1632 05:31:56.460776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1634 05:31:56.552006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1635 05:31:56.552648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1637 05:31:56.643503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1638 05:31:56.644430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1640 05:31:56.734594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1641 05:31:56.735606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1643 05:31:56.828177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1644 05:31:56.829036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1646 05:31:56.922211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1647 05:31:56.923050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1649 05:31:57.016716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1650 05:31:57.017546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1652 05:31:57.110676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1653 05:31:57.111535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1655 05:31:57.202341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1656 05:31:57.203206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1658 05:31:57.293961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1659 05:31:57.294808 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1661 05:31:57.387024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1662 05:31:57.388028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1664 05:31:57.480675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1665 05:31:57.481335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1667 05:31:57.573928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1668 05:31:57.574880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1670 05:31:57.667711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1671 05:31:57.668519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1673 05:31:57.768530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1674 05:31:57.769302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1676 05:31:57.871535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1677 05:31:57.872235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1679 05:31:57.962818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1680 05:31:57.963593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1682 05:31:58.055528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1683 05:31:58.056297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1685 05:31:58.157267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1686 05:31:58.157988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1688 05:31:58.252974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1689 05:31:58.253483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1691 05:31:58.344504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1692 05:31:58.345127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1694 05:31:58.433998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1695 05:31:58.434830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1697 05:31:58.525021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1698 05:31:58.525793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1700 05:31:58.617441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1701 05:31:58.618286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1703 05:31:58.710086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1704 05:31:58.710804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1706 05:31:58.801222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1707 05:31:58.801929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1709 05:31:58.891670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1710 05:31:58.892369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1712 05:31:58.983181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1713 05:31:58.983872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1715 05:31:59.076034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1716 05:31:59.076890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1718 05:31:59.169596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1719 05:31:59.170188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1721 05:31:59.270596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1722 05:31:59.271383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1724 05:31:59.372008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1725 05:31:59.372766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1727 05:31:59.465347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1728 05:31:59.466207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1730 05:31:59.558576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1731 05:31:59.559383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1733 05:31:59.652263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1734 05:31:59.653025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1736 05:31:59.744817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1737 05:31:59.745505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1739 05:31:59.837609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1740 05:31:59.838324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1742 05:31:59.930286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1743 05:31:59.931070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1745 05:32:00.022174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1746 05:32:00.023035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1748 05:32:00.114578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1749 05:32:00.115474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1751 05:32:00.204896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1752 05:32:00.205752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1754 05:32:00.297666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1755 05:32:00.298353 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1757 05:32:00.390429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1758 05:32:00.391284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1760 05:32:00.483567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1761 05:32:00.484430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1763 05:32:00.574045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1764 05:32:00.574857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1766 05:32:00.666042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1767 05:32:00.666834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1769 05:32:00.759072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1770 05:32:00.759847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1772 05:32:00.850713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1773 05:32:00.851491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1775 05:32:00.942568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1776 05:32:00.943344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1778 05:32:01.035866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1779 05:32:01.036681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1781 05:32:01.135771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1782 05:32:01.136578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1784 05:32:01.236828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1785 05:32:01.237603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1787 05:32:01.339201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1788 05:32:01.339974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1790 05:32:01.431642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1791 05:32:01.432459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1793 05:32:01.524358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1794 05:32:01.526428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1796 05:32:01.615438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1797 05:32:01.616205 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1799 05:32:01.704476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1800 05:32:01.705248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1802 05:32:01.797975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1803 05:32:01.798735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1805 05:32:01.891585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1806 05:32:01.892339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1808 05:32:01.992543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1809 05:32:01.993249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1811 05:32:02.093795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1812 05:32:02.094593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1814 05:32:02.184974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1815 05:32:02.185683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1817 05:32:02.276462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1818 05:32:02.277176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1820 05:32:02.370305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1821 05:32:02.371050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1823 05:32:02.463023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1824 05:32:02.463756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1826 05:32:02.554320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1827 05:32:02.555073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1829 05:32:02.647243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1830 05:32:02.647969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1832 05:32:02.739962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1833 05:32:02.740747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1835 05:32:02.833388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1836 05:32:02.834176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1838 05:32:02.924388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1839 05:32:02.925119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1841 05:32:03.017493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1842 05:32:03.018340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1844 05:32:03.113412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1845 05:32:03.114260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1847 05:32:03.206139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1848 05:32:03.206870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1850 05:32:03.295098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1851 05:32:03.295848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1853 05:32:03.390219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1854 05:32:03.390954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1856 05:32:03.482664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1857 05:32:03.483414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1859 05:32:03.575123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1860 05:32:03.575862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1862 05:32:03.665569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1863 05:32:03.666321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1865 05:32:03.766598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1866 05:32:03.767350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1868 05:32:03.867943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1869 05:32:03.868707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1871 05:32:03.960279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1872 05:32:03.961042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1874 05:32:04.053213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1875 05:32:04.054067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1877 05:32:04.145319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1878 05:32:04.146273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1880 05:32:04.238965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1881 05:32:04.239846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1883 05:32:04.330634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1884 05:32:04.331535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1886 05:32:04.422472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1887 05:32:04.423390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1889 05:32:04.514981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1890 05:32:04.515904 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1892 05:32:04.608756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1893 05:32:04.609699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1895 05:32:04.703837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1896 05:32:04.704697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1898 05:32:04.796541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1899 05:32:04.797408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1901 05:32:04.892446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1902 05:32:04.893289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1904 05:32:04.983787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1905 05:32:04.984614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1907 05:32:05.076023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1908 05:32:05.076913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1910 05:32:05.165213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1911 05:32:05.166047 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1913 05:32:05.250847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1914 05:32:05.251692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1916 05:32:05.343460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1917 05:32:05.344303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1919 05:32:05.435551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1920 05:32:05.436433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1922 05:32:05.527153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1923 05:32:05.528027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1925 05:32:05.620086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1926 05:32:05.620948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1928 05:32:05.713140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1929 05:32:05.714009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1931 05:32:05.813166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1932 05:32:05.814011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1934 05:32:05.906073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1935 05:32:05.906726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1937 05:32:05.998832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1939 05:32:06.000986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1940 05:32:06.091175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1942 05:32:06.093516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1943 05:32:06.184677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1945 05:32:06.186609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1946 05:32:06.277806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1947 05:32:06.278635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1949 05:32:06.369852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1950 05:32:06.370691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1952 05:32:06.460459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1953 05:32:06.461057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1955 05:32:06.551762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1956 05:32:06.552600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1958 05:32:06.642332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1959 05:32:06.643086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1961 05:32:06.735998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1962 05:32:06.736743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1964 05:32:06.828504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1965 05:32:06.829254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1967 05:32:06.921318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1968 05:32:06.922225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1970 05:32:07.013697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1971 05:32:07.014580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1973 05:32:07.105230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1974 05:32:07.106168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1976 05:32:07.196380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1977 05:32:07.197228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1979 05:32:07.287963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1980 05:32:07.288818 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1982 05:32:07.379261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1983 05:32:07.380132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1985 05:32:07.471284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1986 05:32:07.472154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1988 05:32:07.564448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1989 05:32:07.565342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1991 05:32:07.655792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1992 05:32:07.656634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
1994 05:32:07.745765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1995 05:32:07.746634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
1997 05:32:07.839119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
1998 05:32:07.839943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2000 05:32:07.934118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2001 05:32:07.934958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2003 05:32:08.025982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2004 05:32:08.026838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2006 05:32:08.118244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2007 05:32:08.119110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2009 05:32:08.207114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2010 05:32:08.207953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2012 05:32:08.297876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2013 05:32:08.299033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2015 05:32:08.388531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2016 05:32:08.389414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2018 05:32:08.479311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2019 05:32:08.480046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2021 05:32:08.569455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2022 05:32:08.570339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2024 05:32:08.661284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2025 05:32:08.662134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2027 05:32:08.751909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2028 05:32:08.752695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2030 05:32:08.844797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2031 05:32:08.845579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2033 05:32:08.936522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2034 05:32:08.937316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2036 05:32:09.029374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2037 05:32:09.030399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2039 05:32:09.121417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2040 05:32:09.122263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2042 05:32:09.212707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2043 05:32:09.213540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2045 05:32:09.305018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2046 05:32:09.305929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2048 05:32:09.397436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2049 05:32:09.398265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2051 05:32:09.490443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2052 05:32:09.491171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2054 05:32:09.580965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2055 05:32:09.581785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2057 05:32:09.674265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2058 05:32:09.675030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2060 05:32:09.766457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2061 05:32:09.767222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2063 05:32:09.860009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2064 05:32:09.860782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2066 05:32:09.951544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2067 05:32:09.952334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2069 05:32:10.044825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2070 05:32:10.045718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2072 05:32:10.138100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2073 05:32:10.138949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2075 05:32:10.229785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2076 05:32:10.230655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2078 05:32:10.320512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2079 05:32:10.321350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2081 05:32:10.411936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2082 05:32:10.412812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2084 05:32:10.503546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2085 05:32:10.504468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2087 05:32:10.598315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2088 05:32:10.599210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2090 05:32:10.690320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2091 05:32:10.691174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2093 05:32:10.783235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2094 05:32:10.784099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2096 05:32:10.874099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2097 05:32:10.874633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2099 05:32:10.970060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2100 05:32:10.970952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2102 05:32:11.058654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2103 05:32:11.059499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2105 05:32:11.153117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2106 05:32:11.153931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2108 05:32:11.245756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2109 05:32:11.246696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2111 05:32:11.341745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2112 05:32:11.342596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2114 05:32:11.442480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2115 05:32:11.443315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2117 05:32:11.542953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2118 05:32:11.543806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2120 05:32:11.644788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2121 05:32:11.645605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2123 05:32:11.737293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2124 05:32:11.738120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2126 05:32:11.831291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2127 05:32:11.832091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2129 05:32:11.921887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2130 05:32:11.922700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2132 05:32:12.015055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2133 05:32:12.015863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2135 05:32:12.103951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2136 05:32:12.104779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2138 05:32:12.205453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2139 05:32:12.206309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2141 05:32:12.301130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2142 05:32:12.301951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2144 05:32:12.391324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2145 05:32:12.392138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2147 05:32:12.481167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2148 05:32:12.482016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2150 05:32:12.569759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2151 05:32:12.570619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2153 05:32:12.662544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2154 05:32:12.663350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2156 05:32:12.757341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2157 05:32:12.757870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2159 05:32:12.851077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2160 05:32:12.851724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2162 05:32:12.940859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2163 05:32:12.941658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2165 05:32:13.032063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2166 05:32:13.032900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2168 05:32:13.122636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2169 05:32:13.123162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2171 05:32:13.213322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2172 05:32:13.214184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2174 05:32:13.308075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2175 05:32:13.309828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2177 05:32:13.401034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2178 05:32:13.401906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2180 05:32:13.489703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2181 05:32:13.490601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2183 05:32:13.582371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2184 05:32:13.583968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2186 05:32:13.678669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2187 05:32:13.679300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2189 05:32:13.770685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2190 05:32:13.771330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2192 05:32:13.861796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2193 05:32:13.862944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2195 05:32:13.951085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2196 05:32:13.952056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2198 05:32:14.043143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2199 05:32:14.044067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2201 05:32:14.139042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2202 05:32:14.139857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2204 05:32:14.226447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2205 05:32:14.227232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2207 05:32:14.318294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2208 05:32:14.319069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2210 05:32:14.410913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2211 05:32:14.411815 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2213 05:32:14.502303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2214 05:32:14.502968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2216 05:32:14.594188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2217 05:32:14.595286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2219 05:32:14.685500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2220 05:32:14.686442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2222 05:32:14.780419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2223 05:32:14.781347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2225 05:32:14.874782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2226 05:32:14.875688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2228 05:32:14.969025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2229 05:32:14.969917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2231 05:32:15.060512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2232 05:32:15.061407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2234 05:32:15.151804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2235 05:32:15.152674 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2237 05:32:15.243381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2238 05:32:15.244255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2240 05:32:15.330098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2241 05:32:15.330953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2243 05:32:15.424980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2244 05:32:15.425892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2246 05:32:15.516140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2247 05:32:15.517036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2249 05:32:15.607355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2250 05:32:15.608207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2252 05:32:15.699519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2253 05:32:15.700382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2255 05:32:15.790096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2256 05:32:15.790969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2258 05:32:15.878716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2260 05:32:15.881705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2261 05:32:15.971143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2262 05:32:15.972073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2264 05:32:16.064287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2265 05:32:16.065192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2267 05:32:16.158275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2268 05:32:16.159136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2270 05:32:16.249459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2271 05:32:16.250371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2273 05:32:16.340875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2274 05:32:16.341735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2276 05:32:16.432400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2277 05:32:16.433273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2279 05:32:16.526324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2280 05:32:16.527226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2282 05:32:16.617367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2283 05:32:16.618284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2285 05:32:16.709135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2286 05:32:16.709926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2288 05:32:16.798585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2289 05:32:16.799481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2291 05:32:16.890136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2292 05:32:16.890961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2294 05:32:16.981404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2295 05:32:16.982270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2297 05:32:17.075837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2298 05:32:17.076733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2300 05:32:17.167358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2301 05:32:17.168203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2303 05:32:17.259416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2304 05:32:17.260265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2306 05:32:17.351437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2307 05:32:17.352306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2309 05:32:17.444693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2310 05:32:17.446148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2312 05:32:17.535447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2313 05:32:17.536391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2315 05:32:17.626992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2316 05:32:17.627834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2318 05:32:17.719043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2319 05:32:17.719963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2321 05:32:17.812835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2322 05:32:17.813703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2324 05:32:17.907209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2325 05:32:17.908166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2327 05:32:17.998280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2328 05:32:17.999174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2330 05:32:18.091113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2331 05:32:18.092056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2333 05:32:18.183268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2334 05:32:18.184096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2336 05:32:18.274276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2337 05:32:18.275117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2339 05:32:18.365940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2340 05:32:18.366803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2342 05:32:18.458997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2343 05:32:18.459887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2345 05:32:18.558609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2346 05:32:18.559489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2348 05:32:18.652216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2349 05:32:18.653072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2351 05:32:18.746209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2352 05:32:18.746816 + set +x
2353 05:32:18.747576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2355 05:32:18.750404 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 965201_1.6.2.4.5>
2356 05:32:18.751175 Received signal: <ENDRUN> 1_kselftest-dt 965201_1.6.2.4.5
2357 05:32:18.751659 Ending use of test pattern.
2358 05:32:18.752204 Ending test lava.1_kselftest-dt (965201_1.6.2.4.5), duration 86.48
2360 05:32:18.757092 <LAVA_TEST_RUNNER EXIT>
2361 05:32:18.757927 ok: lava_test_shell seems to have completed
2362 05:32:18.772001 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2363 05:32:18.774229 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2364 05:32:18.775141 end: 3 lava-test-retry (duration 00:01:28) [common]
2365 05:32:18.775798 start: 4 finalize (timeout 00:05:27) [common]
2366 05:32:18.776404 start: 4.1 power-off (timeout 00:00:30) [common]
2367 05:32:18.777514 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2368 05:32:18.813086 >> OK - accepted request
2369 05:32:18.815368 Returned 0 in 0 seconds
2370 05:32:18.916871 end: 4.1 power-off (duration 00:00:00) [common]
2372 05:32:18.918954 start: 4.2 read-feedback (timeout 00:05:27) [common]
2373 05:32:18.920219 Listened to connection for namespace 'common' for up to 1s
2374 05:32:18.921120 Listened to connection for namespace 'common' for up to 1s
2375 05:32:19.920003 Finalising connection for namespace 'common'
2376 05:32:19.920760 Disconnecting from shell: Finalise
2377 05:32:19.921299 / #
2378 05:32:20.022522 end: 4.2 read-feedback (duration 00:00:01) [common]
2379 05:32:20.023441 end: 4 finalize (duration 00:00:01) [common]
2380 05:32:20.024283 Cleaning after the job
2381 05:32:20.025085 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/965201/tftp-deploy-870n_78c/ramdisk
2382 05:32:20.029224 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/965201/tftp-deploy-870n_78c/kernel
2383 05:32:20.031140 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/965201/tftp-deploy-870n_78c/dtb
2384 05:32:20.032358 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/965201/tftp-deploy-870n_78c/nfsrootfs
2385 05:32:20.065150 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/965201/tftp-deploy-870n_78c/modules
2386 05:32:20.072567 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/965201
2387 05:32:23.027418 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/965201
2388 05:32:23.027984 Job finished correctly