Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 6
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 04:59:43.219535 lava-dispatcher, installed at version: 2024.01
2 04:59:43.220324 start: 0 validate
3 04:59:43.220793 Start time: 2024-11-09 04:59:43.220763+00:00 (UTC)
4 04:59:43.221304 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:59:43.221836 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 04:59:43.260351 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:59:43.260863 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-256-gebd9c70be2b2%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 04:59:43.288703 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:59:43.289318 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-256-gebd9c70be2b2%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:59:43.322797 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:59:43.323292 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:59:43.351697 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 04:59:43.352238 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-256-gebd9c70be2b2%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 04:59:43.391459 validate duration: 0.17
16 04:59:43.392336 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:59:43.392656 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:59:43.392963 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:59:43.393516 Not decompressing ramdisk as can be used compressed.
20 04:59:43.393953 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 04:59:43.394226 saving as /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/ramdisk/initrd.cpio.gz
22 04:59:43.394484 total size: 5628169 (5 MB)
23 04:59:43.432579 progress 0 % (0 MB)
24 04:59:43.436996 progress 5 % (0 MB)
25 04:59:43.441042 progress 10 % (0 MB)
26 04:59:43.444643 progress 15 % (0 MB)
27 04:59:43.449102 progress 20 % (1 MB)
28 04:59:43.452831 progress 25 % (1 MB)
29 04:59:43.456883 progress 30 % (1 MB)
30 04:59:43.460896 progress 35 % (1 MB)
31 04:59:43.464530 progress 40 % (2 MB)
32 04:59:43.468526 progress 45 % (2 MB)
33 04:59:43.472035 progress 50 % (2 MB)
34 04:59:43.475961 progress 55 % (2 MB)
35 04:59:43.479972 progress 60 % (3 MB)
36 04:59:43.483611 progress 65 % (3 MB)
37 04:59:43.487542 progress 70 % (3 MB)
38 04:59:43.491128 progress 75 % (4 MB)
39 04:59:43.495184 progress 80 % (4 MB)
40 04:59:43.498560 progress 85 % (4 MB)
41 04:59:43.502419 progress 90 % (4 MB)
42 04:59:43.506104 progress 95 % (5 MB)
43 04:59:43.509565 progress 100 % (5 MB)
44 04:59:43.510258 5 MB downloaded in 0.12 s (46.37 MB/s)
45 04:59:43.510796 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:59:43.511690 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:59:43.512050 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:59:43.512391 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:59:43.512884 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-256-gebd9c70be2b2/arm64/defconfig/gcc-12/kernel/Image
51 04:59:43.513146 saving as /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/kernel/Image
52 04:59:43.513358 total size: 45713920 (43 MB)
53 04:59:43.513569 No compression specified
54 04:59:43.548219 progress 0 % (0 MB)
55 04:59:43.575825 progress 5 % (2 MB)
56 04:59:43.604013 progress 10 % (4 MB)
57 04:59:43.632128 progress 15 % (6 MB)
58 04:59:43.660216 progress 20 % (8 MB)
59 04:59:43.687757 progress 25 % (10 MB)
60 04:59:43.716030 progress 30 % (13 MB)
61 04:59:43.743754 progress 35 % (15 MB)
62 04:59:43.771733 progress 40 % (17 MB)
63 04:59:43.798959 progress 45 % (19 MB)
64 04:59:43.827207 progress 50 % (21 MB)
65 04:59:43.855186 progress 55 % (24 MB)
66 04:59:43.883138 progress 60 % (26 MB)
67 04:59:43.910959 progress 65 % (28 MB)
68 04:59:43.938636 progress 70 % (30 MB)
69 04:59:43.966539 progress 75 % (32 MB)
70 04:59:43.994290 progress 80 % (34 MB)
71 04:59:44.021929 progress 85 % (37 MB)
72 04:59:44.051950 progress 90 % (39 MB)
73 04:59:44.086270 progress 95 % (41 MB)
74 04:59:44.114970 progress 100 % (43 MB)
75 04:59:44.115512 43 MB downloaded in 0.60 s (72.40 MB/s)
76 04:59:44.116007 end: 1.2.1 http-download (duration 00:00:01) [common]
78 04:59:44.116905 end: 1.2 download-retry (duration 00:00:01) [common]
79 04:59:44.117200 start: 1.3 download-retry (timeout 00:09:59) [common]
80 04:59:44.117468 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 04:59:44.117907 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-256-gebd9c70be2b2/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 04:59:44.118172 saving as /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/dtb/meson-g12b-a311d-libretech-cc.dtb
83 04:59:44.118380 total size: 54703 (0 MB)
84 04:59:44.118591 No compression specified
85 04:59:44.161367 progress 59 % (0 MB)
86 04:59:44.162216 progress 100 % (0 MB)
87 04:59:44.162775 0 MB downloaded in 0.04 s (1.18 MB/s)
88 04:59:44.163254 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:59:44.164164 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:59:44.164456 start: 1.4 download-retry (timeout 00:09:59) [common]
92 04:59:44.164734 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 04:59:44.165185 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 04:59:44.165435 saving as /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/nfsrootfs/full.rootfs.tar
95 04:59:44.165653 total size: 120894716 (115 MB)
96 04:59:44.165873 Using unxz to decompress xz
97 04:59:44.200865 progress 0 % (0 MB)
98 04:59:45.022803 progress 5 % (5 MB)
99 04:59:45.877611 progress 10 % (11 MB)
100 04:59:46.674709 progress 15 % (17 MB)
101 04:59:47.416969 progress 20 % (23 MB)
102 04:59:48.098620 progress 25 % (28 MB)
103 04:59:48.995760 progress 30 % (34 MB)
104 04:59:49.799235 progress 35 % (40 MB)
105 04:59:50.147566 progress 40 % (46 MB)
106 04:59:50.535053 progress 45 % (51 MB)
107 04:59:51.267093 progress 50 % (57 MB)
108 04:59:52.161226 progress 55 % (63 MB)
109 04:59:52.960621 progress 60 % (69 MB)
110 04:59:53.736152 progress 65 % (74 MB)
111 04:59:54.526674 progress 70 % (80 MB)
112 04:59:55.367480 progress 75 % (86 MB)
113 04:59:56.161408 progress 80 % (92 MB)
114 04:59:56.940525 progress 85 % (98 MB)
115 04:59:57.826780 progress 90 % (103 MB)
116 04:59:58.762058 progress 95 % (109 MB)
117 04:59:59.775097 progress 100 % (115 MB)
118 04:59:59.791489 115 MB downloaded in 15.63 s (7.38 MB/s)
119 04:59:59.792537 end: 1.4.1 http-download (duration 00:00:16) [common]
121 04:59:59.794286 end: 1.4 download-retry (duration 00:00:16) [common]
122 04:59:59.794842 start: 1.5 download-retry (timeout 00:09:44) [common]
123 04:59:59.795397 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 04:59:59.796519 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-256-gebd9c70be2b2/arm64/defconfig/gcc-12/modules.tar.xz
125 04:59:59.797083 saving as /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/modules/modules.tar
126 04:59:59.797528 total size: 11607448 (11 MB)
127 04:59:59.797983 Using unxz to decompress xz
128 04:59:59.842309 progress 0 % (0 MB)
129 04:59:59.911728 progress 5 % (0 MB)
130 04:59:59.992125 progress 10 % (1 MB)
131 05:00:00.092307 progress 15 % (1 MB)
132 05:00:00.186471 progress 20 % (2 MB)
133 05:00:00.268434 progress 25 % (2 MB)
134 05:00:00.344520 progress 30 % (3 MB)
135 05:00:00.419400 progress 35 % (3 MB)
136 05:00:00.500368 progress 40 % (4 MB)
137 05:00:00.580076 progress 45 % (5 MB)
138 05:00:00.668298 progress 50 % (5 MB)
139 05:00:00.745860 progress 55 % (6 MB)
140 05:00:00.831145 progress 60 % (6 MB)
141 05:00:00.912486 progress 65 % (7 MB)
142 05:00:00.989177 progress 70 % (7 MB)
143 05:00:01.072557 progress 75 % (8 MB)
144 05:00:01.157308 progress 80 % (8 MB)
145 05:00:01.242619 progress 85 % (9 MB)
146 05:00:01.322162 progress 90 % (9 MB)
147 05:00:01.400538 progress 95 % (10 MB)
148 05:00:01.478209 progress 100 % (11 MB)
149 05:00:01.490263 11 MB downloaded in 1.69 s (6.54 MB/s)
150 05:00:01.490850 end: 1.5.1 http-download (duration 00:00:02) [common]
152 05:00:01.491689 end: 1.5 download-retry (duration 00:00:02) [common]
153 05:00:01.491957 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 05:00:01.492552 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 05:00:18.553052 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/965234/extract-nfsrootfs-9k18tv_n
156 05:00:18.553634 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 05:00:18.553927 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 05:00:18.554535 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm
159 05:00:18.554977 makedir: /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin
160 05:00:18.555302 makedir: /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/tests
161 05:00:18.555622 makedir: /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/results
162 05:00:18.555960 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-add-keys
163 05:00:18.556544 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-add-sources
164 05:00:18.557066 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-background-process-start
165 05:00:18.557569 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-background-process-stop
166 05:00:18.558104 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-common-functions
167 05:00:18.558600 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-echo-ipv4
168 05:00:18.559086 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-install-packages
169 05:00:18.559584 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-installed-packages
170 05:00:18.560206 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-os-build
171 05:00:18.560711 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-probe-channel
172 05:00:18.561192 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-probe-ip
173 05:00:18.561665 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-target-ip
174 05:00:18.562134 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-target-mac
175 05:00:18.562611 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-target-storage
176 05:00:18.563098 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-test-case
177 05:00:18.563596 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-test-event
178 05:00:18.564137 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-test-feedback
179 05:00:18.564638 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-test-raise
180 05:00:18.565122 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-test-reference
181 05:00:18.565605 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-test-runner
182 05:00:18.566099 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-test-set
183 05:00:18.566581 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-test-shell
184 05:00:18.567080 Updating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-add-keys (debian)
185 05:00:18.567619 Updating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-add-sources (debian)
186 05:00:18.568160 Updating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-install-packages (debian)
187 05:00:18.568680 Updating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-installed-packages (debian)
188 05:00:18.569196 Updating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/bin/lava-os-build (debian)
189 05:00:18.572758 Creating /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/environment
190 05:00:18.573362 LAVA metadata
191 05:00:18.573653 - LAVA_JOB_ID=965234
192 05:00:18.573879 - LAVA_DISPATCHER_IP=192.168.6.2
193 05:00:18.574280 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 05:00:18.575319 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 05:00:18.575655 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 05:00:18.575866 skipped lava-vland-overlay
197 05:00:18.576141 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 05:00:18.576538 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 05:00:18.576770 skipped lava-multinode-overlay
200 05:00:18.577019 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 05:00:18.577274 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 05:00:18.577535 Loading test definitions
203 05:00:18.577818 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 05:00:18.578040 Using /lava-965234 at stage 0
205 05:00:18.579189 uuid=965234_1.6.2.4.1 testdef=None
206 05:00:18.579504 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 05:00:18.579768 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 05:00:18.581380 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 05:00:18.582181 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 05:00:18.584280 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 05:00:18.585128 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 05:00:18.587006 runner path: /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/0/tests/0_timesync-off test_uuid 965234_1.6.2.4.1
215 05:00:18.587589 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 05:00:18.588442 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 05:00:18.588670 Using /lava-965234 at stage 0
219 05:00:18.589039 Fetching tests from https://github.com/kernelci/test-definitions.git
220 05:00:18.589336 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/0/tests/1_kselftest-alsa'
221 05:00:22.163503 Running '/usr/bin/git checkout kernelci.org
222 05:00:22.337840 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 05:00:22.339274 uuid=965234_1.6.2.4.5 testdef=None
224 05:00:22.339627 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 05:00:22.340429 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 05:00:22.343259 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 05:00:22.344112 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 05:00:22.347817 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 05:00:22.348721 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 05:00:22.352317 runner path: /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/0/tests/1_kselftest-alsa test_uuid 965234_1.6.2.4.5
234 05:00:22.352602 BOARD='meson-g12b-a311d-libretech-cc'
235 05:00:22.352817 BRANCH='broonie-sound'
236 05:00:22.353021 SKIPFILE='/dev/null'
237 05:00:22.353221 SKIP_INSTALL='True'
238 05:00:22.353420 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-256-gebd9c70be2b2/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 05:00:22.353624 TST_CASENAME=''
240 05:00:22.353823 TST_CMDFILES='alsa'
241 05:00:22.354385 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 05:00:22.355181 Creating lava-test-runner.conf files
244 05:00:22.355392 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/965234/lava-overlay-t5x_wmbm/lava-965234/0 for stage 0
245 05:00:22.355788 - 0_timesync-off
246 05:00:22.356068 - 1_kselftest-alsa
247 05:00:22.356424 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 05:00:22.356720 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 05:00:45.797009 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 05:00:45.797469 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 05:00:45.797766 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 05:00:45.798072 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 05:00:45.798342 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 05:00:46.533549 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 05:00:46.534036 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 05:00:46.534288 extracting modules file /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/965234/extract-nfsrootfs-9k18tv_n
257 05:00:48.003753 extracting modules file /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/965234/extract-overlay-ramdisk-p2sveqqo/ramdisk
258 05:00:49.722050 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 05:00:49.722603 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 05:00:49.722955 [common] Applying overlay to NFS
261 05:00:49.723225 [common] Applying overlay /var/lib/lava/dispatcher/tmp/965234/compress-overlay-3g4tl8ou/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/965234/extract-nfsrootfs-9k18tv_n
262 05:00:53.039288 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 05:00:53.039771 start: 1.6.6 prepare-kernel (timeout 00:08:50) [common]
264 05:00:53.040081 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:50) [common]
265 05:00:53.040321 Converting downloaded kernel to a uImage
266 05:00:53.040633 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/kernel/Image /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/kernel/uImage
267 05:00:53.499010 output: Image Name:
268 05:00:53.499451 output: Created: Sat Nov 9 05:00:53 2024
269 05:00:53.499665 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 05:00:53.499872 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 05:00:53.500116 output: Load Address: 01080000
272 05:00:53.500323 output: Entry Point: 01080000
273 05:00:53.500524 output:
274 05:00:53.500867 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 05:00:53.501148 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 05:00:53.501420 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 05:00:53.501679 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 05:00:53.501939 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 05:00:53.502203 Building ramdisk /var/lib/lava/dispatcher/tmp/965234/extract-overlay-ramdisk-p2sveqqo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/965234/extract-overlay-ramdisk-p2sveqqo/ramdisk
280 05:00:55.695493 >> 166792 blocks
281 05:01:04.113104 Adding RAMdisk u-boot header.
282 05:01:04.113561 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/965234/extract-overlay-ramdisk-p2sveqqo/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/965234/extract-overlay-ramdisk-p2sveqqo/ramdisk.cpio.gz.uboot
283 05:01:04.359717 output: Image Name:
284 05:01:04.360302 output: Created: Sat Nov 9 05:01:04 2024
285 05:01:04.360725 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 05:01:04.361136 output: Data Size: 23434296 Bytes = 22885.05 KiB = 22.35 MiB
287 05:01:04.361540 output: Load Address: 00000000
288 05:01:04.361937 output: Entry Point: 00000000
289 05:01:04.362335 output:
290 05:01:04.363444 rename /var/lib/lava/dispatcher/tmp/965234/extract-overlay-ramdisk-p2sveqqo/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/ramdisk/ramdisk.cpio.gz.uboot
291 05:01:04.364195 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 05:01:04.364749 end: 1.6 prepare-tftp-overlay (duration 00:01:03) [common]
293 05:01:04.365308 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:39) [common]
294 05:01:04.365754 No LXC device requested
295 05:01:04.366251 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 05:01:04.366759 start: 1.8 deploy-device-env (timeout 00:08:39) [common]
297 05:01:04.367253 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 05:01:04.367664 Checking files for TFTP limit of 4294967296 bytes.
299 05:01:04.370373 end: 1 tftp-deploy (duration 00:01:21) [common]
300 05:01:04.370985 start: 2 uboot-action (timeout 00:05:00) [common]
301 05:01:04.371541 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 05:01:04.372099 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 05:01:04.372656 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 05:01:04.373211 Using kernel file from prepare-kernel: 965234/tftp-deploy-rwzvuebl/kernel/uImage
305 05:01:04.373863 substitutions:
306 05:01:04.374293 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 05:01:04.374717 - {DTB_ADDR}: 0x01070000
308 05:01:04.375132 - {DTB}: 965234/tftp-deploy-rwzvuebl/dtb/meson-g12b-a311d-libretech-cc.dtb
309 05:01:04.375557 - {INITRD}: 965234/tftp-deploy-rwzvuebl/ramdisk/ramdisk.cpio.gz.uboot
310 05:01:04.375973 - {KERNEL_ADDR}: 0x01080000
311 05:01:04.376476 - {KERNEL}: 965234/tftp-deploy-rwzvuebl/kernel/uImage
312 05:01:04.376893 - {LAVA_MAC}: None
313 05:01:04.377348 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/965234/extract-nfsrootfs-9k18tv_n
314 05:01:04.377769 - {NFS_SERVER_IP}: 192.168.6.2
315 05:01:04.378178 - {PRESEED_CONFIG}: None
316 05:01:04.378585 - {PRESEED_LOCAL}: None
317 05:01:04.378991 - {RAMDISK_ADDR}: 0x08000000
318 05:01:04.379392 - {RAMDISK}: 965234/tftp-deploy-rwzvuebl/ramdisk/ramdisk.cpio.gz.uboot
319 05:01:04.379808 - {ROOT_PART}: None
320 05:01:04.380277 - {ROOT}: None
321 05:01:04.380706 - {SERVER_IP}: 192.168.6.2
322 05:01:04.381129 - {TEE_ADDR}: 0x83000000
323 05:01:04.381554 - {TEE}: None
324 05:01:04.381976 Parsed boot commands:
325 05:01:04.382387 - setenv autoload no
326 05:01:04.382808 - setenv initrd_high 0xffffffff
327 05:01:04.383228 - setenv fdt_high 0xffffffff
328 05:01:04.383649 - dhcp
329 05:01:04.384112 - setenv serverip 192.168.6.2
330 05:01:04.384515 - tftpboot 0x01080000 965234/tftp-deploy-rwzvuebl/kernel/uImage
331 05:01:04.384908 - tftpboot 0x08000000 965234/tftp-deploy-rwzvuebl/ramdisk/ramdisk.cpio.gz.uboot
332 05:01:04.385301 - tftpboot 0x01070000 965234/tftp-deploy-rwzvuebl/dtb/meson-g12b-a311d-libretech-cc.dtb
333 05:01:04.385692 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/965234/extract-nfsrootfs-9k18tv_n,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 05:01:04.386094 - bootm 0x01080000 0x08000000 0x01070000
335 05:01:04.386615 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 05:01:04.388125 start: 2.3 connect-device (timeout 00:05:00) [common]
338 05:01:04.388552 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 05:01:04.404635 Setting prompt string to ['lava-test: # ']
340 05:01:04.406175 end: 2.3 connect-device (duration 00:00:00) [common]
341 05:01:04.406779 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 05:01:04.407363 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 05:01:04.407917 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 05:01:04.408758 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 05:01:04.444255 >> OK - accepted request
346 05:01:04.446384 Returned 0 in 0 seconds
347 05:01:04.547329 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 05:01:04.549079 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 05:01:04.549632 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 05:01:04.550143 Setting prompt string to ['Hit any key to stop autoboot']
352 05:01:04.550591 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 05:01:04.552211 Trying 192.168.56.21...
354 05:01:04.552705 Connected to conserv1.
355 05:01:04.553113 Escape character is '^]'.
356 05:01:04.553519
357 05:01:04.553930 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 05:01:04.554343
359 05:01:16.284844 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 05:01:16.285464 bl2_stage_init 0x01
361 05:01:16.285897 bl2_stage_init 0x81
362 05:01:16.290311 hw id: 0x0000 - pwm id 0x01
363 05:01:16.290826 bl2_stage_init 0xc1
364 05:01:16.291255 bl2_stage_init 0x02
365 05:01:16.291665
366 05:01:16.295846 L0:00000000
367 05:01:16.296338 L1:20000703
368 05:01:16.296751 L2:00008067
369 05:01:16.297146 L3:14000000
370 05:01:16.298761 B2:00402000
371 05:01:16.299193 B1:e0f83180
372 05:01:16.299585
373 05:01:16.299973 TE: 58124
374 05:01:16.300398
375 05:01:16.310017 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 05:01:16.310298
377 05:01:16.310507 Board ID = 1
378 05:01:16.310710 Set A53 clk to 24M
379 05:01:16.310909 Set A73 clk to 24M
380 05:01:16.315758 Set clk81 to 24M
381 05:01:16.316062 A53 clk: 1200 MHz
382 05:01:16.316281 A73 clk: 1200 MHz
383 05:01:16.319019 CLK81: 166.6M
384 05:01:16.319275 smccc: 00012a91
385 05:01:16.324564 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 05:01:16.330136 board id: 1
387 05:01:16.335307 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 05:01:16.346020 fw parse done
389 05:01:16.352015 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 05:01:16.394624 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 05:01:16.405529 PIEI prepare done
392 05:01:16.405856 fastboot data load
393 05:01:16.406075 fastboot data verify
394 05:01:16.412176 verify result: 266
395 05:01:16.416775 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 05:01:16.417275 LPDDR4 probe
397 05:01:16.417683 ddr clk to 1584MHz
398 05:01:16.424691 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 05:01:16.461991
400 05:01:16.462558 dmc_version 0001
401 05:01:16.468584 Check phy result
402 05:01:16.474434 INFO : End of CA training
403 05:01:16.474930 INFO : End of initialization
404 05:01:16.480030 INFO : Training has run successfully!
405 05:01:16.480533 Check phy result
406 05:01:16.485631 INFO : End of initialization
407 05:01:16.486110 INFO : End of read enable training
408 05:01:16.491331 INFO : End of fine write leveling
409 05:01:16.496799 INFO : End of Write leveling coarse delay
410 05:01:16.497251 INFO : Training has run successfully!
411 05:01:16.497652 Check phy result
412 05:01:16.502456 INFO : End of initialization
413 05:01:16.502954 INFO : End of read dq deskew training
414 05:01:16.508020 INFO : End of MPR read delay center optimization
415 05:01:16.513576 INFO : End of write delay center optimization
416 05:01:16.519179 INFO : End of read delay center optimization
417 05:01:16.519692 INFO : End of max read latency training
418 05:01:16.524800 INFO : Training has run successfully!
419 05:01:16.525284 1D training succeed
420 05:01:16.533998 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 05:01:16.581624 Check phy result
422 05:01:16.582164 INFO : End of initialization
423 05:01:16.604208 INFO : End of 2D read delay Voltage center optimization
424 05:01:16.624611 INFO : End of 2D read delay Voltage center optimization
425 05:01:16.676612 INFO : End of 2D write delay Voltage center optimization
426 05:01:16.725928 INFO : End of 2D write delay Voltage center optimization
427 05:01:16.731573 INFO : Training has run successfully!
428 05:01:16.731894
429 05:01:16.732164 channel==0
430 05:01:16.737060 RxClkDly_Margin_A0==78 ps 8
431 05:01:16.737371 TxDqDly_Margin_A0==98 ps 10
432 05:01:16.742679 RxClkDly_Margin_A1==78 ps 8
433 05:01:16.742985 TxDqDly_Margin_A1==98 ps 10
434 05:01:16.743205 TrainedVREFDQ_A0==74
435 05:01:16.748252 TrainedVREFDQ_A1==74
436 05:01:16.748559 VrefDac_Margin_A0==25
437 05:01:16.748777 DeviceVref_Margin_A0==40
438 05:01:16.753855 VrefDac_Margin_A1==25
439 05:01:16.754158 DeviceVref_Margin_A1==40
440 05:01:16.754378
441 05:01:16.754587
442 05:01:16.759662 channel==1
443 05:01:16.759967 RxClkDly_Margin_A0==98 ps 10
444 05:01:16.760217 TxDqDly_Margin_A0==88 ps 9
445 05:01:16.764971 RxClkDly_Margin_A1==98 ps 10
446 05:01:16.765287 TxDqDly_Margin_A1==88 ps 9
447 05:01:16.770594 TrainedVREFDQ_A0==76
448 05:01:16.770901 TrainedVREFDQ_A1==77
449 05:01:16.771116 VrefDac_Margin_A0==22
450 05:01:16.776234 DeviceVref_Margin_A0==38
451 05:01:16.776548 VrefDac_Margin_A1==22
452 05:01:16.781766 DeviceVref_Margin_A1==37
453 05:01:16.782081
454 05:01:16.782305 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 05:01:16.782518
456 05:01:16.815559 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 05:01:16.816199 2D training succeed
458 05:01:16.821034 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 05:01:16.826528 auto size-- 65535DDR cs0 size: 2048MB
460 05:01:16.827017 DDR cs1 size: 2048MB
461 05:01:16.832164 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 05:01:16.832645 cs0 DataBus test pass
463 05:01:16.837766 cs1 DataBus test pass
464 05:01:16.838241 cs0 AddrBus test pass
465 05:01:16.838642 cs1 AddrBus test pass
466 05:01:16.839036
467 05:01:16.843406 100bdlr_step_size ps== 420
468 05:01:16.843892 result report
469 05:01:16.848956 boot times 0Enable ddr reg access
470 05:01:16.854281 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 05:01:16.867763 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 05:01:17.441669 0.0;M3 CHK:0;cm4_sp_mode 0
473 05:01:17.442265 MVN_1=0x00000000
474 05:01:17.446894 MVN_2=0x00000000
475 05:01:17.452680 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 05:01:17.453267 OPS=0x10
477 05:01:17.453691 ring efuse init
478 05:01:17.454089 chipver efuse init
479 05:01:17.458364 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 05:01:17.463854 [0.018961 Inits done]
481 05:01:17.464478 secure task start!
482 05:01:17.464934 high task start!
483 05:01:17.468496 low task start!
484 05:01:17.468936 run into bl31
485 05:01:17.475145 NOTICE: BL31: v1.3(release):4fc40b1
486 05:01:17.483019 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 05:01:17.483520 NOTICE: BL31: G12A normal boot!
488 05:01:17.509417 NOTICE: BL31: BL33 decompress pass
489 05:01:17.514070 ERROR: Error initializing runtime service opteed_fast
490 05:01:18.747017
491 05:01:18.747604
492 05:01:18.755347 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 05:01:18.755913
494 05:01:18.756411 Model: Libre Computer AML-A311D-CC Alta
495 05:01:18.963887 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 05:01:18.987193 DRAM: 2 GiB (effective 3.8 GiB)
497 05:01:19.130213 Core: 408 devices, 31 uclasses, devicetree: separate
498 05:01:19.136085 WDT: Not starting watchdog@f0d0
499 05:01:19.168314 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 05:01:19.180743 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 05:01:19.185832 ** Bad device specification mmc 0 **
502 05:01:19.196094 Card did not respond to voltage select! : -110
503 05:01:19.203758 ** Bad device specification mmc 0 **
504 05:01:19.204341 Couldn't find partition mmc 0
505 05:01:19.212093 Card did not respond to voltage select! : -110
506 05:01:19.217585 ** Bad device specification mmc 0 **
507 05:01:19.218130 Couldn't find partition mmc 0
508 05:01:19.222666 Error: could not access storage.
509 05:01:20.485003 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 05:01:20.485418 bl2_stage_init 0x01
511 05:01:20.485647 bl2_stage_init 0x81
512 05:01:20.490621 hw id: 0x0000 - pwm id 0x01
513 05:01:20.490913 bl2_stage_init 0xc1
514 05:01:20.491135 bl2_stage_init 0x02
515 05:01:20.491347
516 05:01:20.496128 L0:00000000
517 05:01:20.496418 L1:20000703
518 05:01:20.496628 L2:00008067
519 05:01:20.496835 L3:14000000
520 05:01:20.501851 B2:00402000
521 05:01:20.502145 B1:e0f83180
522 05:01:20.502357
523 05:01:20.502561 TE: 58124
524 05:01:20.502766
525 05:01:20.507344 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 05:01:20.507643
527 05:01:20.507855 Board ID = 1
528 05:01:20.512936 Set A53 clk to 24M
529 05:01:20.513226 Set A73 clk to 24M
530 05:01:20.513439 Set clk81 to 24M
531 05:01:20.518583 A53 clk: 1200 MHz
532 05:01:20.518868 A73 clk: 1200 MHz
533 05:01:20.519083 CLK81: 166.6M
534 05:01:20.519294 smccc: 00012a92
535 05:01:20.524131 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 05:01:20.529834 board id: 1
537 05:01:20.535661 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 05:01:20.546292 fw parse done
539 05:01:20.552273 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 05:01:20.594940 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 05:01:20.605913 PIEI prepare done
542 05:01:20.606251 fastboot data load
543 05:01:20.606468 fastboot data verify
544 05:01:20.611356 verify result: 266
545 05:01:20.616963 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 05:01:20.617237 LPDDR4 probe
547 05:01:20.617446 ddr clk to 1584MHz
548 05:01:20.624938 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 05:01:20.662233
550 05:01:20.662559 dmc_version 0001
551 05:01:20.668945 Check phy result
552 05:01:20.674861 INFO : End of CA training
553 05:01:20.675135 INFO : End of initialization
554 05:01:20.680345 INFO : Training has run successfully!
555 05:01:20.680624 Check phy result
556 05:01:20.685945 INFO : End of initialization
557 05:01:20.686223 INFO : End of read enable training
558 05:01:20.691613 INFO : End of fine write leveling
559 05:01:20.697117 INFO : End of Write leveling coarse delay
560 05:01:20.697397 INFO : Training has run successfully!
561 05:01:20.697609 Check phy result
562 05:01:20.702963 INFO : End of initialization
563 05:01:20.703495 INFO : End of read dq deskew training
564 05:01:20.708367 INFO : End of MPR read delay center optimization
565 05:01:20.713933 INFO : End of write delay center optimization
566 05:01:20.719599 INFO : End of read delay center optimization
567 05:01:20.720077 INFO : End of max read latency training
568 05:01:20.725136 INFO : Training has run successfully!
569 05:01:20.725570 1D training succeed
570 05:01:20.734320 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 05:01:20.782100 Check phy result
572 05:01:20.782655 INFO : End of initialization
573 05:01:20.803756 INFO : End of 2D read delay Voltage center optimization
574 05:01:20.824518 INFO : End of 2D read delay Voltage center optimization
575 05:01:20.876084 INFO : End of 2D write delay Voltage center optimization
576 05:01:20.925438 INFO : End of 2D write delay Voltage center optimization
577 05:01:20.931070 INFO : Training has run successfully!
578 05:01:20.931528
579 05:01:20.931935 channel==0
580 05:01:20.936664 RxClkDly_Margin_A0==88 ps 9
581 05:01:20.937122 TxDqDly_Margin_A0==98 ps 10
582 05:01:20.940066 RxClkDly_Margin_A1==88 ps 9
583 05:01:20.940520 TxDqDly_Margin_A1==98 ps 10
584 05:01:20.945612 TrainedVREFDQ_A0==74
585 05:01:20.946071 TrainedVREFDQ_A1==75
586 05:01:20.946476 VrefDac_Margin_A0==25
587 05:01:20.951207 DeviceVref_Margin_A0==40
588 05:01:20.951663 VrefDac_Margin_A1==25
589 05:01:20.956751 DeviceVref_Margin_A1==39
590 05:01:20.957226
591 05:01:20.957634
592 05:01:20.958032 channel==1
593 05:01:20.958422 RxClkDly_Margin_A0==98 ps 10
594 05:01:20.960160 TxDqDly_Margin_A0==98 ps 10
595 05:01:20.965758 RxClkDly_Margin_A1==98 ps 10
596 05:01:20.966216 TxDqDly_Margin_A1==88 ps 9
597 05:01:20.966619 TrainedVREFDQ_A0==77
598 05:01:20.971202 TrainedVREFDQ_A1==77
599 05:01:20.971646 VrefDac_Margin_A0==22
600 05:01:20.976885 DeviceVref_Margin_A0==37
601 05:01:20.977328 VrefDac_Margin_A1==22
602 05:01:20.977720 DeviceVref_Margin_A1==37
603 05:01:20.978110
604 05:01:20.982354 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 05:01:20.982790
606 05:01:21.016020 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 05:01:21.016554 2D training succeed
608 05:01:21.021718 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 05:01:21.027250 auto size-- 65535DDR cs0 size: 2048MB
610 05:01:21.027718 DDR cs1 size: 2048MB
611 05:01:21.032946 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 05:01:21.033406 cs0 DataBus test pass
613 05:01:21.033815 cs1 DataBus test pass
614 05:01:21.038391 cs0 AddrBus test pass
615 05:01:21.038832 cs1 AddrBus test pass
616 05:01:21.039227
617 05:01:21.043948 100bdlr_step_size ps== 420
618 05:01:21.044435 result report
619 05:01:21.044838 boot times 0Enable ddr reg access
620 05:01:21.053996 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 05:01:21.067489 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 05:01:21.641202 0.0;M3 CHK:0;cm4_sp_mode 0
623 05:01:21.641840 MVN_1=0x00000000
624 05:01:21.646591 MVN_2=0x00000000
625 05:01:21.652346 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 05:01:21.652837 OPS=0x10
627 05:01:21.653238 ring efuse init
628 05:01:21.653631 chipver efuse init
629 05:01:21.660547 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 05:01:21.661019 [0.018961 Inits done]
631 05:01:21.668138 secure task start!
632 05:01:21.668584 high task start!
633 05:01:21.668972 low task start!
634 05:01:21.669359 run into bl31
635 05:01:21.674741 NOTICE: BL31: v1.3(release):4fc40b1
636 05:01:21.682525 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 05:01:21.682954 NOTICE: BL31: G12A normal boot!
638 05:01:21.707855 NOTICE: BL31: BL33 decompress pass
639 05:01:21.713523 ERROR: Error initializing runtime service opteed_fast
640 05:01:22.946651
641 05:01:22.947073
642 05:01:22.955087 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 05:01:22.955548
644 05:01:22.955890 Model: Libre Computer AML-A311D-CC Alta
645 05:01:23.163577 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 05:01:23.186968 DRAM: 2 GiB (effective 3.8 GiB)
647 05:01:23.329876 Core: 408 devices, 31 uclasses, devicetree: separate
648 05:01:23.335760 WDT: Not starting watchdog@f0d0
649 05:01:23.368040 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 05:01:23.380335 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 05:01:23.384445 ** Bad device specification mmc 0 **
652 05:01:23.395726 Card did not respond to voltage select! : -110
653 05:01:23.403462 ** Bad device specification mmc 0 **
654 05:01:23.403945 Couldn't find partition mmc 0
655 05:01:23.411691 Card did not respond to voltage select! : -110
656 05:01:23.417479 ** Bad device specification mmc 0 **
657 05:01:23.417835 Couldn't find partition mmc 0
658 05:01:23.422245 Error: could not access storage.
659 05:01:23.765887 Net: eth0: ethernet@ff3f0000
660 05:01:23.766307 starting USB...
661 05:01:24.017660 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 05:01:24.018093 Starting the controller
663 05:01:24.024780 USB XHCI 1.10
664 05:01:25.735284 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 05:01:25.735887 bl2_stage_init 0x01
666 05:01:25.736197 bl2_stage_init 0x81
667 05:01:25.740929 hw id: 0x0000 - pwm id 0x01
668 05:01:25.741239 bl2_stage_init 0xc1
669 05:01:25.741459 bl2_stage_init 0x02
670 05:01:25.741669
671 05:01:25.746475 L0:00000000
672 05:01:25.746791 L1:20000703
673 05:01:25.747009 L2:00008067
674 05:01:25.747216 L3:14000000
675 05:01:25.749472 B2:00402000
676 05:01:25.749776 B1:e0f83180
677 05:01:25.749996
678 05:01:25.750216 TE: 58159
679 05:01:25.750424
680 05:01:25.760624 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 05:01:25.761001
682 05:01:25.761225 Board ID = 1
683 05:01:25.761435 Set A53 clk to 24M
684 05:01:25.761640 Set A73 clk to 24M
685 05:01:25.766272 Set clk81 to 24M
686 05:01:25.766602 A53 clk: 1200 MHz
687 05:01:25.766820 A73 clk: 1200 MHz
688 05:01:25.771710 CLK81: 166.6M
689 05:01:25.772042 smccc: 00012ab5
690 05:01:25.777390 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 05:01:25.777709 board id: 1
692 05:01:25.786232 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 05:01:25.796696 fw parse done
694 05:01:25.802520 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 05:01:25.845292 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 05:01:25.856077 PIEI prepare done
697 05:01:25.856431 fastboot data load
698 05:01:25.856655 fastboot data verify
699 05:01:25.861698 verify result: 266
700 05:01:25.867252 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 05:01:25.867579 LPDDR4 probe
702 05:01:25.867795 ddr clk to 1584MHz
703 05:01:25.875251 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 05:01:25.912550
705 05:01:25.912926 dmc_version 0001
706 05:01:25.919248 Check phy result
707 05:01:25.925087 INFO : End of CA training
708 05:01:25.925557 INFO : End of initialization
709 05:01:25.930682 INFO : Training has run successfully!
710 05:01:25.930993 Check phy result
711 05:01:25.936287 INFO : End of initialization
712 05:01:25.936763 INFO : End of read enable training
713 05:01:25.941869 INFO : End of fine write leveling
714 05:01:25.947493 INFO : End of Write leveling coarse delay
715 05:01:25.947828 INFO : Training has run successfully!
716 05:01:25.948075 Check phy result
717 05:01:25.953116 INFO : End of initialization
718 05:01:25.953444 INFO : End of read dq deskew training
719 05:01:25.958699 INFO : End of MPR read delay center optimization
720 05:01:25.964224 INFO : End of write delay center optimization
721 05:01:25.969901 INFO : End of read delay center optimization
722 05:01:25.970227 INFO : End of max read latency training
723 05:01:25.975510 INFO : Training has run successfully!
724 05:01:25.976020 1D training succeed
725 05:01:25.984792 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 05:01:26.032419 Check phy result
727 05:01:26.032828 INFO : End of initialization
728 05:01:26.054945 INFO : End of 2D read delay Voltage center optimization
729 05:01:26.074908 INFO : End of 2D read delay Voltage center optimization
730 05:01:26.126924 INFO : End of 2D write delay Voltage center optimization
731 05:01:26.176090 INFO : End of 2D write delay Voltage center optimization
732 05:01:26.181605 INFO : Training has run successfully!
733 05:01:26.182095
734 05:01:26.182349 channel==0
735 05:01:26.187196 RxClkDly_Margin_A0==88 ps 9
736 05:01:26.187510 TxDqDly_Margin_A0==98 ps 10
737 05:01:26.190497 RxClkDly_Margin_A1==78 ps 8
738 05:01:26.190905 TxDqDly_Margin_A1==98 ps 10
739 05:01:26.196031 TrainedVREFDQ_A0==74
740 05:01:26.196464 TrainedVREFDQ_A1==74
741 05:01:26.201642 VrefDac_Margin_A0==25
742 05:01:26.202000 DeviceVref_Margin_A0==40
743 05:01:26.202223 VrefDac_Margin_A1==26
744 05:01:26.207185 DeviceVref_Margin_A1==40
745 05:01:26.207498
746 05:01:26.207720
747 05:01:26.207942 channel==1
748 05:01:26.208194 RxClkDly_Margin_A0==98 ps 10
749 05:01:26.212787 TxDqDly_Margin_A0==88 ps 9
750 05:01:26.213095 RxClkDly_Margin_A1==98 ps 10
751 05:01:26.218384 TxDqDly_Margin_A1==88 ps 9
752 05:01:26.218685 TrainedVREFDQ_A0==77
753 05:01:26.218899 TrainedVREFDQ_A1==77
754 05:01:26.223914 VrefDac_Margin_A0==22
755 05:01:26.224229 DeviceVref_Margin_A0==37
756 05:01:26.229573 VrefDac_Margin_A1==22
757 05:01:26.230095 DeviceVref_Margin_A1==37
758 05:01:26.230474
759 05:01:26.235169 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 05:01:26.235479
761 05:01:26.263148 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 05:01:26.268765 2D training succeed
763 05:01:26.274324 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 05:01:26.274636 auto size-- 65535DDR cs0 size: 2048MB
765 05:01:26.279955 DDR cs1 size: 2048MB
766 05:01:26.280404 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 05:01:26.285578 cs0 DataBus test pass
768 05:01:26.285951 cs1 DataBus test pass
769 05:01:26.286185 cs0 AddrBus test pass
770 05:01:26.291158 cs1 AddrBus test pass
771 05:01:26.291598
772 05:01:26.291941 100bdlr_step_size ps== 420
773 05:01:26.292328 result report
774 05:01:26.296738 boot times 0Enable ddr reg access
775 05:01:26.304480 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 05:01:26.317915 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 05:01:26.889968 0.0;M3 CHK:0;cm4_sp_mode 0
778 05:01:26.890424 MVN_1=0x00000000
779 05:01:26.895367 MVN_2=0x00000000
780 05:01:26.901103 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 05:01:26.901466 OPS=0x10
782 05:01:26.901712 ring efuse init
783 05:01:26.901944 chipver efuse init
784 05:01:26.906755 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 05:01:26.912310 [0.018961 Inits done]
786 05:01:26.912636 secure task start!
787 05:01:26.912870 high task start!
788 05:01:26.916152 low task start!
789 05:01:26.916478 run into bl31
790 05:01:26.923588 NOTICE: BL31: v1.3(release):4fc40b1
791 05:01:26.930721 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 05:01:26.931078 NOTICE: BL31: G12A normal boot!
793 05:01:26.956807 NOTICE: BL31: BL33 decompress pass
794 05:01:26.961968 ERROR: Error initializing runtime service opteed_fast
795 05:01:28.195364
796 05:01:28.195804
797 05:01:28.203734 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 05:01:28.204098
799 05:01:28.204346 Model: Libre Computer AML-A311D-CC Alta
800 05:01:28.411679 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 05:01:28.434805 DRAM: 2 GiB (effective 3.8 GiB)
802 05:01:28.578618 Core: 408 devices, 31 uclasses, devicetree: separate
803 05:01:28.583552 WDT: Not starting watchdog@f0d0
804 05:01:28.616817 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 05:01:28.629199 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 05:01:28.633365 ** Bad device specification mmc 0 **
807 05:01:28.644521 Card did not respond to voltage select! : -110
808 05:01:28.651384 ** Bad device specification mmc 0 **
809 05:01:28.651792 Couldn't find partition mmc 0
810 05:01:28.660503 Card did not respond to voltage select! : -110
811 05:01:28.666028 ** Bad device specification mmc 0 **
812 05:01:28.666414 Couldn't find partition mmc 0
813 05:01:28.671124 Error: could not access storage.
814 05:01:29.013191 Net: eth0: ethernet@ff3f0000
815 05:01:29.013758 starting USB...
816 05:01:29.265422 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 05:01:29.265869 Starting the controller
818 05:01:29.272151 USB XHCI 1.10
819 05:01:31.437340 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 05:01:31.437946 bl2_stage_init 0x01
821 05:01:31.438225 bl2_stage_init 0x81
822 05:01:31.442682 hw id: 0x0000 - pwm id 0x01
823 05:01:31.443011 bl2_stage_init 0xc1
824 05:01:31.443249 bl2_stage_init 0x02
825 05:01:31.443493
826 05:01:31.448217 L0:00000000
827 05:01:31.448525 L1:20000703
828 05:01:31.448759 L2:00008067
829 05:01:31.448990 L3:14000000
830 05:01:31.451174 B2:00402000
831 05:01:31.451461 B1:e0f83180
832 05:01:31.451695
833 05:01:31.451931 TE: 58167
834 05:01:31.452200
835 05:01:31.462228 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 05:01:31.462564
837 05:01:31.462807 Board ID = 1
838 05:01:31.463038 Set A53 clk to 24M
839 05:01:31.463265 Set A73 clk to 24M
840 05:01:31.467803 Set clk81 to 24M
841 05:01:31.468143 A53 clk: 1200 MHz
842 05:01:31.468381 A73 clk: 1200 MHz
843 05:01:31.471628 CLK81: 166.6M
844 05:01:31.471929 smccc: 00012abd
845 05:01:31.477198 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 05:01:31.477523 board id: 1
847 05:01:31.487512 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 05:01:31.498294 fw parse done
849 05:01:31.503395 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 05:01:31.546535 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 05:01:31.557835 PIEI prepare done
852 05:01:31.558399 fastboot data load
853 05:01:31.558685 fastboot data verify
854 05:01:31.563249 verify result: 266
855 05:01:31.568927 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 05:01:31.569286 LPDDR4 probe
857 05:01:31.569537 ddr clk to 1584MHz
858 05:01:31.576879 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 05:01:31.614513
860 05:01:31.615164 dmc_version 0001
861 05:01:31.620918 Check phy result
862 05:01:31.626677 INFO : End of CA training
863 05:01:31.627183 INFO : End of initialization
864 05:01:31.632350 INFO : Training has run successfully!
865 05:01:31.632858 Check phy result
866 05:01:31.637942 INFO : End of initialization
867 05:01:31.638510 INFO : End of read enable training
868 05:01:31.643549 INFO : End of fine write leveling
869 05:01:31.649118 INFO : End of Write leveling coarse delay
870 05:01:31.649651 INFO : Training has run successfully!
871 05:01:31.650120 Check phy result
872 05:01:31.654666 INFO : End of initialization
873 05:01:31.655184 INFO : End of read dq deskew training
874 05:01:31.660294 INFO : End of MPR read delay center optimization
875 05:01:31.665898 INFO : End of write delay center optimization
876 05:01:31.671528 INFO : End of read delay center optimization
877 05:01:31.672085 INFO : End of max read latency training
878 05:01:31.677116 INFO : Training has run successfully!
879 05:01:31.677631 1D training succeed
880 05:01:31.686415 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 05:01:31.734005 Check phy result
882 05:01:31.734636 INFO : End of initialization
883 05:01:31.756624 INFO : End of 2D read delay Voltage center optimization
884 05:01:31.776059 INFO : End of 2D read delay Voltage center optimization
885 05:01:31.829058 INFO : End of 2D write delay Voltage center optimization
886 05:01:31.878378 INFO : End of 2D write delay Voltage center optimization
887 05:01:31.883912 INFO : Training has run successfully!
888 05:01:31.884503
889 05:01:31.884971 channel==0
890 05:01:31.889533 RxClkDly_Margin_A0==88 ps 9
891 05:01:31.890094 TxDqDly_Margin_A0==98 ps 10
892 05:01:31.893562 RxClkDly_Margin_A1==88 ps 9
893 05:01:31.894100 TxDqDly_Margin_A1==98 ps 10
894 05:01:31.898519 TrainedVREFDQ_A0==74
895 05:01:31.899091 TrainedVREFDQ_A1==74
896 05:01:31.903804 VrefDac_Margin_A0==24
897 05:01:31.904380 DeviceVref_Margin_A0==40
898 05:01:31.904818 VrefDac_Margin_A1==25
899 05:01:31.909399 DeviceVref_Margin_A1==40
900 05:01:31.909911
901 05:01:31.910349
902 05:01:31.910783 channel==1
903 05:01:31.911213 RxClkDly_Margin_A0==98 ps 10
904 05:01:31.913822 TxDqDly_Margin_A0==88 ps 9
905 05:01:31.919357 RxClkDly_Margin_A1==98 ps 10
906 05:01:31.919866 TxDqDly_Margin_A1==88 ps 9
907 05:01:31.920353 TrainedVREFDQ_A0==76
908 05:01:31.924961 TrainedVREFDQ_A1==77
909 05:01:31.925473 VrefDac_Margin_A0==23
910 05:01:31.925905 DeviceVref_Margin_A0==38
911 05:01:31.930452 VrefDac_Margin_A1==24
912 05:01:31.930958 DeviceVref_Margin_A1==37
913 05:01:31.931391
914 05:01:31.936228 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 05:01:31.936762
916 05:01:31.969577 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
917 05:01:31.970176 2D training succeed
918 05:01:31.975209 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 05:01:31.980802 auto size-- 65535DDR cs0 size: 2048MB
920 05:01:31.981322 DDR cs1 size: 2048MB
921 05:01:31.986370 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 05:01:31.986876 cs0 DataBus test pass
923 05:01:31.987305 cs1 DataBus test pass
924 05:01:31.991965 cs0 AddrBus test pass
925 05:01:31.992506 cs1 AddrBus test pass
926 05:01:31.992942
927 05:01:31.993375 100bdlr_step_size ps== 420
928 05:01:31.997587 result report
929 05:01:31.998101 boot times 0Enable ddr reg access
930 05:01:32.006647 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 05:01:32.020072 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 05:01:32.593667 0.0;M3 CHK:0;cm4_sp_mode 0
933 05:01:32.594089 MVN_1=0x00000000
934 05:01:32.599118 MVN_2=0x00000000
935 05:01:32.604902 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 05:01:32.605219 OPS=0x10
937 05:01:32.605438 ring efuse init
938 05:01:32.605647 chipver efuse init
939 05:01:32.610508 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 05:01:32.616142 [0.018961 Inits done]
941 05:01:32.616461 secure task start!
942 05:01:32.616676 high task start!
943 05:01:32.620832 low task start!
944 05:01:32.621145 run into bl31
945 05:01:32.627311 NOTICE: BL31: v1.3(release):4fc40b1
946 05:01:32.635147 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 05:01:32.635536 NOTICE: BL31: G12A normal boot!
948 05:01:32.660656 NOTICE: BL31: BL33 decompress pass
949 05:01:32.666208 ERROR: Error initializing runtime service opteed_fast
950 05:01:33.899147
951 05:01:33.899593
952 05:01:33.907548 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 05:01:33.908196
954 05:01:33.908549 Model: Libre Computer AML-A311D-CC Alta
955 05:01:34.116038 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 05:01:34.139444 DRAM: 2 GiB (effective 3.8 GiB)
957 05:01:34.282591 Core: 408 devices, 31 uclasses, devicetree: separate
958 05:01:34.288198 WDT: Not starting watchdog@f0d0
959 05:01:34.320785 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 05:01:34.332928 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 05:01:34.337381 ** Bad device specification mmc 0 **
962 05:01:34.348271 Card did not respond to voltage select! : -110
963 05:01:34.355328 ** Bad device specification mmc 0 **
964 05:01:34.355787 Couldn't find partition mmc 0
965 05:01:34.364277 Card did not respond to voltage select! : -110
966 05:01:34.369870 ** Bad device specification mmc 0 **
967 05:01:34.370303 Couldn't find partition mmc 0
968 05:01:34.374982 Error: could not access storage.
969 05:01:34.718433 Net: eth0: ethernet@ff3f0000
970 05:01:34.719135 starting USB...
971 05:01:34.970307 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 05:01:34.971313 Starting the controller
973 05:01:34.977038 USB XHCI 1.10
974 05:01:36.836675 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 05:01:36.837292 bl2_stage_init 0x01
976 05:01:36.837571 bl2_stage_init 0x81
977 05:01:36.842271 hw id: 0x0000 - pwm id 0x01
978 05:01:36.842680 bl2_stage_init 0xc1
979 05:01:36.842916 bl2_stage_init 0x02
980 05:01:36.843146
981 05:01:36.847869 L0:00000000
982 05:01:36.848496 L1:20000703
983 05:01:36.848780 L2:00008067
984 05:01:36.848998 L3:14000000
985 05:01:36.853499 B2:00402000
986 05:01:36.853885 B1:e0f83180
987 05:01:36.854118
988 05:01:36.854351 TE: 58124
989 05:01:36.854577
990 05:01:36.859150 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 05:01:36.859536
992 05:01:36.859768 Board ID = 1
993 05:01:36.864645 Set A53 clk to 24M
994 05:01:36.865021 Set A73 clk to 24M
995 05:01:36.865244 Set clk81 to 24M
996 05:01:36.870246 A53 clk: 1200 MHz
997 05:01:36.870620 A73 clk: 1200 MHz
998 05:01:36.870845 CLK81: 166.6M
999 05:01:36.871053 smccc: 00012a92
1000 05:01:36.875921 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 05:01:36.881458 board id: 1
1002 05:01:36.887321 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 05:01:36.898125 fw parse done
1004 05:01:36.903888 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 05:01:36.946537 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 05:01:36.957522 PIEI prepare done
1007 05:01:36.957885 fastboot data load
1008 05:01:36.958121 fastboot data verify
1009 05:01:36.963425 verify result: 266
1010 05:01:36.969016 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 05:01:36.969347 LPDDR4 probe
1012 05:01:36.969575 ddr clk to 1584MHz
1013 05:01:36.976859 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 05:01:37.014244
1015 05:01:37.014630 dmc_version 0001
1016 05:01:37.020809 Check phy result
1017 05:01:37.026860 INFO : End of CA training
1018 05:01:37.027233 INFO : End of initialization
1019 05:01:37.032490 INFO : Training has run successfully!
1020 05:01:37.032853 Check phy result
1021 05:01:37.037961 INFO : End of initialization
1022 05:01:37.038348 INFO : End of read enable training
1023 05:01:37.043699 INFO : End of fine write leveling
1024 05:01:37.049425 INFO : End of Write leveling coarse delay
1025 05:01:37.050067 INFO : Training has run successfully!
1026 05:01:37.050557 Check phy result
1027 05:01:37.054871 INFO : End of initialization
1028 05:01:37.055463 INFO : End of read dq deskew training
1029 05:01:37.060690 INFO : End of MPR read delay center optimization
1030 05:01:37.065843 INFO : End of write delay center optimization
1031 05:01:37.071461 INFO : End of read delay center optimization
1032 05:01:37.072064 INFO : End of max read latency training
1033 05:01:37.077016 INFO : Training has run successfully!
1034 05:01:37.077571 1D training succeed
1035 05:01:37.086283 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 05:01:37.133845 Check phy result
1037 05:01:37.134437 INFO : End of initialization
1038 05:01:37.155551 INFO : End of 2D read delay Voltage center optimization
1039 05:01:37.175784 INFO : End of 2D read delay Voltage center optimization
1040 05:01:37.227809 INFO : End of 2D write delay Voltage center optimization
1041 05:01:37.277335 INFO : End of 2D write delay Voltage center optimization
1042 05:01:37.282739 INFO : Training has run successfully!
1043 05:01:37.283295
1044 05:01:37.283772 channel==0
1045 05:01:37.288331 RxClkDly_Margin_A0==88 ps 9
1046 05:01:37.288878 TxDqDly_Margin_A0==98 ps 10
1047 05:01:37.293960 RxClkDly_Margin_A1==88 ps 9
1048 05:01:37.294507 TxDqDly_Margin_A1==98 ps 10
1049 05:01:37.294978 TrainedVREFDQ_A0==74
1050 05:01:37.299569 TrainedVREFDQ_A1==74
1051 05:01:37.300159 VrefDac_Margin_A0==25
1052 05:01:37.300628 DeviceVref_Margin_A0==40
1053 05:01:37.305134 VrefDac_Margin_A1==25
1054 05:01:37.305680 DeviceVref_Margin_A1==40
1055 05:01:37.306142
1056 05:01:37.306600
1057 05:01:37.310760 channel==1
1058 05:01:37.311317 RxClkDly_Margin_A0==88 ps 9
1059 05:01:37.311784 TxDqDly_Margin_A0==98 ps 10
1060 05:01:37.316368 RxClkDly_Margin_A1==98 ps 10
1061 05:01:37.316936 TxDqDly_Margin_A1==108 ps 11
1062 05:01:37.321986 TrainedVREFDQ_A0==77
1063 05:01:37.322549 TrainedVREFDQ_A1==78
1064 05:01:37.323014 VrefDac_Margin_A0==22
1065 05:01:37.327548 DeviceVref_Margin_A0==37
1066 05:01:37.328140 VrefDac_Margin_A1==22
1067 05:01:37.333144 DeviceVref_Margin_A1==36
1068 05:01:37.333695
1069 05:01:37.334160 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 05:01:37.338759
1071 05:01:37.366670 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 05:01:37.367305 2D training succeed
1073 05:01:37.372371 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 05:01:37.377978 auto size-- 65535DDR cs0 size: 2048MB
1075 05:01:37.378564 DDR cs1 size: 2048MB
1076 05:01:37.383557 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 05:01:37.384162 cs0 DataBus test pass
1078 05:01:37.389162 cs1 DataBus test pass
1079 05:01:37.389730 cs0 AddrBus test pass
1080 05:01:37.390196 cs1 AddrBus test pass
1081 05:01:37.390653
1082 05:01:37.394788 100bdlr_step_size ps== 420
1083 05:01:37.395372 result report
1084 05:01:37.400392 boot times 0Enable ddr reg access
1085 05:01:37.405894 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 05:01:37.419394 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 05:01:37.993212 0.0;M3 CHK:0;cm4_sp_mode 0
1088 05:01:37.993860 MVN_1=0x00000000
1089 05:01:37.998512 MVN_2=0x00000000
1090 05:01:38.004339 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 05:01:38.004884 OPS=0x10
1092 05:01:38.005350 ring efuse init
1093 05:01:38.005797 chipver efuse init
1094 05:01:38.009837 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 05:01:38.015454 [0.018961 Inits done]
1096 05:01:38.016035 secure task start!
1097 05:01:38.016521 high task start!
1098 05:01:38.020097 low task start!
1099 05:01:38.020649 run into bl31
1100 05:01:38.026741 NOTICE: BL31: v1.3(release):4fc40b1
1101 05:01:38.034515 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 05:01:38.035079 NOTICE: BL31: G12A normal boot!
1103 05:01:38.060093 NOTICE: BL31: BL33 decompress pass
1104 05:01:38.065551 ERROR: Error initializing runtime service opteed_fast
1105 05:01:39.298369
1106 05:01:39.298796
1107 05:01:39.306803 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 05:01:39.307295
1109 05:01:39.307641 Model: Libre Computer AML-A311D-CC Alta
1110 05:01:39.515647 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 05:01:39.538658 DRAM: 2 GiB (effective 3.8 GiB)
1112 05:01:39.681932 Core: 408 devices, 31 uclasses, devicetree: separate
1113 05:01:39.687420 WDT: Not starting watchdog@f0d0
1114 05:01:39.719833 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 05:01:39.732335 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 05:01:39.738165 ** Bad device specification mmc 0 **
1117 05:01:39.747613 Card did not respond to voltage select! : -110
1118 05:01:39.755186 ** Bad device specification mmc 0 **
1119 05:01:39.755698 Couldn't find partition mmc 0
1120 05:01:39.763612 Card did not respond to voltage select! : -110
1121 05:01:39.769128 ** Bad device specification mmc 0 **
1122 05:01:39.769719 Couldn't find partition mmc 0
1123 05:01:39.774124 Error: could not access storage.
1124 05:01:40.116572 Net: eth0: ethernet@ff3f0000
1125 05:01:40.117232 starting USB...
1126 05:01:40.368465 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 05:01:40.369096 Starting the controller
1128 05:01:40.376060 USB XHCI 1.10
1129 05:01:41.929371 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 05:01:41.937762 scanning usb for storage devices... 0 Storage Device(s) found
1132 05:01:41.989496 Hit any key to stop autoboot: 1
1133 05:01:41.990402 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 05:01:41.991199 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1135 05:01:41.991719 Setting prompt string to ['=>']
1136 05:01:41.992316 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1137 05:01:42.005143 0
1138 05:01:42.006117 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 05:01:42.006656 Sending with 10 millisecond of delay
1141 05:01:43.142180 => setenv autoload no
1142 05:01:43.152771 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1143 05:01:43.155814 setenv autoload no
1144 05:01:43.156580 Sending with 10 millisecond of delay
1146 05:01:44.954390 => setenv initrd_high 0xffffffff
1147 05:01:44.964994 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1148 05:01:44.965633 setenv initrd_high 0xffffffff
1149 05:01:44.966144 Sending with 10 millisecond of delay
1151 05:01:46.582848 => setenv fdt_high 0xffffffff
1152 05:01:46.593446 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 05:01:46.594031 setenv fdt_high 0xffffffff
1154 05:01:46.594502 Sending with 10 millisecond of delay
1156 05:01:46.885959 => dhcp
1157 05:01:46.896557 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1158 05:01:46.897171 dhcp
1159 05:01:46.897445 Speed: 1000, full duplex
1160 05:01:46.897664 BOOTP broadcast 1
1161 05:01:46.905826 DHCP client bound to address 192.168.6.27 (9 ms)
1162 05:01:46.906415 Sending with 10 millisecond of delay
1164 05:01:48.584792 => setenv serverip 192.168.6.2
1165 05:01:48.595389 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 05:01:48.596068 setenv serverip 192.168.6.2
1167 05:01:48.596552 Sending with 10 millisecond of delay
1169 05:01:52.324988 => tftpboot 0x01080000 965234/tftp-deploy-rwzvuebl/kernel/uImage
1170 05:01:52.335615 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 05:01:52.336350 tftpboot 0x01080000 965234/tftp-deploy-rwzvuebl/kernel/uImage
1172 05:01:52.336653 Speed: 1000, full duplex
1173 05:01:52.336897 Using ethernet@ff3f0000 device
1174 05:01:52.338548 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 05:01:52.344077 Filename '965234/tftp-deploy-rwzvuebl/kernel/uImage'.
1176 05:01:52.348395 Load address: 0x1080000
1177 05:01:55.951039 Loading: *################################################## 43.6 MiB
1178 05:01:55.951460 12.1 MiB/s
1179 05:01:55.951710 done
1180 05:01:55.955333 Bytes transferred = 45713984 (2b98a40 hex)
1181 05:01:55.955896 Sending with 10 millisecond of delay
1183 05:02:00.647277 => tftpboot 0x08000000 965234/tftp-deploy-rwzvuebl/ramdisk/ramdisk.cpio.gz.uboot
1184 05:02:00.658208 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1185 05:02:00.659185 tftpboot 0x08000000 965234/tftp-deploy-rwzvuebl/ramdisk/ramdisk.cpio.gz.uboot
1186 05:02:00.659682 Speed: 1000, full duplex
1187 05:02:00.660190 Using ethernet@ff3f0000 device
1188 05:02:00.661378 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 05:02:00.673170 Filename '965234/tftp-deploy-rwzvuebl/ramdisk/ramdisk.cpio.gz.uboot'.
1190 05:02:00.673802 Load address: 0x8000000
1191 05:02:02.224273 Loading: *################################################## 22.3 MiB
1192 05:02:02.224945 14.4 MiB/s
1193 05:02:02.225428 done
1194 05:02:02.228823 Bytes transferred = 23434360 (1659478 hex)
1195 05:02:02.229688 Sending with 10 millisecond of delay
1197 05:02:07.402247 => tftpboot 0x01070000 965234/tftp-deploy-rwzvuebl/dtb/meson-g12b-a311d-libretech-cc.dtb
1198 05:02:07.412811 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:57)
1199 05:02:07.413363 tftpboot 0x01070000 965234/tftp-deploy-rwzvuebl/dtb/meson-g12b-a311d-libretech-cc.dtb
1200 05:02:07.413643 Speed: 1000, full duplex
1201 05:02:07.413866 Using ethernet@ff3f0000 device
1202 05:02:07.417892 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1203 05:02:07.425440 Filename '965234/tftp-deploy-rwzvuebl/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1204 05:02:07.439448 Load address: 0x1070000
1205 05:02:07.445647 Loading: *################################################## 53.4 KiB
1206 05:02:07.456366 2.5 MiB/s
1207 05:02:07.456684 done
1208 05:02:07.456895 Bytes transferred = 54703 (d5af hex)
1209 05:02:07.457337 Sending with 10 millisecond of delay
1211 05:02:20.763583 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/965234/extract-nfsrootfs-9k18tv_n,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1212 05:02:20.774614 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:44)
1213 05:02:20.775609 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/965234/extract-nfsrootfs-9k18tv_n,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1214 05:02:20.776523 Sending with 10 millisecond of delay
1216 05:02:23.116034 => bootm 0x01080000 0x08000000 0x01070000
1217 05:02:23.126569 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1218 05:02:23.126872 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:41)
1219 05:02:23.127420 bootm 0x01080000 0x08000000 0x01070000
1220 05:02:23.127652 ## Booting kernel from Legacy Image at 01080000 ...
1221 05:02:23.131345 Image Name:
1222 05:02:23.136942 Image Type: AArch64 Linux Kernel Image (uncompressed)
1223 05:02:23.137309 Data Size: 45713920 Bytes = 43.6 MiB
1224 05:02:23.139137 Load Address: 01080000
1225 05:02:23.145664 Entry Point: 01080000
1226 05:02:23.337893 Verifying Checksum ... OK
1227 05:02:23.338512 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1228 05:02:23.343271 Image Name:
1229 05:02:23.348773 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1230 05:02:23.349765 Data Size: 23434296 Bytes = 22.3 MiB
1231 05:02:23.350997 Load Address: 00000000
1232 05:02:23.357668 Entry Point: 00000000
1233 05:02:23.456543 Verifying Checksum ... OK
1234 05:02:23.457025 ## Flattened Device Tree blob at 01070000
1235 05:02:23.461850 Booting using the fdt blob at 0x1070000
1236 05:02:23.462227 Working FDT set to 1070000
1237 05:02:23.466305 Loading Kernel Image
1238 05:02:23.510956 Loading Ramdisk to 7e9a6000, end 7ffff438 ... OK
1239 05:02:23.519314 Loading Device Tree to 000000007e995000, end 000000007e9a55ae ... OK
1240 05:02:23.519935 Working FDT set to 7e995000
1241 05:02:23.520525
1242 05:02:23.521635 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
1243 05:02:23.522410 start: 2.4.4 auto-login-action (timeout 00:03:41) [common]
1244 05:02:23.523013 Setting prompt string to ['Linux version [0-9]']
1245 05:02:23.523605 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1246 05:02:23.524244 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1247 05:02:23.525560 Starting kernel ...
1248 05:02:23.526139
1249 05:02:23.559640 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1250 05:02:23.560867 start: 2.4.4.1 login-action (timeout 00:03:41) [common]
1251 05:02:23.561550 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1252 05:02:23.562143 Setting prompt string to []
1253 05:02:23.562766 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1254 05:02:23.563355 Using line separator: #'\n'#
1255 05:02:23.563874 No login prompt set.
1256 05:02:23.564496 Parsing kernel messages
1257 05:02:23.565033 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1258 05:02:23.566041 [login-action] Waiting for messages, (timeout 00:03:41)
1259 05:02:23.566613 Waiting using forced prompt support (timeout 00:01:50)
1260 05:02:23.579737 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j370552-arm64-gcc-12-defconfig-pkld2) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Sat Nov 9 04:33:27 UTC 2024
1261 05:02:23.580537 [ 0.000000] KASLR disabled due to lack of seed
1262 05:02:23.585185 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1263 05:02:23.588961 [ 0.000000] efi: UEFI not found.
1264 05:02:23.599935 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1265 05:02:23.605383 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1266 05:02:23.616681 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1267 05:02:23.621920 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1268 05:02:23.632951 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1269 05:02:23.644064 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1270 05:02:23.649564 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1271 05:02:23.655051 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1272 05:02:23.660566 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1273 05:02:23.671608 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1274 05:02:23.672251 [ 0.000000] Zone ranges:
1275 05:02:23.677142 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1276 05:02:23.682657 [ 0.000000] DMA32 empty
1277 05:02:23.683241 [ 0.000000] Normal empty
1278 05:02:23.688227 [ 0.000000] Movable zone start for each node
1279 05:02:23.693717 [ 0.000000] Early memory node ranges
1280 05:02:23.699231 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1281 05:02:23.704754 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1282 05:02:23.710253 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1283 05:02:23.717153 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1284 05:02:23.741462 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1285 05:02:23.746944 [ 0.000000] psci: probing for conduit method from DT.
1286 05:02:23.747526 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1287 05:02:23.756116 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1288 05:02:23.756711 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1289 05:02:23.761618 [ 0.000000] psci: SMC Calling Convention v1.1
1290 05:02:23.767134 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1291 05:02:23.772619 [ 0.000000] Detected VIPT I-cache on CPU0
1292 05:02:23.778201 [ 0.000000] CPU features: detected: ARM erratum 845719
1293 05:02:23.783722 [ 0.000000] alternatives: applying boot alternatives
1294 05:02:23.805779 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/965234/extract-nfsrootfs-9k18tv_n,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1295 05:02:23.811353 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1296 05:02:23.822325 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1297 05:02:23.822936 <6>[ 0.000000] Fallback order for Node 0: 0
1298 05:02:23.833405 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1299 05:02:23.833985 <6>[ 0.000000] Policy zone: DMA
1300 05:02:23.838905 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1301 05:02:23.849957 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1302 05:02:23.850578 <6>[ 0.000000] software IO TLB: area num 8.
1303 05:02:23.860891 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1304 05:02:23.907640 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1305 05:02:23.912998 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1306 05:02:23.916670 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1307 05:02:23.922067 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1308 05:02:23.927635 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1309 05:02:23.933093 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1310 05:02:23.944122 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1311 05:02:23.949655 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1312 05:02:23.955226 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1313 05:02:23.966286 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1314 05:02:23.971790 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1315 05:02:23.977157 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1316 05:02:23.982697 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1317 05:02:23.988154 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1318 05:02:24.001699 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1319 05:02:24.012772 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1320 05:02:24.018383 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1321 05:02:24.023918 <6>[ 0.008793] Console: colour dummy device 80x25
1322 05:02:24.034909 <6>[ 0.012935] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1323 05:02:24.040433 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1324 05:02:24.045957 <6>[ 0.028188] LSM: initializing lsm=capability
1325 05:02:24.051489 <6>[ 0.032727] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1326 05:02:24.056996 <6>[ 0.040210] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1327 05:02:24.062639 <6>[ 0.052298] rcu: Hierarchical SRCU implementation.
1328 05:02:24.068089 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1329 05:02:24.079049 <6>[ 0.058876] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1330 05:02:24.087505 <6>[ 0.071576] EFI services will not be available.
1331 05:02:24.088134 <6>[ 0.075224] smp: Bringing up secondary CPUs ...
1332 05:02:24.099786 <6>[ 0.077133] Detected VIPT I-cache on CPU1
1333 05:02:24.105266 <6>[ 0.077252] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1334 05:02:24.110772 <6>[ 0.078588] CPU features: detected: Spectre-v2
1335 05:02:24.116278 <6>[ 0.078602] CPU features: detected: Spectre-v4
1336 05:02:24.121784 <6>[ 0.078608] CPU features: detected: Spectre-BHB
1337 05:02:24.127376 <6>[ 0.078614] CPU features: detected: ARM erratum 858921
1338 05:02:24.132858 <6>[ 0.078622] Detected VIPT I-cache on CPU2
1339 05:02:24.138374 <6>[ 0.078696] arch_timer: Enabling local workaround for ARM erratum 858921
1340 05:02:24.143870 <6>[ 0.078713] arch_timer: CPU2: Trapping CNTVCT access
1341 05:02:24.149423 <6>[ 0.078723] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1342 05:02:24.154920 <6>[ 0.083571] Detected VIPT I-cache on CPU3
1343 05:02:24.160435 <6>[ 0.083617] arch_timer: Enabling local workaround for ARM erratum 858921
1344 05:02:24.166011 <6>[ 0.083627] arch_timer: CPU3: Trapping CNTVCT access
1345 05:02:24.171572 <6>[ 0.083634] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1346 05:02:24.177024 <6>[ 0.087610] Detected VIPT I-cache on CPU4
1347 05:02:24.182629 <6>[ 0.087656] arch_timer: Enabling local workaround for ARM erratum 858921
1348 05:02:24.188069 <6>[ 0.087666] arch_timer: CPU4: Trapping CNTVCT access
1349 05:02:24.199120 <6>[ 0.087673] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1350 05:02:24.199851 <6>[ 0.091608] Detected VIPT I-cache on CPU5
1351 05:02:24.210069 <6>[ 0.091655] arch_timer: Enabling local workaround for ARM erratum 858921
1352 05:02:24.210712 <6>[ 0.091665] arch_timer: CPU5: Trapping CNTVCT access
1353 05:02:24.221185 <6>[ 0.091672] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1354 05:02:24.221813 <6>[ 0.091785] smp: Brought up 1 node, 6 CPUs
1355 05:02:24.226671 <6>[ 0.213011] SMP: Total of 6 processors activated.
1356 05:02:24.232223 <6>[ 0.217916] CPU: All CPU(s) started at EL2
1357 05:02:24.237640 <6>[ 0.222266] CPU features: detected: 32-bit EL0 Support
1358 05:02:24.243138 <6>[ 0.227578] CPU features: detected: 32-bit EL1 Support
1359 05:02:24.248669 <6>[ 0.232924] CPU features: detected: CRC32 instructions
1360 05:02:24.254265 <6>[ 0.238328] alternatives: applying system-wide alternatives
1361 05:02:24.272241 <6>[ 0.245515] Memory: 3557432K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187800K reserved, 262144K cma-reserved)
1362 05:02:24.272574 <6>[ 0.259856] devtmpfs: initialized
1363 05:02:24.283218 <6>[ 0.269054] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1364 05:02:24.288751 <6>[ 0.273411] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1365 05:02:24.294322 <6>[ 0.284210] 21392 pages in range for non-PLT usage
1366 05:02:24.299833 <6>[ 0.284220] 512912 pages in range for PLT usage
1367 05:02:24.305310 <6>[ 0.285763] pinctrl core: initialized pinctrl subsystem
1368 05:02:24.310805 <6>[ 0.297844] DMI not present or invalid.
1369 05:02:24.316311 <6>[ 0.302128] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1370 05:02:24.321839 <6>[ 0.306877] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1371 05:02:24.332863 <6>[ 0.313648] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1372 05:02:24.338548 <6>[ 0.321753] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1373 05:02:24.343999 <6>[ 0.329244] audit: initializing netlink subsys (disabled)
1374 05:02:24.354967 <5>[ 0.334969] audit: type=2000 audit(0.256:1): state=initialized audit_enabled=0 res=1
1375 05:02:24.360601 <6>[ 0.336394] thermal_sys: Registered thermal governor 'step_wise'
1376 05:02:24.365996 <6>[ 0.342749] thermal_sys: Registered thermal governor 'power_allocator'
1377 05:02:24.371568 <6>[ 0.349008] cpuidle: using governor menu
1378 05:02:24.377024 <6>[ 0.359979] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1379 05:02:24.382584 <6>[ 0.366915] ASID allocator initialised with 65536 entries
1380 05:02:24.390810 <6>[ 0.374351] Serial: AMBA PL011 UART driver
1381 05:02:24.398666 <6>[ 0.384989] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1382 05:02:24.413934 <6>[ 0.400543] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1383 05:02:24.424977 <6>[ 0.403210] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1384 05:02:24.430597 <6>[ 0.416373] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1385 05:02:24.436018 <6>[ 0.419585] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1386 05:02:24.447031 <6>[ 0.428014] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1387 05:02:24.452570 <6>[ 0.435633] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1388 05:02:24.463573 <6>[ 0.449178] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1389 05:02:24.469112 <6>[ 0.451455] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1390 05:02:24.474656 <6>[ 0.457936] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1391 05:02:24.480203 <6>[ 0.464914] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1392 05:02:24.491388 <6>[ 0.471383] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1393 05:02:24.496970 <6>[ 0.478367] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1394 05:02:24.502336 <6>[ 0.484844] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1395 05:02:24.507873 <6>[ 0.491823] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1396 05:02:24.513543 <6>[ 0.499922] ACPI: Interpreter disabled.
1397 05:02:24.518893 <6>[ 0.505342] iommu: Default domain type: Translated
1398 05:02:24.524444 <6>[ 0.507356] iommu: DMA domain TLB invalidation policy: strict mode
1399 05:02:24.529857 <5>[ 0.514120] SCSI subsystem initialized
1400 05:02:24.535422 <6>[ 0.517952] usbcore: registered new interface driver usbfs
1401 05:02:24.540991 <6>[ 0.523417] usbcore: registered new interface driver hub
1402 05:02:24.546507 <6>[ 0.528930] usbcore: registered new device driver usb
1403 05:02:24.552055 <6>[ 0.535211] pps_core: LinuxPPS API ver. 1 registered
1404 05:02:24.557509 <6>[ 0.539349] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1405 05:02:24.563051 <6>[ 0.548669] PTP clock support registered
1406 05:02:24.568708 <6>[ 0.552908] EDAC MC: Ver: 3.0.0
1407 05:02:24.574137 <6>[ 0.556555] scmi_core: SCMI protocol bus registered
1408 05:02:24.574509 <6>[ 0.562156] FPGA manager framework
1409 05:02:24.579679 <6>[ 0.564932] Advanced Linux Sound Architecture Driver Initialized.
1410 05:02:24.585082 <6>[ 0.571861] vgaarb: loaded
1411 05:02:24.590649 <6>[ 0.574410] clocksource: Switched to clocksource arch_sys_counter
1412 05:02:24.596177 <5>[ 0.580582] VFS: Disk quotas dquot_6.6.0
1413 05:02:24.601607 <6>[ 0.584564] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1414 05:02:24.607107 <6>[ 0.591772] pnp: PnP ACPI: disabled
1415 05:02:24.612758 <6>[ 0.600283] NET: Registered PF_INET protocol family
1416 05:02:24.618235 <6>[ 0.600598] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1417 05:02:24.629207 <6>[ 0.610754] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1418 05:02:24.634902 <6>[ 0.616765] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1419 05:02:24.645958 <6>[ 0.624661] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1420 05:02:24.659352 <6>[ 0.632896] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1421 05:02:24.660874 <6>[ 0.640699] TCP: Hash tables configured (established 32768 bind 32768)
1422 05:02:24.665798 <6>[ 0.647172] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1423 05:02:24.671203 <6>[ 0.654023] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1424 05:02:24.676815 <6>[ 0.661447] NET: Registered PF_UNIX/PF_LOCAL protocol family
1425 05:02:24.682120 <6>[ 0.667507] RPC: Registered named UNIX socket transport module.
1426 05:02:24.687829 <6>[ 0.673306] RPC: Registered udp transport module.
1427 05:02:24.693263 <6>[ 0.678211] RPC: Registered tcp transport module.
1428 05:02:24.698823 <6>[ 0.683129] RPC: Registered tcp-with-tls transport module.
1429 05:02:24.704338 <6>[ 0.688820] RPC: Registered tcp NFSv4.1 backchannel transport module.
1430 05:02:24.709863 <6>[ 0.695467] PCI: CLS 0 bytes, default 64
1431 05:02:24.715323 <6>[ 0.699781] Unpacking initramfs...
1432 05:02:24.720949 <6>[ 0.706006] kvm [1]: nv: 554 coarse grained trap handlers
1433 05:02:24.726373 <6>[ 0.709125] kvm [1]: IPA Size Limit: 40 bits
1434 05:02:24.726912 <6>[ 0.714769] kvm [1]: vgic interrupt IRQ9
1435 05:02:24.731922 <6>[ 0.717479] kvm [1]: Hyp nVHE mode initialized successfully
1436 05:02:24.737467 <5>[ 0.724567] Initialise system trusted keyrings
1437 05:02:24.743001 <6>[ 0.728139] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1438 05:02:24.753981 <6>[ 0.734809] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1439 05:02:24.754528 <5>[ 0.740881] NFS: Registering the id_resolver key type
1440 05:02:24.759582 <5>[ 0.745854] Key type id_resolver registered
1441 05:02:24.765244 <5>[ 0.750232] Key type id_legacy registered
1442 05:02:24.770547 <6>[ 0.754469] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1443 05:02:24.781580 <6>[ 0.761358] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1444 05:02:24.785877 <6>[ 0.769247] 9p: Installing v9fs 9p2000 file system support
1445 05:02:24.824051 <5>[ 0.815910] Key type asymmetric registered
1446 05:02:24.829481 <5>[ 0.815947] Asymmetric key parser 'x509' registered
1447 05:02:24.838570 <6>[ 0.819817] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1448 05:02:24.844124 <6>[ 0.827343] io scheduler mq-deadline registered
1449 05:02:24.849547 <6>[ 0.832076] io scheduler kyber registered
1450 05:02:24.850070 <6>[ 0.836347] io scheduler bfq registered
1451 05:02:24.858038 <6>[ 0.844171] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1452 05:02:24.874264 <6>[ 0.862533] ledtrig-cpu: registered to indicate activity on CPUs
1453 05:02:24.907017 <6>[ 0.894050] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1454 05:02:24.926874 <6>[ 0.907609] Serial: 8250/16550 driver, 4 port<6>[ 0.912165] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1455 05:02:24.930195 <6>[ 0.921801] printk: legacy console [ttyAML0] enabled
1456 05:02:24.935810 <6>[ 0.921801] printk: legacy console [ttyAML0] enabled
1457 05:02:24.941288 <6>[ 0.926603] printk: legacy bootconsole [meson0] disabled
1458 05:02:24.946806 <6>[ 0.926603] printk: legacy bootconsole [meson0] disabled
1459 05:02:24.952378 <6>[ 0.939202] msm_serial: driver initialized
1460 05:02:24.957939 <6>[ 0.942604] SuperH (H)SCI(F) driver initialized
1461 05:02:24.963487 <6>[ 0.947098] STM32 USART driver initialized
1462 05:02:24.964033 <5>[ 0.953310] random: crng init done
1463 05:02:24.969026 <6>[ 0.959074] loop: module loaded
1464 05:02:24.976065 <6>[ 0.960343] megasas: 07.727.03.00-rc1
1465 05:02:24.981555 <6>[ 0.969122] tun: Universal TUN/TAP device driver, 1.6
1466 05:02:24.982076 <6>[ 0.970322] thunder_xcv, ver 1.0
1467 05:02:24.987119 <6>[ 0.972328] thunder_bgx, ver 1.0
1468 05:02:24.987635 <6>[ 0.975775] nicpf, ver 1.0
1469 05:02:24.998160 <6>[ 0.980359] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1470 05:02:25.003857 <6>[ 0.986147] hns3: Copyright (c) 2017 Huawei Corporation.
1471 05:02:25.004421 <6>[ 0.991745] hclge is initializing
1472 05:02:25.009350 <6>[ 0.995275] e1000: Intel(R) PRO/1000 Network Driver
1473 05:02:25.014875 <6>[ 1.000353] e1000: Copyright (c) 1999-2006 Intel Corporation.
1474 05:02:25.020483 <6>[ 1.006379] e1000e: Intel(R) PRO/1000 Network Driver
1475 05:02:25.025979 <6>[ 1.011533] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1476 05:02:25.032257 <6>[ 1.017717] igb: Intel(R) Gigabit Ethernet Network Driver
1477 05:02:25.042609 <6>[ 1.023320] igb: Copyright (c) 2007-2014 Intel Corporation.
1478 05:02:25.048192 <6>[ 1.029152] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1479 05:02:25.054725 <6>[ 1.035625] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1480 05:02:25.057991 <6>[ 1.042392] sky2: driver version 1.30
1481 05:02:25.060362 <6>[ 1.047468] VFIO - User Level meta-driver version: 0.3
1482 05:02:25.066041 <6>[ 1.054991] usbcore: registered new interface driver usb-storage
1483 05:02:25.073443 <6>[ 1.061221] i2c_dev: i2c /dev entries driver
1484 05:02:25.085826 <6>[ 1.072209] sdhci: Secure Digital Host Controller Interface driver
1485 05:02:25.086370 <6>[ 1.073016] sdhci: Copyright(c) Pierre Ossman
1486 05:02:25.096878 <6>[ 1.078751] Synopsys Designware Multimedia Card Interface Driver
1487 05:02:25.102549 <6>[ 1.085268] sdhci-pltfm: SDHCI platform and OF driver helper
1488 05:02:25.103076 <6>[ 1.092963] meson-sm: secure-monitor enabled
1489 05:02:25.115315 <6>[ 1.095526] usbcore: registered new interface driver usbhid
1490 05:02:25.115862 <6>[ 1.100074] usbhid: USB HID core driver
1491 05:02:25.122967 <6>[ 1.114847] NET: Registered PF_PACKET protocol family
1492 05:02:25.128492 <6>[ 1.114937] 9pnet: Installing 9P2000 support
1493 05:02:25.135607 <5>[ 1.119086] Key type dns_resolver registered
1494 05:02:25.141090 <6>[ 1.130675] registered taskstats version 1
1495 05:02:25.146587 <5>[ 1.130829] Loading compiled-in X.509 certificates
1496 05:02:25.150200 <6>[ 1.139580] Demotion targets for Node 0: null
1497 05:02:25.191090 <6>[ 1.182927] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1498 05:02:25.196640 <6>[ 1.182973] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1499 05:02:25.207632 <4>[ 1.193146] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1500 05:02:25.213223 <4>[ 1.195771] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1501 05:02:25.218768 <6>[ 1.203324] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1502 05:02:25.224331 <6>[ 1.212544] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1503 05:02:25.235391 <6>[ 1.216018] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1504 05:02:25.246396 <6>[ 1.224003] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1505 05:02:25.252036 <6>[ 1.233530] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1506 05:02:25.257525 <6>[ 1.239757] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1507 05:02:25.263140 <6>[ 1.245378] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1508 05:02:25.268645 <6>[ 1.253263] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1509 05:02:25.274206 <6>[ 1.260549] hub 1-0:1.0: USB hub found
1510 05:02:25.279875 <6>[ 1.264032] hub 1-0:1.0: 2 ports detected
1511 05:02:25.285269 <6>[ 1.270082] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1512 05:02:25.290886 <6>[ 1.276996] hub 2-0:1.0: USB hub found
1513 05:02:25.295923 <6>[ 1.280587] hub 2-0:1.0: 1 port detected
1514 05:02:25.316174 <6>[ 1.305498] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1515 05:02:25.327715 <6>[ 1.316333] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1516 05:02:25.361470 <6>[ 1.349740] Trying to probe devices needed for running init ...
1517 05:02:25.526703 <6>[ 1.514446] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1518 05:02:25.667374 <6>[ 1.653732] mmc0: new ultra high speed SDR104 SDXC card at address e624
1519 05:02:25.673527 <6>[ 1.655500] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1520 05:02:25.674028 <6>[ 1.661227] mmcblk0: p1
1521 05:02:25.686423 <6>[ 1.676594] Freeing initrd memory: 22884K
1522 05:02:25.716302 <6>[ 1.708359] hub 1-1:1.0: USB hub found
1523 05:02:25.722175 <6>[ 1.708634] hub 1-1:1.0: 4 ports detected
1524 05:02:25.782910 <6>[ 1.770562] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1525 05:02:25.829040 <6>[ 1.821017] hub 2-1:1.0: USB hub found
1526 05:02:25.834849 <6>[ 1.821843] hub 2-1:1.0: 4 ports detected
1527 05:02:37.654854 <6>[ 13.646501] clk: Disabling unused clocks
1528 05:02:37.660259 <6>[ 13.646744] PM: genpd: Disabling unused power domains
1529 05:02:37.668651 <6>[ 13.650382] ALSA device list:
1530 05:02:37.669240 <6>[ 13.653575] No soundcards found.
1531 05:02:37.675835 <6>[ 13.667459] Freeing unused kernel memory: 10432K
1532 05:02:37.681957 <6>[ 13.667587] Run /init as init process
1533 05:02:37.688613 Loading, please wait...
1534 05:02:37.722707 Starting systemd-udevd version 252.22-1~deb12u1
1535 05:02:38.134334 <6>[ 14.124013] mc: Linux media interface: v0.10
1536 05:02:38.165710 <6>[ 14.154251] videodev: Linux video capture interface: v2.00
1537 05:02:38.177394 <4>[ 14.163215] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1538 05:02:38.196143 <6>[ 14.188003] meson-vrtc ff8000a8.rtc: registered as rtc0
1539 05:02:38.207113 <6>[ 14.188059] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1540 05:02:38.212775 <6>[ 14.201052] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1541 05:02:38.218421 <6>[ 14.203281] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1542 05:02:38.223880 <6>[ 14.209584] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1543 05:02:38.234826 <6>[ 14.215796] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1544 05:02:38.240340 <4>[ 14.217715] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1545 05:02:38.251469 <6>[ 14.222579] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1546 05:02:38.257167 <3>[ 14.223692] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1547 05:02:38.262763 <6>[ 14.247622] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1548 05:02:38.268271 <6>[ 14.248634] Registered IR keymap rc-empty
1549 05:02:38.273779 <6>[ 14.252633] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1550 05:02:38.284886 <6>[ 14.257012] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1551 05:02:38.290399 <6>[ 14.264569] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1552 05:02:38.296028 <6>[ 14.264578] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1553 05:02:38.301640 <6>[ 14.285802] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1554 05:02:38.312664 <6>[ 14.286557] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1555 05:02:38.318184 <6>[ 14.293078] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1556 05:02:38.323718 <6>[ 14.308569] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1557 05:02:38.329199 <6>[ 14.310260] rc rc0: sw decoder init
1558 05:02:38.334677 <6>[ 14.314555] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1559 05:02:38.340196 <6>[ 14.320507] meson-ir ff808000.ir: receiver initialized
1560 05:02:38.348956 <6>[ 14.324308] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1561 05:02:38.363314 <6>[ 14.355392] panfrost ffe40000.gpu: clock rate = 24000000
1562 05:02:38.375575 <3>[ 14.355484] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1563 05:02:38.396459 <6>[ 14.382811] usbcore: registered new device driver onboard-usb-dev
1564 05:02:38.402025 <6>[ 14.384048] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1565 05:02:38.405486 <6>[ 14.384143] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1566 05:02:38.416499 <6>[ 14.384898] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1567 05:02:38.427717 <6>[ 14.391596] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1568 05:02:38.438700 <6>[ 14.416726] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1569 05:02:38.444282 <6>[ 14.424297] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1570 05:02:38.455341 <6>[ 14.428790] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1571 05:02:38.460950 <6>[ 14.435291] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1572 05:02:38.471954 <6>[ 14.447696] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1573 05:02:38.477529 <6>[ 14.452393] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1574 05:02:38.488705 <6>[ 14.468026] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1575 05:02:38.494169 <3>[ 14.476145] meson-drm ff900000.vpu: DSI transceiver device is disabled
1576 05:02:38.500667 <6>[ 14.483292] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1577 05:02:38.687104 <6>[ 14.655219] Console: switching to colour frame buffer device 128x48
1578 05:02:38.692825 <6>[ 14.674430] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1579 05:02:38.932448 <6>[ 14.924335] hub 1-1:1.0: USB hub found
1580 05:02:38.937867 <6>[ 14.924647] hub 1-1:1.0: 4 ports detected
1581 05:02:38.944319 <6>[ 14.929398] onboard-usb-dev 1-1: USB disconnect, device number 2
1582 05:02:39.072915 Begin: Loading essential drivers ... done.
1583 05:02:39.078491 Begin: Running /scripts/init-premount ... done.
1584 05:02:39.083948 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1585 05:02:39.095009 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1586 05:02:39.095538 Device /sys/class/net/end0 found
1587 05:02:39.096018 done.
1588 05:02:39.104937 Begin: Waiting up to 180 secs for any network device to become available ... done.
1589 05:02:39.165585 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.148516] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1590 05:02:39.166203
1591 05:02:39.254833 <6>[ 15.238525] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=29)
1592 05:02:39.268253 <6>[ 15.254530] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1593 05:02:39.273741 <6>[ 15.256721] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1594 05:02:39.279210 <6>[ 15.260342] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1595 05:02:39.289970 <6>[ 15.270725] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1596 05:02:39.418917 <6>[ 15.406463] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1597 05:02:39.604628 <6>[ 15.596451] hub 1-1:1.0: USB hub found
1598 05:02:39.610266 <6>[ 15.596794] hub 1-1:1.0: 4 ports detected
1599 05:02:40.697925 IP-Config: no response after 2 secs - giving up
1600 05:02:40.739049 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1601 05:02:40.798481 <4>[ 16.790434] rc rc0: two consecutive events of type space
1602 05:02:42.239752 <6>[ 18.225678] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1603 05:02:42.968534 IP-Config: end0 guessed broadcast address 192.168.6.255
1604 05:02:42.974044 IP-Config: end0 complete (dhcp from 192.168.6.1):
1605 05:02:42.979502 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1606 05:02:42.988480 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1607 05:02:42.994051 rootserver: 192.168.6.1 rootpath:
1608 05:02:42.994553 filename :
1609 05:02:43.102493 done.
1610 05:02:43.113093 Begin: Running /scripts/nfs-bottom ... done.
1611 05:02:43.129163 Begin: Running /scripts/init-bottom ... done.
1612 05:02:43.480868 <30>[ 19.468228] systemd[1]: System time before build time, advancing clock.
1613 05:02:43.538743 <6>[ 19.530497] NET: Registered PF_INET6 protocol family
1614 05:02:43.544353 <6>[ 19.532277] Segment Routing with IPv6
1615 05:02:43.549409 <6>[ 19.534003] In-situ OAM (IOAM) with IPv6
1616 05:02:43.625971 <30>[ 19.590302] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1617 05:02:43.631630 <30>[ 19.617678] systemd[1]: Detected architecture arm64.
1618 05:02:43.632221
1619 05:02:43.639925 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1620 05:02:43.640515
1621 05:02:43.648165 <30>[ 19.636176] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1622 05:02:44.569939 <30>[ 20.556912] systemd[1]: Queued start job for default target graphical.target.
1623 05:02:44.600659 <30>[ 20.587093] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1624 05:02:44.608256 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1625 05:02:44.626152 <30>[ 20.612425] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1626 05:02:44.633565 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1627 05:02:44.646055 <30>[ 20.632453] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1628 05:02:44.659308 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1629 05:02:44.664870 <30>[ 20.651998] systemd[1]: Created slice user.slice - User and Session Slice.
1630 05:02:44.672228 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1631 05:02:44.694305 <30>[ 20.675011] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1632 05:02:44.698222 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1633 05:02:44.716537 <30>[ 20.702966] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1634 05:02:44.728569 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1635 05:02:44.745113 <30>[ 20.722850] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1636 05:02:44.756282 <30>[ 20.737042] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1637 05:02:44.763839 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1638 05:02:44.769401 <30>[ 20.758667] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1639 05:02:44.780406 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1640 05:02:44.796271 <30>[ 20.782724] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1641 05:02:44.809975 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1642 05:02:44.815508 <30>[ 20.802774] systemd[1]: Reached target paths.target - Path Units.
1643 05:02:44.823909 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1644 05:02:44.829470 <30>[ 20.818678] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1645 05:02:44.841105 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1646 05:02:44.846700 <30>[ 20.834682] systemd[1]: Reached target slices.target - Slice Units.
1647 05:02:44.854848 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1648 05:02:44.860480 <30>[ 20.850695] systemd[1]: Reached target swap.target - Swaps.
1649 05:02:44.868218 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1650 05:02:44.880345 <30>[ 20.866752] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1651 05:02:44.889107 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1652 05:02:44.904553 <30>[ 20.891060] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1653 05:02:44.913754 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1654 05:02:44.926124 <30>[ 20.912602] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1655 05:02:44.939882 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1656 05:02:44.945515 <30>[ 20.932089] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1657 05:02:44.958484 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1658 05:02:44.963965 <30>[ 20.951402] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1659 05:02:44.972253 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1660 05:02:44.989828 <30>[ 20.976347] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1661 05:02:44.998417 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1662 05:02:45.010996 <30>[ 20.997485] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1663 05:02:45.016596 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1664 05:02:45.028771 <30>[ 21.015243] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1665 05:02:45.037278 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1666 05:02:45.084305 <30>[ 21.070813] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1667 05:02:45.091034 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1668 05:02:45.105606 <30>[ 21.092113] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1669 05:02:45.113139 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1670 05:02:45.130366 <30>[ 21.116887] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1671 05:02:45.137786 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1672 05:02:45.157910 <30>[ 21.138848] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1673 05:02:45.168959 <30>[ 21.151919] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1674 05:02:45.176055 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1675 05:02:45.194918 <30>[ 21.181333] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1676 05:02:45.202783 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1677 05:02:45.214853 <30>[ 21.201383] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1678 05:02:45.221472 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1679 05:02:45.234750 <30>[ 21.221164] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1680 05:02:45.242888 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1681 05:02:45.253984 <6>[ 21.238712] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1682 05:02:45.259673 <30>[ 21.241064] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1683 05:02:45.269705 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1684 05:02:45.282889 <30>[ 21.269352] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1685 05:02:45.290278 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1686 05:02:45.302564 <30>[ 21.289055] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1687 05:02:45.308265 <6>[ 21.293712] fuse: init (API version 7.41)
1688 05:02:45.312160 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1689 05:02:45.337860 <30>[ 21.324301] systemd[1]: Starting systemd-journald.service - Journal Service...
1690 05:02:45.344293 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1691 05:02:45.367301 <30>[ 21.353685] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1692 05:02:45.374845 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1693 05:02:45.389051 <30>[ 21.375462] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1694 05:02:45.398688 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1695 05:02:45.416273 <30>[ 21.402538] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1696 05:02:45.424863 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1697 05:02:45.439866 <30>[ 21.426315] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1698 05:02:45.448008 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1699 05:02:45.462862 <30>[ 21.449297] systemd[1]: Started systemd-journald.service - Journal Service.
1700 05:02:45.469777 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1701 05:02:45.484154 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1702 05:02:45.501248 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1703 05:02:45.517818 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1704 05:02:45.533866 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1705 05:02:45.546864 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1706 05:02:45.559076 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1707 05:02:45.571030 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1708 05:02:45.582060 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1709 05:02:45.594763 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1710 05:02:45.606717 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1711 05:02:45.618696 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1712 05:02:45.633774 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1713 05:02:45.641070 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1714 05:02:45.654900 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1715 05:02:45.723931 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1716 05:02:45.747913 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1717 05:02:45.768405 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1718 05:02:45.785635 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1719 05:02:45.812665 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Ker<46>[ 21.793003] systemd-journald[229]: Received client request to flush runtime journal.
1720 05:02:45.813179 nel Variables...
1721 05:02:45.827084 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1722 05:02:45.841679 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1723 05:02:45.853006 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1724 05:02:45.870590 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1725 05:02:45.885655 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1726 05:02:45.901401 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1727 05:02:45.960638 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1728 05:02:45.999820 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1729 05:02:46.079408 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1730 05:02:46.128144 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1731 05:02:46.135585 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1732 05:02:46.151725 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1733 05:02:46.215419 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1734 05:02:46.221952 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1735 05:02:46.449605 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1736 05:02:46.491829 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1737 05:02:46.506251 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1738 05:02:46.513689 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1739 05:02:46.574422 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1740 05:02:46.595690 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1741 05:02:46.663068 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1742 05:02:46.676757 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1743 05:02:46.692603 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1744 05:02:46.708955 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1745 05:02:46.741183 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m -<46>[ 22.713106] systemd-journald[229]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1746 05:02:46.741706 System Time Set.
1747 05:02:46.755790 <46>[ 22.733918] systemd-journald[229]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1748 05:02:46.777907 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1749 05:02:46.792259 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1750 05:02:46.800742 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1751 05:02:46.874442 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1752 05:02:46.892568 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1753 05:02:46.901484 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1754 05:02:46.919205 <5>[ 22.903962] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1755 05:02:46.948995 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1756 05:02:46.966085 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1757 05:02:46.970450 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1758 05:02:47.015953 <5>[ 23.002477] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1759 05:02:47.021548 <5>[ 23.003381] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1760 05:02:47.027080 <4>[ 23.011218] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1761 05:02:47.035293 <6>[ 23.019081] cfg80211: failed to load regulatory.db
1762 05:02:47.059221 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1763 05:02:47.082206 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1764 05:02:47.100778 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1765 05:02:47.113224 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1766 05:02:47.150338 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1767 05:02:47.164585 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1768 05:02:47.180964 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1769 05:02:47.231026 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1770 05:02:47.237370 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1771 05:02:47.247836 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1772 05:02:47.261095 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1773 05:02:47.278203 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1774 05:02:47.313260 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1775 05:02:47.331219 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1776 05:02:47.371641 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1777 05:02:47.384340 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1778 05:02:47.391866 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1779 05:02:47.400689 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1780 05:02:47.413375 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1781 05:02:47.425469 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1782 05:02:47.468311 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1783 05:02:47.512462 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1784 05:02:47.591558
1785 05:02:47.592263 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1786 05:02:47.598851
1787 05:02:47.599969 debian-bookworm-arm64 login: root (automatic login)
1788 05:02:47.600530
1789 05:02:47.747188 Linux debian-bookworm-arm64 6.12.0-rc2 #1 SMP PREEMPT Sat Nov 9 04:33:27 UTC 2024 aarch64
1790 05:02:47.747815
1791 05:02:47.752726 The programs included with the Debian GNU/Linux system are free software;
1792 05:02:47.758239 the exact distribution terms for each program are described in the
1793 05:02:47.763708 individual files in /usr/share/doc/*/copyright.
1794 05:02:47.764273
1795 05:02:47.769295 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1796 05:02:47.772407 permitted by applicable law.
1797 05:02:48.510128 Matched prompt #10: / #
1799 05:02:48.511120 Setting prompt string to ['/ #']
1800 05:02:48.511465 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1802 05:02:48.512306 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1803 05:02:48.512636 start: 2.4.5 expect-shell-connection (timeout 00:03:16) [common]
1804 05:02:48.512889 Setting prompt string to ['/ #']
1805 05:02:48.513112 Forcing a shell prompt, looking for ['/ #']
1807 05:02:48.563687 / #
1808 05:02:48.564500 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1809 05:02:48.564851 Waiting using forced prompt support (timeout 00:02:30)
1810 05:02:48.569230
1811 05:02:48.569895 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1812 05:02:48.570244 start: 2.4.6 export-device-env (timeout 00:03:16) [common]
1813 05:02:48.570516 Sending with 10 millisecond of delay
1815 05:02:53.560185 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/965234/extract-nfsrootfs-9k18tv_n'
1816 05:02:53.571187 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/965234/extract-nfsrootfs-9k18tv_n'
1817 05:02:53.572046 Sending with 10 millisecond of delay
1819 05:02:55.670435 / # export NFS_SERVER_IP='192.168.6.2'
1820 05:02:55.681364 export NFS_SERVER_IP='192.168.6.2'
1821 05:02:55.682237 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1822 05:02:55.682819 end: 2.4 uboot-commands (duration 00:01:51) [common]
1823 05:02:55.683396 end: 2 uboot-action (duration 00:01:51) [common]
1824 05:02:55.683964 start: 3 lava-test-retry (timeout 00:06:48) [common]
1825 05:02:55.684600 start: 3.1 lava-test-shell (timeout 00:06:48) [common]
1826 05:02:55.685061 Using namespace: common
1828 05:02:55.786267 / # #
1829 05:02:55.787353 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1830 05:02:55.792411 #
1831 05:02:55.793263 Using /lava-965234
1833 05:02:55.894477 / # export SHELL=/bin/bash
1834 05:02:55.901316 export SHELL=/bin/bash
1836 05:02:56.002811 / # . /lava-965234/environment
1837 05:02:56.007956 . /lava-965234/environment
1839 05:02:56.113825 / # /lava-965234/bin/lava-test-runner /lava-965234/0
1840 05:02:56.114667 Test shell timeout: 10s (minimum of the action and connection timeout)
1841 05:02:56.119315 /lava-965234/bin/lava-test-runner /lava-965234/0
1842 05:02:56.324618 + export TESTRUN_ID=0_timesync-off
1843 05:02:56.332519 + TESTRUN_ID=0_timesync-off
1844 05:02:56.333095 + cd /lava-965234/0/tests/0_timesync-off
1845 05:02:56.333555 ++ cat uuid
1846 05:02:56.338128 + UUID=965234_1.6.2.4.1
1847 05:02:56.338643 + set +x
1848 05:02:56.345832 <LAVA_SIGNAL_STARTRUN 0_timesync-off 965234_1.6.2.4.1>
1849 05:02:56.346368 + systemctl stop systemd-timesyncd
1850 05:02:56.347133 Received signal: <STARTRUN> 0_timesync-off 965234_1.6.2.4.1
1851 05:02:56.347692 Starting test lava.0_timesync-off (965234_1.6.2.4.1)
1852 05:02:56.348309 Skipping test definition patterns.
1853 05:02:56.393927 + set +x
1854 05:02:56.394547 <LAVA_SIGNAL_ENDRUN 0_timesync-off 965234_1.6.2.4.1>
1855 05:02:56.395241 Received signal: <ENDRUN> 0_timesync-off 965234_1.6.2.4.1
1856 05:02:56.395750 Ending use of test pattern.
1857 05:02:56.396207 Ending test lava.0_timesync-off (965234_1.6.2.4.1), duration 0.05
1859 05:02:56.475276 + export TESTRUN_ID=1_kselftest-alsa
1860 05:02:56.483141 + TESTRUN_ID=1_kselftest-alsa
1861 05:02:56.483665 + cd /lava-965234/0/tests/1_kselftest-alsa
1862 05:02:56.484155 ++ cat uuid
1863 05:02:56.489535 + UUID=965234_1.6.2.4.5
1864 05:02:56.489989 + set +x
1865 05:02:56.495192 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 965234_1.6.2.4.5>
1866 05:02:56.495792 + cd ./automated/linux/kselftest/
1867 05:02:56.496683 Received signal: <STARTRUN> 1_kselftest-alsa 965234_1.6.2.4.5
1868 05:02:56.497151 Starting test lava.1_kselftest-alsa (965234_1.6.2.4.5)
1869 05:02:56.497655 Skipping test definition patterns.
1870 05:02:56.524792 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-256-gebd9c70be2b2/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1871 05:02:56.570903 INFO: install_deps skipped
1872 05:02:56.699707 --2024-11-09 05:02:56-- http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-256-gebd9c70be2b2/arm64/defconfig/gcc-12/kselftest.tar.xz
1873 05:02:56.730144 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1874 05:02:56.875964 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1875 05:02:57.018322 HTTP request sent, awaiting response... 200 OK
1876 05:02:57.018977 Length: 6925976 (6.6M) [application/octet-stream]
1877 05:02:57.023587 Saving to: 'kselftest_armhf.tar.gz'
1878 05:02:57.024346
1879 05:02:58.344942
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 49.92K 175KB/s
kselftest_armhf.tar 3%[ ] 218.67K 383KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.01MB/s
kselftest_armhf.tar 52%[=========> ] 3.44M 2.93MB/s
kselftest_armhf.tar 100%[===================>] 6.60M 5.00MB/s in 1.3s
1880 05:02:58.345600
1881 05:02:58.442870 2024-11-09 05:02:58 (5.00 MB/s) - 'kselftest_armhf.tar.gz' saved [6925976/6925976]
1882 05:02:58.443516
1883 05:03:07.813420 skiplist:
1884 05:03:07.813845 ========================================
1885 05:03:07.819110 ========================================
1886 05:03:07.857011 alsa:mixer-test
1887 05:03:07.857438 alsa:pcm-test
1888 05:03:07.857696 alsa:test-pcmtest-driver
1889 05:03:07.861254 alsa:utimer-test
1890 05:03:07.874298 ============== Tests to run ===============
1891 05:03:07.874713 alsa:mixer-test
1892 05:03:07.879871 alsa:pcm-test
1893 05:03:07.880268 alsa:test-pcmtest-driver
1894 05:03:07.880527 alsa:utimer-test
1895 05:03:07.888128 ===========End Tests to run ===============
1896 05:03:07.888518 shardfile-alsa pass
1897 05:03:07.981204 <12>[ 43.970853] kselftest: Running tests in alsa
1898 05:03:07.986156 TAP version 13
1899 05:03:07.995048 1..4
1900 05:03:08.016598 # timeout set to 45
1901 05:03:08.017180 # selftests: alsa: mixer-test
1902 05:03:08.214138 # TAP version 13
1903 05:03:08.214770 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1904 05:03:08.219702 # 1..427
1905 05:03:08.220231 # ok 1 get_value.LCALTA.60
1906 05:03:08.220659 # # LCALTA.60 TDMOUT_A SRC SEL
1907 05:03:08.225061 # ok 2 name.LCALTA.60
1908 05:03:08.225534 # ok 3 write_default.LCALTA.60
1909 05:03:08.228678 # ok 4 write_valid.LCALTA.60
1910 05:03:08.234208 # ok 5 write_invalid.LCALTA.60
1911 05:03:08.234690 # ok 6 event_missing.LCALTA.60
1912 05:03:08.239846 # ok 7 event_spurious.LCALTA.60
1913 05:03:08.240347 # ok 8 get_value.LCALTA.59
1914 05:03:08.245339 # # LCALTA.59 TDMOUT_B SRC SEL
1915 05:03:08.245804 # ok 9 name.LCALTA.59
1916 05:03:08.249007 # ok 10 write_default.LCALTA.59
1917 05:03:08.249470 # ok 11 write_valid.LCALTA.59
1918 05:03:08.254520 # ok 12 write_invalid.LCALTA.59
1919 05:03:08.255114 # ok 13 event_missing.LCALTA.59
1920 05:03:08.260050 # ok 14 event_spurious.LCALTA.59
1921 05:03:08.260754 # ok 15 get_value.LCALTA.58
1922 05:03:08.265645 # # LCALTA.58 TDMOUT_C SRC SEL
1923 05:03:08.266199 # ok 16 name.LCALTA.58
1924 05:03:08.271158 # ok 17 write_default.LCALTA.58
1925 05:03:08.271709 # ok 18 write_valid.LCALTA.58
1926 05:03:08.276686 # ok 19 write_invalid.LCALTA.58
1927 05:03:08.277204 # ok 20 event_missing.LCALTA.58
1928 05:03:08.282211 # ok 21 event_spurious.LCALTA.58
1929 05:03:08.282757 # ok 22 get_value.LCALTA.57
1930 05:03:08.287906 # # LCALTA.57 TDMIN_A SRC SEL
1931 05:03:08.288458 # ok 23 name.LCALTA.57
1932 05:03:08.293222 # ok 24 write_default.LCALTA.57
1933 05:03:08.293733 # ok 25 write_valid.LCALTA.57
1934 05:03:08.301322 # ok 26 write_invalid.LCALTA.57
1935 05:03:08.301730 # ok 27 event_missing.LCALTA.57
1936 05:03:08.304199 # ok 28 event_spurious.LCALTA.57
1937 05:03:08.304711 # ok 29 get_value.LCALTA.56
1938 05:03:08.309797 # # LCALTA.56 TDMIN_B SRC SEL
1939 05:03:08.310175 # ok 30 name.LCALTA.56
1940 05:03:08.310431 # ok 31 write_default.LCALTA.56
1941 05:03:08.315380 # ok 32 write_valid.LCALTA.56
1942 05:03:08.315870 # ok 33 write_invalid.LCALTA.56
1943 05:03:08.320932 # ok 34 event_missing.LCALTA.56
1944 05:03:08.326435 # ok 35 event_spurious.LCALTA.56
1945 05:03:08.327012 # ok 36 get_value.LCALTA.55
1946 05:03:08.327385 # # LCALTA.55 TDMIN_C SRC SEL
1947 05:03:08.343139 # o<3>[ 44.320593] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1948 05:03:08.343843 k 37 name.LCALTA.55
1949 05:03:08.348711 # ok 38 write_default.LCALTA.55
1950 05:03:08.349266 # ok 39 write_valid.LCALTA.55
1951 05:03:08.354147 # ok 40 write_invalid.LCALTA.55
1952 05:03:08.354724 # ok 41 event_missing.LCALTA.55
1953 05:03:08.359789 # ok 42 event_spurious.LCALTA.55
1954 05:03:08.360417 # ok 43 get_value.LCALTA.54
1955 05:03:08.365250 # # LCALTA.54 ACODEC Left DAC Sel
1956 05:03:08.365621 # ok 44 name.LCALTA.54
1957 05:03:08.370777 # ok 45 write_default.LCALTA.54
1958 05:03:08.371150 # ok 46 write_valid.LCALTA.54
1959 05:03:08.376451 # ok 47 write_invalid.LCALTA.54
1960 05:03:08.376876 # ok 48 event_missing.LCALTA.54
1961 05:03:08.382020 # ok 49 event_spurious.LCALTA.54
1962 05:03:08.382378 # ok 50 get_value.LCALTA.53
1963 05:03:08.387881 # # LCALTA.53 ACODEC Right DAC Sel
1964 05:03:08.388791 # ok 51 name.LCALTA.53
1965 05:03:08.389080 # ok 52 write_default.LCALTA.53
1966 05:03:08.393174 # ok 53 write_valid.LCALTA.53
1967 05:03:08.393497 # ok 54 write_invalid.LCALTA.53
1968 05:03:08.398512 # ok 55 event_missing.LCALTA.53
1969 05:03:08.404205 # ok 56 event_spurious.LCALTA.53
1970 05:03:08.404742 # ok 57 get_value.LCALTA.52
1971 05:03:08.409595 # # LCALTA.52 TOACODEC OUT EN Switch
1972 05:03:08.410087 # ok 58 name.LCALTA.52
1973 05:03:08.410535 # ok 59 write_default.LCALTA.52
1974 05:03:08.415123 # ok 60 write_valid.LCALTA.52
1975 05:03:08.415620 # ok 61 write_invalid.LCALTA.52
1976 05:03:08.420825 # ok 62 event_missing.LCALTA.52
1977 05:03:08.421368 # ok 63 event_spurious.LCALTA.52
1978 05:03:08.426350 # ok 64 get_value.LCALTA.51
1979 05:03:08.426832 # # LCALTA.51 TOACODEC SRC
1980 05:03:08.431802 # ok 65 name.LCALTA.51
1981 05:03:08.432338 # ok 66 write_default.LCALTA.51
1982 05:03:08.437376 # ok 67 write_valid.LCALTA.51
1983 05:03:08.437888 # ok 68 write_invalid.LCALTA.51
1984 05:03:08.442893 # ok 69 event_missing.LCALTA.51
1985 05:03:08.443381 # ok 70 event_spurious.LCALTA.51
1986 05:03:08.448470 # ok 71 get_value.LCALTA.50
1987 05:03:08.448972 # # LCALTA.50 TOHDMITX SPDIF SRC
1988 05:03:08.453981 # ok 72 name.LCALTA.50
1989 05:03:08.454453 # ok 73 write_default.LCALTA.50
1990 05:03:08.459494 # ok 74 write_valid.LCALTA.50
1991 05:03:08.459967 # ok 75 write_invalid.LCALTA.50
1992 05:03:08.465056 # ok 76 event_missing.LCALTA.50
1993 05:03:08.465530 # ok 77 event_spurious.LCALTA.50
1994 05:03:08.470754 # ok 78 get_value.LCALTA.49
1995 05:03:08.471274 # # LCALTA.49 TOHDMITX Switch
1996 05:03:08.476310 # ok 79 name.LCALTA.49
1997 05:03:08.476789 # ok 80 write_default.LCALTA.49
1998 05:03:08.481815 # ok 81 write_valid.LCALTA.49
1999 05:03:08.482316 # ok 82 write_invalid.LCALTA.49
2000 05:03:08.487325 # ok 83 event_missing.LCALTA.49
2001 05:03:08.487856 # ok 84 event_spurious.LCALTA.49
2002 05:03:08.492873 # ok 85 get_value.LCALTA.48
2003 05:03:08.493386 # # LCALTA.48 TOHDMITX I2S SRC
2004 05:03:08.493832 # ok 86 name.LCALTA.48
2005 05:03:08.498416 # ok 87 write_default.LCALTA.48
2006 05:03:08.498907 # ok 88 write_valid.LCALTA.48
2007 05:03:08.503929 # ok 89 write_invalid.LCALTA.48
2008 05:03:08.504459 # ok 90 event_missing.LCALTA.48
2009 05:03:08.509528 # ok 91 event_spurious.LCALTA.48
2010 05:03:08.510007 # ok 92 get_value.LCALTA.47
2011 05:03:08.515012 # # LCALTA.47 TODDR_C SRC SEL
2012 05:03:08.515489 # ok 93 name.LCALTA.47
2013 05:03:08.520583 # ok 94 write_default.LCALTA.47
2014 05:03:08.521103 # ok 95 write_valid.LCALTA.47
2015 05:03:08.526099 # ok 96 write_invalid.LCALTA.47
2016 05:03:08.526576 # ok 97 event_missing.LCALTA.47
2017 05:03:08.531767 # ok 98 event_spurious.LCALTA.47
2018 05:03:08.532289 # ok 99 get_value.LCALTA.46
2019 05:03:08.537197 # # LCALTA.46 TODDR_B SRC SEL
2020 05:03:08.537680 # ok 100 name.LCALTA.46
2021 05:03:08.542837 # ok 101 write_default.LCALTA.46
2022 05:03:08.543392 # ok 102 write_valid.LCALTA.46
2023 05:03:08.548349 # ok 103 write_invalid.LCALTA.46
2024 05:03:08.548876 # ok 104 event_missing.LCALTA.46
2025 05:03:08.553901 # ok 105 event_spurious.LCALTA.46
2026 05:03:08.554403 # ok 106 get_value.LCALTA.45
2027 05:03:08.559483 # # LCALTA.45 TODDR_A SRC SEL
2028 05:03:08.560040 # ok 107 name.LCALTA.45
2029 05:03:08.565002 # ok 108 write_default.LCALTA.45
2030 05:03:08.565524 # ok 109 write_valid.LCALTA.45
2031 05:03:08.570626 # ok 110 write_invalid.LCALTA.45
2032 05:03:08.571152 # ok 111 event_missing.LCALTA.45
2033 05:03:08.576164 # ok 112 event_spurious.LCALTA.45
2034 05:03:08.576676 # ok 113 get_value.LCALTA.44
2035 05:03:08.581670 # # LCALTA.44 FRDDR_C SINK 3 SEL
2036 05:03:08.582193 # ok 114 name.LCALTA.44
2037 05:03:08.587183 # ok 115 write_default.LCALTA.44
2038 05:03:08.587715 # ok 116 write_valid.LCALTA.44
2039 05:03:08.592866 # ok 117 write_invalid.LCALTA.44
2040 05:03:08.593392 # ok 118 event_missing.LCALTA.44
2041 05:03:08.598262 # ok 119 event_spurious.LCALTA.44
2042 05:03:08.598778 # ok 120 get_value.LCALTA.43
2043 05:03:08.603833 # # LCALTA.43 FRDDR_C SINK 2 SEL
2044 05:03:08.604412 # ok 121 name.LCALTA.43
2045 05:03:08.609375 # ok 122 write_default.LCALTA.43
2046 05:03:08.609883 # ok 123 write_valid.LCALTA.43
2047 05:03:08.614923 # ok 124 write_invalid.LCALTA.43
2048 05:03:08.615432 # ok 125 event_missing.LCALTA.43
2049 05:03:08.620486 # ok 126 event_spurious.LCALTA.43
2050 05:03:08.620995 # ok 127 get_value.LCALTA.42
2051 05:03:08.626032 # # LCALTA.42 FRDDR_C SINK 1 SEL
2052 05:03:08.626569 # ok 128 name.LCALTA.42
2053 05:03:08.631654 # ok 129 write_default.LCALTA.42
2054 05:03:08.632212 # ok 130 write_valid.LCALTA.42
2055 05:03:08.637156 # ok 131 write_invalid.LCALTA.42
2056 05:03:08.637687 # ok 132 event_missing.LCALTA.42
2057 05:03:08.642704 # ok 133 event_spurious.LCALTA.42
2058 05:03:08.643238 # ok 134 get_value.LCALTA.41
2059 05:03:08.648292 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
2060 05:03:08.648822 # ok 135 name.LCALTA.41
2061 05:03:08.653884 # ok 136 write_default.LCALTA.41
2062 05:03:08.654401 # ok 137 write_valid.LCALTA.41
2063 05:03:08.659308 # ok 138 write_invalid.LCALTA.41
2064 05:03:08.659821 # ok 139 event_missing.LCALTA.41
2065 05:03:08.664935 # ok 140 event_spurious.LCALTA.41
2066 05:03:08.670418 # ok 141 get_value.LCALTA.40
2067 05:03:08.670951 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
2068 05:03:08.675961 # ok 142 name.LCALTA.40
2069 05:03:08.676499 # ok 143 write_default.LCALTA.40
2070 05:03:08.681509 # ok 144 write_valid.LCALTA.40
2071 05:03:08.682040 # ok 145 write_invalid.LCALTA.40
2072 05:03:08.687063 # ok 146 event_missing.LCALTA.40
2073 05:03:08.687580 # ok 147 event_spurious.LCALTA.40
2074 05:03:08.692606 # ok 148 get_value.LCALTA.39
2075 05:03:08.693114 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
2076 05:03:08.698171 # ok 149 name.LCALTA.39
2077 05:03:08.698690 # ok 150 write_default.LCALTA.39
2078 05:03:08.703665 # ok 151 write_valid.LCALTA.39
2079 05:03:08.704205 # ok 152 write_invalid.LCALTA.39
2080 05:03:08.709269 # ok 153 event_missing.LCALTA.39
2081 05:03:08.709809 # ok 154 event_spurious.LCALTA.39
2082 05:03:08.714882 # ok 155 get_value.LCALTA.38
2083 05:03:08.715412 # # LCALTA.38 FRDDR_B SINK 3 SEL
2084 05:03:08.720372 # ok 156 name.LCALTA.38
2085 05:03:08.720953 # ok 157 write_default.LCALTA.38
2086 05:03:08.725825 # ok 158 write_valid.LCALTA.38
2087 05:03:08.726355 # ok 159 write_invalid.LCALTA.38
2088 05:03:08.731407 # ok 160 event_missing.LCALTA.38
2089 05:03:08.731906 # ok 161 event_spurious.LCALTA.38
2090 05:03:08.736940 # ok 162 get_value.LCALTA.37
2091 05:03:08.737469 # # LCALTA.37 FRDDR_B SINK 2 SEL
2092 05:03:08.742478 # ok 163 name.LCALTA.37
2093 05:03:08.743001 # ok 164 write_default.LCALTA.37
2094 05:03:08.748112 # ok 165 write_valid.LCALTA.37
2095 05:03:08.748694 # ok 166 write_invalid.LCALTA.37
2096 05:03:08.753717 # ok 167 event_missing.LCALTA.37
2097 05:03:08.754307 # ok 168 event_spurious.LCALTA.37
2098 05:03:08.759197 # ok 169 get_value.LCALTA.36
2099 05:03:08.759806 # # LCALTA.36 FRDDR_B SINK 1 SEL
2100 05:03:08.764739 # ok 170 name.LCALTA.36
2101 05:03:08.765121 # ok 171 write_default.LCALTA.36
2102 05:03:08.770271 # ok 172 write_valid.LCALTA.36
2103 05:03:08.770849 # ok 173 write_invalid.LCALTA.36
2104 05:03:08.775908 # ok 174 event_missing.LCALTA.36
2105 05:03:08.776516 # ok 175 event_spurious.LCALTA.36
2106 05:03:08.781334 # ok 176 get_value.LCALTA.35
2107 05:03:08.781913 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
2108 05:03:08.786877 # ok 177 name.LCALTA.35
2109 05:03:08.787475 # ok 178 write_default.LCALTA.35
2110 05:03:08.792787 # ok 179 write_valid.LCALTA.35
2111 05:03:08.793391 # ok 180 write_invalid.LCALTA.35
2112 05:03:08.798032 # ok 181 event_missing.LCALTA.35
2113 05:03:08.798586 # ok 182 event_spurious.LCALTA.35
2114 05:03:08.803527 # ok 183 get_value.LCALTA.34
2115 05:03:08.809108 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
2116 05:03:08.809669 # ok 184 name.LCALTA.34
2117 05:03:08.810118 # ok 185 write_default.LCALTA.34
2118 05:03:08.814644 # ok 186 write_valid.LCALTA.34
2119 05:03:08.815206 # ok 187 write_invalid.LCALTA.34
2120 05:03:08.820339 # ok 188 event_missing.LCALTA.34
2121 05:03:08.825651 # ok 189 event_spurious.LCALTA.34
2122 05:03:08.826208 # ok 190 get_value.LCALTA.33
2123 05:03:08.831224 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
2124 05:03:08.831737 # ok 191 name.LCALTA.33
2125 05:03:08.836858 # ok 192 write_default.LCALTA.33
2126 05:03:08.837356 # ok 193 write_valid.LCALTA.33
2127 05:03:08.842343 # ok 194 write_invalid.LCALTA.33
2128 05:03:08.842903 # ok 195 event_missing.LCALTA.33
2129 05:03:08.847860 # ok 196 event_spurious.LCALTA.33
2130 05:03:08.848391 # ok 197 get_value.LCALTA.32
2131 05:03:08.853384 # # LCALTA.32 FRDDR_A SINK 3 SEL
2132 05:03:08.853872 # ok 198 name.LCALTA.32
2133 05:03:08.858976 # ok 199 write_default.LCALTA.32
2134 05:03:08.859468 # ok 200 write_valid.LCALTA.32
2135 05:03:08.864503 # ok 201 write_invalid.LCALTA.32
2136 05:03:08.865026 # ok 202 event_missing.LCALTA.32
2137 05:03:08.870068 # ok 203 event_spurious.LCALTA.32
2138 05:03:08.870564 # ok 204 get_value.LCALTA.31
2139 05:03:08.875630 # # LCALTA.31 FRDDR_A SINK 2 SEL
2140 05:03:08.876156 # ok 205 name.LCALTA.31
2141 05:03:08.881170 # ok 206 write_default.LCALTA.31
2142 05:03:08.881662 # ok 207 write_valid.LCALTA.31
2143 05:03:08.886802 # ok 208 write_invalid.LCALTA.31
2144 05:03:08.887181 # ok 209 event_missing.LCALTA.31
2145 05:03:08.892334 # ok 210 event_spurious.LCALTA.31
2146 05:03:08.892685 # ok 211 get_value.LCALTA.30
2147 05:03:08.897856 # # LCALTA.30 FRDDR_A SINK 1 SEL
2148 05:03:08.898195 # ok 212 name.LCALTA.30
2149 05:03:08.903401 # ok 213 write_default.LCALTA.30
2150 05:03:08.903748 # ok 214 write_valid.LCALTA.30
2151 05:03:08.908901 # ok 215 write_invalid.LCALTA.30
2152 05:03:08.909249 # ok 216 event_missing.LCALTA.30
2153 05:03:08.914550 # ok 217 event_spurious.LCALTA.30
2154 05:03:08.914970 # ok 218 get_value.LCALTA.29
2155 05:03:08.920209 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2156 05:03:08.920788 # ok 219 name.LCALTA.29
2157 05:03:08.925637 # ok 220 write_default.LCALTA.29
2158 05:03:08.925994 # ok 221 write_valid.LCALTA.29
2159 05:03:08.931148 # ok 222 write_invalid.LCALTA.29
2160 05:03:08.931544 # ok 223 event_missing.LCALTA.29
2161 05:03:08.936691 # ok 224 event_spurious.LCALTA.29
2162 05:03:08.937267 # ok 225 get_value.LCALTA.28
2163 05:03:08.942217 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2164 05:03:08.942758 # ok 226 name.LCALTA.28
2165 05:03:08.947827 # ok 227 write_default.LCALTA.28
2166 05:03:08.948377 # ok 228 write_valid.LCALTA.28
2167 05:03:08.953603 # ok 229 write_invalid.LCALTA.28
2168 05:03:08.954044 # ok 230 event_missing.LCALTA.28
2169 05:03:08.958902 # ok 231 event_spurious.LCALTA.28
2170 05:03:08.959512 # ok 232 get_value.LCALTA.27
2171 05:03:08.964352 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2172 05:03:08.964857 # ok 233 name.LCALTA.27
2173 05:03:08.969882 # ok 234 write_default.LCALTA.27
2174 05:03:08.970380 # ok 235 write_valid.LCALTA.27
2175 05:03:08.975459 # ok 236 write_invalid.LCALTA.27
2176 05:03:08.980945 # ok 237 event_missing.LCALTA.27
2177 05:03:08.981466 # ok 238 event_spurious.LCALTA.27
2178 05:03:08.986583 # ok 239 get_value.LCALTA.26
2179 05:03:08.987182 # # LCALTA.26 ELD
2180 05:03:08.987634 # ok 240 name.LCALTA.26
2181 05:03:08.992129 # # ELD is not writeable
2182 05:03:08.992707 # ok 241 # SKIP write_default.LCALTA.26
2183 05:03:08.997614 # # ELD is not writeable
2184 05:03:08.998116 # ok 242 # SKIP write_valid.LCALTA.26
2185 05:03:09.003177 # # ELD is not writeable
2186 05:03:09.003726 # ok 243 # SKIP write_invalid.LCALTA.26
2187 05:03:09.008802 # ok 244 event_missing.LCALTA.26
2188 05:03:09.009312 # ok 245 event_spurious.LCALTA.26
2189 05:03:09.014278 # ok 246 get_value.LCALTA.25
2190 05:03:09.019907 # # LCALTA.25 IEC958 Playback Default
2191 05:03:09.020438 # ok 247 name.LCALTA.25
2192 05:03:09.020886 # ok 248 write_default.LCALTA.25
2193 05:03:09.025307 # ok 249 # SKIP write_valid.LCALTA.25
2194 05:03:09.030922 # ok 250 # SKIP write_invalid.LCALTA.25
2195 05:03:09.031432 # ok 251 event_missing.LCALTA.25
2196 05:03:09.036520 # ok 252 event_spurious.LCALTA.25
2197 05:03:09.037120 # ok 253 get_value.LCALTA.24
2198 05:03:09.042061 # # LCALTA.24 IEC958 Playback Mask
2199 05:03:09.042600 # ok 254 name.LCALTA.24
2200 05:03:09.047592 # # IEC958 Playback Mask is not writeable
2201 05:03:09.053067 # ok 255 # SKIP write_default.LCALTA.24
2202 05:03:09.053620 # # IEC958 Playback Mask is not writeable
2203 05:03:09.058494 # ok 256 # SKIP write_valid.LCALTA.24
2204 05:03:09.059004 # # IEC958 Playback Mask is not writeable
2205 05:03:09.064068 # ok 257 # SKIP write_invalid.LCALTA.24
2206 05:03:09.069661 # ok 258 event_missing.LCALTA.24
2207 05:03:09.070143 # ok 259 event_spurious.LCALTA.24
2208 05:03:09.075214 # ok 260 get_value.LCALTA.23
2209 05:03:09.075705 # # LCALTA.23 Playback Channel Map
2210 05:03:09.080870 # ok 261 name.LCALTA.23
2211 05:03:09.081369 # # Playback Channel Map is not writeable
2212 05:03:09.086331 # ok 262 # SKIP write_default.LCALTA.23
2213 05:03:09.091792 # # Playback Channel Map is not writeable
2214 05:03:09.092315 # ok 263 # SKIP write_valid.LCALTA.23
2215 05:03:09.097377 # # Playback Channel Map is not writeable
2216 05:03:09.102913 # ok 264 # SKIP write_invalid.LCALTA.23
2217 05:03:09.103425 # ok 265 event_missing.LCALTA.23
2218 05:03:09.108493 # ok 266 event_spurious.LCALTA.23
2219 05:03:09.109033 # ok 267 get_value.LCALTA.22
2220 05:03:09.114015 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2221 05:03:09.114514 # ok 268 name.LCALTA.22
2222 05:03:09.119566 # ok 269 write_default.LCALTA.22
2223 05:03:09.120080 # ok 270 write_valid.LCALTA.22
2224 05:03:09.125095 # ok 271 write_invalid.LCALTA.22
2225 05:03:09.125582 # ok 272 event_missing.LCALTA.22
2226 05:03:09.130707 # ok 273 event_spurious.LCALTA.22
2227 05:03:09.131227 # ok 274 get_value.LCALTA.21
2228 05:03:09.136257 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2229 05:03:09.136770 # ok 275 name.LCALTA.21
2230 05:03:09.141840 # ok 276 write_default.LCALTA.21
2231 05:03:09.142336 # ok 277 write_valid.LCALTA.21
2232 05:03:09.147340 # ok 278 write_invalid.LCALTA.21
2233 05:03:09.147906 # ok 279 event_missing.LCALTA.21
2234 05:03:09.152990 # ok 280 event_spurious.LCALTA.21
2235 05:03:09.153696 # ok 281 get_value.LCALTA.20
2236 05:03:09.158428 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2237 05:03:09.158961 # ok 282 name.LCALTA.20
2238 05:03:09.164013 # ok 283 write_default.LCALTA.20
2239 05:03:09.164557 # ok 284 write_valid.LCALTA.20
2240 05:03:09.169530 # ok 285 write_invalid.LCALTA.20
2241 05:03:09.170016 # ok 286 event_missing.LCALTA.20
2242 05:03:09.175109 # ok 287 event_spurious.LCALTA.20
2243 05:03:09.175704 # ok 288 get_value.LCALTA.19
2244 05:03:09.180603 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2245 05:03:09.181142 # ok 289 name.LCALTA.19
2246 05:03:09.186146 # ok 290 write_default.LCALTA.19
2247 05:03:09.186640 # ok 291 write_valid.LCALTA.19
2248 05:03:09.191734 # ok 292 write_invalid.LCALTA.19
2249 05:03:09.192265 # ok 293 event_missing.LCALTA.19
2250 05:03:09.197220 # ok 294 event_spurious.LCALTA.19
2251 05:03:09.202852 # ok 295 get_value.LCALTA.18
2252 05:03:09.203332 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2253 05:03:09.203773 # ok 296 name.LCALTA.18
2254 05:03:09.208328 # ok 297 write_default.LCALTA.18
2255 05:03:09.213913 # ok 298 write_valid.LCALTA.18
2256 05:03:09.214448 # ok 299 write_invalid.LCALTA.18
2257 05:03:09.219432 # ok 300 event_missing.LCALTA.18
2258 05:03:09.219953 # ok 301 event_spurious.LCALTA.18
2259 05:03:09.224977 # ok 302 get_value.LCALTA.17
2260 05:03:09.225486 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2261 05:03:09.230574 # ok 303 name.LCALTA.17
2262 05:03:09.231051 # ok 304 write_default.LCALTA.17
2263 05:03:09.236073 # ok 305 write_valid.LCALTA.17
2264 05:03:09.236556 # ok 306 write_invalid.LCALTA.17
2265 05:03:09.241582 # ok 307 event_missing.LCALTA.17
2266 05:03:09.242067 # ok 308 event_spurious.LCALTA.17
2267 05:03:09.247124 # ok 309 get_value.LCALTA.16
2268 05:03:09.247605 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2269 05:03:09.252725 # ok 310 name.LCALTA.16
2270 05:03:09.253202 # ok 311 write_default.LCALTA.16
2271 05:03:09.258255 # ok 312 write_valid.LCALTA.16
2272 05:03:09.258738 # ok 313 write_invalid.LCALTA.16
2273 05:03:09.263870 # ok 314 event_missing.LCALTA.16
2274 05:03:09.264446 # ok 315 event_spurious.LCALTA.16
2275 05:03:09.269381 # ok 316 get_value.LCALTA.15
2276 05:03:09.269906 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2277 05:03:09.274912 # ok 317 name.LCALTA.15
2278 05:03:09.275398 # ok 318 write_default.LCALTA.15
2279 05:03:09.280405 # ok 319 write_valid.LCALTA.15
2280 05:03:09.280880 # ok 320 write_invalid.LCALTA.15
2281 05:03:09.285972 # ok 321 event_missing.LCALTA.15
2282 05:03:09.286459 # ok 322 event_spurious.LCALTA.15
2283 05:03:09.291503 # ok 323 get_value.LCALTA.14
2284 05:03:09.297090 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2285 05:03:09.297568 # ok 324 name.LCALTA.14
2286 05:03:09.298011 # ok 325 write_default.LCALTA.14
2287 05:03:09.302592 # ok 326 write_valid.LCALTA.14
2288 05:03:09.308204 # ok 327 write_invalid.LCALTA.14
2289 05:03:09.308680 # ok 328 event_missing.LCALTA.14
2290 05:03:09.313692 # ok 329 event_spurious.LCALTA.14
2291 05:03:09.314169 # ok 330 get_value.LCALTA.13
2292 05:03:09.319282 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2293 05:03:09.319815 # ok 331 name.LCALTA.13
2294 05:03:09.324890 # ok 332 write_default.LCALTA.13
2295 05:03:09.325369 # ok 333 write_valid.LCALTA.13
2296 05:03:09.330357 # ok 334 write_invalid.LCALTA.13
2297 05:03:09.330881 # ok 335 event_missing.LCALTA.13
2298 05:03:09.335909 # ok 336 event_spurious.LCALTA.13
2299 05:03:09.336426 # ok 337 get_value.LCALTA.12
2300 05:03:09.341444 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2301 05:03:09.341932 # ok 338 name.LCALTA.12
2302 05:03:09.347022 # ok 339 write_default.LCALTA.12
2303 05:03:09.347499 # ok 340 write_valid.LCALTA.12
2304 05:03:09.352510 # ok 341 write_invalid.LCALTA.12
2305 05:03:09.352991 # ok 342 event_missing.LCALTA.12
2306 05:03:09.358064 # ok 343 event_spurious.LCALTA.12
2307 05:03:09.358538 # ok 344 get_value.LCALTA.11
2308 05:03:09.363573 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2309 05:03:09.364087 # ok 345 name.LCALTA.11
2310 05:03:09.369151 # ok 346 write_default.LCALTA.11
2311 05:03:09.369656 # ok 347 write_valid.LCALTA.11
2312 05:03:09.374952 # ok 348 write_invalid.LCALTA.11
2313 05:03:09.375482 # ok 349 event_missing.LCALTA.11
2314 05:03:09.380400 # ok 350 event_spurious.LCALTA.11
2315 05:03:09.380934 # ok 351 get_value.LCALTA.10
2316 05:03:09.385946 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2317 05:03:09.386436 # ok 352 name.LCALTA.10
2318 05:03:09.391363 # ok 353 write_default.LCALTA.10
2319 05:03:09.391837 # ok 354 write_valid.LCALTA.10
2320 05:03:09.396924 # ok 355 write_invalid.LCALTA.10
2321 05:03:09.397400 # ok 356 event_missing.LCALTA.10
2322 05:03:09.402464 # ok 357 event_spurious.LCALTA.10
2323 05:03:09.402958 # ok 358 get_value.LCALTA.9
2324 05:03:09.408029 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2325 05:03:09.408516 # ok 359 name.LCALTA.9
2326 05:03:09.413613 # ok 360 write_default.LCALTA.9
2327 05:03:09.414102 # ok 361 write_valid.LCALTA.9
2328 05:03:09.419121 # ok 362 write_invalid.LCALTA.9
2329 05:03:09.419606 # ok 363 event_missing.LCALTA.9
2330 05:03:09.424616 # ok 364 event_spurious.LCALTA.9
2331 05:03:09.425091 # ok 365 get_value.LCALTA.8
2332 05:03:09.430172 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2333 05:03:09.430705 # ok 366 name.LCALTA.8
2334 05:03:09.435883 # ok 367 write_default.LCALTA.8
2335 05:03:09.436394 # ok 368 write_valid.LCALTA.8
2336 05:03:09.441285 # ok 369 write_invalid.LCALTA.8
2337 05:03:09.441804 # ok 370 event_missing.LCALTA.8
2338 05:03:09.446897 # ok 371 event_spurious.LCALTA.8
2339 05:03:09.447374 # ok 372 get_value.LCALTA.7
2340 05:03:09.452384 # # LCALTA.7 ACODEC Unmute Ramp Switch
2341 05:03:09.452869 # ok 373 name.LCALTA.7
2342 05:03:09.457909 # ok 374 write_default.LCALTA.7
2343 05:03:09.458378 # ok 375 write_valid.LCALTA.7
2344 05:03:09.463517 # ok 376 write_invalid.LCALTA.7
2345 05:03:09.464040 # ok 377 event_missing.LCALTA.7
2346 05:03:09.469074 # ok 378 event_spurious.LCALTA.7
2347 05:03:09.469555 # ok 379 get_value.LCALTA.6
2348 05:03:09.474568 # # LCALTA.6 ACODEC Mute Ramp Switch
2349 05:03:09.475042 # ok 380 name.LCALTA.6
2350 05:03:09.480185 # ok 381 write_default.LCALTA.6
2351 05:03:09.480735 # ok 382 write_valid.LCALTA.6
2352 05:03:09.485679 # ok 383 write_invalid.LCALTA.6
2353 05:03:09.486165 # ok 384 event_missing.LCALTA.6
2354 05:03:09.491218 # ok 385 event_spurious.LCALTA.6
2355 05:03:09.491743 # ok 386 get_value.LCALTA.5
2356 05:03:09.496742 # # LCALTA.5 ACODEC Volume Ramp Switch
2357 05:03:09.497221 # ok 387 name.LCALTA.5
2358 05:03:09.502310 # ok 388 write_default.LCALTA.5
2359 05:03:09.502788 # ok 389 write_valid.LCALTA.5
2360 05:03:09.507905 # ok 390 write_invalid.LCALTA.5
2361 05:03:09.508421 # ok 391 event_missing.LCALTA.5
2362 05:03:09.513361 # ok 392 event_spurious.LCALTA.5
2363 05:03:09.513834 # ok 393 get_value.LCALTA.4
2364 05:03:09.518966 # # LCALTA.4 ACODEC Ramp Rate
2365 05:03:09.519441 # ok 394 name.LCALTA.4
2366 05:03:09.524451 # ok 395 write_default.LCALTA.4
2367 05:03:09.524954 # ok 396 write_valid.LCALTA.4
2368 05:03:09.530031 # ok 397 write_invalid.LCALTA.4
2369 05:03:09.530511 # ok 398 event_missing.LCALTA.4
2370 05:03:09.535674 # ok 399 event_spurious.LCALTA.4
2371 05:03:09.536195 # ok 400 get_value.LCALTA.3
2372 05:03:09.541175 # # LCALTA.3 ACODEC Playback Volume
2373 05:03:09.541709 # ok 401 name.LCALTA.3
2374 05:03:09.546687 # ok 402 write_default.LCALTA.3
2375 05:03:09.547171 # ok 403 write_valid.LCALTA.3
2376 05:03:09.552225 # ok 404 write_invalid.LCALTA.3
2377 05:03:09.552760 # ok 405 event_missing.LCALTA.3
2378 05:03:09.557898 # ok 406 event_spurious.LCALTA.3
2379 05:03:09.558383 # ok 407 get_value.LCALTA.2
2380 05:03:09.563363 # # LCALTA.2 ACODEC Playback Switch
2381 05:03:09.563943 # ok 408 name.LCALTA.2
2382 05:03:09.568980 # ok 409 write_default.LCALTA.2
2383 05:03:09.569507 # ok 410 write_valid.LCALTA.2
2384 05:03:09.574421 # ok 411 write_invalid.LCALTA.2
2385 05:03:09.574900 # ok 412 event_missing.LCALTA.2
2386 05:03:09.579936 # ok 413 event_spurious.LCALTA.2
2387 05:03:09.580446 # ok 414 get_value.LCALTA.1
2388 05:03:09.585470 # # LCALTA.1 ACODEC Playback Channel Mode
2389 05:03:09.585965 # ok 415 name.LCALTA.1
2390 05:03:09.591023 # ok 416 write_default.LCALTA.1
2391 05:03:09.591574 # ok 417 write_valid.LCALTA.1
2392 05:03:09.596615 # ok 418 write_invalid.LCALTA.1
2393 05:03:09.597184 # ok 419 event_missing.LCALTA.1
2394 05:03:09.602112 # ok 420 event_spurious.LCALTA.1
2395 05:03:09.602616 # ok 421 get_value.LCALTA.0
2396 05:03:09.607736 # # LCALTA.0 TOACODEC Lane Select
2397 05:03:09.608238 # ok 422 name.LCALTA.0
2398 05:03:09.613192 # ok 423 write_default.LCALTA.0
2399 05:03:09.613717 # ok 424 write_valid.LCALTA.0
2400 05:03:09.618899 # ok 425 write_invalid.LCALTA.0
2401 05:03:09.619385 # ok 426 event_missing.LCALTA.0
2402 05:03:09.624307 # ok 427 event_spurious.LCALTA.0
2403 05:03:09.629868 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2404 05:03:09.630346 ok 1 selftests: alsa: mixer-test
2405 05:03:09.635404 # timeout set to 45
2406 05:03:09.635881 # selftests: alsa: pcm-test
2407 05:03:09.636361 # TAP version 13
2408 05:03:09.640962 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2409 05:03:09.641443 # # LCALTA.0 - fe.dai-link-0 (*)
2410 05:03:09.646510 # # LCALTA.0 - fe.dai-link-1 (*)
2411 05:03:09.652070 # # LCALTA.0 - fe.dai-link-2 (*)
2412 05:03:09.652550 # # LCALTA.0 - fe.dai-link-3 (*)
2413 05:03:09.657616 # # LCALTA.0 - fe.dai-link-4 (*)
2414 05:03:09.658105 # # LCALTA.0 - fe.dai-link-5 (*)
2415 05:03:09.658550 # 1..42
2416 05:03:09.663147 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2417 05:03:09.668718 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2418 05:03:09.674232 # # snd_pcm_hw_params: Invalid argument
2419 05:03:09.679898 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2420 05:03:09.680409 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2421 05:03:09.685356 # # snd_pcm_hw_params: Invalid argument
2422 05:03:09.690913 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2423 05:03:09.696430 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2424 05:03:09.701978 # # snd_pcm_hw_params: Invalid argument
2425 05:03:09.707554 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2426 05:03:09.708106 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2427 05:03:09.713056 # # snd_pcm_hw_params: Invalid argument
2428 05:03:09.718631 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2429 05:03:09.724249 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2430 05:03:09.724785 # # snd_pcm_hw_params: Invalid argument
2431 05:03:09.735284 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2432 05:03:09.735814 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2433 05:03:09.740888 # # snd_pcm_hw_params: Invalid argument
2434 05:03:09.746369 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2435 05:03:09.751940 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2436 05:03:09.752495 # # snd_pcm_hw_params: Invalid argument
2437 05:03:09.757460 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2438 05:03:09.762950 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2439 05:03:09.768543 # # snd_pcm_hw_params: Invalid argument
2440 05:03:09.774073 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2441 05:03:09.779685 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2442 05:03:09.780251 # # snd_pcm_hw_params: Invalid argument
2443 05:03:09.785186 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2444 05:03:09.790725 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2445 05:03:09.796291 # # snd_pcm_hw_params: Invalid argument
2446 05:03:09.801949 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2447 05:03:09.802467 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2448 05:03:09.807401 # # snd_pcm_hw_params: Invalid argument
2449 05:03:09.812924 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2450 05:03:09.818469 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2451 05:03:09.824045 # # snd_pcm_hw_params: Invalid argument
2452 05:03:09.829590 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2453 05:03:09.830113 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2454 05:03:09.835095 # # snd_pcm_hw_params: Invalid argument
2455 05:03:09.840684 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2456 05:03:09.846191 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2457 05:03:09.851718 # # snd_pcm_hw_params: Invalid argument
2458 05:03:09.857346 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2459 05:03:09.857898 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2460 05:03:09.862955 # # snd_pcm_hw_params: Invalid argument
2461 05:03:09.868396 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2462 05:03:09.873935 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2463 05:03:09.874468 # # snd_pcm_hw_params: Invalid argument
2464 05:03:09.879431 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2465 05:03:09.885076 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2466 05:03:09.890601 # # snd_pcm_hw_params: Invalid argument
2467 05:03:09.896098 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2468 05:03:09.901725 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2469 05:03:09.902264 # # snd_pcm_hw_params: Invalid argument
2470 05:03:09.907188 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2471 05:03:09.912741 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2472 05:03:09.918327 # # snd_pcm_hw_params: Invalid argument
2473 05:03:09.923961 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2474 05:03:09.929397 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2475 05:03:09.929915 # # snd_pcm_hw_params: Invalid argument
2476 05:03:09.934935 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2477 05:03:09.940493 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2478 05:03:09.946059 # # snd_pcm_hw_params: Invalid argument
2479 05:03:09.951612 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2480 05:03:09.957157 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2481 05:03:09.957677 # # snd_pcm_hw_params: Invalid argument
2482 05:03:09.962716 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2483 05:03:09.968268 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2484 05:03:09.973774 # # snd_pcm_hw_params: Invalid argument
2485 05:03:09.979344 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2486 05:03:09.979855 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2487 05:03:09.984963 # # snd_pcm_hw_params: Invalid argument
2488 05:03:09.990394 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2489 05:03:09.995929 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2490 05:03:10.001508 # # snd_pcm_hw_params: Invalid argument
2491 05:03:10.007058 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2492 05:03:10.007585 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2493 05:03:10.012645 # # snd_pcm_hw_params: Invalid argument
2494 05:03:10.018242 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2495 05:03:10.023875 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2496 05:03:10.029472 # # snd_pcm_hw_params: Invalid argument
2497 05:03:10.035061 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2498 05:03:10.035660 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2499 05:03:10.040440 # # snd_pcm_hw_params: Invalid argument
2500 05:03:10.046148 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2501 05:03:10.051550 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2502 05:03:10.057045 # # snd_pcm_hw_params: Invalid argument
2503 05:03:10.062544 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2504 05:03:10.062950 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2505 05:03:10.068662 # # snd_pcm_hw_params: Invalid argument
2506 05:03:10.073717 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2507 05:03:10.079158 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2508 05:03:10.084732 # # snd_pcm_hw_params: Invalid argument
2509 05:03:10.090289 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2510 05:03:10.090686 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2511 05:03:10.095849 # # snd_pcm_hw_params: Invalid argument
2512 05:03:10.101408 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2513 05:03:10.107274 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2514 05:03:10.112598 # # snd_pcm_hw_params: Invalid argument
2515 05:03:10.118073 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2516 05:03:10.118473 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2517 05:03:10.124241 # # snd_pcm_hw_params: Invalid argument
2518 05:03:10.129259 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2519 05:03:10.134777 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2520 05:03:10.140333 # # snd_pcm_hw_params: Invalid argument
2521 05:03:10.145808 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2522 05:03:10.146425 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2523 05:03:10.151542 # # snd_pcm_hw_params: Invalid argument
2524 05:03:10.156916 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2525 05:03:10.162441 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2526 05:03:10.163044 # # snd_pcm_hw_params: Invalid argument
2527 05:03:10.173619 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2528 05:03:10.174303 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2529 05:03:10.179068 # # snd_pcm_hw_params: Invalid argument
2530 05:03:10.184662 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2531 05:03:10.190226 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2532 05:03:10.190800 # # snd_pcm_hw_params: Invalid argument
2533 05:03:10.195723 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2534 05:03:10.201253 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2535 05:03:10.206833 # # snd_pcm_hw_params: Invalid argument
2536 05:03:10.212410 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2537 05:03:10.217972 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2538 05:03:10.218360 # # snd_pcm_hw_params: Invalid argument
2539 05:03:10.229089 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2540 05:03:10.229709 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2541 05:03:10.234544 # # snd_pcm_hw_params: Invalid argument
2542 05:03:10.240090 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2543 05:03:10.240658 ok 2 selftests: alsa: pcm-test
2544 05:03:10.245634 # timeout set to 45
2545 05:03:10.246228 # selftests: alsa: test-pcmtest-driver
2546 05:03:10.251123 # TAP version 13
2547 05:03:10.251480 # 1..5
2548 05:03:10.251754 # # Starting 5 tests from 1 test cases.
2549 05:03:10.256705 # # RUN pcmtest.playback ...
2550 05:03:10.262212 # # SKIP Can't read patterns. Probably, module isn't loaded
2551 05:03:10.267713 # # OK pcmtest.playback
2552 05:03:10.273271 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2553 05:03:10.278814 # # RUN pcmtest.capture ...
2554 05:03:10.284337 # # SKIP Can't read patterns. Probably, module isn't loaded
2555 05:03:10.284743 # # OK pcmtest.capture
2556 05:03:10.295605 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2557 05:03:10.296026 # # RUN pcmtest.ni_capture ...
2558 05:03:10.301028 # # SKIP Can't read patterns. Probably, module isn't loaded
2559 05:03:10.306782 # # OK pcmtest.ni_capture
2560 05:03:10.312319 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2561 05:03:10.317756 # # RUN pcmtest.ni_playback ...
2562 05:03:10.323369 # # SKIP Can't read patterns. Probably, module isn't loaded
2563 05:03:10.330480 # # OK pcmtest.ni_playback
2564 05:03:10.334323 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2565 05:03:10.339807 # # RUN pcmtest.reset_ioctl ...
2566 05:03:10.345465 # # SKIP Can't read patterns. Probably, module isn't loaded
2567 05:03:10.345909 # # OK pcmtest.reset_ioctl
2568 05:03:10.356687 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2569 05:03:10.357370 # # PASSED: 5 / 5 tests passed.
2570 05:03:10.362312 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2571 05:03:10.367657 ok 3 selftests: alsa: test-pcmtest-driver
2572 05:03:10.368310 # timeout set to 45
2573 05:03:10.373311 # selftests: alsa: utimer-test
2574 05:03:10.373763 # TAP version 13
2575 05:03:10.373982 # 1..2
2576 05:03:10.378770 # # Starting 2 tests from 2 test cases.
2577 05:03:10.384397 # # RUN global.wrong_timers_test ...
2578 05:03:10.385184 # # OK global.wrong_timers_test
2579 05:03:10.389933 # ok 1 global.wrong_timers_test
2580 05:03:10.390723 # # RUN timer_f.utimer ...
2581 05:03:10.400968 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2582 05:03:10.406503 # # utimer: Test terminated by assertion
2583 05:03:10.407079 # # FAIL timer_f.utimer
2584 05:03:10.413088 # not ok 2 timer_f.utimer
2585 05:03:10.413591 # # FAILED: 1 / 2 tests passed.
2586 05:03:10.417681 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2587 05:03:10.422521 not ok 4 selftests: alsa: utimer-test # exit=1
2588 05:03:11.024017 alsa_mixer-test_get_value_LCALTA_60 pass
2589 05:03:11.029421 alsa_mixer-test_name_LCALTA_60 pass
2590 05:03:11.029911 alsa_mixer-test_write_default_LCALTA_60 pass
2591 05:03:11.035083 alsa_mixer-test_write_valid_LCALTA_60 pass
2592 05:03:11.040520 alsa_mixer-test_write_invalid_LCALTA_60 pass
2593 05:03:11.046067 alsa_mixer-test_event_missing_LCALTA_60 pass
2594 05:03:11.046460 alsa_mixer-test_event_spurious_LCALTA_60 pass
2595 05:03:11.051605 alsa_mixer-test_get_value_LCALTA_59 pass
2596 05:03:11.057124 alsa_mixer-test_name_LCALTA_59 pass
2597 05:03:11.057597 alsa_mixer-test_write_default_LCALTA_59 pass
2598 05:03:11.062669 alsa_mixer-test_write_valid_LCALTA_59 pass
2599 05:03:11.068252 alsa_mixer-test_write_invalid_LCALTA_59 pass
2600 05:03:11.068643 alsa_mixer-test_event_missing_LCALTA_59 pass
2601 05:03:11.073750 alsa_mixer-test_event_spurious_LCALTA_59 pass
2602 05:03:11.079296 alsa_mixer-test_get_value_LCALTA_58 pass
2603 05:03:11.079686 alsa_mixer-test_name_LCALTA_58 pass
2604 05:03:11.084895 alsa_mixer-test_write_default_LCALTA_58 pass
2605 05:03:11.090425 alsa_mixer-test_write_valid_LCALTA_58 pass
2606 05:03:11.090879 alsa_mixer-test_write_invalid_LCALTA_58 pass
2607 05:03:11.096107 alsa_mixer-test_event_missing_LCALTA_58 pass
2608 05:03:11.101583 alsa_mixer-test_event_spurious_LCALTA_58 pass
2609 05:03:11.107178 alsa_mixer-test_get_value_LCALTA_57 pass
2610 05:03:11.107677 alsa_mixer-test_name_LCALTA_57 pass
2611 05:03:11.113074 alsa_mixer-test_write_default_LCALTA_57 pass
2612 05:03:11.118191 alsa_mixer-test_write_valid_LCALTA_57 pass
2613 05:03:11.118751 alsa_mixer-test_write_invalid_LCALTA_57 pass
2614 05:03:11.123788 alsa_mixer-test_event_missing_LCALTA_57 pass
2615 05:03:11.129329 alsa_mixer-test_event_spurious_LCALTA_57 pass
2616 05:03:11.129730 alsa_mixer-test_get_value_LCALTA_56 pass
2617 05:03:11.134972 alsa_mixer-test_name_LCALTA_56 pass
2618 05:03:11.140497 alsa_mixer-test_write_default_LCALTA_56 pass
2619 05:03:11.140938 alsa_mixer-test_write_valid_LCALTA_56 pass
2620 05:03:11.146162 alsa_mixer-test_write_invalid_LCALTA_56 pass
2621 05:03:11.151608 alsa_mixer-test_event_missing_LCALTA_56 pass
2622 05:03:11.157218 alsa_mixer-test_event_spurious_LCALTA_56 pass
2623 05:03:11.157621 alsa_mixer-test_get_value_LCALTA_55 pass
2624 05:03:11.162694 alsa_mixer-test_name_LCALTA_55 pass
2625 05:03:11.168230 alsa_mixer-test_write_default_LCALTA_55 pass
2626 05:03:11.168734 alsa_mixer-test_write_valid_LCALTA_55 pass
2627 05:03:11.173702 alsa_mixer-test_write_invalid_LCALTA_55 pass
2628 05:03:11.179278 alsa_mixer-test_event_missing_LCALTA_55 pass
2629 05:03:11.179781 alsa_mixer-test_event_spurious_LCALTA_55 pass
2630 05:03:11.184931 alsa_mixer-test_get_value_LCALTA_54 pass
2631 05:03:11.190582 alsa_mixer-test_name_LCALTA_54 pass
2632 05:03:11.191381 alsa_mixer-test_write_default_LCALTA_54 pass
2633 05:03:11.196637 alsa_mixer-test_write_valid_LCALTA_54 pass
2634 05:03:11.201459 alsa_mixer-test_write_invalid_LCALTA_54 pass
2635 05:03:11.201851 alsa_mixer-test_event_missing_LCALTA_54 pass
2636 05:03:11.206967 alsa_mixer-test_event_spurious_LCALTA_54 pass
2637 05:03:11.212573 alsa_mixer-test_get_value_LCALTA_53 pass
2638 05:03:11.212987 alsa_mixer-test_name_LCALTA_53 pass
2639 05:03:11.218171 alsa_mixer-test_write_default_LCALTA_53 pass
2640 05:03:11.223833 alsa_mixer-test_write_valid_LCALTA_53 pass
2641 05:03:11.229173 alsa_mixer-test_write_invalid_LCALTA_53 pass
2642 05:03:11.229559 alsa_mixer-test_event_missing_LCALTA_53 pass
2643 05:03:11.234620 alsa_mixer-test_event_spurious_LCALTA_53 pass
2644 05:03:11.240404 alsa_mixer-test_get_value_LCALTA_52 pass
2645 05:03:11.240872 alsa_mixer-test_name_LCALTA_52 pass
2646 05:03:11.245813 alsa_mixer-test_write_default_LCALTA_52 pass
2647 05:03:11.251278 alsa_mixer-test_write_valid_LCALTA_52 pass
2648 05:03:11.251638 alsa_mixer-test_write_invalid_LCALTA_52 pass
2649 05:03:11.256875 alsa_mixer-test_event_missing_LCALTA_52 pass
2650 05:03:11.262411 alsa_mixer-test_event_spurious_LCALTA_52 pass
2651 05:03:11.262827 alsa_mixer-test_get_value_LCALTA_51 pass
2652 05:03:11.267967 alsa_mixer-test_name_LCALTA_51 pass
2653 05:03:11.273493 alsa_mixer-test_write_default_LCALTA_51 pass
2654 05:03:11.273866 alsa_mixer-test_write_valid_LCALTA_51 pass
2655 05:03:11.279196 alsa_mixer-test_write_invalid_LCALTA_51 pass
2656 05:03:11.284620 alsa_mixer-test_event_missing_LCALTA_51 pass
2657 05:03:11.290319 alsa_mixer-test_event_spurious_LCALTA_51 pass
2658 05:03:11.290750 alsa_mixer-test_get_value_LCALTA_50 pass
2659 05:03:11.295837 alsa_mixer-test_name_LCALTA_50 pass
2660 05:03:11.301242 alsa_mixer-test_write_default_LCALTA_50 pass
2661 05:03:11.301649 alsa_mixer-test_write_valid_LCALTA_50 pass
2662 05:03:11.307158 alsa_mixer-test_write_invalid_LCALTA_50 pass
2663 05:03:11.313027 alsa_mixer-test_event_missing_LCALTA_50 pass
2664 05:03:11.313470 alsa_mixer-test_event_spurious_LCALTA_50 pass
2665 05:03:11.317905 alsa_mixer-test_get_value_LCALTA_49 pass
2666 05:03:11.323434 alsa_mixer-test_name_LCALTA_49 pass
2667 05:03:11.323855 alsa_mixer-test_write_default_LCALTA_49 pass
2668 05:03:11.329072 alsa_mixer-test_write_valid_LCALTA_49 pass
2669 05:03:11.334591 alsa_mixer-test_write_invalid_LCALTA_49 pass
2670 05:03:11.340235 alsa_mixer-test_event_missing_LCALTA_49 pass
2671 05:03:11.340648 alsa_mixer-test_event_spurious_LCALTA_49 pass
2672 05:03:11.345699 alsa_mixer-test_get_value_LCALTA_48 pass
2673 05:03:11.346111 alsa_mixer-test_name_LCALTA_48 pass
2674 05:03:11.351185 alsa_mixer-test_write_default_LCALTA_48 pass
2675 05:03:11.356735 alsa_mixer-test_write_valid_LCALTA_48 pass
2676 05:03:11.362339 alsa_mixer-test_write_invalid_LCALTA_48 pass
2677 05:03:11.362768 alsa_mixer-test_event_missing_LCALTA_48 pass
2678 05:03:11.367897 alsa_mixer-test_event_spurious_LCALTA_48 pass
2679 05:03:11.373403 alsa_mixer-test_get_value_LCALTA_47 pass
2680 05:03:11.373842 alsa_mixer-test_name_LCALTA_47 pass
2681 05:03:11.378966 alsa_mixer-test_write_default_LCALTA_47 pass
2682 05:03:11.384484 alsa_mixer-test_write_valid_LCALTA_47 pass
2683 05:03:11.384891 alsa_mixer-test_write_invalid_LCALTA_47 pass
2684 05:03:11.390052 alsa_mixer-test_event_missing_LCALTA_47 pass
2685 05:03:11.395588 alsa_mixer-test_event_spurious_LCALTA_47 pass
2686 05:03:11.401199 alsa_mixer-test_get_value_LCALTA_46 pass
2687 05:03:11.401597 alsa_mixer-test_name_LCALTA_46 pass
2688 05:03:11.406645 alsa_mixer-test_write_default_LCALTA_46 pass
2689 05:03:11.412249 alsa_mixer-test_write_valid_LCALTA_46 pass
2690 05:03:11.412664 alsa_mixer-test_write_invalid_LCALTA_46 pass
2691 05:03:11.417796 alsa_mixer-test_event_missing_LCALTA_46 pass
2692 05:03:11.423333 alsa_mixer-test_event_spurious_LCALTA_46 pass
2693 05:03:11.423717 alsa_mixer-test_get_value_LCALTA_45 pass
2694 05:03:11.428888 alsa_mixer-test_name_LCALTA_45 pass
2695 05:03:11.434525 alsa_mixer-test_write_default_LCALTA_45 pass
2696 05:03:11.435212 alsa_mixer-test_write_valid_LCALTA_45 pass
2697 05:03:11.439940 alsa_mixer-test_write_invalid_LCALTA_45 pass
2698 05:03:11.446177 alsa_mixer-test_event_missing_LCALTA_45 pass
2699 05:03:11.446878 alsa_mixer-test_event_spurious_LCALTA_45 pass
2700 05:03:11.451004 alsa_mixer-test_get_value_LCALTA_44 pass
2701 05:03:11.456572 alsa_mixer-test_name_LCALTA_44 pass
2702 05:03:11.456966 alsa_mixer-test_write_default_LCALTA_44 pass
2703 05:03:11.462226 alsa_mixer-test_write_valid_LCALTA_44 pass
2704 05:03:11.467657 alsa_mixer-test_write_invalid_LCALTA_44 pass
2705 05:03:11.473190 alsa_mixer-test_event_missing_LCALTA_44 pass
2706 05:03:11.473592 alsa_mixer-test_event_spurious_LCALTA_44 pass
2707 05:03:11.478750 alsa_mixer-test_get_value_LCALTA_43 pass
2708 05:03:11.484439 alsa_mixer-test_name_LCALTA_43 pass
2709 05:03:11.484822 alsa_mixer-test_write_default_LCALTA_43 pass
2710 05:03:11.489835 alsa_mixer-test_write_valid_LCALTA_43 pass
2711 05:03:11.495391 alsa_mixer-test_write_invalid_LCALTA_43 pass
2712 05:03:11.495904 alsa_mixer-test_event_missing_LCALTA_43 pass
2713 05:03:11.501025 alsa_mixer-test_event_spurious_LCALTA_43 pass
2714 05:03:11.506533 alsa_mixer-test_get_value_LCALTA_42 pass
2715 05:03:11.507138 alsa_mixer-test_name_LCALTA_42 pass
2716 05:03:11.512093 alsa_mixer-test_write_default_LCALTA_42 pass
2717 05:03:11.517623 alsa_mixer-test_write_valid_LCALTA_42 pass
2718 05:03:11.518194 alsa_mixer-test_write_invalid_LCALTA_42 pass
2719 05:03:11.523147 alsa_mixer-test_event_missing_LCALTA_42 pass
2720 05:03:11.528647 alsa_mixer-test_event_spurious_LCALTA_42 pass
2721 05:03:11.534136 alsa_mixer-test_get_value_LCALTA_41 pass
2722 05:03:11.534665 alsa_mixer-test_name_LCALTA_41 pass
2723 05:03:11.539824 alsa_mixer-test_write_default_LCALTA_41 pass
2724 05:03:11.545258 alsa_mixer-test_write_valid_LCALTA_41 pass
2725 05:03:11.545831 alsa_mixer-test_write_invalid_LCALTA_41 pass
2726 05:03:11.550770 alsa_mixer-test_event_missing_LCALTA_41 pass
2727 05:03:11.556336 alsa_mixer-test_event_spurious_LCALTA_41 pass
2728 05:03:11.556870 alsa_mixer-test_get_value_LCALTA_40 pass
2729 05:03:11.561885 alsa_mixer-test_name_LCALTA_40 pass
2730 05:03:11.567939 alsa_mixer-test_write_default_LCALTA_40 pass
2731 05:03:11.568556 alsa_mixer-test_write_valid_LCALTA_40 pass
2732 05:03:11.573281 alsa_mixer-test_write_invalid_LCALTA_40 pass
2733 05:03:11.578567 alsa_mixer-test_event_missing_LCALTA_40 pass
2734 05:03:11.584232 alsa_mixer-test_event_spurious_LCALTA_40 pass
2735 05:03:11.584779 alsa_mixer-test_get_value_LCALTA_39 pass
2736 05:03:11.590434 alsa_mixer-test_name_LCALTA_39 pass
2737 05:03:11.595740 alsa_mixer-test_write_default_LCALTA_39 pass
2738 05:03:11.596189 alsa_mixer-test_write_valid_LCALTA_39 pass
2739 05:03:11.600822 alsa_mixer-test_write_invalid_LCALTA_39 pass
2740 05:03:11.606228 alsa_mixer-test_event_missing_LCALTA_39 pass
2741 05:03:11.606540 alsa_mixer-test_event_spurious_LCALTA_39 pass
2742 05:03:11.611775 alsa_mixer-test_get_value_LCALTA_38 pass
2743 05:03:11.617294 alsa_mixer-test_name_LCALTA_38 pass
2744 05:03:11.617583 alsa_mixer-test_write_default_LCALTA_38 pass
2745 05:03:11.622871 alsa_mixer-test_write_valid_LCALTA_38 pass
2746 05:03:11.628424 alsa_mixer-test_write_invalid_LCALTA_38 pass
2747 05:03:11.628747 alsa_mixer-test_event_missing_LCALTA_38 pass
2748 05:03:11.633978 alsa_mixer-test_event_spurious_LCALTA_38 pass
2749 05:03:11.639540 alsa_mixer-test_get_value_LCALTA_37 pass
2750 05:03:11.639883 alsa_mixer-test_name_LCALTA_37 pass
2751 05:03:11.645174 alsa_mixer-test_write_default_LCALTA_37 pass
2752 05:03:11.650664 alsa_mixer-test_write_valid_LCALTA_37 pass
2753 05:03:11.656202 alsa_mixer-test_write_invalid_LCALTA_37 pass
2754 05:03:11.656739 alsa_mixer-test_event_missing_LCALTA_37 pass
2755 05:03:11.661783 alsa_mixer-test_event_spurious_LCALTA_37 pass
2756 05:03:11.667270 alsa_mixer-test_get_value_LCALTA_36 pass
2757 05:03:11.667809 alsa_mixer-test_name_LCALTA_36 pass
2758 05:03:11.672818 alsa_mixer-test_write_default_LCALTA_36 pass
2759 05:03:11.678394 alsa_mixer-test_write_valid_LCALTA_36 pass
2760 05:03:11.678980 alsa_mixer-test_write_invalid_LCALTA_36 pass
2761 05:03:11.683926 alsa_mixer-test_event_missing_LCALTA_36 pass
2762 05:03:11.689494 alsa_mixer-test_event_spurious_LCALTA_36 pass
2763 05:03:11.690076 alsa_mixer-test_get_value_LCALTA_35 pass
2764 05:03:11.695080 alsa_mixer-test_name_LCALTA_35 pass
2765 05:03:11.700605 alsa_mixer-test_write_default_LCALTA_35 pass
2766 05:03:11.701192 alsa_mixer-test_write_valid_LCALTA_35 pass
2767 05:03:11.706195 alsa_mixer-test_write_invalid_LCALTA_35 pass
2768 05:03:11.711629 alsa_mixer-test_event_missing_LCALTA_35 pass
2769 05:03:11.717237 alsa_mixer-test_event_spurious_LCALTA_35 pass
2770 05:03:11.717763 alsa_mixer-test_get_value_LCALTA_34 pass
2771 05:03:11.722864 alsa_mixer-test_name_LCALTA_34 pass
2772 05:03:11.728357 alsa_mixer-test_write_default_LCALTA_34 pass
2773 05:03:11.728942 alsa_mixer-test_write_valid_LCALTA_34 pass
2774 05:03:11.733894 alsa_mixer-test_write_invalid_LCALTA_34 pass
2775 05:03:11.739395 alsa_mixer-test_event_missing_LCALTA_34 pass
2776 05:03:11.739912 alsa_mixer-test_event_spurious_LCALTA_34 pass
2777 05:03:11.744968 alsa_mixer-test_get_value_LCALTA_33 pass
2778 05:03:11.750578 alsa_mixer-test_name_LCALTA_33 pass
2779 05:03:11.751191 alsa_mixer-test_write_default_LCALTA_33 pass
2780 05:03:11.756119 alsa_mixer-test_write_valid_LCALTA_33 pass
2781 05:03:11.761629 alsa_mixer-test_write_invalid_LCALTA_33 pass
2782 05:03:11.767245 alsa_mixer-test_event_missing_LCALTA_33 pass
2783 05:03:11.767867 alsa_mixer-test_event_spurious_LCALTA_33 pass
2784 05:03:11.772693 alsa_mixer-test_get_value_LCALTA_32 pass
2785 05:03:11.773200 alsa_mixer-test_name_LCALTA_32 pass
2786 05:03:11.778257 alsa_mixer-test_write_default_LCALTA_32 pass
2787 05:03:11.783776 alsa_mixer-test_write_valid_LCALTA_32 pass
2788 05:03:11.789356 alsa_mixer-test_write_invalid_LCALTA_32 pass
2789 05:03:11.789930 alsa_mixer-test_event_missing_LCALTA_32 pass
2790 05:03:11.794924 alsa_mixer-test_event_spurious_LCALTA_32 pass
2791 05:03:11.800447 alsa_mixer-test_get_value_LCALTA_31 pass
2792 05:03:11.801004 alsa_mixer-test_name_LCALTA_31 pass
2793 05:03:11.805987 alsa_mixer-test_write_default_LCALTA_31 pass
2794 05:03:11.811544 alsa_mixer-test_write_valid_LCALTA_31 pass
2795 05:03:11.812098 alsa_mixer-test_write_invalid_LCALTA_31 pass
2796 05:03:11.817093 alsa_mixer-test_event_missing_LCALTA_31 pass
2797 05:03:11.822628 alsa_mixer-test_event_spurious_LCALTA_31 pass
2798 05:03:11.828240 alsa_mixer-test_get_value_LCALTA_30 pass
2799 05:03:11.828795 alsa_mixer-test_name_LCALTA_30 pass
2800 05:03:11.833745 alsa_mixer-test_write_default_LCALTA_30 pass
2801 05:03:11.839251 alsa_mixer-test_write_valid_LCALTA_30 pass
2802 05:03:11.839818 alsa_mixer-test_write_invalid_LCALTA_30 pass
2803 05:03:11.844814 alsa_mixer-test_event_missing_LCALTA_30 pass
2804 05:03:11.850416 alsa_mixer-test_event_spurious_LCALTA_30 pass
2805 05:03:11.850966 alsa_mixer-test_get_value_LCALTA_29 pass
2806 05:03:11.855946 alsa_mixer-test_name_LCALTA_29 pass
2807 05:03:11.861444 alsa_mixer-test_write_default_LCALTA_29 pass
2808 05:03:11.861994 alsa_mixer-test_write_valid_LCALTA_29 pass
2809 05:03:11.866984 alsa_mixer-test_write_invalid_LCALTA_29 pass
2810 05:03:11.872503 alsa_mixer-test_event_missing_LCALTA_29 pass
2811 05:03:11.873013 alsa_mixer-test_event_spurious_LCALTA_29 pass
2812 05:03:11.878088 alsa_mixer-test_get_value_LCALTA_28 pass
2813 05:03:11.883613 alsa_mixer-test_name_LCALTA_28 pass
2814 05:03:11.884168 alsa_mixer-test_write_default_LCALTA_28 pass
2815 05:03:11.889246 alsa_mixer-test_write_valid_LCALTA_28 pass
2816 05:03:11.894782 alsa_mixer-test_write_invalid_LCALTA_28 pass
2817 05:03:11.900290 alsa_mixer-test_event_missing_LCALTA_28 pass
2818 05:03:11.900832 alsa_mixer-test_event_spurious_LCALTA_28 pass
2819 05:03:11.905835 alsa_mixer-test_get_value_LCALTA_27 pass
2820 05:03:11.911390 alsa_mixer-test_name_LCALTA_27 pass
2821 05:03:11.911959 alsa_mixer-test_write_default_LCALTA_27 pass
2822 05:03:11.916874 alsa_mixer-test_write_valid_LCALTA_27 pass
2823 05:03:11.922469 alsa_mixer-test_write_invalid_LCALTA_27 pass
2824 05:03:11.923015 alsa_mixer-test_event_missing_LCALTA_27 pass
2825 05:03:11.928006 alsa_mixer-test_event_spurious_LCALTA_27 pass
2826 05:03:11.933562 alsa_mixer-test_get_value_LCALTA_26 pass
2827 05:03:11.934126 alsa_mixer-test_name_LCALTA_26 pass
2828 05:03:11.939101 alsa_mixer-test_write_default_LCALTA_26 skip
2829 05:03:11.944634 alsa_mixer-test_write_valid_LCALTA_26 skip
2830 05:03:11.945141 alsa_mixer-test_write_invalid_LCALTA_26 skip
2831 05:03:11.950270 alsa_mixer-test_event_missing_LCALTA_26 pass
2832 05:03:11.955756 alsa_mixer-test_event_spurious_LCALTA_26 pass
2833 05:03:11.961280 alsa_mixer-test_get_value_LCALTA_25 pass
2834 05:03:11.961796 alsa_mixer-test_name_LCALTA_25 pass
2835 05:03:11.966820 alsa_mixer-test_write_default_LCALTA_25 pass
2836 05:03:11.972340 alsa_mixer-test_write_valid_LCALTA_25 skip
2837 05:03:11.972830 alsa_mixer-test_write_invalid_LCALTA_25 skip
2838 05:03:11.977906 alsa_mixer-test_event_missing_LCALTA_25 pass
2839 05:03:11.983502 alsa_mixer-test_event_spurious_LCALTA_25 pass
2840 05:03:11.984103 alsa_mixer-test_get_value_LCALTA_24 pass
2841 05:03:11.989066 alsa_mixer-test_name_LCALTA_24 pass
2842 05:03:11.994584 alsa_mixer-test_write_default_LCALTA_24 skip
2843 05:03:11.995140 alsa_mixer-test_write_valid_LCALTA_24 skip
2844 05:03:12.000116 alsa_mixer-test_write_invalid_LCALTA_24 skip
2845 05:03:12.005633 alsa_mixer-test_event_missing_LCALTA_24 pass
2846 05:03:12.011281 alsa_mixer-test_event_spurious_LCALTA_24 pass
2847 05:03:12.011814 alsa_mixer-test_get_value_LCALTA_23 pass
2848 05:03:12.016777 alsa_mixer-test_name_LCALTA_23 pass
2849 05:03:12.022483 alsa_mixer-test_write_default_LCALTA_23 skip
2850 05:03:12.023069 alsa_mixer-test_write_valid_LCALTA_23 skip
2851 05:03:12.028010 alsa_mixer-test_write_invalid_LCALTA_23 skip
2852 05:03:12.033486 alsa_mixer-test_event_missing_LCALTA_23 pass
2853 05:03:12.034047 alsa_mixer-test_event_spurious_LCALTA_23 pass
2854 05:03:12.038911 alsa_mixer-test_get_value_LCALTA_22 pass
2855 05:03:12.044447 alsa_mixer-test_name_LCALTA_22 pass
2856 05:03:12.044964 alsa_mixer-test_write_default_LCALTA_22 pass
2857 05:03:12.050016 alsa_mixer-test_write_valid_LCALTA_22 pass
2858 05:03:12.055648 alsa_mixer-test_write_invalid_LCALTA_22 pass
2859 05:03:12.056302 alsa_mixer-test_event_missing_LCALTA_22 pass
2860 05:03:12.061104 alsa_mixer-test_event_spurious_LCALTA_22 pass
2861 05:03:12.066660 alsa_mixer-test_get_value_LCALTA_21 pass
2862 05:03:12.067303 alsa_mixer-test_name_LCALTA_21 pass
2863 05:03:12.072265 alsa_mixer-test_write_default_LCALTA_21 pass
2864 05:03:12.077819 alsa_mixer-test_write_valid_LCALTA_21 pass
2865 05:03:12.083319 alsa_mixer-test_write_invalid_LCALTA_21 pass
2866 05:03:12.083913 alsa_mixer-test_event_missing_LCALTA_21 pass
2867 05:03:12.088797 alsa_mixer-test_event_spurious_LCALTA_21 pass
2868 05:03:12.094431 alsa_mixer-test_get_value_LCALTA_20 pass
2869 05:03:12.095036 alsa_mixer-test_name_LCALTA_20 pass
2870 05:03:12.100108 alsa_mixer-test_write_default_LCALTA_20 pass
2871 05:03:12.105507 alsa_mixer-test_write_valid_LCALTA_20 pass
2872 05:03:12.106078 alsa_mixer-test_write_invalid_LCALTA_20 pass
2873 05:03:12.111133 alsa_mixer-test_event_missing_LCALTA_20 pass
2874 05:03:12.116615 alsa_mixer-test_event_spurious_LCALTA_20 pass
2875 05:03:12.117269 alsa_mixer-test_get_value_LCALTA_19 pass
2876 05:03:12.122292 alsa_mixer-test_name_LCALTA_19 pass
2877 05:03:12.127738 alsa_mixer-test_write_default_LCALTA_19 pass
2878 05:03:12.128390 alsa_mixer-test_write_valid_LCALTA_19 pass
2879 05:03:12.133244 alsa_mixer-test_write_invalid_LCALTA_19 pass
2880 05:03:12.138773 alsa_mixer-test_event_missing_LCALTA_19 pass
2881 05:03:12.144320 alsa_mixer-test_event_spurious_LCALTA_19 pass
2882 05:03:12.145022 alsa_mixer-test_get_value_LCALTA_18 pass
2883 05:03:12.149852 alsa_mixer-test_name_LCALTA_18 pass
2884 05:03:12.155420 alsa_mixer-test_write_default_LCALTA_18 pass
2885 05:03:12.156068 alsa_mixer-test_write_valid_LCALTA_18 pass
2886 05:03:12.161089 alsa_mixer-test_write_invalid_LCALTA_18 pass
2887 05:03:12.166507 alsa_mixer-test_event_missing_LCALTA_18 pass
2888 05:03:12.167090 alsa_mixer-test_event_spurious_LCALTA_18 pass
2889 05:03:12.172142 alsa_mixer-test_get_value_LCALTA_17 pass
2890 05:03:12.177582 alsa_mixer-test_name_LCALTA_17 pass
2891 05:03:12.178110 alsa_mixer-test_write_default_LCALTA_17 pass
2892 05:03:12.183298 alsa_mixer-test_write_valid_LCALTA_17 pass
2893 05:03:12.188769 alsa_mixer-test_write_invalid_LCALTA_17 pass
2894 05:03:12.194296 alsa_mixer-test_event_missing_LCALTA_17 pass
2895 05:03:12.194858 alsa_mixer-test_event_spurious_LCALTA_17 pass
2896 05:03:12.199826 alsa_mixer-test_get_value_LCALTA_16 pass
2897 05:03:12.200438 alsa_mixer-test_name_LCALTA_16 pass
2898 05:03:12.205370 alsa_mixer-test_write_default_LCALTA_16 pass
2899 05:03:12.210901 alsa_mixer-test_write_valid_LCALTA_16 pass
2900 05:03:12.216443 alsa_mixer-test_write_invalid_LCALTA_16 pass
2901 05:03:12.217027 alsa_mixer-test_event_missing_LCALTA_16 pass
2902 05:03:12.221995 alsa_mixer-test_event_spurious_LCALTA_16 pass
2903 05:03:12.227551 alsa_mixer-test_get_value_LCALTA_15 pass
2904 05:03:12.228162 alsa_mixer-test_name_LCALTA_15 pass
2905 05:03:12.233101 alsa_mixer-test_write_default_LCALTA_15 pass
2906 05:03:12.238581 alsa_mixer-test_write_valid_LCALTA_15 pass
2907 05:03:12.239136 alsa_mixer-test_write_invalid_LCALTA_15 pass
2908 05:03:12.244285 alsa_mixer-test_event_missing_LCALTA_15 pass
2909 05:03:12.249739 alsa_mixer-test_event_spurious_LCALTA_15 pass
2910 05:03:12.255341 alsa_mixer-test_get_value_LCALTA_14 pass
2911 05:03:12.255923 alsa_mixer-test_name_LCALTA_14 pass
2912 05:03:12.260837 alsa_mixer-test_write_default_LCALTA_14 pass
2913 05:03:12.266317 alsa_mixer-test_write_valid_LCALTA_14 pass
2914 05:03:12.266853 alsa_mixer-test_write_invalid_LCALTA_14 pass
2915 05:03:12.271865 alsa_mixer-test_event_missing_LCALTA_14 pass
2916 05:03:12.277438 alsa_mixer-test_event_spurious_LCALTA_14 pass
2917 05:03:12.278066 alsa_mixer-test_get_value_LCALTA_13 pass
2918 05:03:12.282982 alsa_mixer-test_name_LCALTA_13 pass
2919 05:03:12.288571 alsa_mixer-test_write_default_LCALTA_13 pass
2920 05:03:12.289168 alsa_mixer-test_write_valid_LCALTA_13 pass
2921 05:03:12.294046 alsa_mixer-test_write_invalid_LCALTA_13 pass
2922 05:03:12.299663 alsa_mixer-test_event_missing_LCALTA_13 pass
2923 05:03:12.300288 alsa_mixer-test_event_spurious_LCALTA_13 pass
2924 05:03:12.305309 alsa_mixer-test_get_value_LCALTA_12 pass
2925 05:03:12.310676 alsa_mixer-test_name_LCALTA_12 pass
2926 05:03:12.311196 alsa_mixer-test_write_default_LCALTA_12 pass
2927 05:03:12.316299 alsa_mixer-test_write_valid_LCALTA_12 pass
2928 05:03:12.321824 alsa_mixer-test_write_invalid_LCALTA_12 pass
2929 05:03:12.327361 alsa_mixer-test_event_missing_LCALTA_12 pass
2930 05:03:12.327957 alsa_mixer-test_event_spurious_LCALTA_12 pass
2931 05:03:12.332939 alsa_mixer-test_get_value_LCALTA_11 pass
2932 05:03:12.338389 alsa_mixer-test_name_LCALTA_11 pass
2933 05:03:12.339021 alsa_mixer-test_write_default_LCALTA_11 pass
2934 05:03:12.344033 alsa_mixer-test_write_valid_LCALTA_11 pass
2935 05:03:12.349578 alsa_mixer-test_write_invalid_LCALTA_11 pass
2936 05:03:12.350234 alsa_mixer-test_event_missing_LCALTA_11 pass
2937 05:03:12.355037 alsa_mixer-test_event_spurious_LCALTA_11 pass
2938 05:03:12.360634 alsa_mixer-test_get_value_LCALTA_10 pass
2939 05:03:12.361225 alsa_mixer-test_name_LCALTA_10 pass
2940 05:03:12.366294 alsa_mixer-test_write_default_LCALTA_10 pass
2941 05:03:12.371734 alsa_mixer-test_write_valid_LCALTA_10 pass
2942 05:03:12.372355 alsa_mixer-test_write_invalid_LCALTA_10 pass
2943 05:03:12.377335 alsa_mixer-test_event_missing_LCALTA_10 pass
2944 05:03:12.382831 alsa_mixer-test_event_spurious_LCALTA_10 pass
2945 05:03:12.388401 alsa_mixer-test_get_value_LCALTA_9 pass
2946 05:03:12.388998 alsa_mixer-test_name_LCALTA_9 pass
2947 05:03:12.393953 alsa_mixer-test_write_default_LCALTA_9 pass
2948 05:03:12.399460 alsa_mixer-test_write_valid_LCALTA_9 pass
2949 05:03:12.400048 alsa_mixer-test_write_invalid_LCALTA_9 pass
2950 05:03:12.405061 alsa_mixer-test_event_missing_LCALTA_9 pass
2951 05:03:12.410653 alsa_mixer-test_event_spurious_LCALTA_9 pass
2952 05:03:12.411263 alsa_mixer-test_get_value_LCALTA_8 pass
2953 05:03:12.416250 alsa_mixer-test_name_LCALTA_8 pass
2954 05:03:12.421676 alsa_mixer-test_write_default_LCALTA_8 pass
2955 05:03:12.422275 alsa_mixer-test_write_valid_LCALTA_8 pass
2956 05:03:12.427267 alsa_mixer-test_write_invalid_LCALTA_8 pass
2957 05:03:12.432753 alsa_mixer-test_event_missing_LCALTA_8 pass
2958 05:03:12.433333 alsa_mixer-test_event_spurious_LCALTA_8 pass
2959 05:03:12.438355 alsa_mixer-test_get_value_LCALTA_7 pass
2960 05:03:12.443855 alsa_mixer-test_name_LCALTA_7 pass
2961 05:03:12.444446 alsa_mixer-test_write_default_LCALTA_7 pass
2962 05:03:12.449415 alsa_mixer-test_write_valid_LCALTA_7 pass
2963 05:03:12.454988 alsa_mixer-test_write_invalid_LCALTA_7 pass
2964 05:03:12.455596 alsa_mixer-test_event_missing_LCALTA_7 pass
2965 05:03:12.460519 alsa_mixer-test_event_spurious_LCALTA_7 pass
2966 05:03:12.466096 alsa_mixer-test_get_value_LCALTA_6 pass
2967 05:03:12.466684 alsa_mixer-test_name_LCALTA_6 pass
2968 05:03:12.471536 alsa_mixer-test_write_default_LCALTA_6 pass
2969 05:03:12.477140 alsa_mixer-test_write_valid_LCALTA_6 pass
2970 05:03:12.477716 alsa_mixer-test_write_invalid_LCALTA_6 pass
2971 05:03:12.482709 alsa_mixer-test_event_missing_LCALTA_6 pass
2972 05:03:12.488331 alsa_mixer-test_event_spurious_LCALTA_6 pass
2973 05:03:12.488905 alsa_mixer-test_get_value_LCALTA_5 pass
2974 05:03:12.493826 alsa_mixer-test_name_LCALTA_5 pass
2975 05:03:12.499356 alsa_mixer-test_write_default_LCALTA_5 pass
2976 05:03:12.500042 alsa_mixer-test_write_valid_LCALTA_5 pass
2977 05:03:12.504874 alsa_mixer-test_write_invalid_LCALTA_5 pass
2978 05:03:12.510461 alsa_mixer-test_event_missing_LCALTA_5 pass
2979 05:03:12.511383 alsa_mixer-test_event_spurious_LCALTA_5 pass
2980 05:03:12.515977 alsa_mixer-test_get_value_LCALTA_4 pass
2981 05:03:12.521563 alsa_mixer-test_name_LCALTA_4 pass
2982 05:03:12.522181 alsa_mixer-test_write_default_LCALTA_4 pass
2983 05:03:12.527111 alsa_mixer-test_write_valid_LCALTA_4 pass
2984 05:03:12.532591 alsa_mixer-test_write_invalid_LCALTA_4 pass
2985 05:03:12.533176 alsa_mixer-test_event_missing_LCALTA_4 pass
2986 05:03:12.538202 alsa_mixer-test_event_spurious_LCALTA_4 pass
2987 05:03:12.543688 alsa_mixer-test_get_value_LCALTA_3 pass
2988 05:03:12.544394 alsa_mixer-test_name_LCALTA_3 pass
2989 05:03:12.549348 alsa_mixer-test_write_default_LCALTA_3 pass
2990 05:03:12.554827 alsa_mixer-test_write_valid_LCALTA_3 pass
2991 05:03:12.555451 alsa_mixer-test_write_invalid_LCALTA_3 pass
2992 05:03:12.560285 alsa_mixer-test_event_missing_LCALTA_3 pass
2993 05:03:12.565932 alsa_mixer-test_event_spurious_LCALTA_3 pass
2994 05:03:12.566519 alsa_mixer-test_get_value_LCALTA_2 pass
2995 05:03:12.571441 alsa_mixer-test_name_LCALTA_2 pass
2996 05:03:12.576965 alsa_mixer-test_write_default_LCALTA_2 pass
2997 05:03:12.577539 alsa_mixer-test_write_valid_LCALTA_2 pass
2998 05:03:12.582545 alsa_mixer-test_write_invalid_LCALTA_2 pass
2999 05:03:12.588026 alsa_mixer-test_event_missing_LCALTA_2 pass
3000 05:03:12.593635 alsa_mixer-test_event_spurious_LCALTA_2 pass
3001 05:03:12.594210 alsa_mixer-test_get_value_LCALTA_1 pass
3002 05:03:12.599218 alsa_mixer-test_name_LCALTA_1 pass
3003 05:03:12.599822 alsa_mixer-test_write_default_LCALTA_1 pass
3004 05:03:12.604677 alsa_mixer-test_write_valid_LCALTA_1 pass
3005 05:03:12.610363 alsa_mixer-test_write_invalid_LCALTA_1 pass
3006 05:03:12.615791 alsa_mixer-test_event_missing_LCALTA_1 pass
3007 05:03:12.616394 alsa_mixer-test_event_spurious_LCALTA_1 pass
3008 05:03:12.621312 alsa_mixer-test_get_value_LCALTA_0 pass
3009 05:03:12.621859 alsa_mixer-test_name_LCALTA_0 pass
3010 05:03:12.626943 alsa_mixer-test_write_default_LCALTA_0 pass
3011 05:03:12.632412 alsa_mixer-test_write_valid_LCALTA_0 pass
3012 05:03:12.638020 alsa_mixer-test_write_invalid_LCALTA_0 pass
3013 05:03:12.638603 alsa_mixer-test_event_missing_LCALTA_0 pass
3014 05:03:12.643553 alsa_mixer-test_event_spurious_LCALTA_0 pass
3015 05:03:12.644269 alsa_mixer-test pass
3016 05:03:12.649058 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
3017 05:03:12.654661 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
3018 05:03:12.660318 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
3019 05:03:12.665867 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
3020 05:03:12.666447 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
3021 05:03:12.671416 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
3022 05:03:12.676814 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
3023 05:03:12.682498 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
3024 05:03:12.688114 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
3025 05:03:12.693679 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
3026 05:03:12.694274 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
3027 05:03:12.699107 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
3028 05:03:12.704655 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
3029 05:03:12.710208 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
3030 05:03:12.715747 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
3031 05:03:12.721270 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
3032 05:03:12.721812 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
3033 05:03:12.726846 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
3034 05:03:12.732466 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
3035 05:03:12.737908 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
3036 05:03:12.743458 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
3037 05:03:12.749005 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
3038 05:03:12.749499 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
3039 05:03:12.754567 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
3040 05:03:12.760090 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
3041 05:03:12.765631 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
3042 05:03:12.771169 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
3043 05:03:12.776703 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
3044 05:03:12.777199 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
3045 05:03:12.782224 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
3046 05:03:12.787819 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
3047 05:03:12.793429 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
3048 05:03:12.798758 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
3049 05:03:12.804388 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
3050 05:03:12.810016 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
3051 05:03:12.810492 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
3052 05:03:12.815571 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
3053 05:03:12.821114 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
3054 05:03:12.826637 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
3055 05:03:12.832236 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
3056 05:03:12.837796 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
3057 05:03:12.838282 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
3058 05:03:12.843251 alsa_pcm-test pass
3059 05:03:12.848833 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3060 05:03:12.859864 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3061 05:03:12.865497 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3062 05:03:12.876546 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3063 05:03:12.882129 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3064 05:03:12.887667 alsa_test-pcmtest-driver pass
3065 05:03:12.893178 alsa_utimer-test_global_wrong_timers_test pass
3066 05:03:12.893667 alsa_utimer-test_timer_f_utimer fail
3067 05:03:12.898702 alsa_utimer-test fail
3068 05:03:12.899179 + ../../utils/send-to-lava.sh ./output/result.txt
3069 05:03:12.904313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
3070 05:03:12.905260 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
3072 05:03:12.915396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
3073 05:03:12.916175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
3075 05:03:12.921185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
3076 05:03:12.921991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
3078 05:03:12.946859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
3079 05:03:12.947849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
3081 05:03:12.998947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
3082 05:03:12.999842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
3084 05:03:13.049361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
3085 05:03:13.050238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
3087 05:03:13.102348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
3088 05:03:13.103199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
3090 05:03:13.162685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
3091 05:03:13.163522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
3093 05:03:13.214821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
3094 05:03:13.215669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
3096 05:03:13.271210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
3097 05:03:13.272933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
3099 05:03:13.328386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
3100 05:03:13.329279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
3102 05:03:13.406396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
3103 05:03:13.407095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
3105 05:03:13.457086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
3106 05:03:13.457892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
3108 05:03:13.519379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
3109 05:03:13.520120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
3111 05:03:13.564248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
3112 05:03:13.564909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
3114 05:03:13.623339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
3115 05:03:13.624216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
3117 05:03:13.681014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
3118 05:03:13.681817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
3120 05:03:13.727056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
3121 05:03:13.727828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
3123 05:03:13.781784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
3124 05:03:13.782562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
3126 05:03:13.837971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
3127 05:03:13.838754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
3129 05:03:13.895380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
3130 05:03:13.896190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
3132 05:03:13.950141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
3133 05:03:13.950927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
3135 05:03:14.004981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
3136 05:03:14.005772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
3138 05:03:14.052284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
3139 05:03:14.053149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
3141 05:03:14.103626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
3142 05:03:14.104499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
3144 05:03:14.163842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3145 05:03:14.164672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3147 05:03:14.216307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3148 05:03:14.217114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3150 05:03:14.266020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3151 05:03:14.266807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3153 05:03:14.316995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3154 05:03:14.317806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3156 05:03:14.369400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3157 05:03:14.370223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3159 05:03:14.422253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3160 05:03:14.423085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3162 05:03:14.473079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3163 05:03:14.473872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3165 05:03:14.521871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3166 05:03:14.522502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3168 05:03:14.579354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3169 05:03:14.579961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3171 05:03:14.627308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3172 05:03:14.628128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3174 05:03:14.680515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3175 05:03:14.681328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3177 05:03:14.734609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3178 05:03:14.735443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3180 05:03:14.788115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3181 05:03:14.788921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3183 05:03:14.840833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3184 05:03:14.841641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3186 05:03:14.894796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3187 05:03:14.895599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3189 05:03:14.953487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3190 05:03:14.954276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3192 05:03:15.004764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3193 05:03:15.005546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3195 05:03:15.049866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3196 05:03:15.050648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3198 05:03:15.097747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3199 05:03:15.098532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3201 05:03:15.149252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3202 05:03:15.150008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3204 05:03:15.206089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3205 05:03:15.206840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3207 05:03:15.259921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3208 05:03:15.260727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3210 05:03:15.316664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3211 05:03:15.317412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3213 05:03:15.373348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3214 05:03:15.374114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3216 05:03:15.430750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3217 05:03:15.431599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3219 05:03:15.487186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3220 05:03:15.488005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3222 05:03:15.542122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3223 05:03:15.543140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3225 05:03:15.597557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3226 05:03:15.598629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3228 05:03:15.654702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3229 05:03:15.655783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3231 05:03:15.706224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3232 05:03:15.707085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3234 05:03:15.762346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3235 05:03:15.763298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3237 05:03:15.821367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3238 05:03:15.822367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3240 05:03:15.875728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3241 05:03:15.876721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3243 05:03:15.933442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3244 05:03:15.934333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3246 05:03:15.986330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3247 05:03:15.987033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3249 05:03:16.043371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3250 05:03:16.044224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3252 05:03:16.101666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3253 05:03:16.102509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3255 05:03:16.162519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3256 05:03:16.163299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3258 05:03:16.209066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3259 05:03:16.210011 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3261 05:03:16.266200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3262 05:03:16.266959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3264 05:03:16.314748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3265 05:03:16.315499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3267 05:03:16.363666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3268 05:03:16.364472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3270 05:03:16.420114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3271 05:03:16.420985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3273 05:03:16.464925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3274 05:03:16.465722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3276 05:03:16.517998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3277 05:03:16.518640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3279 05:03:16.568782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3280 05:03:16.569455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3282 05:03:16.620499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3283 05:03:16.621269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3285 05:03:16.666111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3286 05:03:16.666884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3288 05:03:16.721159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3289 05:03:16.721943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3291 05:03:16.769496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3292 05:03:16.770233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3294 05:03:16.824583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3295 05:03:16.825327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3297 05:03:16.877180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3298 05:03:16.877935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3300 05:03:16.927189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3301 05:03:16.927949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3303 05:03:16.974194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3304 05:03:16.974947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3306 05:03:17.029198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3307 05:03:17.030045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3309 05:03:17.086035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3310 05:03:17.086913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3312 05:03:17.139435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3313 05:03:17.140312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3315 05:03:17.187947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3316 05:03:17.188796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3318 05:03:17.239420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3319 05:03:17.240203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3321 05:03:17.289253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3322 05:03:17.290045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3324 05:03:17.343427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3325 05:03:17.344200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3327 05:03:17.406707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3328 05:03:17.407557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3330 05:03:17.469270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3331 05:03:17.470127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3333 05:03:17.516461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3334 05:03:17.517419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3336 05:03:17.572459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3337 05:03:17.573490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3339 05:03:17.625740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3340 05:03:17.626660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3342 05:03:17.679669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3343 05:03:17.680651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3345 05:03:17.728807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3346 05:03:17.729789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3348 05:03:17.779895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3349 05:03:17.780562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3351 05:03:17.839048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3352 05:03:17.839825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3354 05:03:17.893982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3355 05:03:17.894611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3357 05:03:17.951305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3358 05:03:17.951947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3360 05:03:17.996960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3361 05:03:17.997625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3363 05:03:18.046635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3364 05:03:18.047488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3366 05:03:18.095391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3367 05:03:18.096130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3369 05:03:18.140205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3370 05:03:18.140969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3372 05:03:18.192691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3373 05:03:18.193434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3375 05:03:18.250637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3376 05:03:18.251385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3378 05:03:18.306014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3379 05:03:18.306910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3381 05:03:18.350576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3382 05:03:18.351445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3384 05:03:18.407941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3385 05:03:18.408773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3387 05:03:18.455667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3388 05:03:18.456518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3390 05:03:18.514164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3391 05:03:18.515058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3393 05:03:18.572551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3394 05:03:18.573518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3396 05:03:18.616497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3397 05:03:18.617562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3399 05:03:18.672546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3400 05:03:18.673460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3402 05:03:18.722408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3403 05:03:18.723080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3405 05:03:18.774700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3406 05:03:18.775384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3408 05:03:18.819631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3409 05:03:18.820575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3411 05:03:18.864368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3412 05:03:18.865264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3414 05:03:18.908123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3415 05:03:18.909035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3417 05:03:18.965130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3418 05:03:18.966058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3420 05:03:19.013005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3421 05:03:19.013916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3423 05:03:19.062597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3424 05:03:19.063528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3426 05:03:19.117217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3427 05:03:19.118192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3429 05:03:19.168748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3430 05:03:19.169692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3432 05:03:19.216909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3433 05:03:19.217761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3435 05:03:19.278341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3436 05:03:19.279212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3438 05:03:19.329287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3439 05:03:19.329987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3441 05:03:19.375558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3442 05:03:19.376593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3444 05:03:19.423154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3445 05:03:19.424167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3447 05:03:19.472620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3448 05:03:19.473541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3450 05:03:19.530357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3451 05:03:19.531438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3453 05:03:19.583317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3454 05:03:19.584392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3456 05:03:19.633003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3457 05:03:19.633620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3459 05:03:19.677874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3460 05:03:19.678816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3462 05:03:19.737546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3463 05:03:19.738525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3465 05:03:19.793601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3466 05:03:19.794561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3468 05:03:19.838857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3469 05:03:19.839766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3471 05:03:19.885486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3472 05:03:19.886421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3474 05:03:19.931808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3475 05:03:19.932742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3477 05:03:19.982176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3478 05:03:19.983046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3480 05:03:20.044361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3481 05:03:20.045297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3483 05:03:20.096065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3484 05:03:20.097010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3486 05:03:20.141879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3487 05:03:20.142963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3489 05:03:20.199953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3490 05:03:20.201102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3492 05:03:20.253632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3493 05:03:20.254618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3495 05:03:20.307796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3496 05:03:20.308845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3498 05:03:20.359458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3499 05:03:20.360573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3501 05:03:20.409720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3502 05:03:20.410666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3504 05:03:20.457741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3505 05:03:20.458653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3507 05:03:20.503139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3508 05:03:20.504087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3510 05:03:20.549685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3511 05:03:20.550588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3513 05:03:20.598355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3514 05:03:20.599263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3516 05:03:20.650967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3517 05:03:20.651893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3519 05:03:20.701744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3520 05:03:20.702904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3522 05:03:20.756409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3523 05:03:20.757324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3525 05:03:20.809188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3526 05:03:20.810103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3528 05:03:20.856070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3529 05:03:20.857022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3531 05:03:20.907151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3532 05:03:20.908368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3534 05:03:20.960831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3535 05:03:20.961779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3537 05:03:21.007430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3538 05:03:21.008442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3540 05:03:21.054488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3541 05:03:21.055489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3543 05:03:21.116067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3544 05:03:21.117178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3546 05:03:21.182133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3547 05:03:21.183107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3549 05:03:21.235376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3550 05:03:21.236339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3552 05:03:21.292619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3553 05:03:21.293458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3555 05:03:21.345093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3556 05:03:21.345895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3558 05:03:21.389389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3559 05:03:21.390239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3561 05:03:21.449550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3562 05:03:21.450373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3564 05:03:21.502930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3565 05:03:21.503513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3567 05:03:21.553939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3568 05:03:21.554578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3570 05:03:21.598926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3571 05:03:21.599508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3573 05:03:21.653555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3574 05:03:21.654363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3576 05:03:21.697123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3577 05:03:21.697923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3579 05:03:21.747541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3580 05:03:21.748364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3582 05:03:21.802920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3583 05:03:21.803750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3585 05:03:21.853434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3586 05:03:21.854028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3588 05:03:21.912457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3589 05:03:21.913360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3591 05:03:21.977411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3592 05:03:21.978299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3594 05:03:22.034151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3595 05:03:22.035108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3597 05:03:22.098985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3598 05:03:22.099867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3600 05:03:22.157014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3601 05:03:22.157941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3603 05:03:22.203695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3604 05:03:22.204603 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3606 05:03:22.258172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3607 05:03:22.259047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3609 05:03:22.314493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3610 05:03:22.315364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3612 05:03:22.368084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3613 05:03:22.368962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3615 05:03:22.424362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3616 05:03:22.425272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3618 05:03:22.478928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3619 05:03:22.479806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3621 05:03:22.543806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3622 05:03:22.544761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3624 05:03:22.591229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3625 05:03:22.592126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3627 05:03:22.649563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3628 05:03:22.650387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3630 05:03:22.710063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3631 05:03:22.710893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3633 05:03:22.764765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3634 05:03:22.765600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3636 05:03:22.814568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3637 05:03:22.815129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3639 05:03:22.863279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3640 05:03:22.863902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3642 05:03:22.925714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3643 05:03:22.926357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3645 05:03:22.982531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3646 05:03:22.983246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3648 05:03:23.037613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3649 05:03:23.038349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3651 05:03:23.132015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3652 05:03:23.132851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3654 05:03:23.198149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3655 05:03:23.199064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3657 05:03:23.247425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3658 05:03:23.248606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3660 05:03:23.318884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3661 05:03:23.319759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3663 05:03:23.560901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3664 05:03:23.561564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3666 05:03:23.607415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3667 05:03:23.608098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3669 05:03:23.656025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3670 05:03:23.656580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3672 05:03:23.710049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3673 05:03:23.710606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3675 05:03:23.761146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3676 05:03:23.761927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3678 05:03:23.809759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3679 05:03:23.810536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3681 05:03:23.860024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3682 05:03:23.860838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3684 05:03:23.907880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3685 05:03:23.908694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3687 05:03:23.955037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3688 05:03:23.955807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3690 05:03:24.004521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3691 05:03:24.005310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3693 05:03:24.055386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3694 05:03:24.056199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3696 05:03:24.108856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3697 05:03:24.109653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3699 05:03:24.163485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3700 05:03:24.164303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3702 05:03:24.209821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3703 05:03:24.210600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3705 05:03:24.260212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3706 05:03:24.261013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3708 05:03:24.319139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3709 05:03:24.319943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3711 05:03:24.370135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3712 05:03:24.370920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3714 05:03:24.421242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3715 05:03:24.422088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3717 05:03:24.476936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3718 05:03:24.477742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3720 05:03:24.526850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3721 05:03:24.527794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3723 05:03:24.575492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3724 05:03:24.576358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3726 05:03:24.628303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3727 05:03:24.629100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3729 05:03:24.687818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3730 05:03:24.688658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3732 05:03:24.744819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3733 05:03:24.745709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3735 05:03:24.802377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3736 05:03:24.803220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3738 05:03:24.852485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3739 05:03:24.853302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3741 05:03:24.906153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3742 05:03:24.906959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3744 05:03:24.965212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3745 05:03:24.966004 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3747 05:03:25.018244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3748 05:03:25.019111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3750 05:03:25.071968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3751 05:03:25.072824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3753 05:03:25.124533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3754 05:03:25.125326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3756 05:03:25.175727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3757 05:03:25.176573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3759 05:03:25.221359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3760 05:03:25.222164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3762 05:03:25.275191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3763 05:03:25.276044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3765 05:03:25.325156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3766 05:03:25.325983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3768 05:03:25.378173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3769 05:03:25.378938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3771 05:03:25.425713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3772 05:03:25.426544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3774 05:03:25.477011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3775 05:03:25.477929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3777 05:03:25.527806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3778 05:03:25.528692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3780 05:03:25.578242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3781 05:03:25.579263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3783 05:03:25.631456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3784 05:03:25.632644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3786 05:03:25.690043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3787 05:03:25.691395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3789 05:03:25.735963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3790 05:03:25.737037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3792 05:03:25.790682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3793 05:03:25.791671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3795 05:03:25.842710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3796 05:03:25.844024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3798 05:03:25.893566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3799 05:03:25.894595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3801 05:03:25.938206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3802 05:03:25.939028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3804 05:03:25.994692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3805 05:03:25.995490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3807 05:03:26.058950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3808 05:03:26.059775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3810 05:03:26.106032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3811 05:03:26.106845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3813 05:03:26.158718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3814 05:03:26.159541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3816 05:03:26.202649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3817 05:03:26.203461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3819 05:03:26.252822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3820 05:03:26.253616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3822 05:03:26.300349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3823 05:03:26.301163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3825 05:03:26.358286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3826 05:03:26.359091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3828 05:03:26.408910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3829 05:03:26.409905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3831 05:03:26.459744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3832 05:03:26.460653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3834 05:03:26.521061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3835 05:03:26.521922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3837 05:03:26.567320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3838 05:03:26.568098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3840 05:03:26.621337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3841 05:03:26.622089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3843 05:03:26.670042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3844 05:03:26.670824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3846 05:03:26.718879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3847 05:03:26.719631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3849 05:03:26.764517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3850 05:03:26.765276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3852 05:03:26.813519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3853 05:03:26.814327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3855 05:03:26.879243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3856 05:03:26.880030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3858 05:03:26.927571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3859 05:03:26.928347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3861 05:03:26.978223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3862 05:03:26.978961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3864 05:03:27.031265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3865 05:03:27.032057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3867 05:03:27.089424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3868 05:03:27.090162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3870 05:03:27.141570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3871 05:03:27.142336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3873 05:03:27.194845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3874 05:03:27.195593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3876 05:03:27.242929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3877 05:03:27.243678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3879 05:03:27.294913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3880 05:03:27.295660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3882 05:03:27.340079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3883 05:03:27.340848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3885 05:03:27.393779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3886 05:03:27.394564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3888 05:03:27.441202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3889 05:03:27.441998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3891 05:03:27.493968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3892 05:03:27.494734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3894 05:03:27.537319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3895 05:03:27.538096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3897 05:03:27.600421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3898 05:03:27.601222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3900 05:03:27.649918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3901 05:03:27.650706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3903 05:03:27.701488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3904 05:03:27.702201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3906 05:03:27.759118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3907 05:03:27.759834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3909 05:03:27.806814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3910 05:03:27.807543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3912 05:03:27.855268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3913 05:03:27.855998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3915 05:03:27.913679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3916 05:03:27.914462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3918 05:03:27.959595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3919 05:03:27.960406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3921 05:03:28.004824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3922 05:03:28.005597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3924 05:03:28.061324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3925 05:03:28.062151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3927 05:03:28.112279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3928 05:03:28.113049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3930 05:03:28.168418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3931 05:03:28.169180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3933 05:03:28.237598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3934 05:03:28.238365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3936 05:03:28.282345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3937 05:03:28.283081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3939 05:03:28.328693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3940 05:03:28.329447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3942 05:03:28.375361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3943 05:03:28.376115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3945 05:03:28.423060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3946 05:03:28.423904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3948 05:03:28.475931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3949 05:03:28.476714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3951 05:03:28.529194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3952 05:03:28.529959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3954 05:03:28.582194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3955 05:03:28.582963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3957 05:03:28.629251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3958 05:03:28.629992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3960 05:03:28.682756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3961 05:03:28.683508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3963 05:03:28.735469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3964 05:03:28.736212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3966 05:03:28.780928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3967 05:03:28.781669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3969 05:03:28.827180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3970 05:03:28.827947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3972 05:03:28.883193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3973 05:03:28.883966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3975 05:03:28.932529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3976 05:03:28.933295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3978 05:03:28.985627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3979 05:03:28.986400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3981 05:03:29.043146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3982 05:03:29.044036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3984 05:03:29.098765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3985 05:03:29.099533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3987 05:03:29.158462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3988 05:03:29.159229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3990 05:03:29.208569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3991 05:03:29.209309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3993 05:03:29.270895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3994 05:03:29.271647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3996 05:03:29.326042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3997 05:03:29.326794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3999 05:03:29.368901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
4000 05:03:29.369662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
4002 05:03:29.416029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
4003 05:03:29.416882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
4005 05:03:29.472852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
4006 05:03:29.473698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
4008 05:03:29.523240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
4009 05:03:29.524056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
4011 05:03:29.571510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
4012 05:03:29.572341 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
4014 05:03:29.623870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
4015 05:03:29.624720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
4017 05:03:29.675945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
4018 05:03:29.676751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
4020 05:03:29.729742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
4021 05:03:29.730476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
4023 05:03:29.786806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
4024 05:03:29.787538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
4026 05:03:29.837088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
4027 05:03:29.837834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
4029 05:03:29.882468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
4030 05:03:29.883226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
4032 05:03:29.936202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
4033 05:03:29.936946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
4035 05:03:29.988885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
4036 05:03:29.989622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
4038 05:03:30.042424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
4039 05:03:30.043186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
4041 05:03:30.090359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
4042 05:03:30.091086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
4044 05:03:30.141189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
4045 05:03:30.141933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
4047 05:03:30.198673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
4048 05:03:30.199413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
4050 05:03:30.245435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
4051 05:03:30.246182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
4053 05:03:30.307363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
4054 05:03:30.308105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
4056 05:03:30.365357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
4057 05:03:30.366093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
4059 05:03:30.416463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
4060 05:03:30.417299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
4062 05:03:30.469717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
4063 05:03:30.470488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
4065 05:03:30.522044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
4066 05:03:30.522851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
4068 05:03:30.575324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
4069 05:03:30.576107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
4071 05:03:30.629807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
4072 05:03:30.630769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
4074 05:03:30.679434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
4075 05:03:30.680407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
4077 05:03:30.726191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
4078 05:03:30.727125 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
4080 05:03:30.789786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
4081 05:03:30.790706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
4083 05:03:30.840251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
4084 05:03:30.841096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
4086 05:03:30.896697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
4087 05:03:30.897512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
4089 05:03:30.951256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
4090 05:03:30.952070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
4092 05:03:31.006359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
4093 05:03:31.007136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
4095 05:03:31.061193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
4096 05:03:31.061976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
4098 05:03:31.119593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
4099 05:03:31.120381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
4101 05:03:31.170903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
4102 05:03:31.171718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
4104 05:03:31.224558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
4105 05:03:31.225316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
4107 05:03:31.276123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
4108 05:03:31.276897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
4110 05:03:31.340225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
4111 05:03:31.340998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
4113 05:03:31.392493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
4114 05:03:31.393249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
4116 05:03:31.436337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
4117 05:03:31.437182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
4119 05:03:31.486698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
4120 05:03:31.487469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
4122 05:03:31.544566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
4123 05:03:31.545353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
4125 05:03:31.598135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
4126 05:03:31.598900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
4128 05:03:31.644756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
4129 05:03:31.645520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
4131 05:03:31.690336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
4132 05:03:31.691157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
4134 05:03:31.751784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
4135 05:03:31.752704 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
4137 05:03:31.801666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
4138 05:03:31.802419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
4140 05:03:31.852677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
4141 05:03:31.853432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
4143 05:03:31.899150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
4144 05:03:31.899922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4146 05:03:31.952018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4147 05:03:31.952813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4149 05:03:31.999288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4150 05:03:32.000077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4152 05:03:32.050824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4153 05:03:32.051856 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4155 05:03:32.098882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4156 05:03:32.099957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4158 05:03:32.152071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4159 05:03:32.152918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4161 05:03:32.195593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4162 05:03:32.196371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4164 05:03:32.247143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4165 05:03:32.247906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4167 05:03:32.294968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4168 05:03:32.295773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4170 05:03:32.345710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4171 05:03:32.346489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4173 05:03:32.395489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4174 05:03:32.396321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4176 05:03:32.454614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4177 05:03:32.455469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4179 05:03:32.498425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4180 05:03:32.499203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4182 05:03:32.550292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4183 05:03:32.551088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4185 05:03:32.598206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4186 05:03:32.598969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4188 05:03:32.646746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4189 05:03:32.647537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4191 05:03:32.704090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4192 05:03:32.704951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4194 05:03:32.752611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4195 05:03:32.753365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4197 05:03:32.809880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4198 05:03:32.810628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4200 05:03:32.860896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4201 05:03:32.861734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4203 05:03:32.914749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4204 05:03:32.915508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4206 05:03:32.965445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4207 05:03:32.966193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4209 05:03:33.018619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4210 05:03:33.019381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4212 05:03:33.064149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4213 05:03:33.064897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4215 05:03:33.117904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4216 05:03:33.118786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4218 05:03:33.173996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4219 05:03:33.174857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4221 05:03:33.226420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4222 05:03:33.227305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4224 05:03:33.285679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4225 05:03:33.286573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4227 05:03:33.336623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4228 05:03:33.337246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4230 05:03:33.388486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4231 05:03:33.389381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4233 05:03:33.442841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4234 05:03:33.443740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4236 05:03:33.493524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4237 05:03:33.494571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4239 05:03:33.538652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4240 05:03:33.540056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4242 05:03:33.597149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4243 05:03:33.598252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4245 05:03:33.649237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4246 05:03:33.650233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4248 05:03:33.702261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4249 05:03:33.703167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4251 05:03:33.751975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4252 05:03:33.752936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4254 05:03:33.794596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4255 05:03:33.795535 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4257 05:03:33.851715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4258 05:03:33.852704 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4260 05:03:33.899781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4261 05:03:33.900592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4263 05:03:33.957564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4264 05:03:33.958410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4266 05:03:34.009552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4267 05:03:34.010333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4269 05:03:34.064392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4270 05:03:34.065217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4272 05:03:34.122479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4273 05:03:34.123293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4275 05:03:34.169412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4276 05:03:34.170054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4278 05:03:34.221027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4279 05:03:34.221699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4281 05:03:34.274048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4282 05:03:34.274710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4284 05:03:34.321786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4285 05:03:34.322626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4287 05:03:34.368962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4288 05:03:34.369785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4290 05:03:34.422723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4291 05:03:34.423455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4293 05:03:34.466085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4294 05:03:34.466974 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4296 05:03:34.523719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4297 05:03:34.524592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4299 05:03:34.579126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4300 05:03:34.580007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4302 05:03:34.634535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4303 05:03:34.635478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4305 05:03:34.686219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4306 05:03:34.687066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4308 05:03:34.735964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4309 05:03:34.736853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4311 05:03:34.790433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4312 05:03:34.791244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4314 05:03:34.842443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4315 05:03:34.843247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4317 05:03:34.893343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4318 05:03:34.894178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4320 05:03:34.945336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4321 05:03:34.946128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4323 05:03:35.005152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4324 05:03:35.006057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4326 05:03:35.049574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4327 05:03:35.050498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4329 05:03:35.099941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4330 05:03:35.100954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4332 05:03:35.153492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4333 05:03:35.155037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4335 05:03:35.196227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4336 05:03:35.197296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4338 05:03:35.254070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4339 05:03:35.255437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4341 05:03:35.303036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4342 05:03:35.303966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4344 05:03:35.352848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4345 05:03:35.353828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4347 05:03:35.410945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4348 05:03:35.411831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4350 05:03:35.460542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4351 05:03:35.461221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4353 05:03:35.510095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4355 05:03:35.512970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4356 05:03:35.575786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4357 05:03:35.576850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4359 05:03:35.621482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4360 05:03:35.622678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4362 05:03:35.681099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4363 05:03:35.682170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4365 05:03:35.726045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4366 05:03:35.727111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4368 05:03:35.772849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4369 05:03:35.773833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4371 05:03:35.830991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4372 05:03:35.832161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4374 05:03:35.886648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4375 05:03:35.887565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4377 05:03:35.929751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4378 05:03:35.930657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4380 05:03:35.973949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4381 05:03:35.974883 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4383 05:03:36.028569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4384 05:03:36.029415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4386 05:03:36.073125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4387 05:03:36.073982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4389 05:03:36.129832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4390 05:03:36.130640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4392 05:03:36.187893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4393 05:03:36.188813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4395 05:03:36.243190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4396 05:03:36.244055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4398 05:03:36.294837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4399 05:03:36.295751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4401 05:03:36.342227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4402 05:03:36.343445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4404 05:03:36.390551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4405 05:03:36.391507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4407 05:03:36.441469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4408 05:03:36.442450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4410 05:03:36.492559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4411 05:03:36.493506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4413 05:03:36.555917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4414 05:03:36.556587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4416 05:03:36.607567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4417 05:03:36.608183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4419 05:03:36.665793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4420 05:03:36.666681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4422 05:03:36.717959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4423 05:03:36.719086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4425 05:03:36.768100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4426 05:03:36.769168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4428 05:03:36.825440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4429 05:03:36.826376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4431 05:03:36.874157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4432 05:03:36.875088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4434 05:03:36.935962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4435 05:03:36.938266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4437 05:03:36.993917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4438 05:03:36.994876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4440 05:03:37.046025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4441 05:03:37.046998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4443 05:03:37.102402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4444 05:03:37.103357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4446 05:03:37.157461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4447 05:03:37.158281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4449 05:03:37.231249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4450 05:03:37.232166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4452 05:03:37.288572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4453 05:03:37.289509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4455 05:03:37.337932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4456 05:03:37.338897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4458 05:03:37.394786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4459 05:03:37.395797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4461 05:03:37.442944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4462 05:03:37.443895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4464 05:03:37.499882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4465 05:03:37.500661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4467 05:03:37.558147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4468 05:03:37.558812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4470 05:03:37.606815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4471 05:03:37.607753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4473 05:03:37.653617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4474 05:03:37.654569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4476 05:03:37.713793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4477 05:03:37.714730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4479 05:03:37.768042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4480 05:03:37.768965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4482 05:03:37.819791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4483 05:03:37.820727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4485 05:03:37.880370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4486 05:03:37.881358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4488 05:03:37.934190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4489 05:03:37.934853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4491 05:03:38.010906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4492 05:03:38.011615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4494 05:03:38.081126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4495 05:03:38.082051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4497 05:03:38.138873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4498 05:03:38.139774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4500 05:03:38.188000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4501 05:03:38.188990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4503 05:03:38.234294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4504 05:03:38.235169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4506 05:03:38.293743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4507 05:03:38.294380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4509 05:03:38.342513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4511 05:03:38.347774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4512 05:03:38.348854 + set +x
4513 05:03:38.354076 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 965234_1.6.2.4.5>
4514 05:03:38.354441 <LAVA_TEST_RUNNER EXIT>
4515 05:03:38.354872 Received signal: <ENDRUN> 1_kselftest-alsa 965234_1.6.2.4.5
4516 05:03:38.355115 Ending use of test pattern.
4517 05:03:38.355321 Ending test lava.1_kselftest-alsa (965234_1.6.2.4.5), duration 41.86
4519 05:03:38.356272 ok: lava_test_shell seems to have completed
4520 05:03:38.377772 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4521 05:03:38.379435 end: 3.1 lava-test-shell (duration 00:00:43) [common]
4522 05:03:38.379923 end: 3 lava-test-retry (duration 00:00:43) [common]
4523 05:03:38.380282 start: 4 finalize (timeout 00:06:05) [common]
4524 05:03:38.380606 start: 4.1 power-off (timeout 00:00:30) [common]
4525 05:03:38.381429 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4526 05:03:38.416653 >> OK - accepted request
4527 05:03:38.418751 Returned 0 in 0 seconds
4528 05:03:38.519881 end: 4.1 power-off (duration 00:00:00) [common]
4530 05:03:38.521305 start: 4.2 read-feedback (timeout 00:06:05) [common]
4531 05:03:38.522004 Listened to connection for namespace 'common' for up to 1s
4532 05:03:39.522985 Finalising connection for namespace 'common'
4533 05:03:39.523759 Disconnecting from shell: Finalise
4534 05:03:39.524480 / #
4535 05:03:39.625448 end: 4.2 read-feedback (duration 00:00:01) [common]
4536 05:03:39.625973 end: 4 finalize (duration 00:00:01) [common]
4537 05:03:39.626384 Cleaning after the job
4538 05:03:39.626822 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/ramdisk
4539 05:03:39.628870 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/kernel
4540 05:03:39.632931 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/dtb
4541 05:03:39.633754 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/nfsrootfs
4542 05:03:39.661370 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/965234/tftp-deploy-rwzvuebl/modules
4543 05:03:39.667816 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/965234
4544 05:03:43.837225 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/965234
4545 05:03:43.837913 Job finished correctly