Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:27:36.081843 lava-dispatcher, installed at version: 2024.01
2 23:27:36.082632 start: 0 validate
3 23:27:36.083117 Start time: 2024-11-11 23:27:36.083088+00:00 (UTC)
4 23:27:36.083664 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:27:36.084291 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:27:36.130864 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:27:36.131399 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-263-g52cf5128e13ea%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:27:36.165863 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:27:36.166521 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-263-g52cf5128e13ea%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 23:27:36.202175 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:27:36.202670 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-263-g52cf5128e13ea%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 23:27:36.247408 validate duration: 0.16
14 23:27:36.248264 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:27:36.248590 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:27:36.248877 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:27:36.249447 Not decompressing ramdisk as can be used compressed.
18 23:27:36.249884 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 23:27:36.250116 saving as /var/lib/lava/dispatcher/tmp/977268/tftp-deploy-pjnizx0j/ramdisk/rootfs.cpio.gz
20 23:27:36.250362 total size: 47897469 (45 MB)
21 23:27:36.297724 progress 0 % (0 MB)
22 23:27:36.329179 progress 5 % (2 MB)
23 23:27:36.360015 progress 10 % (4 MB)
24 23:27:36.390707 progress 15 % (6 MB)
25 23:27:36.421216 progress 20 % (9 MB)
26 23:27:36.450595 progress 25 % (11 MB)
27 23:27:36.479996 progress 30 % (13 MB)
28 23:27:36.509479 progress 35 % (16 MB)
29 23:27:36.538796 progress 40 % (18 MB)
30 23:27:36.568143 progress 45 % (20 MB)
31 23:27:36.597656 progress 50 % (22 MB)
32 23:27:36.627136 progress 55 % (25 MB)
33 23:27:36.656825 progress 60 % (27 MB)
34 23:27:36.686057 progress 65 % (29 MB)
35 23:27:36.715528 progress 70 % (32 MB)
36 23:27:36.745586 progress 75 % (34 MB)
37 23:27:36.774680 progress 80 % (36 MB)
38 23:27:36.804207 progress 85 % (38 MB)
39 23:27:36.833729 progress 90 % (41 MB)
40 23:27:36.863260 progress 95 % (43 MB)
41 23:27:36.892056 progress 100 % (45 MB)
42 23:27:36.892821 45 MB downloaded in 0.64 s (71.10 MB/s)
43 23:27:36.893370 end: 1.1.1 http-download (duration 00:00:01) [common]
45 23:27:36.894251 end: 1.1 download-retry (duration 00:00:01) [common]
46 23:27:36.894542 start: 1.2 download-retry (timeout 00:09:59) [common]
47 23:27:36.894811 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 23:27:36.895284 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-263-g52cf5128e13ea/arm64/defconfig/gcc-12/kernel/Image
49 23:27:36.895549 saving as /var/lib/lava/dispatcher/tmp/977268/tftp-deploy-pjnizx0j/kernel/Image
50 23:27:36.895756 total size: 45713920 (43 MB)
51 23:27:36.895964 No compression specified
52 23:27:36.933452 progress 0 % (0 MB)
53 23:27:36.961169 progress 5 % (2 MB)
54 23:27:36.988991 progress 10 % (4 MB)
55 23:27:37.016849 progress 15 % (6 MB)
56 23:27:37.044591 progress 20 % (8 MB)
57 23:27:37.072489 progress 25 % (10 MB)
58 23:27:37.100195 progress 30 % (13 MB)
59 23:27:37.127922 progress 35 % (15 MB)
60 23:27:37.155733 progress 40 % (17 MB)
61 23:27:37.183425 progress 45 % (19 MB)
62 23:27:37.211274 progress 50 % (21 MB)
63 23:27:37.238982 progress 55 % (24 MB)
64 23:27:37.267035 progress 60 % (26 MB)
65 23:27:37.294314 progress 65 % (28 MB)
66 23:27:37.321958 progress 70 % (30 MB)
67 23:27:37.350612 progress 75 % (32 MB)
68 23:27:37.378513 progress 80 % (34 MB)
69 23:27:37.406744 progress 85 % (37 MB)
70 23:27:37.434547 progress 90 % (39 MB)
71 23:27:37.462499 progress 95 % (41 MB)
72 23:27:37.489797 progress 100 % (43 MB)
73 23:27:37.490315 43 MB downloaded in 0.59 s (73.33 MB/s)
74 23:27:37.490795 end: 1.2.1 http-download (duration 00:00:01) [common]
76 23:27:37.491639 end: 1.2 download-retry (duration 00:00:01) [common]
77 23:27:37.491914 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:27:37.492210 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:27:37.492673 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-263-g52cf5128e13ea/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 23:27:37.492919 saving as /var/lib/lava/dispatcher/tmp/977268/tftp-deploy-pjnizx0j/dtb/meson-g12b-a311d-libretech-cc.dtb
81 23:27:37.493124 total size: 54703 (0 MB)
82 23:27:37.493332 No compression specified
83 23:27:37.528926 progress 59 % (0 MB)
84 23:27:37.529776 progress 100 % (0 MB)
85 23:27:37.530318 0 MB downloaded in 0.04 s (1.40 MB/s)
86 23:27:37.530779 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:27:37.531603 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:27:37.531866 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:27:37.532173 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:27:37.532763 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-263-g52cf5128e13ea/arm64/defconfig/gcc-12/modules.tar.xz
92 23:27:37.533023 saving as /var/lib/lava/dispatcher/tmp/977268/tftp-deploy-pjnizx0j/modules/modules.tar
93 23:27:37.533230 total size: 11609460 (11 MB)
94 23:27:37.533439 Using unxz to decompress xz
95 23:27:37.567435 progress 0 % (0 MB)
96 23:27:37.633060 progress 5 % (0 MB)
97 23:27:37.708751 progress 10 % (1 MB)
98 23:27:37.805246 progress 15 % (1 MB)
99 23:27:37.896626 progress 20 % (2 MB)
100 23:27:37.978065 progress 25 % (2 MB)
101 23:27:38.055032 progress 30 % (3 MB)
102 23:27:38.136432 progress 35 % (3 MB)
103 23:27:38.209795 progress 40 % (4 MB)
104 23:27:38.290398 progress 45 % (5 MB)
105 23:27:38.375650 progress 50 % (5 MB)
106 23:27:38.455521 progress 55 % (6 MB)
107 23:27:38.543478 progress 60 % (6 MB)
108 23:27:38.628103 progress 65 % (7 MB)
109 23:27:38.710918 progress 70 % (7 MB)
110 23:27:38.791399 progress 75 % (8 MB)
111 23:27:38.877368 progress 80 % (8 MB)
112 23:27:38.960297 progress 85 % (9 MB)
113 23:27:39.040895 progress 90 % (9 MB)
114 23:27:39.121955 progress 95 % (10 MB)
115 23:27:39.202641 progress 100 % (11 MB)
116 23:27:39.214070 11 MB downloaded in 1.68 s (6.59 MB/s)
117 23:27:39.214750 end: 1.4.1 http-download (duration 00:00:02) [common]
119 23:27:39.215604 end: 1.4 download-retry (duration 00:00:02) [common]
120 23:27:39.215889 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 23:27:39.216451 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 23:27:39.217006 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:27:39.217585 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 23:27:39.218656 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9
125 23:27:39.219959 makedir: /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin
126 23:27:39.221067 makedir: /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/tests
127 23:27:39.221805 makedir: /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/results
128 23:27:39.222489 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-add-keys
129 23:27:39.223696 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-add-sources
130 23:27:39.224816 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-background-process-start
131 23:27:39.225929 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-background-process-stop
132 23:27:39.227134 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-common-functions
133 23:27:39.228296 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-echo-ipv4
134 23:27:39.229496 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-install-packages
135 23:27:39.230699 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-installed-packages
136 23:27:39.231754 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-os-build
137 23:27:39.232903 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-probe-channel
138 23:27:39.234189 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-probe-ip
139 23:27:39.235236 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-target-ip
140 23:27:39.236331 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-target-mac
141 23:27:39.238173 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-target-storage
142 23:27:39.239388 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-test-case
143 23:27:39.240685 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-test-event
144 23:27:39.241930 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-test-feedback
145 23:27:39.242984 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-test-raise
146 23:27:39.244139 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-test-reference
147 23:27:39.245128 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-test-runner
148 23:27:39.246193 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-test-set
149 23:27:39.247249 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-test-shell
150 23:27:39.248377 Updating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-install-packages (oe)
151 23:27:39.249472 Updating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/bin/lava-installed-packages (oe)
152 23:27:39.250496 Creating /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/environment
153 23:27:39.251231 LAVA metadata
154 23:27:39.251724 - LAVA_JOB_ID=977268
155 23:27:39.252235 - LAVA_DISPATCHER_IP=192.168.6.2
156 23:27:39.252927 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 23:27:39.256263 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 23:27:39.256894 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 23:27:39.257308 skipped lava-vland-overlay
160 23:27:39.257797 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 23:27:39.258305 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 23:27:39.258731 skipped lava-multinode-overlay
163 23:27:39.259214 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 23:27:39.259713 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 23:27:39.260226 Loading test definitions
166 23:27:39.260780 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 23:27:39.261219 Using /lava-977268 at stage 0
168 23:27:39.263187 uuid=977268_1.5.2.4.1 testdef=None
169 23:27:39.263643 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 23:27:39.264214 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 23:27:39.267387 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 23:27:39.268263 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 23:27:39.270637 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 23:27:39.271517 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 23:27:39.273902 runner path: /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/0/tests/0_igt-gpu-panfrost test_uuid 977268_1.5.2.4.1
178 23:27:39.274607 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 23:27:39.275470 Creating lava-test-runner.conf files
181 23:27:39.275683 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/977268/lava-overlay-bhyknxr9/lava-977268/0 for stage 0
182 23:27:39.276194 - 0_igt-gpu-panfrost
183 23:27:39.276604 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 23:27:39.276897 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 23:27:39.302756 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 23:27:39.303231 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 23:27:39.303503 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 23:27:39.303775 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 23:27:39.304083 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 23:27:46.431896 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 23:27:46.432362 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 23:27:46.432611 extracting modules file /var/lib/lava/dispatcher/tmp/977268/tftp-deploy-pjnizx0j/modules/modules.tar to /var/lib/lava/dispatcher/tmp/977268/extract-overlay-ramdisk-kdhpaun0/ramdisk
193 23:27:47.848039 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 23:27:47.848486 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 23:27:47.848762 [common] Applying overlay /var/lib/lava/dispatcher/tmp/977268/compress-overlay-8iddtmi0/overlay-1.5.2.5.tar.gz to ramdisk
196 23:27:47.848975 [common] Applying overlay /var/lib/lava/dispatcher/tmp/977268/compress-overlay-8iddtmi0/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/977268/extract-overlay-ramdisk-kdhpaun0/ramdisk
197 23:27:47.878874 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 23:27:47.879284 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 23:27:47.879554 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 23:27:47.879779 Converting downloaded kernel to a uImage
201 23:27:47.880114 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/977268/tftp-deploy-pjnizx0j/kernel/Image /var/lib/lava/dispatcher/tmp/977268/tftp-deploy-pjnizx0j/kernel/uImage
202 23:27:48.344164 output: Image Name:
203 23:27:48.344580 output: Created: Mon Nov 11 23:27:47 2024
204 23:27:48.344787 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 23:27:48.344993 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 23:27:48.345194 output: Load Address: 01080000
207 23:27:48.345393 output: Entry Point: 01080000
208 23:27:48.345592 output:
209 23:27:48.345923 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 23:27:48.346189 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 23:27:48.346454 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 23:27:48.346705 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 23:27:48.346963 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 23:27:48.347215 Building ramdisk /var/lib/lava/dispatcher/tmp/977268/extract-overlay-ramdisk-kdhpaun0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/977268/extract-overlay-ramdisk-kdhpaun0/ramdisk
215 23:27:54.924087 >> 502381 blocks
216 23:28:15.425023 Adding RAMdisk u-boot header.
217 23:28:15.425685 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/977268/extract-overlay-ramdisk-kdhpaun0/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/977268/extract-overlay-ramdisk-kdhpaun0/ramdisk.cpio.gz.uboot
218 23:28:16.112253 output: Image Name:
219 23:28:16.112892 output: Created: Mon Nov 11 23:28:15 2024
220 23:28:16.113316 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 23:28:16.113723 output: Data Size: 65712379 Bytes = 64172.25 KiB = 62.67 MiB
222 23:28:16.114121 output: Load Address: 00000000
223 23:28:16.114522 output: Entry Point: 00000000
224 23:28:16.114914 output:
225 23:28:16.115873 rename /var/lib/lava/dispatcher/tmp/977268/extract-overlay-ramdisk-kdhpaun0/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/977268/tftp-deploy-pjnizx0j/ramdisk/ramdisk.cpio.gz.uboot
226 23:28:16.116646 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 23:28:16.117195 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 23:28:16.117726 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 23:28:16.118181 No LXC device requested
230 23:28:16.118684 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 23:28:16.119193 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 23:28:16.119693 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 23:28:16.120145 Checking files for TFTP limit of 4294967296 bytes.
234 23:28:16.122782 end: 1 tftp-deploy (duration 00:00:40) [common]
235 23:28:16.123359 start: 2 uboot-action (timeout 00:05:00) [common]
236 23:28:16.123894 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 23:28:16.124436 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 23:28:16.124948 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 23:28:16.125483 Using kernel file from prepare-kernel: 977268/tftp-deploy-pjnizx0j/kernel/uImage
240 23:28:16.126117 substitutions:
241 23:28:16.126537 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 23:28:16.126940 - {DTB_ADDR}: 0x01070000
243 23:28:16.127337 - {DTB}: 977268/tftp-deploy-pjnizx0j/dtb/meson-g12b-a311d-libretech-cc.dtb
244 23:28:16.127736 - {INITRD}: 977268/tftp-deploy-pjnizx0j/ramdisk/ramdisk.cpio.gz.uboot
245 23:28:16.128173 - {KERNEL_ADDR}: 0x01080000
246 23:28:16.128577 - {KERNEL}: 977268/tftp-deploy-pjnizx0j/kernel/uImage
247 23:28:16.128975 - {LAVA_MAC}: None
248 23:28:16.129414 - {PRESEED_CONFIG}: None
249 23:28:16.129815 - {PRESEED_LOCAL}: None
250 23:28:16.130207 - {RAMDISK_ADDR}: 0x08000000
251 23:28:16.130594 - {RAMDISK}: 977268/tftp-deploy-pjnizx0j/ramdisk/ramdisk.cpio.gz.uboot
252 23:28:16.130993 - {ROOT_PART}: None
253 23:28:16.131386 - {ROOT}: None
254 23:28:16.131780 - {SERVER_IP}: 192.168.6.2
255 23:28:16.132210 - {TEE_ADDR}: 0x83000000
256 23:28:16.132608 - {TEE}: None
257 23:28:16.133001 Parsed boot commands:
258 23:28:16.133382 - setenv autoload no
259 23:28:16.133770 - setenv initrd_high 0xffffffff
260 23:28:16.134158 - setenv fdt_high 0xffffffff
261 23:28:16.134544 - dhcp
262 23:28:16.134932 - setenv serverip 192.168.6.2
263 23:28:16.135317 - tftpboot 0x01080000 977268/tftp-deploy-pjnizx0j/kernel/uImage
264 23:28:16.135703 - tftpboot 0x08000000 977268/tftp-deploy-pjnizx0j/ramdisk/ramdisk.cpio.gz.uboot
265 23:28:16.136116 - tftpboot 0x01070000 977268/tftp-deploy-pjnizx0j/dtb/meson-g12b-a311d-libretech-cc.dtb
266 23:28:16.136516 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 23:28:16.136913 - bootm 0x01080000 0x08000000 0x01070000
268 23:28:16.137415 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 23:28:16.138889 start: 2.3 connect-device (timeout 00:05:00) [common]
271 23:28:16.139336 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 23:28:16.153848 Setting prompt string to ['lava-test: # ']
273 23:28:16.155321 end: 2.3 connect-device (duration 00:00:00) [common]
274 23:28:16.155951 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 23:28:16.156557 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 23:28:16.157092 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 23:28:16.158275 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 23:28:16.195213 >> OK - accepted request
279 23:28:16.197274 Returned 0 in 0 seconds
280 23:28:16.298337 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 23:28:16.299931 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 23:28:16.300571 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 23:28:16.301089 Setting prompt string to ['Hit any key to stop autoboot']
285 23:28:16.301563 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 23:28:16.303187 Trying 192.168.56.21...
287 23:28:16.303677 Connected to conserv1.
288 23:28:16.304140 Escape character is '^]'.
289 23:28:16.304566
290 23:28:16.304994 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 23:28:16.305435
292 23:28:28.160239 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 23:28:28.160870 bl2_stage_init 0x01
294 23:28:28.161322 bl2_stage_init 0x81
295 23:28:28.165699 hw id: 0x0000 - pwm id 0x01
296 23:28:28.166226 bl2_stage_init 0xc1
297 23:28:28.166657 bl2_stage_init 0x02
298 23:28:28.167051
299 23:28:28.171382 L0:00000000
300 23:28:28.171817 L1:20000703
301 23:28:28.172252 L2:00008067
302 23:28:28.172635 L3:14000000
303 23:28:28.176953 B2:00402000
304 23:28:28.177377 B1:e0f83180
305 23:28:28.177759
306 23:28:28.178140 TE: 58159
307 23:28:28.178520
308 23:28:28.182574 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 23:28:28.182994
310 23:28:28.183380 Board ID = 1
311 23:28:28.188141 Set A53 clk to 24M
312 23:28:28.188561 Set A73 clk to 24M
313 23:28:28.188945 Set clk81 to 24M
314 23:28:28.193740 A53 clk: 1200 MHz
315 23:28:28.194143 A73 clk: 1200 MHz
316 23:28:28.194526 CLK81: 166.6M
317 23:28:28.194902 smccc: 00012ab5
318 23:28:28.199326 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 23:28:28.204950 board id: 1
320 23:28:28.210876 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 23:28:28.221459 fw parse done
322 23:28:28.227390 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 23:28:28.270032 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 23:28:28.280900 PIEI prepare done
325 23:28:28.281319 fastboot data load
326 23:28:28.281709 fastboot data verify
327 23:28:28.286544 verify result: 266
328 23:28:28.292183 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 23:28:28.292646 LPDDR4 probe
330 23:28:28.293046 ddr clk to 1584MHz
331 23:28:28.300154 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 23:28:28.337512
333 23:28:28.338022 dmc_version 0001
334 23:28:28.344070 Check phy result
335 23:28:28.350070 INFO : End of CA training
336 23:28:28.350586 INFO : End of initialization
337 23:28:28.355621 INFO : Training has run successfully!
338 23:28:28.356093 Check phy result
339 23:28:28.361223 INFO : End of initialization
340 23:28:28.361678 INFO : End of read enable training
341 23:28:28.364462 INFO : End of fine write leveling
342 23:28:28.370046 INFO : End of Write leveling coarse delay
343 23:28:28.375597 INFO : Training has run successfully!
344 23:28:28.376070 Check phy result
345 23:28:28.376495 INFO : End of initialization
346 23:28:28.381335 INFO : End of read dq deskew training
347 23:28:28.386835 INFO : End of MPR read delay center optimization
348 23:28:28.387266 INFO : End of write delay center optimization
349 23:28:28.392470 INFO : End of read delay center optimization
350 23:28:28.398055 INFO : End of max read latency training
351 23:28:28.398720 INFO : Training has run successfully!
352 23:28:28.403699 1D training succeed
353 23:28:28.409651 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 23:28:28.457130 Check phy result
355 23:28:28.457592 INFO : End of initialization
356 23:28:28.478947 INFO : End of 2D read delay Voltage center optimization
357 23:28:28.498323 INFO : End of 2D read delay Voltage center optimization
358 23:28:28.550408 INFO : End of 2D write delay Voltage center optimization
359 23:28:28.599725 INFO : End of 2D write delay Voltage center optimization
360 23:28:28.605246 INFO : Training has run successfully!
361 23:28:28.605671
362 23:28:28.606081 channel==0
363 23:28:28.610930 RxClkDly_Margin_A0==88 ps 9
364 23:28:28.611352 TxDqDly_Margin_A0==98 ps 10
365 23:28:28.616472 RxClkDly_Margin_A1==88 ps 9
366 23:28:28.616903 TxDqDly_Margin_A1==98 ps 10
367 23:28:28.617331 TrainedVREFDQ_A0==74
368 23:28:28.621977 TrainedVREFDQ_A1==74
369 23:28:28.622404 VrefDac_Margin_A0==25
370 23:28:28.622800 DeviceVref_Margin_A0==40
371 23:28:28.627677 VrefDac_Margin_A1==25
372 23:28:28.628125 DeviceVref_Margin_A1==40
373 23:28:28.628524
374 23:28:28.628927
375 23:28:28.633327 channel==1
376 23:28:28.633751 RxClkDly_Margin_A0==98 ps 10
377 23:28:28.634151 TxDqDly_Margin_A0==98 ps 10
378 23:28:28.638908 RxClkDly_Margin_A1==88 ps 9
379 23:28:28.639346 TxDqDly_Margin_A1==88 ps 9
380 23:28:28.644422 TrainedVREFDQ_A0==77
381 23:28:28.644860 TrainedVREFDQ_A1==77
382 23:28:28.645262 VrefDac_Margin_A0==23
383 23:28:28.649943 DeviceVref_Margin_A0==37
384 23:28:28.650356 VrefDac_Margin_A1==24
385 23:28:28.655554 DeviceVref_Margin_A1==37
386 23:28:28.656005
387 23:28:28.656420 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 23:28:28.656822
389 23:28:28.689171 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000018 00000019 00000019 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 23:28:28.689671 2D training succeed
391 23:28:28.694789 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 23:28:28.700397 auto size-- 65535DDR cs0 size: 2048MB
393 23:28:28.700820 DDR cs1 size: 2048MB
394 23:28:28.705943 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 23:28:28.706376 cs0 DataBus test pass
396 23:28:28.711555 cs1 DataBus test pass
397 23:28:28.711970 cs0 AddrBus test pass
398 23:28:28.712427 cs1 AddrBus test pass
399 23:28:28.712826
400 23:28:28.717174 100bdlr_step_size ps== 420
401 23:28:28.717603 result report
402 23:28:28.722754 boot times 0Enable ddr reg access
403 23:28:28.728171 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 23:28:28.741654 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 23:28:29.315332 0.0;M3 CHK:0;cm4_sp_mode 0
406 23:28:29.315910 MVN_1=0x00000000
407 23:28:29.320745 MVN_2=0x00000000
408 23:28:29.326530 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 23:28:29.326968 OPS=0x10
410 23:28:29.327379 ring efuse init
411 23:28:29.327776 chipver efuse init
412 23:28:29.334716 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 23:28:29.335165 [0.018960 Inits done]
414 23:28:29.342476 secure task start!
415 23:28:29.343039 high task start!
416 23:28:29.343479 low task start!
417 23:28:29.343893 run into bl31
418 23:28:29.348961 NOTICE: BL31: v1.3(release):4fc40b1
419 23:28:29.356722 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 23:28:29.357189 NOTICE: BL31: G12A normal boot!
421 23:28:29.382646 NOTICE: BL31: BL33 decompress pass
422 23:28:29.388383 ERROR: Error initializing runtime service opteed_fast
423 23:28:30.621275
424 23:28:30.621888
425 23:28:30.629599 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 23:28:30.630061
427 23:28:30.630469 Model: Libre Computer AML-A311D-CC Alta
428 23:28:30.838062 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 23:28:30.861380 DRAM: 2 GiB (effective 3.8 GiB)
430 23:28:31.004469 Core: 408 devices, 31 uclasses, devicetree: separate
431 23:28:31.010240 WDT: Not starting watchdog@f0d0
432 23:28:31.042599 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 23:28:31.054962 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 23:28:31.059944 ** Bad device specification mmc 0 **
435 23:28:31.070301 Card did not respond to voltage select! : -110
436 23:28:31.077916 ** Bad device specification mmc 0 **
437 23:28:31.078344 Couldn't find partition mmc 0
438 23:28:31.086262 Card did not respond to voltage select! : -110
439 23:28:31.091798 ** Bad device specification mmc 0 **
440 23:28:31.092273 Couldn't find partition mmc 0
441 23:28:31.096822 Error: could not access storage.
442 23:28:32.360617 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 23:28:32.361242 bl2_stage_init 0x01
444 23:28:32.361670 bl2_stage_init 0x81
445 23:28:32.366054 hw id: 0x0000 - pwm id 0x01
446 23:28:32.366497 bl2_stage_init 0xc1
447 23:28:32.366902 bl2_stage_init 0x02
448 23:28:32.367302
449 23:28:32.371731 L0:00000000
450 23:28:32.372234 L1:20000703
451 23:28:32.372647 L2:00008067
452 23:28:32.373042 L3:14000000
453 23:28:32.377239 B2:00402000
454 23:28:32.377668 B1:e0f83180
455 23:28:32.378063
456 23:28:32.378462 TE: 58124
457 23:28:32.378854
458 23:28:32.382862 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 23:28:32.383324
460 23:28:32.383726 Board ID = 1
461 23:28:32.388425 Set A53 clk to 24M
462 23:28:32.388855 Set A73 clk to 24M
463 23:28:32.389255 Set clk81 to 24M
464 23:28:32.394053 A53 clk: 1200 MHz
465 23:28:32.394542 A73 clk: 1200 MHz
466 23:28:32.394949 CLK81: 166.6M
467 23:28:32.395344 smccc: 00012a92
468 23:28:32.399761 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 23:28:32.405267 board id: 1
470 23:28:32.411096 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 23:28:32.421788 fw parse done
472 23:28:32.427804 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 23:28:32.470354 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 23:28:32.481340 PIEI prepare done
475 23:28:32.481778 fastboot data load
476 23:28:32.482183 fastboot data verify
477 23:28:32.486967 verify result: 266
478 23:28:32.492550 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 23:28:32.492991 LPDDR4 probe
480 23:28:32.493394 ddr clk to 1584MHz
481 23:28:32.500494 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 23:28:32.537753
483 23:28:32.538195 dmc_version 0001
484 23:28:32.544409 Check phy result
485 23:28:32.550278 INFO : End of CA training
486 23:28:32.550706 INFO : End of initialization
487 23:28:32.555897 INFO : Training has run successfully!
488 23:28:32.556357 Check phy result
489 23:28:32.561506 INFO : End of initialization
490 23:28:32.561926 INFO : End of read enable training
491 23:28:32.567117 INFO : End of fine write leveling
492 23:28:32.572864 INFO : End of Write leveling coarse delay
493 23:28:32.573292 INFO : Training has run successfully!
494 23:28:32.573696 Check phy result
495 23:28:32.578327 INFO : End of initialization
496 23:28:32.578752 INFO : End of read dq deskew training
497 23:28:32.583906 INFO : End of MPR read delay center optimization
498 23:28:32.589525 INFO : End of write delay center optimization
499 23:28:32.595120 INFO : End of read delay center optimization
500 23:28:32.595544 INFO : End of max read latency training
501 23:28:32.600842 INFO : Training has run successfully!
502 23:28:32.601270 1D training succeed
503 23:28:32.609968 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 23:28:32.657469 Check phy result
505 23:28:32.657898 INFO : End of initialization
506 23:28:32.679239 INFO : End of 2D read delay Voltage center optimization
507 23:28:32.699463 INFO : End of 2D read delay Voltage center optimization
508 23:28:32.751488 INFO : End of 2D write delay Voltage center optimization
509 23:28:32.800901 INFO : End of 2D write delay Voltage center optimization
510 23:28:32.806391 INFO : Training has run successfully!
511 23:28:32.806816
512 23:28:32.807219 channel==0
513 23:28:32.811976 RxClkDly_Margin_A0==88 ps 9
514 23:28:32.812439 TxDqDly_Margin_A0==98 ps 10
515 23:28:32.817577 RxClkDly_Margin_A1==88 ps 9
516 23:28:32.817997 TxDqDly_Margin_A1==98 ps 10
517 23:28:32.818400 TrainedVREFDQ_A0==74
518 23:28:32.823169 TrainedVREFDQ_A1==74
519 23:28:32.823606 VrefDac_Margin_A0==25
520 23:28:32.824029 DeviceVref_Margin_A0==40
521 23:28:32.828827 VrefDac_Margin_A1==25
522 23:28:32.829250 DeviceVref_Margin_A1==40
523 23:28:32.829645
524 23:28:32.830037
525 23:28:32.834398 channel==1
526 23:28:32.834830 RxClkDly_Margin_A0==98 ps 10
527 23:28:32.835226 TxDqDly_Margin_A0==98 ps 10
528 23:28:32.839999 RxClkDly_Margin_A1==88 ps 9
529 23:28:32.840426 TxDqDly_Margin_A1==88 ps 9
530 23:28:32.845577 TrainedVREFDQ_A0==77
531 23:28:32.846002 TrainedVREFDQ_A1==77
532 23:28:32.846400 VrefDac_Margin_A0==22
533 23:28:32.851209 DeviceVref_Margin_A0==37
534 23:28:32.851630 VrefDac_Margin_A1==24
535 23:28:32.856817 DeviceVref_Margin_A1==37
536 23:28:32.857240
537 23:28:32.857639 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 23:28:32.858032
539 23:28:32.890377 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
540 23:28:32.890841 2D training succeed
541 23:28:32.896000 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 23:28:32.901565 auto size-- 65535DDR cs0 size: 2048MB
543 23:28:32.901988 DDR cs1 size: 2048MB
544 23:28:32.907250 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 23:28:32.907710 cs0 DataBus test pass
546 23:28:32.912872 cs1 DataBus test pass
547 23:28:32.913302 cs0 AddrBus test pass
548 23:28:32.913700 cs1 AddrBus test pass
549 23:28:32.914095
550 23:28:32.918392 100bdlr_step_size ps== 420
551 23:28:32.918831 result report
552 23:28:32.924064 boot times 0Enable ddr reg access
553 23:28:32.929418 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 23:28:32.942927 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 23:28:33.516640 0.0;M3 CHK:0;cm4_sp_mode 0
556 23:28:33.517264 MVN_1=0x00000000
557 23:28:33.522042 MVN_2=0x00000000
558 23:28:33.527927 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 23:28:33.528497 OPS=0x10
560 23:28:33.528926 ring efuse init
561 23:28:33.529313 chipver efuse init
562 23:28:33.533399 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 23:28:33.538975 [0.018961 Inits done]
564 23:28:33.539392 secure task start!
565 23:28:33.539775 high task start!
566 23:28:33.543545 low task start!
567 23:28:33.543954 run into bl31
568 23:28:33.550227 NOTICE: BL31: v1.3(release):4fc40b1
569 23:28:33.558024 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 23:28:33.558444 NOTICE: BL31: G12A normal boot!
571 23:28:33.583410 NOTICE: BL31: BL33 decompress pass
572 23:28:33.589126 ERROR: Error initializing runtime service opteed_fast
573 23:28:34.822305
574 23:28:34.822900
575 23:28:34.830642 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 23:28:34.831080
577 23:28:34.831486 Model: Libre Computer AML-A311D-CC Alta
578 23:28:35.039159 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 23:28:35.062456 DRAM: 2 GiB (effective 3.8 GiB)
580 23:28:35.205293 Core: 408 devices, 31 uclasses, devicetree: separate
581 23:28:35.211387 WDT: Not starting watchdog@f0d0
582 23:28:35.243458 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 23:28:35.255918 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 23:28:35.261046 ** Bad device specification mmc 0 **
585 23:28:35.271294 Card did not respond to voltage select! : -110
586 23:28:35.279002 ** Bad device specification mmc 0 **
587 23:28:35.279434 Couldn't find partition mmc 0
588 23:28:35.287252 Card did not respond to voltage select! : -110
589 23:28:35.292770 ** Bad device specification mmc 0 **
590 23:28:35.293205 Couldn't find partition mmc 0
591 23:28:35.297823 Error: could not access storage.
592 23:28:35.640433 Net: eth0: ethernet@ff3f0000
593 23:28:35.641024 starting USB...
594 23:28:35.892195 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 23:28:35.892668 Starting the controller
596 23:28:35.899180 USB XHCI 1.10
597 23:28:37.611070 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 23:28:37.611713 bl2_stage_init 0x01
599 23:28:37.612202 bl2_stage_init 0x81
600 23:28:37.616556 hw id: 0x0000 - pwm id 0x01
601 23:28:37.617012 bl2_stage_init 0xc1
602 23:28:37.617425 bl2_stage_init 0x02
603 23:28:37.617824
604 23:28:37.622106 L0:00000000
605 23:28:37.622549 L1:20000703
606 23:28:37.622955 L2:00008067
607 23:28:37.623348 L3:14000000
608 23:28:37.627734 B2:00402000
609 23:28:37.628199 B1:e0f83180
610 23:28:37.628604
611 23:28:37.629003 TE: 58167
612 23:28:37.629403
613 23:28:37.633299 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 23:28:37.633739
615 23:28:37.634141 Board ID = 1
616 23:28:37.638905 Set A53 clk to 24M
617 23:28:37.639335 Set A73 clk to 24M
618 23:28:37.639736 Set clk81 to 24M
619 23:28:37.644557 A53 clk: 1200 MHz
620 23:28:37.644999 A73 clk: 1200 MHz
621 23:28:37.645402 CLK81: 166.6M
622 23:28:37.645794 smccc: 00012abe
623 23:28:37.650074 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 23:28:37.655638 board id: 1
625 23:28:37.660844 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 23:28:37.672214 fw parse done
627 23:28:37.678061 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 23:28:37.720702 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 23:28:37.731608 PIEI prepare done
630 23:28:37.732087 fastboot data load
631 23:28:37.732496 fastboot data verify
632 23:28:37.737183 verify result: 266
633 23:28:37.743000 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 23:28:37.743439 LPDDR4 probe
635 23:28:37.743838 ddr clk to 1584MHz
636 23:28:37.750782 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 23:28:37.788069
638 23:28:37.788535 dmc_version 0001
639 23:28:37.794710 Check phy result
640 23:28:37.800581 INFO : End of CA training
641 23:28:37.801013 INFO : End of initialization
642 23:28:37.806178 INFO : Training has run successfully!
643 23:28:37.806606 Check phy result
644 23:28:37.811775 INFO : End of initialization
645 23:28:37.812237 INFO : End of read enable training
646 23:28:37.817378 INFO : End of fine write leveling
647 23:28:37.822978 INFO : End of Write leveling coarse delay
648 23:28:37.823407 INFO : Training has run successfully!
649 23:28:37.823806 Check phy result
650 23:28:37.828588 INFO : End of initialization
651 23:28:37.829021 INFO : End of read dq deskew training
652 23:28:37.834180 INFO : End of MPR read delay center optimization
653 23:28:37.839783 INFO : End of write delay center optimization
654 23:28:37.845389 INFO : End of read delay center optimization
655 23:28:37.845818 INFO : End of max read latency training
656 23:28:37.850953 INFO : Training has run successfully!
657 23:28:37.851381 1D training succeed
658 23:28:37.860206 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 23:28:37.907744 Check phy result
660 23:28:37.908235 INFO : End of initialization
661 23:28:37.930263 INFO : End of 2D read delay Voltage center optimization
662 23:28:37.950345 INFO : End of 2D read delay Voltage center optimization
663 23:28:38.002214 INFO : End of 2D write delay Voltage center optimization
664 23:28:38.051434 INFO : End of 2D write delay Voltage center optimization
665 23:28:38.057023 INFO : Training has run successfully!
666 23:28:38.057459
667 23:28:38.057867 channel==0
668 23:28:38.062620 RxClkDly_Margin_A0==88 ps 9
669 23:28:38.063050 TxDqDly_Margin_A0==98 ps 10
670 23:28:38.068231 RxClkDly_Margin_A1==88 ps 9
671 23:28:38.068668 TxDqDly_Margin_A1==88 ps 9
672 23:28:38.069083 TrainedVREFDQ_A0==74
673 23:28:38.073816 TrainedVREFDQ_A1==74
674 23:28:38.074253 VrefDac_Margin_A0==25
675 23:28:38.074651 DeviceVref_Margin_A0==40
676 23:28:38.079416 VrefDac_Margin_A1==25
677 23:28:38.079844 DeviceVref_Margin_A1==40
678 23:28:38.080292
679 23:28:38.080693
680 23:28:38.081092 channel==1
681 23:28:38.085026 RxClkDly_Margin_A0==98 ps 10
682 23:28:38.085456 TxDqDly_Margin_A0==98 ps 10
683 23:28:38.090595 RxClkDly_Margin_A1==88 ps 9
684 23:28:38.091023 TxDqDly_Margin_A1==88 ps 9
685 23:28:38.096412 TrainedVREFDQ_A0==77
686 23:28:38.096843 TrainedVREFDQ_A1==77
687 23:28:38.097243 VrefDac_Margin_A0==22
688 23:28:38.101857 DeviceVref_Margin_A0==37
689 23:28:38.102289 VrefDac_Margin_A1==24
690 23:28:38.107530 DeviceVref_Margin_A1==37
691 23:28:38.107964
692 23:28:38.108398 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 23:28:38.108797
694 23:28:38.141053 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
695 23:28:38.141519 2D training succeed
696 23:28:38.146654 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 23:28:38.152236 auto size-- 65535DDR cs0 size: 2048MB
698 23:28:38.152667 DDR cs1 size: 2048MB
699 23:28:38.157837 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 23:28:38.158264 cs0 DataBus test pass
701 23:28:38.163445 cs1 DataBus test pass
702 23:28:38.163869 cs0 AddrBus test pass
703 23:28:38.164306 cs1 AddrBus test pass
704 23:28:38.164705
705 23:28:38.169026 100bdlr_step_size ps== 420
706 23:28:38.169465 result report
707 23:28:38.174651 boot times 0Enable ddr reg access
708 23:28:38.179900 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 23:28:38.193351 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 23:28:38.765444 0.0;M3 CHK:0;cm4_sp_mode 0
711 23:28:38.766063 MVN_1=0x00000000
712 23:28:38.770839 MVN_2=0x00000000
713 23:28:38.776711 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 23:28:38.777236 OPS=0x10
715 23:28:38.777635 ring efuse init
716 23:28:38.778023 chipver efuse init
717 23:28:38.782175 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 23:28:38.787800 [0.018960 Inits done]
719 23:28:38.788272 secure task start!
720 23:28:38.788662 high task start!
721 23:28:38.792372 low task start!
722 23:28:38.792803 run into bl31
723 23:28:38.799029 NOTICE: BL31: v1.3(release):4fc40b1
724 23:28:38.806810 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 23:28:38.807241 NOTICE: BL31: G12A normal boot!
726 23:28:38.832252 NOTICE: BL31: BL33 decompress pass
727 23:28:38.837946 ERROR: Error initializing runtime service opteed_fast
728 23:28:40.070959
729 23:28:40.071585
730 23:28:40.079193 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 23:28:40.079646
732 23:28:40.080094 Model: Libre Computer AML-A311D-CC Alta
733 23:28:40.287612 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 23:28:40.311031 DRAM: 2 GiB (effective 3.8 GiB)
735 23:28:40.454073 Core: 408 devices, 31 uclasses, devicetree: separate
736 23:28:40.460011 WDT: Not starting watchdog@f0d0
737 23:28:40.492254 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 23:28:40.504598 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 23:28:40.509582 ** Bad device specification mmc 0 **
740 23:28:40.519919 Card did not respond to voltage select! : -110
741 23:28:40.527565 ** Bad device specification mmc 0 **
742 23:28:40.528050 Couldn't find partition mmc 0
743 23:28:40.535912 Card did not respond to voltage select! : -110
744 23:28:40.541420 ** Bad device specification mmc 0 **
745 23:28:40.541889 Couldn't find partition mmc 0
746 23:28:40.546497 Error: could not access storage.
747 23:28:40.890123 Net: eth0: ethernet@ff3f0000
748 23:28:40.890722 starting USB...
749 23:28:41.141866 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 23:28:41.142423 Starting the controller
751 23:28:41.148783 USB XHCI 1.10
752 23:28:43.312527 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 23:28:43.312958 bl2_stage_init 0x01
754 23:28:43.313177 bl2_stage_init 0x81
755 23:28:43.318037 hw id: 0x0000 - pwm id 0x01
756 23:28:43.318430 bl2_stage_init 0xc1
757 23:28:43.318745 bl2_stage_init 0x02
758 23:28:43.319042
759 23:28:43.323619 L0:00000000
760 23:28:43.324022 L1:20000703
761 23:28:43.324264 L2:00008067
762 23:28:43.324467 L3:14000000
763 23:28:43.326577 B2:00402000
764 23:28:43.326951 B1:e0f83180
765 23:28:43.327255
766 23:28:43.327555 TE: 58124
767 23:28:43.327849
768 23:28:43.337630 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 23:28:43.337926
770 23:28:43.338153 Board ID = 1
771 23:28:43.338353 Set A53 clk to 24M
772 23:28:43.338551 Set A73 clk to 24M
773 23:28:43.343323 Set clk81 to 24M
774 23:28:43.343876 A53 clk: 1200 MHz
775 23:28:43.344342 A73 clk: 1200 MHz
776 23:28:43.346895 CLK81: 166.6M
777 23:28:43.347374 smccc: 00012a91
778 23:28:43.352427 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 23:28:43.357994 board id: 1
780 23:28:43.363182 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 23:28:43.373883 fw parse done
782 23:28:43.379826 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 23:28:43.422520 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 23:28:43.433423 PIEI prepare done
785 23:28:43.433919 fastboot data load
786 23:28:43.434343 fastboot data verify
787 23:28:43.438946 verify result: 266
788 23:28:43.444536 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 23:28:43.445013 LPDDR4 probe
790 23:28:43.445423 ddr clk to 1584MHz
791 23:28:43.452583 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 23:28:43.489987
793 23:28:43.490558 dmc_version 0001
794 23:28:43.496605 Check phy result
795 23:28:43.502345 INFO : End of CA training
796 23:28:43.502814 INFO : End of initialization
797 23:28:43.507913 INFO : Training has run successfully!
798 23:28:43.508427 Check phy result
799 23:28:43.513521 INFO : End of initialization
800 23:28:43.513993 INFO : End of read enable training
801 23:28:43.519136 INFO : End of fine write leveling
802 23:28:43.524743 INFO : End of Write leveling coarse delay
803 23:28:43.525208 INFO : Training has run successfully!
804 23:28:43.525619 Check phy result
805 23:28:43.530358 INFO : End of initialization
806 23:28:43.530830 INFO : End of read dq deskew training
807 23:28:43.535914 INFO : End of MPR read delay center optimization
808 23:28:43.541522 INFO : End of write delay center optimization
809 23:28:43.547139 INFO : End of read delay center optimization
810 23:28:43.547601 INFO : End of max read latency training
811 23:28:43.552737 INFO : Training has run successfully!
812 23:28:43.553201 1D training succeed
813 23:28:43.561946 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 23:28:43.609626 Check phy result
815 23:28:43.610114 INFO : End of initialization
816 23:28:43.631178 INFO : End of 2D read delay Voltage center optimization
817 23:28:43.651246 INFO : End of 2D read delay Voltage center optimization
818 23:28:43.703130 INFO : End of 2D write delay Voltage center optimization
819 23:28:43.752419 INFO : End of 2D write delay Voltage center optimization
820 23:28:43.757975 INFO : Training has run successfully!
821 23:28:43.758443
822 23:28:43.758859 channel==0
823 23:28:43.763595 RxClkDly_Margin_A0==88 ps 9
824 23:28:43.764112 TxDqDly_Margin_A0==98 ps 10
825 23:28:43.767003 RxClkDly_Margin_A1==88 ps 9
826 23:28:43.767466 TxDqDly_Margin_A1==98 ps 10
827 23:28:43.772779 TrainedVREFDQ_A0==74
828 23:28:43.773296 TrainedVREFDQ_A1==74
829 23:28:43.773716 VrefDac_Margin_A0==25
830 23:28:43.778138 DeviceVref_Margin_A0==40
831 23:28:43.778639 VrefDac_Margin_A1==25
832 23:28:43.783805 DeviceVref_Margin_A1==40
833 23:28:43.784311
834 23:28:43.784711
835 23:28:43.785096 channel==1
836 23:28:43.785477 RxClkDly_Margin_A0==98 ps 10
837 23:28:43.787356 TxDqDly_Margin_A0==88 ps 9
838 23:28:43.792897 RxClkDly_Margin_A1==88 ps 9
839 23:28:43.793366 TxDqDly_Margin_A1==88 ps 9
840 23:28:43.793759 TrainedVREFDQ_A0==76
841 23:28:43.798514 TrainedVREFDQ_A1==77
842 23:28:43.798981 VrefDac_Margin_A0==22
843 23:28:43.804087 DeviceVref_Margin_A0==38
844 23:28:43.804556 VrefDac_Margin_A1==24
845 23:28:43.804944 DeviceVref_Margin_A1==37
846 23:28:43.805325
847 23:28:43.809705 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 23:28:43.810172
849 23:28:43.843288 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
850 23:28:43.843815 2D training succeed
851 23:28:43.848713 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 23:28:43.854320 auto size-- 65535DDR cs0 size: 2048MB
853 23:28:43.854792 DDR cs1 size: 2048MB
854 23:28:43.859922 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 23:28:43.860420 cs0 DataBus test pass
856 23:28:43.860809 cs1 DataBus test pass
857 23:28:43.865502 cs0 AddrBus test pass
858 23:28:43.865970 cs1 AddrBus test pass
859 23:28:43.866361
860 23:28:43.871096 100bdlr_step_size ps== 420
861 23:28:43.871580 result report
862 23:28:43.871969 boot times 0Enable ddr reg access
863 23:28:43.880687 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 23:28:43.894181 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 23:28:44.466228 0.0;M3 CHK:0;cm4_sp_mode 0
866 23:28:44.466842 MVN_1=0x00000000
867 23:28:44.471693 MVN_2=0x00000000
868 23:28:44.477588 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 23:28:44.478105 OPS=0x10
870 23:28:44.478526 ring efuse init
871 23:28:44.478929 chipver efuse init
872 23:28:44.483048 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 23:28:44.488677 [0.018960 Inits done]
874 23:28:44.489206 secure task start!
875 23:28:44.489617 high task start!
876 23:28:44.493258 low task start!
877 23:28:44.493752 run into bl31
878 23:28:44.499894 NOTICE: BL31: v1.3(release):4fc40b1
879 23:28:44.507693 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 23:28:44.508212 NOTICE: BL31: G12A normal boot!
881 23:28:44.533121 NOTICE: BL31: BL33 decompress pass
882 23:28:44.538814 ERROR: Error initializing runtime service opteed_fast
883 23:28:45.771722
884 23:28:45.772360
885 23:28:45.780092 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 23:28:45.780577
887 23:28:45.780998 Model: Libre Computer AML-A311D-CC Alta
888 23:28:45.988532 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 23:28:46.011900 DRAM: 2 GiB (effective 3.8 GiB)
890 23:28:46.154862 Core: 408 devices, 31 uclasses, devicetree: separate
891 23:28:46.160827 WDT: Not starting watchdog@f0d0
892 23:28:46.192994 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 23:28:46.205437 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 23:28:46.210446 ** Bad device specification mmc 0 **
895 23:28:46.220797 Card did not respond to voltage select! : -110
896 23:28:46.228514 ** Bad device specification mmc 0 **
897 23:28:46.228984 Couldn't find partition mmc 0
898 23:28:46.236791 Card did not respond to voltage select! : -110
899 23:28:46.242273 ** Bad device specification mmc 0 **
900 23:28:46.242739 Couldn't find partition mmc 0
901 23:28:46.247350 Error: could not access storage.
902 23:28:46.590835 Net: eth0: ethernet@ff3f0000
903 23:28:46.591275 starting USB...
904 23:28:46.841742 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 23:28:46.842406 Starting the controller
906 23:28:46.848585 USB XHCI 1.10
907 23:28:48.712386 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 23:28:48.713051 bl2_stage_init 0x01
909 23:28:48.713525 bl2_stage_init 0x81
910 23:28:48.717963 hw id: 0x0000 - pwm id 0x01
911 23:28:48.718450 bl2_stage_init 0xc1
912 23:28:48.718902 bl2_stage_init 0x02
913 23:28:48.719350
914 23:28:48.723557 L0:00000000
915 23:28:48.724072 L1:20000703
916 23:28:48.724528 L2:00008067
917 23:28:48.724966 L3:14000000
918 23:28:48.729157 B2:00402000
919 23:28:48.729634 B1:e0f83180
920 23:28:48.730084
921 23:28:48.730527 TE: 58124
922 23:28:48.730966
923 23:28:48.734758 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 23:28:48.735265
925 23:28:48.735716 Board ID = 1
926 23:28:48.740348 Set A53 clk to 24M
927 23:28:48.740825 Set A73 clk to 24M
928 23:28:48.741270 Set clk81 to 24M
929 23:28:48.745938 A53 clk: 1200 MHz
930 23:28:48.746410 A73 clk: 1200 MHz
931 23:28:48.746855 CLK81: 166.6M
932 23:28:48.747299 smccc: 00012a92
933 23:28:48.751517 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 23:28:48.757141 board id: 1
935 23:28:48.763030 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 23:28:48.773694 fw parse done
937 23:28:48.779698 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 23:28:48.822304 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 23:28:48.833193 PIEI prepare done
940 23:28:48.833716 fastboot data load
941 23:28:48.834163 fastboot data verify
942 23:28:48.838783 verify result: 266
943 23:28:48.844375 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 23:28:48.844846 LPDDR4 probe
945 23:28:48.845279 ddr clk to 1584MHz
946 23:28:48.852601 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 23:28:48.889823
948 23:28:48.890323 dmc_version 0001
949 23:28:48.896505 Check phy result
950 23:28:48.902318 INFO : End of CA training
951 23:28:48.902785 INFO : End of initialization
952 23:28:48.908022 INFO : Training has run successfully!
953 23:28:48.908556 Check phy result
954 23:28:48.913538 INFO : End of initialization
955 23:28:48.914027 INFO : End of read enable training
956 23:28:48.916801 INFO : End of fine write leveling
957 23:28:48.922439 INFO : End of Write leveling coarse delay
958 23:28:48.928083 INFO : Training has run successfully!
959 23:28:48.928573 Check phy result
960 23:28:48.929030 INFO : End of initialization
961 23:28:48.933654 INFO : End of read dq deskew training
962 23:28:48.939251 INFO : End of MPR read delay center optimization
963 23:28:48.939741 INFO : End of write delay center optimization
964 23:28:48.944841 INFO : End of read delay center optimization
965 23:28:48.950307 INFO : End of max read latency training
966 23:28:48.950793 INFO : Training has run successfully!
967 23:28:48.955958 1D training succeed
968 23:28:48.961833 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 23:28:49.009416 Check phy result
970 23:28:49.009970 INFO : End of initialization
971 23:28:49.031859 INFO : End of 2D read delay Voltage center optimization
972 23:28:49.052059 INFO : End of 2D read delay Voltage center optimization
973 23:28:49.103945 INFO : End of 2D write delay Voltage center optimization
974 23:28:49.153170 INFO : End of 2D write delay Voltage center optimization
975 23:28:49.158681 INFO : Training has run successfully!
976 23:28:49.159181
977 23:28:49.159638 channel==0
978 23:28:49.164366 RxClkDly_Margin_A0==88 ps 9
979 23:28:49.164868 TxDqDly_Margin_A0==98 ps 10
980 23:28:49.169973 RxClkDly_Margin_A1==88 ps 9
981 23:28:49.170460 TxDqDly_Margin_A1==98 ps 10
982 23:28:49.170914 TrainedVREFDQ_A0==74
983 23:28:49.175568 TrainedVREFDQ_A1==75
984 23:28:49.176089 VrefDac_Margin_A0==25
985 23:28:49.176544 DeviceVref_Margin_A0==40
986 23:28:49.181130 VrefDac_Margin_A1==25
987 23:28:49.181616 DeviceVref_Margin_A1==39
988 23:28:49.182067
989 23:28:49.182504
990 23:28:49.186693 channel==1
991 23:28:49.187207 RxClkDly_Margin_A0==98 ps 10
992 23:28:49.187661 TxDqDly_Margin_A0==98 ps 10
993 23:28:49.192330 RxClkDly_Margin_A1==98 ps 10
994 23:28:49.192828 TxDqDly_Margin_A1==88 ps 9
995 23:28:49.197970 TrainedVREFDQ_A0==77
996 23:28:49.198466 TrainedVREFDQ_A1==77
997 23:28:49.198920 VrefDac_Margin_A0==22
998 23:28:49.203472 DeviceVref_Margin_A0==37
999 23:28:49.203964 VrefDac_Margin_A1==22
1000 23:28:49.209266 DeviceVref_Margin_A1==37
1001 23:28:49.209791
1002 23:28:49.210249 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 23:28:49.214782
1004 23:28:49.242670 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1005 23:28:49.243200 2D training succeed
1006 23:28:49.248272 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 23:28:49.253825 auto size-- 65535DDR cs0 size: 2048MB
1008 23:28:49.254328 DDR cs1 size: 2048MB
1009 23:28:49.259435 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 23:28:49.259935 cs0 DataBus test pass
1011 23:28:49.265043 cs1 DataBus test pass
1012 23:28:49.265542 cs0 AddrBus test pass
1013 23:28:49.265996 cs1 AddrBus test pass
1014 23:28:49.266437
1015 23:28:49.270631 100bdlr_step_size ps== 420
1016 23:28:49.271168 result report
1017 23:28:49.276228 boot times 0Enable ddr reg access
1018 23:28:49.281637 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 23:28:49.295124 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 23:28:49.867260 0.0;M3 CHK:0;cm4_sp_mode 0
1021 23:28:49.867897 MVN_1=0x00000000
1022 23:28:49.872668 MVN_2=0x00000000
1023 23:28:49.878411 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 23:28:49.878911 OPS=0x10
1025 23:28:49.879375 ring efuse init
1026 23:28:49.879823 chipver efuse init
1027 23:28:49.884039 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 23:28:49.889622 [0.018960 Inits done]
1029 23:28:49.890114 secure task start!
1030 23:28:49.890565 high task start!
1031 23:28:49.894201 low task start!
1032 23:28:49.894690 run into bl31
1033 23:28:49.900798 NOTICE: BL31: v1.3(release):4fc40b1
1034 23:28:49.908597 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 23:28:49.909091 NOTICE: BL31: G12A normal boot!
1036 23:28:49.934464 NOTICE: BL31: BL33 decompress pass
1037 23:28:49.940148 ERROR: Error initializing runtime service opteed_fast
1038 23:28:51.173046
1039 23:28:51.173696
1040 23:28:51.181305 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 23:28:51.181812
1042 23:28:51.182270 Model: Libre Computer AML-A311D-CC Alta
1043 23:28:51.389839 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 23:28:51.413196 DRAM: 2 GiB (effective 3.8 GiB)
1045 23:28:51.556221 Core: 408 devices, 31 uclasses, devicetree: separate
1046 23:28:51.562001 WDT: Not starting watchdog@f0d0
1047 23:28:51.594298 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 23:28:51.606683 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 23:28:51.611663 ** Bad device specification mmc 0 **
1050 23:28:51.622005 Card did not respond to voltage select! : -110
1051 23:28:51.629663 ** Bad device specification mmc 0 **
1052 23:28:51.630157 Couldn't find partition mmc 0
1053 23:28:51.637970 Card did not respond to voltage select! : -110
1054 23:28:51.643503 ** Bad device specification mmc 0 **
1055 23:28:51.644024 Couldn't find partition mmc 0
1056 23:28:51.648547 Error: could not access storage.
1057 23:28:51.991083 Net: eth0: ethernet@ff3f0000
1058 23:28:51.991686 starting USB...
1059 23:28:52.242912 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 23:28:52.243535 Starting the controller
1061 23:28:52.249832 USB XHCI 1.10
1062 23:28:53.803933 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 23:28:53.812190 scanning usb for storage devices... 0 Storage Device(s) found
1065 23:28:53.863896 Hit any key to stop autoboot: 1
1066 23:28:53.864804 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1067 23:28:53.865435 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1068 23:28:53.865938 Setting prompt string to ['=>']
1069 23:28:53.866442 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1070 23:28:53.879606 0
1071 23:28:53.880566 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 23:28:53.881100 Sending with 10 millisecond of delay
1074 23:28:55.016096 => setenv autoload no
1075 23:28:55.026952 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1076 23:28:55.032375 setenv autoload no
1077 23:28:55.033217 Sending with 10 millisecond of delay
1079 23:28:56.830113 => setenv initrd_high 0xffffffff
1080 23:28:56.840900 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1081 23:28:56.841782 setenv initrd_high 0xffffffff
1082 23:28:56.842546 Sending with 10 millisecond of delay
1084 23:28:58.458905 => setenv fdt_high 0xffffffff
1085 23:28:58.469721 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 23:28:58.470578 setenv fdt_high 0xffffffff
1087 23:28:58.471335 Sending with 10 millisecond of delay
1089 23:28:58.763265 => dhcp
1090 23:28:58.773997 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1091 23:28:58.774839 dhcp
1092 23:28:58.775317 Speed: 1000, full duplex
1093 23:28:58.775770 BOOTP broadcast 1
1094 23:28:58.786175 DHCP client bound to address 192.168.6.27 (12 ms)
1095 23:28:58.786976 Sending with 10 millisecond of delay
1097 23:29:00.463568 => setenv serverip 192.168.6.2
1098 23:29:00.474454 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 23:29:00.475394 setenv serverip 192.168.6.2
1100 23:29:00.476133 Sending with 10 millisecond of delay
1102 23:29:04.199539 => tftpboot 0x01080000 977268/tftp-deploy-pjnizx0j/kernel/uImage
1103 23:29:04.210311 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 23:29:04.211246 tftpboot 0x01080000 977268/tftp-deploy-pjnizx0j/kernel/uImage
1105 23:29:04.211745 Speed: 1000, full duplex
1106 23:29:04.212257 Using ethernet@ff3f0000 device
1107 23:29:04.213045 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 23:29:04.218493 Filename '977268/tftp-deploy-pjnizx0j/kernel/uImage'.
1109 23:29:04.222374 Load address: 0x1080000
1110 23:29:07.096192 Loading: *################################################## 43.6 MiB
1111 23:29:07.096849 15.2 MiB/s
1112 23:29:07.097333 done
1113 23:29:07.100657 Bytes transferred = 45713984 (2b98a40 hex)
1114 23:29:07.101539 Sending with 10 millisecond of delay
1116 23:29:11.787941 => tftpboot 0x08000000 977268/tftp-deploy-pjnizx0j/ramdisk/ramdisk.cpio.gz.uboot
1117 23:29:11.798774 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1118 23:29:11.799626 tftpboot 0x08000000 977268/tftp-deploy-pjnizx0j/ramdisk/ramdisk.cpio.gz.uboot
1119 23:29:11.800151 Speed: 1000, full duplex
1120 23:29:11.800612 Using ethernet@ff3f0000 device
1121 23:29:11.801394 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 23:29:11.810162 Filename '977268/tftp-deploy-pjnizx0j/ramdisk/ramdisk.cpio.gz.uboot'.
1123 23:29:11.810714 Load address: 0x8000000
1124 23:29:20.998710 Loading: *######T ########################################### UDP wrong checksum 0000000f 0000189d
1125 23:29:26.000081 T UDP wrong checksum 0000000f 0000189d
1126 23:29:36.002147 T T UDP wrong checksum 0000000f 0000189d
1127 23:29:56.006888 T T T T UDP wrong checksum 0000000f 0000189d
1128 23:30:09.928910 T T UDP wrong checksum 000000ff 0000fd66
1129 23:30:09.937425 UDP wrong checksum 000000ff 00008a59
1130 23:30:11.010989
1131 23:30:11.011584 Retry count exceeded; starting again
1133 23:30:11.013014 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
1136 23:30:11.014795 end: 2.4 uboot-commands (duration 00:01:55) [common]
1138 23:30:11.016168 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1140 23:30:11.017226 end: 2 uboot-action (duration 00:01:55) [common]
1142 23:30:11.018736 Cleaning after the job
1143 23:30:11.019295 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/977268/tftp-deploy-pjnizx0j/ramdisk
1144 23:30:11.020450 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/977268/tftp-deploy-pjnizx0j/kernel
1145 23:30:11.065545 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/977268/tftp-deploy-pjnizx0j/dtb
1146 23:30:11.066370 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/977268/tftp-deploy-pjnizx0j/modules
1147 23:30:11.086310 start: 4.1 power-off (timeout 00:00:30) [common]
1148 23:30:11.086963 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1149 23:30:11.121890 >> OK - accepted request
1150 23:30:11.123900 Returned 0 in 0 seconds
1151 23:30:11.224822 end: 4.1 power-off (duration 00:00:00) [common]
1153 23:30:11.226204 start: 4.2 read-feedback (timeout 00:10:00) [common]
1154 23:30:11.227165 Listened to connection for namespace 'common' for up to 1s
1155 23:30:12.228055 Finalising connection for namespace 'common'
1156 23:30:12.228783 Disconnecting from shell: Finalise
1157 23:30:12.229256 =>
1158 23:30:12.330152 end: 4.2 read-feedback (duration 00:00:01) [common]
1159 23:30:12.330660 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/977268
1160 23:30:12.959301 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/977268
1161 23:30:12.959893 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.