Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:15:15.491620 lava-dispatcher, installed at version: 2024.01
2 23:15:15.492436 start: 0 validate
3 23:15:15.492907 Start time: 2024-11-11 23:15:15.492876+00:00 (UTC)
4 23:15:15.493458 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:15:15.494007 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:15:15.536026 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:15:15.536583 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-263-g52cf5128e13ea%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:15:15.564453 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:15:15.565115 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-263-g52cf5128e13ea%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 23:15:15.595520 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:15:15.596061 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:15:15.626211 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 23:15:15.627035 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fasoc-fix-v6.12-rc6-263-g52cf5128e13ea%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 23:15:15.665486 validate duration: 0.17
16 23:15:15.666351 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:15:15.666685 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:15:15.667015 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:15:15.667623 Not decompressing ramdisk as can be used compressed.
20 23:15:15.668093 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:15:15.668390 saving as /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/ramdisk/initrd.cpio.gz
22 23:15:15.668668 total size: 5628169 (5 MB)
23 23:15:15.705848 progress 0 % (0 MB)
24 23:15:15.710131 progress 5 % (0 MB)
25 23:15:15.714539 progress 10 % (0 MB)
26 23:15:15.718368 progress 15 % (0 MB)
27 23:15:15.722702 progress 20 % (1 MB)
28 23:15:15.726528 progress 25 % (1 MB)
29 23:15:15.730662 progress 30 % (1 MB)
30 23:15:15.734834 progress 35 % (1 MB)
31 23:15:15.738687 progress 40 % (2 MB)
32 23:15:15.742843 progress 45 % (2 MB)
33 23:15:15.746555 progress 50 % (2 MB)
34 23:15:15.750683 progress 55 % (2 MB)
35 23:15:15.754819 progress 60 % (3 MB)
36 23:15:15.758633 progress 65 % (3 MB)
37 23:15:15.763103 progress 70 % (3 MB)
38 23:15:15.766979 progress 75 % (4 MB)
39 23:15:15.771094 progress 80 % (4 MB)
40 23:15:15.774828 progress 85 % (4 MB)
41 23:15:15.779086 progress 90 % (4 MB)
42 23:15:15.783071 progress 95 % (5 MB)
43 23:15:15.786377 progress 100 % (5 MB)
44 23:15:15.787018 5 MB downloaded in 0.12 s (45.36 MB/s)
45 23:15:15.787546 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:15:15.788485 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:15:15.788766 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:15:15.789029 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:15:15.789485 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-263-g52cf5128e13ea/arm64/defconfig/gcc-12/kernel/Image
51 23:15:15.789759 saving as /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/kernel/Image
52 23:15:15.789970 total size: 45713920 (43 MB)
53 23:15:15.790181 No compression specified
54 23:15:15.824488 progress 0 % (0 MB)
55 23:15:15.852604 progress 5 % (2 MB)
56 23:15:15.881063 progress 10 % (4 MB)
57 23:15:15.909503 progress 15 % (6 MB)
58 23:15:15.938003 progress 20 % (8 MB)
59 23:15:15.965631 progress 25 % (10 MB)
60 23:15:15.993691 progress 30 % (13 MB)
61 23:15:16.021675 progress 35 % (15 MB)
62 23:15:16.050085 progress 40 % (17 MB)
63 23:15:16.077851 progress 45 % (19 MB)
64 23:15:16.105871 progress 50 % (21 MB)
65 23:15:16.134386 progress 55 % (24 MB)
66 23:15:16.162327 progress 60 % (26 MB)
67 23:15:16.189668 progress 65 % (28 MB)
68 23:15:16.217461 progress 70 % (30 MB)
69 23:15:16.245664 progress 75 % (32 MB)
70 23:15:16.273942 progress 80 % (34 MB)
71 23:15:16.301612 progress 85 % (37 MB)
72 23:15:16.329678 progress 90 % (39 MB)
73 23:15:16.358443 progress 95 % (41 MB)
74 23:15:16.386289 progress 100 % (43 MB)
75 23:15:16.386888 43 MB downloaded in 0.60 s (73.04 MB/s)
76 23:15:16.387367 end: 1.2.1 http-download (duration 00:00:01) [common]
78 23:15:16.388228 end: 1.2 download-retry (duration 00:00:01) [common]
79 23:15:16.388506 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:15:16.388774 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:15:16.389323 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-263-g52cf5128e13ea/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 23:15:16.389611 saving as /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/dtb/meson-g12b-a311d-libretech-cc.dtb
83 23:15:16.389818 total size: 54703 (0 MB)
84 23:15:16.390026 No compression specified
85 23:15:16.432715 progress 59 % (0 MB)
86 23:15:16.433575 progress 100 % (0 MB)
87 23:15:16.434127 0 MB downloaded in 0.04 s (1.18 MB/s)
88 23:15:16.434596 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:15:16.435414 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:15:16.435674 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:15:16.435934 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:15:16.436428 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:15:16.436676 saving as /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/nfsrootfs/full.rootfs.tar
95 23:15:16.436880 total size: 120894716 (115 MB)
96 23:15:16.437089 Using unxz to decompress xz
97 23:15:16.470841 progress 0 % (0 MB)
98 23:15:17.286035 progress 5 % (5 MB)
99 23:15:18.135198 progress 10 % (11 MB)
100 23:15:18.930062 progress 15 % (17 MB)
101 23:15:19.664170 progress 20 % (23 MB)
102 23:15:20.266871 progress 25 % (28 MB)
103 23:15:21.092764 progress 30 % (34 MB)
104 23:15:21.882596 progress 35 % (40 MB)
105 23:15:22.237620 progress 40 % (46 MB)
106 23:15:22.613165 progress 45 % (51 MB)
107 23:15:23.331161 progress 50 % (57 MB)
108 23:15:24.209634 progress 55 % (63 MB)
109 23:15:24.991274 progress 60 % (69 MB)
110 23:15:25.750189 progress 65 % (74 MB)
111 23:15:26.522542 progress 70 % (80 MB)
112 23:15:27.340910 progress 75 % (86 MB)
113 23:15:28.152193 progress 80 % (92 MB)
114 23:15:28.954839 progress 85 % (98 MB)
115 23:15:29.882585 progress 90 % (103 MB)
116 23:15:30.664175 progress 95 % (109 MB)
117 23:15:31.497533 progress 100 % (115 MB)
118 23:15:31.510143 115 MB downloaded in 15.07 s (7.65 MB/s)
119 23:15:31.510711 end: 1.4.1 http-download (duration 00:00:15) [common]
121 23:15:31.511526 end: 1.4 download-retry (duration 00:00:15) [common]
122 23:15:31.511793 start: 1.5 download-retry (timeout 00:09:44) [common]
123 23:15:31.512182 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 23:15:31.513190 downloading http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-263-g52cf5128e13ea/arm64/defconfig/gcc-12/modules.tar.xz
125 23:15:31.513704 saving as /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/modules/modules.tar
126 23:15:31.514145 total size: 11609460 (11 MB)
127 23:15:31.514601 Using unxz to decompress xz
128 23:15:31.554049 progress 0 % (0 MB)
129 23:15:31.619845 progress 5 % (0 MB)
130 23:15:31.693439 progress 10 % (1 MB)
131 23:15:31.788596 progress 15 % (1 MB)
132 23:15:31.878597 progress 20 % (2 MB)
133 23:15:31.958425 progress 25 % (2 MB)
134 23:15:32.033878 progress 30 % (3 MB)
135 23:15:32.111961 progress 35 % (3 MB)
136 23:15:32.183691 progress 40 % (4 MB)
137 23:15:32.260386 progress 45 % (5 MB)
138 23:15:32.344919 progress 50 % (5 MB)
139 23:15:32.422046 progress 55 % (6 MB)
140 23:15:32.507505 progress 60 % (6 MB)
141 23:15:32.588517 progress 65 % (7 MB)
142 23:15:32.670566 progress 70 % (7 MB)
143 23:15:32.749101 progress 75 % (8 MB)
144 23:15:32.831755 progress 80 % (8 MB)
145 23:15:32.914060 progress 85 % (9 MB)
146 23:15:32.997802 progress 90 % (9 MB)
147 23:15:33.075122 progress 95 % (10 MB)
148 23:15:33.151814 progress 100 % (11 MB)
149 23:15:33.163069 11 MB downloaded in 1.65 s (6.71 MB/s)
150 23:15:33.163677 end: 1.5.1 http-download (duration 00:00:02) [common]
152 23:15:33.165109 end: 1.5 download-retry (duration 00:00:02) [common]
153 23:15:33.165639 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 23:15:33.166149 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 23:15:50.161384 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/977229/extract-nfsrootfs-tydh2t4u
156 23:15:50.161988 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 23:15:50.162275 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 23:15:50.162994 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y
159 23:15:50.163454 makedir: /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin
160 23:15:50.163789 makedir: /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/tests
161 23:15:50.164186 makedir: /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/results
162 23:15:50.164529 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-add-keys
163 23:15:50.165059 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-add-sources
164 23:15:50.165564 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-background-process-start
165 23:15:50.166098 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-background-process-stop
166 23:15:50.166670 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-common-functions
167 23:15:50.167225 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-echo-ipv4
168 23:15:50.167731 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-install-packages
169 23:15:50.168273 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-installed-packages
170 23:15:50.168805 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-os-build
171 23:15:50.169305 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-probe-channel
172 23:15:50.169851 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-probe-ip
173 23:15:50.170351 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-target-ip
174 23:15:50.170832 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-target-mac
175 23:15:50.171330 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-target-storage
176 23:15:50.171817 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-test-case
177 23:15:50.172340 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-test-event
178 23:15:50.172824 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-test-feedback
179 23:15:50.173295 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-test-raise
180 23:15:50.173772 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-test-reference
181 23:15:50.174247 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-test-runner
182 23:15:50.174733 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-test-set
183 23:15:50.175209 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-test-shell
184 23:15:50.175693 Updating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-add-keys (debian)
185 23:15:50.176248 Updating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-add-sources (debian)
186 23:15:50.176768 Updating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-install-packages (debian)
187 23:15:50.177276 Updating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-installed-packages (debian)
188 23:15:50.177778 Updating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/bin/lava-os-build (debian)
189 23:15:50.178232 Creating /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/environment
190 23:15:50.178615 LAVA metadata
191 23:15:50.178879 - LAVA_JOB_ID=977229
192 23:15:50.179092 - LAVA_DISPATCHER_IP=192.168.6.2
193 23:15:50.179461 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 23:15:50.180462 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 23:15:50.180777 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 23:15:50.180986 skipped lava-vland-overlay
197 23:15:50.181228 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 23:15:50.181482 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 23:15:50.181700 skipped lava-multinode-overlay
200 23:15:50.181941 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 23:15:50.182189 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 23:15:50.182436 Loading test definitions
203 23:15:50.182712 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 23:15:50.182930 Using /lava-977229 at stage 0
205 23:15:50.184038 uuid=977229_1.6.2.4.1 testdef=None
206 23:15:50.184353 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 23:15:50.184619 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 23:15:50.186197 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 23:15:50.186983 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 23:15:50.189022 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 23:15:50.189855 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 23:15:50.191734 runner path: /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/0/tests/0_timesync-off test_uuid 977229_1.6.2.4.1
215 23:15:50.192368 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 23:15:50.193192 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 23:15:50.193418 Using /lava-977229 at stage 0
219 23:15:50.193778 Fetching tests from https://github.com/kernelci/test-definitions.git
220 23:15:50.194072 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/0/tests/1_kselftest-dt'
221 23:15:53.680583 Running '/usr/bin/git checkout kernelci.org
222 23:15:54.126895 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 23:15:54.129275 uuid=977229_1.6.2.4.5 testdef=None
224 23:15:54.129895 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 23:15:54.131351 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 23:15:54.136754 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 23:15:54.138343 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 23:15:54.145547 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 23:15:54.147208 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 23:15:54.154289 runner path: /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/0/tests/1_kselftest-dt test_uuid 977229_1.6.2.4.5
234 23:15:54.154812 BOARD='meson-g12b-a311d-libretech-cc'
235 23:15:54.155227 BRANCH='broonie-sound'
236 23:15:54.155624 SKIPFILE='/dev/null'
237 23:15:54.156051 SKIP_INSTALL='True'
238 23:15:54.156454 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/asoc-fix-v6.12-rc6-263-g52cf5128e13ea/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 23:15:54.156858 TST_CASENAME=''
240 23:15:54.157256 TST_CMDFILES='dt'
241 23:15:54.158252 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 23:15:54.159790 Creating lava-test-runner.conf files
244 23:15:54.160563 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/977229/lava-overlay-trej_b2y/lava-977229/0 for stage 0
245 23:15:54.161701 - 0_timesync-off
246 23:15:54.162328 - 1_kselftest-dt
247 23:15:54.163153 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 23:15:54.163857 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 23:16:18.034649 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 23:16:18.035107 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 23:16:18.035406 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 23:16:18.035720 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 23:16:18.036042 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 23:16:18.656667 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 23:16:18.657161 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 23:16:18.657434 extracting modules file /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/977229/extract-nfsrootfs-tydh2t4u
257 23:16:19.991168 extracting modules file /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/977229/extract-overlay-ramdisk-jj6nxh_a/ramdisk
258 23:16:21.355287 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 23:16:21.355757 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 23:16:21.356073 [common] Applying overlay to NFS
261 23:16:21.356305 [common] Applying overlay /var/lib/lava/dispatcher/tmp/977229/compress-overlay-n1e057je/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/977229/extract-nfsrootfs-tydh2t4u
262 23:16:24.126060 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 23:16:24.126523 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 23:16:24.126830 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 23:16:24.127093 Converting downloaded kernel to a uImage
266 23:16:24.127436 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/kernel/Image /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/kernel/uImage
267 23:16:24.589501 output: Image Name:
268 23:16:24.589927 output: Created: Mon Nov 11 23:16:24 2024
269 23:16:24.590133 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 23:16:24.590337 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 23:16:24.590535 output: Load Address: 01080000
272 23:16:24.590733 output: Entry Point: 01080000
273 23:16:24.590930 output:
274 23:16:24.591261 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 23:16:24.591529 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 23:16:24.591797 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 23:16:24.592088 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 23:16:24.592354 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 23:16:24.592628 Building ramdisk /var/lib/lava/dispatcher/tmp/977229/extract-overlay-ramdisk-jj6nxh_a/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/977229/extract-overlay-ramdisk-jj6nxh_a/ramdisk
280 23:16:26.696957 >> 166793 blocks
281 23:16:34.504333 Adding RAMdisk u-boot header.
282 23:16:34.504986 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/977229/extract-overlay-ramdisk-jj6nxh_a/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/977229/extract-overlay-ramdisk-jj6nxh_a/ramdisk.cpio.gz.uboot
283 23:16:34.798431 output: Image Name:
284 23:16:34.798856 output: Created: Mon Nov 11 23:16:34 2024
285 23:16:34.799065 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 23:16:34.799271 output: Data Size: 23432301 Bytes = 22883.11 KiB = 22.35 MiB
287 23:16:34.799472 output: Load Address: 00000000
288 23:16:34.799671 output: Entry Point: 00000000
289 23:16:34.799868 output:
290 23:16:34.800883 rename /var/lib/lava/dispatcher/tmp/977229/extract-overlay-ramdisk-jj6nxh_a/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/ramdisk/ramdisk.cpio.gz.uboot
291 23:16:34.801600 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 23:16:34.802138 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 23:16:34.802659 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 23:16:34.803116 No LXC device requested
295 23:16:34.803611 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 23:16:34.804151 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 23:16:34.804648 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 23:16:34.805055 Checking files for TFTP limit of 4294967296 bytes.
299 23:16:34.807677 end: 1 tftp-deploy (duration 00:01:19) [common]
300 23:16:34.808283 start: 2 uboot-action (timeout 00:05:00) [common]
301 23:16:34.808802 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 23:16:34.809292 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 23:16:34.809788 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 23:16:34.810309 Using kernel file from prepare-kernel: 977229/tftp-deploy-y5xxna7m/kernel/uImage
305 23:16:34.810926 substitutions:
306 23:16:34.811321 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 23:16:34.811720 - {DTB_ADDR}: 0x01070000
308 23:16:34.812147 - {DTB}: 977229/tftp-deploy-y5xxna7m/dtb/meson-g12b-a311d-libretech-cc.dtb
309 23:16:34.812550 - {INITRD}: 977229/tftp-deploy-y5xxna7m/ramdisk/ramdisk.cpio.gz.uboot
310 23:16:34.812943 - {KERNEL_ADDR}: 0x01080000
311 23:16:34.813331 - {KERNEL}: 977229/tftp-deploy-y5xxna7m/kernel/uImage
312 23:16:34.813718 - {LAVA_MAC}: None
313 23:16:34.814142 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/977229/extract-nfsrootfs-tydh2t4u
314 23:16:34.814532 - {NFS_SERVER_IP}: 192.168.6.2
315 23:16:34.814916 - {PRESEED_CONFIG}: None
316 23:16:34.815299 - {PRESEED_LOCAL}: None
317 23:16:34.815683 - {RAMDISK_ADDR}: 0x08000000
318 23:16:34.816091 - {RAMDISK}: 977229/tftp-deploy-y5xxna7m/ramdisk/ramdisk.cpio.gz.uboot
319 23:16:34.816479 - {ROOT_PART}: None
320 23:16:34.816863 - {ROOT}: None
321 23:16:34.817245 - {SERVER_IP}: 192.168.6.2
322 23:16:34.817625 - {TEE_ADDR}: 0x83000000
323 23:16:34.818003 - {TEE}: None
324 23:16:34.818381 Parsed boot commands:
325 23:16:34.818753 - setenv autoload no
326 23:16:34.819130 - setenv initrd_high 0xffffffff
327 23:16:34.819504 - setenv fdt_high 0xffffffff
328 23:16:34.819880 - dhcp
329 23:16:34.820285 - setenv serverip 192.168.6.2
330 23:16:34.820672 - tftpboot 0x01080000 977229/tftp-deploy-y5xxna7m/kernel/uImage
331 23:16:34.821056 - tftpboot 0x08000000 977229/tftp-deploy-y5xxna7m/ramdisk/ramdisk.cpio.gz.uboot
332 23:16:34.821439 - tftpboot 0x01070000 977229/tftp-deploy-y5xxna7m/dtb/meson-g12b-a311d-libretech-cc.dtb
333 23:16:34.821823 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/977229/extract-nfsrootfs-tydh2t4u,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 23:16:34.822217 - bootm 0x01080000 0x08000000 0x01070000
335 23:16:34.822701 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 23:16:34.824181 start: 2.3 connect-device (timeout 00:05:00) [common]
338 23:16:34.824599 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 23:16:34.838494 Setting prompt string to ['lava-test: # ']
340 23:16:34.840013 end: 2.3 connect-device (duration 00:00:00) [common]
341 23:16:34.840612 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 23:16:34.841170 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 23:16:34.841731 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 23:16:34.843097 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 23:16:34.882991 >> OK - accepted request
346 23:16:34.885252 Returned 0 in 0 seconds
347 23:16:34.986306 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 23:16:34.987904 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 23:16:34.988517 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 23:16:34.989033 Setting prompt string to ['Hit any key to stop autoboot']
352 23:16:34.989486 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 23:16:34.991046 Trying 192.168.56.21...
354 23:16:34.991524 Connected to conserv1.
355 23:16:34.991950 Escape character is '^]'.
356 23:16:34.992405
357 23:16:34.992829 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 23:16:34.993256
359 23:16:45.886386 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 23:16:45.887020 bl2_stage_init 0x01
361 23:16:45.887463 bl2_stage_init 0x81
362 23:16:45.891714 hw id: 0x0000 - pwm id 0x01
363 23:16:45.892271 bl2_stage_init 0xc1
364 23:16:45.892695 bl2_stage_init 0x02
365 23:16:45.893104
366 23:16:45.897433 L0:00000000
367 23:16:45.897894 L1:20000703
368 23:16:45.898287 L2:00008067
369 23:16:45.898681 L3:14000000
370 23:16:45.902944 B2:00402000
371 23:16:45.903379 B1:e0f83180
372 23:16:45.903767
373 23:16:45.904207 TE: 58124
374 23:16:45.904600
375 23:16:45.908529 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 23:16:45.908953
377 23:16:45.909341 Board ID = 1
378 23:16:45.914137 Set A53 clk to 24M
379 23:16:45.914557 Set A73 clk to 24M
380 23:16:45.914943 Set clk81 to 24M
381 23:16:45.919754 A53 clk: 1200 MHz
382 23:16:45.920207 A73 clk: 1200 MHz
383 23:16:45.920594 CLK81: 166.6M
384 23:16:45.920975 smccc: 00012a92
385 23:16:45.925275 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 23:16:45.930837 board id: 1
387 23:16:45.936911 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 23:16:45.947324 fw parse done
389 23:16:45.953339 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 23:16:45.995951 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 23:16:46.006860 PIEI prepare done
392 23:16:46.007279 fastboot data load
393 23:16:46.007668 fastboot data verify
394 23:16:46.012557 verify result: 266
395 23:16:46.018142 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 23:16:46.018563 LPDDR4 probe
397 23:16:46.018949 ddr clk to 1584MHz
398 23:16:46.026156 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 23:16:46.063390
400 23:16:46.063825 dmc_version 0001
401 23:16:46.070043 Check phy result
402 23:16:46.075877 INFO : End of CA training
403 23:16:46.076324 INFO : End of initialization
404 23:16:46.081466 INFO : Training has run successfully!
405 23:16:46.081883 Check phy result
406 23:16:46.087132 INFO : End of initialization
407 23:16:46.087546 INFO : End of read enable training
408 23:16:46.092655 INFO : End of fine write leveling
409 23:16:46.098288 INFO : End of Write leveling coarse delay
410 23:16:46.098700 INFO : Training has run successfully!
411 23:16:46.099091 Check phy result
412 23:16:46.103883 INFO : End of initialization
413 23:16:46.104338 INFO : End of read dq deskew training
414 23:16:46.109539 INFO : End of MPR read delay center optimization
415 23:16:46.115144 INFO : End of write delay center optimization
416 23:16:46.120653 INFO : End of read delay center optimization
417 23:16:46.121089 INFO : End of max read latency training
418 23:16:46.126302 INFO : Training has run successfully!
419 23:16:46.126717 1D training succeed
420 23:16:46.135508 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 23:16:46.183038 Check phy result
422 23:16:46.183461 INFO : End of initialization
423 23:16:46.205528 INFO : End of 2D read delay Voltage center optimization
424 23:16:46.225652 INFO : End of 2D read delay Voltage center optimization
425 23:16:46.277591 INFO : End of 2D write delay Voltage center optimization
426 23:16:46.326920 INFO : End of 2D write delay Voltage center optimization
427 23:16:46.332338 INFO : Training has run successfully!
428 23:16:46.332768
429 23:16:46.333162 channel==0
430 23:16:46.337972 RxClkDly_Margin_A0==88 ps 9
431 23:16:46.338400 TxDqDly_Margin_A0==98 ps 10
432 23:16:46.341442 RxClkDly_Margin_A1==88 ps 9
433 23:16:46.341865 TxDqDly_Margin_A1==98 ps 10
434 23:16:46.346895 TrainedVREFDQ_A0==74
435 23:16:46.347330 TrainedVREFDQ_A1==75
436 23:16:46.352463 VrefDac_Margin_A0==24
437 23:16:46.352895 DeviceVref_Margin_A0==40
438 23:16:46.353283 VrefDac_Margin_A1==25
439 23:16:46.358050 DeviceVref_Margin_A1==39
440 23:16:46.358480
441 23:16:46.358873
442 23:16:46.359261 channel==1
443 23:16:46.359644 RxClkDly_Margin_A0==88 ps 9
444 23:16:46.361533 TxDqDly_Margin_A0==98 ps 10
445 23:16:46.367075 RxClkDly_Margin_A1==98 ps 10
446 23:16:46.367496 TxDqDly_Margin_A1==98 ps 10
447 23:16:46.367889 TrainedVREFDQ_A0==77
448 23:16:46.372698 TrainedVREFDQ_A1==78
449 23:16:46.373136 VrefDac_Margin_A0==22
450 23:16:46.378222 DeviceVref_Margin_A0==37
451 23:16:46.378640 VrefDac_Margin_A1==22
452 23:16:46.379026 DeviceVref_Margin_A1==36
453 23:16:46.379411
454 23:16:46.383809 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 23:16:46.384257
456 23:16:46.417391 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 23:16:46.417917 2D training succeed
458 23:16:46.423001 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 23:16:46.428587 auto size-- 65535DDR cs0 size: 2048MB
460 23:16:46.429011 DDR cs1 size: 2048MB
461 23:16:46.434280 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 23:16:46.434711 cs0 DataBus test pass
463 23:16:46.435102 cs1 DataBus test pass
464 23:16:46.439838 cs0 AddrBus test pass
465 23:16:46.440279 cs1 AddrBus test pass
466 23:16:46.440670
467 23:16:46.445381 100bdlr_step_size ps== 420
468 23:16:46.445807 result report
469 23:16:46.446195 boot times 0Enable ddr reg access
470 23:16:46.455442 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 23:16:46.468889 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 23:16:47.040768 0.0;M3 CHK:0;cm4_sp_mode 0
473 23:16:47.041323 MVN_1=0x00000000
474 23:16:47.046308 MVN_2=0x00000000
475 23:16:47.052073 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 23:16:47.052522 OPS=0x10
477 23:16:47.052928 ring efuse init
478 23:16:47.053326 chipver efuse init
479 23:16:47.057618 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 23:16:47.063232 [0.018961 Inits done]
481 23:16:47.063657 secure task start!
482 23:16:47.064088 high task start!
483 23:16:47.067856 low task start!
484 23:16:47.068312 run into bl31
485 23:16:47.074490 NOTICE: BL31: v1.3(release):4fc40b1
486 23:16:47.082297 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 23:16:47.082731 NOTICE: BL31: G12A normal boot!
488 23:16:47.107637 NOTICE: BL31: BL33 decompress pass
489 23:16:47.113391 ERROR: Error initializing runtime service opteed_fast
490 23:16:48.346309
491 23:16:48.346913
492 23:16:48.354602 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 23:16:48.355057
494 23:16:48.355461 Model: Libre Computer AML-A311D-CC Alta
495 23:16:48.563061 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 23:16:48.586483 DRAM: 2 GiB (effective 3.8 GiB)
497 23:16:48.729525 Core: 408 devices, 31 uclasses, devicetree: separate
498 23:16:48.735196 WDT: Not starting watchdog@f0d0
499 23:16:48.767498 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 23:16:48.779923 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 23:16:48.784900 ** Bad device specification mmc 0 **
502 23:16:48.795243 Card did not respond to voltage select! : -110
503 23:16:48.802895 ** Bad device specification mmc 0 **
504 23:16:48.803325 Couldn't find partition mmc 0
505 23:16:48.811231 Card did not respond to voltage select! : -110
506 23:16:48.816747 ** Bad device specification mmc 0 **
507 23:16:48.817174 Couldn't find partition mmc 0
508 23:16:48.821798 Error: could not access storage.
509 23:16:50.086348 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 23:16:50.086935 bl2_stage_init 0x01
511 23:16:50.087367 bl2_stage_init 0x81
512 23:16:50.091913 hw id: 0x0000 - pwm id 0x01
513 23:16:50.092378 bl2_stage_init 0xc1
514 23:16:50.092786 bl2_stage_init 0x02
515 23:16:50.093183
516 23:16:50.097583 L0:00000000
517 23:16:50.098019 L1:20000703
518 23:16:50.098422 L2:00008067
519 23:16:50.098819 L3:14000000
520 23:16:50.103090 B2:00402000
521 23:16:50.103518 B1:e0f83180
522 23:16:50.103916
523 23:16:50.104358 TE: 58159
524 23:16:50.104757
525 23:16:50.108717 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 23:16:50.109149
527 23:16:50.109550 Board ID = 1
528 23:16:50.114305 Set A53 clk to 24M
529 23:16:50.114734 Set A73 clk to 24M
530 23:16:50.115136 Set clk81 to 24M
531 23:16:50.119894 A53 clk: 1200 MHz
532 23:16:50.120348 A73 clk: 1200 MHz
533 23:16:50.120748 CLK81: 166.6M
534 23:16:50.121143 smccc: 00012ab5
535 23:16:50.125589 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 23:16:50.131084 board id: 1
537 23:16:50.136979 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 23:16:50.147633 fw parse done
539 23:16:50.153703 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 23:16:50.195429 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 23:16:50.207111 PIEI prepare done
542 23:16:50.207543 fastboot data load
543 23:16:50.207948 fastboot data verify
544 23:16:50.212823 verify result: 266
545 23:16:50.218415 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 23:16:50.218841 LPDDR4 probe
547 23:16:50.219236 ddr clk to 1584MHz
548 23:16:50.225381 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 23:16:50.262710
550 23:16:50.263162 dmc_version 0001
551 23:16:50.269401 Check phy result
552 23:16:50.276326 INFO : End of CA training
553 23:16:50.276751 INFO : End of initialization
554 23:16:50.281756 INFO : Training has run successfully!
555 23:16:50.282178 Check phy result
556 23:16:50.287340 INFO : End of initialization
557 23:16:50.287782 INFO : End of read enable training
558 23:16:50.290684 INFO : End of fine write leveling
559 23:16:50.296202 INFO : End of Write leveling coarse delay
560 23:16:50.301801 INFO : Training has run successfully!
561 23:16:50.302219 Check phy result
562 23:16:50.302618 INFO : End of initialization
563 23:16:50.307412 INFO : End of read dq deskew training
564 23:16:50.312991 INFO : End of MPR read delay center optimization
565 23:16:50.313424 INFO : End of write delay center optimization
566 23:16:50.318694 INFO : End of read delay center optimization
567 23:16:50.324192 INFO : End of max read latency training
568 23:16:50.324635 INFO : Training has run successfully!
569 23:16:50.329797 1D training succeed
570 23:16:50.335771 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 23:16:50.383478 Check phy result
572 23:16:50.383958 INFO : End of initialization
573 23:16:50.404942 INFO : End of 2D read delay Voltage center optimization
574 23:16:50.425138 INFO : End of 2D read delay Voltage center optimization
575 23:16:50.477111 INFO : End of 2D write delay Voltage center optimization
576 23:16:50.526259 INFO : End of 2D write delay Voltage center optimization
577 23:16:50.531772 INFO : Training has run successfully!
578 23:16:50.532243
579 23:16:50.532667 channel==0
580 23:16:50.537398 RxClkDly_Margin_A0==88 ps 9
581 23:16:50.537824 TxDqDly_Margin_A0==98 ps 10
582 23:16:50.542932 RxClkDly_Margin_A1==88 ps 9
583 23:16:50.543356 TxDqDly_Margin_A1==98 ps 10
584 23:16:50.543756 TrainedVREFDQ_A0==74
585 23:16:50.548548 TrainedVREFDQ_A1==74
586 23:16:50.548975 VrefDac_Margin_A0==25
587 23:16:50.549370 DeviceVref_Margin_A0==40
588 23:16:50.554206 VrefDac_Margin_A1==25
589 23:16:50.554627 DeviceVref_Margin_A1==40
590 23:16:50.555028
591 23:16:50.555428
592 23:16:50.559794 channel==1
593 23:16:50.560247 RxClkDly_Margin_A0==98 ps 10
594 23:16:50.560651 TxDqDly_Margin_A0==98 ps 10
595 23:16:50.565569 RxClkDly_Margin_A1==98 ps 10
596 23:16:50.565992 TxDqDly_Margin_A1==88 ps 9
597 23:16:50.571043 TrainedVREFDQ_A0==77
598 23:16:50.571472 TrainedVREFDQ_A1==77
599 23:16:50.571873 VrefDac_Margin_A0==22
600 23:16:50.576732 DeviceVref_Margin_A0==37
601 23:16:50.577155 VrefDac_Margin_A1==22
602 23:16:50.582135 DeviceVref_Margin_A1==37
603 23:16:50.582557
604 23:16:50.582957 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 23:16:50.587740
606 23:16:50.615778 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 23:16:50.616267 2D training succeed
608 23:16:50.621394 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 23:16:50.626964 auto size-- 65535DDR cs0 size: 2048MB
610 23:16:50.627393 DDR cs1 size: 2048MB
611 23:16:50.632528 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 23:16:50.632954 cs0 DataBus test pass
613 23:16:50.638147 cs1 DataBus test pass
614 23:16:50.638577 cs0 AddrBus test pass
615 23:16:50.638978 cs1 AddrBus test pass
616 23:16:50.639370
617 23:16:50.643756 100bdlr_step_size ps== 420
618 23:16:50.644223 result report
619 23:16:50.649312 boot times 0Enable ddr reg access
620 23:16:50.654814 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 23:16:50.668263 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 23:16:51.240220 0.0;M3 CHK:0;cm4_sp_mode 0
623 23:16:51.240743 MVN_1=0x00000000
624 23:16:51.245750 MVN_2=0x00000000
625 23:16:51.251518 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 23:16:51.251974 OPS=0x10
627 23:16:51.252448 ring efuse init
628 23:16:51.252849 chipver efuse init
629 23:16:51.257220 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 23:16:51.262747 [0.018961 Inits done]
631 23:16:51.263162 secure task start!
632 23:16:51.263547 high task start!
633 23:16:51.266472 low task start!
634 23:16:51.266891 run into bl31
635 23:16:51.273993 NOTICE: BL31: v1.3(release):4fc40b1
636 23:16:51.281840 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 23:16:51.282263 NOTICE: BL31: G12A normal boot!
638 23:16:51.307156 NOTICE: BL31: BL33 decompress pass
639 23:16:51.312926 ERROR: Error initializing runtime service opteed_fast
640 23:16:52.546051
641 23:16:52.546611
642 23:16:52.554394 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 23:16:52.554838
644 23:16:52.555242 Model: Libre Computer AML-A311D-CC Alta
645 23:16:52.762901 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 23:16:52.786183 DRAM: 2 GiB (effective 3.8 GiB)
647 23:16:52.929223 Core: 408 devices, 31 uclasses, devicetree: separate
648 23:16:52.935001 WDT: Not starting watchdog@f0d0
649 23:16:52.967151 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 23:16:52.979641 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 23:16:52.984605 ** Bad device specification mmc 0 **
652 23:16:52.994962 Card did not respond to voltage select! : -110
653 23:16:53.002547 ** Bad device specification mmc 0 **
654 23:16:53.002977 Couldn't find partition mmc 0
655 23:16:53.010898 Card did not respond to voltage select! : -110
656 23:16:53.016462 ** Bad device specification mmc 0 **
657 23:16:53.016899 Couldn't find partition mmc 0
658 23:16:53.021480 Error: could not access storage.
659 23:16:53.363205 Net: eth0: ethernet@ff3f0000
660 23:16:53.363714 starting USB...
661 23:16:53.615714 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 23:16:53.616267 Starting the controller
663 23:16:53.621787 USB XHCI 1.10
664 23:16:55.336560 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 23:16:55.337232 bl2_stage_init 0x01
666 23:16:55.337715 bl2_stage_init 0x81
667 23:16:55.342232 hw id: 0x0000 - pwm id 0x01
668 23:16:55.342808 bl2_stage_init 0xc1
669 23:16:55.343270 bl2_stage_init 0x02
670 23:16:55.343721
671 23:16:55.347755 L0:00000000
672 23:16:55.348317 L1:20000703
673 23:16:55.348776 L2:00008067
674 23:16:55.349215 L3:14000000
675 23:16:55.353475 B2:00402000
676 23:16:55.354022 B1:e0f83180
677 23:16:55.354477
678 23:16:55.354922 TE: 58124
679 23:16:55.355364
680 23:16:55.358953 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 23:16:55.359472
682 23:16:55.359929 Board ID = 1
683 23:16:55.364546 Set A53 clk to 24M
684 23:16:55.365058 Set A73 clk to 24M
685 23:16:55.365506 Set clk81 to 24M
686 23:16:55.370163 A53 clk: 1200 MHz
687 23:16:55.370688 A73 clk: 1200 MHz
688 23:16:55.371136 CLK81: 166.6M
689 23:16:55.371575 smccc: 00012a92
690 23:16:55.375749 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 23:16:55.381405 board id: 1
692 23:16:55.387203 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 23:16:55.397845 fw parse done
694 23:16:55.402882 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 23:16:55.446305 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 23:16:55.457401 PIEI prepare done
697 23:16:55.457906 fastboot data load
698 23:16:55.458368 fastboot data verify
699 23:16:55.463056 verify result: 266
700 23:16:55.469606 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 23:16:55.470113 LPDDR4 probe
702 23:16:55.470565 ddr clk to 1584MHz
703 23:16:55.475743 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 23:16:55.513913
705 23:16:55.514461 dmc_version 0001
706 23:16:55.519664 Check phy result
707 23:16:55.526507 INFO : End of CA training
708 23:16:55.527007 INFO : End of initialization
709 23:16:55.532045 INFO : Training has run successfully!
710 23:16:55.532542 Check phy result
711 23:16:55.537631 INFO : End of initialization
712 23:16:55.538129 INFO : End of read enable training
713 23:16:55.543217 INFO : End of fine write leveling
714 23:16:55.548844 INFO : End of Write leveling coarse delay
715 23:16:55.549339 INFO : Training has run successfully!
716 23:16:55.549783 Check phy result
717 23:16:55.554512 INFO : End of initialization
718 23:16:55.555011 INFO : End of read dq deskew training
719 23:16:55.560040 INFO : End of MPR read delay center optimization
720 23:16:55.565590 INFO : End of write delay center optimization
721 23:16:55.571191 INFO : End of read delay center optimization
722 23:16:55.571686 INFO : End of max read latency training
723 23:16:55.576858 INFO : Training has run successfully!
724 23:16:55.577372 1D training succeed
725 23:16:55.585944 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 23:16:55.632711 Check phy result
727 23:16:55.633238 INFO : End of initialization
728 23:16:55.654301 INFO : End of 2D read delay Voltage center optimization
729 23:16:55.674474 INFO : End of 2D read delay Voltage center optimization
730 23:16:55.727354 INFO : End of 2D write delay Voltage center optimization
731 23:16:55.776541 INFO : End of 2D write delay Voltage center optimization
732 23:16:55.782033 INFO : Training has run successfully!
733 23:16:55.782542
734 23:16:55.782998 channel==0
735 23:16:55.787616 RxClkDly_Margin_A0==88 ps 9
736 23:16:55.788159 TxDqDly_Margin_A0==98 ps 10
737 23:16:55.793301 RxClkDly_Margin_A1==88 ps 9
738 23:16:55.793839 TxDqDly_Margin_A1==88 ps 9
739 23:16:55.794302 TrainedVREFDQ_A0==74
740 23:16:55.798845 TrainedVREFDQ_A1==74
741 23:16:55.799392 VrefDac_Margin_A0==25
742 23:16:55.799833 DeviceVref_Margin_A0==40
743 23:16:55.804533 VrefDac_Margin_A1==25
744 23:16:55.805032 DeviceVref_Margin_A1==40
745 23:16:55.805474
746 23:16:55.805910
747 23:16:55.806343 channel==1
748 23:16:55.810022 RxClkDly_Margin_A0==98 ps 10
749 23:16:55.810518 TxDqDly_Margin_A0==88 ps 9
750 23:16:55.815598 RxClkDly_Margin_A1==98 ps 10
751 23:16:55.816132 TxDqDly_Margin_A1==88 ps 9
752 23:16:55.821182 TrainedVREFDQ_A0==77
753 23:16:55.821677 TrainedVREFDQ_A1==77
754 23:16:55.822118 VrefDac_Margin_A0==22
755 23:16:55.826824 DeviceVref_Margin_A0==37
756 23:16:55.827317 VrefDac_Margin_A1==22
757 23:16:55.832545 DeviceVref_Margin_A1==37
758 23:16:55.833045
759 23:16:55.833487 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 23:16:55.833922
761 23:16:55.865928 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
762 23:16:55.866460 2D training succeed
763 23:16:55.871626 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 23:16:55.877165 auto size-- 65535DDR cs0 size: 2048MB
765 23:16:55.877668 DDR cs1 size: 2048MB
766 23:16:55.882843 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 23:16:55.883363 cs0 DataBus test pass
768 23:16:55.888560 cs1 DataBus test pass
769 23:16:55.889059 cs0 AddrBus test pass
770 23:16:55.889505 cs1 AddrBus test pass
771 23:16:55.889945
772 23:16:55.894011 100bdlr_step_size ps== 420
773 23:16:55.894523 result report
774 23:16:55.899645 boot times 0Enable ddr reg access
775 23:16:55.903969 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 23:16:55.918329 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 23:16:56.490274 0.0;M3 CHK:0;cm4_sp_mode 0
778 23:16:56.490937 MVN_1=0x00000000
779 23:16:56.495975 MVN_2=0x00000000
780 23:16:56.501610 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 23:16:56.502150 OPS=0x10
782 23:16:56.502591 ring efuse init
783 23:16:56.503018 chipver efuse init
784 23:16:56.507164 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 23:16:56.512743 [0.018960 Inits done]
786 23:16:56.513228 secure task start!
787 23:16:56.513663 high task start!
788 23:16:56.516796 low task start!
789 23:16:56.517286 run into bl31
790 23:16:56.523954 NOTICE: BL31: v1.3(release):4fc40b1
791 23:16:56.530841 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 23:16:56.531332 NOTICE: BL31: G12A normal boot!
793 23:16:56.557207 NOTICE: BL31: BL33 decompress pass
794 23:16:56.562924 ERROR: Error initializing runtime service opteed_fast
795 23:16:57.982171
796 23:16:57.982834
797 23:16:57.984507 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 23:16:57.985025
799 23:16:57.985687 Model: Libre Computer AML-A311D-CC Alta
800 23:16:58.012701 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 23:16:58.036155 DRAM: 2 GiB (effective 3.8 GiB)
802 23:16:58.178976 Core: 408 devices, 31 uclasses, devicetree: separate
803 23:16:58.184905 WDT: Not starting watchdog@f0d0
804 23:16:58.217155 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 23:16:58.229573 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 23:16:58.234428 ** Bad device specification mmc 0 **
807 23:16:58.244907 Card did not respond to voltage select! : -110
808 23:16:58.252684 ** Bad device specification mmc 0 **
809 23:16:58.253185 Couldn't find partition mmc 0
810 23:16:58.260945 Card did not respond to voltage select! : -110
811 23:16:58.266455 ** Bad device specification mmc 0 **
812 23:16:58.266959 Couldn't find partition mmc 0
813 23:16:58.271498 Error: could not access storage.
814 23:16:58.614102 Net: eth0: ethernet@ff3f0000
815 23:16:58.614767 starting USB...
816 23:16:58.865889 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 23:16:58.866456 Starting the controller
818 23:16:58.873019 USB XHCI 1.10
819 23:17:01.036542 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 23:17:01.037214 bl2_stage_init 0x01
821 23:17:01.037686 bl2_stage_init 0x81
822 23:17:01.042184 hw id: 0x0000 - pwm id 0x01
823 23:17:01.042690 bl2_stage_init 0xc1
824 23:17:01.043144 bl2_stage_init 0x02
825 23:17:01.043589
826 23:17:01.047586 L0:00000000
827 23:17:01.048114 L1:20000703
828 23:17:01.048568 L2:00008067
829 23:17:01.049011 L3:14000000
830 23:17:01.053229 B2:00402000
831 23:17:01.053726 B1:e0f83180
832 23:17:01.054174
833 23:17:01.054613 TE: 58124
834 23:17:01.055061
835 23:17:01.058894 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 23:17:01.059392
837 23:17:01.059846 Board ID = 1
838 23:17:01.064396 Set A53 clk to 24M
839 23:17:01.064901 Set A73 clk to 24M
840 23:17:01.065351 Set clk81 to 24M
841 23:17:01.070096 A53 clk: 1200 MHz
842 23:17:01.070600 A73 clk: 1200 MHz
843 23:17:01.071056 CLK81: 166.6M
844 23:17:01.071495 smccc: 00012a92
845 23:17:01.075614 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 23:17:01.081244 board id: 1
847 23:17:01.087252 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 23:17:01.097787 fw parse done
849 23:17:01.103804 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 23:17:01.146312 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 23:17:01.157190 PIEI prepare done
852 23:17:01.157686 fastboot data load
853 23:17:01.158135 fastboot data verify
854 23:17:01.162916 verify result: 266
855 23:17:01.168441 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 23:17:01.168929 LPDDR4 probe
857 23:17:01.169376 ddr clk to 1584MHz
858 23:17:01.176434 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 23:17:01.213693
860 23:17:01.214216 dmc_version 0001
861 23:17:01.220381 Check phy result
862 23:17:01.226240 INFO : End of CA training
863 23:17:01.226745 INFO : End of initialization
864 23:17:01.231860 INFO : Training has run successfully!
865 23:17:01.232386 Check phy result
866 23:17:01.237410 INFO : End of initialization
867 23:17:01.237892 INFO : End of read enable training
868 23:17:01.240729 INFO : End of fine write leveling
869 23:17:01.246461 INFO : End of Write leveling coarse delay
870 23:17:01.252033 INFO : Training has run successfully!
871 23:17:01.252592 Check phy result
872 23:17:01.253054 INFO : End of initialization
873 23:17:01.257570 INFO : End of read dq deskew training
874 23:17:01.263241 INFO : End of MPR read delay center optimization
875 23:17:01.263751 INFO : End of write delay center optimization
876 23:17:01.268728 INFO : End of read delay center optimization
877 23:17:01.274405 INFO : End of max read latency training
878 23:17:01.274912 INFO : Training has run successfully!
879 23:17:01.279960 1D training succeed
880 23:17:01.285970 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 23:17:01.333537 Check phy result
882 23:17:01.334136 INFO : End of initialization
883 23:17:01.355248 INFO : End of 2D read delay Voltage center optimization
884 23:17:01.375294 INFO : End of 2D read delay Voltage center optimization
885 23:17:01.427210 INFO : End of 2D write delay Voltage center optimization
886 23:17:01.476401 INFO : End of 2D write delay Voltage center optimization
887 23:17:01.482095 INFO : Training has run successfully!
888 23:17:01.482595
889 23:17:01.483051 channel==0
890 23:17:01.487548 RxClkDly_Margin_A0==88 ps 9
891 23:17:01.488143 TxDqDly_Margin_A0==98 ps 10
892 23:17:01.493282 RxClkDly_Margin_A1==88 ps 9
893 23:17:01.493829 TxDqDly_Margin_A1==98 ps 10
894 23:17:01.494270 TrainedVREFDQ_A0==74
895 23:17:01.498893 TrainedVREFDQ_A1==74
896 23:17:01.499410 VrefDac_Margin_A0==25
897 23:17:01.499845 DeviceVref_Margin_A0==40
898 23:17:01.504409 VrefDac_Margin_A1==25
899 23:17:01.504945 DeviceVref_Margin_A1==40
900 23:17:01.505412
901 23:17:01.505846
902 23:17:01.510151 channel==1
903 23:17:01.510657 RxClkDly_Margin_A0==98 ps 10
904 23:17:01.511088 TxDqDly_Margin_A0==98 ps 10
905 23:17:01.517399 RxClkDly_Margin_A1==98 ps 10
906 23:17:01.517892 TxDqDly_Margin_A1==88 ps 9
907 23:17:01.518326 TrainedVREFDQ_A0==77
908 23:17:01.523056 TrainedVREFDQ_A1==77
909 23:17:01.523547 VrefDac_Margin_A0==22
910 23:17:01.523974 DeviceVref_Margin_A0==37
911 23:17:01.528646 VrefDac_Margin_A1==22
912 23:17:01.529128 DeviceVref_Margin_A1==37
913 23:17:01.529560
914 23:17:01.534263 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 23:17:01.534750
916 23:17:01.567834 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
917 23:17:01.568402 2D training succeed
918 23:17:01.573487 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 23:17:01.578958 auto size-- 65535DDR cs0 size: 2048MB
920 23:17:01.579447 DDR cs1 size: 2048MB
921 23:17:01.584570 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 23:17:01.585060 cs0 DataBus test pass
923 23:17:01.585487 cs1 DataBus test pass
924 23:17:01.590248 cs0 AddrBus test pass
925 23:17:01.590732 cs1 AddrBus test pass
926 23:17:01.591157
927 23:17:01.591584 100bdlr_step_size ps== 420
928 23:17:01.595761 result report
929 23:17:01.596285 boot times 0Enable ddr reg access
930 23:17:01.604859 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 23:17:01.618336 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 23:17:02.190259 0.0;M3 CHK:0;cm4_sp_mode 0
933 23:17:02.190897 MVN_1=0x00000000
934 23:17:02.195854 MVN_2=0x00000000
935 23:17:02.201616 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 23:17:02.202124 OPS=0x10
937 23:17:02.202575 ring efuse init
938 23:17:02.203012 chipver efuse init
939 23:17:02.209832 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 23:17:02.210379 [0.018961 Inits done]
941 23:17:02.217365 secure task start!
942 23:17:02.217866 high task start!
943 23:17:02.218314 low task start!
944 23:17:02.218754 run into bl31
945 23:17:02.224081 NOTICE: BL31: v1.3(release):4fc40b1
946 23:17:02.231857 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 23:17:02.232393 NOTICE: BL31: G12A normal boot!
948 23:17:02.257253 NOTICE: BL31: BL33 decompress pass
949 23:17:02.263004 ERROR: Error initializing runtime service opteed_fast
950 23:17:03.495762
951 23:17:03.496427
952 23:17:03.504215 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 23:17:03.504732
954 23:17:03.505206 Model: Libre Computer AML-A311D-CC Alta
955 23:17:03.712609 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 23:17:03.736056 DRAM: 2 GiB (effective 3.8 GiB)
957 23:17:03.878994 Core: 408 devices, 31 uclasses, devicetree: separate
958 23:17:03.884848 WDT: Not starting watchdog@f0d0
959 23:17:03.917127 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 23:17:03.929526 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 23:17:03.934558 ** Bad device specification mmc 0 **
962 23:17:03.944872 Card did not respond to voltage select! : -110
963 23:17:03.952559 ** Bad device specification mmc 0 **
964 23:17:03.953062 Couldn't find partition mmc 0
965 23:17:03.960880 Card did not respond to voltage select! : -110
966 23:17:03.966455 ** Bad device specification mmc 0 **
967 23:17:03.966956 Couldn't find partition mmc 0
968 23:17:03.971524 Error: could not access storage.
969 23:17:04.313005 Net: eth0: ethernet@ff3f0000
970 23:17:04.313605 starting USB...
971 23:17:04.565789 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 23:17:04.566420 Starting the controller
973 23:17:04.571799 USB XHCI 1.10
974 23:17:06.436314 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 23:17:06.436992 bl2_stage_init 0x01
976 23:17:06.437461 bl2_stage_init 0x81
977 23:17:06.441874 hw id: 0x0000 - pwm id 0x01
978 23:17:06.442396 bl2_stage_init 0xc1
979 23:17:06.442856 bl2_stage_init 0x02
980 23:17:06.443300
981 23:17:06.447466 L0:00000000
982 23:17:06.448018 L1:20000703
983 23:17:06.448484 L2:00008067
984 23:17:06.448925 L3:14000000
985 23:17:06.453046 B2:00402000
986 23:17:06.453549 B1:e0f83180
987 23:17:06.453997
988 23:17:06.454440 TE: 58124
989 23:17:06.454882
990 23:17:06.458811 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 23:17:06.459318
992 23:17:06.459771 Board ID = 1
993 23:17:06.464251 Set A53 clk to 24M
994 23:17:06.464754 Set A73 clk to 24M
995 23:17:06.465202 Set clk81 to 24M
996 23:17:06.469838 A53 clk: 1200 MHz
997 23:17:06.470339 A73 clk: 1200 MHz
998 23:17:06.470786 CLK81: 166.6M
999 23:17:06.471228 smccc: 00012a92
1000 23:17:06.475418 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 23:17:06.480992 board id: 1
1002 23:17:06.486914 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 23:17:06.497627 fw parse done
1004 23:17:06.503656 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 23:17:06.546177 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 23:17:06.557049 PIEI prepare done
1007 23:17:06.557537 fastboot data load
1008 23:17:06.557972 fastboot data verify
1009 23:17:06.562901 verify result: 266
1010 23:17:06.568358 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 23:17:06.568848 LPDDR4 probe
1012 23:17:06.569281 ddr clk to 1584MHz
1013 23:17:06.576363 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 23:17:06.613720
1015 23:17:06.614225 dmc_version 0001
1016 23:17:06.620364 Check phy result
1017 23:17:06.626185 INFO : End of CA training
1018 23:17:06.626689 INFO : End of initialization
1019 23:17:06.632034 INFO : Training has run successfully!
1020 23:17:06.632614 Check phy result
1021 23:17:06.637480 INFO : End of initialization
1022 23:17:06.637985 INFO : End of read enable training
1023 23:17:06.643126 INFO : End of fine write leveling
1024 23:17:06.648731 INFO : End of Write leveling coarse delay
1025 23:17:06.649236 INFO : Training has run successfully!
1026 23:17:06.649694 Check phy result
1027 23:17:06.654232 INFO : End of initialization
1028 23:17:06.654732 INFO : End of read dq deskew training
1029 23:17:06.659949 INFO : End of MPR read delay center optimization
1030 23:17:06.665519 INFO : End of write delay center optimization
1031 23:17:06.671027 INFO : End of read delay center optimization
1032 23:17:06.671524 INFO : End of max read latency training
1033 23:17:06.676570 INFO : Training has run successfully!
1034 23:17:06.677072 1D training succeed
1035 23:17:06.685703 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 23:17:06.733355 Check phy result
1037 23:17:06.733882 INFO : End of initialization
1038 23:17:06.756053 INFO : End of 2D read delay Voltage center optimization
1039 23:17:06.776116 INFO : End of 2D read delay Voltage center optimization
1040 23:17:06.828181 INFO : End of 2D write delay Voltage center optimization
1041 23:17:06.877512 INFO : End of 2D write delay Voltage center optimization
1042 23:17:06.883072 INFO : Training has run successfully!
1043 23:17:06.883569
1044 23:17:06.884092 channel==0
1045 23:17:06.888687 RxClkDly_Margin_A0==88 ps 9
1046 23:17:06.889198 TxDqDly_Margin_A0==98 ps 10
1047 23:17:06.894292 RxClkDly_Margin_A1==88 ps 9
1048 23:17:06.894786 TxDqDly_Margin_A1==98 ps 10
1049 23:17:06.895237 TrainedVREFDQ_A0==74
1050 23:17:06.899953 TrainedVREFDQ_A1==74
1051 23:17:06.900482 VrefDac_Margin_A0==24
1052 23:17:06.900928 DeviceVref_Margin_A0==40
1053 23:17:06.905476 VrefDac_Margin_A1==25
1054 23:17:06.905975 DeviceVref_Margin_A1==40
1055 23:17:06.906421
1056 23:17:06.906862
1057 23:17:06.911051 channel==1
1058 23:17:06.911544 RxClkDly_Margin_A0==98 ps 10
1059 23:17:06.912025 TxDqDly_Margin_A0==98 ps 10
1060 23:17:06.916661 RxClkDly_Margin_A1==98 ps 10
1061 23:17:06.917155 TxDqDly_Margin_A1==88 ps 9
1062 23:17:06.922263 TrainedVREFDQ_A0==77
1063 23:17:06.922757 TrainedVREFDQ_A1==77
1064 23:17:06.923203 VrefDac_Margin_A0==22
1065 23:17:06.927955 DeviceVref_Margin_A0==37
1066 23:17:06.928475 VrefDac_Margin_A1==22
1067 23:17:06.933515 DeviceVref_Margin_A1==37
1068 23:17:06.934024
1069 23:17:06.934473 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 23:17:06.939099
1071 23:17:06.967032 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000017 00000016 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1072 23:17:06.967563 2D training succeed
1073 23:17:06.972684 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 23:17:06.978275 auto size-- 65535DDR cs0 size: 2048MB
1075 23:17:06.978772 DDR cs1 size: 2048MB
1076 23:17:06.983966 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 23:17:06.984515 cs0 DataBus test pass
1078 23:17:06.989463 cs1 DataBus test pass
1079 23:17:06.989958 cs0 AddrBus test pass
1080 23:17:06.990409 cs1 AddrBus test pass
1081 23:17:06.990847
1082 23:17:06.995085 100bdlr_step_size ps== 420
1083 23:17:06.995593 result report
1084 23:17:07.000689 boot times 0Enable ddr reg access
1085 23:17:07.006113 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 23:17:07.019534 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 23:17:07.593277 0.0;M3 CHK:0;cm4_sp_mode 0
1088 23:17:07.593931 MVN_1=0x00000000
1089 23:17:07.598780 MVN_2=0x00000000
1090 23:17:07.604504 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 23:17:07.605008 OPS=0x10
1092 23:17:07.605471 ring efuse init
1093 23:17:07.605920 chipver efuse init
1094 23:17:07.612716 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 23:17:07.613240 [0.018960 Inits done]
1096 23:17:07.619317 secure task start!
1097 23:17:07.619817 high task start!
1098 23:17:07.620315 low task start!
1099 23:17:07.620763 run into bl31
1100 23:17:07.626950 NOTICE: BL31: v1.3(release):4fc40b1
1101 23:17:07.634100 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 23:17:07.634680 NOTICE: BL31: G12A normal boot!
1103 23:17:07.660214 NOTICE: BL31: BL33 decompress pass
1104 23:17:07.664885 ERROR: Error initializing runtime service opteed_fast
1105 23:17:08.898621
1106 23:17:08.899256
1107 23:17:08.907112 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 23:17:08.907632
1109 23:17:08.908143 Model: Libre Computer AML-A311D-CC Alta
1110 23:17:09.115542 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 23:17:09.138934 DRAM: 2 GiB (effective 3.8 GiB)
1112 23:17:09.281967 Core: 408 devices, 31 uclasses, devicetree: separate
1113 23:17:09.287770 WDT: Not starting watchdog@f0d0
1114 23:17:09.319939 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 23:17:09.332398 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 23:17:09.337354 ** Bad device specification mmc 0 **
1117 23:17:09.347759 Card did not respond to voltage select! : -110
1118 23:17:09.355358 ** Bad device specification mmc 0 **
1119 23:17:09.355702 Couldn't find partition mmc 0
1120 23:17:09.363667 Card did not respond to voltage select! : -110
1121 23:17:09.369221 ** Bad device specification mmc 0 **
1122 23:17:09.369739 Couldn't find partition mmc 0
1123 23:17:09.374319 Error: could not access storage.
1124 23:17:09.716819 Net: eth0: ethernet@ff3f0000
1125 23:17:09.717392 starting USB...
1126 23:17:09.968556 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 23:17:09.969102 Starting the controller
1128 23:17:09.975494 USB XHCI 1.10
1129 23:17:11.532863 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 23:17:11.541006 scanning usb for storage devices... 0 Storage Device(s) found
1132 23:17:11.592606 Hit any key to stop autoboot: 1
1133 23:17:11.593401 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 23:17:11.593983 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 23:17:11.594431 Setting prompt string to ['=>']
1136 23:17:11.594884 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 23:17:11.608441 0
1138 23:17:11.609317 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 23:17:11.609801 Sending with 10 millisecond of delay
1141 23:17:12.744426 => setenv autoload no
1142 23:17:12.755202 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 23:17:12.760040 setenv autoload no
1144 23:17:12.760782 Sending with 10 millisecond of delay
1146 23:17:14.557363 => setenv initrd_high 0xffffffff
1147 23:17:14.568142 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 23:17:14.568996 setenv initrd_high 0xffffffff
1149 23:17:14.569704 Sending with 10 millisecond of delay
1151 23:17:16.185777 => setenv fdt_high 0xffffffff
1152 23:17:16.196555 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1153 23:17:16.197385 setenv fdt_high 0xffffffff
1154 23:17:16.198099 Sending with 10 millisecond of delay
1156 23:17:16.489851 => dhcp
1157 23:17:16.500592 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 23:17:16.501432 dhcp
1159 23:17:16.501867 Speed: 1000, full duplex
1160 23:17:16.502280 BOOTP broadcast 1
1161 23:17:16.515352 DHCP client bound to address 192.168.6.27 (15 ms)
1162 23:17:16.516081 Sending with 10 millisecond of delay
1164 23:17:18.192170 => setenv serverip 192.168.6.2
1165 23:17:18.202950 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1166 23:17:18.203816 setenv serverip 192.168.6.2
1167 23:17:18.204559 Sending with 10 millisecond of delay
1169 23:17:21.927319 => tftpboot 0x01080000 977229/tftp-deploy-y5xxna7m/kernel/uImage
1170 23:17:21.938141 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1171 23:17:21.938966 tftpboot 0x01080000 977229/tftp-deploy-y5xxna7m/kernel/uImage
1172 23:17:21.939426 Speed: 1000, full duplex
1173 23:17:21.939839 Using ethernet@ff3f0000 device
1174 23:17:21.941163 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 23:17:21.946653 Filename '977229/tftp-deploy-y5xxna7m/kernel/uImage'.
1176 23:17:21.950319 Load address: 0x1080000
1177 23:17:24.786492 Loading: *################################################## 43.6 MiB
1178 23:17:24.787170 15.4 MiB/s
1179 23:17:24.787655 done
1180 23:17:24.791058 Bytes transferred = 45713984 (2b98a40 hex)
1181 23:17:24.791921 Sending with 10 millisecond of delay
1183 23:17:29.479921 => tftpboot 0x08000000 977229/tftp-deploy-y5xxna7m/ramdisk/ramdisk.cpio.gz.uboot
1184 23:17:29.490835 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 23:17:29.491766 tftpboot 0x08000000 977229/tftp-deploy-y5xxna7m/ramdisk/ramdisk.cpio.gz.uboot
1186 23:17:29.492300 Speed: 1000, full duplex
1187 23:17:29.492762 Using ethernet@ff3f0000 device
1188 23:17:29.493794 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 23:17:29.502365 Filename '977229/tftp-deploy-y5xxna7m/ramdisk/ramdisk.cpio.gz.uboot'.
1190 23:17:29.502906 Load address: 0x8000000
1191 23:17:36.023500 Loading: *#####################T ############################ UDP wrong checksum 00000005 0000d2cd
1192 23:17:41.024699 T UDP wrong checksum 00000005 0000d2cd
1193 23:17:51.027866 T T UDP wrong checksum 00000005 0000d2cd
1194 23:18:11.031866 T T T T UDP wrong checksum 00000005 0000d2cd
1195 23:18:23.572852 T T UDP wrong checksum 000000ff 0000942a
1196 23:18:23.615132 UDP wrong checksum 000000ff 0000301d
1197 23:18:26.035881
1198 23:18:26.036645 Retry count exceeded; starting again
1200 23:18:26.038168 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1203 23:18:26.040242 end: 2.4 uboot-commands (duration 00:01:51) [common]
1205 23:18:26.041763 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1207 23:18:26.042892 end: 2 uboot-action (duration 00:01:51) [common]
1209 23:18:26.044732 Cleaning after the job
1210 23:18:26.045351 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/ramdisk
1211 23:18:26.046896 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/kernel
1212 23:18:26.095403 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/dtb
1213 23:18:26.096410 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/nfsrootfs
1214 23:18:26.255472 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/977229/tftp-deploy-y5xxna7m/modules
1215 23:18:26.274499 start: 4.1 power-off (timeout 00:00:30) [common]
1216 23:18:26.275134 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1217 23:18:26.308650 >> OK - accepted request
1218 23:18:26.310651 Returned 0 in 0 seconds
1219 23:18:26.411417 end: 4.1 power-off (duration 00:00:00) [common]
1221 23:18:26.412454 start: 4.2 read-feedback (timeout 00:10:00) [common]
1222 23:18:26.413127 Listened to connection for namespace 'common' for up to 1s
1223 23:18:27.414093 Finalising connection for namespace 'common'
1224 23:18:27.414599 Disconnecting from shell: Finalise
1225 23:18:27.414902 =>
1226 23:18:27.515620 end: 4.2 read-feedback (duration 00:00:01) [common]
1227 23:18:27.516165 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/977229
1228 23:18:30.377602 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/977229
1229 23:18:30.378235 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.