Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 6
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 13:43:46.029207 lava-dispatcher, installed at version: 2024.01
2 13:43:46.030013 start: 0 validate
3 13:43:46.030475 Start time: 2024-10-22 13:43:46.030445+00:00 (UTC)
4 13:43:46.031007 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 13:43:46.031562 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:43:46.071975 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 13:43:46.072546 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fv6.12-rc2-163-g376efb6ef727%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 13:43:46.104333 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 13:43:46.104964 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fv6.12-rc2-163-g376efb6ef727%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 13:43:46.134852 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 13:43:46.135345 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:43:46.165779 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 13:43:46.166289 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fv6.12-rc2-163-g376efb6ef727%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 13:43:46.206692 validate duration: 0.18
16 13:43:46.207539 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:43:46.207865 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:43:46.208213 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:43:46.208789 Not decompressing ramdisk as can be used compressed.
20 13:43:46.209250 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 13:43:46.209539 saving as /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/ramdisk/initrd.cpio.gz
22 13:43:46.209810 total size: 5628169 (5 MB)
23 13:43:46.245989 progress 0 % (0 MB)
24 13:43:46.253354 progress 5 % (0 MB)
25 13:43:46.261164 progress 10 % (0 MB)
26 13:43:46.268322 progress 15 % (0 MB)
27 13:43:46.274044 progress 20 % (1 MB)
28 13:43:46.277884 progress 25 % (1 MB)
29 13:43:46.282115 progress 30 % (1 MB)
30 13:43:46.286273 progress 35 % (1 MB)
31 13:43:46.290013 progress 40 % (2 MB)
32 13:43:46.294180 progress 45 % (2 MB)
33 13:43:46.297800 progress 50 % (2 MB)
34 13:43:46.301755 progress 55 % (2 MB)
35 13:43:46.306092 progress 60 % (3 MB)
36 13:43:46.309885 progress 65 % (3 MB)
37 13:43:46.313804 progress 70 % (3 MB)
38 13:43:46.317384 progress 75 % (4 MB)
39 13:43:46.321253 progress 80 % (4 MB)
40 13:43:46.324802 progress 85 % (4 MB)
41 13:43:46.328735 progress 90 % (4 MB)
42 13:43:46.332582 progress 95 % (5 MB)
43 13:43:46.335827 progress 100 % (5 MB)
44 13:43:46.336493 5 MB downloaded in 0.13 s (42.38 MB/s)
45 13:43:46.337023 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:43:46.337908 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:43:46.338200 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:43:46.338468 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:43:46.338927 downloading http://storage.kernelci.org/broonie-sound/for-next/v6.12-rc2-163-g376efb6ef727/arm64/defconfig/gcc-12/kernel/Image
51 13:43:46.339169 saving as /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/kernel/Image
52 13:43:46.339377 total size: 45713920 (43 MB)
53 13:43:46.339588 No compression specified
54 13:43:46.374965 progress 0 % (0 MB)
55 13:43:46.404318 progress 5 % (2 MB)
56 13:43:46.433317 progress 10 % (4 MB)
57 13:43:46.463430 progress 15 % (6 MB)
58 13:43:46.494970 progress 20 % (8 MB)
59 13:43:46.526029 progress 25 % (10 MB)
60 13:43:46.556080 progress 30 % (13 MB)
61 13:43:46.585411 progress 35 % (15 MB)
62 13:43:46.614605 progress 40 % (17 MB)
63 13:43:46.643404 progress 45 % (19 MB)
64 13:43:46.672080 progress 50 % (21 MB)
65 13:43:46.701764 progress 55 % (24 MB)
66 13:43:46.730723 progress 60 % (26 MB)
67 13:43:46.759616 progress 65 % (28 MB)
68 13:43:46.788829 progress 70 % (30 MB)
69 13:43:46.818374 progress 75 % (32 MB)
70 13:43:46.847761 progress 80 % (34 MB)
71 13:43:46.876466 progress 85 % (37 MB)
72 13:43:46.906029 progress 90 % (39 MB)
73 13:43:46.935214 progress 95 % (41 MB)
74 13:43:46.963757 progress 100 % (43 MB)
75 13:43:46.964309 43 MB downloaded in 0.62 s (69.76 MB/s)
76 13:43:46.964778 end: 1.2.1 http-download (duration 00:00:01) [common]
78 13:43:46.965590 end: 1.2 download-retry (duration 00:00:01) [common]
79 13:43:46.965861 start: 1.3 download-retry (timeout 00:09:59) [common]
80 13:43:46.966124 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 13:43:46.966580 downloading http://storage.kernelci.org/broonie-sound/for-next/v6.12-rc2-163-g376efb6ef727/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 13:43:46.966840 saving as /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/dtb/meson-g12b-a311d-libretech-cc.dtb
83 13:43:46.967049 total size: 54703 (0 MB)
84 13:43:46.967257 No compression specified
85 13:43:47.004880 progress 59 % (0 MB)
86 13:43:47.005694 progress 100 % (0 MB)
87 13:43:47.006245 0 MB downloaded in 0.04 s (1.33 MB/s)
88 13:43:47.006699 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:43:47.007506 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:43:47.007767 start: 1.4 download-retry (timeout 00:09:59) [common]
92 13:43:47.008057 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 13:43:47.008512 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 13:43:47.008749 saving as /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/nfsrootfs/full.rootfs.tar
95 13:43:47.008956 total size: 120894716 (115 MB)
96 13:43:47.009166 Using unxz to decompress xz
97 13:43:47.046086 progress 0 % (0 MB)
98 13:43:47.847133 progress 5 % (5 MB)
99 13:43:48.693480 progress 10 % (11 MB)
100 13:43:49.486058 progress 15 % (17 MB)
101 13:43:50.232624 progress 20 % (23 MB)
102 13:43:50.832357 progress 25 % (28 MB)
103 13:43:51.659252 progress 30 % (34 MB)
104 13:43:52.468329 progress 35 % (40 MB)
105 13:43:52.837443 progress 40 % (46 MB)
106 13:43:53.232234 progress 45 % (51 MB)
107 13:43:54.002088 progress 50 % (57 MB)
108 13:43:54.891016 progress 55 % (63 MB)
109 13:43:55.680370 progress 60 % (69 MB)
110 13:43:56.471337 progress 65 % (74 MB)
111 13:43:57.262125 progress 70 % (80 MB)
112 13:43:58.097116 progress 75 % (86 MB)
113 13:43:58.885945 progress 80 % (92 MB)
114 13:43:59.662048 progress 85 % (98 MB)
115 13:44:00.528855 progress 90 % (103 MB)
116 13:44:01.319389 progress 95 % (109 MB)
117 13:44:02.287611 progress 100 % (115 MB)
118 13:44:02.303924 115 MB downloaded in 15.29 s (7.54 MB/s)
119 13:44:02.305192 end: 1.4.1 http-download (duration 00:00:15) [common]
121 13:44:02.307275 end: 1.4 download-retry (duration 00:00:15) [common]
122 13:44:02.308021 start: 1.5 download-retry (timeout 00:09:44) [common]
123 13:44:02.308713 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 13:44:02.309990 downloading http://storage.kernelci.org/broonie-sound/for-next/v6.12-rc2-163-g376efb6ef727/arm64/defconfig/gcc-12/modules.tar.xz
125 13:44:02.310610 saving as /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/modules/modules.tar
126 13:44:02.311163 total size: 11619300 (11 MB)
127 13:44:02.311725 Using unxz to decompress xz
128 13:44:02.355285 progress 0 % (0 MB)
129 13:44:02.418298 progress 5 % (0 MB)
130 13:44:02.497944 progress 10 % (1 MB)
131 13:44:02.589386 progress 15 % (1 MB)
132 13:44:02.691198 progress 20 % (2 MB)
133 13:44:02.774197 progress 25 % (2 MB)
134 13:44:02.851948 progress 30 % (3 MB)
135 13:44:02.934631 progress 35 % (3 MB)
136 13:44:03.010557 progress 40 % (4 MB)
137 13:44:03.087950 progress 45 % (5 MB)
138 13:44:03.170536 progress 50 % (5 MB)
139 13:44:03.259072 progress 55 % (6 MB)
140 13:44:03.342633 progress 60 % (6 MB)
141 13:44:03.417913 progress 65 % (7 MB)
142 13:44:03.497838 progress 70 % (7 MB)
143 13:44:03.571234 progress 75 % (8 MB)
144 13:44:03.648378 progress 80 % (8 MB)
145 13:44:03.732490 progress 85 % (9 MB)
146 13:44:03.816422 progress 90 % (10 MB)
147 13:44:03.892004 progress 95 % (10 MB)
148 13:44:03.971464 progress 100 % (11 MB)
149 13:44:03.985443 11 MB downloaded in 1.67 s (6.62 MB/s)
150 13:44:03.986068 end: 1.5.1 http-download (duration 00:00:02) [common]
152 13:44:03.986898 end: 1.5 download-retry (duration 00:00:02) [common]
153 13:44:03.987167 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 13:44:03.987434 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 13:44:20.674807 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/881554/extract-nfsrootfs-lvrh3p1b
156 13:44:20.675405 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 13:44:20.675691 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 13:44:20.676317 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b
159 13:44:20.676742 makedir: /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin
160 13:44:20.677063 makedir: /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/tests
161 13:44:20.677374 makedir: /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/results
162 13:44:20.677700 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-add-keys
163 13:44:20.678218 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-add-sources
164 13:44:20.678706 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-background-process-start
165 13:44:20.679193 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-background-process-stop
166 13:44:20.679703 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-common-functions
167 13:44:20.680244 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-echo-ipv4
168 13:44:20.680760 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-install-packages
169 13:44:20.681251 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-installed-packages
170 13:44:20.681795 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-os-build
171 13:44:20.682268 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-probe-channel
172 13:44:20.682734 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-probe-ip
173 13:44:20.683195 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-target-ip
174 13:44:20.683652 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-target-mac
175 13:44:20.684137 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-target-storage
176 13:44:20.684647 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-test-case
177 13:44:20.685136 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-test-event
178 13:44:20.685594 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-test-feedback
179 13:44:20.686051 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-test-raise
180 13:44:20.686504 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-test-reference
181 13:44:20.686958 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-test-runner
182 13:44:20.687421 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-test-set
183 13:44:20.687878 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-test-shell
184 13:44:20.688433 Updating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-add-keys (debian)
185 13:44:20.688979 Updating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-add-sources (debian)
186 13:44:20.689472 Updating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-install-packages (debian)
187 13:44:20.689956 Updating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-installed-packages (debian)
188 13:44:20.690434 Updating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/bin/lava-os-build (debian)
189 13:44:20.690852 Creating /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/environment
190 13:44:20.691208 LAVA metadata
191 13:44:20.691464 - LAVA_JOB_ID=881554
192 13:44:20.691676 - LAVA_DISPATCHER_IP=192.168.6.2
193 13:44:20.692055 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 13:44:20.692992 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 13:44:20.693294 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 13:44:20.693501 skipped lava-vland-overlay
197 13:44:20.693738 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 13:44:20.693989 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 13:44:20.694204 skipped lava-multinode-overlay
200 13:44:20.694443 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 13:44:20.694693 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 13:44:20.694934 Loading test definitions
203 13:44:20.695205 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 13:44:20.695422 Using /lava-881554 at stage 0
205 13:44:20.696504 uuid=881554_1.6.2.4.1 testdef=None
206 13:44:20.696798 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 13:44:20.697060 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 13:44:20.698593 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 13:44:20.699376 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 13:44:20.701290 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 13:44:20.702104 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 13:44:20.703873 runner path: /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/0/tests/0_timesync-off test_uuid 881554_1.6.2.4.1
215 13:44:20.704422 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 13:44:20.705226 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 13:44:20.705447 Using /lava-881554 at stage 0
219 13:44:20.705790 Fetching tests from https://github.com/kernelci/test-definitions.git
220 13:44:20.706075 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/0/tests/1_kselftest-alsa'
221 13:44:24.197361 Running '/usr/bin/git checkout kernelci.org
222 13:44:24.415816 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 13:44:24.417286 uuid=881554_1.6.2.4.5 testdef=None
224 13:44:24.417627 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 13:44:24.418371 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 13:44:24.421207 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 13:44:24.422027 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 13:44:24.425690 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 13:44:24.426539 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 13:44:24.430101 runner path: /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/0/tests/1_kselftest-alsa test_uuid 881554_1.6.2.4.5
234 13:44:24.430382 BOARD='meson-g12b-a311d-libretech-cc'
235 13:44:24.430590 BRANCH='broonie-sound'
236 13:44:24.430788 SKIPFILE='/dev/null'
237 13:44:24.430985 SKIP_INSTALL='True'
238 13:44:24.431180 TESTPROG_URL='http://storage.kernelci.org/broonie-sound/for-next/v6.12-rc2-163-g376efb6ef727/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 13:44:24.431380 TST_CASENAME=''
240 13:44:24.431573 TST_CMDFILES='alsa'
241 13:44:24.432123 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 13:44:24.432911 Creating lava-test-runner.conf files
244 13:44:24.433117 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/881554/lava-overlay-bzxq1c2b/lava-881554/0 for stage 0
245 13:44:24.433461 - 0_timesync-off
246 13:44:24.433694 - 1_kselftest-alsa
247 13:44:24.434031 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 13:44:24.434315 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 13:44:47.760317 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 13:44:47.760790 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 13:44:47.761101 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 13:44:47.761417 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 13:44:47.761722 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 13:44:48.388883 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 13:44:48.389374 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 13:44:48.389644 extracting modules file /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/881554/extract-nfsrootfs-lvrh3p1b
257 13:44:49.758798 extracting modules file /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/881554/extract-overlay-ramdisk-evhmndb1/ramdisk
258 13:44:51.176333 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 13:44:51.176802 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 13:44:51.177098 [common] Applying overlay to NFS
261 13:44:51.177331 [common] Applying overlay /var/lib/lava/dispatcher/tmp/881554/compress-overlay-albue65i/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/881554/extract-nfsrootfs-lvrh3p1b
262 13:44:54.111315 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 13:44:54.111771 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 13:44:54.112089 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 13:44:54.112352 Converting downloaded kernel to a uImage
266 13:44:54.112686 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/kernel/Image /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/kernel/uImage
267 13:44:54.580911 output: Image Name:
268 13:44:54.581344 output: Created: Tue Oct 22 13:44:54 2024
269 13:44:54.581556 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 13:44:54.581764 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 13:44:54.581969 output: Load Address: 01080000
272 13:44:54.582171 output: Entry Point: 01080000
273 13:44:54.582370 output:
274 13:44:54.582708 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 13:44:54.582976 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 13:44:54.583244 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 13:44:54.583498 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 13:44:54.583756 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 13:44:54.584046 Building ramdisk /var/lib/lava/dispatcher/tmp/881554/extract-overlay-ramdisk-evhmndb1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/881554/extract-overlay-ramdisk-evhmndb1/ramdisk
280 13:44:56.895631 >> 166782 blocks
281 13:45:04.584490 Adding RAMdisk u-boot header.
282 13:45:04.585164 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/881554/extract-overlay-ramdisk-evhmndb1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/881554/extract-overlay-ramdisk-evhmndb1/ramdisk.cpio.gz.uboot
283 13:45:04.828749 output: Image Name:
284 13:45:04.829182 output: Created: Tue Oct 22 13:45:04 2024
285 13:45:04.829396 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 13:45:04.829604 output: Data Size: 23422252 Bytes = 22873.29 KiB = 22.34 MiB
287 13:45:04.829810 output: Load Address: 00000000
288 13:45:04.830010 output: Entry Point: 00000000
289 13:45:04.830212 output:
290 13:45:04.830827 rename /var/lib/lava/dispatcher/tmp/881554/extract-overlay-ramdisk-evhmndb1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/ramdisk/ramdisk.cpio.gz.uboot
291 13:45:04.831271 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 13:45:04.831560 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 13:45:04.831862 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 13:45:04.832278 No LXC device requested
295 13:45:04.832843 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 13:45:04.833409 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 13:45:04.833956 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 13:45:04.834409 Checking files for TFTP limit of 4294967296 bytes.
299 13:45:04.837383 end: 1 tftp-deploy (duration 00:01:19) [common]
300 13:45:04.838026 start: 2 uboot-action (timeout 00:05:00) [common]
301 13:45:04.838603 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 13:45:04.839157 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 13:45:04.839717 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 13:45:04.840349 Using kernel file from prepare-kernel: 881554/tftp-deploy-7cc4wlfk/kernel/uImage
305 13:45:04.841053 substitutions:
306 13:45:04.841507 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 13:45:04.841954 - {DTB_ADDR}: 0x01070000
308 13:45:04.842399 - {DTB}: 881554/tftp-deploy-7cc4wlfk/dtb/meson-g12b-a311d-libretech-cc.dtb
309 13:45:04.842845 - {INITRD}: 881554/tftp-deploy-7cc4wlfk/ramdisk/ramdisk.cpio.gz.uboot
310 13:45:04.843286 - {KERNEL_ADDR}: 0x01080000
311 13:45:04.843724 - {KERNEL}: 881554/tftp-deploy-7cc4wlfk/kernel/uImage
312 13:45:04.844206 - {LAVA_MAC}: None
313 13:45:04.844690 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/881554/extract-nfsrootfs-lvrh3p1b
314 13:45:04.845134 - {NFS_SERVER_IP}: 192.168.6.2
315 13:45:04.845571 - {PRESEED_CONFIG}: None
316 13:45:04.846004 - {PRESEED_LOCAL}: None
317 13:45:04.846436 - {RAMDISK_ADDR}: 0x08000000
318 13:45:04.846872 - {RAMDISK}: 881554/tftp-deploy-7cc4wlfk/ramdisk/ramdisk.cpio.gz.uboot
319 13:45:04.847310 - {ROOT_PART}: None
320 13:45:04.847747 - {ROOT}: None
321 13:45:04.848215 - {SERVER_IP}: 192.168.6.2
322 13:45:04.848653 - {TEE_ADDR}: 0x83000000
323 13:45:04.849082 - {TEE}: None
324 13:45:04.849514 Parsed boot commands:
325 13:45:04.849932 - setenv autoload no
326 13:45:04.850360 - setenv initrd_high 0xffffffff
327 13:45:04.850790 - setenv fdt_high 0xffffffff
328 13:45:04.851224 - dhcp
329 13:45:04.851648 - setenv serverip 192.168.6.2
330 13:45:04.852117 - tftpboot 0x01080000 881554/tftp-deploy-7cc4wlfk/kernel/uImage
331 13:45:04.852558 - tftpboot 0x08000000 881554/tftp-deploy-7cc4wlfk/ramdisk/ramdisk.cpio.gz.uboot
332 13:45:04.852998 - tftpboot 0x01070000 881554/tftp-deploy-7cc4wlfk/dtb/meson-g12b-a311d-libretech-cc.dtb
333 13:45:04.853433 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/881554/extract-nfsrootfs-lvrh3p1b,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 13:45:04.853879 - bootm 0x01080000 0x08000000 0x01070000
335 13:45:04.854439 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 13:45:04.856164 start: 2.3 connect-device (timeout 00:05:00) [common]
338 13:45:04.856670 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 13:45:04.873035 Setting prompt string to ['lava-test: # ']
340 13:45:04.874840 end: 2.3 connect-device (duration 00:00:00) [common]
341 13:45:04.875560 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 13:45:04.876304 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 13:45:04.876935 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 13:45:04.878276 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 13:45:04.918473 >> OK - accepted request
346 13:45:04.920848 Returned 0 in 0 seconds
347 13:45:05.022078 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 13:45:05.023858 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 13:45:05.024548 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 13:45:05.025118 Setting prompt string to ['Hit any key to stop autoboot']
352 13:45:05.025611 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 13:45:05.027370 Trying 192.168.56.21...
354 13:45:05.027927 Connected to conserv1.
355 13:45:05.028428 Escape character is '^]'.
356 13:45:05.028879
357 13:45:05.029338 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 13:45:05.029806
359 13:45:15.817943 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 13:45:15.818603 bl2_stage_init 0x01
361 13:45:15.819069 bl2_stage_init 0x81
362 13:45:15.823467 hw id: 0x0000 - pwm id 0x01
363 13:45:15.824018 bl2_stage_init 0xc1
364 13:45:15.824481 bl2_stage_init 0x02
365 13:45:15.824916
366 13:45:15.828973 L0:00000000
367 13:45:15.829500 L1:20000703
368 13:45:15.829959 L2:00008067
369 13:45:15.830411 L3:14000000
370 13:45:15.831962 B2:00402000
371 13:45:15.832488 B1:e0f83180
372 13:45:15.832945
373 13:45:15.833379 TE: 58124
374 13:45:15.833809
375 13:45:15.843226 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 13:45:15.843725
377 13:45:15.844203 Board ID = 1
378 13:45:15.844632 Set A53 clk to 24M
379 13:45:15.845058 Set A73 clk to 24M
380 13:45:15.848658 Set clk81 to 24M
381 13:45:15.849145 A53 clk: 1200 MHz
382 13:45:15.849581 A73 clk: 1200 MHz
383 13:45:15.854327 CLK81: 166.6M
384 13:45:15.854808 smccc: 00012a92
385 13:45:15.860004 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 13:45:15.860490 board id: 1
387 13:45:15.868510 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 13:45:15.879182 fw parse done
389 13:45:15.885110 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 13:45:15.927711 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 13:45:15.938574 PIEI prepare done
392 13:45:15.939060 fastboot data load
393 13:45:15.939497 fastboot data verify
394 13:45:15.944315 verify result: 266
395 13:45:15.949893 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 13:45:15.950397 LPDDR4 probe
397 13:45:15.950839 ddr clk to 1584MHz
398 13:45:15.957885 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 13:45:15.995137
400 13:45:15.995730 dmc_version 0001
401 13:45:16.001796 Check phy result
402 13:45:16.007657 INFO : End of CA training
403 13:45:16.008238 INFO : End of initialization
404 13:45:16.013275 INFO : Training has run successfully!
405 13:45:16.013832 Check phy result
406 13:45:16.018857 INFO : End of initialization
407 13:45:16.019379 INFO : End of read enable training
408 13:45:16.024459 INFO : End of fine write leveling
409 13:45:16.030071 INFO : End of Write leveling coarse delay
410 13:45:16.030547 INFO : Training has run successfully!
411 13:45:16.030988 Check phy result
412 13:45:16.035644 INFO : End of initialization
413 13:45:16.036162 INFO : End of read dq deskew training
414 13:45:16.041188 INFO : End of MPR read delay center optimization
415 13:45:16.046854 INFO : End of write delay center optimization
416 13:45:16.052443 INFO : End of read delay center optimization
417 13:45:16.052918 INFO : End of max read latency training
418 13:45:16.058017 INFO : Training has run successfully!
419 13:45:16.058482 1D training succeed
420 13:45:16.067261 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 13:45:16.114982 Check phy result
422 13:45:16.115591 INFO : End of initialization
423 13:45:16.136777 INFO : End of 2D read delay Voltage center optimization
424 13:45:16.156921 INFO : End of 2D read delay Voltage center optimization
425 13:45:16.208997 INFO : End of 2D write delay Voltage center optimization
426 13:45:16.258414 INFO : End of 2D write delay Voltage center optimization
427 13:45:16.264089 INFO : Training has run successfully!
428 13:45:16.264675
429 13:45:16.265196 channel==0
430 13:45:16.269602 RxClkDly_Margin_A0==88 ps 9
431 13:45:16.270177 TxDqDly_Margin_A0==98 ps 10
432 13:45:16.273048 RxClkDly_Margin_A1==88 ps 9
433 13:45:16.273616 TxDqDly_Margin_A1==98 ps 10
434 13:45:16.278556 TrainedVREFDQ_A0==74
435 13:45:16.279121 TrainedVREFDQ_A1==74
436 13:45:16.284090 VrefDac_Margin_A0==25
437 13:45:16.284669 DeviceVref_Margin_A0==40
438 13:45:16.285179 VrefDac_Margin_A1==26
439 13:45:16.289788 DeviceVref_Margin_A1==40
440 13:45:16.290350
441 13:45:16.290870
442 13:45:16.291319 channel==1
443 13:45:16.291813 RxClkDly_Margin_A0==98 ps 10
444 13:45:16.293430 TxDqDly_Margin_A0==88 ps 9
445 13:45:16.299230 RxClkDly_Margin_A1==98 ps 10
446 13:45:16.299802 TxDqDly_Margin_A1==88 ps 9
447 13:45:16.300349 TrainedVREFDQ_A0==77
448 13:45:16.304609 TrainedVREFDQ_A1==77
449 13:45:16.305112 VrefDac_Margin_A0==22
450 13:45:16.310309 DeviceVref_Margin_A0==37
451 13:45:16.310803 VrefDac_Margin_A1==22
452 13:45:16.311241 DeviceVref_Margin_A1==37
453 13:45:16.311674
454 13:45:16.315804 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 13:45:16.316403
456 13:45:16.349323 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 13:45:16.349965 2D training succeed
458 13:45:16.354904 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 13:45:16.360483 auto size-- 65535DDR cs0 size: 2048MB
460 13:45:16.361084 DDR cs1 size: 2048MB
461 13:45:16.366070 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 13:45:16.366640 cs0 DataBus test pass
463 13:45:16.367103 cs1 DataBus test pass
464 13:45:16.371676 cs0 AddrBus test pass
465 13:45:16.372312 cs1 AddrBus test pass
466 13:45:16.372836
467 13:45:16.377272 100bdlr_step_size ps== 420
468 13:45:16.377844 result report
469 13:45:16.378288 boot times 0Enable ddr reg access
470 13:45:16.386699 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 13:45:16.400296 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 13:45:16.973818 0.0;M3 CHK:0;cm4_sp_mode 0
473 13:45:16.974487 MVN_1=0x00000000
474 13:45:16.979334 MVN_2=0x00000000
475 13:45:16.985098 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 13:45:16.985639 OPS=0x10
477 13:45:16.986087 ring efuse init
478 13:45:16.986523 chipver efuse init
479 13:45:16.990704 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 13:45:16.996316 [0.018961 Inits done]
481 13:45:16.996824 secure task start!
482 13:45:16.997265 high task start!
483 13:45:17.000865 low task start!
484 13:45:17.001360 run into bl31
485 13:45:17.007564 NOTICE: BL31: v1.3(release):4fc40b1
486 13:45:17.015339 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 13:45:17.015861 NOTICE: BL31: G12A normal boot!
488 13:45:17.040720 NOTICE: BL31: BL33 decompress pass
489 13:45:17.046408 ERROR: Error initializing runtime service opteed_fast
490 13:45:18.279235
491 13:45:18.279906
492 13:45:18.287664 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 13:45:18.288223
494 13:45:18.288670 Model: Libre Computer AML-A311D-CC Alta
495 13:45:18.495484 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 13:45:18.519641 DRAM: 2 GiB (effective 3.8 GiB)
497 13:45:18.663177 Core: 408 devices, 31 uclasses, devicetree: separate
498 13:45:18.668337 WDT: Not starting watchdog@f0d0
499 13:45:18.700643 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 13:45:18.713029 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 13:45:18.718033 ** Bad device specification mmc 0 **
502 13:45:18.728828 Card did not respond to voltage select! : -110
503 13:45:18.736202 ** Bad device specification mmc 0 **
504 13:45:18.736720 Couldn't find partition mmc 0
505 13:45:18.744354 Card did not respond to voltage select! : -110
506 13:45:18.749853 ** Bad device specification mmc 0 **
507 13:45:18.750384 Couldn't find partition mmc 0
508 13:45:18.754956 Error: could not access storage.
509 13:45:20.018210 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 13:45:20.018675 bl2_stage_init 0x01
511 13:45:20.018916 bl2_stage_init 0x81
512 13:45:20.023601 hw id: 0x0000 - pwm id 0x01
513 13:45:20.024159 bl2_stage_init 0xc1
514 13:45:20.024438 bl2_stage_init 0x02
515 13:45:20.024667
516 13:45:20.029153 L0:00000000
517 13:45:20.029559 L1:20000703
518 13:45:20.029788 L2:00008067
519 13:45:20.030018 L3:14000000
520 13:45:20.034756 B2:00402000
521 13:45:20.035476 B1:e0f83180
522 13:45:20.035750
523 13:45:20.036000 TE: 58124
524 13:45:20.036740
525 13:45:20.040396 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 13:45:20.040784
527 13:45:20.041002 Board ID = 1
528 13:45:20.045948 Set A53 clk to 24M
529 13:45:20.046531 Set A73 clk to 24M
530 13:45:20.046992 Set clk81 to 24M
531 13:45:20.051763 A53 clk: 1200 MHz
532 13:45:20.052379 A73 clk: 1200 MHz
533 13:45:20.052841 CLK81: 166.6M
534 13:45:20.053287 smccc: 00012a92
535 13:45:20.057103 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 13:45:20.062768 board id: 1
537 13:45:20.068661 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 13:45:20.079284 fw parse done
539 13:45:20.085198 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 13:45:20.127858 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 13:45:20.138869 PIEI prepare done
542 13:45:20.139574 fastboot data load
543 13:45:20.140179 fastboot data verify
544 13:45:20.144441 verify result: 266
545 13:45:20.150323 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 13:45:20.150997 LPDDR4 probe
547 13:45:20.151498 ddr clk to 1584MHz
548 13:45:20.157988 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 13:45:20.196052
550 13:45:20.196750 dmc_version 0001
551 13:45:20.201988 Check phy result
552 13:45:20.207809 INFO : End of CA training
553 13:45:20.208620 INFO : End of initialization
554 13:45:20.213388 INFO : Training has run successfully!
555 13:45:20.213948 Check phy result
556 13:45:20.218943 INFO : End of initialization
557 13:45:20.219477 INFO : End of read enable training
558 13:45:20.222724 INFO : End of fine write leveling
559 13:45:20.227922 INFO : End of Write leveling coarse delay
560 13:45:20.233696 INFO : Training has run successfully!
561 13:45:20.234184 Check phy result
562 13:45:20.234630 INFO : End of initialization
563 13:45:20.239109 INFO : End of read dq deskew training
564 13:45:20.244859 INFO : End of MPR read delay center optimization
565 13:45:20.245399 INFO : End of write delay center optimization
566 13:45:20.250797 INFO : End of read delay center optimization
567 13:45:20.255778 INFO : End of max read latency training
568 13:45:20.256301 INFO : Training has run successfully!
569 13:45:20.261436 1D training succeed
570 13:45:20.267347 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 13:45:20.315158 Check phy result
572 13:45:20.315808 INFO : End of initialization
573 13:45:20.337171 INFO : End of 2D read delay Voltage center optimization
574 13:45:20.357020 INFO : End of 2D read delay Voltage center optimization
575 13:45:20.409052 INFO : End of 2D write delay Voltage center optimization
576 13:45:20.458384 INFO : End of 2D write delay Voltage center optimization
577 13:45:20.464177 INFO : Training has run successfully!
578 13:45:20.464757
579 13:45:20.465249 channel==0
580 13:45:20.469560 RxClkDly_Margin_A0==88 ps 9
581 13:45:20.470141 TxDqDly_Margin_A0==108 ps 11
582 13:45:20.475270 RxClkDly_Margin_A1==88 ps 9
583 13:45:20.475825 TxDqDly_Margin_A1==88 ps 9
584 13:45:20.476356 TrainedVREFDQ_A0==74
585 13:45:20.480682 TrainedVREFDQ_A1==74
586 13:45:20.482122 VrefDac_Margin_A0==25
587 13:45:20.482386 DeviceVref_Margin_A0==40
588 13:45:20.486313 VrefDac_Margin_A1==25
589 13:45:20.486671 DeviceVref_Margin_A1==40
590 13:45:20.486930
591 13:45:20.487196
592 13:45:20.492046 channel==1
593 13:45:20.492364 RxClkDly_Margin_A0==98 ps 10
594 13:45:20.492592 TxDqDly_Margin_A0==88 ps 9
595 13:45:20.497484 RxClkDly_Margin_A1==98 ps 10
596 13:45:20.498028 TxDqDly_Margin_A1==88 ps 9
597 13:45:20.503506 TrainedVREFDQ_A0==77
598 13:45:20.503886 TrainedVREFDQ_A1==77
599 13:45:20.505061 VrefDac_Margin_A0==22
600 13:45:20.508690 DeviceVref_Margin_A0==37
601 13:45:20.509699 VrefDac_Margin_A1==22
602 13:45:20.514377 DeviceVref_Margin_A1==37
603 13:45:20.514725
604 13:45:20.514978 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 13:45:20.516006
606 13:45:20.547877 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 13:45:20.548318 2D training succeed
608 13:45:20.553953 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 13:45:20.559155 auto size-- 65535DDR cs0 size: 2048MB
610 13:45:20.559526 DDR cs1 size: 2048MB
611 13:45:20.564982 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 13:45:20.565499 cs0 DataBus test pass
613 13:45:20.570287 cs1 DataBus test pass
614 13:45:20.570756 cs0 AddrBus test pass
615 13:45:20.571163 cs1 AddrBus test pass
616 13:45:20.571557
617 13:45:20.575927 100bdlr_step_size ps== 420
618 13:45:20.576429 result report
619 13:45:20.581496 boot times 0Enable ddr reg access
620 13:45:20.587257 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 13:45:20.600904 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 13:45:21.173411 0.0;M3 CHK:0;cm4_sp_mode 0
623 13:45:21.173815 MVN_1=0x00000000
624 13:45:21.178897 MVN_2=0x00000000
625 13:45:21.184824 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 13:45:21.185133 OPS=0x10
627 13:45:21.185399 ring efuse init
628 13:45:21.185645 chipver efuse init
629 13:45:21.190271 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 13:45:21.195902 [0.018961 Inits done]
631 13:45:21.196601 secure task start!
632 13:45:21.197021 high task start!
633 13:45:21.199515 low task start!
634 13:45:21.200053 run into bl31
635 13:45:21.207099 NOTICE: BL31: v1.3(release):4fc40b1
636 13:45:21.214939 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 13:45:21.215459 NOTICE: BL31: G12A normal boot!
638 13:45:21.240789 NOTICE: BL31: BL33 decompress pass
639 13:45:21.245146 ERROR: Error initializing runtime service opteed_fast
640 13:45:22.479097
641 13:45:22.479707
642 13:45:22.487655 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 13:45:22.488168
644 13:45:22.488594 Model: Libre Computer AML-A311D-CC Alta
645 13:45:22.696169 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 13:45:22.719368 DRAM: 2 GiB (effective 3.8 GiB)
647 13:45:22.862447 Core: 408 devices, 31 uclasses, devicetree: separate
648 13:45:22.868365 WDT: Not starting watchdog@f0d0
649 13:45:22.900487 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 13:45:22.912915 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 13:45:22.917987 ** Bad device specification mmc 0 **
652 13:45:22.928236 Card did not respond to voltage select! : -110
653 13:45:22.935977 ** Bad device specification mmc 0 **
654 13:45:22.936499 Couldn't find partition mmc 0
655 13:45:22.944248 Card did not respond to voltage select! : -110
656 13:45:22.949594 ** Bad device specification mmc 0 **
657 13:45:22.950051 Couldn't find partition mmc 0
658 13:45:22.954764 Error: could not access storage.
659 13:45:23.299331 Net: eth0: ethernet@ff3f0000
660 13:45:23.299951 starting USB...
661 13:45:23.549640 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 13:45:23.550268 Starting the controller
663 13:45:23.556059 USB XHCI 1.10
664 13:45:25.268390 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 13:45:25.269005 bl2_stage_init 0x01
666 13:45:25.269448 bl2_stage_init 0x81
667 13:45:25.273936 hw id: 0x0000 - pwm id 0x01
668 13:45:25.274392 bl2_stage_init 0xc1
669 13:45:25.274806 bl2_stage_init 0x02
670 13:45:25.275271
671 13:45:25.279508 L0:00000000
672 13:45:25.279967 L1:20000703
673 13:45:25.280419 L2:00008067
674 13:45:25.280825 L3:14000000
675 13:45:25.282490 B2:00402000
676 13:45:25.282931 B1:e0f83180
677 13:45:25.283342
678 13:45:25.283756 TE: 58159
679 13:45:25.284213
680 13:45:25.293591 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 13:45:25.294050
682 13:45:25.294473 Board ID = 1
683 13:45:25.294885 Set A53 clk to 24M
684 13:45:25.295284 Set A73 clk to 24M
685 13:45:25.299333 Set clk81 to 24M
686 13:45:25.299792 A53 clk: 1200 MHz
687 13:45:25.300263 A73 clk: 1200 MHz
688 13:45:25.304772 CLK81: 166.6M
689 13:45:25.305222 smccc: 00012ab5
690 13:45:25.310449 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 13:45:25.310899 board id: 1
692 13:45:25.318909 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 13:45:25.329750 fw parse done
694 13:45:25.335539 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 13:45:25.378231 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 13:45:25.389084 PIEI prepare done
697 13:45:25.389669 fastboot data load
698 13:45:25.390167 fastboot data verify
699 13:45:25.394729 verify result: 266
700 13:45:25.400346 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 13:45:25.400858 LPDDR4 probe
702 13:45:25.401386 ddr clk to 1584MHz
703 13:45:25.408424 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 13:45:25.445731
705 13:45:25.446317 dmc_version 0001
706 13:45:25.454439 Check phy result
707 13:45:25.458561 INFO : End of CA training
708 13:45:25.459128 INFO : End of initialization
709 13:45:25.464043 INFO : Training has run successfully!
710 13:45:25.464600 Check phy result
711 13:45:25.469408 INFO : End of initialization
712 13:45:25.469954 INFO : End of read enable training
713 13:45:25.472694 INFO : End of fine write leveling
714 13:45:25.478213 INFO : End of Write leveling coarse delay
715 13:45:25.485930 INFO : Training has run successfully!
716 13:45:25.486530 Check phy result
717 13:45:25.487002 INFO : End of initialization
718 13:45:25.489958 INFO : End of read dq deskew training
719 13:45:25.495263 INFO : End of MPR read delay center optimization
720 13:45:25.495825 INFO : End of write delay center optimization
721 13:45:25.500606 INFO : End of read delay center optimization
722 13:45:25.506252 INFO : End of max read latency training
723 13:45:25.506806 INFO : Training has run successfully!
724 13:45:25.511838 1D training succeed
725 13:45:25.517799 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 13:45:25.567448 Check phy result
727 13:45:25.568121 INFO : End of initialization
728 13:45:25.586999 INFO : End of 2D read delay Voltage center optimization
729 13:45:25.607363 INFO : End of 2D read delay Voltage center optimization
730 13:45:25.659097 INFO : End of 2D write delay Voltage center optimization
731 13:45:25.708306 INFO : End of 2D write delay Voltage center optimization
732 13:45:25.713875 INFO : Training has run successfully!
733 13:45:25.714423
734 13:45:25.714893 channel==0
735 13:45:25.721136 RxClkDly_Margin_A0==88 ps 9
736 13:45:25.721735 TxDqDly_Margin_A0==98 ps 10
737 13:45:25.724393 RxClkDly_Margin_A1==88 ps 9
738 13:45:25.725074 TxDqDly_Margin_A1==98 ps 10
739 13:45:25.728532 TrainedVREFDQ_A0==74
740 13:45:25.729135 TrainedVREFDQ_A1==74
741 13:45:25.733780 VrefDac_Margin_A0==25
742 13:45:25.734354 DeviceVref_Margin_A0==40
743 13:45:25.734835 VrefDac_Margin_A1==25
744 13:45:25.739366 DeviceVref_Margin_A1==40
745 13:45:25.739935
746 13:45:25.740480
747 13:45:25.740956 channel==1
748 13:45:25.741419 RxClkDly_Margin_A0==98 ps 10
749 13:45:25.744991 TxDqDly_Margin_A0==98 ps 10
750 13:45:25.745562 RxClkDly_Margin_A1==98 ps 10
751 13:45:25.752065 TxDqDly_Margin_A1==98 ps 10
752 13:45:25.752642 TrainedVREFDQ_A0==77
753 13:45:25.753233 TrainedVREFDQ_A1==78
754 13:45:25.756447 VrefDac_Margin_A0==22
755 13:45:25.757028 DeviceVref_Margin_A0==37
756 13:45:25.761775 VrefDac_Margin_A1==22
757 13:45:25.762334 DeviceVref_Margin_A1==36
758 13:45:25.762779
759 13:45:25.767359 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 13:45:25.767918
761 13:45:25.795360 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 13:45:25.800982 2D training succeed
763 13:45:25.808551 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 13:45:25.809108 auto size-- 65535DDR cs0 size: 2048MB
765 13:45:25.812494 DDR cs1 size: 2048MB
766 13:45:25.813111 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 13:45:25.817701 cs0 DataBus test pass
768 13:45:25.818286 cs1 DataBus test pass
769 13:45:25.818747 cs0 AddrBus test pass
770 13:45:25.823344 cs1 AddrBus test pass
771 13:45:25.823853
772 13:45:25.824344 100bdlr_step_size ps== 420
773 13:45:25.824797 result report
774 13:45:25.828962 boot times 0Enable ddr reg access
775 13:45:25.837814 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 13:45:25.850222 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 13:45:26.424298 0.0;M3 CHK:0;cm4_sp_mode 0
778 13:45:26.425016 MVN_1=0x00000000
779 13:45:26.427745 MVN_2=0x00000000
780 13:45:26.433517 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 13:45:26.434015 OPS=0x10
782 13:45:26.434445 ring efuse init
783 13:45:26.434849 chipver efuse init
784 13:45:26.439062 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 13:45:26.444674 [0.018961 Inits done]
786 13:45:26.445174 secure task start!
787 13:45:26.445590 high task start!
788 13:45:26.449190 low task start!
789 13:45:26.449692 run into bl31
790 13:45:26.455886 NOTICE: BL31: v1.3(release):4fc40b1
791 13:45:26.464208 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 13:45:26.464865 NOTICE: BL31: G12A normal boot!
793 13:45:26.489053 NOTICE: BL31: BL33 decompress pass
794 13:45:26.494686 ERROR: Error initializing runtime service opteed_fast
795 13:45:27.727805
796 13:45:27.728456
797 13:45:27.735925 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 13:45:27.736568
799 13:45:27.737032 Model: Libre Computer AML-A311D-CC Alta
800 13:45:27.944377 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 13:45:27.967784 DRAM: 2 GiB (effective 3.8 GiB)
802 13:45:28.110821 Core: 408 devices, 31 uclasses, devicetree: separate
803 13:45:28.116559 WDT: Not starting watchdog@f0d0
804 13:45:28.148882 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 13:45:28.161307 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 13:45:28.166251 ** Bad device specification mmc 0 **
807 13:45:28.176692 Card did not respond to voltage select! : -110
808 13:45:28.184291 ** Bad device specification mmc 0 **
809 13:45:28.184811 Couldn't find partition mmc 0
810 13:45:28.192753 Card did not respond to voltage select! : -110
811 13:45:28.198093 ** Bad device specification mmc 0 **
812 13:45:28.198668 Couldn't find partition mmc 0
813 13:45:28.203183 Error: could not access storage.
814 13:45:28.545661 Net: eth0: ethernet@ff3f0000
815 13:45:28.546271 starting USB...
816 13:45:28.797655 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 13:45:28.798406 Starting the controller
818 13:45:28.803412 USB XHCI 1.10
819 13:45:30.968397 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 13:45:30.969056 bl2_stage_init 0x01
821 13:45:30.969560 bl2_stage_init 0x81
822 13:45:30.974067 hw id: 0x0000 - pwm id 0x01
823 13:45:30.974637 bl2_stage_init 0xc1
824 13:45:30.975167 bl2_stage_init 0x02
825 13:45:30.975645
826 13:45:30.979604 L0:00000000
827 13:45:30.980085 L1:20000703
828 13:45:30.980494 L2:00008067
829 13:45:30.981022 L3:14000000
830 13:45:30.985284 B2:00402000
831 13:45:30.985778 B1:e0f83180
832 13:45:30.986189
833 13:45:30.986592 TE: 58159
834 13:45:30.986998
835 13:45:30.990842 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 13:45:30.991425
837 13:45:30.992008 Board ID = 1
838 13:45:30.996477 Set A53 clk to 24M
839 13:45:30.996930 Set A73 clk to 24M
840 13:45:30.997332 Set clk81 to 24M
841 13:45:31.002098 A53 clk: 1200 MHz
842 13:45:31.002599 A73 clk: 1200 MHz
843 13:45:31.003072 CLK81: 166.6M
844 13:45:31.003475 smccc: 00012ab5
845 13:45:31.007603 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 13:45:31.013391 board id: 1
847 13:45:31.019227 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 13:45:31.029723 fw parse done
849 13:45:31.035957 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 13:45:31.078304 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 13:45:31.089288 PIEI prepare done
852 13:45:31.090036 fastboot data load
853 13:45:31.090530 fastboot data verify
854 13:45:31.094920 verify result: 266
855 13:45:31.100565 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 13:45:31.101242 LPDDR4 probe
857 13:45:31.101750 ddr clk to 1584MHz
858 13:45:31.108784 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 13:45:31.145626
860 13:45:31.146185 dmc_version 0001
861 13:45:31.152394 Check phy result
862 13:45:31.158217 INFO : End of CA training
863 13:45:31.158712 INFO : End of initialization
864 13:45:31.163893 INFO : Training has run successfully!
865 13:45:31.164330 Check phy result
866 13:45:31.169388 INFO : End of initialization
867 13:45:31.169760 INFO : End of read enable training
868 13:45:31.175003 INFO : End of fine write leveling
869 13:45:31.180534 INFO : End of Write leveling coarse delay
870 13:45:31.180988 INFO : Training has run successfully!
871 13:45:31.181349 Check phy result
872 13:45:31.186161 INFO : End of initialization
873 13:45:31.186571 INFO : End of read dq deskew training
874 13:45:31.191684 INFO : End of MPR read delay center optimization
875 13:45:31.197272 INFO : End of write delay center optimization
876 13:45:31.202911 INFO : End of read delay center optimization
877 13:45:31.203329 INFO : End of max read latency training
878 13:45:31.208458 INFO : Training has run successfully!
879 13:45:31.208860 1D training succeed
880 13:45:31.217698 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 13:45:31.265248 Check phy result
882 13:45:31.265735 INFO : End of initialization
883 13:45:31.286883 INFO : End of 2D read delay Voltage center optimization
884 13:45:31.306927 INFO : End of 2D read delay Voltage center optimization
885 13:45:31.358898 INFO : End of 2D write delay Voltage center optimization
886 13:45:31.408267 INFO : End of 2D write delay Voltage center optimization
887 13:45:31.413653 INFO : Training has run successfully!
888 13:45:31.414060
889 13:45:31.414387 channel==0
890 13:45:31.419668 RxClkDly_Margin_A0==88 ps 9
891 13:45:31.420125 TxDqDly_Margin_A0==98 ps 10
892 13:45:31.424856 RxClkDly_Margin_A1==88 ps 9
893 13:45:31.425255 TxDqDly_Margin_A1==88 ps 9
894 13:45:31.425641 TrainedVREFDQ_A0==74
895 13:45:31.430478 TrainedVREFDQ_A1==74
896 13:45:31.430900 VrefDac_Margin_A0==25
897 13:45:31.431242 DeviceVref_Margin_A0==40
898 13:45:31.436050 VrefDac_Margin_A1==25
899 13:45:31.436821 DeviceVref_Margin_A1==40
900 13:45:31.437487
901 13:45:31.438197
902 13:45:31.438866 channel==1
903 13:45:31.441873 RxClkDly_Margin_A0==98 ps 10
904 13:45:31.442726 TxDqDly_Margin_A0==98 ps 10
905 13:45:31.447464 RxClkDly_Margin_A1==98 ps 10
906 13:45:31.448475 TxDqDly_Margin_A1==88 ps 9
907 13:45:31.453170 TrainedVREFDQ_A0==77
908 13:45:31.454047 TrainedVREFDQ_A1==77
909 13:45:31.454824 VrefDac_Margin_A0==22
910 13:45:31.458705 DeviceVref_Margin_A0==37
911 13:45:31.459553 VrefDac_Margin_A1==22
912 13:45:31.464467 DeviceVref_Margin_A1==37
913 13:45:31.465400
914 13:45:31.466176 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 13:45:31.466943
916 13:45:31.497740 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
917 13:45:31.498312 2D training succeed
918 13:45:31.503357 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 13:45:31.509066 auto size-- 65535DDR cs0 size: 2048MB
920 13:45:31.509417 DDR cs1 size: 2048MB
921 13:45:31.514556 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 13:45:31.515068 cs0 DataBus test pass
923 13:45:31.520343 cs1 DataBus test pass
924 13:45:31.520687 cs0 AddrBus test pass
925 13:45:31.520943 cs1 AddrBus test pass
926 13:45:31.521173
927 13:45:31.525829 100bdlr_step_size ps== 420
928 13:45:31.526398 result report
929 13:45:31.531475 boot times 0Enable ddr reg access
930 13:45:31.536729 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 13:45:31.550166 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 13:45:32.122183 0.0;M3 CHK:0;cm4_sp_mode 0
933 13:45:32.122784 MVN_1=0x00000000
934 13:45:32.127723 MVN_2=0x00000000
935 13:45:32.133413 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 13:45:32.133886 OPS=0x10
937 13:45:32.134291 ring efuse init
938 13:45:32.134684 chipver efuse init
939 13:45:32.139002 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 13:45:32.144645 [0.018961 Inits done]
941 13:45:32.145127 secure task start!
942 13:45:32.145526 high task start!
943 13:45:32.149233 low task start!
944 13:45:32.149768 run into bl31
945 13:45:32.155846 NOTICE: BL31: v1.3(release):4fc40b1
946 13:45:32.163803 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 13:45:32.164511 NOTICE: BL31: G12A normal boot!
948 13:45:32.189038 NOTICE: BL31: BL33 decompress pass
949 13:45:32.194671 ERROR: Error initializing runtime service opteed_fast
950 13:45:33.427665
951 13:45:33.428346
952 13:45:33.435929 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 13:45:33.436519
954 13:45:33.436971 Model: Libre Computer AML-A311D-CC Alta
955 13:45:33.644291 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 13:45:33.666884 DRAM: 2 GiB (effective 3.8 GiB)
957 13:45:33.810662 Core: 408 devices, 31 uclasses, devicetree: separate
958 13:45:33.815755 WDT: Not starting watchdog@f0d0
959 13:45:33.848784 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 13:45:33.861315 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 13:45:33.866270 ** Bad device specification mmc 0 **
962 13:45:33.876641 Card did not respond to voltage select! : -110
963 13:45:33.883325 ** Bad device specification mmc 0 **
964 13:45:33.883865 Couldn't find partition mmc 0
965 13:45:33.892631 Card did not respond to voltage select! : -110
966 13:45:33.898090 ** Bad device specification mmc 0 **
967 13:45:33.898626 Couldn't find partition mmc 0
968 13:45:33.902301 Error: could not access storage.
969 13:45:34.245726 Net: eth0: ethernet@ff3f0000
970 13:45:34.246313 starting USB...
971 13:45:34.497420 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 13:45:34.498055 Starting the controller
973 13:45:34.504584 USB XHCI 1.10
974 13:45:36.058575 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 13:45:36.066043 scanning usb for storage devices... 0 Storage Device(s) found
977 13:45:36.117644 Hit any key to stop autoboot: 1
978 13:45:36.118760 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
979 13:45:36.119441 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
980 13:45:36.119976 Setting prompt string to ['=>']
981 13:45:36.120594 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
982 13:45:36.123595 0
983 13:45:36.124554 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 13:45:36.125100 Sending with 10 millisecond of delay
986 13:45:37.261888 => setenv autoload no
987 13:45:37.272788 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:28)
988 13:45:37.278360 setenv autoload no
989 13:45:37.279207 Sending with 10 millisecond of delay
991 13:45:39.076211 => setenv initrd_high 0xffffffff
992 13:45:39.087020 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
993 13:45:39.087950 setenv initrd_high 0xffffffff
994 13:45:39.088767 Sending with 10 millisecond of delay
996 13:45:40.705271 => setenv fdt_high 0xffffffff
997 13:45:40.716098 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
998 13:45:40.717084 setenv fdt_high 0xffffffff
999 13:45:40.717873 Sending with 10 millisecond of delay
1001 13:45:41.009966 => dhcp
1002 13:45:41.020770 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
1003 13:45:41.021655 dhcp
1004 13:45:41.022128 Speed: 1000, full duplex
1005 13:45:41.022581 BOOTP broadcast 1
1006 13:45:41.028874 DHCP client bound to address 192.168.6.27 (8 ms)
1007 13:45:41.029648 Sending with 10 millisecond of delay
1009 13:45:42.706197 => setenv serverip 192.168.6.2
1010 13:45:42.717022 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1011 13:45:42.717971 setenv serverip 192.168.6.2
1012 13:45:42.718715 Sending with 10 millisecond of delay
1014 13:45:46.442616 => tftpboot 0x01080000 881554/tftp-deploy-7cc4wlfk/kernel/uImage
1015 13:45:46.453412 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1016 13:45:46.454240 tftpboot 0x01080000 881554/tftp-deploy-7cc4wlfk/kernel/uImage
1017 13:45:46.454685 Speed: 1000, full duplex
1018 13:45:46.455102 Using ethernet@ff3f0000 device
1019 13:45:46.457887 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1020 13:45:46.463613 Filename '881554/tftp-deploy-7cc4wlfk/kernel/uImage'.
1021 13:45:46.467450 Load address: 0x1080000
1022 13:45:49.334777 Loading: *################################################## 43.6 MiB
1023 13:45:49.335393 15.2 MiB/s
1024 13:45:49.335825 done
1025 13:45:49.339140 Bytes transferred = 45713984 (2b98a40 hex)
1026 13:45:49.340338 Sending with 10 millisecond of delay
1028 13:45:54.025763 => tftpboot 0x08000000 881554/tftp-deploy-7cc4wlfk/ramdisk/ramdisk.cpio.gz.uboot
1029 13:45:54.036565 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1030 13:45:54.037384 tftpboot 0x08000000 881554/tftp-deploy-7cc4wlfk/ramdisk/ramdisk.cpio.gz.uboot
1031 13:45:54.037828 Speed: 1000, full duplex
1032 13:45:54.038244 Using ethernet@ff3f0000 device
1033 13:45:54.039458 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1034 13:45:54.048022 Filename '881554/tftp-deploy-7cc4wlfk/ramdisk/ramdisk.cpio.gz.uboot'.
1035 13:45:54.048516 Load address: 0x8000000
1036 13:46:01.014873 Loading: *##################T ################################ 22.3 MiB
1037 13:46:01.015498 3.2 MiB/s
1038 13:46:01.015929 done
1039 13:46:01.019365 Bytes transferred = 23422316 (165656c hex)
1040 13:46:01.020123 Sending with 10 millisecond of delay
1042 13:46:06.187411 => tftpboot 0x01070000 881554/tftp-deploy-7cc4wlfk/dtb/meson-g12b-a311d-libretech-cc.dtb
1043 13:46:06.198231 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
1044 13:46:06.199060 tftpboot 0x01070000 881554/tftp-deploy-7cc4wlfk/dtb/meson-g12b-a311d-libretech-cc.dtb
1045 13:46:06.199527 Speed: 1000, full duplex
1046 13:46:06.199944 Using ethernet@ff3f0000 device
1047 13:46:06.203392 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1048 13:46:06.215884 Filename '881554/tftp-deploy-7cc4wlfk/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1049 13:46:06.216482 Load address: 0x1070000
1050 13:46:06.236398 Loading: *################################################## 53.4 KiB
1051 13:46:06.247671 1.9 MiB/s
1052 13:46:06.248162 done
1053 13:46:06.248582 Bytes transferred = 54703 (d5af hex)
1054 13:46:06.249264 Sending with 10 millisecond of delay
1056 13:46:19.543707 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/881554/extract-nfsrootfs-lvrh3p1b,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1057 13:46:19.554715 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:45)
1058 13:46:19.555605 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/881554/extract-nfsrootfs-lvrh3p1b,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1059 13:46:19.556362 Sending with 10 millisecond of delay
1061 13:46:21.894862 => bootm 0x01080000 0x08000000 0x01070000
1062 13:46:21.905676 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1063 13:46:21.906225 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:43)
1064 13:46:21.907237 bootm 0x01080000 0x08000000 0x01070000
1065 13:46:21.907686 ## Booting kernel from Legacy Image at 01080000 ...
1066 13:46:21.910528 Image Name:
1067 13:46:21.916010 Image Type: AArch64 Linux Kernel Image (uncompressed)
1068 13:46:21.916455 Data Size: 45713920 Bytes = 43.6 MiB
1069 13:46:21.921489 Load Address: 01080000
1070 13:46:21.921927 Entry Point: 01080000
1071 13:46:22.116763 Verifying Checksum ... OK
1072 13:46:22.117328 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1073 13:46:22.122207 Image Name:
1074 13:46:22.127745 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1075 13:46:22.128233 Data Size: 23422252 Bytes = 22.3 MiB
1076 13:46:22.133297 Load Address: 00000000
1077 13:46:22.133745 Entry Point: 00000000
1078 13:46:22.235519 Verifying Checksum ... OK
1079 13:46:22.236103 ## Flattened Device Tree blob at 01070000
1080 13:46:22.241063 Booting using the fdt blob at 0x1070000
1081 13:46:22.241548 Working FDT set to 1070000
1082 13:46:22.244479 Loading Kernel Image
1083 13:46:22.396048 Loading Ramdisk to 7e9a9000, end 7ffff52c ... OK
1084 13:46:22.404301 Loading Device Tree to 000000007e998000, end 000000007e9a85ae ... OK
1085 13:46:22.404757 Working FDT set to 7e998000
1086 13:46:22.405175
1087 13:46:22.406064 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1088 13:46:22.406654 start: 2.4.4 auto-login-action (timeout 00:03:42) [common]
1089 13:46:22.407128 Setting prompt string to ['Linux version [0-9]']
1090 13:46:22.407584 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1091 13:46:22.408082 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1092 13:46:22.409111 Starting kernel ...
1093 13:46:22.409560
1094 13:46:22.444610 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1095 13:46:22.445516 start: 2.4.4.1 login-action (timeout 00:03:42) [common]
1096 13:46:22.446045 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1097 13:46:22.446511 Setting prompt string to []
1098 13:46:22.446995 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1099 13:46:22.447453 Using line separator: #'\n'#
1100 13:46:22.447863 No login prompt set.
1101 13:46:22.448343 Parsing kernel messages
1102 13:46:22.448753 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1103 13:46:22.449533 [login-action] Waiting for messages, (timeout 00:03:42)
1104 13:46:22.449988 Waiting using forced prompt support (timeout 00:01:51)
1105 13:46:22.464707 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j351118-arm64-gcc-12-defconfig-6mjks) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Tue Oct 22 12:41:09 UTC 2024
1106 13:46:22.465207 [ 0.000000] KASLR disabled due to lack of seed
1107 13:46:22.470226 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1108 13:46:22.475730 [ 0.000000] efi: UEFI not found.
1109 13:46:22.481184 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1110 13:46:22.492187 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1111 13:46:22.497804 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1112 13:46:22.508837 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1113 13:46:22.519871 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1114 13:46:22.530932 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1115 13:46:22.536447 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1116 13:46:22.541967 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1117 13:46:22.547513 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1118 13:46:22.552983 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1119 13:46:22.558555 [ 0.000000] Zone ranges:
1120 13:46:22.563966 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1121 13:46:22.564431 [ 0.000000] DMA32 empty
1122 13:46:22.569486 [ 0.000000] Normal empty
1123 13:46:22.574981 [ 0.000000] Movable zone start for each node
1124 13:46:22.575411 [ 0.000000] Early memory node ranges
1125 13:46:22.580533 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1126 13:46:22.586149 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1127 13:46:22.597165 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1128 13:46:22.602249 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1129 13:46:22.626396 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1130 13:46:22.631956 [ 0.000000] psci: probing for conduit method from DT.
1131 13:46:22.632426 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1132 13:46:22.637464 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1133 13:46:22.642971 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1134 13:46:22.648501 [ 0.000000] psci: SMC Calling Convention v1.1
1135 13:46:22.654013 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1136 13:46:22.659529 [ 0.000000] Detected VIPT I-cache on CPU0
1137 13:46:22.665172 [ 0.000000] CPU features: detected: ARM erratum 845719
1138 13:46:22.670590 [ 0.000000] alternatives: applying boot alternatives
1139 13:46:22.687179 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/881554/extract-nfsrootfs-lvrh3p1b,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1140 13:46:22.698178 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1141 13:46:22.703715 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1142 13:46:22.709242 <6>[ 0.000000] Fallback order for Node 0: 0
1143 13:46:22.714726 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1144 13:46:22.720262 <6>[ 0.000000] Policy zone: DMA
1145 13:46:22.725785 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1146 13:46:22.731324 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1147 13:46:22.736823 <6>[ 0.000000] software IO TLB: area num 8.
1148 13:46:22.745845 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1149 13:46:22.792426 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1150 13:46:22.797946 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1151 13:46:22.803445 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1152 13:46:22.809000 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1153 13:46:22.814496 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1154 13:46:22.820041 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1155 13:46:22.825526 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1156 13:46:22.831072 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1157 13:46:22.842200 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1158 13:46:22.853221 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1159 13:46:22.858671 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1160 13:46:22.864217 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1161 13:46:22.864651 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1162 13:46:22.874057 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1163 13:46:22.886714 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1164 13:46:22.897719 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1165 13:46:22.903244 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1166 13:46:22.908777 <6>[ 0.008798] Console: colour dummy device 80x25
1167 13:46:22.919846 <6>[ 0.012941] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1168 13:46:22.925342 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1169 13:46:22.930869 <6>[ 0.028190] LSM: initializing lsm=capability
1170 13:46:22.936397 <6>[ 0.032727] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1171 13:46:22.941985 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1172 13:46:22.947430 <6>[ 0.052299] rcu: Hierarchical SRCU implementation.
1173 13:46:22.952944 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1174 13:46:22.964063 <6>[ 0.058876] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1175 13:46:22.972418 <6>[ 0.071554] EFI services will not be available.
1176 13:46:22.972852 <6>[ 0.075205] smp: Bringing up secondary CPUs ...
1177 13:46:22.988653 <6>[ 0.077129] Detected VIPT I-cache on CPU1
1178 13:46:22.994247 <6>[ 0.077251] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1179 13:46:22.999707 <6>[ 0.078583] CPU features: detected: Spectre-v2
1180 13:46:23.005224 <6>[ 0.078598] CPU features: detected: Spectre-v4
1181 13:46:23.010734 <6>[ 0.078603] CPU features: detected: Spectre-BHB
1182 13:46:23.016275 <6>[ 0.078608] CPU features: detected: ARM erratum 858921
1183 13:46:23.021748 <6>[ 0.078616] Detected VIPT I-cache on CPU2
1184 13:46:23.027245 <6>[ 0.078689] arch_timer: Enabling local workaround for ARM erratum 858921
1185 13:46:23.033222 <6>[ 0.078707] arch_timer: CPU2: Trapping CNTVCT access
1186 13:46:23.039207 <6>[ 0.078717] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1187 13:46:23.044092 <6>[ 0.083555] Detected VIPT I-cache on CPU3
1188 13:46:23.049604 <6>[ 0.083601] arch_timer: Enabling local workaround for ARM erratum 858921
1189 13:46:23.055234 <6>[ 0.083611] arch_timer: CPU3: Trapping CNTVCT access
1190 13:46:23.061018 <6>[ 0.083618] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1191 13:46:23.066346 <6>[ 0.087592] Detected VIPT I-cache on CPU4
1192 13:46:23.071669 <6>[ 0.087639] arch_timer: Enabling local workaround for ARM erratum 858921
1193 13:46:23.077549 <6>[ 0.087649] arch_timer: CPU4: Trapping CNTVCT access
1194 13:46:23.088260 <6>[ 0.087656] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1195 13:46:23.090233 <6>[ 0.095615] Detected VIPT I-cache on CPU5
1196 13:46:23.099427 <6>[ 0.095662] arch_timer: Enabling local workaround for ARM erratum 858921
1197 13:46:23.099860 <6>[ 0.095672] arch_timer: CPU5: Trapping CNTVCT access
1198 13:46:23.110624 <6>[ 0.095680] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1199 13:46:23.111155 <6>[ 0.095793] smp: Brought up 1 node, 6 CPUs
1200 13:46:23.115866 <6>[ 0.217026] SMP: Total of 6 processors activated.
1201 13:46:23.121272 <6>[ 0.221929] CPU: All CPU(s) started at EL2
1202 13:46:23.126724 <6>[ 0.226271] CPU features: detected: 32-bit EL0 Support
1203 13:46:23.132276 <6>[ 0.231588] CPU features: detected: 32-bit EL1 Support
1204 13:46:23.137880 <6>[ 0.236936] CPU features: detected: CRC32 instructions
1205 13:46:23.143557 <6>[ 0.242338] alternatives: applying system-wide alternatives
1206 13:46:23.161472 <6>[ 0.249524] Memory: 3557444K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187788K reserved, 262144K cma-reserved)
1207 13:46:23.162119 <6>[ 0.263868] devtmpfs: initialized
1208 13:46:23.172370 <6>[ 0.273048] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1209 13:46:23.177729 <6>[ 0.277405] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1210 13:46:23.183130 <6>[ 0.288202] 21392 pages in range for non-PLT usage
1211 13:46:23.188645 <6>[ 0.288212] 512912 pages in range for PLT usage
1212 13:46:23.195084 <6>[ 0.289757] pinctrl core: initialized pinctrl subsystem
1213 13:46:23.199800 <6>[ 0.301837] DMI not present or invalid.
1214 13:46:23.205280 <6>[ 0.306125] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1215 13:46:23.210786 <6>[ 0.310876] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1216 13:46:23.221837 <6>[ 0.317641] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1217 13:46:23.227265 <6>[ 0.325742] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1218 13:46:23.232789 <6>[ 0.333236] audit: initializing netlink subsys (disabled)
1219 13:46:23.243852 <5>[ 0.338965] audit: type=2000 audit(0.260:1): state=initialized audit_enabled=0 res=1
1220 13:46:23.249444 <6>[ 0.340383] thermal_sys: Registered thermal governor 'step_wise'
1221 13:46:23.254984 <6>[ 0.346742] thermal_sys: Registered thermal governor 'power_allocator'
1222 13:46:23.260497 <6>[ 0.353004] cpuidle: using governor menu
1223 13:46:23.266027 <6>[ 0.364041] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1224 13:46:23.271570 <6>[ 0.370918] ASID allocator initialised with 65536 entries
1225 13:46:23.279746 <6>[ 0.378405] Serial: AMBA PL011 UART driver
1226 13:46:23.287577 <6>[ 0.388982] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1227 13:46:23.302804 <6>[ 0.404438] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1228 13:46:23.313833 <6>[ 0.407095] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1229 13:46:23.319377 <6>[ 0.420251] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1230 13:46:23.324894 <6>[ 0.423480] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1231 13:46:23.335906 <6>[ 0.431901] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1232 13:46:23.341435 <6>[ 0.439523] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1233 13:46:23.352474 <6>[ 0.453105] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1234 13:46:23.357980 <6>[ 0.455345] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1235 13:46:23.363510 <6>[ 0.461826] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1236 13:46:23.369054 <6>[ 0.468805] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1237 13:46:23.380072 <6>[ 0.475273] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1238 13:46:23.385591 <6>[ 0.482257] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1239 13:46:23.391266 <6>[ 0.488727] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1240 13:46:23.396646 <6>[ 0.495712] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1241 13:46:23.402233 <6>[ 0.503736] ACPI: Interpreter disabled.
1242 13:46:23.407647 <6>[ 0.509212] iommu: Default domain type: Translated
1243 13:46:23.413278 <6>[ 0.511245] iommu: DMA domain TLB invalidation policy: strict mode
1244 13:46:23.418720 <5>[ 0.517964] SCSI subsystem initialized
1245 13:46:23.424261 <6>[ 0.521880] usbcore: registered new interface driver usbfs
1246 13:46:23.429750 <6>[ 0.527304] usbcore: registered new interface driver hub
1247 13:46:23.435269 <6>[ 0.532819] usbcore: registered new device driver usb
1248 13:46:23.440804 <6>[ 0.539085] pps_core: LinuxPPS API ver. 1 registered
1249 13:46:23.446306 <6>[ 0.543240] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1250 13:46:23.451833 <6>[ 0.552561] PTP clock support registered
1251 13:46:23.457343 <6>[ 0.556801] EDAC MC: Ver: 3.0.0
1252 13:46:23.462854 <6>[ 0.560452] scmi_core: SCMI protocol bus registered
1253 13:46:23.463283 <6>[ 0.566099] FPGA manager framework
1254 13:46:23.468394 <6>[ 0.568821] Advanced Linux Sound Architecture Driver Initialized.
1255 13:46:23.473930 <6>[ 0.575777] vgaarb: loaded
1256 13:46:23.479411 <6>[ 0.578324] clocksource: Switched to clocksource arch_sys_counter
1257 13:46:23.484926 <5>[ 0.584460] VFS: Disk quotas dquot_6.6.0
1258 13:46:23.490443 <6>[ 0.588454] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1259 13:46:23.496061 <6>[ 0.595664] pnp: PnP ACPI: disabled
1260 13:46:23.501532 <6>[ 0.604119] NET: Registered PF_INET protocol family
1261 13:46:23.507040 <6>[ 0.604488] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1262 13:46:23.518063 <6>[ 0.614641] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1263 13:46:23.523586 <6>[ 0.620657] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1264 13:46:23.534624 <6>[ 0.628551] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1265 13:46:23.540311 <6>[ 0.636789] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1266 13:46:23.545667 <6>[ 0.644589] TCP: Hash tables configured (established 32768 bind 32768)
1267 13:46:23.551290 <6>[ 0.651063] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1268 13:46:23.562290 <6>[ 0.657909] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1269 13:46:23.567756 <6>[ 0.665328] NET: Registered PF_UNIX/PF_LOCAL protocol family
1270 13:46:23.573292 <6>[ 0.671414] RPC: Registered named UNIX socket transport module.
1271 13:46:23.578800 <6>[ 0.677197] RPC: Registered udp transport module.
1272 13:46:23.584343 <6>[ 0.682102] RPC: Registered tcp transport module.
1273 13:46:23.589813 <6>[ 0.687017] RPC: Registered tcp-with-tls transport module.
1274 13:46:23.595351 <6>[ 0.692710] RPC: Registered tcp NFSv4.1 backchannel transport module.
1275 13:46:23.600878 <6>[ 0.699358] PCI: CLS 0 bytes, default 64
1276 13:46:23.601316 <6>[ 0.703679] Unpacking initramfs...
1277 13:46:23.606417 <6>[ 0.709855] kvm [1]: nv: 554 coarse grained trap handlers
1278 13:46:23.611940 <6>[ 0.713007] kvm [1]: IPA Size Limit: 40 bits
1279 13:46:23.617447 <6>[ 0.718678] kvm [1]: vgic interrupt IRQ9
1280 13:46:23.622954 <6>[ 0.721369] kvm [1]: Hyp nVHE mode initialized successfully
1281 13:46:23.628471 <5>[ 0.728444] Initialise system trusted keyrings
1282 13:46:23.634047 <6>[ 0.732031] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1283 13:46:23.639501 <6>[ 0.738675] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1284 13:46:23.645049 <5>[ 0.744759] NFS: Registering the id_resolver key type
1285 13:46:23.650548 <5>[ 0.749745] Key type id_resolver registered
1286 13:46:23.656144 <5>[ 0.754122] Key type id_legacy registered
1287 13:46:23.661595 <6>[ 0.758359] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1288 13:46:23.667120 <6>[ 0.765247] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1289 13:46:23.674525 <6>[ 0.773035] 9p: Installing v9fs 9p2000 file system support
1290 13:46:23.712568 <5>[ 0.819709] Key type asymmetric registered
1291 13:46:23.718096 <5>[ 0.819747] Asymmetric key parser 'x509' registered
1292 13:46:23.729121 <6>[ 0.823614] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1293 13:46:23.729562 <6>[ 0.831139] io scheduler mq-deadline registered
1294 13:46:23.734643 <6>[ 0.835871] io scheduler kyber registered
1295 13:46:23.740183 <6>[ 0.840144] io scheduler bfq registered
1296 13:46:23.746589 <6>[ 0.848058] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1297 13:46:23.763109 <6>[ 0.866467] ledtrig-cpu: registered to indicate activity on CPUs
1298 13:46:23.795666 <6>[ 0.897814] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1299 13:46:23.815571 <6>[ 0.911454] Serial: 8250/16550 driver, 4 ports<6>[ 0.916051] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1300 13:46:23.821088 <6>[ 0.925682] printk: legacy console [ttyAML0] enabled
1301 13:46:23.826606 <6>[ 0.925682] printk: legacy console [ttyAML0] enabled
1302 13:46:23.832193 <6>[ 0.930483] printk: legacy bootconsole [meson0] disabled
1303 13:46:23.837679 <6>[ 0.930483] printk: legacy bootconsole [meson0] disabled
1304 13:46:23.843343 <6>[ 0.943150] msm_serial: driver initialized
1305 13:46:23.848820 <6>[ 0.946473] SuperH (H)SCI(F) driver initialized
1306 13:46:23.849255 <6>[ 0.950984] STM32 USART driver initialized
1307 13:46:23.854383 <5>[ 0.957215] random: crng init done
1308 13:46:23.861379 <6>[ 0.962917] loop: module loaded
1309 13:46:23.861805 <6>[ 0.964180] megasas: 07.727.03.00-rc1
1310 13:46:23.866905 <6>[ 0.972990] tun: Universal TUN/TAP device driver, 1.6
1311 13:46:23.872475 <6>[ 0.974173] thunder_xcv, ver 1.0
1312 13:46:23.877988 <6>[ 0.976182] thunder_bgx, ver 1.0
1313 13:46:23.878416 <6>[ 0.979624] nicpf, ver 1.0
1314 13:46:23.883512 <6>[ 0.984228] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1315 13:46:23.889079 <6>[ 0.990015] hns3: Copyright (c) 2017 Huawei Corporation.
1316 13:46:23.894621 <6>[ 0.995602] hclge is initializing
1317 13:46:23.900176 <6>[ 0.999137] e1000: Intel(R) PRO/1000 Network Driver
1318 13:46:23.905715 <6>[ 1.004221] e1000: Copyright (c) 1999-2006 Intel Corporation.
1319 13:46:23.911348 <6>[ 1.010245] e1000e: Intel(R) PRO/1000 Network Driver
1320 13:46:23.916825 <6>[ 1.015401] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1321 13:46:23.922394 <6>[ 1.021581] igb: Intel(R) Gigabit Ethernet Network Driver
1322 13:46:23.927902 <6>[ 1.027186] igb: Copyright (c) 2007-2014 Intel Corporation.
1323 13:46:23.933458 <6>[ 1.033041] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1324 13:46:23.938994 <6>[ 1.039496] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1325 13:46:23.944543 <6>[ 1.046259] sky2: driver version 1.30
1326 13:46:23.950090 <6>[ 1.051365] VFIO - User Level meta-driver version: 0.3
1327 13:46:23.955620 <6>[ 1.058877] usbcore: registered new interface driver usb-storage
1328 13:46:23.961659 <6>[ 1.065144] i2c_dev: i2c /dev entries driver
1329 13:46:23.974500 <6>[ 1.076078] sdhci: Secure Digital Host Controller Interface driver
1330 13:46:23.974985 <6>[ 1.076881] sdhci: Copyright(c) Pierre Ossman
1331 13:46:23.985590 <6>[ 1.082566] Synopsys Designware Multimedia Card Interface Driver
1332 13:46:23.991154 <6>[ 1.089097] sdhci-pltfm: SDHCI platform and OF driver helper
1333 13:46:23.991588 <6>[ 1.096800] meson-sm: secure-monitor enabled
1334 13:46:24.004020 <6>[ 1.099370] usbcore: registered new interface driver usbhid
1335 13:46:24.004456 <6>[ 1.103941] usbhid: USB HID core driver
1336 13:46:24.011620 <6>[ 1.118742] NET: Registered PF_PACKET protocol family
1337 13:46:24.017161 <6>[ 1.118837] 9pnet: Installing 9P2000 support
1338 13:46:24.024353 <5>[ 1.123002] Key type dns_resolver registered
1339 13:46:24.031657 <6>[ 1.134560] registered taskstats version 1
1340 13:46:24.032111 <5>[ 1.134717] Loading compiled-in X.509 certificates
1341 13:46:24.038957 <6>[ 1.143414] Demotion targets for Node 0: null
1342 13:46:24.079502 <6>[ 1.186587] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1343 13:46:24.085008 <6>[ 1.186630] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1344 13:46:24.096136 <4>[ 1.196793] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1345 13:46:24.101654 <4>[ 1.199420] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1346 13:46:24.107205 <6>[ 1.206972] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1347 13:46:24.112750 <6>[ 1.216228] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1348 13:46:24.123812 <6>[ 1.219668] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1349 13:46:24.134924 <6>[ 1.227665] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1350 13:46:24.140488 <6>[ 1.237197] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1351 13:46:24.146024 <6>[ 1.243420] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1352 13:46:24.151569 <6>[ 1.249036] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1353 13:46:24.157117 <6>[ 1.256929] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1354 13:46:24.162672 <6>[ 1.264190] hub 1-0:1.0: USB hub found
1355 13:46:24.168214 <6>[ 1.267698] hub 1-0:1.0: 2 ports detected
1356 13:46:24.173751 <6>[ 1.273723] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1357 13:46:24.179363 <6>[ 1.280678] hub 2-0:1.0: USB hub found
1358 13:46:24.184443 <6>[ 1.284244] hub 2-0:1.0: 1 port detected
1359 13:46:24.204454 <6>[ 1.308910] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1360 13:46:24.215825 <6>[ 1.319448] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1361 13:46:24.249593 <6>[ 1.353028] Trying to probe devices needed for running init ...
1362 13:46:24.415621 <6>[ 1.518358] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1363 13:46:24.556083 <6>[ 1.657628] mmc0: new ultra high speed SDR104 SDXC card at address e624
1364 13:46:24.562598 <6>[ 1.659363] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1365 13:46:24.563089 <6>[ 1.669384] mmcblk0: p1
1366 13:46:24.572540 <6>[ 1.677780] Freeing initrd memory: 22872K
1367 13:46:24.604883 <6>[ 1.712010] hub 1-1:1.0: USB hub found
1368 13:46:24.610637 <6>[ 1.712311] hub 1-1:1.0: 4 ports detected
1369 13:46:24.671638 <6>[ 1.774465] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1370 13:46:24.717540 <6>[ 1.824657] hub 2-1:1.0: USB hub found
1371 13:46:24.723331 <6>[ 1.825477] hub 2-1:1.0: 4 ports detected
1372 13:46:36.544085 <6>[ 13.650713] clk: Disabling unused clocks
1373 13:46:36.549386 <6>[ 13.650948] PM: genpd: Disabling unused power domains
1374 13:46:36.557666 <6>[ 13.654632] ALSA device list:
1375 13:46:36.558149 <6>[ 13.657762] No soundcards found.
1376 13:46:36.564683 <6>[ 13.671669] Freeing unused kernel memory: 10432K
1377 13:46:36.571173 <6>[ 13.671797] Run /init as init process
1378 13:46:36.577731 Loading, please wait...
1379 13:46:36.617593 Starting systemd-udevd version 252.22-1~deb12u1
1380 13:46:37.070000 <6>[ 14.176716] meson-vrtc ff8000a8.rtc: registered as rtc0
1381 13:46:37.081126 <6>[ 14.176773] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1382 13:46:37.095543 <6>[ 14.196981] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1383 13:46:37.101033 <6>[ 14.198225] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1384 13:46:37.106568 <6>[ 14.205025] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1385 13:46:37.112300 <6>[ 14.211113] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1386 13:46:37.117678 <6>[ 14.221658] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1387 13:46:37.123312 <6>[ 14.224463] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1388 13:46:37.128840 <6>[ 14.227362] mc: Linux media interface: v0.10
1389 13:46:37.139903 <6>[ 14.229886] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1390 13:46:37.145408 <6>[ 14.242093] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1391 13:46:37.151027 <6>[ 14.249803] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1392 13:46:37.156559 <6>[ 14.255259] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1393 13:46:37.167672 <6>[ 14.262539] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1394 13:46:37.173388 <6>[ 14.274624] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1395 13:46:37.178799 <6>[ 14.275490] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1396 13:46:37.179202 <6>[ 14.277255] Registered IR keymap rc-empty
1397 13:46:37.184259 <6>[ 14.281567] panfrost ffe40000.gpu: clock rate = 24000000
1398 13:46:37.195248 <6>[ 14.285978] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1399 13:46:37.206443 <3>[ 14.291368] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1400 13:46:37.211956 <4>[ 14.299888] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1401 13:46:37.223007 <3>[ 14.320411] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1402 13:46:37.228530 <6>[ 14.321233] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1403 13:46:37.234186 <6>[ 14.326230] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1404 13:46:37.245218 <6>[ 14.332834] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1405 13:46:37.256267 <6>[ 14.332847] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1406 13:46:37.261827 <6>[ 14.361614] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1407 13:46:37.267341 <6>[ 14.363254] videodev: Linux video capture interface: v2.00
1408 13:46:37.272953 <6>[ 14.363771] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1409 13:46:37.284007 <6>[ 14.368034] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1410 13:46:37.289564 <6>[ 14.390406] rc rc0: sw decoder init
1411 13:46:37.293256 <6>[ 14.391948] meson-ir ff808000.ir: receiver initialized
1412 13:46:37.309497 <6>[ 14.411026] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1413 13:46:37.320582 <6>[ 14.419293] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1414 13:46:37.331677 <4>[ 14.428074] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1415 13:46:37.337244 <6>[ 14.437244] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1416 13:46:37.342785 <6>[ 14.443615] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1417 13:46:37.353828 <3>[ 14.444916] meson-drm ff900000.vpu: DSI transceiver device is disabled
1418 13:46:37.359451 <6>[ 14.457157] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1419 13:46:37.365517 <6>[ 14.463405] usbcore: registered new device driver onboard-usb-dev
1420 13:46:37.552527 <6>[ 14.492013] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1421 13:46:37.558090 <6>[ 14.635105] Console: switching to colour frame buffer device 128x48
1422 13:46:37.564925 <6>[ 14.661466] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1423 13:46:37.721245 <6>[ 14.819199] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1424 13:46:37.789073 <6>[ 14.896009] hub 1-1:1.0: USB hub found
1425 13:46:37.794368 <6>[ 14.896335] hub 1-1:1.0: 4 ports detected
1426 13:46:37.800984 <6>[ 14.901074] onboard-usb-dev 1-1: USB disconnect, device number 2
1427 13:46:37.932307 Begin: Loading essential drivers ... done.
1428 13:46:37.937740 Begin: Running /scripts/init-premount ... done.
1429 13:46:37.943395 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1430 13:46:37.956864 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1431 13:46:37.957190 Device /sys/class/net/end0 found
1432 13:46:37.957425 done.
1433 13:46:37.972526 Begin: Waiting up to 180 secs for any network device to become available ... done.
1434 13:46:38.018907 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.116718] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1435 13:46:38.019588
1436 13:46:38.087582 <6>[ 15.186442] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=30)
1437 13:46:38.100944 <6>[ 15.202477] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1438 13:46:38.106489 <6>[ 15.204669] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1439 13:46:38.115786 <6>[ 15.212035] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1440 13:46:38.175625 <6>[ 15.278364] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1441 13:46:38.365215 <6>[ 15.472095] hub 1-1:1.0: USB hub found
1442 13:46:38.370808 <6>[ 15.472422] hub 1-1:1.0: 4 ports detected
1443 13:46:38.561567 <6>[ 15.663974] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1444 13:46:38.818271 <6>[ 15.919973] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1445 13:46:39.204275 <4>[ 16.311289] rc rc0: two consecutive events of type space
1446 13:46:39.571643 IP-Config: no response after 2 secs - giving up
1447 13:46:39.635030 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1448 13:46:41.082329 <6>[ 18.183308] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1449 13:46:41.761078 IP-Config: end0 guessed broadcast address 192.168.6.255
1450 13:46:41.766611 IP-Config: end0 complete (dhcp from 192.168.6.1):
1451 13:46:41.772120 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1452 13:46:41.783253 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1453 13:46:41.783790 rootserver: 192.168.6.1 rootpath:
1454 13:46:41.786629 filename :
1455 13:46:41.864837 done.
1456 13:46:41.875839 Begin: Running /scripts/nfs-bottom ... done.
1457 13:46:41.889924 Begin: Running /scripts/init-bottom ... done.
1458 13:46:42.253331 <30>[ 19.355843] systemd[1]: System time before build time, advancing clock.
1459 13:46:42.313745 <6>[ 19.420706] NET: Registered PF_INET6 protocol family
1460 13:46:42.319229 <6>[ 19.421500] Segment Routing with IPv6
1461 13:46:42.324502 <6>[ 19.424239] In-situ OAM (IOAM) with IPv6
1462 13:46:42.405276 <30>[ 19.481212] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1463 13:46:42.410878 <30>[ 19.508591] systemd[1]: Detected architecture arm64.
1464 13:46:42.411175
1465 13:46:42.414745 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1466 13:46:42.415036
1467 13:46:42.424984 <30>[ 19.528139] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1468 13:46:43.115441 <30>[ 20.217528] systemd[1]: Queued start job for default target graphical.target.
1469 13:46:43.155173 <30>[ 20.256681] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1470 13:46:43.162760 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1471 13:46:43.173826 <30>[ 20.275319] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1472 13:46:43.182192 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1473 13:46:43.193790 <30>[ 20.295398] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1474 13:46:43.202852 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1475 13:46:43.213897 <30>[ 20.315065] systemd[1]: Created slice user.slice - User and Session Slice.
1476 13:46:43.220231 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1477 13:46:43.234158 <30>[ 20.330600] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1478 13:46:43.240195 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1479 13:46:43.251147 <30>[ 20.350526] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1480 13:46:43.263234 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1481 13:46:43.280040 <30>[ 20.370505] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1482 13:46:43.285438 <30>[ 20.384625] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1483 13:46:43.298668 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1484 13:46:43.304213 <30>[ 20.406423] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1485 13:46:43.313062 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1486 13:46:43.328886 <30>[ 20.430436] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1487 13:46:43.342619 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1488 13:46:43.348166 <30>[ 20.450468] systemd[1]: Reached target paths.target - Path Units.
1489 13:46:43.356587 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1490 13:46:43.362137 <30>[ 20.466438] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1491 13:46:43.373905 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1492 13:46:43.379423 <30>[ 20.482419] systemd[1]: Reached target slices.target - Slice Units.
1493 13:46:43.387566 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1494 13:46:43.393078 <30>[ 20.498437] systemd[1]: Reached target swap.target - Swaps.
1495 13:46:43.400984 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1496 13:46:43.412831 <30>[ 20.514452] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1497 13:46:43.421726 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1498 13:46:43.437024 <30>[ 20.538622] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1499 13:46:43.446247 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1500 13:46:43.458041 <30>[ 20.559678] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1501 13:46:43.466847 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1502 13:46:43.481736 <30>[ 20.583320] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1503 13:46:43.491062 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1504 13:46:43.505135 <30>[ 20.606760] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1505 13:46:43.511974 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1506 13:46:43.519635 <30>[ 20.623375] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1507 13:46:43.530863 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1508 13:46:43.542634 <30>[ 20.644276] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1509 13:46:43.548190 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1510 13:46:43.561025 <30>[ 20.662661] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1511 13:46:43.569484 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1512 13:46:43.609005 <30>[ 20.710544] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1513 13:46:43.615636 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1514 13:46:43.635191 <30>[ 20.736789] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1515 13:46:43.642696 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1516 13:46:43.701045 <30>[ 20.802560] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1517 13:46:43.707239 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1518 13:46:43.726646 <30>[ 20.818732] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1519 13:46:43.732172 <30>[ 20.831850] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1520 13:46:43.737734 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1521 13:46:43.759487 <30>[ 20.861120] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1522 13:46:43.767439 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1523 13:46:43.779059 <30>[ 20.880708] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1524 13:46:43.786673 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1525 13:46:43.799609 <30>[ 20.901281] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1526 13:46:43.810749 <6>[ 20.901970] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1527 13:46:43.815571 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1528 13:46:43.827636 <30>[ 20.929303] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1529 13:46:43.836097 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1530 13:46:43.847146 <30>[ 20.948477] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1531 13:46:43.854111 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1532 13:46:43.871790 <30>[ 20.973392] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1533 13:46:43.877332 <6>[ 20.976593] fuse: init (API version 7.41)
1534 13:46:43.881249 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1535 13:46:43.902408 <30>[ 21.004052] systemd[1]: Starting systemd-journald.service - Journal Service...
1536 13:46:43.908851 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1537 13:46:43.933063 <30>[ 21.034672] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1538 13:46:43.940577 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1539 13:46:43.959449 <30>[ 21.061060] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1540 13:46:43.968771 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1541 13:46:44.013660 <30>[ 21.115066] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1542 13:46:44.022255 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1543 13:46:44.041626 <30>[ 21.143168] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1544 13:46:44.049658 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1545 13:46:44.068866 <30>[ 21.170445] systemd[1]: Started systemd-journald.service - Journal Service.
1546 13:46:44.075661 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1547 13:46:44.092634 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1548 13:46:44.106006 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1549 13:46:44.122027 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1550 13:46:44.142611 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1551 13:46:44.159671 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1552 13:46:44.174398 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1553 13:46:44.185714 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1554 13:46:44.198068 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1555 13:46:44.218034 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1556 13:46:44.229863 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1557 13:46:44.241828 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1558 13:46:44.261969 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1559 13:46:44.281792 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1560 13:46:44.294221 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1561 13:46:44.336505 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1562 13:46:44.347468 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1563 13:46:44.362798 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1564 13:46:44.378512 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1565 13:46:44.401458 <46>[ 21.502960] systemd-journald[226]: Received client request to flush runtime journal.
1566 13:46:44.428776 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1567 13:46:44.496656 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1568 13:46:44.545032 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1569 13:46:44.557790 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1570 13:46:44.569875 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1571 13:46:44.590286 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1572 13:46:44.601807 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1573 13:46:44.638319 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1574 13:46:44.674160 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1575 13:46:44.705663 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1576 13:46:44.758303 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1577 13:46:44.773483 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1578 13:46:44.792535 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1579 13:46:44.844549 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1580 13:46:44.854795 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1581 13:46:45.094920 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1582 13:46:45.135669 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1583 13:46:45.142251 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1584 13:46:45.153452 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1585 13:46:45.243301 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1586 13:46:45.257873 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1587 13:46:45.304551 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1588 13:46:45.321248 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1589 13:46:45.328295 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1590 13:46:45.345529 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1591 13:46:45.363793 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1592 13:46:45.381329 <46>[ 22.472644] systemd-journald[226]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1593 13:46:45.395897 [<46>[ 22.485322] systemd-journald[226]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1594 13:46:45.403938 [0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1595 13:46:45.421084 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1596 13:46:45.428638 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1597 13:46:45.514986 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1598 13:46:45.529494 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1599 13:46:45.541267 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1600 13:46:45.547969 <5>[ 22.648200] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1601 13:46:45.584947 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1602 13:46:45.592055 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1603 13:46:45.604876 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1604 13:46:45.644836 <5>[ 22.746380] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1605 13:46:45.650354 <5>[ 22.747257] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1606 13:46:45.655859 <4>[ 22.754729] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1607 13:46:45.661496 <6>[ 22.762995] cfg80211: failed to load regulatory.db
1608 13:46:45.670527 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1609 13:46:45.687956 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1610 13:46:45.706301 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1611 13:46:45.723898 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1612 13:46:45.778636 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1613 13:46:45.785442 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1614 13:46:45.810140 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1615 13:46:45.844502 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1616 13:46:45.862287 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1617 13:46:45.868647 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1618 13:46:45.885811 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1619 13:46:45.898827 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1620 13:46:45.914166 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1621 13:46:45.924527 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1622 13:46:45.960432 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1623 13:46:45.976408 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1624 13:46:45.990784 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1625 13:46:45.997587 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1626 13:46:46.009914 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1627 13:46:46.025221 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1628 13:46:46.065005 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1629 13:46:46.127738 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1630 13:46:46.196835
1631 13:46:46.197437 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1632 13:46:46.197851
1633 13:46:46.203952 debian-bookworm-arm64 login: root (automatic login)
1634 13:46:46.204430
1635 13:46:46.355028 Linux debian-bookworm-arm64 6.12.0-rc2 #1 SMP PREEMPT Tue Oct 22 12:41:09 UTC 2024 aarch64
1636 13:46:46.355620
1637 13:46:46.360932 The programs included with the Debian GNU/Linux system are free software;
1638 13:46:46.366093 the exact distribution terms for each program are described in the
1639 13:46:46.371568 individual files in /usr/share/doc/*/copyright.
1640 13:46:46.372043
1641 13:46:46.377112 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1642 13:46:46.380274 permitted by applicable law.
1643 13:46:47.009359 Matched prompt #10: / #
1645 13:46:47.010846 Setting prompt string to ['/ #']
1646 13:46:47.011383 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1648 13:46:47.012784 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1649 13:46:47.013310 start: 2.4.5 expect-shell-connection (timeout 00:03:18) [common]
1650 13:46:47.013742 Setting prompt string to ['/ #']
1651 13:46:47.014141 Forcing a shell prompt, looking for ['/ #']
1653 13:46:47.065099 / #
1654 13:46:47.065774 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1655 13:46:47.066214 Waiting using forced prompt support (timeout 00:02:30)
1656 13:46:47.071430
1657 13:46:47.072244 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1658 13:46:47.072800 start: 2.4.6 export-device-env (timeout 00:03:18) [common]
1659 13:46:47.073260 Sending with 10 millisecond of delay
1661 13:46:52.060587 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/881554/extract-nfsrootfs-lvrh3p1b'
1662 13:46:52.071599 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/881554/extract-nfsrootfs-lvrh3p1b'
1663 13:46:52.072509 Sending with 10 millisecond of delay
1665 13:46:54.170344 / # export NFS_SERVER_IP='192.168.6.2'
1666 13:46:54.181244 export NFS_SERVER_IP='192.168.6.2'
1667 13:46:54.182095 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1668 13:46:54.182682 end: 2.4 uboot-commands (duration 00:01:49) [common]
1669 13:46:54.183252 end: 2 uboot-action (duration 00:01:49) [common]
1670 13:46:54.183827 start: 3 lava-test-retry (timeout 00:06:52) [common]
1671 13:46:54.184611 start: 3.1 lava-test-shell (timeout 00:06:52) [common]
1672 13:46:54.185091 Using namespace: common
1674 13:46:54.286261 / # #
1675 13:46:54.286932 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1676 13:46:54.291889 #
1677 13:46:54.292668 Using /lava-881554
1679 13:46:54.393793 / # export SHELL=/bin/bash
1680 13:46:54.399445 export SHELL=/bin/bash
1682 13:46:54.500869 / # . /lava-881554/environment
1683 13:46:54.505822 . /lava-881554/environment
1685 13:46:54.611808 / # /lava-881554/bin/lava-test-runner /lava-881554/0
1686 13:46:54.612658 Test shell timeout: 10s (minimum of the action and connection timeout)
1687 13:46:54.616787 /lava-881554/bin/lava-test-runner /lava-881554/0
1688 13:46:54.828960 + export TESTRUN_ID=0_timesync-off
1689 13:46:54.836228 + TESTRUN_ID=0_timesync-off
1690 13:46:54.836721 + cd /lava-881554/0/tests/0_timesync-off
1691 13:46:54.837157 ++ cat uuid
1692 13:46:54.841781 + UUID=881554_1.6.2.4.1
1693 13:46:54.842222 + set +x
1694 13:46:54.843465 <LAVA_SIGNAL_STARTRUN 0_timesync-off 881554_1.6.2.4.1>
1695 13:46:54.844180 Received signal: <STARTRUN> 0_timesync-off 881554_1.6.2.4.1
1696 13:46:54.844632 Starting test lava.0_timesync-off (881554_1.6.2.4.1)
1697 13:46:54.845173 Skipping test definition patterns.
1698 13:46:54.849810 + systemctl stop systemd-timesyncd
1699 13:46:54.910029 + set +x
1700 13:46:54.910524 <LAVA_SIGNAL_ENDRUN 0_timesync-off 881554_1.6.2.4.1>
1701 13:46:54.911195 Received signal: <ENDRUN> 0_timesync-off 881554_1.6.2.4.1
1702 13:46:54.911695 Ending use of test pattern.
1703 13:46:54.912158 Ending test lava.0_timesync-off (881554_1.6.2.4.1), duration 0.07
1705 13:46:54.975427 + export TESTRUN_ID=1_kselftest-alsa
1706 13:46:54.982690 + TESTRUN_ID=1_kselftest-alsa
1707 13:46:54.983034 + cd /lava-881554/0/tests/1_kselftest-alsa
1708 13:46:54.983253 ++ cat uuid
1709 13:46:54.988224 + UUID=881554_1.6.2.4.5
1710 13:46:54.988501 + set +x
1711 13:46:54.993735 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 881554_1.6.2.4.5>
1712 13:46:54.994023 + cd ./automated/linux/kselftest/
1713 13:46:54.994470 Received signal: <STARTRUN> 1_kselftest-alsa 881554_1.6.2.4.5
1714 13:46:54.994706 Starting test lava.1_kselftest-alsa (881554_1.6.2.4.5)
1715 13:46:54.994969 Skipping test definition patterns.
1716 13:46:55.023359 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-sound/for-next/v6.12-rc2-163-g376efb6ef727/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g broonie-sound -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1717 13:46:55.059053 INFO: install_deps skipped
1718 13:46:55.195106 --2024-10-22 13:46:55-- http://storage.kernelci.org/broonie-sound/for-next/v6.12-rc2-163-g376efb6ef727/arm64/defconfig/gcc-12/kselftest.tar.xz
1719 13:46:55.219671 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1720 13:46:55.365423 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1721 13:46:55.513769 HTTP request sent, awaiting response... 200 OK
1722 13:46:55.514199 Length: 6953580 (6.6M) [application/octet-stream]
1723 13:46:55.519317 Saving to: 'kselftest_armhf.tar.gz'
1724 13:46:55.519651
1725 13:46:56.706202
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 49.92K 175KB/s
kselftest_armhf.tar 3%[ ] 216.29K 378KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.02MB/s
kselftest_armhf.tar 52%[=========> ] 3.51M 3.06MB/s
kselftest_armhf.tar 100%[===================>] 6.63M 5.58MB/s in 1.2s
1726 13:46:56.706642
1727 13:46:56.801209 2024-10-22 13:46:56 (5.58 MB/s) - 'kselftest_armhf.tar.gz' saved [6953580/6953580]
1728 13:46:56.801608
1729 13:47:06.180874 skiplist:
1730 13:47:06.181564 ========================================
1731 13:47:06.186697 ========================================
1732 13:47:06.231417 alsa:mixer-test
1733 13:47:06.232150 alsa:pcm-test
1734 13:47:06.232637 alsa:test-pcmtest-driver
1735 13:47:06.235445 alsa:utimer-test
1736 13:47:06.248366 ============== Tests to run ===============
1737 13:47:06.248979 alsa:mixer-test
1738 13:47:06.254000 alsa:pcm-test
1739 13:47:06.254638 alsa:test-pcmtest-driver
1740 13:47:06.255102 alsa:utimer-test
1741 13:47:06.262080 ===========End Tests to run ===============
1742 13:47:06.262669 shardfile-alsa pass
1743 13:47:06.387693 <12>[ 43.492417] kselftest: Running tests in alsa
1744 13:47:06.394773 TAP version 13
1745 13:47:06.402755 1..4
1746 13:47:06.424406 # timeout set to 45
1747 13:47:06.425046 # selftests: alsa: mixer-test
1748 13:47:06.585910 # TAP version 13
1749 13:47:06.586601 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1750 13:47:06.591493 # 1..427
1751 13:47:06.592160 # ok 1 get_value.LCALTA.60
1752 13:47:06.592636 # # LCALTA.60 TDMOUT_A SRC SEL
1753 13:47:06.596862 # ok 2 name.LCALTA.60
1754 13:47:06.597416 # ok 3 write_default.LCALTA.60
1755 13:47:06.600482 # ok 4 write_valid.LCALTA.60
1756 13:47:06.605921 # ok 5 write_invalid.LCALTA.60
1757 13:47:06.606476 # ok 6 event_missing.LCALTA.60
1758 13:47:06.611544 # ok 7 event_spurious.LCALTA.60
1759 13:47:06.612119 # ok 8 get_value.LCALTA.59
1760 13:47:06.617143 # # LCALTA.59 TDMOUT_B SRC SEL
1761 13:47:06.617694 # ok 9 name.LCALTA.59
1762 13:47:06.618160 # ok 10 write_default.LCALTA.59
1763 13:47:06.620917 # ok 11 write_valid.LCALTA.59
1764 13:47:06.626399 # ok 12 write_invalid.LCALTA.59
1765 13:47:06.626947 # ok 13 event_missing.LCALTA.59
1766 13:47:06.632044 # ok 14 event_spurious.LCALTA.59
1767 13:47:06.632595 # ok 15 get_value.LCALTA.58
1768 13:47:06.637556 # # LCALTA.58 TDMOUT_C SRC SEL
1769 13:47:06.638103 # ok 16 name.LCALTA.58
1770 13:47:06.643047 # ok 17 write_default.LCALTA.58
1771 13:47:06.643613 # ok 18 write_valid.LCALTA.58
1772 13:47:06.648691 # ok 19 write_invalid.LCALTA.58
1773 13:47:06.649265 # ok 20 event_missing.LCALTA.58
1774 13:47:06.654125 # ok 21 event_spurious.LCALTA.58
1775 13:47:06.654695 # ok 22 get_value.LCALTA.57
1776 13:47:06.659782 # # LCALTA.57 TDMIN_A SRC SEL
1777 13:47:06.660477 # ok 23 name.LCALTA.57
1778 13:47:06.665185 # ok 24 write_default.LCALTA.57
1779 13:47:06.665535 # ok 25 write_valid.LCALTA.57
1780 13:47:06.670723 # ok 26 write_invalid.LCALTA.57
1781 13:47:06.671288 # ok 27 event_missing.LCALTA.57
1782 13:47:06.676372 # ok 28 event_spurious.LCALTA.57
1783 13:47:06.676986 # ok 29 get_value.LCALTA.56
1784 13:47:06.681879 # # LCALTA.56 TDMIN_B SRC SEL
1785 13:47:06.682485 # ok 30 name.LCALTA.56
1786 13:47:06.682957 # ok 31 write_default.LCALTA.56
1787 13:47:06.698401 # ok 32 write_valid.<3>[ 43.791436] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1788 13:47:06.699083 LCALTA.56
1789 13:47:06.703817 # ok 33 write_invalid.LCALTA.56
1790 13:47:06.704456 # ok 34 event_missing.LCALTA.56
1791 13:47:06.709457 # ok 35 event_spurious.LCALTA.56
1792 13:47:06.710081 # ok 36 get_value.LCALTA.55
1793 13:47:06.714982 # # LCALTA.55 TDMIN_C SRC SEL
1794 13:47:06.715609 # ok 37 name.LCALTA.55
1795 13:47:06.720574 # ok 38 write_default.LCALTA.55
1796 13:47:06.721226 # ok 39 write_valid.LCALTA.55
1797 13:47:06.726017 # ok 40 write_invalid.LCALTA.55
1798 13:47:06.726606 # ok 41 event_missing.LCALTA.55
1799 13:47:06.732317 # ok 42 event_spurious.LCALTA.55
1800 13:47:06.732960 # ok 43 get_value.LCALTA.54
1801 13:47:06.737109 # # LCALTA.54 ACODEC Left DAC Sel
1802 13:47:06.737647 # ok 44 name.LCALTA.54
1803 13:47:06.738106 # ok 45 write_default.LCALTA.54
1804 13:47:06.742674 # ok 46 write_valid.LCALTA.54
1805 13:47:06.743223 # ok 47 write_invalid.LCALTA.54
1806 13:47:06.748274 # ok 48 event_missing.LCALTA.54
1807 13:47:06.753731 # ok 49 event_spurious.LCALTA.54
1808 13:47:06.754294 # ok 50 get_value.LCALTA.53
1809 13:47:06.759358 # # LCALTA.53 ACODEC Right DAC Sel
1810 13:47:06.759893 # ok 51 name.LCALTA.53
1811 13:47:06.760396 # ok 52 write_default.LCALTA.53
1812 13:47:06.764893 # ok 53 write_valid.LCALTA.53
1813 13:47:06.765460 # ok 54 write_invalid.LCALTA.53
1814 13:47:06.770430 # ok 55 event_missing.LCALTA.53
1815 13:47:06.770971 # ok 56 event_spurious.LCALTA.53
1816 13:47:06.775964 # ok 57 get_value.LCALTA.52
1817 13:47:06.781460 # # LCALTA.52 TOACODEC OUT EN Switch
1818 13:47:06.781971 # ok 58 name.LCALTA.52
1819 13:47:06.782421 # ok 59 write_default.LCALTA.52
1820 13:47:06.787032 # ok 60 write_valid.LCALTA.52
1821 13:47:06.787540 # ok 61 write_invalid.LCALTA.52
1822 13:47:06.792576 # ok 62 event_missing.LCALTA.52
1823 13:47:06.793077 # ok 63 event_spurious.LCALTA.52
1824 13:47:06.798119 # ok 64 get_value.LCALTA.51
1825 13:47:06.798632 # # LCALTA.51 TOACODEC SRC
1826 13:47:06.803683 # ok 65 name.LCALTA.51
1827 13:47:06.804251 # ok 66 write_default.LCALTA.51
1828 13:47:06.809288 # ok 67 write_valid.LCALTA.51
1829 13:47:06.809838 # ok 68 write_invalid.LCALTA.51
1830 13:47:06.814779 # ok 69 event_missing.LCALTA.51
1831 13:47:06.815335 # ok 70 event_spurious.LCALTA.51
1832 13:47:06.820413 # ok 71 get_value.LCALTA.50
1833 13:47:06.820925 # # LCALTA.50 TOHDMITX SPDIF SRC
1834 13:47:06.825861 # ok 72 name.LCALTA.50
1835 13:47:06.826380 # ok 73 write_default.LCALTA.50
1836 13:47:06.831441 # ok 74 write_valid.LCALTA.50
1837 13:47:06.831943 # ok 75 write_invalid.LCALTA.50
1838 13:47:06.836929 # ok 76 event_missing.LCALTA.50
1839 13:47:06.837429 # ok 77 event_spurious.LCALTA.50
1840 13:47:06.842522 # ok 78 get_value.LCALTA.49
1841 13:47:06.843030 # # LCALTA.49 TOHDMITX Switch
1842 13:47:06.848060 # ok 79 name.LCALTA.49
1843 13:47:06.848574 # ok 80 write_default.LCALTA.49
1844 13:47:06.853581 # ok 81 write_valid.LCALTA.49
1845 13:47:06.854086 # ok 82 write_invalid.LCALTA.49
1846 13:47:06.859129 # ok 83 event_missing.LCALTA.49
1847 13:47:06.859638 # ok 84 event_spurious.LCALTA.49
1848 13:47:06.864679 # ok 85 get_value.LCALTA.48
1849 13:47:06.865185 # # LCALTA.48 TOHDMITX I2S SRC
1850 13:47:06.865618 # ok 86 name.LCALTA.48
1851 13:47:06.870233 # ok 87 write_default.LCALTA.48
1852 13:47:06.870736 # ok 88 write_valid.LCALTA.48
1853 13:47:06.875775 # ok 89 write_invalid.LCALTA.48
1854 13:47:06.876317 # ok 90 event_missing.LCALTA.48
1855 13:47:06.881406 # ok 91 event_spurious.LCALTA.48
1856 13:47:06.881912 # ok 92 get_value.LCALTA.47
1857 13:47:06.886891 # # LCALTA.47 TODDR_C SRC SEL
1858 13:47:06.887401 # ok 93 name.LCALTA.47
1859 13:47:06.892446 # ok 94 write_default.LCALTA.47
1860 13:47:06.892955 # ok 95 write_valid.LCALTA.47
1861 13:47:06.897967 # ok 96 write_invalid.LCALTA.47
1862 13:47:06.898481 # ok 97 event_missing.LCALTA.47
1863 13:47:06.903534 # ok 98 event_spurious.LCALTA.47
1864 13:47:06.904099 # ok 99 get_value.LCALTA.46
1865 13:47:06.909177 # # LCALTA.46 TODDR_B SRC SEL
1866 13:47:06.909708 # ok 100 name.LCALTA.46
1867 13:47:06.914625 # ok 101 write_default.LCALTA.46
1868 13:47:06.915151 # ok 102 write_valid.LCALTA.46
1869 13:47:06.920276 # ok 103 write_invalid.LCALTA.46
1870 13:47:06.920808 # ok 104 event_missing.LCALTA.46
1871 13:47:06.925726 # ok 105 event_spurious.LCALTA.46
1872 13:47:06.926244 # ok 106 get_value.LCALTA.45
1873 13:47:06.931252 # # LCALTA.45 TODDR_A SRC SEL
1874 13:47:06.931757 # ok 107 name.LCALTA.45
1875 13:47:06.936786 # ok 108 write_default.LCALTA.45
1876 13:47:06.937302 # ok 109 write_valid.LCALTA.45
1877 13:47:06.942488 # ok 110 write_invalid.LCALTA.45
1878 13:47:06.943054 # ok 111 event_missing.LCALTA.45
1879 13:47:06.947915 # ok 112 event_spurious.LCALTA.45
1880 13:47:06.948484 # ok 113 get_value.LCALTA.44
1881 13:47:06.953463 # # LCALTA.44 FRDDR_C SINK 3 SEL
1882 13:47:06.953997 # ok 114 name.LCALTA.44
1883 13:47:06.958995 # ok 115 write_default.LCALTA.44
1884 13:47:06.959529 # ok 116 write_valid.LCALTA.44
1885 13:47:06.964585 # ok 117 write_invalid.LCALTA.44
1886 13:47:06.965127 # ok 118 event_missing.LCALTA.44
1887 13:47:06.970196 # ok 119 event_spurious.LCALTA.44
1888 13:47:06.970743 # ok 120 get_value.LCALTA.43
1889 13:47:06.975651 # # LCALTA.43 FRDDR_C SINK 2 SEL
1890 13:47:06.976227 # ok 121 name.LCALTA.43
1891 13:47:06.981283 # ok 122 write_default.LCALTA.43
1892 13:47:06.981859 # ok 123 write_valid.LCALTA.43
1893 13:47:06.986788 # ok 124 write_invalid.LCALTA.43
1894 13:47:06.987378 # ok 125 event_missing.LCALTA.43
1895 13:47:06.992489 # ok 126 event_spurious.LCALTA.43
1896 13:47:06.993061 # ok 127 get_value.LCALTA.42
1897 13:47:06.997864 # # LCALTA.42 FRDDR_C SINK 1 SEL
1898 13:47:06.998413 # ok 128 name.LCALTA.42
1899 13:47:07.003464 # ok 129 write_default.LCALTA.42
1900 13:47:07.004050 # ok 130 write_valid.LCALTA.42
1901 13:47:07.008939 # ok 131 write_invalid.LCALTA.42
1902 13:47:07.009488 # ok 132 event_missing.LCALTA.42
1903 13:47:07.014455 # ok 133 event_spurious.LCALTA.42
1904 13:47:07.014992 # ok 134 get_value.LCALTA.41
1905 13:47:07.020028 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1906 13:47:07.020583 # ok 135 name.LCALTA.41
1907 13:47:07.025515 # ok 136 write_default.LCALTA.41
1908 13:47:07.026045 # ok 137 write_valid.LCALTA.41
1909 13:47:07.031160 # ok 138 write_invalid.LCALTA.41
1910 13:47:07.031686 # ok 139 event_missing.LCALTA.41
1911 13:47:07.036604 # ok 140 event_spurious.LCALTA.41
1912 13:47:07.037130 # ok 141 get_value.LCALTA.40
1913 13:47:07.042190 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1914 13:47:07.042720 # ok 142 name.LCALTA.40
1915 13:47:07.047703 # ok 143 write_default.LCALTA.40
1916 13:47:07.053437 # ok 144 write_valid.LCALTA.40
1917 13:47:07.053972 # ok 145 write_invalid.LCALTA.40
1918 13:47:07.058784 # ok 146 event_missing.LCALTA.40
1919 13:47:07.059305 # ok 147 event_spurious.LCALTA.40
1920 13:47:07.064376 # ok 148 get_value.LCALTA.39
1921 13:47:07.064896 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1922 13:47:07.069878 # ok 149 name.LCALTA.39
1923 13:47:07.070390 # ok 150 write_default.LCALTA.39
1924 13:47:07.075426 # ok 151 write_valid.LCALTA.39
1925 13:47:07.075939 # ok 152 write_invalid.LCALTA.39
1926 13:47:07.080979 # ok 153 event_missing.LCALTA.39
1927 13:47:07.081497 # ok 154 event_spurious.LCALTA.39
1928 13:47:07.086519 # ok 155 get_value.LCALTA.38
1929 13:47:07.087031 # # LCALTA.38 FRDDR_B SINK 3 SEL
1930 13:47:07.092271 # ok 156 name.LCALTA.38
1931 13:47:07.092800 # ok 157 write_default.LCALTA.38
1932 13:47:07.097660 # ok 158 write_valid.LCALTA.38
1933 13:47:07.098188 # ok 159 write_invalid.LCALTA.38
1934 13:47:07.103188 # ok 160 event_missing.LCALTA.38
1935 13:47:07.103707 # ok 161 event_spurious.LCALTA.38
1936 13:47:07.108712 # ok 162 get_value.LCALTA.37
1937 13:47:07.109230 # # LCALTA.37 FRDDR_B SINK 2 SEL
1938 13:47:07.114411 # ok 163 name.LCALTA.37
1939 13:47:07.114932 # ok 164 write_default.LCALTA.37
1940 13:47:07.119821 # ok 165 write_valid.LCALTA.37
1941 13:47:07.120383 # ok 166 write_invalid.LCALTA.37
1942 13:47:07.125439 # ok 167 event_missing.LCALTA.37
1943 13:47:07.125977 # ok 168 event_spurious.LCALTA.37
1944 13:47:07.130907 # ok 169 get_value.LCALTA.36
1945 13:47:07.131436 # # LCALTA.36 FRDDR_B SINK 1 SEL
1946 13:47:07.136466 # ok 170 name.LCALTA.36
1947 13:47:07.137000 # ok 171 write_default.LCALTA.36
1948 13:47:07.142032 # ok 172 write_valid.LCALTA.36
1949 13:47:07.142565 # ok 173 write_invalid.LCALTA.36
1950 13:47:07.147545 # ok 174 event_missing.LCALTA.36
1951 13:47:07.148107 # ok 175 event_spurious.LCALTA.36
1952 13:47:07.153189 # ok 176 get_value.LCALTA.35
1953 13:47:07.153720 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1954 13:47:07.158653 # ok 177 name.LCALTA.35
1955 13:47:07.159185 # ok 178 write_default.LCALTA.35
1956 13:47:07.164255 # ok 179 write_valid.LCALTA.35
1957 13:47:07.164795 # ok 180 write_invalid.LCALTA.35
1958 13:47:07.169736 # ok 181 event_missing.LCALTA.35
1959 13:47:07.170267 # ok 182 event_spurious.LCALTA.35
1960 13:47:07.175412 # ok 183 get_value.LCALTA.34
1961 13:47:07.180823 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1962 13:47:07.181367 # ok 184 name.LCALTA.34
1963 13:47:07.181808 # ok 185 write_default.LCALTA.34
1964 13:47:07.186412 # ok 186 write_valid.LCALTA.34
1965 13:47:07.186941 # ok 187 write_invalid.LCALTA.34
1966 13:47:07.191947 # ok 188 event_missing.LCALTA.34
1967 13:47:07.197498 # ok 189 event_spurious.LCALTA.34
1968 13:47:07.198028 # ok 190 get_value.LCALTA.33
1969 13:47:07.203042 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1970 13:47:07.203587 # ok 191 name.LCALTA.33
1971 13:47:07.208591 # ok 192 write_default.LCALTA.33
1972 13:47:07.209135 # ok 193 write_valid.LCALTA.33
1973 13:47:07.214237 # ok 194 write_invalid.LCALTA.33
1974 13:47:07.214776 # ok 195 event_missing.LCALTA.33
1975 13:47:07.219725 # ok 196 event_spurious.LCALTA.33
1976 13:47:07.220309 # ok 197 get_value.LCALTA.32
1977 13:47:07.225248 # # LCALTA.32 FRDDR_A SINK 3 SEL
1978 13:47:07.225789 # ok 198 name.LCALTA.32
1979 13:47:07.230839 # ok 199 write_default.LCALTA.32
1980 13:47:07.231387 # ok 200 write_valid.LCALTA.32
1981 13:47:07.236479 # ok 201 write_invalid.LCALTA.32
1982 13:47:07.237014 # ok 202 event_missing.LCALTA.32
1983 13:47:07.241890 # ok 203 event_spurious.LCALTA.32
1984 13:47:07.242441 # ok 204 get_value.LCALTA.31
1985 13:47:07.247491 # # LCALTA.31 FRDDR_A SINK 2 SEL
1986 13:47:07.248064 # ok 205 name.LCALTA.31
1987 13:47:07.253021 # ok 206 write_default.LCALTA.31
1988 13:47:07.253567 # ok 207 write_valid.LCALTA.31
1989 13:47:07.258553 # ok 208 write_invalid.LCALTA.31
1990 13:47:07.259100 # ok 209 event_missing.LCALTA.31
1991 13:47:07.264100 # ok 210 event_spurious.LCALTA.31
1992 13:47:07.264646 # ok 211 get_value.LCALTA.30
1993 13:47:07.269632 # # LCALTA.30 FRDDR_A SINK 1 SEL
1994 13:47:07.270172 # ok 212 name.LCALTA.30
1995 13:47:07.275273 # ok 213 write_default.LCALTA.30
1996 13:47:07.275820 # ok 214 write_valid.LCALTA.30
1997 13:47:07.280737 # ok 215 write_invalid.LCALTA.30
1998 13:47:07.281282 # ok 216 event_missing.LCALTA.30
1999 13:47:07.286280 # ok 217 event_spurious.LCALTA.30
2000 13:47:07.286821 # ok 218 get_value.LCALTA.29
2001 13:47:07.291820 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2002 13:47:07.292394 # ok 219 name.LCALTA.29
2003 13:47:07.297487 # ok 220 write_default.LCALTA.29
2004 13:47:07.298023 # ok 221 write_valid.LCALTA.29
2005 13:47:07.302911 # ok 222 write_invalid.LCALTA.29
2006 13:47:07.303455 # ok 223 event_missing.LCALTA.29
2007 13:47:07.308493 # ok 224 event_spurious.LCALTA.29
2008 13:47:07.309040 # ok 225 get_value.LCALTA.28
2009 13:47:07.313995 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2010 13:47:07.314535 # ok 226 name.LCALTA.28
2011 13:47:07.319550 # ok 227 write_default.LCALTA.28
2012 13:47:07.320141 # ok 228 write_valid.LCALTA.28
2013 13:47:07.325098 # ok 229 write_invalid.LCALTA.28
2014 13:47:07.325648 # ok 230 event_missing.LCALTA.28
2015 13:47:07.330652 # ok 231 event_spurious.LCALTA.28
2016 13:47:07.331209 # ok 232 get_value.LCALTA.27
2017 13:47:07.336273 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2018 13:47:07.336869 # ok 233 name.LCALTA.27
2019 13:47:07.341821 # ok 234 write_default.LCALTA.27
2020 13:47:07.342434 # ok 235 write_valid.LCALTA.27
2021 13:47:07.347335 # ok 236 write_invalid.LCALTA.27
2022 13:47:07.352816 # ok 237 event_missing.LCALTA.27
2023 13:47:07.353390 # ok 238 event_spurious.LCALTA.27
2024 13:47:07.358482 # ok 239 get_value.LCALTA.26
2025 13:47:07.359036 # # LCALTA.26 ELD
2026 13:47:07.359492 # ok 240 name.LCALTA.26
2027 13:47:07.363921 # # ELD is not writeable
2028 13:47:07.364503 # ok 241 # SKIP write_default.LCALTA.26
2029 13:47:07.369514 # # ELD is not writeable
2030 13:47:07.370092 # ok 242 # SKIP write_valid.LCALTA.26
2031 13:47:07.375030 # # ELD is not writeable
2032 13:47:07.375570 # ok 243 # SKIP write_invalid.LCALTA.26
2033 13:47:07.380552 # ok 244 event_missing.LCALTA.26
2034 13:47:07.381095 # ok 245 event_spurious.LCALTA.26
2035 13:47:07.386109 # ok 246 get_value.LCALTA.25
2036 13:47:07.391645 # # LCALTA.25 IEC958 Playback Default
2037 13:47:07.392230 # ok 247 name.LCALTA.25
2038 13:47:07.392688 # ok 248 write_default.LCALTA.25
2039 13:47:07.397309 # ok 249 # SKIP write_valid.LCALTA.25
2040 13:47:07.402763 # ok 250 # SKIP write_invalid.LCALTA.25
2041 13:47:07.403342 # ok 251 event_missing.LCALTA.25
2042 13:47:07.408304 # ok 252 event_spurious.LCALTA.25
2043 13:47:07.408870 # ok 253 get_value.LCALTA.24
2044 13:47:07.413829 # # LCALTA.24 IEC958 Playback Mask
2045 13:47:07.414396 # ok 254 name.LCALTA.24
2046 13:47:07.419472 # # IEC958 Playback Mask is not writeable
2047 13:47:07.420066 # ok 255 # SKIP write_default.LCALTA.24
2048 13:47:07.424948 # # IEC958 Playback Mask is not writeable
2049 13:47:07.430514 # ok 256 # SKIP write_valid.LCALTA.24
2050 13:47:07.431085 # # IEC958 Playback Mask is not writeable
2051 13:47:07.436053 # ok 257 # SKIP write_invalid.LCALTA.24
2052 13:47:07.441545 # ok 258 event_missing.LCALTA.24
2053 13:47:07.442094 # ok 259 event_spurious.LCALTA.24
2054 13:47:07.447102 # ok 260 get_value.LCALTA.23
2055 13:47:07.447642 # # LCALTA.23 Playback Channel Map
2056 13:47:07.452639 # ok 261 name.LCALTA.23
2057 13:47:07.453181 # # Playback Channel Map is not writeable
2058 13:47:07.458209 # ok 262 # SKIP write_default.LCALTA.23
2059 13:47:07.463724 # # Playback Channel Map is not writeable
2060 13:47:07.464303 # ok 263 # SKIP write_valid.LCALTA.23
2061 13:47:07.469298 # # Playback Channel Map is not writeable
2062 13:47:07.469836 # ok 264 # SKIP write_invalid.LCALTA.23
2063 13:47:07.474862 # ok 265 event_missing.LCALTA.23
2064 13:47:07.480479 # ok 266 event_spurious.LCALTA.23
2065 13:47:07.481044 # ok 267 get_value.LCALTA.22
2066 13:47:07.485956 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2067 13:47:07.486503 # ok 268 name.LCALTA.22
2068 13:47:07.491509 # ok 269 write_default.LCALTA.22
2069 13:47:07.492077 # ok 270 write_valid.LCALTA.22
2070 13:47:07.497049 # ok 271 write_invalid.LCALTA.22
2071 13:47:07.497580 # ok 272 event_missing.LCALTA.22
2072 13:47:07.502574 # ok 273 event_spurious.LCALTA.22
2073 13:47:07.503101 # ok 274 get_value.LCALTA.21
2074 13:47:07.508146 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2075 13:47:07.508675 # ok 275 name.LCALTA.21
2076 13:47:07.513678 # ok 276 write_default.LCALTA.21
2077 13:47:07.514227 # ok 277 write_valid.LCALTA.21
2078 13:47:07.519263 # ok 278 write_invalid.LCALTA.21
2079 13:47:07.519822 # ok 279 event_missing.LCALTA.21
2080 13:47:07.524736 # ok 280 event_spurious.LCALTA.21
2081 13:47:07.525289 # ok 281 get_value.LCALTA.20
2082 13:47:07.530314 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2083 13:47:07.530861 # ok 282 name.LCALTA.20
2084 13:47:07.535881 # ok 283 write_default.LCALTA.20
2085 13:47:07.536475 # ok 284 write_valid.LCALTA.20
2086 13:47:07.541513 # ok 285 write_invalid.LCALTA.20
2087 13:47:07.542047 # ok 286 event_missing.LCALTA.20
2088 13:47:07.546922 # ok 287 event_spurious.LCALTA.20
2089 13:47:07.547454 # ok 288 get_value.LCALTA.19
2090 13:47:07.552504 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2091 13:47:07.553050 # ok 289 name.LCALTA.19
2092 13:47:07.558052 # ok 290 write_default.LCALTA.19
2093 13:47:07.558580 # ok 291 write_valid.LCALTA.19
2094 13:47:07.563567 # ok 292 write_invalid.LCALTA.19
2095 13:47:07.564139 # ok 293 event_missing.LCALTA.19
2096 13:47:07.569144 # ok 294 event_spurious.LCALTA.19
2097 13:47:07.569687 # ok 295 get_value.LCALTA.18
2098 13:47:07.574727 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2099 13:47:07.575311 # ok 296 name.LCALTA.18
2100 13:47:07.580298 # ok 297 write_default.LCALTA.18
2101 13:47:07.585809 # ok 298 write_valid.LCALTA.18
2102 13:47:07.586377 # ok 299 write_invalid.LCALTA.18
2103 13:47:07.591351 # ok 300 event_missing.LCALTA.18
2104 13:47:07.591900 # ok 301 event_spurious.LCALTA.18
2105 13:47:07.596886 # ok 302 get_value.LCALTA.17
2106 13:47:07.597435 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2107 13:47:07.602511 # ok 303 name.LCALTA.17
2108 13:47:07.603068 # ok 304 write_default.LCALTA.17
2109 13:47:07.607951 # ok 305 write_valid.LCALTA.17
2110 13:47:07.608539 # ok 306 write_invalid.LCALTA.17
2111 13:47:07.613531 # ok 307 event_missing.LCALTA.17
2112 13:47:07.614094 # ok 308 event_spurious.LCALTA.17
2113 13:47:07.619076 # ok 309 get_value.LCALTA.16
2114 13:47:07.619626 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2115 13:47:07.624608 # ok 310 name.LCALTA.16
2116 13:47:07.625158 # ok 311 write_default.LCALTA.16
2117 13:47:07.630167 # ok 312 write_valid.LCALTA.16
2118 13:47:07.630720 # ok 313 write_invalid.LCALTA.16
2119 13:47:07.635679 # ok 314 event_missing.LCALTA.16
2120 13:47:07.636261 # ok 315 event_spurious.LCALTA.16
2121 13:47:07.641324 # ok 316 get_value.LCALTA.15
2122 13:47:07.641870 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2123 13:47:07.646807 # ok 317 name.LCALTA.15
2124 13:47:07.647339 # ok 318 write_default.LCALTA.15
2125 13:47:07.652359 # ok 319 write_valid.LCALTA.15
2126 13:47:07.652916 # ok 320 write_invalid.LCALTA.15
2127 13:47:07.657912 # ok 321 event_missing.LCALTA.15
2128 13:47:07.658463 # ok 322 event_spurious.LCALTA.15
2129 13:47:07.663498 # ok 323 get_value.LCALTA.14
2130 13:47:07.668981 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2131 13:47:07.669531 # ok 324 name.LCALTA.14
2132 13:47:07.669988 # ok 325 write_default.LCALTA.14
2133 13:47:07.674536 # ok 326 write_valid.LCALTA.14
2134 13:47:07.675092 # ok 327 write_invalid.LCALTA.14
2135 13:47:07.680115 # ok 328 event_missing.LCALTA.14
2136 13:47:07.685627 # ok 329 event_spurious.LCALTA.14
2137 13:47:07.686182 # ok 330 get_value.LCALTA.13
2138 13:47:07.691160 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2139 13:47:07.691713 # ok 331 name.LCALTA.13
2140 13:47:07.696719 # ok 332 write_default.LCALTA.13
2141 13:47:07.697267 # ok 333 write_valid.LCALTA.13
2142 13:47:07.702205 # ok 334 write_invalid.LCALTA.13
2143 13:47:07.702754 # ok 335 event_missing.LCALTA.13
2144 13:47:07.707818 # ok 336 event_spurious.LCALTA.13
2145 13:47:07.708405 # ok 337 get_value.LCALTA.12
2146 13:47:07.713348 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2147 13:47:07.713895 # ok 338 name.LCALTA.12
2148 13:47:07.718919 # ok 339 write_default.LCALTA.12
2149 13:47:07.719464 # ok 340 write_valid.LCALTA.12
2150 13:47:07.724524 # ok 341 write_invalid.LCALTA.12
2151 13:47:07.725063 # ok 342 event_missing.LCALTA.12
2152 13:47:07.730009 # ok 343 event_spurious.LCALTA.12
2153 13:47:07.730580 # ok 344 get_value.LCALTA.11
2154 13:47:07.735539 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2155 13:47:07.736132 # ok 345 name.LCALTA.11
2156 13:47:07.741086 # ok 346 write_default.LCALTA.11
2157 13:47:07.741621 # ok 347 write_valid.LCALTA.11
2158 13:47:07.746613 # ok 348 write_invalid.LCALTA.11
2159 13:47:07.747166 # ok 349 event_missing.LCALTA.11
2160 13:47:07.752158 # ok 350 event_spurious.LCALTA.11
2161 13:47:07.752694 # ok 351 get_value.LCALTA.10
2162 13:47:07.757705 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2163 13:47:07.758259 # ok 352 name.LCALTA.10
2164 13:47:07.763272 # ok 353 write_default.LCALTA.10
2165 13:47:07.763813 # ok 354 write_valid.LCALTA.10
2166 13:47:07.768833 # ok 355 write_invalid.LCALTA.10
2167 13:47:07.769385 # ok 356 event_missing.LCALTA.10
2168 13:47:07.774317 # ok 357 event_spurious.LCALTA.10
2169 13:47:07.774865 # ok 358 get_value.LCALTA.9
2170 13:47:07.779918 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2171 13:47:07.780492 # ok 359 name.LCALTA.9
2172 13:47:07.785536 # ok 360 write_default.LCALTA.9
2173 13:47:07.786082 # ok 361 write_valid.LCALTA.9
2174 13:47:07.791007 # ok 362 write_invalid.LCALTA.9
2175 13:47:07.791541 # ok 363 event_missing.LCALTA.9
2176 13:47:07.796581 # ok 364 event_spurious.LCALTA.9
2177 13:47:07.797121 # ok 365 get_value.LCALTA.8
2178 13:47:07.802072 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2179 13:47:07.802600 # ok 366 name.LCALTA.8
2180 13:47:07.807604 # ok 367 write_default.LCALTA.8
2181 13:47:07.808163 # ok 368 write_valid.LCALTA.8
2182 13:47:07.813180 # ok 369 write_invalid.LCALTA.8
2183 13:47:07.813703 # ok 370 event_missing.LCALTA.8
2184 13:47:07.818730 # ok 371 event_spurious.LCALTA.8
2185 13:47:07.819267 # ok 372 get_value.LCALTA.7
2186 13:47:07.824271 # # LCALTA.7 ACODEC Unmute Ramp Switch
2187 13:47:07.824822 # ok 373 name.LCALTA.7
2188 13:47:07.829826 # ok 374 write_default.LCALTA.7
2189 13:47:07.830352 # ok 375 write_valid.LCALTA.7
2190 13:47:07.835335 # ok 376 write_invalid.LCALTA.7
2191 13:47:07.835851 # ok 377 event_missing.LCALTA.7
2192 13:47:07.840906 # ok 378 event_spurious.LCALTA.7
2193 13:47:07.841420 # ok 379 get_value.LCALTA.6
2194 13:47:07.846501 # # LCALTA.6 ACODEC Mute Ramp Switch
2195 13:47:07.847021 # ok 380 name.LCALTA.6
2196 13:47:07.852036 # ok 381 write_default.LCALTA.6
2197 13:47:07.852551 # ok 382 write_valid.LCALTA.6
2198 13:47:07.857633 # ok 383 write_invalid.LCALTA.6
2199 13:47:07.858157 # ok 384 event_missing.LCALTA.6
2200 13:47:07.863108 # ok 385 event_spurious.LCALTA.6
2201 13:47:07.863626 # ok 386 get_value.LCALTA.5
2202 13:47:07.868645 # # LCALTA.5 ACODEC Volume Ramp Switch
2203 13:47:07.869157 # ok 387 name.LCALTA.5
2204 13:47:07.874207 # ok 388 write_default.LCALTA.5
2205 13:47:07.874726 # ok 389 write_valid.LCALTA.5
2206 13:47:07.879731 # ok 390 write_invalid.LCALTA.5
2207 13:47:07.880286 # ok 391 event_missing.LCALTA.5
2208 13:47:07.885286 # ok 392 event_spurious.LCALTA.5
2209 13:47:07.885811 # ok 393 get_value.LCALTA.4
2210 13:47:07.890841 # # LCALTA.4 ACODEC Ramp Rate
2211 13:47:07.891355 # ok 394 name.LCALTA.4
2212 13:47:07.896370 # ok 395 write_default.LCALTA.4
2213 13:47:07.896890 # ok 396 write_valid.LCALTA.4
2214 13:47:07.901913 # ok 397 write_invalid.LCALTA.4
2215 13:47:07.902434 # ok 398 event_missing.LCALTA.4
2216 13:47:07.907524 # ok 399 event_spurious.LCALTA.4
2217 13:47:07.908073 # ok 400 get_value.LCALTA.3
2218 13:47:07.913015 # # LCALTA.3 ACODEC Playback Volume
2219 13:47:07.913542 # ok 401 name.LCALTA.3
2220 13:47:07.918594 # ok 402 write_default.LCALTA.3
2221 13:47:07.919128 # ok 403 write_valid.LCALTA.3
2222 13:47:07.924101 # ok 404 write_invalid.LCALTA.3
2223 13:47:07.924628 # ok 405 event_missing.LCALTA.3
2224 13:47:07.929657 # ok 406 event_spurious.LCALTA.3
2225 13:47:07.930166 # ok 407 get_value.LCALTA.2
2226 13:47:07.935190 # # LCALTA.2 ACODEC Playback Switch
2227 13:47:07.935713 # ok 408 name.LCALTA.2
2228 13:47:07.940741 # ok 409 write_default.LCALTA.2
2229 13:47:07.941266 # ok 410 write_valid.LCALTA.2
2230 13:47:07.946279 # ok 411 write_invalid.LCALTA.2
2231 13:47:07.946796 # ok 412 event_missing.LCALTA.2
2232 13:47:07.951824 # ok 413 event_spurious.LCALTA.2
2233 13:47:07.952380 # ok 414 get_value.LCALTA.1
2234 13:47:07.957382 # # LCALTA.1 ACODEC Playback Channel Mode
2235 13:47:07.957910 # ok 415 name.LCALTA.1
2236 13:47:07.962962 # ok 416 write_default.LCALTA.1
2237 13:47:07.963485 # ok 417 write_valid.LCALTA.1
2238 13:47:07.968559 # ok 418 write_invalid.LCALTA.1
2239 13:47:07.969097 # ok 419 event_missing.LCALTA.1
2240 13:47:07.974030 # ok 420 event_spurious.LCALTA.1
2241 13:47:07.974552 # ok 421 get_value.LCALTA.0
2242 13:47:07.979590 # # LCALTA.0 TOACODEC Lane Select
2243 13:47:07.980147 # ok 422 name.LCALTA.0
2244 13:47:07.985120 # ok 423 write_default.LCALTA.0
2245 13:47:07.985634 # ok 424 write_valid.LCALTA.0
2246 13:47:07.990643 # ok 425 write_invalid.LCALTA.0
2247 13:47:07.991158 # ok 426 event_missing.LCALTA.0
2248 13:47:07.996316 # ok 427 event_spurious.LCALTA.0
2249 13:47:08.001731 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2250 13:47:08.002259 ok 1 selftests: alsa: mixer-test
2251 13:47:08.007318 # timeout set to 45
2252 13:47:08.007832 # selftests: alsa: pcm-test
2253 13:47:08.008324 # TAP version 13
2254 13:47:08.012860 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2255 13:47:08.013378 # # LCALTA.0 - fe.dai-link-0 (*)
2256 13:47:08.018372 # # LCALTA.0 - fe.dai-link-1 (*)
2257 13:47:08.023931 # # LCALTA.0 - fe.dai-link-2 (*)
2258 13:47:08.024476 # # LCALTA.0 - fe.dai-link-3 (*)
2259 13:47:08.029544 # # LCALTA.0 - fe.dai-link-4 (*)
2260 13:47:08.030063 # # LCALTA.0 - fe.dai-link-5 (*)
2261 13:47:08.030521 # 1..42
2262 13:47:08.035051 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2263 13:47:08.040574 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2264 13:47:08.046096 # # snd_pcm_hw_params: Invalid argument
2265 13:47:08.051677 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2266 13:47:08.052239 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2267 13:47:08.057192 # # snd_pcm_hw_params: Invalid argument
2268 13:47:08.062758 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2269 13:47:08.068324 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2270 13:47:08.073854 # # snd_pcm_hw_params: Invalid argument
2271 13:47:08.079369 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2272 13:47:08.079892 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2273 13:47:08.084937 # # snd_pcm_hw_params: Invalid argument
2274 13:47:08.090543 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2275 13:47:08.096084 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2276 13:47:08.096616 # # snd_pcm_hw_params: Invalid argument
2277 13:47:08.107088 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2278 13:47:08.107616 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2279 13:47:08.112689 # # snd_pcm_hw_params: Invalid argument
2280 13:47:08.118223 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2281 13:47:08.123789 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2282 13:47:08.124340 # # snd_pcm_hw_params: Invalid argument
2283 13:47:08.129358 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2284 13:47:08.134880 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2285 13:47:08.140574 # # snd_pcm_hw_params: Invalid argument
2286 13:47:08.145974 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2287 13:47:08.151545 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2288 13:47:08.152104 # # snd_pcm_hw_params: Invalid argument
2289 13:47:08.157082 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2290 13:47:08.162623 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2291 13:47:08.168140 # # snd_pcm_hw_params: Invalid argument
2292 13:47:08.173700 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2293 13:47:08.174224 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2294 13:47:08.179328 # # snd_pcm_hw_params: Invalid argument
2295 13:47:08.184799 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2296 13:47:08.190366 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2297 13:47:08.195876 # # snd_pcm_hw_params: Invalid argument
2298 13:47:08.201448 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2299 13:47:08.201974 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2300 13:47:08.207014 # # snd_pcm_hw_params: Invalid argument
2301 13:47:08.212619 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2302 13:47:08.218111 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2303 13:47:08.223641 # # snd_pcm_hw_params: Invalid argument
2304 13:47:08.229159 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2305 13:47:08.229704 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2306 13:47:08.234733 # # snd_pcm_hw_params: Invalid argument
2307 13:47:08.240445 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2308 13:47:08.245852 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2309 13:47:08.246423 # # snd_pcm_hw_params: Invalid argument
2310 13:47:08.251400 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2311 13:47:08.256945 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2312 13:47:08.262629 # # snd_pcm_hw_params: Invalid argument
2313 13:47:08.268016 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2314 13:47:08.273581 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2315 13:47:08.274130 # # snd_pcm_hw_params: Invalid argument
2316 13:47:08.279084 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2317 13:47:08.284638 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2318 13:47:08.290199 # # snd_pcm_hw_params: Invalid argument
2319 13:47:08.295752 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2320 13:47:08.301358 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2321 13:47:08.301910 # # snd_pcm_hw_params: Invalid argument
2322 13:47:08.306840 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2323 13:47:08.312376 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2324 13:47:08.317935 # # snd_pcm_hw_params: Invalid argument
2325 13:47:08.323597 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2326 13:47:08.324202 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2327 13:47:08.329037 # # snd_pcm_hw_params: Invalid argument
2328 13:47:08.334614 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2329 13:47:08.340141 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2330 13:47:08.345674 # # snd_pcm_hw_params: Invalid argument
2331 13:47:08.351235 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2332 13:47:08.351812 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2333 13:47:08.356771 # # snd_pcm_hw_params: Invalid argument
2334 13:47:08.362403 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2335 13:47:08.367894 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2336 13:47:08.373442 # # snd_pcm_hw_params: Invalid argument
2337 13:47:08.378963 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2338 13:47:08.379536 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2339 13:47:08.384631 # # snd_pcm_hw_params: Invalid argument
2340 13:47:08.390067 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2341 13:47:08.395598 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2342 13:47:08.401117 # # snd_pcm_hw_params: Invalid argument
2343 13:47:08.406657 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2344 13:47:08.407184 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2345 13:47:08.412221 # # snd_pcm_hw_params: Invalid argument
2346 13:47:08.417756 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2347 13:47:08.423315 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2348 13:47:08.428812 # # snd_pcm_hw_params: Invalid argument
2349 13:47:08.434351 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2350 13:47:08.434867 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2351 13:47:08.439899 # # snd_pcm_hw_params: Invalid argument
2352 13:47:08.445564 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2353 13:47:08.450993 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2354 13:47:08.456590 # # snd_pcm_hw_params: Invalid argument
2355 13:47:08.462105 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2356 13:47:08.462635 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2357 13:47:08.467666 # # snd_pcm_hw_params: Invalid argument
2358 13:47:08.473256 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2359 13:47:08.478778 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2360 13:47:08.479297 # # snd_pcm_hw_params: Invalid argument
2361 13:47:08.489792 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2362 13:47:08.490329 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2363 13:47:08.495420 # # snd_pcm_hw_params: Invalid argument
2364 13:47:08.500937 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2365 13:47:08.506603 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2366 13:47:08.512062 # # snd_pcm_hw_params: Invalid argument
2367 13:47:08.517614 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2368 13:47:08.518138 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2369 13:47:08.523122 # # snd_pcm_hw_params: Invalid argument
2370 13:47:08.528674 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2371 13:47:08.534210 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2372 13:47:08.534742 # # snd_pcm_hw_params: Invalid argument
2373 13:47:08.545257 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2374 13:47:08.545798 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2375 13:47:08.550816 # # snd_pcm_hw_params: Invalid argument
2376 13:47:08.556364 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2377 13:47:08.561926 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2378 13:47:08.562444 # # snd_pcm_hw_params: Invalid argument
2379 13:47:08.567556 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2380 13:47:08.573015 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2381 13:47:08.578567 # # snd_pcm_hw_params: Invalid argument
2382 13:47:08.584107 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2383 13:47:08.589649 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2384 13:47:08.590158 # # snd_pcm_hw_params: Invalid argument
2385 13:47:08.595229 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2386 13:47:08.600734 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2387 13:47:08.606329 # # snd_pcm_hw_params: Invalid argument
2388 13:47:08.611816 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2389 13:47:08.612354 ok 2 selftests: alsa: pcm-test
2390 13:47:08.617386 # timeout set to 45
2391 13:47:08.617945 # selftests: alsa: test-pcmtest-driver
2392 13:47:08.622986 # TAP version 13
2393 13:47:08.623556 # 1..5
2394 13:47:08.624050 # # Starting 5 tests from 1 test cases.
2395 13:47:08.628607 # # RUN pcmtest.playback ...
2396 13:47:08.634218 # # SKIP Can't read patterns. Probably, module isn't loaded
2397 13:47:08.639606 # # OK pcmtest.playback
2398 13:47:08.645125 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2399 13:47:08.650697 # # RUN pcmtest.capture ...
2400 13:47:08.656306 # # SKIP Can't read patterns. Probably, module isn't loaded
2401 13:47:08.656841 # # OK pcmtest.capture
2402 13:47:08.667326 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2403 13:47:08.667951 # # RUN pcmtest.ni_capture ...
2404 13:47:08.673114 # # SKIP Can't read patterns. Probably, module isn't loaded
2405 13:47:08.678486 # # OK pcmtest.ni_capture
2406 13:47:08.684015 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2407 13:47:08.689634 # # RUN pcmtest.ni_playback ...
2408 13:47:08.695058 # # SKIP Can't read patterns. Probably, module isn't loaded
2409 13:47:08.700645 # # OK pcmtest.ni_playback
2410 13:47:08.706160 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2411 13:47:08.711715 # # RUN pcmtest.reset_ioctl ...
2412 13:47:08.717254 # # SKIP Can't read patterns. Probably, module isn't loaded
2413 13:47:08.717801 # # OK pcmtest.reset_ioctl
2414 13:47:08.728347 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2415 13:47:08.728940 # # PASSED: 5 / 5 tests passed.
2416 13:47:08.733876 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2417 13:47:08.739418 ok 3 selftests: alsa: test-pcmtest-driver
2418 13:47:08.739941 # timeout set to 45
2419 13:47:08.744967 # selftests: alsa: utimer-test
2420 13:47:08.745483 # TAP version 13
2421 13:47:08.745938 # 1..2
2422 13:47:08.750612 # # Starting 2 tests from 2 test cases.
2423 13:47:08.756090 # # RUN global.wrong_timers_test ...
2424 13:47:08.756612 # # OK global.wrong_timers_test
2425 13:47:08.761612 # ok 1 global.wrong_timers_test
2426 13:47:08.762135 # # RUN timer_f.utimer ...
2427 13:47:08.772700 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2428 13:47:08.778299 # # utimer: Test terminated by assertion
2429 13:47:08.778881 # # FAIL timer_f.utimer
2430 13:47:08.783819 # not ok 2 timer_f.utimer
2431 13:47:08.784400 # # FAILED: 1 / 2 tests passed.
2432 13:47:08.789378 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2433 13:47:08.795091 not ok 4 selftests: alsa: utimer-test # exit=1
2434 13:47:09.347779 alsa_mixer-test_get_value_LCALTA_60 pass
2435 13:47:09.353215 alsa_mixer-test_name_LCALTA_60 pass
2436 13:47:09.353760 alsa_mixer-test_write_default_LCALTA_60 pass
2437 13:47:09.358772 alsa_mixer-test_write_valid_LCALTA_60 pass
2438 13:47:09.364309 alsa_mixer-test_write_invalid_LCALTA_60 pass
2439 13:47:09.369824 alsa_mixer-test_event_missing_LCALTA_60 pass
2440 13:47:09.370355 alsa_mixer-test_event_spurious_LCALTA_60 pass
2441 13:47:09.375395 alsa_mixer-test_get_value_LCALTA_59 pass
2442 13:47:09.380928 alsa_mixer-test_name_LCALTA_59 pass
2443 13:47:09.381465 alsa_mixer-test_write_default_LCALTA_59 pass
2444 13:47:09.386462 alsa_mixer-test_write_valid_LCALTA_59 pass
2445 13:47:09.392038 alsa_mixer-test_write_invalid_LCALTA_59 pass
2446 13:47:09.392570 alsa_mixer-test_event_missing_LCALTA_59 pass
2447 13:47:09.397651 alsa_mixer-test_event_spurious_LCALTA_59 pass
2448 13:47:09.403093 alsa_mixer-test_get_value_LCALTA_58 pass
2449 13:47:09.403610 alsa_mixer-test_name_LCALTA_58 pass
2450 13:47:09.408640 alsa_mixer-test_write_default_LCALTA_58 pass
2451 13:47:09.414210 alsa_mixer-test_write_valid_LCALTA_58 pass
2452 13:47:09.414753 alsa_mixer-test_write_invalid_LCALTA_58 pass
2453 13:47:09.419787 alsa_mixer-test_event_missing_LCALTA_58 pass
2454 13:47:09.425274 alsa_mixer-test_event_spurious_LCALTA_58 pass
2455 13:47:09.430843 alsa_mixer-test_get_value_LCALTA_57 pass
2456 13:47:09.431376 alsa_mixer-test_name_LCALTA_57 pass
2457 13:47:09.436481 alsa_mixer-test_write_default_LCALTA_57 pass
2458 13:47:09.442020 alsa_mixer-test_write_valid_LCALTA_57 pass
2459 13:47:09.442550 alsa_mixer-test_write_invalid_LCALTA_57 pass
2460 13:47:09.447529 alsa_mixer-test_event_missing_LCALTA_57 pass
2461 13:47:09.453114 alsa_mixer-test_event_spurious_LCALTA_57 pass
2462 13:47:09.453646 alsa_mixer-test_get_value_LCALTA_56 pass
2463 13:47:09.458761 alsa_mixer-test_name_LCALTA_56 pass
2464 13:47:09.464301 alsa_mixer-test_write_default_LCALTA_56 pass
2465 13:47:09.464842 alsa_mixer-test_write_valid_LCALTA_56 pass
2466 13:47:09.469822 alsa_mixer-test_write_invalid_LCALTA_56 pass
2467 13:47:09.475261 alsa_mixer-test_event_missing_LCALTA_56 pass
2468 13:47:09.480849 alsa_mixer-test_event_spurious_LCALTA_56 pass
2469 13:47:09.481366 alsa_mixer-test_get_value_LCALTA_55 pass
2470 13:47:09.486397 alsa_mixer-test_name_LCALTA_55 pass
2471 13:47:09.491927 alsa_mixer-test_write_default_LCALTA_55 pass
2472 13:47:09.492482 alsa_mixer-test_write_valid_LCALTA_55 pass
2473 13:47:09.497492 alsa_mixer-test_write_invalid_LCALTA_55 pass
2474 13:47:09.503038 alsa_mixer-test_event_missing_LCALTA_55 pass
2475 13:47:09.503555 alsa_mixer-test_event_spurious_LCALTA_55 pass
2476 13:47:09.508578 alsa_mixer-test_get_value_LCALTA_54 pass
2477 13:47:09.514121 alsa_mixer-test_name_LCALTA_54 pass
2478 13:47:09.514641 alsa_mixer-test_write_default_LCALTA_54 pass
2479 13:47:09.519766 alsa_mixer-test_write_valid_LCALTA_54 pass
2480 13:47:09.525212 alsa_mixer-test_write_invalid_LCALTA_54 pass
2481 13:47:09.525737 alsa_mixer-test_event_missing_LCALTA_54 pass
2482 13:47:09.530817 alsa_mixer-test_event_spurious_LCALTA_54 pass
2483 13:47:09.536304 alsa_mixer-test_get_value_LCALTA_53 pass
2484 13:47:09.536820 alsa_mixer-test_name_LCALTA_53 pass
2485 13:47:09.541856 alsa_mixer-test_write_default_LCALTA_53 pass
2486 13:47:09.547407 alsa_mixer-test_write_valid_LCALTA_53 pass
2487 13:47:09.552927 alsa_mixer-test_write_invalid_LCALTA_53 pass
2488 13:47:09.553450 alsa_mixer-test_event_missing_LCALTA_53 pass
2489 13:47:09.558499 alsa_mixer-test_event_spurious_LCALTA_53 pass
2490 13:47:09.564101 alsa_mixer-test_get_value_LCALTA_52 pass
2491 13:47:09.564644 alsa_mixer-test_name_LCALTA_52 pass
2492 13:47:09.569588 alsa_mixer-test_write_default_LCALTA_52 pass
2493 13:47:09.575139 alsa_mixer-test_write_valid_LCALTA_52 pass
2494 13:47:09.575658 alsa_mixer-test_write_invalid_LCALTA_52 pass
2495 13:47:09.580729 alsa_mixer-test_event_missing_LCALTA_52 pass
2496 13:47:09.586258 alsa_mixer-test_event_spurious_LCALTA_52 pass
2497 13:47:09.586806 alsa_mixer-test_get_value_LCALTA_51 pass
2498 13:47:09.591785 alsa_mixer-test_name_LCALTA_51 pass
2499 13:47:09.597354 alsa_mixer-test_write_default_LCALTA_51 pass
2500 13:47:09.597897 alsa_mixer-test_write_valid_LCALTA_51 pass
2501 13:47:09.602885 alsa_mixer-test_write_invalid_LCALTA_51 pass
2502 13:47:09.608417 alsa_mixer-test_event_missing_LCALTA_51 pass
2503 13:47:09.613957 alsa_mixer-test_event_spurious_LCALTA_51 pass
2504 13:47:09.614470 alsa_mixer-test_get_value_LCALTA_50 pass
2505 13:47:09.619496 alsa_mixer-test_name_LCALTA_50 pass
2506 13:47:09.625040 alsa_mixer-test_write_default_LCALTA_50 pass
2507 13:47:09.625557 alsa_mixer-test_write_valid_LCALTA_50 pass
2508 13:47:09.630629 alsa_mixer-test_write_invalid_LCALTA_50 pass
2509 13:47:09.636159 alsa_mixer-test_event_missing_LCALTA_50 pass
2510 13:47:09.636685 alsa_mixer-test_event_spurious_LCALTA_50 pass
2511 13:47:09.641771 alsa_mixer-test_get_value_LCALTA_49 pass
2512 13:47:09.647214 alsa_mixer-test_name_LCALTA_49 pass
2513 13:47:09.647732 alsa_mixer-test_write_default_LCALTA_49 pass
2514 13:47:09.652804 alsa_mixer-test_write_valid_LCALTA_49 pass
2515 13:47:09.658328 alsa_mixer-test_write_invalid_LCALTA_49 pass
2516 13:47:09.663913 alsa_mixer-test_event_missing_LCALTA_49 pass
2517 13:47:09.664476 alsa_mixer-test_event_spurious_LCALTA_49 pass
2518 13:47:09.669419 alsa_mixer-test_get_value_LCALTA_48 pass
2519 13:47:09.669931 alsa_mixer-test_name_LCALTA_48 pass
2520 13:47:09.674994 alsa_mixer-test_write_default_LCALTA_48 pass
2521 13:47:09.680480 alsa_mixer-test_write_valid_LCALTA_48 pass
2522 13:47:09.686084 alsa_mixer-test_write_invalid_LCALTA_48 pass
2523 13:47:09.686598 alsa_mixer-test_event_missing_LCALTA_48 pass
2524 13:47:09.691608 alsa_mixer-test_event_spurious_LCALTA_48 pass
2525 13:47:09.697162 alsa_mixer-test_get_value_LCALTA_47 pass
2526 13:47:09.697682 alsa_mixer-test_name_LCALTA_47 pass
2527 13:47:09.702774 alsa_mixer-test_write_default_LCALTA_47 pass
2528 13:47:09.708276 alsa_mixer-test_write_valid_LCALTA_47 pass
2529 13:47:09.708797 alsa_mixer-test_write_invalid_LCALTA_47 pass
2530 13:47:09.713821 alsa_mixer-test_event_missing_LCALTA_47 pass
2531 13:47:09.719353 alsa_mixer-test_event_spurious_LCALTA_47 pass
2532 13:47:09.724894 alsa_mixer-test_get_value_LCALTA_46 pass
2533 13:47:09.725430 alsa_mixer-test_name_LCALTA_46 pass
2534 13:47:09.730416 alsa_mixer-test_write_default_LCALTA_46 pass
2535 13:47:09.736011 alsa_mixer-test_write_valid_LCALTA_46 pass
2536 13:47:09.736559 alsa_mixer-test_write_invalid_LCALTA_46 pass
2537 13:47:09.741588 alsa_mixer-test_event_missing_LCALTA_46 pass
2538 13:47:09.747084 alsa_mixer-test_event_spurious_LCALTA_46 pass
2539 13:47:09.747607 alsa_mixer-test_get_value_LCALTA_45 pass
2540 13:47:09.752629 alsa_mixer-test_name_LCALTA_45 pass
2541 13:47:09.758196 alsa_mixer-test_write_default_LCALTA_45 pass
2542 13:47:09.758719 alsa_mixer-test_write_valid_LCALTA_45 pass
2543 13:47:09.763799 alsa_mixer-test_write_invalid_LCALTA_45 pass
2544 13:47:09.769298 alsa_mixer-test_event_missing_LCALTA_45 pass
2545 13:47:09.769825 alsa_mixer-test_event_spurious_LCALTA_45 pass
2546 13:47:09.774840 alsa_mixer-test_get_value_LCALTA_44 pass
2547 13:47:09.780380 alsa_mixer-test_name_LCALTA_44 pass
2548 13:47:09.780898 alsa_mixer-test_write_default_LCALTA_44 pass
2549 13:47:09.785923 alsa_mixer-test_write_valid_LCALTA_44 pass
2550 13:47:09.791427 alsa_mixer-test_write_invalid_LCALTA_44 pass
2551 13:47:09.796986 alsa_mixer-test_event_missing_LCALTA_44 pass
2552 13:47:09.797505 alsa_mixer-test_event_spurious_LCALTA_44 pass
2553 13:47:09.802569 alsa_mixer-test_get_value_LCALTA_43 pass
2554 13:47:09.808144 alsa_mixer-test_name_LCALTA_43 pass
2555 13:47:09.808672 alsa_mixer-test_write_default_LCALTA_43 pass
2556 13:47:09.813670 alsa_mixer-test_write_valid_LCALTA_43 pass
2557 13:47:09.819204 alsa_mixer-test_write_invalid_LCALTA_43 pass
2558 13:47:09.819724 alsa_mixer-test_event_missing_LCALTA_43 pass
2559 13:47:09.824836 alsa_mixer-test_event_spurious_LCALTA_43 pass
2560 13:47:09.830291 alsa_mixer-test_get_value_LCALTA_42 pass
2561 13:47:09.830819 alsa_mixer-test_name_LCALTA_42 pass
2562 13:47:09.835831 alsa_mixer-test_write_default_LCALTA_42 pass
2563 13:47:09.841416 alsa_mixer-test_write_valid_LCALTA_42 pass
2564 13:47:09.841955 alsa_mixer-test_write_invalid_LCALTA_42 pass
2565 13:47:09.846946 alsa_mixer-test_event_missing_LCALTA_42 pass
2566 13:47:09.852543 alsa_mixer-test_event_spurious_LCALTA_42 pass
2567 13:47:09.858049 alsa_mixer-test_get_value_LCALTA_41 pass
2568 13:47:09.858575 alsa_mixer-test_name_LCALTA_41 pass
2569 13:47:09.863622 alsa_mixer-test_write_default_LCALTA_41 pass
2570 13:47:09.869138 alsa_mixer-test_write_valid_LCALTA_41 pass
2571 13:47:09.869663 alsa_mixer-test_write_invalid_LCALTA_41 pass
2572 13:47:09.874852 alsa_mixer-test_event_missing_LCALTA_41 pass
2573 13:47:09.880262 alsa_mixer-test_event_spurious_LCALTA_41 pass
2574 13:47:09.880791 alsa_mixer-test_get_value_LCALTA_40 pass
2575 13:47:09.885854 alsa_mixer-test_name_LCALTA_40 pass
2576 13:47:09.891315 alsa_mixer-test_write_default_LCALTA_40 pass
2577 13:47:09.891831 alsa_mixer-test_write_valid_LCALTA_40 pass
2578 13:47:09.896870 alsa_mixer-test_write_invalid_LCALTA_40 pass
2579 13:47:09.902415 alsa_mixer-test_event_missing_LCALTA_40 pass
2580 13:47:09.907958 alsa_mixer-test_event_spurious_LCALTA_40 pass
2581 13:47:09.908508 alsa_mixer-test_get_value_LCALTA_39 pass
2582 13:47:09.913595 alsa_mixer-test_name_LCALTA_39 pass
2583 13:47:09.919050 alsa_mixer-test_write_default_LCALTA_39 pass
2584 13:47:09.919571 alsa_mixer-test_write_valid_LCALTA_39 pass
2585 13:47:09.924619 alsa_mixer-test_write_invalid_LCALTA_39 pass
2586 13:47:09.930107 alsa_mixer-test_event_missing_LCALTA_39 pass
2587 13:47:09.930623 alsa_mixer-test_event_spurious_LCALTA_39 pass
2588 13:47:09.935774 alsa_mixer-test_get_value_LCALTA_38 pass
2589 13:47:09.941219 alsa_mixer-test_name_LCALTA_38 pass
2590 13:47:09.941729 alsa_mixer-test_write_default_LCALTA_38 pass
2591 13:47:09.946814 alsa_mixer-test_write_valid_LCALTA_38 pass
2592 13:47:09.952288 alsa_mixer-test_write_invalid_LCALTA_38 pass
2593 13:47:09.952796 alsa_mixer-test_event_missing_LCALTA_38 pass
2594 13:47:09.957838 alsa_mixer-test_event_spurious_LCALTA_38 pass
2595 13:47:09.963384 alsa_mixer-test_get_value_LCALTA_37 pass
2596 13:47:09.963886 alsa_mixer-test_name_LCALTA_37 pass
2597 13:47:09.968914 alsa_mixer-test_write_default_LCALTA_37 pass
2598 13:47:09.974555 alsa_mixer-test_write_valid_LCALTA_37 pass
2599 13:47:09.980087 alsa_mixer-test_write_invalid_LCALTA_37 pass
2600 13:47:09.980607 alsa_mixer-test_event_missing_LCALTA_37 pass
2601 13:47:09.985668 alsa_mixer-test_event_spurious_LCALTA_37 pass
2602 13:47:09.991217 alsa_mixer-test_get_value_LCALTA_36 pass
2603 13:47:09.991775 alsa_mixer-test_name_LCALTA_36 pass
2604 13:47:09.996886 alsa_mixer-test_write_default_LCALTA_36 pass
2605 13:47:10.002291 alsa_mixer-test_write_valid_LCALTA_36 pass
2606 13:47:10.002848 alsa_mixer-test_write_invalid_LCALTA_36 pass
2607 13:47:10.007885 alsa_mixer-test_event_missing_LCALTA_36 pass
2608 13:47:10.013369 alsa_mixer-test_event_spurious_LCALTA_36 pass
2609 13:47:10.013943 alsa_mixer-test_get_value_LCALTA_35 pass
2610 13:47:10.018901 alsa_mixer-test_name_LCALTA_35 pass
2611 13:47:10.024486 alsa_mixer-test_write_default_LCALTA_35 pass
2612 13:47:10.025046 alsa_mixer-test_write_valid_LCALTA_35 pass
2613 13:47:10.029992 alsa_mixer-test_write_invalid_LCALTA_35 pass
2614 13:47:10.035589 alsa_mixer-test_event_missing_LCALTA_35 pass
2615 13:47:10.041049 alsa_mixer-test_event_spurious_LCALTA_35 pass
2616 13:47:10.041562 alsa_mixer-test_get_value_LCALTA_34 pass
2617 13:47:10.046631 alsa_mixer-test_name_LCALTA_34 pass
2618 13:47:10.052159 alsa_mixer-test_write_default_LCALTA_34 pass
2619 13:47:10.052671 alsa_mixer-test_write_valid_LCALTA_34 pass
2620 13:47:10.057830 alsa_mixer-test_write_invalid_LCALTA_34 pass
2621 13:47:10.063257 alsa_mixer-test_event_missing_LCALTA_34 pass
2622 13:47:10.063774 alsa_mixer-test_event_spurious_LCALTA_34 pass
2623 13:47:10.068833 alsa_mixer-test_get_value_LCALTA_33 pass
2624 13:47:10.074317 alsa_mixer-test_name_LCALTA_33 pass
2625 13:47:10.074828 alsa_mixer-test_write_default_LCALTA_33 pass
2626 13:47:10.079896 alsa_mixer-test_write_valid_LCALTA_33 pass
2627 13:47:10.085392 alsa_mixer-test_write_invalid_LCALTA_33 pass
2628 13:47:10.090972 alsa_mixer-test_event_missing_LCALTA_33 pass
2629 13:47:10.091488 alsa_mixer-test_event_spurious_LCALTA_33 pass
2630 13:47:10.096587 alsa_mixer-test_get_value_LCALTA_32 pass
2631 13:47:10.097110 alsa_mixer-test_name_LCALTA_32 pass
2632 13:47:10.102092 alsa_mixer-test_write_default_LCALTA_32 pass
2633 13:47:10.107634 alsa_mixer-test_write_valid_LCALTA_32 pass
2634 13:47:10.113174 alsa_mixer-test_write_invalid_LCALTA_32 pass
2635 13:47:10.113690 alsa_mixer-test_event_missing_LCALTA_32 pass
2636 13:47:10.118841 alsa_mixer-test_event_spurious_LCALTA_32 pass
2637 13:47:10.124270 alsa_mixer-test_get_value_LCALTA_31 pass
2638 13:47:10.124783 alsa_mixer-test_name_LCALTA_31 pass
2639 13:47:10.129851 alsa_mixer-test_write_default_LCALTA_31 pass
2640 13:47:10.135359 alsa_mixer-test_write_valid_LCALTA_31 pass
2641 13:47:10.135874 alsa_mixer-test_write_invalid_LCALTA_31 pass
2642 13:47:10.140920 alsa_mixer-test_event_missing_LCALTA_31 pass
2643 13:47:10.146506 alsa_mixer-test_event_spurious_LCALTA_31 pass
2644 13:47:10.152052 alsa_mixer-test_get_value_LCALTA_30 pass
2645 13:47:10.152590 alsa_mixer-test_name_LCALTA_30 pass
2646 13:47:10.157619 alsa_mixer-test_write_default_LCALTA_30 pass
2647 13:47:10.163111 alsa_mixer-test_write_valid_LCALTA_30 pass
2648 13:47:10.163637 alsa_mixer-test_write_invalid_LCALTA_30 pass
2649 13:47:10.168658 alsa_mixer-test_event_missing_LCALTA_30 pass
2650 13:47:10.174211 alsa_mixer-test_event_spurious_LCALTA_30 pass
2651 13:47:10.174748 alsa_mixer-test_get_value_LCALTA_29 pass
2652 13:47:10.179853 alsa_mixer-test_name_LCALTA_29 pass
2653 13:47:10.185255 alsa_mixer-test_write_default_LCALTA_29 pass
2654 13:47:10.185762 alsa_mixer-test_write_valid_LCALTA_29 pass
2655 13:47:10.190842 alsa_mixer-test_write_invalid_LCALTA_29 pass
2656 13:47:10.196354 alsa_mixer-test_event_missing_LCALTA_29 pass
2657 13:47:10.196863 alsa_mixer-test_event_spurious_LCALTA_29 pass
2658 13:47:10.201894 alsa_mixer-test_get_value_LCALTA_28 pass
2659 13:47:10.207460 alsa_mixer-test_name_LCALTA_28 pass
2660 13:47:10.207970 alsa_mixer-test_write_default_LCALTA_28 pass
2661 13:47:10.213007 alsa_mixer-test_write_valid_LCALTA_28 pass
2662 13:47:10.218592 alsa_mixer-test_write_invalid_LCALTA_28 pass
2663 13:47:10.224103 alsa_mixer-test_event_missing_LCALTA_28 pass
2664 13:47:10.224608 alsa_mixer-test_event_spurious_LCALTA_28 pass
2665 13:47:10.229638 alsa_mixer-test_get_value_LCALTA_27 pass
2666 13:47:10.235198 alsa_mixer-test_name_LCALTA_27 pass
2667 13:47:10.235701 alsa_mixer-test_write_default_LCALTA_27 pass
2668 13:47:10.240847 alsa_mixer-test_write_valid_LCALTA_27 pass
2669 13:47:10.246267 alsa_mixer-test_write_invalid_LCALTA_27 pass
2670 13:47:10.246774 alsa_mixer-test_event_missing_LCALTA_27 pass
2671 13:47:10.251843 alsa_mixer-test_event_spurious_LCALTA_27 pass
2672 13:47:10.257382 alsa_mixer-test_get_value_LCALTA_26 pass
2673 13:47:10.257893 alsa_mixer-test_name_LCALTA_26 pass
2674 13:47:10.262906 alsa_mixer-test_write_default_LCALTA_26 skip
2675 13:47:10.268491 alsa_mixer-test_write_valid_LCALTA_26 skip
2676 13:47:10.268993 alsa_mixer-test_write_invalid_LCALTA_26 skip
2677 13:47:10.274004 alsa_mixer-test_event_missing_LCALTA_26 pass
2678 13:47:10.279618 alsa_mixer-test_event_spurious_LCALTA_26 pass
2679 13:47:10.285095 alsa_mixer-test_get_value_LCALTA_25 pass
2680 13:47:10.285605 alsa_mixer-test_name_LCALTA_25 pass
2681 13:47:10.290663 alsa_mixer-test_write_default_LCALTA_25 pass
2682 13:47:10.296283 alsa_mixer-test_write_valid_LCALTA_25 skip
2683 13:47:10.296807 alsa_mixer-test_write_invalid_LCALTA_25 skip
2684 13:47:10.301869 alsa_mixer-test_event_missing_LCALTA_25 pass
2685 13:47:10.307290 alsa_mixer-test_event_spurious_LCALTA_25 pass
2686 13:47:10.307802 alsa_mixer-test_get_value_LCALTA_24 pass
2687 13:47:10.312861 alsa_mixer-test_name_LCALTA_24 pass
2688 13:47:10.318381 alsa_mixer-test_write_default_LCALTA_24 skip
2689 13:47:10.318887 alsa_mixer-test_write_valid_LCALTA_24 skip
2690 13:47:10.323940 alsa_mixer-test_write_invalid_LCALTA_24 skip
2691 13:47:10.329507 alsa_mixer-test_event_missing_LCALTA_24 pass
2692 13:47:10.335030 alsa_mixer-test_event_spurious_LCALTA_24 pass
2693 13:47:10.335543 alsa_mixer-test_get_value_LCALTA_23 pass
2694 13:47:10.340620 alsa_mixer-test_name_LCALTA_23 pass
2695 13:47:10.346106 alsa_mixer-test_write_default_LCALTA_23 skip
2696 13:47:10.346617 alsa_mixer-test_write_valid_LCALTA_23 skip
2697 13:47:10.351684 alsa_mixer-test_write_invalid_LCALTA_23 skip
2698 13:47:10.357230 alsa_mixer-test_event_missing_LCALTA_23 pass
2699 13:47:10.357773 alsa_mixer-test_event_spurious_LCALTA_23 pass
2700 13:47:10.362895 alsa_mixer-test_get_value_LCALTA_22 pass
2701 13:47:10.368319 alsa_mixer-test_name_LCALTA_22 pass
2702 13:47:10.368833 alsa_mixer-test_write_default_LCALTA_22 pass
2703 13:47:10.373889 alsa_mixer-test_write_valid_LCALTA_22 pass
2704 13:47:10.379418 alsa_mixer-test_write_invalid_LCALTA_22 pass
2705 13:47:10.379934 alsa_mixer-test_event_missing_LCALTA_22 pass
2706 13:47:10.384964 alsa_mixer-test_event_spurious_LCALTA_22 pass
2707 13:47:10.390517 alsa_mixer-test_get_value_LCALTA_21 pass
2708 13:47:10.391043 alsa_mixer-test_name_LCALTA_21 pass
2709 13:47:10.396082 alsa_mixer-test_write_default_LCALTA_21 pass
2710 13:47:10.401615 alsa_mixer-test_write_valid_LCALTA_21 pass
2711 13:47:10.407131 alsa_mixer-test_write_invalid_LCALTA_21 pass
2712 13:47:10.407636 alsa_mixer-test_event_missing_LCALTA_21 pass
2713 13:47:10.412680 alsa_mixer-test_event_spurious_LCALTA_21 pass
2714 13:47:10.418225 alsa_mixer-test_get_value_LCALTA_20 pass
2715 13:47:10.418732 alsa_mixer-test_name_LCALTA_20 pass
2716 13:47:10.423880 alsa_mixer-test_write_default_LCALTA_20 pass
2717 13:47:10.429334 alsa_mixer-test_write_valid_LCALTA_20 pass
2718 13:47:10.429844 alsa_mixer-test_write_invalid_LCALTA_20 pass
2719 13:47:10.434873 alsa_mixer-test_event_missing_LCALTA_20 pass
2720 13:47:10.440411 alsa_mixer-test_event_spurious_LCALTA_20 pass
2721 13:47:10.440929 alsa_mixer-test_get_value_LCALTA_19 pass
2722 13:47:10.445965 alsa_mixer-test_name_LCALTA_19 pass
2723 13:47:10.451482 alsa_mixer-test_write_default_LCALTA_19 pass
2724 13:47:10.452026 alsa_mixer-test_write_valid_LCALTA_19 pass
2725 13:47:10.457039 alsa_mixer-test_write_invalid_LCALTA_19 pass
2726 13:47:10.462610 alsa_mixer-test_event_missing_LCALTA_19 pass
2727 13:47:10.468182 alsa_mixer-test_event_spurious_LCALTA_19 pass
2728 13:47:10.468702 alsa_mixer-test_get_value_LCALTA_18 pass
2729 13:47:10.473704 alsa_mixer-test_name_LCALTA_18 pass
2730 13:47:10.479231 alsa_mixer-test_write_default_LCALTA_18 pass
2731 13:47:10.479763 alsa_mixer-test_write_valid_LCALTA_18 pass
2732 13:47:10.484871 alsa_mixer-test_write_invalid_LCALTA_18 pass
2733 13:47:10.490295 alsa_mixer-test_event_missing_LCALTA_18 pass
2734 13:47:10.490804 alsa_mixer-test_event_spurious_LCALTA_18 pass
2735 13:47:10.495853 alsa_mixer-test_get_value_LCALTA_17 pass
2736 13:47:10.501447 alsa_mixer-test_name_LCALTA_17 pass
2737 13:47:10.501967 alsa_mixer-test_write_default_LCALTA_17 pass
2738 13:47:10.506977 alsa_mixer-test_write_valid_LCALTA_17 pass
2739 13:47:10.512511 alsa_mixer-test_write_invalid_LCALTA_17 pass
2740 13:47:10.518076 alsa_mixer-test_event_missing_LCALTA_17 pass
2741 13:47:10.518586 alsa_mixer-test_event_spurious_LCALTA_17 pass
2742 13:47:10.523641 alsa_mixer-test_get_value_LCALTA_16 pass
2743 13:47:10.524189 alsa_mixer-test_name_LCALTA_16 pass
2744 13:47:10.529176 alsa_mixer-test_write_default_LCALTA_16 pass
2745 13:47:10.534699 alsa_mixer-test_write_valid_LCALTA_16 pass
2746 13:47:10.540279 alsa_mixer-test_write_invalid_LCALTA_16 pass
2747 13:47:10.540788 alsa_mixer-test_event_missing_LCALTA_16 pass
2748 13:47:10.545896 alsa_mixer-test_event_spurious_LCALTA_16 pass
2749 13:47:10.551347 alsa_mixer-test_get_value_LCALTA_15 pass
2750 13:47:10.551858 alsa_mixer-test_name_LCALTA_15 pass
2751 13:47:10.556900 alsa_mixer-test_write_default_LCALTA_15 pass
2752 13:47:10.562449 alsa_mixer-test_write_valid_LCALTA_15 pass
2753 13:47:10.562958 alsa_mixer-test_write_invalid_LCALTA_15 pass
2754 13:47:10.568023 alsa_mixer-test_event_missing_LCALTA_15 pass
2755 13:47:10.573551 alsa_mixer-test_event_spurious_LCALTA_15 pass
2756 13:47:10.579049 alsa_mixer-test_get_value_LCALTA_14 pass
2757 13:47:10.579559 alsa_mixer-test_name_LCALTA_14 pass
2758 13:47:10.584616 alsa_mixer-test_write_default_LCALTA_14 pass
2759 13:47:10.590163 alsa_mixer-test_write_valid_LCALTA_14 pass
2760 13:47:10.590673 alsa_mixer-test_write_invalid_LCALTA_14 pass
2761 13:47:10.595754 alsa_mixer-test_event_missing_LCALTA_14 pass
2762 13:47:10.601276 alsa_mixer-test_event_spurious_LCALTA_14 pass
2763 13:47:10.601781 alsa_mixer-test_get_value_LCALTA_13 pass
2764 13:47:10.606907 alsa_mixer-test_name_LCALTA_13 pass
2765 13:47:10.612359 alsa_mixer-test_write_default_LCALTA_13 pass
2766 13:47:10.612874 alsa_mixer-test_write_valid_LCALTA_13 pass
2767 13:47:10.617963 alsa_mixer-test_write_invalid_LCALTA_13 pass
2768 13:47:10.623456 alsa_mixer-test_event_missing_LCALTA_13 pass
2769 13:47:10.623963 alsa_mixer-test_event_spurious_LCALTA_13 pass
2770 13:47:10.629018 alsa_mixer-test_get_value_LCALTA_12 pass
2771 13:47:10.634541 alsa_mixer-test_name_LCALTA_12 pass
2772 13:47:10.635048 alsa_mixer-test_write_default_LCALTA_12 pass
2773 13:47:10.640125 alsa_mixer-test_write_valid_LCALTA_12 pass
2774 13:47:10.645645 alsa_mixer-test_write_invalid_LCALTA_12 pass
2775 13:47:10.651190 alsa_mixer-test_event_missing_LCALTA_12 pass
2776 13:47:10.651720 alsa_mixer-test_event_spurious_LCALTA_12 pass
2777 13:47:10.656749 alsa_mixer-test_get_value_LCALTA_11 pass
2778 13:47:10.662282 alsa_mixer-test_name_LCALTA_11 pass
2779 13:47:10.662796 alsa_mixer-test_write_default_LCALTA_11 pass
2780 13:47:10.667932 alsa_mixer-test_write_valid_LCALTA_11 pass
2781 13:47:10.673379 alsa_mixer-test_write_invalid_LCALTA_11 pass
2782 13:47:10.673887 alsa_mixer-test_event_missing_LCALTA_11 pass
2783 13:47:10.678991 alsa_mixer-test_event_spurious_LCALTA_11 pass
2784 13:47:10.684496 alsa_mixer-test_get_value_LCALTA_10 pass
2785 13:47:10.685021 alsa_mixer-test_name_LCALTA_10 pass
2786 13:47:10.690085 alsa_mixer-test_write_default_LCALTA_10 pass
2787 13:47:10.695587 alsa_mixer-test_write_valid_LCALTA_10 pass
2788 13:47:10.696171 alsa_mixer-test_write_invalid_LCALTA_10 pass
2789 13:47:10.701145 alsa_mixer-test_event_missing_LCALTA_10 pass
2790 13:47:10.706720 alsa_mixer-test_event_spurious_LCALTA_10 pass
2791 13:47:10.712312 alsa_mixer-test_get_value_LCALTA_9 pass
2792 13:47:10.712882 alsa_mixer-test_name_LCALTA_9 pass
2793 13:47:10.717824 alsa_mixer-test_write_default_LCALTA_9 pass
2794 13:47:10.723349 alsa_mixer-test_write_valid_LCALTA_9 pass
2795 13:47:10.723920 alsa_mixer-test_write_invalid_LCALTA_9 pass
2796 13:47:10.729007 alsa_mixer-test_event_missing_LCALTA_9 pass
2797 13:47:10.734457 alsa_mixer-test_event_spurious_LCALTA_9 pass
2798 13:47:10.735035 alsa_mixer-test_get_value_LCALTA_8 pass
2799 13:47:10.740060 alsa_mixer-test_name_LCALTA_8 pass
2800 13:47:10.745566 alsa_mixer-test_write_default_LCALTA_8 pass
2801 13:47:10.746148 alsa_mixer-test_write_valid_LCALTA_8 pass
2802 13:47:10.751134 alsa_mixer-test_write_invalid_LCALTA_8 pass
2803 13:47:10.756662 alsa_mixer-test_event_missing_LCALTA_8 pass
2804 13:47:10.757237 alsa_mixer-test_event_spurious_LCALTA_8 pass
2805 13:47:10.762185 alsa_mixer-test_get_value_LCALTA_7 pass
2806 13:47:10.767726 alsa_mixer-test_name_LCALTA_7 pass
2807 13:47:10.768311 alsa_mixer-test_write_default_LCALTA_7 pass
2808 13:47:10.773243 alsa_mixer-test_write_valid_LCALTA_7 pass
2809 13:47:10.778781 alsa_mixer-test_write_invalid_LCALTA_7 pass
2810 13:47:10.779293 alsa_mixer-test_event_missing_LCALTA_7 pass
2811 13:47:10.784317 alsa_mixer-test_event_spurious_LCALTA_7 pass
2812 13:47:10.789937 alsa_mixer-test_get_value_LCALTA_6 pass
2813 13:47:10.790448 alsa_mixer-test_name_LCALTA_6 pass
2814 13:47:10.795426 alsa_mixer-test_write_default_LCALTA_6 pass
2815 13:47:10.800974 alsa_mixer-test_write_valid_LCALTA_6 pass
2816 13:47:10.801485 alsa_mixer-test_write_invalid_LCALTA_6 pass
2817 13:47:10.806485 alsa_mixer-test_event_missing_LCALTA_6 pass
2818 13:47:10.812100 alsa_mixer-test_event_spurious_LCALTA_6 pass
2819 13:47:10.812614 alsa_mixer-test_get_value_LCALTA_5 pass
2820 13:47:10.817689 alsa_mixer-test_name_LCALTA_5 pass
2821 13:47:10.823139 alsa_mixer-test_write_default_LCALTA_5 pass
2822 13:47:10.823648 alsa_mixer-test_write_valid_LCALTA_5 pass
2823 13:47:10.828692 alsa_mixer-test_write_invalid_LCALTA_5 pass
2824 13:47:10.834227 alsa_mixer-test_event_missing_LCALTA_5 pass
2825 13:47:10.834737 alsa_mixer-test_event_spurious_LCALTA_5 pass
2826 13:47:10.839801 alsa_mixer-test_get_value_LCALTA_4 pass
2827 13:47:10.845387 alsa_mixer-test_name_LCALTA_4 pass
2828 13:47:10.845932 alsa_mixer-test_write_default_LCALTA_4 pass
2829 13:47:10.850968 alsa_mixer-test_write_valid_LCALTA_4 pass
2830 13:47:10.856415 alsa_mixer-test_write_invalid_LCALTA_4 pass
2831 13:47:10.856929 alsa_mixer-test_event_missing_LCALTA_4 pass
2832 13:47:10.861994 alsa_mixer-test_event_spurious_LCALTA_4 pass
2833 13:47:10.867559 alsa_mixer-test_get_value_LCALTA_3 pass
2834 13:47:10.868137 alsa_mixer-test_name_LCALTA_3 pass
2835 13:47:10.873133 alsa_mixer-test_write_default_LCALTA_3 pass
2836 13:47:10.878684 alsa_mixer-test_write_valid_LCALTA_3 pass
2837 13:47:10.879204 alsa_mixer-test_write_invalid_LCALTA_3 pass
2838 13:47:10.884127 alsa_mixer-test_event_missing_LCALTA_3 pass
2839 13:47:10.889744 alsa_mixer-test_event_spurious_LCALTA_3 pass
2840 13:47:10.890260 alsa_mixer-test_get_value_LCALTA_2 pass
2841 13:47:10.895227 alsa_mixer-test_name_LCALTA_2 pass
2842 13:47:10.900773 alsa_mixer-test_write_default_LCALTA_2 pass
2843 13:47:10.901282 alsa_mixer-test_write_valid_LCALTA_2 pass
2844 13:47:10.906314 alsa_mixer-test_write_invalid_LCALTA_2 pass
2845 13:47:10.911923 alsa_mixer-test_event_missing_LCALTA_2 pass
2846 13:47:10.917402 alsa_mixer-test_event_spurious_LCALTA_2 pass
2847 13:47:10.917911 alsa_mixer-test_get_value_LCALTA_1 pass
2848 13:47:10.922981 alsa_mixer-test_name_LCALTA_1 pass
2849 13:47:10.923485 alsa_mixer-test_write_default_LCALTA_1 pass
2850 13:47:10.928500 alsa_mixer-test_write_valid_LCALTA_1 pass
2851 13:47:10.934036 alsa_mixer-test_write_invalid_LCALTA_1 pass
2852 13:47:10.939587 alsa_mixer-test_event_missing_LCALTA_1 pass
2853 13:47:10.940116 alsa_mixer-test_event_spurious_LCALTA_1 pass
2854 13:47:10.945128 alsa_mixer-test_get_value_LCALTA_0 pass
2855 13:47:10.945630 alsa_mixer-test_name_LCALTA_0 pass
2856 13:47:10.950758 alsa_mixer-test_write_default_LCALTA_0 pass
2857 13:47:10.956250 alsa_mixer-test_write_valid_LCALTA_0 pass
2858 13:47:10.961800 alsa_mixer-test_write_invalid_LCALTA_0 pass
2859 13:47:10.962306 alsa_mixer-test_event_missing_LCALTA_0 pass
2860 13:47:10.967352 alsa_mixer-test_event_spurious_LCALTA_0 pass
2861 13:47:10.967854 alsa_mixer-test pass
2862 13:47:10.972980 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2863 13:47:10.978458 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2864 13:47:10.984025 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2865 13:47:10.989519 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2866 13:47:10.990028 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2867 13:47:10.995095 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2868 13:47:11.000723 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2869 13:47:11.006167 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2870 13:47:11.011766 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2871 13:47:11.017245 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2872 13:47:11.017753 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2873 13:47:11.022830 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2874 13:47:11.028363 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2875 13:47:11.033981 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2876 13:47:11.039485 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2877 13:47:11.045034 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2878 13:47:11.045536 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2879 13:47:11.050552 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2880 13:47:11.056187 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2881 13:47:11.061715 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2882 13:47:11.067116 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2883 13:47:11.072670 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2884 13:47:11.073159 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2885 13:47:11.078209 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2886 13:47:11.083907 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2887 13:47:11.089205 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2888 13:47:11.094832 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2889 13:47:11.100342 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2890 13:47:11.100845 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2891 13:47:11.105866 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2892 13:47:11.111383 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2893 13:47:11.116949 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2894 13:47:11.122579 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2895 13:47:11.128092 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2896 13:47:11.133615 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2897 13:47:11.134097 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2898 13:47:11.139151 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2899 13:47:11.144813 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2900 13:47:11.150244 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2901 13:47:11.155819 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2902 13:47:11.161326 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2903 13:47:11.161809 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2904 13:47:11.166868 alsa_pcm-test pass
2905 13:47:11.172410 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2906 13:47:11.183590 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2907 13:47:11.189073 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2908 13:47:11.200180 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2909 13:47:11.205819 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2910 13:47:11.211236 alsa_test-pcmtest-driver pass
2911 13:47:11.216815 alsa_utimer-test_global_wrong_timers_test pass
2912 13:47:11.217307 alsa_utimer-test_timer_f_utimer fail
2913 13:47:11.222330 alsa_utimer-test fail
2914 13:47:11.222822 + ../../utils/send-to-lava.sh ./output/result.txt
2915 13:47:11.227877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2916 13:47:11.228948 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2918 13:47:11.238955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2919 13:47:11.239737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2921 13:47:11.244744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2922 13:47:11.245501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2924 13:47:11.279776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2925 13:47:11.280655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2927 13:47:11.333522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2928 13:47:11.334368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2930 13:47:11.377055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2931 13:47:11.378233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2933 13:47:11.422716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2934 13:47:11.423547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2936 13:47:11.480588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2937 13:47:11.481481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2939 13:47:11.529914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2940 13:47:11.530721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2942 13:47:11.582949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2943 13:47:11.583810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2945 13:47:11.628163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2946 13:47:11.628949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2948 13:47:11.687010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2949 13:47:11.687863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2951 13:47:11.739844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2952 13:47:11.740660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2954 13:47:11.790362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2955 13:47:11.791239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2957 13:47:11.845971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2958 13:47:11.846894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2960 13:47:11.900620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2961 13:47:11.901561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2963 13:47:11.944357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2964 13:47:11.945278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2966 13:47:11.998198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2967 13:47:11.999208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2969 13:47:12.043407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2970 13:47:12.044343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2972 13:47:12.108243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2973 13:47:12.109151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2975 13:47:12.159408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2976 13:47:12.160321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2978 13:47:12.220263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2979 13:47:12.221186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2981 13:47:12.272269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2982 13:47:12.273217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2984 13:47:12.328309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2985 13:47:12.329256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2987 13:47:12.381033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2988 13:47:12.382058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2990 13:47:12.436590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2991 13:47:12.437666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2993 13:47:12.493397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
2994 13:47:12.494353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
2996 13:47:12.548186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
2997 13:47:12.549184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
2999 13:47:12.616919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3000 13:47:12.617823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3002 13:47:12.663821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3003 13:47:12.664652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3005 13:47:12.719328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3006 13:47:12.720202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3008 13:47:12.778365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3009 13:47:12.779180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3011 13:47:12.828890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3012 13:47:12.829765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3014 13:47:12.878766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3015 13:47:12.879557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3017 13:47:12.941957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3018 13:47:12.942829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3020 13:47:12.998030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3021 13:47:12.998896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3023 13:47:13.058616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3024 13:47:13.059441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3026 13:47:13.109211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3027 13:47:13.110283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3029 13:47:13.176022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3030 13:47:13.176970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3032 13:47:13.227748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3033 13:47:13.228718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3035 13:47:13.278351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3036 13:47:13.279230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3038 13:47:13.321072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3039 13:47:13.321988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3041 13:47:13.381521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3042 13:47:13.382445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3044 13:47:13.431289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3045 13:47:13.432224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3047 13:47:13.489596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3048 13:47:13.490535 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3050 13:47:13.535062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3051 13:47:13.536028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3053 13:47:13.589184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3054 13:47:13.590040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3056 13:47:13.642952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3057 13:47:13.643800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3059 13:47:13.695517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3060 13:47:13.696420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3062 13:47:13.740054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3063 13:47:13.740900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3065 13:47:13.814254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3066 13:47:13.815165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3068 13:47:13.869078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3069 13:47:13.869935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3071 13:47:13.921562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3072 13:47:13.922406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3074 13:47:13.984550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3075 13:47:13.985417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3077 13:47:14.039796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3078 13:47:14.040722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3080 13:47:14.085707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3081 13:47:14.086573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3083 13:47:14.142627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3084 13:47:14.143479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3086 13:47:14.195564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3087 13:47:14.196435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3089 13:47:14.250800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3090 13:47:14.251619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3092 13:47:14.299071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3093 13:47:14.299896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3095 13:47:14.356338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3096 13:47:14.357192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3098 13:47:14.413833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3099 13:47:14.414705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3101 13:47:14.464602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3102 13:47:14.465452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3104 13:47:14.513168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3105 13:47:14.514025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3107 13:47:14.589792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3108 13:47:14.590692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3110 13:47:14.644100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3111 13:47:14.644957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3113 13:47:14.707162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3114 13:47:14.708040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3116 13:47:14.758183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3117 13:47:14.759008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3119 13:47:14.814690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3120 13:47:14.815561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3122 13:47:14.866516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3123 13:47:14.867403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3125 13:47:14.925713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3126 13:47:14.926620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3128 13:47:14.978144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3129 13:47:14.979001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3131 13:47:15.023706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3132 13:47:15.024606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3134 13:47:15.084849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3135 13:47:15.085703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3137 13:47:15.138498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3138 13:47:15.139383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3140 13:47:15.189975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3141 13:47:15.190810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3143 13:47:15.240106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3144 13:47:15.240917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3146 13:47:15.291097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3147 13:47:15.291900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3149 13:47:15.355724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3150 13:47:15.356579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3152 13:47:15.404841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3153 13:47:15.405648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3155 13:47:15.454740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3156 13:47:15.455537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3158 13:47:15.506795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3159 13:47:15.507608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3161 13:47:15.559335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3162 13:47:15.560164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3164 13:47:15.605744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3165 13:47:15.606570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3167 13:47:15.653967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3168 13:47:15.654789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3170 13:47:15.700488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3171 13:47:15.701314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3173 13:47:15.748261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3174 13:47:15.749126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3176 13:47:15.802222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3177 13:47:15.803103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3179 13:47:15.858829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3180 13:47:15.859687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3182 13:47:15.908754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3183 13:47:15.909552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3185 13:47:15.960425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3186 13:47:15.961213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3188 13:47:16.009730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3189 13:47:16.010462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3191 13:47:16.060874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3192 13:47:16.061597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3194 13:47:16.105750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3195 13:47:16.106474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3197 13:47:16.151526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3198 13:47:16.152305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3200 13:47:16.200551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3201 13:47:16.201271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3203 13:47:16.251495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3204 13:47:16.252378 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3206 13:47:16.296770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3207 13:47:16.297543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3209 13:47:16.349549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3210 13:47:16.350433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3212 13:47:16.395441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3213 13:47:16.396393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3215 13:47:16.448107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3216 13:47:16.448987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3218 13:47:16.491935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3219 13:47:16.492816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3221 13:47:16.536875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3222 13:47:16.537733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3224 13:47:16.582431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3225 13:47:16.583274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3227 13:47:16.633906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3228 13:47:16.634792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3230 13:47:16.687398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3231 13:47:16.688331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3233 13:47:16.736680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3234 13:47:16.737560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3236 13:47:16.782325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3237 13:47:16.783295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3239 13:47:16.830064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3240 13:47:16.830947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3242 13:47:16.879592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3243 13:47:16.880543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3245 13:47:16.933254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3246 13:47:16.934165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3248 13:47:16.988322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3249 13:47:16.994515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3251 13:47:17.052211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3252 13:47:17.053003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3254 13:47:17.103200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3255 13:47:17.103964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3257 13:47:17.156952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3258 13:47:17.157706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3260 13:47:17.211788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3261 13:47:17.212577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3263 13:47:17.259940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3264 13:47:17.260788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3266 13:47:17.312653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3267 13:47:17.313309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3269 13:47:17.369354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3270 13:47:17.370038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3272 13:47:17.426755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3273 13:47:17.427441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3275 13:47:17.479316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3276 13:47:17.479959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3278 13:47:17.536767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3279 13:47:17.537410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3281 13:47:17.589541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3282 13:47:17.590471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3284 13:47:17.743678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3285 13:47:17.744353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3287 13:47:17.791314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3288 13:47:17.791864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3290 13:47:17.843548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3291 13:47:17.844332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3293 13:47:17.893418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3294 13:47:17.894149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3296 13:47:17.943404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3297 13:47:17.944202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3299 13:47:17.991224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3300 13:47:17.992029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3302 13:47:18.049030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3303 13:47:18.049807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3305 13:47:18.106192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3306 13:47:18.106912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3308 13:47:18.155297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3309 13:47:18.156035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3311 13:47:18.205325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3312 13:47:18.206038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3314 13:47:18.265352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3315 13:47:18.266146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3317 13:47:18.308359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3318 13:47:18.309096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3320 13:47:18.360008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3321 13:47:18.360773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3323 13:47:18.412979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3324 13:47:18.413735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3326 13:47:18.461536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3327 13:47:18.462260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3329 13:47:18.510096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3330 13:47:18.510840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3332 13:47:18.562495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3333 13:47:18.563230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3335 13:47:18.611115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3336 13:47:18.611844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3338 13:47:18.663251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3339 13:47:18.664037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3341 13:47:18.718329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3342 13:47:18.719056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3344 13:47:18.763269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3345 13:47:18.764021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3347 13:47:18.810070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3348 13:47:18.810798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3350 13:47:18.857402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3351 13:47:18.858140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3353 13:47:18.914321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3354 13:47:18.915036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3356 13:47:18.959944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3357 13:47:18.960726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3359 13:47:19.008228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3360 13:47:19.008967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3362 13:47:19.052259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3363 13:47:19.053005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3365 13:47:19.096508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3366 13:47:19.097253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3368 13:47:19.145920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3369 13:47:19.146663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3371 13:47:19.196270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3372 13:47:19.197020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3374 13:47:19.239764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3375 13:47:19.240609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3377 13:47:19.289962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3378 13:47:19.290722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3380 13:47:19.338191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3381 13:47:19.338955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3383 13:47:19.385211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3384 13:47:19.385989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3386 13:47:19.439615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3387 13:47:19.440388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3389 13:47:19.489683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3390 13:47:19.490416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3392 13:47:19.534977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3393 13:47:19.535708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3395 13:47:19.583225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3396 13:47:19.583969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3398 13:47:19.634039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3399 13:47:19.634785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3401 13:47:19.686056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3402 13:47:19.686799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3404 13:47:19.729570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3405 13:47:19.730421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3407 13:47:19.773731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3408 13:47:19.774460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3410 13:47:19.820439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3411 13:47:19.821206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3413 13:47:19.870119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3414 13:47:19.870877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3416 13:47:19.924409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3417 13:47:19.925177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3419 13:47:19.978038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3420 13:47:19.978761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3422 13:47:20.022979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3423 13:47:20.023809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3425 13:47:20.071699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3426 13:47:20.072516 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3428 13:47:20.128233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3429 13:47:20.129056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3431 13:47:20.181680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3432 13:47:20.182430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3434 13:47:20.237118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3435 13:47:20.237900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3437 13:47:20.287092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3438 13:47:20.287826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3440 13:47:20.334715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3441 13:47:20.335458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3443 13:47:20.385321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3444 13:47:20.386099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3446 13:47:20.437226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3447 13:47:20.437961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3449 13:47:20.484403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3450 13:47:20.485128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3452 13:47:20.535903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3453 13:47:20.536697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3455 13:47:20.596405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3456 13:47:20.597141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3458 13:47:20.649274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3459 13:47:20.649870 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3461 13:47:20.692891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3462 13:47:20.693761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3464 13:47:20.748349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3465 13:47:20.749136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3467 13:47:20.800639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3468 13:47:20.801376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3470 13:47:20.851817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3471 13:47:20.852571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3473 13:47:20.910918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3474 13:47:20.911675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3476 13:47:20.965054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3477 13:47:20.965860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3479 13:47:21.019840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3480 13:47:21.020597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3482 13:47:21.065926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3483 13:47:21.066613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3485 13:47:21.120712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3486 13:47:21.121413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3488 13:47:21.166109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3489 13:47:21.166793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3491 13:47:21.217328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3492 13:47:21.218023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3494 13:47:21.265880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3495 13:47:21.266687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3497 13:47:21.310491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3498 13:47:21.311218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3500 13:47:21.356260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3501 13:47:21.356989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3503 13:47:21.401238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3504 13:47:21.401967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3506 13:47:21.453480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3507 13:47:21.454204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3509 13:47:21.505996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3510 13:47:21.506719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3512 13:47:21.562301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3513 13:47:21.563022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3515 13:47:21.614517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3516 13:47:21.615261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3518 13:47:21.665498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3519 13:47:21.666330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3521 13:47:21.717637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3522 13:47:21.718386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3524 13:47:21.768520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3525 13:47:21.769217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3527 13:47:21.820088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3528 13:47:21.820785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3530 13:47:21.875247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3531 13:47:21.875961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3533 13:47:21.929510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3534 13:47:21.930228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3536 13:47:21.989668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3537 13:47:21.990367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3539 13:47:22.042936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3540 13:47:22.043628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3542 13:47:22.098762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3543 13:47:22.099464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3545 13:47:22.153136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3546 13:47:22.153846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3548 13:47:22.206980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3549 13:47:22.207676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3551 13:47:22.258008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3552 13:47:22.258752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3554 13:47:22.313359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3555 13:47:22.314080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3557 13:47:22.359276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3558 13:47:22.360024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3560 13:47:22.413330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3561 13:47:22.414050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3563 13:47:22.466703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3564 13:47:22.467404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3566 13:47:22.524631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3567 13:47:22.525336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3569 13:47:22.571062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3570 13:47:22.571759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3572 13:47:22.617282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3573 13:47:22.617972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3575 13:47:22.673719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3576 13:47:22.674421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3578 13:47:22.726078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3579 13:47:22.726766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3581 13:47:22.772104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3582 13:47:22.772805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3584 13:47:22.822767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3585 13:47:22.823466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3587 13:47:22.867656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3588 13:47:22.868389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3590 13:47:22.913156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3591 13:47:22.913859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3593 13:47:22.973691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3594 13:47:22.974388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3596 13:47:23.021457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3597 13:47:23.022144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3599 13:47:23.065040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3600 13:47:23.065728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3602 13:47:23.116684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3603 13:47:23.117381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3605 13:47:23.171923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3606 13:47:23.172669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3608 13:47:23.227629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3609 13:47:23.228420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3611 13:47:23.280695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3612 13:47:23.281423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3614 13:47:23.336788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3615 13:47:23.337529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3617 13:47:23.390095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3618 13:47:23.390889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3620 13:47:23.441798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3621 13:47:23.442522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3623 13:47:23.500831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3624 13:47:23.501606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3626 13:47:23.551438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3627 13:47:23.552179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3629 13:47:23.602787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3630 13:47:23.603626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3632 13:47:23.651662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3633 13:47:23.652463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3635 13:47:23.699846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3636 13:47:23.700621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3638 13:47:23.760193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3639 13:47:23.760959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3641 13:47:23.805319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3642 13:47:23.806057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3644 13:47:23.854094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3645 13:47:23.854845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3647 13:47:23.908214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3648 13:47:23.909032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3650 13:47:23.954154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3651 13:47:23.954948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3653 13:47:24.004065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3654 13:47:24.004780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3656 13:47:24.058176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3657 13:47:24.058879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3659 13:47:24.111586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3660 13:47:24.112313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3662 13:47:24.165064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3663 13:47:24.165771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3665 13:47:24.223407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3666 13:47:24.224151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3668 13:47:24.273009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3669 13:47:24.273714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3671 13:47:24.326020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3672 13:47:24.326716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3674 13:47:24.371888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3675 13:47:24.372617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3677 13:47:24.416896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3678 13:47:24.417591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3680 13:47:24.473420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3681 13:47:24.474118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3683 13:47:24.526927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3684 13:47:24.527620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3686 13:47:24.572325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3687 13:47:24.573021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3689 13:47:24.627501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3690 13:47:24.628192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3692 13:47:24.684369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3693 13:47:24.685063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3695 13:47:24.731142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3696 13:47:24.731837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3698 13:47:24.777339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3699 13:47:24.778041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3701 13:47:24.831095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3702 13:47:24.831796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3704 13:47:24.879639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3705 13:47:24.880362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3707 13:47:24.930619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3708 13:47:24.931321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3710 13:47:24.983115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3711 13:47:24.983823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3713 13:47:25.040145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3714 13:47:25.040848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3716 13:47:25.086749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3717 13:47:25.087441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3719 13:47:25.136443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3720 13:47:25.137165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3722 13:47:25.186476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3723 13:47:25.187246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3725 13:47:25.244222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3726 13:47:25.244961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3728 13:47:25.296653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3729 13:47:25.297377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3731 13:47:25.340661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3732 13:47:25.341351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3734 13:47:25.385590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3735 13:47:25.386289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3737 13:47:25.442290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3738 13:47:25.443092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3740 13:47:25.495374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3741 13:47:25.496153 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3743 13:47:25.541617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3744 13:47:25.542341 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3746 13:47:25.598545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3747 13:47:25.599262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3749 13:47:25.642691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3750 13:47:25.643402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3752 13:47:25.695206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3753 13:47:25.696057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3755 13:47:25.748247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3756 13:47:25.748999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3758 13:47:25.795492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3759 13:47:25.796262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3761 13:47:25.845346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3762 13:47:25.846066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3764 13:47:25.892572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3765 13:47:25.893323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3767 13:47:25.946176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3768 13:47:25.946907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3770 13:47:25.997366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3771 13:47:25.998177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3773 13:47:26.052441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3774 13:47:26.053136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3776 13:47:26.105649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3777 13:47:26.106355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3779 13:47:26.158507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3780 13:47:26.159205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3782 13:47:26.205908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3783 13:47:26.206496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3785 13:47:26.259610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3786 13:47:26.260569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3788 13:47:26.309049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3789 13:47:26.309932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3791 13:47:26.366997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3792 13:47:26.367796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3794 13:47:26.420284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3795 13:47:26.421140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3797 13:47:26.476275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3798 13:47:26.477222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3800 13:47:26.518438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3801 13:47:26.519425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3803 13:47:26.568042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3804 13:47:26.568865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3806 13:47:26.624374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3807 13:47:26.625228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3809 13:47:26.677422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3810 13:47:26.678251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3812 13:47:26.722819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3813 13:47:26.723612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3815 13:47:26.779130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3816 13:47:26.779931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3818 13:47:26.829273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3819 13:47:26.830052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3821 13:47:26.879943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3822 13:47:26.880765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3824 13:47:26.929019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3825 13:47:26.929846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3827 13:47:26.982928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3828 13:47:26.983715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3830 13:47:27.040988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3831 13:47:27.041772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3833 13:47:27.093436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3834 13:47:27.094211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3836 13:47:27.146805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3837 13:47:27.147589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3839 13:47:27.194425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3840 13:47:27.195207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3842 13:47:27.253066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3843 13:47:27.253859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3845 13:47:27.304750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3846 13:47:27.305639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3848 13:47:27.360631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3849 13:47:27.361474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3851 13:47:27.408370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3852 13:47:27.409196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3854 13:47:27.459476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3855 13:47:27.460327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3857 13:47:27.504358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3858 13:47:27.505179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3860 13:47:27.558970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3861 13:47:27.559865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3863 13:47:27.612250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3864 13:47:27.613140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3866 13:47:27.669424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3867 13:47:27.670306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3869 13:47:27.722688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3870 13:47:27.723563 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3872 13:47:27.776266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3873 13:47:27.777143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3875 13:47:27.827885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3876 13:47:27.828805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3878 13:47:27.876443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3879 13:47:27.877444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3881 13:47:27.931682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3882 13:47:27.932616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3884 13:47:27.978802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3885 13:47:27.979695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3887 13:47:28.036637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3888 13:47:28.037546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3890 13:47:28.082630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3891 13:47:28.083504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3893 13:47:28.133457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3894 13:47:28.134312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3896 13:47:28.187094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3897 13:47:28.188048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3899 13:47:28.241927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3900 13:47:28.242820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3902 13:47:28.286748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3903 13:47:28.287723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3905 13:47:28.334605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3906 13:47:28.335420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3908 13:47:28.381236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3909 13:47:28.382074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3911 13:47:28.431305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3912 13:47:28.432130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3914 13:47:28.484015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3915 13:47:28.484827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3917 13:47:28.538819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3918 13:47:28.539646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3920 13:47:28.589376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3921 13:47:28.590185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3923 13:47:28.644038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3924 13:47:28.644852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3926 13:47:28.694348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3927 13:47:28.695165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3929 13:47:28.742173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3930 13:47:28.743056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3932 13:47:28.790300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3933 13:47:28.791099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3935 13:47:28.836563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3936 13:47:28.837383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3938 13:47:28.881963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3939 13:47:28.882770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3941 13:47:28.928765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3942 13:47:28.929588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3944 13:47:28.976586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3945 13:47:28.977403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3947 13:47:29.030080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3948 13:47:29.030884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3950 13:47:29.080935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3951 13:47:29.081743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3953 13:47:29.137817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3954 13:47:29.138629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3956 13:47:29.190883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3957 13:47:29.191691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3959 13:47:29.243040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3960 13:47:29.243868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3962 13:47:29.292776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3963 13:47:29.293575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3965 13:47:29.346660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3966 13:47:29.348183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3968 13:47:29.403638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3969 13:47:29.404753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3971 13:47:29.455508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3972 13:47:29.456552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3974 13:47:29.501377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3975 13:47:29.502399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3977 13:47:29.546192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3978 13:47:29.547174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3980 13:47:29.595514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3981 13:47:29.596498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3983 13:47:29.650921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3984 13:47:29.651925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3986 13:47:29.693980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3987 13:47:29.695034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3989 13:47:29.744962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3990 13:47:29.745831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3992 13:47:29.789975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3993 13:47:29.790819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
3995 13:47:29.838892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
3996 13:47:29.839747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
3998 13:47:29.890899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
3999 13:47:29.891735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4001 13:47:29.937545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4002 13:47:29.938385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4004 13:47:29.995727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4005 13:47:29.996628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4007 13:47:30.048226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4008 13:47:30.049093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4010 13:47:30.100066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4011 13:47:30.100921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4013 13:47:30.159055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4014 13:47:30.159911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4016 13:47:30.212529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4017 13:47:30.213385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4019 13:47:30.257749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4020 13:47:30.258588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4022 13:47:30.308283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4023 13:47:30.309170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4025 13:47:30.364102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4026 13:47:30.364967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4028 13:47:30.418810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4029 13:47:30.419659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4031 13:47:30.465794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4032 13:47:30.466642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4034 13:47:30.515791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4035 13:47:30.516687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4037 13:47:30.568103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4038 13:47:30.568949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4040 13:47:30.616569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4041 13:47:30.617481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4043 13:47:30.679495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4044 13:47:30.680385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4046 13:47:30.723089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4047 13:47:30.723931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4049 13:47:30.777052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4050 13:47:30.777906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4052 13:47:30.824585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4053 13:47:30.825421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4055 13:47:30.865878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4056 13:47:30.866721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4058 13:47:30.916355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4059 13:47:30.917185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4061 13:47:30.968220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4062 13:47:30.969065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4064 13:47:31.026144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4065 13:47:31.027008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4067 13:47:31.083122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4068 13:47:31.083933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4070 13:47:31.126906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4071 13:47:31.127708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4073 13:47:31.183008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4074 13:47:31.183802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4076 13:47:31.234270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4077 13:47:31.235076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4079 13:47:31.280476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4080 13:47:31.281276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4082 13:47:31.329711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4083 13:47:31.330551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4085 13:47:31.374462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4086 13:47:31.375288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4088 13:47:31.428284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4089 13:47:31.429101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4091 13:47:31.476402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4092 13:47:31.477230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4094 13:47:31.528735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4095 13:47:31.529548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4097 13:47:31.575697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4098 13:47:31.576552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4100 13:47:31.623773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4101 13:47:31.624663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4103 13:47:31.669607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4104 13:47:31.670460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4106 13:47:31.720747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4107 13:47:31.721611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4109 13:47:31.767126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4110 13:47:31.768010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4112 13:47:31.826118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4113 13:47:31.826975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4115 13:47:31.880522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4116 13:47:31.881369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4118 13:47:31.930287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4119 13:47:31.931142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4121 13:47:31.988282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4122 13:47:31.989149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4124 13:47:32.043032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4125 13:47:32.043902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4127 13:47:32.088179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4128 13:47:32.089027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4130 13:47:32.137150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4131 13:47:32.138028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4133 13:47:32.196059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4134 13:47:32.196911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4136 13:47:32.245714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4137 13:47:32.246529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4139 13:47:32.296648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4140 13:47:32.297479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4142 13:47:32.343046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4143 13:47:32.343914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4145 13:47:32.396066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4146 13:47:32.396907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4148 13:47:32.441565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4149 13:47:32.442390 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4151 13:47:32.500236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4152 13:47:32.501087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4154 13:47:32.547102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4155 13:47:32.548028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4157 13:47:32.601541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4158 13:47:32.602412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4160 13:47:32.650943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4161 13:47:32.651764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4163 13:47:32.704388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4164 13:47:32.705207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4166 13:47:32.756273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4167 13:47:32.757091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4169 13:47:32.815878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4170 13:47:32.816752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4172 13:47:32.868291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4173 13:47:32.869110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4175 13:47:32.919398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4176 13:47:32.920215 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4178 13:47:32.970750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4179 13:47:32.971569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4181 13:47:33.025124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4182 13:47:33.025953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4184 13:47:33.070461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4185 13:47:33.071280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4187 13:47:33.120954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4188 13:47:33.121768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4190 13:47:33.169693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4191 13:47:33.170510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4193 13:47:33.227383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4194 13:47:33.228219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4196 13:47:33.282003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4197 13:47:33.282826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4199 13:47:33.327757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4201 13:47:33.330820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4202 13:47:33.384250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4203 13:47:33.385080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4205 13:47:33.433607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4206 13:47:33.434429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4208 13:47:33.485756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4209 13:47:33.486574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4211 13:47:33.534485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4212 13:47:33.535313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4214 13:47:33.589390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4215 13:47:33.590218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4217 13:47:33.641921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4218 13:47:33.642758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4220 13:47:33.687801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4221 13:47:33.688658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4223 13:47:33.734223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4224 13:47:33.735047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4226 13:47:33.786352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4227 13:47:33.787171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4229 13:47:33.838018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4230 13:47:33.838847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4232 13:47:33.888789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4233 13:47:33.889615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4235 13:47:33.934108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4236 13:47:33.934931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4238 13:47:33.978281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4239 13:47:33.979101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4241 13:47:34.032714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4242 13:47:34.033548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4244 13:47:34.085270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4245 13:47:34.086101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4247 13:47:34.130276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4248 13:47:34.131106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4250 13:47:34.182406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4251 13:47:34.183235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4253 13:47:34.234321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4254 13:47:34.235134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4256 13:47:34.283539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4257 13:47:34.284381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4259 13:47:34.335063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4260 13:47:34.335879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4262 13:47:34.380480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4263 13:47:34.381283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4265 13:47:34.433329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4266 13:47:34.434196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4268 13:47:34.480352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4269 13:47:34.481251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4271 13:47:34.538145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4272 13:47:34.539015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4274 13:47:34.590039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4275 13:47:34.590881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4277 13:47:34.643734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4278 13:47:34.644632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4280 13:47:34.704349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4281 13:47:34.705209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4283 13:47:34.750845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4284 13:47:34.751687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4286 13:47:34.802360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4287 13:47:34.803183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4289 13:47:34.846041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4290 13:47:34.846857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4292 13:47:34.898271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4293 13:47:34.899092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4295 13:47:34.955262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4296 13:47:34.956088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4298 13:47:35.006154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4299 13:47:35.006979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4301 13:47:35.052431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4302 13:47:35.053315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4304 13:47:35.101945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4305 13:47:35.102829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4307 13:47:35.158794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4308 13:47:35.159651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4310 13:47:35.207876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4311 13:47:35.208914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4313 13:47:35.264675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4314 13:47:35.265613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4316 13:47:35.321216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4317 13:47:35.322112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4319 13:47:35.373560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4320 13:47:35.374404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4322 13:47:35.420649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4323 13:47:35.421445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4325 13:47:35.465466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4326 13:47:35.466265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4328 13:47:35.519936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4329 13:47:35.520782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4331 13:47:35.570262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4332 13:47:35.571057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4334 13:47:35.622483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4335 13:47:35.623279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4337 13:47:35.675591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4338 13:47:35.676436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4340 13:47:35.731943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4341 13:47:35.732804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4343 13:47:35.781128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4344 13:47:35.781925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4346 13:47:35.828757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4347 13:47:35.829549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4349 13:47:35.895511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4350 13:47:35.896352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4352 13:47:35.948243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4353 13:47:35.949031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4355 13:47:36.001828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4357 13:47:36.007144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4358 13:47:36.007683 + set +x
4359 13:47:36.013057 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 881554_1.6.2.4.5>
4360 13:47:36.013579 <LAVA_TEST_RUNNER EXIT>
4361 13:47:36.014276 Received signal: <ENDRUN> 1_kselftest-alsa 881554_1.6.2.4.5
4362 13:47:36.014769 Ending use of test pattern.
4363 13:47:36.015207 Ending test lava.1_kselftest-alsa (881554_1.6.2.4.5), duration 41.02
4365 13:47:36.016911 ok: lava_test_shell seems to have completed
4366 13:47:36.042082 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4367 13:47:36.043964 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4368 13:47:36.044606 end: 3 lava-test-retry (duration 00:00:42) [common]
4369 13:47:36.045191 start: 4 finalize (timeout 00:06:10) [common]
4370 13:47:36.045793 start: 4.1 power-off (timeout 00:00:30) [common]
4371 13:47:36.046845 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4372 13:47:36.088084 >> OK - accepted request
4373 13:47:36.090070 Returned 0 in 0 seconds
4374 13:47:36.191282 end: 4.1 power-off (duration 00:00:00) [common]
4376 13:47:36.193136 start: 4.2 read-feedback (timeout 00:06:10) [common]
4377 13:47:36.194314 Listened to connection for namespace 'common' for up to 1s
4378 13:47:37.195084 Finalising connection for namespace 'common'
4379 13:47:37.195857 Disconnecting from shell: Finalise
4380 13:47:37.196499 / #
4381 13:47:37.297543 end: 4.2 read-feedback (duration 00:00:01) [common]
4382 13:47:37.298290 end: 4 finalize (duration 00:00:01) [common]
4383 13:47:37.299039 Cleaning after the job
4384 13:47:37.299768 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/ramdisk
4385 13:47:37.303273 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/kernel
4386 13:47:37.311355 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/dtb
4387 13:47:37.312693 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/nfsrootfs
4388 13:47:37.361185 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/881554/tftp-deploy-7cc4wlfk/modules
4389 13:47:37.367457 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/881554
4390 13:47:40.751325 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/881554
4391 13:47:40.751896 Job finished correctly