Boot log: meson-g12b-a311d-libretech-cc

    1 21:25:24.076627  lava-dispatcher, installed at version: 2024.01
    2 21:25:24.077403  start: 0 validate
    3 21:25:24.077887  Start time: 2024-10-22 21:25:24.077857+00:00 (UTC)
    4 21:25:24.078424  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    5 21:25:24.078959  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
    6 21:25:24.118477  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    7 21:25:24.119036  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fv6.12-rc2-167-g902934bf5a62%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
    8 21:25:24.147735  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    9 21:25:24.148718  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fv6.12-rc2-167-g902934bf5a62%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
   10 21:25:25.203459  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
   11 21:25:25.204009  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fv6.12-rc2-167-g902934bf5a62%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
   12 21:25:25.243614  validate duration: 1.17
   14 21:25:25.244784  start: 1 tftp-deploy (timeout 00:10:00) [common]
   15 21:25:25.245355  start: 1.1 download-retry (timeout 00:10:00) [common]
   16 21:25:25.245850  start: 1.1.1 http-download (timeout 00:10:00) [common]
   17 21:25:25.246759  Not decompressing ramdisk as can be used compressed.
   18 21:25:25.247419  downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
   19 21:25:25.247812  saving as /var/lib/lava/dispatcher/tmp/884205/tftp-deploy-ax4dfmn7/ramdisk/rootfs.cpio.gz
   20 21:25:25.248246  total size: 8181887 (7 MB)
   21 21:25:25.286094  progress   0 % (0 MB)
   22 21:25:25.295641  progress   5 % (0 MB)
   23 21:25:25.305729  progress  10 % (0 MB)
   24 21:25:25.312884  progress  15 % (1 MB)
   25 21:25:25.319492  progress  20 % (1 MB)
   26 21:25:25.326545  progress  25 % (1 MB)
   27 21:25:25.333445  progress  30 % (2 MB)
   28 21:25:25.340530  progress  35 % (2 MB)
   29 21:25:25.347042  progress  40 % (3 MB)
   30 21:25:25.353893  progress  45 % (3 MB)
   31 21:25:25.359910  progress  50 % (3 MB)
   32 21:25:25.366710  progress  55 % (4 MB)
   33 21:25:25.372980  progress  60 % (4 MB)
   34 21:25:25.379856  progress  65 % (5 MB)
   35 21:25:25.386149  progress  70 % (5 MB)
   36 21:25:25.392986  progress  75 % (5 MB)
   37 21:25:25.399359  progress  80 % (6 MB)
   38 21:25:25.406108  progress  85 % (6 MB)
   39 21:25:25.412346  progress  90 % (7 MB)
   40 21:25:25.418755  progress  95 % (7 MB)
   41 21:25:25.424394  progress 100 % (7 MB)
   42 21:25:25.425144  7 MB downloaded in 0.18 s (44.11 MB/s)
   43 21:25:25.425772  end: 1.1.1 http-download (duration 00:00:00) [common]
   45 21:25:25.426820  end: 1.1 download-retry (duration 00:00:00) [common]
   46 21:25:25.427157  start: 1.2 download-retry (timeout 00:10:00) [common]
   47 21:25:25.427495  start: 1.2.1 http-download (timeout 00:10:00) [common]
   48 21:25:25.428076  downloading http://storage.kernelci.org/broonie-sound/for-next/v6.12-rc2-167-g902934bf5a62/arm64/defconfig/gcc-12/kernel/Image
   49 21:25:25.428373  saving as /var/lib/lava/dispatcher/tmp/884205/tftp-deploy-ax4dfmn7/kernel/Image
   50 21:25:25.428632  total size: 45713920 (43 MB)
   51 21:25:25.428881  No compression specified
   52 21:25:25.467643  progress   0 % (0 MB)
   53 21:25:25.498628  progress   5 % (2 MB)
   54 21:25:25.528303  progress  10 % (4 MB)
   55 21:25:25.558007  progress  15 % (6 MB)
   56 21:25:25.587618  progress  20 % (8 MB)
   57 21:25:25.616592  progress  25 % (10 MB)
   58 21:25:25.647424  progress  30 % (13 MB)
   59 21:25:25.678095  progress  35 % (15 MB)
   60 21:25:25.708208  progress  40 % (17 MB)
   61 21:25:25.737589  progress  45 % (19 MB)
   62 21:25:25.767095  progress  50 % (21 MB)
   63 21:25:25.796870  progress  55 % (24 MB)
   64 21:25:25.826492  progress  60 % (26 MB)
   65 21:25:25.855752  progress  65 % (28 MB)
   66 21:25:25.884929  progress  70 % (30 MB)
   67 21:25:25.915176  progress  75 % (32 MB)
   68 21:25:25.945471  progress  80 % (34 MB)
   69 21:25:25.975013  progress  85 % (37 MB)
   70 21:25:26.005845  progress  90 % (39 MB)
   71 21:25:26.036231  progress  95 % (41 MB)
   72 21:25:26.065090  progress 100 % (43 MB)
   73 21:25:26.065632  43 MB downloaded in 0.64 s (68.44 MB/s)
   74 21:25:26.066130  end: 1.2.1 http-download (duration 00:00:01) [common]
   76 21:25:26.066970  end: 1.2 download-retry (duration 00:00:01) [common]
   77 21:25:26.067252  start: 1.3 download-retry (timeout 00:09:59) [common]
   78 21:25:26.067522  start: 1.3.1 http-download (timeout 00:09:59) [common]
   79 21:25:26.068022  downloading http://storage.kernelci.org/broonie-sound/for-next/v6.12-rc2-167-g902934bf5a62/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
   80 21:25:26.068327  saving as /var/lib/lava/dispatcher/tmp/884205/tftp-deploy-ax4dfmn7/dtb/meson-g12b-a311d-libretech-cc.dtb
   81 21:25:26.068545  total size: 54703 (0 MB)
   82 21:25:26.068760  No compression specified
   83 21:25:26.108519  progress  59 % (0 MB)
   84 21:25:26.109399  progress 100 % (0 MB)
   85 21:25:26.110014  0 MB downloaded in 0.04 s (1.26 MB/s)
   86 21:25:26.110529  end: 1.3.1 http-download (duration 00:00:00) [common]
   88 21:25:26.111483  end: 1.3 download-retry (duration 00:00:00) [common]
   89 21:25:26.111811  start: 1.4 download-retry (timeout 00:09:59) [common]
   90 21:25:26.112132  start: 1.4.1 http-download (timeout 00:09:59) [common]
   91 21:25:26.112632  downloading http://storage.kernelci.org/broonie-sound/for-next/v6.12-rc2-167-g902934bf5a62/arm64/defconfig/gcc-12/modules.tar.xz
   92 21:25:26.112906  saving as /var/lib/lava/dispatcher/tmp/884205/tftp-deploy-ax4dfmn7/modules/modules.tar
   93 21:25:26.113124  total size: 11588116 (11 MB)
   94 21:25:26.113337  Using unxz to decompress xz
   95 21:25:26.154735  progress   0 % (0 MB)
   96 21:25:26.258633  progress   5 % (0 MB)
   97 21:25:26.375661  progress  10 % (1 MB)
   98 21:25:26.504299  progress  15 % (1 MB)
   99 21:25:26.623437  progress  20 % (2 MB)
  100 21:25:26.722742  progress  25 % (2 MB)
  101 21:25:26.802232  progress  30 % (3 MB)
  102 21:25:26.874695  progress  35 % (3 MB)
  103 21:25:26.954032  progress  40 % (4 MB)
  104 21:25:27.038765  progress  45 % (5 MB)
  105 21:25:27.115216  progress  50 % (5 MB)
  106 21:25:27.197657  progress  55 % (6 MB)
  107 21:25:27.278170  progress  60 % (6 MB)
  108 21:25:27.357336  progress  65 % (7 MB)
  109 21:25:27.438534  progress  70 % (7 MB)
  110 21:25:27.519659  progress  75 % (8 MB)
  111 21:25:27.597823  progress  80 % (8 MB)
  112 21:25:27.695439  progress  85 % (9 MB)
  113 21:25:27.760409  progress  90 % (9 MB)
  114 21:25:27.855013  progress  95 % (10 MB)
  115 21:25:27.954121  progress 100 % (11 MB)
  116 21:25:27.967170  11 MB downloaded in 1.85 s (5.96 MB/s)
  117 21:25:27.967797  end: 1.4.1 http-download (duration 00:00:02) [common]
  119 21:25:27.968754  end: 1.4 download-retry (duration 00:00:02) [common]
  120 21:25:27.969043  start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
  121 21:25:27.969317  start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
  122 21:25:27.969576  end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
  123 21:25:27.969841  start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
  124 21:25:27.970470  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz
  125 21:25:27.970994  makedir: /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin
  126 21:25:27.971352  makedir: /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/tests
  127 21:25:27.971684  makedir: /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/results
  128 21:25:27.972165  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-add-keys
  129 21:25:27.972836  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-add-sources
  130 21:25:27.973396  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-background-process-start
  131 21:25:27.973957  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-background-process-stop
  132 21:25:27.974572  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-common-functions
  133 21:25:27.975134  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-echo-ipv4
  134 21:25:27.975663  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-install-packages
  135 21:25:27.976215  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-installed-packages
  136 21:25:27.976787  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-os-build
  137 21:25:27.977340  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-probe-channel
  138 21:25:27.977851  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-probe-ip
  139 21:25:27.978389  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-target-ip
  140 21:25:27.978980  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-target-mac
  141 21:25:27.979520  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-target-storage
  142 21:25:27.980090  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-test-case
  143 21:25:27.980650  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-test-event
  144 21:25:27.981267  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-test-feedback
  145 21:25:27.981838  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-test-raise
  146 21:25:27.982405  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-test-reference
  147 21:25:27.982964  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-test-runner
  148 21:25:27.983638  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-test-set
  149 21:25:27.984284  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-test-shell
  150 21:25:27.984853  Updating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-install-packages (oe)
  151 21:25:27.985460  Updating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/bin/lava-installed-packages (oe)
  152 21:25:27.986005  Creating /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/environment
  153 21:25:27.986446  LAVA metadata
  154 21:25:27.986720  - LAVA_JOB_ID=884205
  155 21:25:27.986941  - LAVA_DISPATCHER_IP=192.168.6.2
  156 21:25:27.987335  start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
  157 21:25:27.988496  end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
  158 21:25:27.988846  start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
  159 21:25:27.989063  skipped lava-vland-overlay
  160 21:25:27.989316  end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
  161 21:25:27.989578  start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
  162 21:25:27.989856  skipped lava-multinode-overlay
  163 21:25:27.990142  end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  164 21:25:27.990410  start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
  165 21:25:27.990675  Loading test definitions
  166 21:25:27.990966  start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
  167 21:25:27.991199  Using /lava-884205 at stage 0
  168 21:25:27.992607  uuid=884205_1.5.2.4.1 testdef=None
  169 21:25:27.992948  end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
  170 21:25:27.993229  start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
  171 21:25:27.995190  end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
  173 21:25:27.996068  start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
  174 21:25:27.998527  end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
  176 21:25:27.999408  start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
  177 21:25:28.001780  runner path: /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/0/tests/0_dmesg test_uuid 884205_1.5.2.4.1
  178 21:25:28.002402  end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  180 21:25:28.003187  Creating lava-test-runner.conf files
  181 21:25:28.003394  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/884205/lava-overlay-tyiv9srz/lava-884205/0 for stage 0
  182 21:25:28.003780  - 0_dmesg
  183 21:25:28.004204  end: 1.5.2.4 test-definition (duration 00:00:00) [common]
  184 21:25:28.004514  start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
  185 21:25:28.032202  end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
  186 21:25:28.032648  start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
  187 21:25:28.032916  end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  188 21:25:28.033185  end: 1.5.2 lava-overlay (duration 00:00:00) [common]
  189 21:25:28.033448  start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
  190 21:25:29.013126  end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
  191 21:25:29.013589  start: 1.5.4 extract-modules (timeout 00:09:56) [common]
  192 21:25:29.013844  extracting modules file /var/lib/lava/dispatcher/tmp/884205/tftp-deploy-ax4dfmn7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/884205/extract-overlay-ramdisk-mmfh6lgr/ramdisk
  193 21:25:30.370003  end: 1.5.4 extract-modules (duration 00:00:01) [common]
  194 21:25:30.370479  start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
  195 21:25:30.370757  [common] Applying overlay /var/lib/lava/dispatcher/tmp/884205/compress-overlay-nl1e_qw9/overlay-1.5.2.5.tar.gz to ramdisk
  196 21:25:30.370969  [common] Applying overlay /var/lib/lava/dispatcher/tmp/884205/compress-overlay-nl1e_qw9/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/884205/extract-overlay-ramdisk-mmfh6lgr/ramdisk
  197 21:25:30.401006  end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
  198 21:25:30.401416  start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
  199 21:25:30.401687  start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
  200 21:25:30.401915  Converting downloaded kernel to a uImage
  201 21:25:30.402223  mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/884205/tftp-deploy-ax4dfmn7/kernel/Image /var/lib/lava/dispatcher/tmp/884205/tftp-deploy-ax4dfmn7/kernel/uImage
  202 21:25:30.887163  output: Image Name:   
  203 21:25:30.887581  output: Created:      Tue Oct 22 21:25:30 2024
  204 21:25:30.887789  output: Image Type:   AArch64 Linux Kernel Image (uncompressed)
  205 21:25:30.888027  output: Data Size:    45713920 Bytes = 44642.50 KiB = 43.60 MiB
  206 21:25:30.888236  output: Load Address: 01080000
  207 21:25:30.888437  output: Entry Point:  01080000
  208 21:25:30.888634  output: 
  209 21:25:30.888966  end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
  210 21:25:30.889228  end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
  211 21:25:30.889494  start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
  212 21:25:30.889743  end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
  213 21:25:30.889998  start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
  214 21:25:30.890249  Building ramdisk /var/lib/lava/dispatcher/tmp/884205/extract-overlay-ramdisk-mmfh6lgr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/884205/extract-overlay-ramdisk-mmfh6lgr/ramdisk
  215 21:25:33.246239  >> 181565 blocks

  216 21:25:41.791632  Adding RAMdisk u-boot header.
  217 21:25:41.792382  mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/884205/extract-overlay-ramdisk-mmfh6lgr/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/884205/extract-overlay-ramdisk-mmfh6lgr/ramdisk.cpio.gz.uboot
  218 21:25:42.071580  output: Image Name:   
  219 21:25:42.072068  output: Created:      Tue Oct 22 21:25:41 2024
  220 21:25:42.072541  output: Image Type:   AArch64 Linux RAMDisk Image (uncompressed)
  221 21:25:42.072989  output: Data Size:    26056603 Bytes = 25445.90 KiB = 24.85 MiB
  222 21:25:42.073449  output: Load Address: 00000000
  223 21:25:42.073891  output: Entry Point:  00000000
  224 21:25:42.074323  output: 
  225 21:25:42.075528  rename /var/lib/lava/dispatcher/tmp/884205/extract-overlay-ramdisk-mmfh6lgr/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/884205/tftp-deploy-ax4dfmn7/ramdisk/ramdisk.cpio.gz.uboot
  226 21:25:42.076334  end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
  227 21:25:42.076927  end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
  228 21:25:42.077495  start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
  229 21:25:42.077986  No LXC device requested
  230 21:25:42.078529  end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
  231 21:25:42.079078  start: 1.7 deploy-device-env (timeout 00:09:43) [common]
  232 21:25:42.079612  end: 1.7 deploy-device-env (duration 00:00:00) [common]
  233 21:25:42.080092  Checking files for TFTP limit of 4294967296 bytes.
  234 21:25:42.082965  end: 1 tftp-deploy (duration 00:00:17) [common]
  235 21:25:42.083586  start: 2 uboot-action (timeout 00:05:00) [common]
  236 21:25:42.084192  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  237 21:25:42.084737  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  238 21:25:42.085284  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  239 21:25:42.085856  Using kernel file from prepare-kernel: 884205/tftp-deploy-ax4dfmn7/kernel/uImage
  240 21:25:42.086531  substitutions:
  241 21:25:42.086979  - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
  242 21:25:42.087420  - {DTB_ADDR}: 0x01070000
  243 21:25:42.087854  - {DTB}: 884205/tftp-deploy-ax4dfmn7/dtb/meson-g12b-a311d-libretech-cc.dtb
  244 21:25:42.088328  - {INITRD}: 884205/tftp-deploy-ax4dfmn7/ramdisk/ramdisk.cpio.gz.uboot
  245 21:25:42.088768  - {KERNEL_ADDR}: 0x01080000
  246 21:25:42.089200  - {KERNEL}: 884205/tftp-deploy-ax4dfmn7/kernel/uImage
  247 21:25:42.089635  - {LAVA_MAC}: None
  248 21:25:42.090105  - {PRESEED_CONFIG}: None
  249 21:25:42.090537  - {PRESEED_LOCAL}: None
  250 21:25:42.090965  - {RAMDISK_ADDR}: 0x08000000
  251 21:25:42.091387  - {RAMDISK}: 884205/tftp-deploy-ax4dfmn7/ramdisk/ramdisk.cpio.gz.uboot
  252 21:25:42.091819  - {ROOT_PART}: None
  253 21:25:42.092277  - {ROOT}: None
  254 21:25:42.092705  - {SERVER_IP}: 192.168.6.2
  255 21:25:42.093136  - {TEE_ADDR}: 0x83000000
  256 21:25:42.093564  - {TEE}: None
  257 21:25:42.093991  Parsed boot commands:
  258 21:25:42.094406  - setenv autoload no
  259 21:25:42.094829  - setenv initrd_high 0xffffffff
  260 21:25:42.095251  - setenv fdt_high 0xffffffff
  261 21:25:42.095676  - dhcp
  262 21:25:42.096121  - setenv serverip 192.168.6.2
  263 21:25:42.096546  - tftpboot 0x01080000 884205/tftp-deploy-ax4dfmn7/kernel/uImage
  264 21:25:42.096971  - tftpboot 0x08000000 884205/tftp-deploy-ax4dfmn7/ramdisk/ramdisk.cpio.gz.uboot
  265 21:25:42.097392  - tftpboot 0x01070000 884205/tftp-deploy-ax4dfmn7/dtb/meson-g12b-a311d-libretech-cc.dtb
  266 21:25:42.097815  - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  267 21:25:42.098245  - bootm 0x01080000 0x08000000 0x01070000
  268 21:25:42.098773  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  270 21:25:42.100450  start: 2.3 connect-device (timeout 00:05:00) [common]
  271 21:25:42.100934  [common] connect-device Connecting to device using 'telnet conserv1 3007'
  272 21:25:42.116213  Setting prompt string to ['lava-test: # ']
  273 21:25:42.117793  end: 2.3 connect-device (duration 00:00:00) [common]
  274 21:25:42.118440  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  275 21:25:42.119023  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  276 21:25:42.119588  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  277 21:25:42.120862  Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
  278 21:25:42.158147  >> OK - accepted request

  279 21:25:42.160402  Returned 0 in 0 seconds
  280 21:25:42.261593  end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
  282 21:25:42.263341  end: 2.4.1 reset-device (duration 00:00:00) [common]
  283 21:25:42.263948  start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
  284 21:25:42.264559  Setting prompt string to ['Hit any key to stop autoboot']
  285 21:25:42.265059  bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
  286 21:25:42.266783  Trying 192.168.56.21...
  287 21:25:42.267308  Connected to conserv1.
  288 21:25:42.267772  Escape character is '^]'.
  289 21:25:42.268277  
  290 21:25:42.268756  ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
  291 21:25:42.269219  
  292 21:25:54.314275  G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  293 21:25:54.314939  bl2_stage_init 0x01
  294 21:25:54.315407  bl2_stage_init 0x81
  295 21:25:54.319775  hw id: 0x0000 - pwm id 0x01
  296 21:25:54.320297  bl2_stage_init 0xc1
  297 21:25:54.320751  bl2_stage_init 0x02
  298 21:25:54.321195  
  299 21:25:54.325283  L0:00000000
  300 21:25:54.325771  L1:20000703
  301 21:25:54.326203  L2:00008067
  302 21:25:54.326627  L3:14000000
  303 21:25:54.328217  B2:00402000
  304 21:25:54.328681  B1:e0f83180
  305 21:25:54.329107  
  306 21:25:54.329537  TE: 58124
  307 21:25:54.329963  
  308 21:25:54.339317  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  309 21:25:54.339794  
  310 21:25:54.340265  Board ID = 1
  311 21:25:54.340696  Set A53 clk to 24M
  312 21:25:54.341123  Set A73 clk to 24M
  313 21:25:54.344970  Set clk81 to 24M
  314 21:25:54.345432  A53 clk: 1200 MHz
  315 21:25:54.345859  A73 clk: 1200 MHz
  316 21:25:54.350516  CLK81: 166.6M
  317 21:25:54.350979  smccc: 00012a92
  318 21:25:54.356167  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  319 21:25:54.356632  board id: 1
  320 21:25:54.361755  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  321 21:25:54.375323  fw parse done
  322 21:25:54.381285  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  323 21:25:54.423053  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  324 21:25:54.434867  PIEI prepare done
  325 21:25:54.435330  fastboot data load
  326 21:25:54.435766  fastboot data verify
  327 21:25:54.440476  verify result: 266
  328 21:25:54.446060  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  329 21:25:54.446526  LPDDR4 probe
  330 21:25:54.446961  ddr clk to 1584MHz
  331 21:25:54.454033  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  332 21:25:54.491326  
  333 21:25:54.491882  dmc_version 0001
  334 21:25:54.498006  Check phy result
  335 21:25:54.503926  INFO : End of CA training
  336 21:25:54.504432  INFO : End of initialization
  337 21:25:54.509446  INFO : Training has run successfully!
  338 21:25:54.509913  Check phy result
  339 21:25:54.515040  INFO : End of initialization
  340 21:25:54.515501  INFO : End of read enable training
  341 21:25:54.520660  INFO : End of fine write leveling
  342 21:25:54.526231  INFO : End of Write leveling coarse delay
  343 21:25:54.526690  INFO : Training has run successfully!
  344 21:25:54.527123  Check phy result
  345 21:25:54.531904  INFO : End of initialization
  346 21:25:54.532395  INFO : End of read dq deskew training
  347 21:25:54.537447  INFO : End of MPR read delay center optimization
  348 21:25:54.543066  INFO : End of write delay center optimization
  349 21:25:54.548661  INFO : End of read delay center optimization
  350 21:25:54.549127  INFO : End of max read latency training
  351 21:25:54.554244  INFO : Training has run successfully!
  352 21:25:54.554704  1D training succeed
  353 21:25:54.563438  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  354 21:25:54.611081  Check phy result
  355 21:25:54.611675  INFO : End of initialization
  356 21:25:54.632651  INFO : End of 2D read delay Voltage center optimization
  357 21:25:54.652784  INFO : End of 2D read delay Voltage center optimization
  358 21:25:54.704666  INFO : End of 2D write delay Voltage center optimization
  359 21:25:54.754019  INFO : End of 2D write delay Voltage center optimization
  360 21:25:54.759411  INFO : Training has run successfully!
  361 21:25:54.759880  
  362 21:25:54.760373  channel==0
  363 21:25:54.765013  RxClkDly_Margin_A0==88 ps 9
  364 21:25:54.765504  TxDqDly_Margin_A0==98 ps 10
  365 21:25:54.770623  RxClkDly_Margin_A1==88 ps 9
  366 21:25:54.771082  TxDqDly_Margin_A1==98 ps 10
  367 21:25:54.771575  TrainedVREFDQ_A0==74
  368 21:25:54.776234  TrainedVREFDQ_A1==74
  369 21:25:54.776707  VrefDac_Margin_A0==25
  370 21:25:54.777137  DeviceVref_Margin_A0==40
  371 21:25:54.781819  VrefDac_Margin_A1==25
  372 21:25:54.782280  DeviceVref_Margin_A1==40
  373 21:25:54.782714  
  374 21:25:54.783144  
  375 21:25:54.787419  channel==1
  376 21:25:54.787877  RxClkDly_Margin_A0==98 ps 10
  377 21:25:54.788346  TxDqDly_Margin_A0==88 ps 9
  378 21:25:54.793008  RxClkDly_Margin_A1==88 ps 9
  379 21:25:54.793467  TxDqDly_Margin_A1==88 ps 9
  380 21:25:54.798620  TrainedVREFDQ_A0==77
  381 21:25:54.799086  TrainedVREFDQ_A1==77
  382 21:25:54.799521  VrefDac_Margin_A0==22
  383 21:25:54.804197  DeviceVref_Margin_A0==37
  384 21:25:54.804661  VrefDac_Margin_A1==24
  385 21:25:54.809959  DeviceVref_Margin_A1==37
  386 21:25:54.810412  
  387 21:25:54.810846   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  388 21:25:54.811275  
  389 21:25:54.843404  soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
  390 21:25:54.843954  2D training succeed
  391 21:25:54.849012  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  392 21:25:54.854597  auto size-- 65535DDR cs0 size: 2048MB
  393 21:25:54.855058  DDR cs1 size: 2048MB
  394 21:25:54.860239  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  395 21:25:54.860699  cs0 DataBus test pass
  396 21:25:54.865809  cs1 DataBus test pass
  397 21:25:54.866268  cs0 AddrBus test pass
  398 21:25:54.866699  cs1 AddrBus test pass
  399 21:25:54.867129  
  400 21:25:54.871371  100bdlr_step_size ps== 420
  401 21:25:54.871891  result report
  402 21:25:54.877032  boot times 0Enable ddr reg access
  403 21:25:54.882284  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  404 21:25:54.895821  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  405 21:25:55.467788  0.0;M3 CHK:0;cm4_sp_mode 0
  406 21:25:55.468469  MVN_1=0x00000000
  407 21:25:55.473222  MVN_2=0x00000000
  408 21:25:55.479005  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  409 21:25:55.479530  OPS=0x10
  410 21:25:55.480019  ring efuse init
  411 21:25:55.480467  chipver efuse init
  412 21:25:55.484565  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  413 21:25:55.490147  [0.018961 Inits done]
  414 21:25:55.490622  secure task start!
  415 21:25:55.491069  high task start!
  416 21:25:55.494829  low task start!
  417 21:25:55.495299  run into bl31
  418 21:25:55.501406  NOTICE:  BL31: v1.3(release):4fc40b1
  419 21:25:55.509207  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  420 21:25:55.509694  NOTICE:  BL31: G12A normal boot!
  421 21:25:55.535101  NOTICE:  BL31: BL33 decompress pass
  422 21:25:55.540814  ERROR:   Error initializing runtime service opteed_fast
  423 21:25:56.773840  
  424 21:25:56.774494  
  425 21:25:56.782281  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  426 21:25:56.782828  
  427 21:25:56.783288  Model: Libre Computer AML-A311D-CC Alta
  428 21:25:56.990794  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  429 21:25:57.013035  DRAM:  2 GiB (effective 3.8 GiB)
  430 21:25:57.156865  Core:  408 devices, 31 uclasses, devicetree: separate
  431 21:25:57.162652  WDT:   Not starting watchdog@f0d0
  432 21:25:57.195045  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  433 21:25:57.207433  Loading Environment from FAT... Card did not respond to voltage select! : -110
  434 21:25:57.212425  ** Bad device specification mmc 0 **
  435 21:25:57.222746  Card did not respond to voltage select! : -110
  436 21:25:57.229805  ** Bad device specification mmc 0 **
  437 21:25:57.230311  Couldn't find partition mmc 0
  438 21:25:57.238762  Card did not respond to voltage select! : -110
  439 21:25:57.244334  ** Bad device specification mmc 0 **
  440 21:25:57.244827  Couldn't find partition mmc 0
  441 21:25:57.248317  Error: could not access storage.
  442 21:25:58.514686  G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  443 21:25:58.515331  bl2_stage_init 0x01
  444 21:25:58.515800  bl2_stage_init 0x81
  445 21:25:58.520229  hw id: 0x0000 - pwm id 0x01
  446 21:25:58.520709  bl2_stage_init 0xc1
  447 21:25:58.521155  bl2_stage_init 0x02
  448 21:25:58.521597  
  449 21:25:58.525792  L0:00000000
  450 21:25:58.526257  L1:20000703
  451 21:25:58.526700  L2:00008067
  452 21:25:58.527140  L3:14000000
  453 21:25:58.531390  B2:00402000
  454 21:25:58.531857  B1:e0f83180
  455 21:25:58.532341  
  456 21:25:58.532788  TE: 58159
  457 21:25:58.533235  
  458 21:25:58.537011  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  459 21:25:58.537488  
  460 21:25:58.537937  Board ID = 1
  461 21:25:58.542596  Set A53 clk to 24M
  462 21:25:58.543060  Set A73 clk to 24M
  463 21:25:58.543504  Set clk81 to 24M
  464 21:25:58.548175  A53 clk: 1200 MHz
  465 21:25:58.548646  A73 clk: 1200 MHz
  466 21:25:58.549090  CLK81: 166.6M
  467 21:25:58.549525  smccc: 00012ab4
  468 21:25:58.553781  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  469 21:25:58.559392  board id: 1
  470 21:25:58.565289  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  471 21:25:58.575960  fw parse done
  472 21:25:58.580940  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  473 21:25:58.624547  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  474 21:25:58.635447  PIEI prepare done
  475 21:25:58.635919  fastboot data load
  476 21:25:58.636417  fastboot data verify
  477 21:25:58.641093  verify result: 266
  478 21:25:58.646660  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  479 21:25:58.647126  LPDDR4 probe
  480 21:25:58.647571  ddr clk to 1584MHz
  481 21:25:58.654634  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  482 21:25:58.691924  
  483 21:25:58.692458  dmc_version 0001
  484 21:25:58.698332  Check phy result
  485 21:25:58.704462  INFO : End of CA training
  486 21:25:58.704932  INFO : End of initialization
  487 21:25:58.710043  INFO : Training has run successfully!
  488 21:25:58.710506  Check phy result
  489 21:25:58.715629  INFO : End of initialization
  490 21:25:58.716125  INFO : End of read enable training
  491 21:25:58.721236  INFO : End of fine write leveling
  492 21:25:58.726804  INFO : End of Write leveling coarse delay
  493 21:25:58.727266  INFO : Training has run successfully!
  494 21:25:58.727708  Check phy result
  495 21:25:58.732439  INFO : End of initialization
  496 21:25:58.732903  INFO : End of read dq deskew training
  497 21:25:58.738049  INFO : End of MPR read delay center optimization
  498 21:25:58.743638  INFO : End of write delay center optimization
  499 21:25:58.749240  INFO : End of read delay center optimization
  500 21:25:58.749705  INFO : End of max read latency training
  501 21:25:58.754819  INFO : Training has run successfully!
  502 21:25:58.755284  1D training succeed
  503 21:25:58.764070  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  504 21:25:58.811649  Check phy result
  505 21:25:58.812188  INFO : End of initialization
  506 21:25:58.833239  INFO : End of 2D read delay Voltage center optimization
  507 21:25:58.852553  INFO : End of 2D read delay Voltage center optimization
  508 21:25:58.904402  INFO : End of 2D write delay Voltage center optimization
  509 21:25:58.953599  INFO : End of 2D write delay Voltage center optimization
  510 21:25:58.959230  INFO : Training has run successfully!
  511 21:25:58.959700  
  512 21:25:58.960203  channel==0
  513 21:25:58.964748  RxClkDly_Margin_A0==88 ps 9
  514 21:25:58.965215  TxDqDly_Margin_A0==98 ps 10
  515 21:25:58.970451  RxClkDly_Margin_A1==88 ps 9
  516 21:25:58.970931  TxDqDly_Margin_A1==98 ps 10
  517 21:25:58.971379  TrainedVREFDQ_A0==74
  518 21:25:58.975946  TrainedVREFDQ_A1==74
  519 21:25:58.976443  VrefDac_Margin_A0==25
  520 21:25:58.976887  DeviceVref_Margin_A0==40
  521 21:25:58.981556  VrefDac_Margin_A1==25
  522 21:25:58.982027  DeviceVref_Margin_A1==40
  523 21:25:58.982469  
  524 21:25:58.982906  
  525 21:25:58.987198  channel==1
  526 21:25:58.987653  RxClkDly_Margin_A0==98 ps 10
  527 21:25:58.988127  TxDqDly_Margin_A0==88 ps 9
  528 21:25:58.992786  RxClkDly_Margin_A1==88 ps 9
  529 21:25:58.993343  TxDqDly_Margin_A1==88 ps 9
  530 21:25:58.998459  TrainedVREFDQ_A0==76
  531 21:25:58.998954  TrainedVREFDQ_A1==77
  532 21:25:58.999412  VrefDac_Margin_A0==23
  533 21:25:59.003958  DeviceVref_Margin_A0==38
  534 21:25:59.004459  VrefDac_Margin_A1==24
  535 21:25:59.009558  DeviceVref_Margin_A1==37
  536 21:25:59.010031  
  537 21:25:59.010482   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  538 21:25:59.010925  
  539 21:25:59.043251  soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
  540 21:25:59.043765  2D training succeed
  541 21:25:59.048761  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  542 21:25:59.054496  auto size-- 65535DDR cs0 size: 2048MB
  543 21:25:59.054971  DDR cs1 size: 2048MB
  544 21:25:59.060030  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  545 21:25:59.060509  cs0 DataBus test pass
  546 21:25:59.065544  cs1 DataBus test pass
  547 21:25:59.066011  cs0 AddrBus test pass
  548 21:25:59.066455  cs1 AddrBus test pass
  549 21:25:59.066895  
  550 21:25:59.071224  100bdlr_step_size ps== 420
  551 21:25:59.071700  result report
  552 21:25:59.076756  boot times 0Enable ddr reg access
  553 21:25:59.082020  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  554 21:25:59.095571  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  555 21:25:59.667668  0.0;M3 CHK:0;cm4_sp_mode 0
  556 21:25:59.668309  MVN_1=0x00000000
  557 21:25:59.673220  MVN_2=0x00000000
  558 21:25:59.678979  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  559 21:25:59.679486  OPS=0x10
  560 21:25:59.679958  ring efuse init
  561 21:25:59.680461  chipver efuse init
  562 21:25:59.684540  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  563 21:25:59.690040  [0.018961 Inits done]
  564 21:25:59.690507  secure task start!
  565 21:25:59.690935  high task start!
  566 21:25:59.694884  low task start!
  567 21:25:59.695378  run into bl31
  568 21:25:59.701294  NOTICE:  BL31: v1.3(release):4fc40b1
  569 21:25:59.709073  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  570 21:25:59.709546  NOTICE:  BL31: G12A normal boot!
  571 21:25:59.734396  NOTICE:  BL31: BL33 decompress pass
  572 21:25:59.740171  ERROR:   Error initializing runtime service opteed_fast
  573 21:26:00.973169  
  574 21:26:00.973821  
  575 21:26:00.981620  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  576 21:26:00.982121  
  577 21:26:00.982584  Model: Libre Computer AML-A311D-CC Alta
  578 21:26:01.190157  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  579 21:26:01.213384  DRAM:  2 GiB (effective 3.8 GiB)
  580 21:26:01.356461  Core:  408 devices, 31 uclasses, devicetree: separate
  581 21:26:01.362255  WDT:   Not starting watchdog@f0d0
  582 21:26:01.394593  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  583 21:26:01.407001  Loading Environment from FAT... Card did not respond to voltage select! : -110
  584 21:26:01.412084  ** Bad device specification mmc 0 **
  585 21:26:01.422261  Card did not respond to voltage select! : -110
  586 21:26:01.430083  ** Bad device specification mmc 0 **
  587 21:26:01.430559  Couldn't find partition mmc 0
  588 21:26:01.438189  Card did not respond to voltage select! : -110
  589 21:26:01.443689  ** Bad device specification mmc 0 **
  590 21:26:01.444210  Couldn't find partition mmc 0
  591 21:26:01.448779  Error: could not access storage.
  592 21:26:01.791449  Net:   eth0: ethernet@ff3f0000
  593 21:26:01.792070  starting USB...
  594 21:26:02.043193  Bus usb@ff500000: Register 3000140 NbrPorts 3
  595 21:26:02.043772  Starting the controller
  596 21:26:02.050294  USB XHCI 1.10
  597 21:26:03.763475  scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  598 21:26:03.764187  bl2_stage_init 0x01
  599 21:26:03.764663  bl2_stage_init 0x81
  600 21:26:03.768884  hw id: 0x0000 - pwm id 0x01
  601 21:26:03.769380  bl2_stage_init 0xc1
  602 21:26:03.769836  bl2_stage_init 0x02
  603 21:26:03.770286  
  604 21:26:03.774594  L0:00000000
  605 21:26:03.775097  L1:20000703
  606 21:26:03.775550  L2:00008067
  607 21:26:03.776028  L3:14000000
  608 21:26:03.780165  B2:00402000
  609 21:26:03.780695  B1:e0f83180
  610 21:26:03.781220  
  611 21:26:03.781707  TE: 58124
  612 21:26:03.782164  
  613 21:26:03.785759  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  614 21:26:03.786304  
  615 21:26:03.786767  Board ID = 1
  616 21:26:03.791425  Set A53 clk to 24M
  617 21:26:03.791935  Set A73 clk to 24M
  618 21:26:03.792428  Set clk81 to 24M
  619 21:26:03.796891  A53 clk: 1200 MHz
  620 21:26:03.797439  A73 clk: 1200 MHz
  621 21:26:03.797896  CLK81: 166.6M
  622 21:26:03.798336  smccc: 00012a91
  623 21:26:03.802509  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  624 21:26:03.808131  board id: 1
  625 21:26:03.814063  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  626 21:26:03.824662  fw parse done
  627 21:26:03.830633  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  628 21:26:03.873137  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  629 21:26:03.884266  PIEI prepare done
  630 21:26:03.884855  fastboot data load
  631 21:26:03.885339  fastboot data verify
  632 21:26:03.889657  verify result: 266
  633 21:26:03.895244  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  634 21:26:03.895758  LPDDR4 probe
  635 21:26:03.896258  ddr clk to 1584MHz
  636 21:26:03.903216  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  637 21:26:03.940502  
  638 21:26:03.941156  dmc_version 0001
  639 21:26:03.947118  Check phy result
  640 21:26:03.952955  INFO : End of CA training
  641 21:26:03.953289  INFO : End of initialization
  642 21:26:03.958511  INFO : Training has run successfully!
  643 21:26:03.958952  Check phy result
  644 21:26:03.964229  INFO : End of initialization
  645 21:26:03.964561  INFO : End of read enable training
  646 21:26:03.969719  INFO : End of fine write leveling
  647 21:26:03.975362  INFO : End of Write leveling coarse delay
  648 21:26:03.975843  INFO : Training has run successfully!
  649 21:26:03.976132  Check phy result
  650 21:26:03.980959  INFO : End of initialization
  651 21:26:03.981421  INFO : End of read dq deskew training
  652 21:26:03.986538  INFO : End of MPR read delay center optimization
  653 21:26:03.992241  INFO : End of write delay center optimization
  654 21:26:03.997778  INFO : End of read delay center optimization
  655 21:26:03.998139  INFO : End of max read latency training
  656 21:26:04.003379  INFO : Training has run successfully!
  657 21:26:04.003886  1D training succeed
  658 21:26:04.012543  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  659 21:26:04.060301  Check phy result
  660 21:26:04.060974  INFO : End of initialization
  661 21:26:04.081812  INFO : End of 2D read delay Voltage center optimization
  662 21:26:04.101600  INFO : End of 2D read delay Voltage center optimization
  663 21:26:04.153780  INFO : End of 2D write delay Voltage center optimization
  664 21:26:04.203001  INFO : End of 2D write delay Voltage center optimization
  665 21:26:04.208551  INFO : Training has run successfully!
  666 21:26:04.208897  
  667 21:26:04.209110  channel==0
  668 21:26:04.214148  RxClkDly_Margin_A0==88 ps 9
  669 21:26:04.214628  TxDqDly_Margin_A0==98 ps 10
  670 21:26:04.219730  RxClkDly_Margin_A1==88 ps 9
  671 21:26:04.220231  TxDqDly_Margin_A1==98 ps 10
  672 21:26:04.220484  TrainedVREFDQ_A0==74
  673 21:26:04.225323  TrainedVREFDQ_A1==74
  674 21:26:04.225666  VrefDac_Margin_A0==25
  675 21:26:04.225875  DeviceVref_Margin_A0==40
  676 21:26:04.230905  VrefDac_Margin_A1==25
  677 21:26:04.231356  DeviceVref_Margin_A1==40
  678 21:26:04.231675  
  679 21:26:04.232012  
  680 21:26:04.236528  channel==1
  681 21:26:04.236981  RxClkDly_Margin_A0==98 ps 10
  682 21:26:04.237220  TxDqDly_Margin_A0==88 ps 9
  683 21:26:04.242129  RxClkDly_Margin_A1==88 ps 9
  684 21:26:04.242456  TxDqDly_Margin_A1==108 ps 11
  685 21:26:04.247742  TrainedVREFDQ_A0==77
  686 21:26:04.248231  TrainedVREFDQ_A1==77
  687 21:26:04.248552  VrefDac_Margin_A0==22
  688 21:26:04.253311  DeviceVref_Margin_A0==37
  689 21:26:04.253633  VrefDac_Margin_A1==24
  690 21:26:04.258916  DeviceVref_Margin_A1==37
  691 21:26:04.259361  
  692 21:26:04.259682   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  693 21:26:04.264523  
  694 21:26:04.292489  soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
  695 21:26:04.292879  2D training succeed
  696 21:26:04.298158  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  697 21:26:04.303694  auto size-- 65535DDR cs0 size: 2048MB
  698 21:26:04.304147  DDR cs1 size: 2048MB
  699 21:26:04.309325  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  700 21:26:04.309630  cs0 DataBus test pass
  701 21:26:04.314926  cs1 DataBus test pass
  702 21:26:04.315368  cs0 AddrBus test pass
  703 21:26:04.315684  cs1 AddrBus test pass
  704 21:26:04.316004  
  705 21:26:04.320551  100bdlr_step_size ps== 420
  706 21:26:04.320877  result report
  707 21:26:04.326121  boot times 0Enable ddr reg access
  708 21:26:04.331540  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  709 21:26:04.344055  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  710 21:26:04.917021  0.0;M3 CHK:0;cm4_sp_mode 0
  711 21:26:04.917651  MVN_1=0x00000000
  712 21:26:04.922502  MVN_2=0x00000000
  713 21:26:04.928359  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  714 21:26:04.928924  OPS=0x10
  715 21:26:04.929329  ring efuse init
  716 21:26:04.929719  chipver efuse init
  717 21:26:04.933847  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  718 21:26:04.939442  [0.018961 Inits done]
  719 21:26:04.939888  secure task start!
  720 21:26:04.940334  high task start!
  721 21:26:04.943453  low task start!
  722 21:26:04.943946  run into bl31
  723 21:26:04.950745  NOTICE:  BL31: v1.3(release):4fc40b1
  724 21:26:04.958556  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  725 21:26:04.959031  NOTICE:  BL31: G12A normal boot!
  726 21:26:04.984156  NOTICE:  BL31: BL33 decompress pass
  727 21:26:04.989563  ERROR:   Error initializing runtime service opteed_fast
  728 21:26:06.222445  
  729 21:26:06.222888  
  730 21:26:06.230769  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  731 21:26:06.231093  
  732 21:26:06.231310  Model: Libre Computer AML-A311D-CC Alta
  733 21:26:06.439158  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  734 21:26:06.462615  DRAM:  2 GiB (effective 3.8 GiB)
  735 21:26:06.605588  Core:  408 devices, 31 uclasses, devicetree: separate
  736 21:26:06.611361  WDT:   Not starting watchdog@f0d0
  737 21:26:06.643687  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  738 21:26:06.656148  Loading Environment from FAT... Card did not respond to voltage select! : -110
  739 21:26:06.661100  ** Bad device specification mmc 0 **
  740 21:26:06.671513  Card did not respond to voltage select! : -110
  741 21:26:06.679073  ** Bad device specification mmc 0 **
  742 21:26:06.679385  Couldn't find partition mmc 0
  743 21:26:06.687513  Card did not respond to voltage select! : -110
  744 21:26:06.692918  ** Bad device specification mmc 0 **
  745 21:26:06.693235  Couldn't find partition mmc 0
  746 21:26:06.697965  Error: could not access storage.
  747 21:26:07.040701  Net:   eth0: ethernet@ff3f0000
  748 21:26:07.041114  starting USB...
  749 21:26:07.293338  Bus usb@ff500000: Register 3000140 NbrPorts 3
  750 21:26:07.293765  Starting the controller
  751 21:26:07.300276  USB XHCI 1.10
  752 21:26:09.465076  scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  753 21:26:09.465508  bl2_stage_init 0x01
  754 21:26:09.465731  bl2_stage_init 0x81
  755 21:26:09.469695  hw id: 0x0000 - pwm id 0x01
  756 21:26:09.470125  bl2_stage_init 0xc1
  757 21:26:09.470457  bl2_stage_init 0x02
  758 21:26:09.470774  
  759 21:26:09.475222  L0:00000000
  760 21:26:09.475619  L1:20000703
  761 21:26:09.475860  L2:00008067
  762 21:26:09.476105  L3:14000000
  763 21:26:09.480967  B2:00402000
  764 21:26:09.481254  B1:e0f83180
  765 21:26:09.481470  
  766 21:26:09.481676  TE: 58124
  767 21:26:09.481881  
  768 21:26:09.486617  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  769 21:26:09.487028  
  770 21:26:09.487359  Board ID = 1
  771 21:26:09.492036  Set A53 clk to 24M
  772 21:26:09.492432  Set A73 clk to 24M
  773 21:26:09.492761  Set clk81 to 24M
  774 21:26:09.498132  A53 clk: 1200 MHz
  775 21:26:09.498546  A73 clk: 1200 MHz
  776 21:26:09.498885  CLK81: 166.6M
  777 21:26:09.499118  smccc: 00012a91
  778 21:26:09.503344  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  779 21:26:09.508901  board id: 1
  780 21:26:09.515307  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  781 21:26:09.525374  fw parse done
  782 21:26:09.531337  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  783 21:26:09.574067  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  784 21:26:09.585362  PIEI prepare done
  785 21:26:09.585696  fastboot data load
  786 21:26:09.585917  fastboot data verify
  787 21:26:09.590499  verify result: 266
  788 21:26:09.596057  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  789 21:26:09.596346  LPDDR4 probe
  790 21:26:09.596566  ddr clk to 1584MHz
  791 21:26:09.604122  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  792 21:26:09.640793  
  793 21:26:09.641166  dmc_version 0001
  794 21:26:09.648154  Check phy result
  795 21:26:09.653890  INFO : End of CA training
  796 21:26:09.654283  INFO : End of initialization
  797 21:26:09.659443  INFO : Training has run successfully!
  798 21:26:09.659718  Check phy result
  799 21:26:09.665043  INFO : End of initialization
  800 21:26:09.665445  INFO : End of read enable training
  801 21:26:09.668378  INFO : End of fine write leveling
  802 21:26:09.674049  INFO : End of Write leveling coarse delay
  803 21:26:09.679550  INFO : Training has run successfully!
  804 21:26:09.679808  Check phy result
  805 21:26:09.680040  INFO : End of initialization
  806 21:26:09.685183  INFO : End of read dq deskew training
  807 21:26:09.688589  INFO : End of MPR read delay center optimization
  808 21:26:09.694186  INFO : End of write delay center optimization
  809 21:26:09.699777  INFO : End of read delay center optimization
  810 21:26:09.700070  INFO : End of max read latency training
  811 21:26:09.705398  INFO : Training has run successfully!
  812 21:26:09.705694  1D training succeed
  813 21:26:09.713550  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  814 21:26:09.761186  Check phy result
  815 21:26:09.761698  INFO : End of initialization
  816 21:26:09.782662  INFO : End of 2D read delay Voltage center optimization
  817 21:26:09.802814  INFO : End of 2D read delay Voltage center optimization
  818 21:26:09.854877  INFO : End of 2D write delay Voltage center optimization
  819 21:26:09.904196  INFO : End of 2D write delay Voltage center optimization
  820 21:26:09.909644  INFO : Training has run successfully!
  821 21:26:09.910166  
  822 21:26:09.910546  channel==0
  823 21:26:09.915183  RxClkDly_Margin_A0==88 ps 9
  824 21:26:09.915700  TxDqDly_Margin_A0==98 ps 10
  825 21:26:09.920683  RxClkDly_Margin_A1==88 ps 9
  826 21:26:09.921189  TxDqDly_Margin_A1==88 ps 9
  827 21:26:09.921666  TrainedVREFDQ_A0==74
  828 21:26:09.926412  TrainedVREFDQ_A1==74
  829 21:26:09.926952  VrefDac_Margin_A0==25
  830 21:26:09.927409  DeviceVref_Margin_A0==40
  831 21:26:09.931914  VrefDac_Margin_A1==25
  832 21:26:09.932471  DeviceVref_Margin_A1==40
  833 21:26:09.932906  
  834 21:26:09.933338  
  835 21:26:09.933766  channel==1
  836 21:26:09.937522  RxClkDly_Margin_A0==98 ps 10
  837 21:26:09.937991  TxDqDly_Margin_A0==88 ps 9
  838 21:26:09.943146  RxClkDly_Margin_A1==88 ps 9
  839 21:26:09.943607  TxDqDly_Margin_A1==88 ps 9
  840 21:26:09.948762  TrainedVREFDQ_A0==77
  841 21:26:09.949225  TrainedVREFDQ_A1==77
  842 21:26:09.949657  VrefDac_Margin_A0==22
  843 21:26:09.954249  DeviceVref_Margin_A0==37
  844 21:26:09.954713  VrefDac_Margin_A1==24
  845 21:26:09.959869  DeviceVref_Margin_A1==37
  846 21:26:09.960348  
  847 21:26:09.960781   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  848 21:26:09.961208  
  849 21:26:09.993504  soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
  850 21:26:09.994129  2D training succeed
  851 21:26:09.999163  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  852 21:26:10.004662  auto size-- 65535DDR cs0 size: 2048MB
  853 21:26:10.005164  DDR cs1 size: 2048MB
  854 21:26:10.010465  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  855 21:26:10.011025  cs0 DataBus test pass
  856 21:26:10.015924  cs1 DataBus test pass
  857 21:26:10.016448  cs0 AddrBus test pass
  858 21:26:10.016886  cs1 AddrBus test pass
  859 21:26:10.017311  
  860 21:26:10.021511  100bdlr_step_size ps== 420
  861 21:26:10.021988  result report
  862 21:26:10.027143  boot times 0Enable ddr reg access
  863 21:26:10.032286  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  864 21:26:10.045841  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  865 21:26:10.617799  0.0;M3 CHK:0;cm4_sp_mode 0
  866 21:26:10.618471  MVN_1=0x00000000
  867 21:26:10.623225  MVN_2=0x00000000
  868 21:26:10.628995  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  869 21:26:10.629502  OPS=0x10
  870 21:26:10.629961  ring efuse init
  871 21:26:10.630411  chipver efuse init
  872 21:26:10.634587  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  873 21:26:10.640239  [0.018961 Inits done]
  874 21:26:10.640746  secure task start!
  875 21:26:10.641195  high task start!
  876 21:26:10.644785  low task start!
  877 21:26:10.645280  run into bl31
  878 21:26:10.651431  NOTICE:  BL31: v1.3(release):4fc40b1
  879 21:26:10.659232  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  880 21:26:10.659744  NOTICE:  BL31: G12A normal boot!
  881 21:26:10.684602  NOTICE:  BL31: BL33 decompress pass
  882 21:26:10.690058  ERROR:   Error initializing runtime service opteed_fast
  883 21:26:11.923090  
  884 21:26:11.923789  
  885 21:26:11.930877  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  886 21:26:11.931489  
  887 21:26:11.931943  Model: Libre Computer AML-A311D-CC Alta
  888 21:26:12.140042  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  889 21:26:12.163518  DRAM:  2 GiB (effective 3.8 GiB)
  890 21:26:12.306620  Core:  408 devices, 31 uclasses, devicetree: separate
  891 21:26:12.312274  WDT:   Not starting watchdog@f0d0
  892 21:26:12.344509  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  893 21:26:12.356920  Loading Environment from FAT... Card did not respond to voltage select! : -110
  894 21:26:12.362090  ** Bad device specification mmc 0 **
  895 21:26:12.372403  Card did not respond to voltage select! : -110
  896 21:26:12.380069  ** Bad device specification mmc 0 **
  897 21:26:12.380649  Couldn't find partition mmc 0
  898 21:26:12.388340  Card did not respond to voltage select! : -110
  899 21:26:12.393869  ** Bad device specification mmc 0 **
  900 21:26:12.394403  Couldn't find partition mmc 0
  901 21:26:12.398895  Error: could not access storage.
  902 21:26:12.742516  Net:   eth0: ethernet@ff3f0000
  903 21:26:12.743182  starting USB...
  904 21:26:12.994250  Bus usb@ff500000: Register 3000140 NbrPorts 3
  905 21:26:12.994879  Starting the controller
  906 21:26:13.001193  USB XHCI 1.10
  907 21:26:14.863359  scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  908 21:26:14.864068  bl2_stage_init 0x01
  909 21:26:14.864550  bl2_stage_init 0x81
  910 21:26:14.868982  hw id: 0x0000 - pwm id 0x01
  911 21:26:14.869537  bl2_stage_init 0xc1
  912 21:26:14.870010  bl2_stage_init 0x02
  913 21:26:14.870464  
  914 21:26:14.874621  L0:00000000
  915 21:26:14.875149  L1:20000703
  916 21:26:14.875613  L2:00008067
  917 21:26:14.876113  L3:14000000
  918 21:26:14.880128  B2:00402000
  919 21:26:14.880659  B1:e0f83180
  920 21:26:14.881110  
  921 21:26:14.881559  TE: 58159
  922 21:26:14.882001  
  923 21:26:14.885866  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  924 21:26:14.886416  
  925 21:26:14.886875  Board ID = 1
  926 21:26:14.891338  Set A53 clk to 24M
  927 21:26:14.891862  Set A73 clk to 24M
  928 21:26:14.892364  Set clk81 to 24M
  929 21:26:14.896936  A53 clk: 1200 MHz
  930 21:26:14.897463  A73 clk: 1200 MHz
  931 21:26:14.897915  CLK81: 166.6M
  932 21:26:14.898361  smccc: 00012ab5
  933 21:26:14.902524  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  934 21:26:14.908178  board id: 1
  935 21:26:14.913986  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  936 21:26:14.924679  fw parse done
  937 21:26:14.930666  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  938 21:26:14.973154  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  939 21:26:14.984096  PIEI prepare done
  940 21:26:14.984623  fastboot data load
  941 21:26:14.985068  fastboot data verify
  942 21:26:14.989873  verify result: 266
  943 21:26:14.995343  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  944 21:26:14.995847  LPDDR4 probe
  945 21:26:14.996325  ddr clk to 1584MHz
  946 21:26:15.003366  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  947 21:26:15.040606  
  948 21:26:15.041153  dmc_version 0001
  949 21:26:15.047262  Check phy result
  950 21:26:15.053158  INFO : End of CA training
  951 21:26:15.053675  INFO : End of initialization
  952 21:26:15.058930  INFO : Training has run successfully!
  953 21:26:15.059477  Check phy result
  954 21:26:15.064418  INFO : End of initialization
  955 21:26:15.064973  INFO : End of read enable training
  956 21:26:15.070044  INFO : End of fine write leveling
  957 21:26:15.075607  INFO : End of Write leveling coarse delay
  958 21:26:15.076164  INFO : Training has run successfully!
  959 21:26:15.076640  Check phy result
  960 21:26:15.081357  INFO : End of initialization
  961 21:26:15.081885  INFO : End of read dq deskew training
  962 21:26:15.087022  INFO : End of MPR read delay center optimization
  963 21:26:15.092481  INFO : End of write delay center optimization
  964 21:26:15.098039  INFO : End of read delay center optimization
  965 21:26:15.098563  INFO : End of max read latency training
  966 21:26:15.103704  INFO : Training has run successfully!
  967 21:26:15.104269  1D training succeed
  968 21:26:15.112844  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  969 21:26:15.160487  Check phy result
  970 21:26:15.161036  INFO : End of initialization
  971 21:26:15.182062  INFO : End of 2D read delay Voltage center optimization
  972 21:26:15.201335  INFO : End of 2D read delay Voltage center optimization
  973 21:26:15.253210  INFO : End of 2D write delay Voltage center optimization
  974 21:26:15.302524  INFO : End of 2D write delay Voltage center optimization
  975 21:26:15.308070  INFO : Training has run successfully!
  976 21:26:15.308595  
  977 21:26:15.309055  channel==0
  978 21:26:15.313672  RxClkDly_Margin_A0==88 ps 9
  979 21:26:15.314181  TxDqDly_Margin_A0==98 ps 10
  980 21:26:15.317089  RxClkDly_Margin_A1==88 ps 9
  981 21:26:15.317596  TxDqDly_Margin_A1==98 ps 10
  982 21:26:15.322767  TrainedVREFDQ_A0==74
  983 21:26:15.323291  TrainedVREFDQ_A1==76
  984 21:26:15.323752  VrefDac_Margin_A0==25
  985 21:26:15.328318  DeviceVref_Margin_A0==40
  986 21:26:15.328829  VrefDac_Margin_A1==25
  987 21:26:15.333867  DeviceVref_Margin_A1==38
  988 21:26:15.334375  
  989 21:26:15.334832  
  990 21:26:15.335278  channel==1
  991 21:26:15.335715  RxClkDly_Margin_A0==88 ps 9
  992 21:26:15.339469  TxDqDly_Margin_A0==88 ps 9
  993 21:26:15.340014  RxClkDly_Margin_A1==88 ps 9
  994 21:26:15.345103  TxDqDly_Margin_A1==88 ps 9
  995 21:26:15.345618  TrainedVREFDQ_A0==77
  996 21:26:15.346072  TrainedVREFDQ_A1==77
  997 21:26:15.350669  VrefDac_Margin_A0==23
  998 21:26:15.351186  DeviceVref_Margin_A0==37
  999 21:26:15.351635  VrefDac_Margin_A1==24
 1000 21:26:15.356231  DeviceVref_Margin_A1==37
 1001 21:26:15.356748  
 1002 21:26:15.361992   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
 1003 21:26:15.362519  
 1004 21:26:15.389954  soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
 1005 21:26:15.395331  2D training succeed
 1006 21:26:15.400927  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
 1007 21:26:15.401476  auto size-- 65535DDR cs0 size: 2048MB
 1008 21:26:15.406559  DDR cs1 size: 2048MB
 1009 21:26:15.407084  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
 1010 21:26:15.412126  cs0 DataBus test pass
 1011 21:26:15.412652  cs1 DataBus test pass
 1012 21:26:15.413102  cs0 AddrBus test pass
 1013 21:26:15.417742  cs1 AddrBus test pass
 1014 21:26:15.418264  
 1015 21:26:15.418717  100bdlr_step_size ps== 420
 1016 21:26:15.419170  result report
 1017 21:26:15.423305  boot times 0Enable ddr reg access
 1018 21:26:15.429863  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
 1019 21:26:15.443188  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
 1020 21:26:16.016233  0.0;M3 CHK:0;cm4_sp_mode 0
 1021 21:26:16.016909  MVN_1=0x00000000
 1022 21:26:16.021723  MVN_2=0x00000000
 1023 21:26:16.027418  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
 1024 21:26:16.028020  OPS=0x10
 1025 21:26:16.028502  ring efuse init
 1026 21:26:16.028954  chipver efuse init
 1027 21:26:16.033052  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
 1028 21:26:16.038627  [0.018961 Inits done]
 1029 21:26:16.039219  secure task start!
 1030 21:26:16.039676  high task start!
 1031 21:26:16.043207  low task start!
 1032 21:26:16.043782  run into bl31
 1033 21:26:16.049983  NOTICE:  BL31: v1.3(release):4fc40b1
 1034 21:26:16.057708  NOTICE:  BL31: Built : 15:58:17, May 22 2019
 1035 21:26:16.058309  NOTICE:  BL31: G12A normal boot!
 1036 21:26:16.083030  NOTICE:  BL31: BL33 decompress pass
 1037 21:26:16.088759  ERROR:   Error initializing runtime service opteed_fast
 1038 21:26:17.321571  
 1039 21:26:17.322220  
 1040 21:26:17.330011  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
 1041 21:26:17.330546  
 1042 21:26:17.331009  Model: Libre Computer AML-A311D-CC Alta
 1043 21:26:17.537432  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
 1044 21:26:17.560880  DRAM:  2 GiB (effective 3.8 GiB)
 1045 21:26:17.704819  Core:  408 devices, 31 uclasses, devicetree: separate
 1046 21:26:17.710246  WDT:   Not starting watchdog@f0d0
 1047 21:26:17.743012  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
 1048 21:26:17.755343  Loading Environment from FAT... Card did not respond to voltage select! : -110
 1049 21:26:17.760366  ** Bad device specification mmc 0 **
 1050 21:26:17.770727  Card did not respond to voltage select! : -110
 1051 21:26:17.777442  ** Bad device specification mmc 0 **
 1052 21:26:17.777978  Couldn't find partition mmc 0
 1053 21:26:17.786715  Card did not respond to voltage select! : -110
 1054 21:26:17.792232  ** Bad device specification mmc 0 **
 1055 21:26:17.792769  Couldn't find partition mmc 0
 1056 21:26:17.797312  Error: could not access storage.
 1057 21:26:18.139707  Net:   eth0: ethernet@ff3f0000
 1058 21:26:18.140388  starting USB...
 1059 21:26:18.391496  Bus usb@ff500000: Register 3000140 NbrPorts 3
 1060 21:26:18.392180  Starting the controller
 1061 21:26:18.398517  USB XHCI 1.10
 1062 21:26:19.952772  scanning bus usb@ff500000 for devices... 3 USB Device(s) found
 1063 21:26:19.961125         scanning usb for storage devices... 0 Storage Device(s) found
 1065 21:26:20.012785  Hit any key to stop autoboot:  1 
 1066 21:26:20.013636  end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
 1067 21:26:20.014335  start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
 1068 21:26:20.014846  Setting prompt string to ['=>']
 1069 21:26:20.015357  bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
 1070 21:26:20.028611   0 
 1071 21:26:20.029563  Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
 1072 21:26:20.030088  Sending with 10 millisecond of delay
 1074 21:26:21.164809  => setenv autoload no
 1075 21:26:21.175658  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
 1076 21:26:21.181057  setenv autoload no
 1077 21:26:21.181845  Sending with 10 millisecond of delay
 1079 21:26:22.979255  => setenv initrd_high 0xffffffff
 1080 21:26:22.989986  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
 1081 21:26:22.990515  setenv initrd_high 0xffffffff
 1082 21:26:22.990999  Sending with 10 millisecond of delay
 1084 21:26:24.607271  => setenv fdt_high 0xffffffff
 1085 21:26:24.618011  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
 1086 21:26:24.618711  setenv fdt_high 0xffffffff
 1087 21:26:24.619205  Sending with 10 millisecond of delay
 1089 21:26:24.910649  => dhcp
 1090 21:26:24.921405  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
 1091 21:26:24.921978  dhcp
 1092 21:26:24.922223  Speed: 1000, full duplex
 1093 21:26:24.922434  BOOTP broadcast 1
 1094 21:26:24.929242  DHCP client bound to address 192.168.6.27 (8 ms)
 1095 21:26:24.929754  Sending with 10 millisecond of delay
 1097 21:26:26.606482  => setenv serverip 192.168.6.2
 1098 21:26:26.617301  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
 1099 21:26:26.618163  setenv serverip 192.168.6.2
 1100 21:26:26.618898  Sending with 10 millisecond of delay
 1102 21:26:30.342705  => tftpboot 0x01080000 884205/tftp-deploy-ax4dfmn7/kernel/uImage
 1103 21:26:30.353505  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
 1104 21:26:30.354083  tftpboot 0x01080000 884205/tftp-deploy-ax4dfmn7/kernel/uImage
 1105 21:26:30.354347  Speed: 1000, full duplex
 1106 21:26:30.354567  Using ethernet@ff3f0000 device
 1107 21:26:30.356022  TFTP from server 192.168.6.2; our IP address is 192.168.6.27
 1108 21:26:30.361526  Filename '884205/tftp-deploy-ax4dfmn7/kernel/uImage'.
 1109 21:26:30.365403  Load address: 0x1080000
 1110 21:26:33.254624  Loading: *##################################################  43.6 MiB
 1111 21:26:33.255293  	 15.1 MiB/s
 1112 21:26:33.255771  done
 1113 21:26:33.259085  Bytes transferred = 45713984 (2b98a40 hex)
 1114 21:26:33.259939  Sending with 10 millisecond of delay
 1116 21:26:37.952140  => tftpboot 0x08000000 884205/tftp-deploy-ax4dfmn7/ramdisk/ramdisk.cpio.gz.uboot
 1117 21:26:37.962706  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
 1118 21:26:37.963244  tftpboot 0x08000000 884205/tftp-deploy-ax4dfmn7/ramdisk/ramdisk.cpio.gz.uboot
 1119 21:26:37.963489  Speed: 1000, full duplex
 1120 21:26:37.963706  Using ethernet@ff3f0000 device
 1121 21:26:37.965178  TFTP from server 192.168.6.2; our IP address is 192.168.6.27
 1122 21:26:37.977027  Filename '884205/tftp-deploy-ax4dfmn7/ramdisk/ramdisk.cpio.gz.uboot'.
 1123 21:26:37.977367  Load address: 0x8000000
 1124 21:26:44.616317  Loading: *################T ################################# UDP wrong checksum 00000005 000046f4
 1125 21:26:46.157921   UDP wrong checksum 000000ff 0000c25c
 1126 21:26:46.174373   UDP wrong checksum 000000ff 0000594f
 1127 21:26:49.618829  T  UDP wrong checksum 00000005 000046f4
 1128 21:26:59.620582  T T  UDP wrong checksum 00000005 000046f4
 1129 21:27:18.180319  T T T  UDP wrong checksum 000000ff 000048a1
 1130 21:27:18.221687   UDP wrong checksum 000000ff 0000d893
 1131 21:27:19.624597  T  UDP wrong checksum 00000005 000046f4
 1132 21:27:34.628945  T T 
 1133 21:27:34.629546  Retry count exceeded; starting again
 1135 21:27:34.630976  end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
 1138 21:27:34.632952  end: 2.4 uboot-commands (duration 00:01:53) [common]
 1140 21:27:34.634356  uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
 1142 21:27:34.635372  end: 2 uboot-action (duration 00:01:53) [common]
 1144 21:27:34.636901  Cleaning after the job
 1145 21:27:34.637436  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/884205/tftp-deploy-ax4dfmn7/ramdisk
 1146 21:27:34.638644  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/884205/tftp-deploy-ax4dfmn7/kernel
 1147 21:27:34.688431  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/884205/tftp-deploy-ax4dfmn7/dtb
 1148 21:27:34.689239  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/884205/tftp-deploy-ax4dfmn7/modules
 1149 21:27:34.711409  start: 4.1 power-off (timeout 00:00:30) [common]
 1150 21:27:34.712087  Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
 1151 21:27:34.745431  >> OK - accepted request

 1152 21:27:34.747883  Returned 0 in 0 seconds
 1153 21:27:34.848819  end: 4.1 power-off (duration 00:00:00) [common]
 1155 21:27:34.849780  start: 4.2 read-feedback (timeout 00:10:00) [common]
 1156 21:27:34.850437  Listened to connection for namespace 'common' for up to 1s
 1157 21:27:35.850569  Finalising connection for namespace 'common'
 1158 21:27:35.851268  Disconnecting from shell: Finalise
 1159 21:27:35.851778  => 
 1160 21:27:35.952751  end: 4.2 read-feedback (duration 00:00:01) [common]
 1161 21:27:35.953366  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/884205
 1162 21:27:36.272645  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/884205
 1163 21:27:36.273339  InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.