Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:24:43.774191 lava-dispatcher, installed at version: 2024.01
2 21:24:43.774986 start: 0 validate
3 21:24:43.775465 Start time: 2024-10-22 21:24:43.775435+00:00 (UTC)
4 21:24:43.776029 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:24:43.776580 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 21:24:43.812711 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:24:43.813283 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fv6.12-rc2-167-g902934bf5a62%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 21:24:43.851844 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:24:43.852516 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fv6.12-rc2-167-g902934bf5a62%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 21:24:44.899378 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:24:44.900038 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-sound%2Ffor-next%2Fv6.12-rc2-167-g902934bf5a62%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 21:24:44.938055 validate duration: 1.16
14 21:24:44.938962 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:24:44.939343 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:24:44.939811 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:24:44.940480 Not decompressing ramdisk as can be used compressed.
18 21:24:44.941059 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 21:24:44.941450 saving as /var/lib/lava/dispatcher/tmp/884215/tftp-deploy-l3s4s_rn/ramdisk/rootfs.cpio.gz
20 21:24:44.941849 total size: 8181887 (7 MB)
21 21:24:44.984866 progress 0 % (0 MB)
22 21:24:44.993215 progress 5 % (0 MB)
23 21:24:44.998813 progress 10 % (0 MB)
24 21:24:45.004778 progress 15 % (1 MB)
25 21:24:45.010232 progress 20 % (1 MB)
26 21:24:45.016055 progress 25 % (1 MB)
27 21:24:45.021502 progress 30 % (2 MB)
28 21:24:45.027234 progress 35 % (2 MB)
29 21:24:45.032610 progress 40 % (3 MB)
30 21:24:45.038414 progress 45 % (3 MB)
31 21:24:45.043778 progress 50 % (3 MB)
32 21:24:45.049646 progress 55 % (4 MB)
33 21:24:45.054963 progress 60 % (4 MB)
34 21:24:45.060787 progress 65 % (5 MB)
35 21:24:45.066163 progress 70 % (5 MB)
36 21:24:45.071859 progress 75 % (5 MB)
37 21:24:45.077216 progress 80 % (6 MB)
38 21:24:45.082949 progress 85 % (6 MB)
39 21:24:45.088320 progress 90 % (7 MB)
40 21:24:45.093832 progress 95 % (7 MB)
41 21:24:45.098764 progress 100 % (7 MB)
42 21:24:45.099447 7 MB downloaded in 0.16 s (49.52 MB/s)
43 21:24:45.100053 end: 1.1.1 http-download (duration 00:00:00) [common]
45 21:24:45.101019 end: 1.1 download-retry (duration 00:00:00) [common]
46 21:24:45.101343 start: 1.2 download-retry (timeout 00:10:00) [common]
47 21:24:45.101640 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 21:24:45.102134 downloading http://storage.kernelci.org/broonie-sound/for-next/v6.12-rc2-167-g902934bf5a62/arm64/defconfig/gcc-12/kernel/Image
49 21:24:45.102413 saving as /var/lib/lava/dispatcher/tmp/884215/tftp-deploy-l3s4s_rn/kernel/Image
50 21:24:45.102644 total size: 45713920 (43 MB)
51 21:24:45.102877 No compression specified
52 21:24:45.143998 progress 0 % (0 MB)
53 21:24:45.175643 progress 5 % (2 MB)
54 21:24:45.207435 progress 10 % (4 MB)
55 21:24:45.238065 progress 15 % (6 MB)
56 21:24:45.267500 progress 20 % (8 MB)
57 21:24:45.300298 progress 25 % (10 MB)
58 21:24:45.333614 progress 30 % (13 MB)
59 21:24:45.364163 progress 35 % (15 MB)
60 21:24:45.394943 progress 40 % (17 MB)
61 21:24:45.425364 progress 45 % (19 MB)
62 21:24:45.455918 progress 50 % (21 MB)
63 21:24:45.487468 progress 55 % (24 MB)
64 21:24:45.518066 progress 60 % (26 MB)
65 21:24:45.548847 progress 65 % (28 MB)
66 21:24:45.580973 progress 70 % (30 MB)
67 21:24:45.632288 progress 75 % (32 MB)
68 21:24:45.661407 progress 80 % (34 MB)
69 21:24:45.689665 progress 85 % (37 MB)
70 21:24:45.718225 progress 90 % (39 MB)
71 21:24:45.747046 progress 95 % (41 MB)
72 21:24:45.774907 progress 100 % (43 MB)
73 21:24:45.775425 43 MB downloaded in 0.67 s (64.80 MB/s)
74 21:24:45.775907 end: 1.2.1 http-download (duration 00:00:01) [common]
76 21:24:45.776753 end: 1.2 download-retry (duration 00:00:01) [common]
77 21:24:45.777027 start: 1.3 download-retry (timeout 00:09:59) [common]
78 21:24:45.777288 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 21:24:45.777746 downloading http://storage.kernelci.org/broonie-sound/for-next/v6.12-rc2-167-g902934bf5a62/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 21:24:45.778011 saving as /var/lib/lava/dispatcher/tmp/884215/tftp-deploy-l3s4s_rn/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 21:24:45.778219 total size: 53209 (0 MB)
82 21:24:45.778427 No compression specified
83 21:24:45.821391 progress 61 % (0 MB)
84 21:24:45.822225 progress 100 % (0 MB)
85 21:24:45.822759 0 MB downloaded in 0.04 s (1.14 MB/s)
86 21:24:45.823221 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:24:45.824063 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:24:45.824333 start: 1.4 download-retry (timeout 00:09:59) [common]
90 21:24:45.824593 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 21:24:45.825060 downloading http://storage.kernelci.org/broonie-sound/for-next/v6.12-rc2-167-g902934bf5a62/arm64/defconfig/gcc-12/modules.tar.xz
92 21:24:45.825302 saving as /var/lib/lava/dispatcher/tmp/884215/tftp-deploy-l3s4s_rn/modules/modules.tar
93 21:24:45.825505 total size: 11588116 (11 MB)
94 21:24:45.825714 Using unxz to decompress xz
95 21:24:45.865260 progress 0 % (0 MB)
96 21:24:45.931794 progress 5 % (0 MB)
97 21:24:46.006747 progress 10 % (1 MB)
98 21:24:46.086414 progress 15 % (1 MB)
99 21:24:46.161820 progress 20 % (2 MB)
100 21:24:46.237436 progress 25 % (2 MB)
101 21:24:46.316664 progress 30 % (3 MB)
102 21:24:46.389264 progress 35 % (3 MB)
103 21:24:46.468233 progress 40 % (4 MB)
104 21:24:46.552936 progress 45 % (5 MB)
105 21:24:46.630731 progress 50 % (5 MB)
106 21:24:46.714034 progress 55 % (6 MB)
107 21:24:46.794641 progress 60 % (6 MB)
108 21:24:46.874956 progress 65 % (7 MB)
109 21:24:46.956853 progress 70 % (7 MB)
110 21:24:47.038594 progress 75 % (8 MB)
111 21:24:47.117502 progress 80 % (8 MB)
112 21:24:47.197939 progress 85 % (9 MB)
113 21:24:47.270836 progress 90 % (9 MB)
114 21:24:47.364328 progress 95 % (10 MB)
115 21:24:47.461945 progress 100 % (11 MB)
116 21:24:47.474981 11 MB downloaded in 1.65 s (6.70 MB/s)
117 21:24:47.475629 end: 1.4.1 http-download (duration 00:00:02) [common]
119 21:24:47.477273 end: 1.4 download-retry (duration 00:00:02) [common]
120 21:24:47.477819 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 21:24:47.478357 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 21:24:47.478864 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:24:47.479378 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 21:24:47.480399 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_
125 21:24:47.481238 makedir: /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin
126 21:24:47.481890 makedir: /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/tests
127 21:24:47.482626 makedir: /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/results
128 21:24:47.483270 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-add-keys
129 21:24:47.484267 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-add-sources
130 21:24:47.485218 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-background-process-start
131 21:24:47.486177 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-background-process-stop
132 21:24:47.487188 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-common-functions
133 21:24:47.488288 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-echo-ipv4
134 21:24:47.489288 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-install-packages
135 21:24:47.490217 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-installed-packages
136 21:24:47.491115 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-os-build
137 21:24:47.492051 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-probe-channel
138 21:24:47.492979 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-probe-ip
139 21:24:47.493895 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-target-ip
140 21:24:47.494806 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-target-mac
141 21:24:47.495717 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-target-storage
142 21:24:47.496695 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-test-case
143 21:24:47.497627 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-test-event
144 21:24:47.498605 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-test-feedback
145 21:24:47.499657 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-test-raise
146 21:24:47.500684 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-test-reference
147 21:24:47.501725 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-test-runner
148 21:24:47.502660 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-test-set
149 21:24:47.503576 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-test-shell
150 21:24:47.504563 Updating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-install-packages (oe)
151 21:24:47.505560 Updating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/bin/lava-installed-packages (oe)
152 21:24:47.506402 Creating /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/environment
153 21:24:47.507124 LAVA metadata
154 21:24:47.507615 - LAVA_JOB_ID=884215
155 21:24:47.508105 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:24:47.508798 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 21:24:47.510743 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:24:47.511369 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 21:24:47.511796 skipped lava-vland-overlay
160 21:24:47.512338 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:24:47.512858 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 21:24:47.513291 skipped lava-multinode-overlay
163 21:24:47.513780 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:24:47.514283 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 21:24:47.514766 Loading test definitions
166 21:24:47.515322 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 21:24:47.515764 Using /lava-884215 at stage 0
168 21:24:47.517231 uuid=884215_1.5.2.4.1 testdef=None
169 21:24:47.517551 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:24:47.517836 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 21:24:47.519667 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:24:47.520528 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 21:24:47.523303 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:24:47.524206 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 21:24:47.526786 runner path: /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/0/tests/0_dmesg test_uuid 884215_1.5.2.4.1
178 21:24:47.527573 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:24:47.528442 Creating lava-test-runner.conf files
181 21:24:47.528669 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/884215/lava-overlay-rg594yf_/lava-884215/0 for stage 0
182 21:24:47.529054 - 0_dmesg
183 21:24:47.529463 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:24:47.529787 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 21:24:47.555400 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:24:47.555846 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 21:24:47.556142 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:24:47.556415 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:24:47.556768 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 21:24:48.607554 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 21:24:48.608106 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 21:24:48.608596 extracting modules file /var/lib/lava/dispatcher/tmp/884215/tftp-deploy-l3s4s_rn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/884215/extract-overlay-ramdisk-lbq0xq4s/ramdisk
193 21:24:50.001342 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 21:24:50.001830 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 21:24:50.002104 [common] Applying overlay /var/lib/lava/dispatcher/tmp/884215/compress-overlay-z1lduei4/overlay-1.5.2.5.tar.gz to ramdisk
196 21:24:50.002314 [common] Applying overlay /var/lib/lava/dispatcher/tmp/884215/compress-overlay-z1lduei4/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/884215/extract-overlay-ramdisk-lbq0xq4s/ramdisk
197 21:24:50.032798 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:24:50.033240 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 21:24:50.033508 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 21:24:50.033736 Converting downloaded kernel to a uImage
201 21:24:50.034044 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/884215/tftp-deploy-l3s4s_rn/kernel/Image /var/lib/lava/dispatcher/tmp/884215/tftp-deploy-l3s4s_rn/kernel/uImage
202 21:24:50.502033 output: Image Name:
203 21:24:50.502429 output: Created: Tue Oct 22 21:24:50 2024
204 21:24:50.502636 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:24:50.502839 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 21:24:50.503038 output: Load Address: 01080000
207 21:24:50.503235 output: Entry Point: 01080000
208 21:24:50.503430 output:
209 21:24:50.503760 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 21:24:50.504053 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 21:24:50.504331 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 21:24:50.504583 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:24:50.504836 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 21:24:50.505086 Building ramdisk /var/lib/lava/dispatcher/tmp/884215/extract-overlay-ramdisk-lbq0xq4s/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/884215/extract-overlay-ramdisk-lbq0xq4s/ramdisk
215 21:24:53.007372 >> 181565 blocks
216 21:25:01.482919 Adding RAMdisk u-boot header.
217 21:25:01.483574 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/884215/extract-overlay-ramdisk-lbq0xq4s/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/884215/extract-overlay-ramdisk-lbq0xq4s/ramdisk.cpio.gz.uboot
218 21:25:01.755518 output: Image Name:
219 21:25:01.755938 output: Created: Tue Oct 22 21:25:01 2024
220 21:25:01.756429 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:25:01.756885 output: Data Size: 26056805 Bytes = 25446.10 KiB = 24.85 MiB
222 21:25:01.757342 output: Load Address: 00000000
223 21:25:01.757775 output: Entry Point: 00000000
224 21:25:01.758207 output:
225 21:25:01.759457 rename /var/lib/lava/dispatcher/tmp/884215/extract-overlay-ramdisk-lbq0xq4s/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/884215/tftp-deploy-l3s4s_rn/ramdisk/ramdisk.cpio.gz.uboot
226 21:25:01.760275 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 21:25:01.760876 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 21:25:01.761447 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 21:25:01.761941 No LXC device requested
230 21:25:01.762489 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:25:01.763045 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 21:25:01.763584 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:25:01.764062 Checking files for TFTP limit of 4294967296 bytes.
234 21:25:01.766962 end: 1 tftp-deploy (duration 00:00:17) [common]
235 21:25:01.767577 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:25:01.768176 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:25:01.768728 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:25:01.769291 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:25:01.769866 Using kernel file from prepare-kernel: 884215/tftp-deploy-l3s4s_rn/kernel/uImage
240 21:25:01.770522 substitutions:
241 21:25:01.770966 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:25:01.771404 - {DTB_ADDR}: 0x01070000
243 21:25:01.771839 - {DTB}: 884215/tftp-deploy-l3s4s_rn/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 21:25:01.772305 - {INITRD}: 884215/tftp-deploy-l3s4s_rn/ramdisk/ramdisk.cpio.gz.uboot
245 21:25:01.772740 - {KERNEL_ADDR}: 0x01080000
246 21:25:01.773166 - {KERNEL}: 884215/tftp-deploy-l3s4s_rn/kernel/uImage
247 21:25:01.773592 - {LAVA_MAC}: None
248 21:25:01.774059 - {PRESEED_CONFIG}: None
249 21:25:01.774486 - {PRESEED_LOCAL}: None
250 21:25:01.774913 - {RAMDISK_ADDR}: 0x08000000
251 21:25:01.775337 - {RAMDISK}: 884215/tftp-deploy-l3s4s_rn/ramdisk/ramdisk.cpio.gz.uboot
252 21:25:01.775765 - {ROOT_PART}: None
253 21:25:01.776224 - {ROOT}: None
254 21:25:01.776652 - {SERVER_IP}: 192.168.6.2
255 21:25:01.777083 - {TEE_ADDR}: 0x83000000
256 21:25:01.777508 - {TEE}: None
257 21:25:01.777930 Parsed boot commands:
258 21:25:01.778343 - setenv autoload no
259 21:25:01.778769 - setenv initrd_high 0xffffffff
260 21:25:01.779189 - setenv fdt_high 0xffffffff
261 21:25:01.779611 - dhcp
262 21:25:01.780058 - setenv serverip 192.168.6.2
263 21:25:01.780485 - tftpboot 0x01080000 884215/tftp-deploy-l3s4s_rn/kernel/uImage
264 21:25:01.780909 - tftpboot 0x08000000 884215/tftp-deploy-l3s4s_rn/ramdisk/ramdisk.cpio.gz.uboot
265 21:25:01.781332 - tftpboot 0x01070000 884215/tftp-deploy-l3s4s_rn/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 21:25:01.781754 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:25:01.782183 - bootm 0x01080000 0x08000000 0x01070000
268 21:25:01.782721 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:25:01.784366 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:25:01.784845 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 21:25:01.800037 Setting prompt string to ['lava-test: # ']
273 21:25:01.801667 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:25:01.802329 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:25:01.802914 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:25:01.803644 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:25:01.804926 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 21:25:01.844694 >> OK - accepted request
279 21:25:01.846935 Returned 0 in 0 seconds
280 21:25:01.948381 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:25:01.950196 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:25:01.950824 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:25:01.951380 Setting prompt string to ['Hit any key to stop autoboot']
285 21:25:01.951865 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:25:01.953616 Trying 192.168.56.21...
287 21:25:01.954142 Connected to conserv1.
288 21:25:01.954595 Escape character is '^]'.
289 21:25:01.955051
290 21:25:01.955507 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 21:25:01.955971
292 21:25:09.050059 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 21:25:09.050482 bl2_stage_init 0x01
294 21:25:09.050793 bl2_stage_init 0x81
295 21:25:09.055716 hw id: 0x0000 - pwm id 0x01
296 21:25:09.056080 bl2_stage_init 0xc1
297 21:25:09.056308 bl2_stage_init 0x02
298 21:25:09.056522
299 21:25:09.061223 L0:00000000
300 21:25:09.061547 L1:00000703
301 21:25:09.061762 L2:00008067
302 21:25:09.061961 L3:15000000
303 21:25:09.062179 S1:00000000
304 21:25:09.067799 B2:20282000
305 21:25:09.068167 B1:a0f83180
306 21:25:09.068378
307 21:25:09.068580 TE: 70146
308 21:25:09.068780
309 21:25:09.073498 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 21:25:09.073853
311 21:25:09.074064 Board ID = 1
312 21:25:09.079098 Set cpu clk to 24M
313 21:25:09.079438 Set clk81 to 24M
314 21:25:09.079642 Use GP1_pll as DSU clk.
315 21:25:09.082419 DSU clk: 1200 Mhz
316 21:25:09.082734 CPU clk: 1200 MHz
317 21:25:09.088039 Set clk81 to 166.6M
318 21:25:09.093749 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 21:25:09.094099 board id: 1
320 21:25:09.100567 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 21:25:09.111883 fw parse done
322 21:25:09.116896 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 21:25:09.160209 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 21:25:09.171363 PIEI prepare done
325 21:25:09.171849 fastboot data load
326 21:25:09.172383 fastboot data verify
327 21:25:09.177086 verify result: 266
328 21:25:09.182624 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 21:25:09.182923 LPDDR4 probe
330 21:25:09.183152 ddr clk to 1584MHz
331 21:25:09.189691 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 21:25:09.227833
333 21:25:09.228263 dmc_version 0001
334 21:25:09.234036 Check phy result
335 21:25:09.240456 INFO : End of CA training
336 21:25:09.240783 INFO : End of initialization
337 21:25:09.246495 INFO : Training has run successfully!
338 21:25:09.246816 Check phy result
339 21:25:09.251744 INFO : End of initialization
340 21:25:09.252075 INFO : End of read enable training
341 21:25:09.255087 INFO : End of fine write leveling
342 21:25:09.260513 INFO : End of Write leveling coarse delay
343 21:25:09.266047 INFO : Training has run successfully!
344 21:25:09.266348 Check phy result
345 21:25:09.266561 INFO : End of initialization
346 21:25:09.271735 INFO : End of read dq deskew training
347 21:25:09.275103 INFO : End of MPR read delay center optimization
348 21:25:09.280746 INFO : End of write delay center optimization
349 21:25:09.286231 INFO : End of read delay center optimization
350 21:25:09.286566 INFO : End of max read latency training
351 21:25:09.291836 INFO : Training has run successfully!
352 21:25:09.292175 1D training succeed
353 21:25:09.299671 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 21:25:09.346608 Check phy result
355 21:25:09.347012 INFO : End of initialization
356 21:25:09.368861 INFO : End of 2D read delay Voltage center optimization
357 21:25:09.388143 INFO : End of 2D read delay Voltage center optimization
358 21:25:09.440666 INFO : End of 2D write delay Voltage center optimization
359 21:25:09.490151 INFO : End of 2D write delay Voltage center optimization
360 21:25:09.495732 INFO : Training has run successfully!
361 21:25:09.496070
362 21:25:09.496302 channel==0
363 21:25:09.501305 RxClkDly_Margin_A0==78 ps 8
364 21:25:09.501597 TxDqDly_Margin_A0==98 ps 10
365 21:25:09.506844 RxClkDly_Margin_A1==88 ps 9
366 21:25:09.507113 TxDqDly_Margin_A1==88 ps 9
367 21:25:09.507328 TrainedVREFDQ_A0==74
368 21:25:09.512484 TrainedVREFDQ_A1==74
369 21:25:09.512765 VrefDac_Margin_A0==23
370 21:25:09.512974 DeviceVref_Margin_A0==40
371 21:25:09.518017 VrefDac_Margin_A1==22
372 21:25:09.518328 DeviceVref_Margin_A1==40
373 21:25:09.518542
374 21:25:09.518746
375 21:25:09.518947 channel==1
376 21:25:09.523710 RxClkDly_Margin_A0==88 ps 9
377 21:25:09.524019 TxDqDly_Margin_A0==98 ps 10
378 21:25:09.529340 RxClkDly_Margin_A1==88 ps 9
379 21:25:09.529622 TxDqDly_Margin_A1==78 ps 8
380 21:25:09.534826 TrainedVREFDQ_A0==78
381 21:25:09.535112 TrainedVREFDQ_A1==75
382 21:25:09.535321 VrefDac_Margin_A0==22
383 21:25:09.540583 DeviceVref_Margin_A0==36
384 21:25:09.540894 VrefDac_Margin_A1==22
385 21:25:09.546140 DeviceVref_Margin_A1==39
386 21:25:09.546436
387 21:25:09.546660 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 21:25:09.546868
389 21:25:09.579902 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
390 21:25:09.580337 2D training succeed
391 21:25:09.585292 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 21:25:09.591011 auto size-- 65535DDR cs0 size: 2048MB
393 21:25:09.591300 DDR cs1 size: 2048MB
394 21:25:09.596596 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 21:25:09.596893 cs0 DataBus test pass
396 21:25:09.602048 cs1 DataBus test pass
397 21:25:09.602321 cs0 AddrBus test pass
398 21:25:09.602527 cs1 AddrBus test pass
399 21:25:09.602738
400 21:25:09.607867 100bdlr_step_size ps== 478
401 21:25:09.608184 result report
402 21:25:09.613262 boot times 0Enable ddr reg access
403 21:25:09.618075 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 21:25:09.631538 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 21:25:10.286632 bl2z: ptr: 05129330, size: 00001e40
406 21:25:10.294973 0.0;M3 CHK:0;cm4_sp_mode 0
407 21:25:10.295274 MVN_1=0x00000000
408 21:25:10.295490 MVN_2=0x00000000
409 21:25:10.306467 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 21:25:10.306752 OPS=0x04
411 21:25:10.306968 ring efuse init
412 21:25:10.312083 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 21:25:10.312359 [0.017319 Inits done]
414 21:25:10.312574 secure task start!
415 21:25:10.319051 high task start!
416 21:25:10.319333 low task start!
417 21:25:10.319546 run into bl31
418 21:25:10.328019 NOTICE: BL31: v1.3(release):4fc40b1
419 21:25:10.335448 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 21:25:10.335724 NOTICE: BL31: G12A normal boot!
421 21:25:10.351455 NOTICE: BL31: BL33 decompress pass
422 21:25:10.356568 ERROR: Error initializing runtime service opteed_fast
423 21:25:13.097325 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 21:25:13.097772 bl2_stage_init 0x01
425 21:25:13.097998 bl2_stage_init 0x81
426 21:25:13.102792 hw id: 0x0000 - pwm id 0x01
427 21:25:13.103112 bl2_stage_init 0xc1
428 21:25:13.108368 bl2_stage_init 0x02
429 21:25:13.108663
430 21:25:13.108874 L0:00000000
431 21:25:13.109074 L1:00000703
432 21:25:13.109272 L2:00008067
433 21:25:13.109473 L3:15000000
434 21:25:13.113959 S1:00000000
435 21:25:13.114239 B2:20282000
436 21:25:13.114438 B1:a0f83180
437 21:25:13.114631
438 21:25:13.114825 TE: 69460
439 21:25:13.115020
440 21:25:13.119544 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 21:25:13.119812
442 21:25:13.125228 Board ID = 1
443 21:25:13.125506 Set cpu clk to 24M
444 21:25:13.125702 Set clk81 to 24M
445 21:25:13.130764 Use GP1_pll as DSU clk.
446 21:25:13.131060 DSU clk: 1200 Mhz
447 21:25:13.131263 CPU clk: 1200 MHz
448 21:25:13.136359 Set clk81 to 166.6M
449 21:25:13.141960 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 21:25:13.142245 board id: 1
451 21:25:13.149187 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 21:25:13.159881 fw parse done
453 21:25:13.165800 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 21:25:13.208420 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 21:25:13.219367 PIEI prepare done
456 21:25:13.219693 fastboot data load
457 21:25:13.219898 fastboot data verify
458 21:25:13.225023 verify result: 266
459 21:25:13.230546 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 21:25:13.230853 LPDDR4 probe
461 21:25:13.231058 ddr clk to 1584MHz
462 21:25:13.238555 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 21:25:13.275958
464 21:25:13.276813 dmc_version 0001
465 21:25:13.282492 Check phy result
466 21:25:13.288469 INFO : End of CA training
467 21:25:13.289057 INFO : End of initialization
468 21:25:13.293992 INFO : Training has run successfully!
469 21:25:13.294549 Check phy result
470 21:25:13.299565 INFO : End of initialization
471 21:25:13.300161 INFO : End of read enable training
472 21:25:13.305245 INFO : End of fine write leveling
473 21:25:13.310693 INFO : End of Write leveling coarse delay
474 21:25:13.311041 INFO : Training has run successfully!
475 21:25:13.311309 Check phy result
476 21:25:13.316338 INFO : End of initialization
477 21:25:13.316673 INFO : End of read dq deskew training
478 21:25:13.321944 INFO : End of MPR read delay center optimization
479 21:25:13.327489 INFO : End of write delay center optimization
480 21:25:13.333200 INFO : End of read delay center optimization
481 21:25:13.333544 INFO : End of max read latency training
482 21:25:13.338676 INFO : Training has run successfully!
483 21:25:13.339023 1D training succeed
484 21:25:13.347890 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 21:25:13.395556 Check phy result
486 21:25:13.395970 INFO : End of initialization
487 21:25:13.417940 INFO : End of 2D read delay Voltage center optimization
488 21:25:13.437042 INFO : End of 2D read delay Voltage center optimization
489 21:25:13.488926 INFO : End of 2D write delay Voltage center optimization
490 21:25:13.538137 INFO : End of 2D write delay Voltage center optimization
491 21:25:13.543661 INFO : Training has run successfully!
492 21:25:13.544054
493 21:25:13.544292 channel==0
494 21:25:13.549304 RxClkDly_Margin_A0==88 ps 9
495 21:25:13.549655 TxDqDly_Margin_A0==98 ps 10
496 21:25:13.554878 RxClkDly_Margin_A1==88 ps 9
497 21:25:13.555563 TxDqDly_Margin_A1==88 ps 9
498 21:25:13.555848 TrainedVREFDQ_A0==74
499 21:25:13.560410 TrainedVREFDQ_A1==74
500 21:25:13.560786 VrefDac_Margin_A0==24
501 21:25:13.561060 DeviceVref_Margin_A0==40
502 21:25:13.566000 VrefDac_Margin_A1==23
503 21:25:13.566510 DeviceVref_Margin_A1==40
504 21:25:13.566973
505 21:25:13.567341
506 21:25:13.567588 channel==1
507 21:25:13.571545 RxClkDly_Margin_A0==88 ps 9
508 21:25:13.571890 TxDqDly_Margin_A0==98 ps 10
509 21:25:13.577259 RxClkDly_Margin_A1==78 ps 8
510 21:25:13.577756 TxDqDly_Margin_A1==88 ps 9
511 21:25:13.582807 TrainedVREFDQ_A0==78
512 21:25:13.583194 TrainedVREFDQ_A1==78
513 21:25:13.583431 VrefDac_Margin_A0==23
514 21:25:13.588453 DeviceVref_Margin_A0==36
515 21:25:13.588811 VrefDac_Margin_A1==22
516 21:25:13.594129 DeviceVref_Margin_A1==36
517 21:25:13.594513
518 21:25:13.594759 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 21:25:13.594995
520 21:25:13.627640 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 21:25:13.628081 2D training succeed
522 21:25:13.633343 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 21:25:13.638869 auto size-- 65535DDR cs0 size: 2048MB
524 21:25:13.639239 DDR cs1 size: 2048MB
525 21:25:13.644461 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 21:25:13.644827 cs0 DataBus test pass
527 21:25:13.650071 cs1 DataBus test pass
528 21:25:13.650435 cs0 AddrBus test pass
529 21:25:13.650653 cs1 AddrBus test pass
530 21:25:13.650853
531 21:25:13.655662 100bdlr_step_size ps== 478
532 21:25:13.656057 result report
533 21:25:13.661327 boot times 0Enable ddr reg access
534 21:25:13.666450 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 21:25:13.680248 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 21:25:14.334901 bl2z: ptr: 05129330, size: 00001e40
537 21:25:14.340936 0.0;M3 CHK:0;cm4_sp_mode 0
538 21:25:14.341414 MVN_1=0x00000000
539 21:25:14.341667 MVN_2=0x00000000
540 21:25:14.352476 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 21:25:14.352837 OPS=0x04
542 21:25:14.353056 ring efuse init
543 21:25:14.355387 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 21:25:14.361775 [0.017319 Inits done]
545 21:25:14.362119 secure task start!
546 21:25:14.362343 high task start!
547 21:25:14.362556 low task start!
548 21:25:14.366094 run into bl31
549 21:25:14.374646 NOTICE: BL31: v1.3(release):4fc40b1
550 21:25:14.382485 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 21:25:14.382853 NOTICE: BL31: G12A normal boot!
552 21:25:14.397936 NOTICE: BL31: BL33 decompress pass
553 21:25:14.403757 ERROR: Error initializing runtime service opteed_fast
554 21:25:15.797659 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 21:25:15.798102 bl2_stage_init 0x01
556 21:25:15.798325 bl2_stage_init 0x81
557 21:25:15.803233 hw id: 0x0000 - pwm id 0x01
558 21:25:15.803588 bl2_stage_init 0xc1
559 21:25:15.808909 bl2_stage_init 0x02
560 21:25:15.809241
561 21:25:15.809587 L0:00000000
562 21:25:15.809798 L1:00000703
563 21:25:15.809996 L2:00008067
564 21:25:15.810195 L3:15000000
565 21:25:15.810670 S1:00000000
566 21:25:15.815196 B2:20282000
567 21:25:15.815511 B1:a0f83180
568 21:25:15.815714
569 21:25:15.815912 TE: 69530
570 21:25:15.816146
571 21:25:15.821017 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 21:25:15.821392
573 21:25:15.826451 Board ID = 1
574 21:25:15.826903 Set cpu clk to 24M
575 21:25:15.827248 Set clk81 to 24M
576 21:25:15.832027 Use GP1_pll as DSU clk.
577 21:25:15.832370 DSU clk: 1200 Mhz
578 21:25:15.832577 CPU clk: 1200 MHz
579 21:25:15.832777 Set clk81 to 166.6M
580 21:25:15.843065 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 21:25:15.843594 board id: 1
582 21:25:15.849532 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 21:25:15.860436 fw parse done
584 21:25:15.866343 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 21:25:15.909538 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 21:25:15.920796 PIEI prepare done
587 21:25:15.921366 fastboot data load
588 21:25:15.921631 fastboot data verify
589 21:25:15.926225 verify result: 266
590 21:25:15.932124 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 21:25:15.932549 LPDDR4 probe
592 21:25:15.932770 ddr clk to 1584MHz
593 21:25:15.940268 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 21:25:15.977711
595 21:25:15.978256 dmc_version 0001
596 21:25:15.984558 Check phy result
597 21:25:15.990526 INFO : End of CA training
598 21:25:15.990828 INFO : End of initialization
599 21:25:15.996211 INFO : Training has run successfully!
600 21:25:15.996539 Check phy result
601 21:25:16.001747 INFO : End of initialization
602 21:25:16.002083 INFO : End of read enable training
603 21:25:16.004943 INFO : End of fine write leveling
604 21:25:16.010532 INFO : End of Write leveling coarse delay
605 21:25:16.016161 INFO : Training has run successfully!
606 21:25:16.016479 Check phy result
607 21:25:16.016691 INFO : End of initialization
608 21:25:16.021834 INFO : End of read dq deskew training
609 21:25:16.027383 INFO : End of MPR read delay center optimization
610 21:25:16.027687 INFO : End of write delay center optimization
611 21:25:16.032917 INFO : End of read delay center optimization
612 21:25:16.038608 INFO : End of max read latency training
613 21:25:16.038937 INFO : Training has run successfully!
614 21:25:16.044174 1D training succeed
615 21:25:16.050119 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 21:25:16.098457 Check phy result
617 21:25:16.098851 INFO : End of initialization
618 21:25:16.125896 INFO : End of 2D read delay Voltage center optimization
619 21:25:16.150102 INFO : End of 2D read delay Voltage center optimization
620 21:25:16.206738 INFO : End of 2D write delay Voltage center optimization
621 21:25:16.260929 INFO : End of 2D write delay Voltage center optimization
622 21:25:16.266332 INFO : Training has run successfully!
623 21:25:16.266637
624 21:25:16.266850 channel==0
625 21:25:16.271906 RxClkDly_Margin_A0==78 ps 8
626 21:25:16.272221 TxDqDly_Margin_A0==88 ps 9
627 21:25:16.275202 RxClkDly_Margin_A1==69 ps 7
628 21:25:16.275491 TxDqDly_Margin_A1==98 ps 10
629 21:25:16.280849 TrainedVREFDQ_A0==74
630 21:25:16.281284 TrainedVREFDQ_A1==75
631 21:25:16.281621 VrefDac_Margin_A0==23
632 21:25:16.286382 DeviceVref_Margin_A0==40
633 21:25:16.286678 VrefDac_Margin_A1==22
634 21:25:16.291954 DeviceVref_Margin_A1==39
635 21:25:16.292262
636 21:25:16.292470
637 21:25:16.292679 channel==1
638 21:25:16.292883 RxClkDly_Margin_A0==88 ps 9
639 21:25:16.295446 TxDqDly_Margin_A0==88 ps 9
640 21:25:16.300954 RxClkDly_Margin_A1==78 ps 8
641 21:25:16.301257 TxDqDly_Margin_A1==98 ps 10
642 21:25:16.301469 TrainedVREFDQ_A0==75
643 21:25:16.306581 TrainedVREFDQ_A1==78
644 21:25:16.306880 VrefDac_Margin_A0==22
645 21:25:16.312194 DeviceVref_Margin_A0==39
646 21:25:16.312480 VrefDac_Margin_A1==22
647 21:25:16.312688 DeviceVref_Margin_A1==36
648 21:25:16.312897
649 21:25:16.317807 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 21:25:16.318255
651 21:25:16.351438 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000016 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
652 21:25:16.351849 2D training succeed
653 21:25:16.357019 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 21:25:16.362474 auto size-- 65535DDR cs0 size: 2048MB
655 21:25:16.362762 DDR cs1 size: 2048MB
656 21:25:16.368095 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 21:25:16.368392 cs0 DataBus test pass
658 21:25:16.368599 cs1 DataBus test pass
659 21:25:16.373783 cs0 AddrBus test pass
660 21:25:16.374095 cs1 AddrBus test pass
661 21:25:16.374311
662 21:25:16.379310 100bdlr_step_size ps== 471
663 21:25:16.379627 result report
664 21:25:16.379828 boot times 0Enable ddr reg access
665 21:25:16.388961 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 21:25:16.402874 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 21:25:17.062241 bl2z: ptr: 05129330, size: 00001e40
668 21:25:17.070920 0.0;M3 CHK:0;cm4_sp_mode 0
669 21:25:17.071404 MVN_1=0x00000000
670 21:25:17.071643 MVN_2=0x00000000
671 21:25:17.082315 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 21:25:17.082756 OPS=0x04
673 21:25:17.083000 ring efuse init
674 21:25:17.085284 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 21:25:17.091098 [0.017354 Inits done]
676 21:25:17.091377 secure task start!
677 21:25:17.091580 high task start!
678 21:25:17.091779 low task start!
679 21:25:17.095407 run into bl31
680 21:25:17.104050 NOTICE: BL31: v1.3(release):4fc40b1
681 21:25:17.111890 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 21:25:17.112214 NOTICE: BL31: G12A normal boot!
683 21:25:17.127546 NOTICE: BL31: BL33 decompress pass
684 21:25:17.133141 ERROR: Error initializing runtime service opteed_fast
685 21:25:17.928626
686 21:25:17.929285
687 21:25:17.934020 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 21:25:17.934531
689 21:25:17.937543 Model: Libre Computer AML-S905D3-CC Solitude
690 21:25:18.084151 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 21:25:18.099365 DRAM: 2 GiB (effective 3.8 GiB)
692 21:25:18.200982 Core: 406 devices, 33 uclasses, devicetree: separate
693 21:25:18.205818 WDT: Not starting watchdog@f0d0
694 21:25:18.232013 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 21:25:18.244082 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 21:25:18.249036 ** Bad device specification mmc 0 **
697 21:25:18.259235 Card did not respond to voltage select! : -110
698 21:25:18.265973 ** Bad device specification mmc 0 **
699 21:25:18.266468 Couldn't find partition mmc 0
700 21:25:18.275214 Card did not respond to voltage select! : -110
701 21:25:18.280814 ** Bad device specification mmc 0 **
702 21:25:18.281286 Couldn't find partition mmc 0
703 21:25:18.284842 Error: could not access storage.
704 21:25:18.581675 Net: eth0: ethernet@ff3f0000
705 21:25:18.582254 starting USB...
706 21:25:18.826960 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 21:25:18.827518 Starting the controller
708 21:25:18.832951 USB XHCI 1.10
709 21:25:20.388164 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 21:25:20.395595 scanning usb for storage devices... 0 Storage Device(s) found
712 21:25:20.447109 Hit any key to stop autoboot: 1
713 21:25:20.447946 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
714 21:25:20.448803 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 21:25:20.449311 Setting prompt string to ['=>']
716 21:25:20.449805 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 21:25:20.461420 0
718 21:25:20.462348 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 21:25:20.563564 => setenv autoload no
721 21:25:20.564271 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 21:25:20.569131 setenv autoload no
724 21:25:20.670646 => setenv initrd_high 0xffffffff
725 21:25:20.671278 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 21:25:20.675110 setenv initrd_high 0xffffffff
728 21:25:20.776590 => setenv fdt_high 0xffffffff
729 21:25:20.777230 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 21:25:20.780568 setenv fdt_high 0xffffffff
732 21:25:20.882154 => dhcp
733 21:25:20.882803 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 21:25:20.886891 dhcp
735 21:25:22.142452 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete... done
736 21:25:22.143084 Speed: 1000, full duplex
737 21:25:22.143515 BOOTP broadcast 1
738 21:25:22.155413 DHCP client bound to address 192.168.6.21 (12 ms)
740 21:25:22.256887 => setenv serverip 192.168.6.2
741 21:25:22.257663 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
742 21:25:22.261365 setenv serverip 192.168.6.2
744 21:25:22.362805 => tftpboot 0x01080000 884215/tftp-deploy-l3s4s_rn/kernel/uImage
745 21:25:22.363517 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
746 21:25:22.370286 tftpboot 0x01080000 884215/tftp-deploy-l3s4s_rn/kernel/uImage
747 21:25:22.370775 Speed: 1000, full duplex
748 21:25:22.371190 Using ethernet@ff3f0000 device
749 21:25:22.375687 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 21:25:22.381283 Filename '884215/tftp-deploy-l3s4s_rn/kernel/uImage'.
751 21:25:22.384655 Load address: 0x1080000
752 21:25:25.281945 Loading: *################################################## 43.6 MiB
753 21:25:25.282353 15 MiB/s
754 21:25:25.282638 done
755 21:25:25.285578 Bytes transferred = 45713984 (2b98a40 hex)
757 21:25:25.387189 => tftpboot 0x08000000 884215/tftp-deploy-l3s4s_rn/ramdisk/ramdisk.cpio.gz.uboot
758 21:25:25.387694 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
759 21:25:25.394690 tftpboot 0x08000000 884215/tftp-deploy-l3s4s_rn/ramdisk/ramdisk.cpio.gz.uboot
760 21:25:25.395432 Speed: 1000, full duplex
761 21:25:25.396067 Using ethernet@ff3f0000 device
762 21:25:25.400223 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
763 21:25:25.409815 Filename '884215/tftp-deploy-l3s4s_rn/ramdisk/ramdisk.cpio.gz.uboot'.
764 21:25:25.410411 Load address: 0x8000000
765 21:25:27.244310 Loading: *################################################# UDP wrong checksum 00000005 0000ebe8
766 21:25:32.245331 T UDP wrong checksum 00000005 0000ebe8
767 21:25:42.247513 T T UDP wrong checksum 00000005 0000ebe8
768 21:26:02.251374 T T T T UDP wrong checksum 00000005 0000ebe8
769 21:26:22.255974 T T T
770 21:26:22.256676 Retry count exceeded; starting again
772 21:26:22.258191 end: 2.4.3 bootloader-commands (duration 00:01:02) [common]
775 21:26:22.260290 end: 2.4 uboot-commands (duration 00:01:20) [common]
777 21:26:22.261805 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
779 21:26:22.262865 end: 2 uboot-action (duration 00:01:20) [common]
781 21:26:22.264545 Cleaning after the job
782 21:26:22.265112 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/884215/tftp-deploy-l3s4s_rn/ramdisk
783 21:26:22.266429 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/884215/tftp-deploy-l3s4s_rn/kernel
784 21:26:22.314766 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/884215/tftp-deploy-l3s4s_rn/dtb
785 21:26:22.315524 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/884215/tftp-deploy-l3s4s_rn/modules
786 21:26:22.335626 start: 4.1 power-off (timeout 00:00:30) [common]
787 21:26:22.336273 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
788 21:26:22.366307 >> OK - accepted request
789 21:26:22.368034 Returned 0 in 0 seconds
790 21:26:22.468774 end: 4.1 power-off (duration 00:00:00) [common]
792 21:26:22.469699 start: 4.2 read-feedback (timeout 00:10:00) [common]
793 21:26:22.470344 Listened to connection for namespace 'common' for up to 1s
794 21:26:23.471353 Finalising connection for namespace 'common'
795 21:26:23.472217 Disconnecting from shell: Finalise
796 21:26:23.472800 =>
797 21:26:23.573828 end: 4.2 read-feedback (duration 00:00:01) [common]
798 21:26:23.574531 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/884215
799 21:26:23.888815 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/884215
800 21:26:23.889405 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.