Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:43:54.505478 lava-dispatcher, installed at version: 2024.01
2 21:43:54.506254 start: 0 validate
3 21:43:54.506742 Start time: 2024-10-31 21:43:54.506712+00:00 (UTC)
4 21:43:54.507291 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:43:54.507813 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 21:43:54.542402 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:43:54.543010 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-54-gb69ef01da0f2%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 21:43:54.577511 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:43:54.578181 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-54-gb69ef01da0f2%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 21:44:01.658145 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:44:01.658647 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-54-gb69ef01da0f2%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 21:44:02.702419 validate duration: 8.20
14 21:44:02.703295 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:44:02.703638 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:44:02.703957 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:44:02.704601 Not decompressing ramdisk as can be used compressed.
18 21:44:02.705032 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 21:44:02.705312 saving as /var/lib/lava/dispatcher/tmp/918826/tftp-deploy-42o3hy5k/ramdisk/rootfs.cpio.gz
20 21:44:02.705594 total size: 8181887 (7 MB)
21 21:44:02.747390 progress 0 % (0 MB)
22 21:44:02.757289 progress 5 % (0 MB)
23 21:44:02.762831 progress 10 % (0 MB)
24 21:44:02.768606 progress 15 % (1 MB)
25 21:44:02.774188 progress 20 % (1 MB)
26 21:44:02.779860 progress 25 % (1 MB)
27 21:44:02.785267 progress 30 % (2 MB)
28 21:44:02.790984 progress 35 % (2 MB)
29 21:44:02.796247 progress 40 % (3 MB)
30 21:44:02.802057 progress 45 % (3 MB)
31 21:44:02.807324 progress 50 % (3 MB)
32 21:44:02.812985 progress 55 % (4 MB)
33 21:44:02.818523 progress 60 % (4 MB)
34 21:44:02.824241 progress 65 % (5 MB)
35 21:44:02.829632 progress 70 % (5 MB)
36 21:44:02.835398 progress 75 % (5 MB)
37 21:44:02.840585 progress 80 % (6 MB)
38 21:44:02.846203 progress 85 % (6 MB)
39 21:44:02.851182 progress 90 % (7 MB)
40 21:44:02.856613 progress 95 % (7 MB)
41 21:44:02.861601 progress 100 % (7 MB)
42 21:44:02.862259 7 MB downloaded in 0.16 s (49.81 MB/s)
43 21:44:02.862843 end: 1.1.1 http-download (duration 00:00:00) [common]
45 21:44:02.863839 end: 1.1 download-retry (duration 00:00:00) [common]
46 21:44:02.864208 start: 1.2 download-retry (timeout 00:10:00) [common]
47 21:44:02.864535 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 21:44:02.865065 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-54-gb69ef01da0f2/arm64/defconfig/gcc-12/kernel/Image
49 21:44:02.865345 saving as /var/lib/lava/dispatcher/tmp/918826/tftp-deploy-42o3hy5k/kernel/Image
50 21:44:02.865582 total size: 45713920 (43 MB)
51 21:44:02.865814 No compression specified
52 21:44:02.903197 progress 0 % (0 MB)
53 21:44:02.946355 progress 5 % (2 MB)
54 21:44:02.982134 progress 10 % (4 MB)
55 21:44:03.015846 progress 15 % (6 MB)
56 21:44:03.045410 progress 20 % (8 MB)
57 21:44:03.072202 progress 25 % (10 MB)
58 21:44:03.099226 progress 30 % (13 MB)
59 21:44:03.127574 progress 35 % (15 MB)
60 21:44:03.155293 progress 40 % (17 MB)
61 21:44:03.181843 progress 45 % (19 MB)
62 21:44:03.209011 progress 50 % (21 MB)
63 21:44:03.236662 progress 55 % (24 MB)
64 21:44:03.263695 progress 60 % (26 MB)
65 21:44:03.290329 progress 65 % (28 MB)
66 21:44:03.318488 progress 70 % (30 MB)
67 21:44:03.346954 progress 75 % (32 MB)
68 21:44:03.374551 progress 80 % (34 MB)
69 21:44:03.401137 progress 85 % (37 MB)
70 21:44:03.429045 progress 90 % (39 MB)
71 21:44:03.457577 progress 95 % (41 MB)
72 21:44:03.484319 progress 100 % (43 MB)
73 21:44:03.484902 43 MB downloaded in 0.62 s (70.40 MB/s)
74 21:44:03.485391 end: 1.2.1 http-download (duration 00:00:01) [common]
76 21:44:03.486213 end: 1.2 download-retry (duration 00:00:01) [common]
77 21:44:03.486486 start: 1.3 download-retry (timeout 00:09:59) [common]
78 21:44:03.486746 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 21:44:03.487228 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-54-gb69ef01da0f2/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 21:44:03.487483 saving as /var/lib/lava/dispatcher/tmp/918826/tftp-deploy-42o3hy5k/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 21:44:03.487689 total size: 53209 (0 MB)
82 21:44:03.487907 No compression specified
83 21:44:03.573510 progress 61 % (0 MB)
84 21:44:03.574387 progress 100 % (0 MB)
85 21:44:03.574970 0 MB downloaded in 0.09 s (0.58 MB/s)
86 21:44:03.575476 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:44:03.576365 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:44:03.576645 start: 1.4 download-retry (timeout 00:09:59) [common]
90 21:44:03.576920 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 21:44:03.577411 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-54-gb69ef01da0f2/arm64/defconfig/gcc-12/modules.tar.xz
92 21:44:03.577665 saving as /var/lib/lava/dispatcher/tmp/918826/tftp-deploy-42o3hy5k/modules/modules.tar
93 21:44:03.577871 total size: 11610020 (11 MB)
94 21:44:03.578084 Using unxz to decompress xz
95 21:44:03.619098 progress 0 % (0 MB)
96 21:44:03.696229 progress 5 % (0 MB)
97 21:44:03.770629 progress 10 % (1 MB)
98 21:44:03.853410 progress 15 % (1 MB)
99 21:44:03.930427 progress 20 % (2 MB)
100 21:44:04.008589 progress 25 % (2 MB)
101 21:44:04.090802 progress 30 % (3 MB)
102 21:44:04.168942 progress 35 % (3 MB)
103 21:44:04.245452 progress 40 % (4 MB)
104 21:44:04.331501 progress 45 % (5 MB)
105 21:44:04.413598 progress 50 % (5 MB)
106 21:44:04.492820 progress 55 % (6 MB)
107 21:44:04.576165 progress 60 % (6 MB)
108 21:44:04.661631 progress 65 % (7 MB)
109 21:44:04.745254 progress 70 % (7 MB)
110 21:44:04.820894 progress 75 % (8 MB)
111 21:44:04.904286 progress 80 % (8 MB)
112 21:44:04.985609 progress 85 % (9 MB)
113 21:44:05.055636 progress 90 % (9 MB)
114 21:44:05.155167 progress 95 % (10 MB)
115 21:44:05.253902 progress 100 % (11 MB)
116 21:44:05.265777 11 MB downloaded in 1.69 s (6.56 MB/s)
117 21:44:05.266589 end: 1.4.1 http-download (duration 00:00:02) [common]
119 21:44:05.267737 end: 1.4 download-retry (duration 00:00:02) [common]
120 21:44:05.268386 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 21:44:05.269493 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 21:44:05.270462 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:44:05.271482 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 21:44:05.273552 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p
125 21:44:05.275179 makedir: /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin
126 21:44:05.276529 makedir: /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/tests
127 21:44:05.277838 makedir: /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/results
128 21:44:05.278968 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-add-keys
129 21:44:05.280912 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-add-sources
130 21:44:05.282803 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-background-process-start
131 21:44:05.284764 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-background-process-stop
132 21:44:05.286731 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-common-functions
133 21:44:05.288708 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-echo-ipv4
134 21:44:05.290539 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-install-packages
135 21:44:05.293328 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-installed-packages
136 21:44:05.295409 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-os-build
137 21:44:05.297367 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-probe-channel
138 21:44:05.299155 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-probe-ip
139 21:44:05.300978 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-target-ip
140 21:44:05.302577 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-target-mac
141 21:44:05.304285 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-target-storage
142 21:44:05.306017 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-test-case
143 21:44:05.307633 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-test-event
144 21:44:05.308676 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-test-feedback
145 21:44:05.309419 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-test-raise
146 21:44:05.310120 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-test-reference
147 21:44:05.310863 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-test-runner
148 21:44:05.311580 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-test-set
149 21:44:05.312380 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-test-shell
150 21:44:05.313103 Updating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-install-packages (oe)
151 21:44:05.313892 Updating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/bin/lava-installed-packages (oe)
152 21:44:05.314541 Creating /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/environment
153 21:44:05.315107 LAVA metadata
154 21:44:05.315508 - LAVA_JOB_ID=918826
155 21:44:05.315825 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:44:05.316363 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 21:44:05.317807 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:44:05.318248 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 21:44:05.318549 skipped lava-vland-overlay
160 21:44:05.318927 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:44:05.319283 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 21:44:05.319573 skipped lava-multinode-overlay
163 21:44:05.319923 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:44:05.320302 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 21:44:05.320692 Loading test definitions
166 21:44:05.321116 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 21:44:05.321411 Using /lava-918826 at stage 0
168 21:44:05.323191 uuid=918826_1.5.2.4.1 testdef=None
169 21:44:05.323626 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:44:05.324031 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 21:44:05.326673 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:44:05.327792 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 21:44:05.331080 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:44:05.332241 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 21:44:05.335428 runner path: /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/0/tests/0_dmesg test_uuid 918826_1.5.2.4.1
178 21:44:05.336294 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:44:05.337360 Creating lava-test-runner.conf files
181 21:44:05.337631 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/918826/lava-overlay-e2yn8f4p/lava-918826/0 for stage 0
182 21:44:05.338143 - 0_dmesg
183 21:44:05.338654 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:44:05.339032 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 21:44:05.372876 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:44:05.373456 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 21:44:05.373846 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:44:05.374279 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:44:05.374635 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 21:44:06.340003 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 21:44:06.340494 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 21:44:06.340741 extracting modules file /var/lib/lava/dispatcher/tmp/918826/tftp-deploy-42o3hy5k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/918826/extract-overlay-ramdisk-j9cfoz7q/ramdisk
193 21:44:07.677759 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 21:44:07.678252 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 21:44:07.678529 [common] Applying overlay /var/lib/lava/dispatcher/tmp/918826/compress-overlay-56d_zmhz/overlay-1.5.2.5.tar.gz to ramdisk
196 21:44:07.678744 [common] Applying overlay /var/lib/lava/dispatcher/tmp/918826/compress-overlay-56d_zmhz/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/918826/extract-overlay-ramdisk-j9cfoz7q/ramdisk
197 21:44:07.709394 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:44:07.709832 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 21:44:07.710118 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 21:44:07.710347 Converting downloaded kernel to a uImage
201 21:44:07.710653 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/918826/tftp-deploy-42o3hy5k/kernel/Image /var/lib/lava/dispatcher/tmp/918826/tftp-deploy-42o3hy5k/kernel/uImage
202 21:44:08.237868 output: Image Name:
203 21:44:08.238295 output: Created: Thu Oct 31 21:44:07 2024
204 21:44:08.238502 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:44:08.238704 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 21:44:08.238905 output: Load Address: 01080000
207 21:44:08.239101 output: Entry Point: 01080000
208 21:44:08.239296 output:
209 21:44:08.239630 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 21:44:08.239898 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 21:44:08.240215 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 21:44:08.240475 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:44:08.240731 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 21:44:08.240983 Building ramdisk /var/lib/lava/dispatcher/tmp/918826/extract-overlay-ramdisk-j9cfoz7q/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/918826/extract-overlay-ramdisk-j9cfoz7q/ramdisk
215 21:44:10.908488 >> 181557 blocks
216 21:44:19.375699 Adding RAMdisk u-boot header.
217 21:44:19.376290 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/918826/extract-overlay-ramdisk-j9cfoz7q/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/918826/extract-overlay-ramdisk-j9cfoz7q/ramdisk.cpio.gz.uboot
218 21:44:19.709004 output: Image Name:
219 21:44:19.709420 output: Created: Thu Oct 31 21:44:19 2024
220 21:44:19.709625 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:44:19.709827 output: Data Size: 26056419 Bytes = 25445.72 KiB = 24.85 MiB
222 21:44:19.710026 output: Load Address: 00000000
223 21:44:19.710221 output: Entry Point: 00000000
224 21:44:19.710416 output:
225 21:44:19.711047 rename /var/lib/lava/dispatcher/tmp/918826/extract-overlay-ramdisk-j9cfoz7q/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/918826/tftp-deploy-42o3hy5k/ramdisk/ramdisk.cpio.gz.uboot
226 21:44:19.711482 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 21:44:19.711763 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 21:44:19.712164 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 21:44:19.712676 No LXC device requested
230 21:44:19.713258 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:44:19.713825 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 21:44:19.714364 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:44:19.714814 Checking files for TFTP limit of 4294967296 bytes.
234 21:44:19.717779 end: 1 tftp-deploy (duration 00:00:17) [common]
235 21:44:19.718428 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:44:19.719000 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:44:19.719545 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:44:19.720140 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:44:19.720724 Using kernel file from prepare-kernel: 918826/tftp-deploy-42o3hy5k/kernel/uImage
240 21:44:19.721383 substitutions:
241 21:44:19.721828 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:44:19.722266 - {DTB_ADDR}: 0x01070000
243 21:44:19.722700 - {DTB}: 918826/tftp-deploy-42o3hy5k/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 21:44:19.723137 - {INITRD}: 918826/tftp-deploy-42o3hy5k/ramdisk/ramdisk.cpio.gz.uboot
245 21:44:19.723570 - {KERNEL_ADDR}: 0x01080000
246 21:44:19.724023 - {KERNEL}: 918826/tftp-deploy-42o3hy5k/kernel/uImage
247 21:44:19.724462 - {LAVA_MAC}: None
248 21:44:19.724938 - {PRESEED_CONFIG}: None
249 21:44:19.725368 - {PRESEED_LOCAL}: None
250 21:44:19.725792 - {RAMDISK_ADDR}: 0x08000000
251 21:44:19.726215 - {RAMDISK}: 918826/tftp-deploy-42o3hy5k/ramdisk/ramdisk.cpio.gz.uboot
252 21:44:19.726642 - {ROOT_PART}: None
253 21:44:19.727068 - {ROOT}: None
254 21:44:19.727489 - {SERVER_IP}: 192.168.6.2
255 21:44:19.727917 - {TEE_ADDR}: 0x83000000
256 21:44:19.728372 - {TEE}: None
257 21:44:19.728801 Parsed boot commands:
258 21:44:19.729215 - setenv autoload no
259 21:44:19.729640 - setenv initrd_high 0xffffffff
260 21:44:19.730060 - setenv fdt_high 0xffffffff
261 21:44:19.730481 - dhcp
262 21:44:19.730904 - setenv serverip 192.168.6.2
263 21:44:19.731326 - tftpboot 0x01080000 918826/tftp-deploy-42o3hy5k/kernel/uImage
264 21:44:19.731749 - tftpboot 0x08000000 918826/tftp-deploy-42o3hy5k/ramdisk/ramdisk.cpio.gz.uboot
265 21:44:19.732199 - tftpboot 0x01070000 918826/tftp-deploy-42o3hy5k/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 21:44:19.732626 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:44:19.733060 - bootm 0x01080000 0x08000000 0x01070000
268 21:44:19.733607 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:44:19.735236 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:44:19.735722 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 21:44:19.750320 Setting prompt string to ['lava-test: # ']
273 21:44:19.751969 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:44:19.752679 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:44:19.753280 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:44:19.753832 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:44:19.755061 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 21:44:19.792180 >> OK - accepted request
279 21:44:19.794095 Returned 0 in 0 seconds
280 21:44:19.895410 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:44:19.897006 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:44:19.897589 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:44:19.898020 Setting prompt string to ['Hit any key to stop autoboot']
285 21:44:19.898463 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:44:19.899833 Trying 192.168.56.21...
287 21:44:19.900318 Connected to conserv1.
288 21:44:19.900710 Escape character is '^]'.
289 21:44:19.901074
290 21:44:19.901466 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 21:44:19.901906
292 21:44:27.271533 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 21:44:27.271964 bl2_stage_init 0x01
294 21:44:27.272233 bl2_stage_init 0x81
295 21:44:27.277142 hw id: 0x0000 - pwm id 0x01
296 21:44:27.277434 bl2_stage_init 0xc1
297 21:44:27.282662 bl2_stage_init 0x02
298 21:44:27.283048
299 21:44:27.283385 L0:00000000
300 21:44:27.283718 L1:00000703
301 21:44:27.283960 L2:00008067
302 21:44:27.284205 L3:15000000
303 21:44:27.288168 S1:00000000
304 21:44:27.288543 B2:20282000
305 21:44:27.288867 B1:a0f83180
306 21:44:27.289178
307 21:44:27.289491 TE: 69807
308 21:44:27.289804
309 21:44:27.293894 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 21:44:27.294172
311 21:44:27.299356 Board ID = 1
312 21:44:27.299621 Set cpu clk to 24M
313 21:44:27.299831 Set clk81 to 24M
314 21:44:27.305134 Use GP1_pll as DSU clk.
315 21:44:27.305391 DSU clk: 1200 Mhz
316 21:44:27.305604 CPU clk: 1200 MHz
317 21:44:27.310634 Set clk81 to 166.6M
318 21:44:27.316155 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 21:44:27.316416 board id: 1
320 21:44:27.322542 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 21:44:27.333992 fw parse done
322 21:44:27.340118 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 21:44:27.381742 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 21:44:27.393703 PIEI prepare done
325 21:44:27.394165 fastboot data load
326 21:44:27.394561 fastboot data verify
327 21:44:27.399236 verify result: 266
328 21:44:27.404912 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 21:44:27.405382 LPDDR4 probe
330 21:44:27.405773 ddr clk to 1584MHz
331 21:44:27.412851 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 21:44:27.450237
333 21:44:27.450817 dmc_version 0001
334 21:44:27.456813 Check phy result
335 21:44:27.462718 INFO : End of CA training
336 21:44:27.463185 INFO : End of initialization
337 21:44:27.468327 INFO : Training has run successfully!
338 21:44:27.468769 Check phy result
339 21:44:27.473912 INFO : End of initialization
340 21:44:27.474350 INFO : End of read enable training
341 21:44:27.479552 INFO : End of fine write leveling
342 21:44:27.485159 INFO : End of Write leveling coarse delay
343 21:44:27.485621 INFO : Training has run successfully!
344 21:44:27.486014 Check phy result
345 21:44:27.490727 INFO : End of initialization
346 21:44:27.491174 INFO : End of read dq deskew training
347 21:44:27.496374 INFO : End of MPR read delay center optimization
348 21:44:27.501916 INFO : End of write delay center optimization
349 21:44:27.507676 INFO : End of read delay center optimization
350 21:44:27.508302 INFO : End of max read latency training
351 21:44:27.513208 INFO : Training has run successfully!
352 21:44:27.513732 1D training succeed
353 21:44:27.522343 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 21:44:27.569887 Check phy result
355 21:44:27.570399 INFO : End of initialization
356 21:44:27.592346 INFO : End of 2D read delay Voltage center optimization
357 21:44:27.611443 INFO : End of 2D read delay Voltage center optimization
358 21:44:27.663401 INFO : End of 2D write delay Voltage center optimization
359 21:44:27.712553 INFO : End of 2D write delay Voltage center optimization
360 21:44:27.718119 INFO : Training has run successfully!
361 21:44:27.718575
362 21:44:27.718973 channel==0
363 21:44:27.723654 RxClkDly_Margin_A0==78 ps 8
364 21:44:27.724159 TxDqDly_Margin_A0==98 ps 10
365 21:44:27.729303 RxClkDly_Margin_A1==88 ps 9
366 21:44:27.729761 TxDqDly_Margin_A1==88 ps 9
367 21:44:27.730154 TrainedVREFDQ_A0==74
368 21:44:27.734932 TrainedVREFDQ_A1==74
369 21:44:27.735374 VrefDac_Margin_A0==24
370 21:44:27.735761 DeviceVref_Margin_A0==40
371 21:44:27.740439 VrefDac_Margin_A1==23
372 21:44:27.740880 DeviceVref_Margin_A1==40
373 21:44:27.741272
374 21:44:27.741657
375 21:44:27.742043 channel==1
376 21:44:27.746060 RxClkDly_Margin_A0==88 ps 9
377 21:44:27.746553 TxDqDly_Margin_A0==98 ps 10
378 21:44:27.751718 RxClkDly_Margin_A1==88 ps 9
379 21:44:27.752217 TxDqDly_Margin_A1==88 ps 9
380 21:44:27.757289 TrainedVREFDQ_A0==75
381 21:44:27.757759 TrainedVREFDQ_A1==75
382 21:44:27.758154 VrefDac_Margin_A0==23
383 21:44:27.762870 DeviceVref_Margin_A0==39
384 21:44:27.763338 VrefDac_Margin_A1==22
385 21:44:27.768577 DeviceVref_Margin_A1==39
386 21:44:27.769057
387 21:44:27.769456 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 21:44:27.769844
389 21:44:27.802003 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000018 00000015 00000019 00000016 00000017 00000017 00000017 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
390 21:44:27.802614 2D training succeed
391 21:44:27.807713 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 21:44:27.813215 auto size-- 65535DDR cs0 size: 2048MB
393 21:44:27.813664 DDR cs1 size: 2048MB
394 21:44:27.818847 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 21:44:27.819298 cs0 DataBus test pass
396 21:44:27.824459 cs1 DataBus test pass
397 21:44:27.824911 cs0 AddrBus test pass
398 21:44:27.825300 cs1 AddrBus test pass
399 21:44:27.825683
400 21:44:27.830076 100bdlr_step_size ps== 478
401 21:44:27.830551 result report
402 21:44:27.835652 boot times 0Enable ddr reg access
403 21:44:27.840833 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 21:44:27.854565 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 21:44:28.509517 bl2z: ptr: 05129330, size: 00001e40
406 21:44:28.516219 0.0;M3 CHK:0;cm4_sp_mode 0
407 21:44:28.516691 MVN_1=0x00000000
408 21:44:28.517102 MVN_2=0x00000000
409 21:44:28.527696 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 21:44:28.528180 OPS=0x04
411 21:44:28.528591 ring efuse init
412 21:44:28.533310 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 21:44:28.533751 [0.017310 Inits done]
414 21:44:28.534153 secure task start!
415 21:44:28.540696 high task start!
416 21:44:28.541125 low task start!
417 21:44:28.541526 run into bl31
418 21:44:28.549298 NOTICE: BL31: v1.3(release):4fc40b1
419 21:44:28.557205 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 21:44:28.557667 NOTICE: BL31: G12A normal boot!
421 21:44:28.572665 NOTICE: BL31: BL33 decompress pass
422 21:44:28.578444 ERROR: Error initializing runtime service opteed_fast
423 21:44:29.820063 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 21:44:29.820497 bl2_stage_init 0x01
425 21:44:29.820723 bl2_stage_init 0x81
426 21:44:29.825565 hw id: 0x0000 - pwm id 0x01
427 21:44:29.825864 bl2_stage_init 0xc1
428 21:44:29.830810 bl2_stage_init 0x02
429 21:44:29.831164
430 21:44:29.831384 L0:00000000
431 21:44:29.831597 L1:00000703
432 21:44:29.831801 L2:00008067
433 21:44:29.832055 L3:15000000
434 21:44:29.836450 S1:00000000
435 21:44:29.836762 B2:20282000
436 21:44:29.836990 B1:a0f83180
437 21:44:29.837208
438 21:44:29.837421 TE: 68168
439 21:44:29.837622
440 21:44:29.842031 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 21:44:29.847579
442 21:44:29.847869 Board ID = 1
443 21:44:29.848144 Set cpu clk to 24M
444 21:44:29.848363 Set clk81 to 24M
445 21:44:29.850877 Use GP1_pll as DSU clk.
446 21:44:29.851131 DSU clk: 1200 Mhz
447 21:44:29.856478 CPU clk: 1200 MHz
448 21:44:29.856749 Set clk81 to 166.6M
449 21:44:29.862099 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 21:44:29.862366 board id: 1
451 21:44:29.871904 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 21:44:29.882856 fw parse done
453 21:44:29.888816 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 21:44:29.931935 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 21:44:29.943166 PIEI prepare done
456 21:44:29.943534 fastboot data load
457 21:44:29.943751 fastboot data verify
458 21:44:29.948624 verify result: 266
459 21:44:29.954314 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 21:44:29.954611 LPDDR4 probe
461 21:44:29.954820 ddr clk to 1584MHz
462 21:44:31.328502 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 21:44:31.328949 bl2_stage_init 0x01
464 21:44:31.329202 bl2_stage_init 0x81
465 21:44:31.334013 hw id: 0x0000 - pwm id 0x01
466 21:44:31.334470 bl2_stage_init 0xc1
467 21:44:31.334854 bl2_stage_init 0x02
468 21:44:31.335234
469 21:44:31.339596 L0:00000000
470 21:44:31.339925 L1:00000703
471 21:44:31.340207 L2:00008067
472 21:44:31.340453 L3:15000000
473 21:44:31.340682 S1:00000000
474 21:44:31.345199 B2:20282000
475 21:44:31.345533 B1:a0f83180
476 21:44:31.345772
477 21:44:31.346005 TE: 74780
478 21:44:31.346230
479 21:44:31.350792 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 21:44:31.351263
481 21:44:31.356510 Board ID = 1
482 21:44:31.356979 Set cpu clk to 24M
483 21:44:31.357381 Set clk81 to 24M
484 21:44:31.362079 Use GP1_pll as DSU clk.
485 21:44:31.362407 DSU clk: 1200 Mhz
486 21:44:31.362648 CPU clk: 1200 MHz
487 21:44:31.362878 Set clk81 to 166.6M
488 21:44:31.373273 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 21:44:31.373801 board id: 1
490 21:44:31.379595 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 21:44:31.390617 fw parse done
492 21:44:31.396536 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 21:44:31.439596 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 21:44:31.450739 PIEI prepare done
495 21:44:31.451223 fastboot data load
496 21:44:31.451644 fastboot data verify
497 21:44:31.456266 verify result: 266
498 21:44:31.461926 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 21:44:31.462367 LPDDR4 probe
500 21:44:31.462772 ddr clk to 1584MHz
501 21:44:31.469864 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 21:44:31.507764
503 21:44:31.508330 dmc_version 0001
504 21:44:31.514642 Check phy result
505 21:44:31.520630 INFO : End of CA training
506 21:44:31.521063 INFO : End of initialization
507 21:44:31.526229 INFO : Training has run successfully!
508 21:44:31.526666 Check phy result
509 21:44:31.531817 INFO : End of initialization
510 21:44:31.532284 INFO : End of read enable training
511 21:44:31.537510 INFO : End of fine write leveling
512 21:44:31.543010 INFO : End of Write leveling coarse delay
513 21:44:31.543448 INFO : Training has run successfully!
514 21:44:31.543852 Check phy result
515 21:44:31.548620 INFO : End of initialization
516 21:44:31.549054 INFO : End of read dq deskew training
517 21:44:31.554191 INFO : End of MPR read delay center optimization
518 21:44:31.559831 INFO : End of write delay center optimization
519 21:44:31.565524 INFO : End of read delay center optimization
520 21:44:31.565953 INFO : End of max read latency training
521 21:44:31.571028 INFO : Training has run successfully!
522 21:44:31.571460 1D training succeed
523 21:44:31.580197 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 21:44:31.628598 Check phy result
525 21:44:31.629152 INFO : End of initialization
526 21:44:31.655921 INFO : End of 2D read delay Voltage center optimization
527 21:44:31.680032 INFO : End of 2D read delay Voltage center optimization
528 21:44:31.736749 INFO : End of 2D write delay Voltage center optimization
529 21:44:31.790606 INFO : End of 2D write delay Voltage center optimization
530 21:44:31.796219 INFO : Training has run successfully!
531 21:44:31.796691
532 21:44:31.797122 channel==0
533 21:44:31.801749 RxClkDly_Margin_A0==88 ps 9
534 21:44:31.802174 TxDqDly_Margin_A0==88 ps 9
535 21:44:31.807400 RxClkDly_Margin_A1==88 ps 9
536 21:44:31.807824 TxDqDly_Margin_A1==98 ps 10
537 21:44:31.808277 TrainedVREFDQ_A0==74
538 21:44:31.812952 TrainedVREFDQ_A1==75
539 21:44:31.813376 VrefDac_Margin_A0==24
540 21:44:31.813777 DeviceVref_Margin_A0==40
541 21:44:31.818536 VrefDac_Margin_A1==23
542 21:44:31.818958 DeviceVref_Margin_A1==39
543 21:44:31.819359
544 21:44:31.819759
545 21:44:31.820191 channel==1
546 21:44:31.824151 RxClkDly_Margin_A0==78 ps 8
547 21:44:31.824581 TxDqDly_Margin_A0==98 ps 10
548 21:44:31.829768 RxClkDly_Margin_A1==78 ps 8
549 21:44:31.830191 TxDqDly_Margin_A1==88 ps 9
550 21:44:31.835319 TrainedVREFDQ_A0==78
551 21:44:31.835740 TrainedVREFDQ_A1==75
552 21:44:31.836172 VrefDac_Margin_A0==22
553 21:44:31.840945 DeviceVref_Margin_A0==36
554 21:44:31.841368 VrefDac_Margin_A1==22
555 21:44:31.846556 DeviceVref_Margin_A1==39
556 21:44:31.846993
557 21:44:31.847396 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 21:44:31.847790
559 21:44:31.880174 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000018 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
560 21:44:31.880703 2D training succeed
561 21:44:31.885774 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 21:44:31.891583 auto size-- 65535DDR cs0 size: 2048MB
563 21:44:31.892054 DDR cs1 size: 2048MB
564 21:44:31.897002 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 21:44:31.897478 cs0 DataBus test pass
566 21:44:31.902594 cs1 DataBus test pass
567 21:44:31.903023 cs0 AddrBus test pass
568 21:44:31.903424 cs1 AddrBus test pass
569 21:44:31.903824
570 21:44:31.908188 100bdlr_step_size ps== 478
571 21:44:31.908626 result report
572 21:44:31.913770 boot times 0Enable ddr reg access
573 21:44:31.918978 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 21:44:31.932817 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 21:44:32.591247 bl2z: ptr: 05129330, size: 00001e40
576 21:44:32.598767 0.0;M3 CHK:0;cm4_sp_mode 0
577 21:44:32.599316 MVN_1=0x00000000
578 21:44:32.599733 MVN_2=0x00000000
579 21:44:32.610219 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 21:44:32.610699 OPS=0x04
581 21:44:32.611111 ring efuse init
582 21:44:32.613116 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 21:44:32.619208 [0.017354 Inits done]
584 21:44:32.619773 secure task start!
585 21:44:32.620232 high task start!
586 21:44:32.620634 low task start!
587 21:44:32.622479 run into bl31
588 21:44:32.632082 NOTICE: BL31: v1.3(release):4fc40b1
589 21:44:32.639848 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 21:44:32.640340 NOTICE: BL31: G12A normal boot!
591 21:44:32.655433 NOTICE: BL31: BL33 decompress pass
592 21:44:32.661547 ERROR: Error initializing runtime service opteed_fast
593 21:44:33.870719 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 21:44:33.871344 bl2_stage_init 0x01
595 21:44:33.871768 bl2_stage_init 0x81
596 21:44:33.876256 hw id: 0x0000 - pwm id 0x01
597 21:44:33.876706 bl2_stage_init 0xc1
598 21:44:33.881472 bl2_stage_init 0x02
599 21:44:33.881907
600 21:44:33.882318 L0:00000000
601 21:44:33.882720 L1:00000703
602 21:44:33.883119 L2:00008067
603 21:44:33.887021 L3:15000000
604 21:44:33.887452 S1:00000000
605 21:44:33.887855 B2:20282000
606 21:44:33.888291 B1:a0f83180
607 21:44:33.888690
608 21:44:33.889083 TE: 68726
609 21:44:33.889477
610 21:44:33.892622 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 21:44:33.898185
612 21:44:33.898621 Board ID = 1
613 21:44:33.899025 Set cpu clk to 24M
614 21:44:33.899422 Set clk81 to 24M
615 21:44:33.901745 Use GP1_pll as DSU clk.
616 21:44:33.902173 DSU clk: 1200 Mhz
617 21:44:33.907244 CPU clk: 1200 MHz
618 21:44:33.907677 Set clk81 to 166.6M
619 21:44:33.912978 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 21:44:33.913427 board id: 1
621 21:44:33.922685 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 21:44:33.933554 fw parse done
623 21:44:33.939548 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 21:44:33.982594 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 21:44:33.993766 PIEI prepare done
626 21:44:33.994334 fastboot data load
627 21:44:33.994750 fastboot data verify
628 21:44:33.999233 verify result: 266
629 21:44:34.004930 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 21:44:34.005377 LPDDR4 probe
631 21:44:34.005783 ddr clk to 1584MHz
632 21:44:34.012881 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 21:44:34.050634
634 21:44:34.051098 dmc_version 0001
635 21:44:34.057589 Check phy result
636 21:44:34.063554 INFO : End of CA training
637 21:44:34.064007 INFO : End of initialization
638 21:44:34.069155 INFO : Training has run successfully!
639 21:44:34.069587 Check phy result
640 21:44:34.074839 INFO : End of initialization
641 21:44:34.075282 INFO : End of read enable training
642 21:44:34.078115 INFO : End of fine write leveling
643 21:44:34.083571 INFO : End of Write leveling coarse delay
644 21:44:34.089262 INFO : Training has run successfully!
645 21:44:34.089704 Check phy result
646 21:44:34.090108 INFO : End of initialization
647 21:44:34.094843 INFO : End of read dq deskew training
648 21:44:34.100452 INFO : End of MPR read delay center optimization
649 21:44:34.100888 INFO : End of write delay center optimization
650 21:44:34.106058 INFO : End of read delay center optimization
651 21:44:34.111689 INFO : End of max read latency training
652 21:44:34.112155 INFO : Training has run successfully!
653 21:44:34.117254 1D training succeed
654 21:44:34.123208 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 21:44:34.171181 Check phy result
656 21:44:34.171816 INFO : End of initialization
657 21:44:34.198952 INFO : End of 2D read delay Voltage center optimization
658 21:44:34.223131 INFO : End of 2D read delay Voltage center optimization
659 21:44:34.279762 INFO : End of 2D write delay Voltage center optimization
660 21:44:34.333748 INFO : End of 2D write delay Voltage center optimization
661 21:44:34.339375 INFO : Training has run successfully!
662 21:44:34.339824
663 21:44:34.340281 channel==0
664 21:44:34.345067 RxClkDly_Margin_A0==78 ps 8
665 21:44:34.345505 TxDqDly_Margin_A0==98 ps 10
666 21:44:34.348279 RxClkDly_Margin_A1==88 ps 9
667 21:44:34.348712 TxDqDly_Margin_A1==98 ps 10
668 21:44:34.353801 TrainedVREFDQ_A0==76
669 21:44:34.354250 TrainedVREFDQ_A1==75
670 21:44:34.359357 VrefDac_Margin_A0==25
671 21:44:34.359788 DeviceVref_Margin_A0==38
672 21:44:34.360233 VrefDac_Margin_A1==23
673 21:44:34.365206 DeviceVref_Margin_A1==39
674 21:44:34.365646
675 21:44:34.366052
676 21:44:34.366449 channel==1
677 21:44:34.366840 RxClkDly_Margin_A0==88 ps 9
678 21:44:34.370618 TxDqDly_Margin_A0==98 ps 10
679 21:44:34.371054 RxClkDly_Margin_A1==88 ps 9
680 21:44:34.376198 TxDqDly_Margin_A1==88 ps 9
681 21:44:34.376643 TrainedVREFDQ_A0==75
682 21:44:34.377051 TrainedVREFDQ_A1==75
683 21:44:34.381730 VrefDac_Margin_A0==22
684 21:44:34.382168 DeviceVref_Margin_A0==38
685 21:44:34.387372 VrefDac_Margin_A1==22
686 21:44:34.387814 DeviceVref_Margin_A1==39
687 21:44:34.388263
688 21:44:34.393017 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 21:44:34.393468
690 21:44:34.421013 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
691 21:44:34.426541 2D training succeed
692 21:44:34.432201 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 21:44:34.432634 auto size-- 65535DDR cs0 size: 2048MB
694 21:44:34.437708 DDR cs1 size: 2048MB
695 21:44:34.438144 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 21:44:34.443311 cs0 DataBus test pass
697 21:44:34.443742 cs1 DataBus test pass
698 21:44:34.444174 cs0 AddrBus test pass
699 21:44:34.449002 cs1 AddrBus test pass
700 21:44:34.449429
701 21:44:34.449831 100bdlr_step_size ps== 485
702 21:44:34.450236 result report
703 21:44:34.454520 boot times 0Enable ddr reg access
704 21:44:34.462197 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 21:44:34.475120 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 21:44:35.134096 bl2z: ptr: 05129330, size: 00001e40
707 21:44:35.141495 0.0;M3 CHK:0;cm4_sp_mode 0
708 21:44:35.141897 MVN_1=0x00000000
709 21:44:35.142146 MVN_2=0x00000000
710 21:44:35.153093 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 21:44:35.153474 OPS=0x04
712 21:44:35.153722 ring efuse init
713 21:44:35.155975 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 21:44:35.161419 [0.017354 Inits done]
715 21:44:35.161737 secure task start!
716 21:44:35.161985 high task start!
717 21:44:35.162220 low task start!
718 21:44:35.165273 run into bl31
719 21:44:35.174858 NOTICE: BL31: v1.3(release):4fc40b1
720 21:44:35.182622 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 21:44:35.182945 NOTICE: BL31: G12A normal boot!
722 21:44:35.198249 NOTICE: BL31: BL33 decompress pass
723 21:44:35.203152 ERROR: Error initializing runtime service opteed_fast
724 21:44:35.999395
725 21:44:35.999835
726 21:44:36.004691 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 21:44:36.005015
728 21:44:36.008225 Model: Libre Computer AML-S905D3-CC Solitude
729 21:44:36.155720 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 21:44:36.170670 DRAM: 2 GiB (effective 3.8 GiB)
731 21:44:36.271739 Core: 406 devices, 33 uclasses, devicetree: separate
732 21:44:36.277500 WDT: Not starting watchdog@f0d0
733 21:44:36.302524 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 21:44:36.314839 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 21:44:36.319701 ** Bad device specification mmc 0 **
736 21:44:36.329750 Card did not respond to voltage select! : -110
737 21:44:36.337396 ** Bad device specification mmc 0 **
738 21:44:36.337903 Couldn't find partition mmc 0
739 21:44:36.345766 Card did not respond to voltage select! : -110
740 21:44:36.351264 ** Bad device specification mmc 0 **
741 21:44:36.351757 Couldn't find partition mmc 0
742 21:44:36.356336 Error: could not access storage.
743 21:44:36.652876 Net: eth0: ethernet@ff3f0000
744 21:44:36.653500 starting USB...
745 21:44:36.898551 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 21:44:36.899166 Starting the controller
747 21:44:36.904535 USB XHCI 1.10
748 21:44:38.459808 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 21:44:38.468028 scanning usb for storage devices... 0 Storage Device(s) found
751 21:44:38.519430 Hit any key to stop autoboot: 1
752 21:44:38.520469 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 21:44:38.521178 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 21:44:38.521772 Setting prompt string to ['=>']
755 21:44:38.522037 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 21:44:38.534143 0
757 21:44:38.535158 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 21:44:38.636070 => setenv autoload no
760 21:44:38.636687 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 21:44:38.640905 setenv autoload no
763 21:44:38.742212 => setenv initrd_high 0xffffffff
764 21:44:38.742938 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 21:44:38.747223 setenv initrd_high 0xffffffff
767 21:44:38.848455 => setenv fdt_high 0xffffffff
768 21:44:38.849232 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 21:44:38.853639 setenv fdt_high 0xffffffff
771 21:44:38.955075 => dhcp
772 21:44:38.955646 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 21:44:38.959751 dhcp
774 21:44:39.965028 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 21:44:39.965451 Speed: 1000, full duplex
776 21:44:39.965664 BOOTP broadcast 1
777 21:44:40.214464 BOOTP broadcast 2
778 21:44:40.229885 DHCP client bound to address 192.168.6.21 (263 ms)
780 21:44:40.331398 => setenv serverip 192.168.6.2
781 21:44:40.332172 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
782 21:44:40.336893 setenv serverip 192.168.6.2
784 21:44:40.438311 => tftpboot 0x01080000 918826/tftp-deploy-42o3hy5k/kernel/uImage
785 21:44:40.439006 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
786 21:44:40.446114 tftpboot 0x01080000 918826/tftp-deploy-42o3hy5k/kernel/uImage
787 21:44:40.446745 Speed: 1000, full duplex
788 21:44:40.447269 Using ethernet@ff3f0000 device
789 21:44:40.451407 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
790 21:44:40.457145 Filename '918826/tftp-deploy-42o3hy5k/kernel/uImage'.
791 21:44:40.460925 Load address: 0x1080000
792 21:44:43.777298 Loading: *################################################## 43.6 MiB
793 21:44:43.777898 13.1 MiB/s
794 21:44:43.778307 done
795 21:44:43.781553 Bytes transferred = 45713984 (2b98a40 hex)
797 21:44:43.882937 => tftpboot 0x08000000 918826/tftp-deploy-42o3hy5k/ramdisk/ramdisk.cpio.gz.uboot
798 21:44:43.883562 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
799 21:44:43.890240 tftpboot 0x08000000 918826/tftp-deploy-42o3hy5k/ramdisk/ramdisk.cpio.gz.uboot
800 21:44:43.890808 Speed: 1000, full duplex
801 21:44:43.891247 Using ethernet@ff3f0000 device
802 21:44:43.895705 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
803 21:44:43.905477 Filename '918826/tftp-deploy-42o3hy5k/ramdisk/ramdisk.cpio.gz.uboot'.
804 21:44:43.906078 Load address: 0x8000000
805 21:44:50.552292 Loading: *#################################################T UDP wrong checksum 00000005 000060a5
806 21:44:55.553388 T UDP wrong checksum 00000005 000060a5
807 21:45:05.554230 T T UDP wrong checksum 00000005 000060a5
808 21:45:25.559513 T T T T UDP wrong checksum 00000005 000060a5
809 21:45:29.879033 UDP wrong checksum 000000ff 00000aa4
810 21:45:29.888633 UDP wrong checksum 000000ff 00009396
811 21:45:31.332549 T UDP wrong checksum 000000ff 0000106d
812 21:45:31.342960 UDP wrong checksum 000000ff 0000a75f
813 21:45:40.563166 T
814 21:45:40.563775 Retry count exceeded; starting again
816 21:45:40.565225 end: 2.4.3 bootloader-commands (duration 00:01:02) [common]
819 21:45:40.567008 end: 2.4 uboot-commands (duration 00:01:21) [common]
821 21:45:40.568404 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
823 21:45:40.569409 end: 2 uboot-action (duration 00:01:21) [common]
825 21:45:40.570942 Cleaning after the job
826 21:45:40.571500 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/918826/tftp-deploy-42o3hy5k/ramdisk
827 21:45:40.572976 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/918826/tftp-deploy-42o3hy5k/kernel
828 21:45:40.617619 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/918826/tftp-deploy-42o3hy5k/dtb
829 21:45:40.618731 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/918826/tftp-deploy-42o3hy5k/modules
830 21:45:40.637438 start: 4.1 power-off (timeout 00:00:30) [common]
831 21:45:40.638128 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
832 21:45:40.728412 >> OK - accepted request
833 21:45:40.732913 Returned 0 in 0 seconds
834 21:45:40.834108 end: 4.1 power-off (duration 00:00:00) [common]
836 21:45:40.835773 start: 4.2 read-feedback (timeout 00:10:00) [common]
837 21:45:40.836940 Listened to connection for namespace 'common' for up to 1s
838 21:45:41.837335 Finalising connection for namespace 'common'
839 21:45:41.837824 Disconnecting from shell: Finalise
840 21:45:41.838109 =>
841 21:45:41.938764 end: 4.2 read-feedback (duration 00:00:01) [common]
842 21:45:41.939206 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/918826
843 21:45:42.204519 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/918826
844 21:45:42.205143 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.