Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:12:34.640869 lava-dispatcher, installed at version: 2024.01
2 22:12:34.641603 start: 0 validate
3 22:12:34.642066 Start time: 2024-10-31 22:12:34.642037+00:00 (UTC)
4 22:12:34.642599 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:12:34.643124 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:12:34.681837 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:12:34.682414 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-54-gb69ef01da0f2%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 22:12:34.715209 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:12:34.715799 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-54-gb69ef01da0f2%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 22:12:34.747685 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:12:34.748368 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:12:34.781573 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 22:12:34.782042 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-54-gb69ef01da0f2%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 22:12:34.822632 validate duration: 0.18
16 22:12:34.823478 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:12:34.823821 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:12:34.824179 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:12:34.824765 Not decompressing ramdisk as can be used compressed.
20 22:12:34.825221 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 22:12:34.825526 saving as /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/ramdisk/initrd.cpio.gz
22 22:12:34.825814 total size: 5628169 (5 MB)
23 22:12:34.865655 progress 0 % (0 MB)
24 22:12:34.873024 progress 5 % (0 MB)
25 22:12:34.880749 progress 10 % (0 MB)
26 22:12:34.887583 progress 15 % (0 MB)
27 22:12:34.895138 progress 20 % (1 MB)
28 22:12:34.899111 progress 25 % (1 MB)
29 22:12:34.903064 progress 30 % (1 MB)
30 22:12:34.907057 progress 35 % (1 MB)
31 22:12:34.910602 progress 40 % (2 MB)
32 22:12:34.914580 progress 45 % (2 MB)
33 22:12:34.918147 progress 50 % (2 MB)
34 22:12:34.922070 progress 55 % (2 MB)
35 22:12:34.925974 progress 60 % (3 MB)
36 22:12:34.929492 progress 65 % (3 MB)
37 22:12:34.933493 progress 70 % (3 MB)
38 22:12:34.937010 progress 75 % (4 MB)
39 22:12:34.940900 progress 80 % (4 MB)
40 22:12:34.944449 progress 85 % (4 MB)
41 22:12:34.948311 progress 90 % (4 MB)
42 22:12:34.951913 progress 95 % (5 MB)
43 22:12:34.955146 progress 100 % (5 MB)
44 22:12:34.955783 5 MB downloaded in 0.13 s (41.30 MB/s)
45 22:12:34.956339 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:12:34.957243 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:12:34.957539 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:12:34.957811 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:12:34.958286 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-54-gb69ef01da0f2/arm64/defconfig/gcc-12/kernel/Image
51 22:12:34.958536 saving as /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/kernel/Image
52 22:12:34.958747 total size: 45713920 (43 MB)
53 22:12:34.958958 No compression specified
54 22:12:34.996496 progress 0 % (0 MB)
55 22:12:35.024366 progress 5 % (2 MB)
56 22:12:35.051767 progress 10 % (4 MB)
57 22:12:35.079178 progress 15 % (6 MB)
58 22:12:35.106488 progress 20 % (8 MB)
59 22:12:35.133723 progress 25 % (10 MB)
60 22:12:35.160894 progress 30 % (13 MB)
61 22:12:35.188244 progress 35 % (15 MB)
62 22:12:35.215471 progress 40 % (17 MB)
63 22:12:35.242469 progress 45 % (19 MB)
64 22:12:35.269939 progress 50 % (21 MB)
65 22:12:35.297504 progress 55 % (24 MB)
66 22:12:35.325144 progress 60 % (26 MB)
67 22:12:35.352178 progress 65 % (28 MB)
68 22:12:35.379501 progress 70 % (30 MB)
69 22:12:35.406890 progress 75 % (32 MB)
70 22:12:35.434455 progress 80 % (34 MB)
71 22:12:35.461338 progress 85 % (37 MB)
72 22:12:35.490867 progress 90 % (39 MB)
73 22:12:35.518322 progress 95 % (41 MB)
74 22:12:35.545239 progress 100 % (43 MB)
75 22:12:35.545753 43 MB downloaded in 0.59 s (74.27 MB/s)
76 22:12:35.546237 end: 1.2.1 http-download (duration 00:00:01) [common]
78 22:12:35.547066 end: 1.2 download-retry (duration 00:00:01) [common]
79 22:12:35.547347 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:12:35.547615 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:12:35.548111 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-54-gb69ef01da0f2/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 22:12:35.548427 saving as /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/dtb/meson-g12b-a311d-libretech-cc.dtb
83 22:12:35.548638 total size: 54703 (0 MB)
84 22:12:35.548847 No compression specified
85 22:12:35.588165 progress 59 % (0 MB)
86 22:12:35.589042 progress 100 % (0 MB)
87 22:12:35.589707 0 MB downloaded in 0.04 s (1.27 MB/s)
88 22:12:35.590207 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:12:35.591118 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:12:35.591424 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:12:35.591695 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:12:35.592169 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 22:12:35.592440 saving as /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/nfsrootfs/full.rootfs.tar
95 22:12:35.592647 total size: 120894716 (115 MB)
96 22:12:35.592860 Using unxz to decompress xz
97 22:12:35.624631 progress 0 % (0 MB)
98 22:12:36.415102 progress 5 % (5 MB)
99 22:12:37.252504 progress 10 % (11 MB)
100 22:12:38.075976 progress 15 % (17 MB)
101 22:12:38.823132 progress 20 % (23 MB)
102 22:12:39.418395 progress 25 % (28 MB)
103 22:12:40.254318 progress 30 % (34 MB)
104 22:12:41.047836 progress 35 % (40 MB)
105 22:12:41.393103 progress 40 % (46 MB)
106 22:12:41.762621 progress 45 % (51 MB)
107 22:12:42.482146 progress 50 % (57 MB)
108 22:12:43.369197 progress 55 % (63 MB)
109 22:12:44.149892 progress 60 % (69 MB)
110 22:12:44.907248 progress 65 % (74 MB)
111 22:12:45.681996 progress 70 % (80 MB)
112 22:12:46.505278 progress 75 % (86 MB)
113 22:12:47.287209 progress 80 % (92 MB)
114 22:12:48.044540 progress 85 % (98 MB)
115 22:12:48.896898 progress 90 % (103 MB)
116 22:12:49.669512 progress 95 % (109 MB)
117 22:12:50.505247 progress 100 % (115 MB)
118 22:12:50.517619 115 MB downloaded in 14.92 s (7.72 MB/s)
119 22:12:50.518181 end: 1.4.1 http-download (duration 00:00:15) [common]
121 22:12:50.518994 end: 1.4 download-retry (duration 00:00:15) [common]
122 22:12:50.519260 start: 1.5 download-retry (timeout 00:09:44) [common]
123 22:12:50.519520 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 22:12:50.520148 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-54-gb69ef01da0f2/arm64/defconfig/gcc-12/modules.tar.xz
125 22:12:50.520676 saving as /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/modules/modules.tar
126 22:12:50.521121 total size: 11610020 (11 MB)
127 22:12:50.521576 Using unxz to decompress xz
128 22:12:50.564893 progress 0 % (0 MB)
129 22:12:50.631609 progress 5 % (0 MB)
130 22:12:50.705814 progress 10 % (1 MB)
131 22:12:50.784778 progress 15 % (1 MB)
132 22:12:50.861939 progress 20 % (2 MB)
133 22:12:50.936742 progress 25 % (2 MB)
134 22:12:51.014494 progress 30 % (3 MB)
135 22:12:51.089291 progress 35 % (3 MB)
136 22:12:51.163366 progress 40 % (4 MB)
137 22:12:51.246963 progress 45 % (5 MB)
138 22:12:51.327843 progress 50 % (5 MB)
139 22:12:51.405068 progress 55 % (6 MB)
140 22:12:51.484526 progress 60 % (6 MB)
141 22:12:51.568052 progress 65 % (7 MB)
142 22:12:51.650456 progress 70 % (7 MB)
143 22:12:51.724223 progress 75 % (8 MB)
144 22:12:51.805016 progress 80 % (8 MB)
145 22:12:51.883659 progress 85 % (9 MB)
146 22:12:51.953808 progress 90 % (9 MB)
147 22:12:52.051032 progress 95 % (10 MB)
148 22:12:52.150930 progress 100 % (11 MB)
149 22:12:52.162461 11 MB downloaded in 1.64 s (6.75 MB/s)
150 22:12:52.163098 end: 1.5.1 http-download (duration 00:00:02) [common]
152 22:12:52.163944 end: 1.5 download-retry (duration 00:00:02) [common]
153 22:12:52.164594 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 22:12:52.165192 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 22:13:08.309302 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/918825/extract-nfsrootfs-_7fnanbq
156 22:13:08.309910 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 22:13:08.310198 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
158 22:13:08.310944 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d
159 22:13:08.311411 makedir: /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin
160 22:13:08.311742 makedir: /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/tests
161 22:13:08.312104 makedir: /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/results
162 22:13:08.312461 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-add-keys
163 22:13:08.313000 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-add-sources
164 22:13:08.313516 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-background-process-start
165 22:13:08.314038 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-background-process-stop
166 22:13:08.314612 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-common-functions
167 22:13:08.315140 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-echo-ipv4
168 22:13:08.315648 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-install-packages
169 22:13:08.316165 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-installed-packages
170 22:13:08.316659 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-os-build
171 22:13:08.317138 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-probe-channel
172 22:13:08.317620 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-probe-ip
173 22:13:08.318091 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-target-ip
174 22:13:08.318564 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-target-mac
175 22:13:08.319046 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-target-storage
176 22:13:08.319571 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-test-case
177 22:13:08.320187 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-test-event
178 22:13:08.320688 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-test-feedback
179 22:13:08.321170 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-test-raise
180 22:13:08.321643 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-test-reference
181 22:13:08.322112 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-test-runner
182 22:13:08.322593 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-test-set
183 22:13:08.323065 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-test-shell
184 22:13:08.323582 Updating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-add-keys (debian)
185 22:13:08.324159 Updating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-add-sources (debian)
186 22:13:08.324681 Updating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-install-packages (debian)
187 22:13:08.325192 Updating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-installed-packages (debian)
188 22:13:08.325686 Updating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/bin/lava-os-build (debian)
189 22:13:08.326124 Creating /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/environment
190 22:13:08.326496 LAVA metadata
191 22:13:08.326762 - LAVA_JOB_ID=918825
192 22:13:08.326976 - LAVA_DISPATCHER_IP=192.168.6.2
193 22:13:08.327330 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 22:13:08.328341 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 22:13:08.328674 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 22:13:08.328885 skipped lava-vland-overlay
197 22:13:08.329125 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 22:13:08.329400 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 22:13:08.329619 skipped lava-multinode-overlay
200 22:13:08.329861 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 22:13:08.330111 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 22:13:08.330359 Loading test definitions
203 22:13:08.330630 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 22:13:08.330850 Using /lava-918825 at stage 0
205 22:13:08.331903 uuid=918825_1.6.2.4.1 testdef=None
206 22:13:08.332251 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 22:13:08.332519 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 22:13:08.334129 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 22:13:08.334931 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 22:13:08.336906 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 22:13:08.337740 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 22:13:08.339558 runner path: /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/0/tests/0_timesync-off test_uuid 918825_1.6.2.4.1
215 22:13:08.340129 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 22:13:08.340952 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 22:13:08.341177 Using /lava-918825 at stage 0
219 22:13:08.341529 Fetching tests from https://github.com/kernelci/test-definitions.git
220 22:13:08.341822 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/0/tests/1_kselftest-alsa'
221 22:13:11.834472 Running '/usr/bin/git checkout kernelci.org
222 22:13:12.278857 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 22:13:12.281882 uuid=918825_1.6.2.4.5 testdef=None
224 22:13:12.282662 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 22:13:12.284638 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
227 22:13:12.291705 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 22:13:12.293775 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
230 22:13:12.303105 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 22:13:12.305271 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
233 22:13:12.314402 runner path: /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/0/tests/1_kselftest-alsa test_uuid 918825_1.6.2.4.5
234 22:13:12.315075 BOARD='meson-g12b-a311d-libretech-cc'
235 22:13:12.315614 BRANCH='broonie-spi'
236 22:13:12.316189 SKIPFILE='/dev/null'
237 22:13:12.316713 SKIP_INSTALL='True'
238 22:13:12.317237 TESTPROG_URL='http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-54-gb69ef01da0f2/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 22:13:12.317798 TST_CASENAME=''
240 22:13:12.318318 TST_CMDFILES='alsa'
241 22:13:12.319583 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 22:13:12.321594 Creating lava-test-runner.conf files
244 22:13:12.322135 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/918825/lava-overlay-jitcge4d/lava-918825/0 for stage 0
245 22:13:12.322977 - 0_timesync-off
246 22:13:12.323575 - 1_kselftest-alsa
247 22:13:12.324286 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 22:13:12.324653 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 22:13:35.557959 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 22:13:35.558402 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 22:13:35.558700 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 22:13:35.559012 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 22:13:35.559310 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 22:13:36.166963 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 22:13:36.167442 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
256 22:13:36.167694 extracting modules file /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/modules/modules.tar to /var/lib/lava/dispatcher/tmp/918825/extract-nfsrootfs-_7fnanbq
257 22:13:37.501227 extracting modules file /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/modules/modules.tar to /var/lib/lava/dispatcher/tmp/918825/extract-overlay-ramdisk-d85ewu7w/ramdisk
258 22:13:38.862967 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 22:13:38.863425 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
260 22:13:38.863703 [common] Applying overlay to NFS
261 22:13:38.863920 [common] Applying overlay /var/lib/lava/dispatcher/tmp/918825/compress-overlay-mgtxvv4x/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/918825/extract-nfsrootfs-_7fnanbq
262 22:13:41.679780 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 22:13:41.680268 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 22:13:41.680543 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 22:13:41.680771 Converting downloaded kernel to a uImage
266 22:13:41.681080 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/kernel/Image /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/kernel/uImage
267 22:13:42.144329 output: Image Name:
268 22:13:42.144750 output: Created: Thu Oct 31 22:13:41 2024
269 22:13:42.144959 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 22:13:42.145164 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 22:13:42.145365 output: Load Address: 01080000
272 22:13:42.145563 output: Entry Point: 01080000
273 22:13:42.145759 output:
274 22:13:42.146089 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 22:13:42.146357 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 22:13:42.146624 start: 1.6.7 configure-preseed-file (timeout 00:08:53) [common]
277 22:13:42.146880 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 22:13:42.147136 start: 1.6.8 compress-ramdisk (timeout 00:08:53) [common]
279 22:13:42.147394 Building ramdisk /var/lib/lava/dispatcher/tmp/918825/extract-overlay-ramdisk-d85ewu7w/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/918825/extract-overlay-ramdisk-d85ewu7w/ramdisk
280 22:13:44.297861 >> 166774 blocks
281 22:13:52.004482 Adding RAMdisk u-boot header.
282 22:13:52.005149 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/918825/extract-overlay-ramdisk-d85ewu7w/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/918825/extract-overlay-ramdisk-d85ewu7w/ramdisk.cpio.gz.uboot
283 22:13:52.245843 output: Image Name:
284 22:13:52.246270 output: Created: Thu Oct 31 22:13:52 2024
285 22:13:52.246481 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 22:13:52.246684 output: Data Size: 23430499 Bytes = 22881.35 KiB = 22.35 MiB
287 22:13:52.246884 output: Load Address: 00000000
288 22:13:52.247081 output: Entry Point: 00000000
289 22:13:52.247279 output:
290 22:13:52.247958 rename /var/lib/lava/dispatcher/tmp/918825/extract-overlay-ramdisk-d85ewu7w/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/ramdisk/ramdisk.cpio.gz.uboot
291 22:13:52.248694 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 22:13:52.249232 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 22:13:52.249749 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:43) [common]
294 22:13:52.250200 No LXC device requested
295 22:13:52.250690 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 22:13:52.251187 start: 1.8 deploy-device-env (timeout 00:08:43) [common]
297 22:13:52.251673 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 22:13:52.252109 Checking files for TFTP limit of 4294967296 bytes.
299 22:13:52.254745 end: 1 tftp-deploy (duration 00:01:17) [common]
300 22:13:52.255306 start: 2 uboot-action (timeout 00:05:00) [common]
301 22:13:52.255822 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 22:13:52.256351 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 22:13:52.256847 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 22:13:52.257366 Using kernel file from prepare-kernel: 918825/tftp-deploy-l50qmk55/kernel/uImage
305 22:13:52.257987 substitutions:
306 22:13:52.258387 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 22:13:52.258785 - {DTB_ADDR}: 0x01070000
308 22:13:52.259176 - {DTB}: 918825/tftp-deploy-l50qmk55/dtb/meson-g12b-a311d-libretech-cc.dtb
309 22:13:52.259574 - {INITRD}: 918825/tftp-deploy-l50qmk55/ramdisk/ramdisk.cpio.gz.uboot
310 22:13:52.259967 - {KERNEL_ADDR}: 0x01080000
311 22:13:52.260390 - {KERNEL}: 918825/tftp-deploy-l50qmk55/kernel/uImage
312 22:13:52.260778 - {LAVA_MAC}: None
313 22:13:52.261202 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/918825/extract-nfsrootfs-_7fnanbq
314 22:13:52.261593 - {NFS_SERVER_IP}: 192.168.6.2
315 22:13:52.261978 - {PRESEED_CONFIG}: None
316 22:13:52.262360 - {PRESEED_LOCAL}: None
317 22:13:52.262741 - {RAMDISK_ADDR}: 0x08000000
318 22:13:52.263119 - {RAMDISK}: 918825/tftp-deploy-l50qmk55/ramdisk/ramdisk.cpio.gz.uboot
319 22:13:52.263499 - {ROOT_PART}: None
320 22:13:52.263877 - {ROOT}: None
321 22:13:52.264284 - {SERVER_IP}: 192.168.6.2
322 22:13:52.264665 - {TEE_ADDR}: 0x83000000
323 22:13:52.265043 - {TEE}: None
324 22:13:52.265421 Parsed boot commands:
325 22:13:52.265789 - setenv autoload no
326 22:13:52.266167 - setenv initrd_high 0xffffffff
327 22:13:52.266545 - setenv fdt_high 0xffffffff
328 22:13:52.266919 - dhcp
329 22:13:52.267293 - setenv serverip 192.168.6.2
330 22:13:52.267672 - tftpboot 0x01080000 918825/tftp-deploy-l50qmk55/kernel/uImage
331 22:13:52.268081 - tftpboot 0x08000000 918825/tftp-deploy-l50qmk55/ramdisk/ramdisk.cpio.gz.uboot
332 22:13:52.268469 - tftpboot 0x01070000 918825/tftp-deploy-l50qmk55/dtb/meson-g12b-a311d-libretech-cc.dtb
333 22:13:52.268854 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/918825/extract-nfsrootfs-_7fnanbq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 22:13:52.269246 - bootm 0x01080000 0x08000000 0x01070000
335 22:13:52.269741 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 22:13:52.271204 start: 2.3 connect-device (timeout 00:05:00) [common]
338 22:13:52.271619 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 22:13:52.285796 Setting prompt string to ['lava-test: # ']
340 22:13:52.287318 end: 2.3 connect-device (duration 00:00:00) [common]
341 22:13:52.287915 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 22:13:52.288544 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 22:13:52.289082 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 22:13:52.290241 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 22:13:52.326473 >> OK - accepted request
346 22:13:52.328342 Returned 0 in 0 seconds
347 22:13:52.429442 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 22:13:52.431079 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 22:13:52.431646 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 22:13:52.432239 Setting prompt string to ['Hit any key to stop autoboot']
352 22:13:52.432717 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 22:13:52.434316 Trying 192.168.56.21...
354 22:13:52.434794 Connected to conserv1.
355 22:13:52.435222 Escape character is '^]'.
356 22:13:52.435646
357 22:13:52.436104 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 22:13:52.436539
359 22:14:03.798591 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
360 22:14:03.799201 bl2_stage_init 0x81
361 22:14:03.804178 hw id: 0x0000 - pwm id 0x01
362 22:14:03.804641 bl2_stage_init 0xc1
363 22:14:03.805061 bl2_stage_init 0x02
364 22:14:03.805476
365 22:14:03.809740 L0:00000000
366 22:14:03.810182 L1:20000703
367 22:14:03.810600 L2:00008067
368 22:14:03.810997 L3:14000000
369 22:14:03.811394 B2:00402000
370 22:14:03.812490 B1:e0f83180
371 22:14:03.812931
372 22:14:03.813335 TE: 58150
373 22:14:03.813727
374 22:14:03.823706 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
375 22:14:03.824165
376 22:14:03.824564 Board ID = 1
377 22:14:03.824951 Set A53 clk to 24M
378 22:14:03.825336 Set A73 clk to 24M
379 22:14:03.829291 Set clk81 to 24M
380 22:14:03.829716 A53 clk: 1200 MHz
381 22:14:03.830108 A73 clk: 1200 MHz
382 22:14:03.832580 CLK81: 166.6M
383 22:14:03.832996 smccc: 00012aac
384 22:14:03.838113 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
385 22:14:03.843804 board id: 1
386 22:14:03.849089 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
387 22:14:03.859811 fw parse done
388 22:14:03.865820 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
389 22:14:03.908360 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
390 22:14:03.919339 PIEI prepare done
391 22:14:03.919754 fastboot data load
392 22:14:03.920190 fastboot data verify
393 22:14:03.925142 verify result: 266
394 22:14:03.930604 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
395 22:14:03.931027 LPDDR4 probe
396 22:14:03.931419 ddr clk to 1584MHz
397 22:14:03.938683 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
398 22:14:03.976023
399 22:14:03.976449 dmc_version 0001
400 22:14:03.982657 Check phy result
401 22:14:03.988480 INFO : End of CA training
402 22:14:03.988894 INFO : End of initialization
403 22:14:03.993987 INFO : Training has run successfully!
404 22:14:03.994401 Check phy result
405 22:14:03.999552 INFO : End of initialization
406 22:14:03.999962 INFO : End of read enable training
407 22:14:04.005235 INFO : End of fine write leveling
408 22:14:04.009192 INFO : End of Write leveling coarse delay
409 22:14:04.012438 INFO : Training has run successfully!
410 22:14:04.012853 Check phy result
411 22:14:04.018044 INFO : End of initialization
412 22:14:04.018469 INFO : End of read dq deskew training
413 22:14:04.023621 INFO : End of MPR read delay center optimization
414 22:14:04.029111 INFO : End of write delay center optimization
415 22:14:04.029540 INFO : End of read delay center optimization
416 22:14:04.034732 INFO : End of max read latency training
417 22:14:04.040302 INFO : Training has run successfully!
418 22:14:04.040714 1D training succeed
419 22:14:04.047955 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
420 22:14:04.094565 Check phy result
421 22:14:04.095013 INFO : End of initialization
422 22:14:04.117263 INFO : End of 2D read delay Voltage center optimization
423 22:14:04.136587 INFO : End of 2D read delay Voltage center optimization
424 22:14:04.189567 INFO : End of 2D write delay Voltage center optimization
425 22:14:04.238973 INFO : End of 2D write delay Voltage center optimization
426 22:14:04.244475 INFO : Training has run successfully!
427 22:14:04.244886
428 22:14:04.245283 channel==0
429 22:14:04.250076 RxClkDly_Margin_A0==88 ps 9
430 22:14:04.250490 TxDqDly_Margin_A0==98 ps 10
431 22:14:04.255773 RxClkDly_Margin_A1==88 ps 9
432 22:14:04.256240 TxDqDly_Margin_A1==98 ps 10
433 22:14:04.256636 TrainedVREFDQ_A0==74
434 22:14:04.261361 TrainedVREFDQ_A1==74
435 22:14:04.261776 VrefDac_Margin_A0==25
436 22:14:04.262165 DeviceVref_Margin_A0==40
437 22:14:04.266979 VrefDac_Margin_A1==25
438 22:14:04.267392 DeviceVref_Margin_A1==40
439 22:14:04.267783
440 22:14:04.268205
441 22:14:04.272461 channel==1
442 22:14:04.272872 RxClkDly_Margin_A0==98 ps 10
443 22:14:04.273261 TxDqDly_Margin_A0==98 ps 10
444 22:14:04.278074 RxClkDly_Margin_A1==98 ps 10
445 22:14:04.278489 TxDqDly_Margin_A1==88 ps 9
446 22:14:04.283767 TrainedVREFDQ_A0==77
447 22:14:04.284211 TrainedVREFDQ_A1==77
448 22:14:04.284603 VrefDac_Margin_A0==22
449 22:14:04.289350 DeviceVref_Margin_A0==37
450 22:14:04.289763 VrefDac_Margin_A1==24
451 22:14:04.295009 DeviceVref_Margin_A1==37
452 22:14:04.295419
453 22:14:04.295813 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
454 22:14:04.300590
455 22:14:04.328545 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
456 22:14:04.329035 2D training succeed
457 22:14:04.334122 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
458 22:14:04.339627 auto size-- 65535DDR cs0 size: 2048MB
459 22:14:04.340068 DDR cs1 size: 2048MB
460 22:14:04.345205 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
461 22:14:04.345625 cs0 DataBus test pass
462 22:14:04.350866 cs1 DataBus test pass
463 22:14:04.351286 cs0 AddrBus test pass
464 22:14:04.351676 cs1 AddrBus test pass
465 22:14:04.352090
466 22:14:04.356425 100bdlr_step_size ps== 420
467 22:14:04.356844 result report
468 22:14:04.362039 boot times 0Enable ddr reg access
469 22:14:04.367457 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
470 22:14:04.380985 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
471 22:14:04.954592 0.0;M3 CHK:0;cm4_sp_mode 0
472 22:14:04.955088 MVN_1=0x00000000
473 22:14:04.960105 MVN_2=0x00000000
474 22:14:04.965882 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
475 22:14:04.966312 OPS=0x10
476 22:14:04.966716 ring efuse init
477 22:14:04.967111 chipver efuse init
478 22:14:04.971446 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
479 22:14:04.977048 [0.018961 Inits done]
480 22:14:04.977473 secure task start!
481 22:14:04.977874 high task start!
482 22:14:04.981626 low task start!
483 22:14:04.982049 run into bl31
484 22:14:04.988282 NOTICE: BL31: v1.3(release):4fc40b1
485 22:14:04.996090 NOTICE: BL31: Built : 15:58:17, May 22 2019
486 22:14:04.996518 NOTICE: BL31: G12A normal boot!
487 22:14:05.021455 NOTICE: BL31: BL33 decompress pass
488 22:14:05.027167 ERROR: Error initializing runtime service opteed_fast
489 22:14:06.260110
490 22:14:06.260604
491 22:14:06.268403 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
492 22:14:06.268838
493 22:14:06.269247 Model: Libre Computer AML-A311D-CC Alta
494 22:14:06.476832 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
495 22:14:06.500230 DRAM: 2 GiB (effective 3.8 GiB)
496 22:14:06.643224 Core: 408 devices, 31 uclasses, devicetree: separate
497 22:14:06.649114 WDT: Not starting watchdog@f0d0
498 22:14:06.681391 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
499 22:14:06.693805 Loading Environment from FAT... Card did not respond to voltage select! : -110
500 22:14:06.698798 ** Bad device specification mmc 0 **
501 22:14:06.709128 Card did not respond to voltage select! : -110
502 22:14:06.716767 ** Bad device specification mmc 0 **
503 22:14:06.717188 Couldn't find partition mmc 0
504 22:14:06.725132 Card did not respond to voltage select! : -110
505 22:14:06.730631 ** Bad device specification mmc 0 **
506 22:14:06.731051 Couldn't find partition mmc 0
507 22:14:06.735678 Error: could not access storage.
508 22:14:07.999054 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
509 22:14:07.999588 bl2_stage_init 0x01
510 22:14:08.000062 bl2_stage_init 0x81
511 22:14:08.004673 hw id: 0x0000 - pwm id 0x01
512 22:14:08.005107 bl2_stage_init 0xc1
513 22:14:08.005512 bl2_stage_init 0x02
514 22:14:08.005911
515 22:14:08.010301 L0:00000000
516 22:14:08.010729 L1:20000703
517 22:14:08.011128 L2:00008067
518 22:14:08.011521 L3:14000000
519 22:14:08.015811 B2:00402000
520 22:14:08.016262 B1:e0f83180
521 22:14:08.016665
522 22:14:08.017063 TE: 58167
523 22:14:08.017458
524 22:14:08.021409 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 22:14:08.021839
526 22:14:08.022242 Board ID = 1
527 22:14:08.027019 Set A53 clk to 24M
528 22:14:08.027441 Set A73 clk to 24M
529 22:14:08.027843 Set clk81 to 24M
530 22:14:08.032652 A53 clk: 1200 MHz
531 22:14:08.033081 A73 clk: 1200 MHz
532 22:14:08.033480 CLK81: 166.6M
533 22:14:08.033875 smccc: 00012abd
534 22:14:08.038308 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 22:14:08.043823 board id: 1
536 22:14:08.049699 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 22:14:08.060368 fw parse done
538 22:14:08.066373 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 22:14:08.108993 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 22:14:08.119866 PIEI prepare done
541 22:14:08.120330 fastboot data load
542 22:14:08.120737 fastboot data verify
543 22:14:08.125532 verify result: 266
544 22:14:08.131149 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 22:14:08.131572 LPDDR4 probe
546 22:14:08.131968 ddr clk to 1584MHz
547 22:14:08.139111 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 22:14:08.176339
549 22:14:08.176765 dmc_version 0001
550 22:14:08.183029 Check phy result
551 22:14:08.188907 INFO : End of CA training
552 22:14:08.189329 INFO : End of initialization
553 22:14:08.194501 INFO : Training has run successfully!
554 22:14:08.194923 Check phy result
555 22:14:08.200142 INFO : End of initialization
556 22:14:08.200561 INFO : End of read enable training
557 22:14:08.203462 INFO : End of fine write leveling
558 22:14:08.208948 INFO : End of Write leveling coarse delay
559 22:14:08.214552 INFO : Training has run successfully!
560 22:14:08.214972 Check phy result
561 22:14:08.215371 INFO : End of initialization
562 22:14:08.220177 INFO : End of read dq deskew training
563 22:14:08.225757 INFO : End of MPR read delay center optimization
564 22:14:08.226182 INFO : End of write delay center optimization
565 22:14:08.231392 INFO : End of read delay center optimization
566 22:14:08.236955 INFO : End of max read latency training
567 22:14:08.237384 INFO : Training has run successfully!
568 22:14:08.242555 1D training succeed
569 22:14:08.248527 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 22:14:08.296065 Check phy result
571 22:14:08.296481 INFO : End of initialization
572 22:14:08.319604 INFO : End of 2D read delay Voltage center optimization
573 22:14:08.338372 INFO : End of 2D read delay Voltage center optimization
574 22:14:08.390672 INFO : End of 2D write delay Voltage center optimization
575 22:14:08.439608 INFO : End of 2D write delay Voltage center optimization
576 22:14:08.445090 INFO : Training has run successfully!
577 22:14:08.445412
578 22:14:08.445639 channel==0
579 22:14:08.450720 RxClkDly_Margin_A0==88 ps 9
580 22:14:08.451032 TxDqDly_Margin_A0==98 ps 10
581 22:14:08.456281 RxClkDly_Margin_A1==88 ps 9
582 22:14:08.456571 TxDqDly_Margin_A1==98 ps 10
583 22:14:08.456790 TrainedVREFDQ_A0==74
584 22:14:08.461829 TrainedVREFDQ_A1==74
585 22:14:08.462094 VrefDac_Margin_A0==25
586 22:14:08.462309 DeviceVref_Margin_A0==40
587 22:14:08.467428 VrefDac_Margin_A1==25
588 22:14:08.467677 DeviceVref_Margin_A1==40
589 22:14:08.467886
590 22:14:08.468117
591 22:14:08.473034 channel==1
592 22:14:08.473284 RxClkDly_Margin_A0==98 ps 10
593 22:14:08.473493 TxDqDly_Margin_A0==98 ps 10
594 22:14:08.478620 RxClkDly_Margin_A1==98 ps 10
595 22:14:08.478869 TxDqDly_Margin_A1==98 ps 10
596 22:14:08.484341 TrainedVREFDQ_A0==77
597 22:14:08.484802 TrainedVREFDQ_A1==77
598 22:14:08.485214 VrefDac_Margin_A0==22
599 22:14:08.489960 DeviceVref_Margin_A0==37
600 22:14:08.490417 VrefDac_Margin_A1==22
601 22:14:08.495608 DeviceVref_Margin_A1==37
602 22:14:08.496144
603 22:14:08.496603 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 22:14:08.501194
605 22:14:08.529161 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
606 22:14:08.529706 2D training succeed
607 22:14:08.534810 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 22:14:08.540415 auto size-- 65535DDR cs0 size: 2048MB
609 22:14:08.540918 DDR cs1 size: 2048MB
610 22:14:08.545999 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 22:14:08.546501 cs0 DataBus test pass
612 22:14:08.551598 cs1 DataBus test pass
613 22:14:08.552154 cs0 AddrBus test pass
614 22:14:08.552620 cs1 AddrBus test pass
615 22:14:08.553062
616 22:14:08.557205 100bdlr_step_size ps== 420
617 22:14:08.557721 result report
618 22:14:08.562818 boot times 0Enable ddr reg access
619 22:14:08.568332 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 22:14:08.581774 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 22:14:09.155412 0.0;M3 CHK:0;cm4_sp_mode 0
622 22:14:09.156075 MVN_1=0x00000000
623 22:14:09.160920 MVN_2=0x00000000
624 22:14:09.166663 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 22:14:09.167183 OPS=0x10
626 22:14:09.167636 ring efuse init
627 22:14:09.168149 chipver efuse init
628 22:14:09.172274 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 22:14:09.177849 [0.018961 Inits done]
630 22:14:09.178341 secure task start!
631 22:14:09.178770 high task start!
632 22:14:09.182466 low task start!
633 22:14:09.182952 run into bl31
634 22:14:09.189038 NOTICE: BL31: v1.3(release):4fc40b1
635 22:14:09.195888 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 22:14:09.196412 NOTICE: BL31: G12A normal boot!
637 22:14:09.222263 NOTICE: BL31: BL33 decompress pass
638 22:14:09.227928 ERROR: Error initializing runtime service opteed_fast
639 22:14:10.460868
640 22:14:10.461444
641 22:14:10.469341 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 22:14:10.469854
643 22:14:10.470309 Model: Libre Computer AML-A311D-CC Alta
644 22:14:10.677668 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 22:14:10.701131 DRAM: 2 GiB (effective 3.8 GiB)
646 22:14:10.844074 Core: 408 devices, 31 uclasses, devicetree: separate
647 22:14:10.850090 WDT: Not starting watchdog@f0d0
648 22:14:10.882183 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 22:14:10.894881 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 22:14:10.899646 ** Bad device specification mmc 0 **
651 22:14:10.910031 Card did not respond to voltage select! : -110
652 22:14:10.917681 ** Bad device specification mmc 0 **
653 22:14:10.918203 Couldn't find partition mmc 0
654 22:14:10.926078 Card did not respond to voltage select! : -110
655 22:14:10.931483 ** Bad device specification mmc 0 **
656 22:14:10.932024 Couldn't find partition mmc 0
657 22:14:10.936660 Error: could not access storage.
658 22:14:11.279142 Net: eth0: ethernet@ff3f0000
659 22:14:11.279725 starting USB...
660 22:14:11.530996 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 22:14:11.531594 Starting the controller
662 22:14:11.537946 USB XHCI 1.10
663 22:14:13.247965 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
664 22:14:13.248691 bl2_stage_init 0x01
665 22:14:13.249155 bl2_stage_init 0x81
666 22:14:13.253519 hw id: 0x0000 - pwm id 0x01
667 22:14:13.254040 bl2_stage_init 0xc1
668 22:14:13.254502 bl2_stage_init 0x02
669 22:14:13.254949
670 22:14:13.259137 L0:00000000
671 22:14:13.259646 L1:20000703
672 22:14:13.260138 L2:00008067
673 22:14:13.260665 L3:14000000
674 22:14:13.262020 B2:00402000
675 22:14:13.262528 B1:e0f83180
676 22:14:13.262985
677 22:14:13.263433 TE: 58124
678 22:14:13.263879
679 22:14:13.273244 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 22:14:13.273792
681 22:14:13.274250 Board ID = 1
682 22:14:13.274695 Set A53 clk to 24M
683 22:14:13.275133 Set A73 clk to 24M
684 22:14:13.278797 Set clk81 to 24M
685 22:14:13.279313 A53 clk: 1200 MHz
686 22:14:13.279761 A73 clk: 1200 MHz
687 22:14:13.284318 CLK81: 166.6M
688 22:14:13.284837 smccc: 00012a91
689 22:14:13.290003 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 22:14:13.290514 board id: 1
691 22:14:13.298576 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 22:14:13.309304 fw parse done
693 22:14:13.315305 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 22:14:13.357650 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 22:14:13.368599 PIEI prepare done
696 22:14:13.369167 fastboot data load
697 22:14:13.369629 fastboot data verify
698 22:14:13.374304 verify result: 266
699 22:14:13.379886 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 22:14:13.380486 LPDDR4 probe
701 22:14:13.380964 ddr clk to 1584MHz
702 22:14:13.387784 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 22:14:13.425131
704 22:14:13.425741 dmc_version 0001
705 22:14:13.432326 Check phy result
706 22:14:13.437587 INFO : End of CA training
707 22:14:13.437966 INFO : End of initialization
708 22:14:13.443340 INFO : Training has run successfully!
709 22:14:13.443913 Check phy result
710 22:14:13.448880 INFO : End of initialization
711 22:14:13.449435 INFO : End of read enable training
712 22:14:13.454861 INFO : End of fine write leveling
713 22:14:13.460075 INFO : End of Write leveling coarse delay
714 22:14:13.460651 INFO : Training has run successfully!
715 22:14:13.461140 Check phy result
716 22:14:13.465734 INFO : End of initialization
717 22:14:13.466361 INFO : End of read dq deskew training
718 22:14:13.471263 INFO : End of MPR read delay center optimization
719 22:14:13.476914 INFO : End of write delay center optimization
720 22:14:13.483228 INFO : End of read delay center optimization
721 22:14:13.484347 INFO : End of max read latency training
722 22:14:13.488210 INFO : Training has run successfully!
723 22:14:13.488547 1D training succeed
724 22:14:13.497221 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 22:14:13.544972 Check phy result
726 22:14:13.545599 INFO : End of initialization
727 22:14:13.567891 INFO : End of 2D read delay Voltage center optimization
728 22:14:13.587281 INFO : End of 2D read delay Voltage center optimization
729 22:14:13.638859 INFO : End of 2D write delay Voltage center optimization
730 22:14:13.688219 INFO : End of 2D write delay Voltage center optimization
731 22:14:13.693736 INFO : Training has run successfully!
732 22:14:13.694271
733 22:14:13.694746 channel==0
734 22:14:13.699332 RxClkDly_Margin_A0==88 ps 9
735 22:14:13.699864 TxDqDly_Margin_A0==98 ps 10
736 22:14:13.704938 RxClkDly_Margin_A1==88 ps 9
737 22:14:13.705468 TxDqDly_Margin_A1==98 ps 10
738 22:14:13.705932 TrainedVREFDQ_A0==74
739 22:14:13.710515 TrainedVREFDQ_A1==74
740 22:14:13.711044 VrefDac_Margin_A0==25
741 22:14:13.711506 DeviceVref_Margin_A0==40
742 22:14:13.716137 VrefDac_Margin_A1==24
743 22:14:13.716662 DeviceVref_Margin_A1==40
744 22:14:13.717122
745 22:14:13.717577
746 22:14:13.721714 channel==1
747 22:14:13.722242 RxClkDly_Margin_A0==98 ps 10
748 22:14:13.722697 TxDqDly_Margin_A0==98 ps 10
749 22:14:13.727316 RxClkDly_Margin_A1==98 ps 10
750 22:14:13.727856 TxDqDly_Margin_A1==88 ps 9
751 22:14:13.732920 TrainedVREFDQ_A0==77
752 22:14:13.733455 TrainedVREFDQ_A1==77
753 22:14:13.733913 VrefDac_Margin_A0==22
754 22:14:13.738521 DeviceVref_Margin_A0==37
755 22:14:13.739039 VrefDac_Margin_A1==22
756 22:14:13.744134 DeviceVref_Margin_A1==37
757 22:14:13.744664
758 22:14:13.745121 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 22:14:13.749711
760 22:14:13.777696 soc_vref_reg_value 0x 00000019 00000019 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
761 22:14:13.778281 2D training succeed
762 22:14:13.783344 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 22:14:13.788919 auto size-- 65535DDR cs0 size: 2048MB
764 22:14:13.789450 DDR cs1 size: 2048MB
765 22:14:13.794539 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 22:14:13.795062 cs0 DataBus test pass
767 22:14:13.800158 cs1 DataBus test pass
768 22:14:13.800681 cs0 AddrBus test pass
769 22:14:13.801141 cs1 AddrBus test pass
770 22:14:13.801587
771 22:14:13.805744 100bdlr_step_size ps== 420
772 22:14:13.806279 result report
773 22:14:13.811354 boot times 0Enable ddr reg access
774 22:14:13.816760 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 22:14:13.830298 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 22:14:14.403905 0.0;M3 CHK:0;cm4_sp_mode 0
777 22:14:14.404551 MVN_1=0x00000000
778 22:14:14.409348 MVN_2=0x00000000
779 22:14:14.415150 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 22:14:14.415710 OPS=0x10
781 22:14:14.416199 ring efuse init
782 22:14:14.416637 chipver efuse init
783 22:14:14.420656 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 22:14:14.426256 [0.018961 Inits done]
785 22:14:14.426739 secure task start!
786 22:14:14.427168 high task start!
787 22:14:14.430860 low task start!
788 22:14:14.431345 run into bl31
789 22:14:14.437505 NOTICE: BL31: v1.3(release):4fc40b1
790 22:14:14.445324 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 22:14:14.445831 NOTICE: BL31: G12A normal boot!
792 22:14:14.470689 NOTICE: BL31: BL33 decompress pass
793 22:14:14.476373 ERROR: Error initializing runtime service opteed_fast
794 22:14:15.709346
795 22:14:15.710007
796 22:14:15.717652 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 22:14:15.718161
798 22:14:15.718604 Model: Libre Computer AML-A311D-CC Alta
799 22:14:15.926156 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 22:14:15.949570 DRAM: 2 GiB (effective 3.8 GiB)
801 22:14:16.092493 Core: 408 devices, 31 uclasses, devicetree: separate
802 22:14:16.098317 WDT: Not starting watchdog@f0d0
803 22:14:16.130542 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 22:14:16.143041 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 22:14:16.148055 ** Bad device specification mmc 0 **
806 22:14:16.158455 Card did not respond to voltage select! : -110
807 22:14:16.165969 ** Bad device specification mmc 0 **
808 22:14:16.166450 Couldn't find partition mmc 0
809 22:14:16.174321 Card did not respond to voltage select! : -110
810 22:14:16.179815 ** Bad device specification mmc 0 **
811 22:14:16.180331 Couldn't find partition mmc 0
812 22:14:16.184910 Error: could not access storage.
813 22:14:16.527371 Net: eth0: ethernet@ff3f0000
814 22:14:16.528029 starting USB...
815 22:14:16.779216 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 22:14:16.779760 Starting the controller
817 22:14:16.786164 USB XHCI 1.10
818 22:14:18.948837 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 22:14:18.949475 bl2_stage_init 0x01
820 22:14:18.949939 bl2_stage_init 0x81
821 22:14:18.954460 hw id: 0x0000 - pwm id 0x01
822 22:14:18.954950 bl2_stage_init 0xc1
823 22:14:18.955399 bl2_stage_init 0x02
824 22:14:18.955843
825 22:14:18.960048 L0:00000000
826 22:14:18.960532 L1:20000703
827 22:14:18.960973 L2:00008067
828 22:14:18.961411 L3:14000000
829 22:14:18.963082 B2:00402000
830 22:14:18.963561 B1:e0f83180
831 22:14:18.964037
832 22:14:18.964486 TE: 58167
833 22:14:18.964929
834 22:14:18.974140 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 22:14:18.974626
836 22:14:18.975073 Board ID = 1
837 22:14:18.975510 Set A53 clk to 24M
838 22:14:18.975948 Set A73 clk to 24M
839 22:14:18.979787 Set clk81 to 24M
840 22:14:18.980299 A53 clk: 1200 MHz
841 22:14:18.980746 A73 clk: 1200 MHz
842 22:14:18.985387 CLK81: 166.6M
843 22:14:18.985872 smccc: 00012abe
844 22:14:18.990921 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 22:14:18.991403 board id: 1
846 22:14:18.999479 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 22:14:19.010117 fw parse done
848 22:14:19.016110 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 22:14:19.058746 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 22:14:19.069635 PIEI prepare done
851 22:14:19.070113 fastboot data load
852 22:14:19.070561 fastboot data verify
853 22:14:19.075286 verify result: 266
854 22:14:19.080896 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 22:14:19.081394 LPDDR4 probe
856 22:14:19.081847 ddr clk to 1584MHz
857 22:14:19.088841 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 22:14:19.126132
859 22:14:19.126632 dmc_version 0001
860 22:14:19.132803 Check phy result
861 22:14:19.138664 INFO : End of CA training
862 22:14:19.139156 INFO : End of initialization
863 22:14:19.144320 INFO : Training has run successfully!
864 22:14:19.144811 Check phy result
865 22:14:19.149902 INFO : End of initialization
866 22:14:19.150397 INFO : End of read enable training
867 22:14:19.155483 INFO : End of fine write leveling
868 22:14:19.161144 INFO : End of Write leveling coarse delay
869 22:14:19.161640 INFO : Training has run successfully!
870 22:14:19.162092 Check phy result
871 22:14:19.166739 INFO : End of initialization
872 22:14:19.167236 INFO : End of read dq deskew training
873 22:14:19.172286 INFO : End of MPR read delay center optimization
874 22:14:19.177909 INFO : End of write delay center optimization
875 22:14:19.183492 INFO : End of read delay center optimization
876 22:14:19.184024 INFO : End of max read latency training
877 22:14:19.189121 INFO : Training has run successfully!
878 22:14:19.189617 1D training succeed
879 22:14:19.198245 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 22:14:19.245879 Check phy result
881 22:14:19.246376 INFO : End of initialization
882 22:14:19.267512 INFO : End of 2D read delay Voltage center optimization
883 22:14:19.286790 INFO : End of 2D read delay Voltage center optimization
884 22:14:19.338716 INFO : End of 2D write delay Voltage center optimization
885 22:14:19.387954 INFO : End of 2D write delay Voltage center optimization
886 22:14:19.393596 INFO : Training has run successfully!
887 22:14:19.394078
888 22:14:19.394529 channel==0
889 22:14:19.399106 RxClkDly_Margin_A0==88 ps 9
890 22:14:19.399575 TxDqDly_Margin_A0==98 ps 10
891 22:14:19.404601 RxClkDly_Margin_A1==88 ps 9
892 22:14:19.405070 TxDqDly_Margin_A1==98 ps 10
893 22:14:19.405536 TrainedVREFDQ_A0==74
894 22:14:19.410285 TrainedVREFDQ_A1==74
895 22:14:19.410793 VrefDac_Margin_A0==25
896 22:14:19.411240 DeviceVref_Margin_A0==40
897 22:14:19.415914 VrefDac_Margin_A1==25
898 22:14:19.416444 DeviceVref_Margin_A1==40
899 22:14:19.416876
900 22:14:19.417300
901 22:14:19.421462 channel==1
902 22:14:19.421922 RxClkDly_Margin_A0==98 ps 10
903 22:14:19.422348 TxDqDly_Margin_A0==98 ps 10
904 22:14:19.427094 RxClkDly_Margin_A1==88 ps 9
905 22:14:19.427549 TxDqDly_Margin_A1==88 ps 9
906 22:14:19.432668 TrainedVREFDQ_A0==77
907 22:14:19.433147 TrainedVREFDQ_A1==77
908 22:14:19.433580 VrefDac_Margin_A0==23
909 22:14:19.438279 DeviceVref_Margin_A0==37
910 22:14:19.438734 VrefDac_Margin_A1==24
911 22:14:19.443869 DeviceVref_Margin_A1==37
912 22:14:19.444368
913 22:14:19.444801 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 22:14:19.445225
915 22:14:19.477482 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000018 00000018 00000019 00000019 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
916 22:14:19.477975 2D training succeed
917 22:14:19.482970 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 22:14:19.488531 auto size-- 65535DDR cs0 size: 2048MB
919 22:14:19.488986 DDR cs1 size: 2048MB
920 22:14:19.494125 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 22:14:19.494580 cs0 DataBus test pass
922 22:14:19.499729 cs1 DataBus test pass
923 22:14:19.500221 cs0 AddrBus test pass
924 22:14:19.500647 cs1 AddrBus test pass
925 22:14:19.501071
926 22:14:19.505321 100bdlr_step_size ps== 420
927 22:14:19.505792 result report
928 22:14:19.510937 boot times 0Enable ddr reg access
929 22:14:19.516274 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 22:14:19.529735 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 22:14:20.101738 0.0;M3 CHK:0;cm4_sp_mode 0
932 22:14:20.102293 MVN_1=0x00000000
933 22:14:20.107215 MVN_2=0x00000000
934 22:14:20.112997 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 22:14:20.113478 OPS=0x10
936 22:14:20.113927 ring efuse init
937 22:14:20.114360 chipver efuse init
938 22:14:20.118575 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 22:14:20.124178 [0.018961 Inits done]
940 22:14:20.124643 secure task start!
941 22:14:20.125085 high task start!
942 22:14:20.128744 low task start!
943 22:14:20.129210 run into bl31
944 22:14:20.135394 NOTICE: BL31: v1.3(release):4fc40b1
945 22:14:20.143204 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 22:14:20.143684 NOTICE: BL31: G12A normal boot!
947 22:14:20.169119 NOTICE: BL31: BL33 decompress pass
948 22:14:20.174776 ERROR: Error initializing runtime service opteed_fast
949 22:14:21.407792
950 22:14:21.408452
951 22:14:21.416143 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 22:14:21.416627
953 22:14:21.417079 Model: Libre Computer AML-A311D-CC Alta
954 22:14:21.624520 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 22:14:21.647919 DRAM: 2 GiB (effective 3.8 GiB)
956 22:14:21.790927 Core: 408 devices, 31 uclasses, devicetree: separate
957 22:14:21.796782 WDT: Not starting watchdog@f0d0
958 22:14:21.829109 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 22:14:21.841515 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 22:14:21.846475 ** Bad device specification mmc 0 **
961 22:14:21.856837 Card did not respond to voltage select! : -110
962 22:14:21.864521 ** Bad device specification mmc 0 **
963 22:14:21.865008 Couldn't find partition mmc 0
964 22:14:21.872817 Card did not respond to voltage select! : -110
965 22:14:21.878336 ** Bad device specification mmc 0 **
966 22:14:21.878803 Couldn't find partition mmc 0
967 22:14:21.883367 Error: could not access storage.
968 22:14:22.226904 Net: eth0: ethernet@ff3f0000
969 22:14:22.227396 starting USB...
970 22:14:22.478716 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 22:14:22.479200 Starting the controller
972 22:14:22.485689 USB XHCI 1.10
973 22:14:24.347656 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
974 22:14:24.348236 bl2_stage_init 0x01
975 22:14:24.348697 bl2_stage_init 0x81
976 22:14:24.353247 hw id: 0x0000 - pwm id 0x01
977 22:14:24.353733 bl2_stage_init 0xc1
978 22:14:24.354181 bl2_stage_init 0x02
979 22:14:24.354619
980 22:14:24.358829 L0:00000000
981 22:14:24.359294 L1:20000703
982 22:14:24.359734 L2:00008067
983 22:14:24.360214 L3:14000000
984 22:14:24.364449 B2:00402000
985 22:14:24.364920 B1:e0f83180
986 22:14:24.365360
987 22:14:24.365803 TE: 58159
988 22:14:24.366239
989 22:14:24.370020 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 22:14:24.370494
991 22:14:24.370938 Board ID = 1
992 22:14:24.375654 Set A53 clk to 24M
993 22:14:24.376147 Set A73 clk to 24M
994 22:14:24.376592 Set clk81 to 24M
995 22:14:24.381241 A53 clk: 1200 MHz
996 22:14:24.381705 A73 clk: 1200 MHz
997 22:14:24.382146 CLK81: 166.6M
998 22:14:24.382582 smccc: 00012ab5
999 22:14:24.386904 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 22:14:24.392434 board id: 1
1001 22:14:24.398280 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 22:14:24.408960 fw parse done
1003 22:14:24.414942 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 22:14:24.456650 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 22:14:24.468459 PIEI prepare done
1006 22:14:24.468917 fastboot data load
1007 22:14:24.469346 fastboot data verify
1008 22:14:24.474170 verify result: 266
1009 22:14:24.479725 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 22:14:24.480234 LPDDR4 probe
1011 22:14:24.480665 ddr clk to 1584MHz
1012 22:14:24.487932 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 22:14:24.525203
1014 22:14:24.525664 dmc_version 0001
1015 22:14:24.531944 Check phy result
1016 22:14:24.537813 INFO : End of CA training
1017 22:14:24.538316 INFO : End of initialization
1018 22:14:24.543284 INFO : Training has run successfully!
1019 22:14:24.543756 Check phy result
1020 22:14:24.548884 INFO : End of initialization
1021 22:14:24.549355 INFO : End of read enable training
1022 22:14:24.554484 INFO : End of fine write leveling
1023 22:14:24.560193 INFO : End of Write leveling coarse delay
1024 22:14:24.560664 INFO : Training has run successfully!
1025 22:14:24.561109 Check phy result
1026 22:14:24.565703 INFO : End of initialization
1027 22:14:24.566171 INFO : End of read dq deskew training
1028 22:14:24.571215 INFO : End of MPR read delay center optimization
1029 22:14:24.576933 INFO : End of write delay center optimization
1030 22:14:24.582408 INFO : End of read delay center optimization
1031 22:14:24.582879 INFO : End of max read latency training
1032 22:14:24.587943 INFO : Training has run successfully!
1033 22:14:24.588455 1D training succeed
1034 22:14:24.597170 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 22:14:24.644831 Check phy result
1036 22:14:24.645296 INFO : End of initialization
1037 22:14:24.667329 INFO : End of 2D read delay Voltage center optimization
1038 22:14:24.687683 INFO : End of 2D read delay Voltage center optimization
1039 22:14:24.739761 INFO : End of 2D write delay Voltage center optimization
1040 22:14:24.789121 INFO : End of 2D write delay Voltage center optimization
1041 22:14:24.794689 INFO : Training has run successfully!
1042 22:14:24.795159
1043 22:14:24.795608 channel==0
1044 22:14:24.800230 RxClkDly_Margin_A0==88 ps 9
1045 22:14:24.800702 TxDqDly_Margin_A0==98 ps 10
1046 22:14:24.803647 RxClkDly_Margin_A1==88 ps 9
1047 22:14:24.804147 TxDqDly_Margin_A1==98 ps 10
1048 22:14:24.809177 TrainedVREFDQ_A0==74
1049 22:14:24.809645 TrainedVREFDQ_A1==74
1050 22:14:24.810089 VrefDac_Margin_A0==24
1051 22:14:24.814812 DeviceVref_Margin_A0==40
1052 22:14:24.815275 VrefDac_Margin_A1==24
1053 22:14:24.820377 DeviceVref_Margin_A1==40
1054 22:14:24.820846
1055 22:14:24.821288
1056 22:14:24.821723 channel==1
1057 22:14:24.822154 RxClkDly_Margin_A0==98 ps 10
1058 22:14:24.823877 TxDqDly_Margin_A0==88 ps 9
1059 22:14:24.829486 RxClkDly_Margin_A1==98 ps 10
1060 22:14:24.829955 TxDqDly_Margin_A1==88 ps 9
1061 22:14:24.830402 TrainedVREFDQ_A0==76
1062 22:14:24.835045 TrainedVREFDQ_A1==77
1063 22:14:24.835517 VrefDac_Margin_A0==22
1064 22:14:24.840751 DeviceVref_Margin_A0==38
1065 22:14:24.841217 VrefDac_Margin_A1==22
1066 22:14:24.841655 DeviceVref_Margin_A1==37
1067 22:14:24.842092
1068 22:14:24.846268 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 22:14:24.846736
1070 22:14:24.879847 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000017 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000018 dram_vref_reg_value 0x 00000060
1071 22:14:24.880375 2D training succeed
1072 22:14:24.885460 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 22:14:24.890927 auto size-- 65535DDR cs0 size: 2048MB
1074 22:14:24.891396 DDR cs1 size: 2048MB
1075 22:14:24.896561 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 22:14:24.897027 cs0 DataBus test pass
1077 22:14:24.897466 cs1 DataBus test pass
1078 22:14:24.902123 cs0 AddrBus test pass
1079 22:14:24.902595 cs1 AddrBus test pass
1080 22:14:24.903034
1081 22:14:24.907752 100bdlr_step_size ps== 420
1082 22:14:24.908272 result report
1083 22:14:24.908717 boot times 0Enable ddr reg access
1084 22:14:24.917454 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 22:14:24.931026 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 22:14:25.504572 0.0;M3 CHK:0;cm4_sp_mode 0
1087 22:14:25.505096 MVN_1=0x00000000
1088 22:14:25.510024 MVN_2=0x00000000
1089 22:14:25.515793 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 22:14:25.516324 OPS=0x10
1091 22:14:25.516774 ring efuse init
1092 22:14:25.517215 chipver efuse init
1093 22:14:25.521394 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 22:14:25.527000 [0.018961 Inits done]
1095 22:14:25.527470 secure task start!
1096 22:14:25.527914 high task start!
1097 22:14:25.531578 low task start!
1098 22:14:25.532073 run into bl31
1099 22:14:25.538258 NOTICE: BL31: v1.3(release):4fc40b1
1100 22:14:25.546065 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 22:14:25.546543 NOTICE: BL31: G12A normal boot!
1102 22:14:25.571418 NOTICE: BL31: BL33 decompress pass
1103 22:14:25.577107 ERROR: Error initializing runtime service opteed_fast
1104 22:14:26.810077
1105 22:14:26.810581
1106 22:14:26.818399 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 22:14:26.818877
1108 22:14:26.819322 Model: Libre Computer AML-A311D-CC Alta
1109 22:14:27.026819 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 22:14:27.050182 DRAM: 2 GiB (effective 3.8 GiB)
1111 22:14:27.193164 Core: 408 devices, 31 uclasses, devicetree: separate
1112 22:14:27.199074 WDT: Not starting watchdog@f0d0
1113 22:14:27.231296 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 22:14:27.243823 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 22:14:27.248736 ** Bad device specification mmc 0 **
1116 22:14:27.259090 Card did not respond to voltage select! : -110
1117 22:14:27.266716 ** Bad device specification mmc 0 **
1118 22:14:27.267187 Couldn't find partition mmc 0
1119 22:14:27.275079 Card did not respond to voltage select! : -110
1120 22:14:27.280578 ** Bad device specification mmc 0 **
1121 22:14:27.281047 Couldn't find partition mmc 0
1122 22:14:27.285645 Error: could not access storage.
1123 22:14:27.628220 Net: eth0: ethernet@ff3f0000
1124 22:14:27.628709 starting USB...
1125 22:14:27.879940 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 22:14:27.880460 Starting the controller
1127 22:14:27.886910 USB XHCI 1.10
1128 22:14:29.444190 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 22:14:29.452443 scanning usb for storage devices... 0 Storage Device(s) found
1131 22:14:29.504171 Hit any key to stop autoboot: 1
1132 22:14:29.504970 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1133 22:14:29.505584 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1134 22:14:29.506083 Setting prompt string to ['=>']
1135 22:14:29.506573 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1136 22:14:29.519873 0
1137 22:14:29.520794 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 22:14:29.521332 Sending with 10 millisecond of delay
1140 22:14:30.656033 => setenv autoload no
1141 22:14:30.666781 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1142 22:14:30.672193 setenv autoload no
1143 22:14:30.672967 Sending with 10 millisecond of delay
1145 22:14:32.469694 => setenv initrd_high 0xffffffff
1146 22:14:32.480419 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1147 22:14:32.481280 setenv initrd_high 0xffffffff
1148 22:14:32.482029 Sending with 10 millisecond of delay
1150 22:14:34.098197 => setenv fdt_high 0xffffffff
1151 22:14:34.108940 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1152 22:14:34.109780 setenv fdt_high 0xffffffff
1153 22:14:34.110529 Sending with 10 millisecond of delay
1155 22:14:34.402382 => dhcp
1156 22:14:34.413039 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1157 22:14:34.413860 dhcp
1158 22:14:34.414328 Speed: 1000, full duplex
1159 22:14:34.414780 BOOTP broadcast 1
1160 22:14:34.429817 DHCP client bound to address 192.168.6.27 (17 ms)
1161 22:14:34.430575 Sending with 10 millisecond of delay
1163 22:14:36.106997 => setenv serverip 192.168.6.2
1164 22:14:36.117716 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1165 22:14:36.118612 setenv serverip 192.168.6.2
1166 22:14:36.119343 Sending with 10 millisecond of delay
1168 22:14:39.842367 => tftpboot 0x01080000 918825/tftp-deploy-l50qmk55/kernel/uImage
1169 22:14:39.853085 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1170 22:14:39.853946 tftpboot 0x01080000 918825/tftp-deploy-l50qmk55/kernel/uImage
1171 22:14:39.854430 Speed: 1000, full duplex
1172 22:14:39.854885 Using ethernet@ff3f0000 device
1173 22:14:39.856108 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1174 22:14:39.861527 Filename '918825/tftp-deploy-l50qmk55/kernel/uImage'.
1175 22:14:39.865402 Load address: 0x1080000
1176 22:14:42.664277 Loading: *################################################## 43.6 MiB
1177 22:14:42.664929 15.6 MiB/s
1178 22:14:42.665404 done
1179 22:14:42.668603 Bytes transferred = 45713984 (2b98a40 hex)
1180 22:14:42.669452 Sending with 10 millisecond of delay
1182 22:14:47.355753 => tftpboot 0x08000000 918825/tftp-deploy-l50qmk55/ramdisk/ramdisk.cpio.gz.uboot
1183 22:14:47.366578 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1184 22:14:47.367460 tftpboot 0x08000000 918825/tftp-deploy-l50qmk55/ramdisk/ramdisk.cpio.gz.uboot
1185 22:14:47.367948 Speed: 1000, full duplex
1186 22:14:47.368453 Using ethernet@ff3f0000 device
1187 22:14:47.369645 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1188 22:14:47.381281 Filename '918825/tftp-deploy-l50qmk55/ramdisk/ramdisk.cpio.gz.uboot'.
1189 22:14:47.381812 Load address: 0x8000000
1190 22:14:54.306245 Loading: *####################T ############################# UDP wrong checksum 00000005 0000fffc
1191 22:14:59.306858 T UDP wrong checksum 00000005 0000fffc
1192 22:15:09.310048 T T UDP wrong checksum 00000005 0000fffc
1193 22:15:29.314160 T T T T UDP wrong checksum 00000005 0000fffc
1194 22:15:44.318251 T T
1195 22:15:44.318978 Retry count exceeded; starting again
1197 22:15:44.320640 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1200 22:15:44.321615 end: 2.4 uboot-commands (duration 00:01:52) [common]
1202 22:15:44.322352 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1204 22:15:44.322917 end: 2 uboot-action (duration 00:01:52) [common]
1206 22:15:44.323746 Cleaning after the job
1207 22:15:44.324144 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/ramdisk
1208 22:15:44.325055 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/kernel
1209 22:15:44.349186 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/dtb
1210 22:15:44.349992 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/nfsrootfs
1211 22:15:44.512497 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/918825/tftp-deploy-l50qmk55/modules
1212 22:15:44.531838 start: 4.1 power-off (timeout 00:00:30) [common]
1213 22:15:44.532647 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1214 22:15:44.568298 >> OK - accepted request
1215 22:15:44.570329 Returned 0 in 0 seconds
1216 22:15:44.671092 end: 4.1 power-off (duration 00:00:00) [common]
1218 22:15:44.672075 start: 4.2 read-feedback (timeout 00:10:00) [common]
1219 22:15:44.672773 Listened to connection for namespace 'common' for up to 1s
1220 22:15:45.673717 Finalising connection for namespace 'common'
1221 22:15:45.674224 Disconnecting from shell: Finalise
1222 22:15:45.674521 =>
1223 22:15:45.775116 end: 4.2 read-feedback (duration 00:00:01) [common]
1224 22:15:45.775460 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/918825
1225 22:15:48.833957 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/918825
1226 22:15:48.834680 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.