Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 14:58:37.552814 lava-dispatcher, installed at version: 2024.01
2 14:58:37.553666 start: 0 validate
3 14:58:37.554155 Start time: 2024-11-05 14:58:37.554125+00:00 (UTC)
4 14:58:37.554733 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 14:58:37.555272 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 14:58:37.601879 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 14:58:37.602473 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-60-ge38568da5f05b%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 14:58:37.634019 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 14:58:37.634735 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-60-ge38568da5f05b%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 14:58:37.669549 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 14:58:37.670103 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-60-ge38568da5f05b%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 14:58:37.712519 validate duration: 0.16
14 14:58:37.713354 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 14:58:37.713665 start: 1.1 download-retry (timeout 00:10:00) [common]
16 14:58:37.713967 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 14:58:37.714520 Not decompressing ramdisk as can be used compressed.
18 14:58:37.714933 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 14:58:37.715190 saving as /var/lib/lava/dispatcher/tmp/940320/tftp-deploy-ss1q1dte/ramdisk/rootfs.cpio.gz
20 14:58:37.715453 total size: 47897469 (45 MB)
21 14:58:37.755679 progress 0 % (0 MB)
22 14:58:37.786809 progress 5 % (2 MB)
23 14:58:37.817200 progress 10 % (4 MB)
24 14:58:37.847284 progress 15 % (6 MB)
25 14:58:37.877470 progress 20 % (9 MB)
26 14:58:37.907204 progress 25 % (11 MB)
27 14:58:37.937071 progress 30 % (13 MB)
28 14:58:37.967558 progress 35 % (16 MB)
29 14:58:37.997554 progress 40 % (18 MB)
30 14:58:38.027268 progress 45 % (20 MB)
31 14:58:38.057176 progress 50 % (22 MB)
32 14:58:38.087593 progress 55 % (25 MB)
33 14:58:38.118072 progress 60 % (27 MB)
34 14:58:38.147922 progress 65 % (29 MB)
35 14:58:38.178380 progress 70 % (32 MB)
36 14:58:38.208703 progress 75 % (34 MB)
37 14:58:38.238803 progress 80 % (36 MB)
38 14:58:38.269081 progress 85 % (38 MB)
39 14:58:38.299464 progress 90 % (41 MB)
40 14:58:38.329187 progress 95 % (43 MB)
41 14:58:38.358243 progress 100 % (45 MB)
42 14:58:38.359005 45 MB downloaded in 0.64 s (70.98 MB/s)
43 14:58:38.359568 end: 1.1.1 http-download (duration 00:00:01) [common]
45 14:58:38.360481 end: 1.1 download-retry (duration 00:00:01) [common]
46 14:58:38.360778 start: 1.2 download-retry (timeout 00:09:59) [common]
47 14:58:38.361050 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 14:58:38.361514 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-60-ge38568da5f05b/arm64/defconfig/gcc-12/kernel/Image
49 14:58:38.361757 saving as /var/lib/lava/dispatcher/tmp/940320/tftp-deploy-ss1q1dte/kernel/Image
50 14:58:38.361964 total size: 45713920 (43 MB)
51 14:58:38.362176 No compression specified
52 14:58:38.402118 progress 0 % (0 MB)
53 14:58:38.429905 progress 5 % (2 MB)
54 14:58:38.457759 progress 10 % (4 MB)
55 14:58:38.485486 progress 15 % (6 MB)
56 14:58:38.512919 progress 20 % (8 MB)
57 14:58:38.540187 progress 25 % (10 MB)
58 14:58:38.567644 progress 30 % (13 MB)
59 14:58:38.596293 progress 35 % (15 MB)
60 14:58:38.624296 progress 40 % (17 MB)
61 14:58:38.651746 progress 45 % (19 MB)
62 14:58:38.679607 progress 50 % (21 MB)
63 14:58:38.707721 progress 55 % (24 MB)
64 14:58:38.735592 progress 60 % (26 MB)
65 14:58:38.763085 progress 65 % (28 MB)
66 14:58:38.790895 progress 70 % (30 MB)
67 14:58:38.819083 progress 75 % (32 MB)
68 14:58:38.846839 progress 80 % (34 MB)
69 14:58:38.874196 progress 85 % (37 MB)
70 14:58:38.902302 progress 90 % (39 MB)
71 14:58:38.929767 progress 95 % (41 MB)
72 14:58:38.956606 progress 100 % (43 MB)
73 14:58:38.957111 43 MB downloaded in 0.60 s (73.25 MB/s)
74 14:58:38.957585 end: 1.2.1 http-download (duration 00:00:01) [common]
76 14:58:38.958401 end: 1.2 download-retry (duration 00:00:01) [common]
77 14:58:38.958676 start: 1.3 download-retry (timeout 00:09:59) [common]
78 14:58:38.958940 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 14:58:38.959400 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-60-ge38568da5f05b/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 14:58:38.959672 saving as /var/lib/lava/dispatcher/tmp/940320/tftp-deploy-ss1q1dte/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 14:58:38.959882 total size: 53209 (0 MB)
82 14:58:38.960115 No compression specified
83 14:58:39.003422 progress 61 % (0 MB)
84 14:58:39.004293 progress 100 % (0 MB)
85 14:58:39.004819 0 MB downloaded in 0.04 s (1.13 MB/s)
86 14:58:39.005270 end: 1.3.1 http-download (duration 00:00:00) [common]
88 14:58:39.006072 end: 1.3 download-retry (duration 00:00:00) [common]
89 14:58:39.006331 start: 1.4 download-retry (timeout 00:09:59) [common]
90 14:58:39.006594 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 14:58:39.007036 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-60-ge38568da5f05b/arm64/defconfig/gcc-12/modules.tar.xz
92 14:58:39.007272 saving as /var/lib/lava/dispatcher/tmp/940320/tftp-deploy-ss1q1dte/modules/modules.tar
93 14:58:39.007477 total size: 11603148 (11 MB)
94 14:58:39.007687 Using unxz to decompress xz
95 14:58:39.045969 progress 0 % (0 MB)
96 14:58:39.112065 progress 5 % (0 MB)
97 14:58:39.186248 progress 10 % (1 MB)
98 14:58:39.282922 progress 15 % (1 MB)
99 14:58:39.376326 progress 20 % (2 MB)
100 14:58:39.456582 progress 25 % (2 MB)
101 14:58:39.532479 progress 30 % (3 MB)
102 14:58:39.607144 progress 35 % (3 MB)
103 14:58:39.684459 progress 40 % (4 MB)
104 14:58:39.761657 progress 45 % (5 MB)
105 14:58:39.849093 progress 50 % (5 MB)
106 14:58:39.927114 progress 55 % (6 MB)
107 14:58:40.013174 progress 60 % (6 MB)
108 14:58:40.094021 progress 65 % (7 MB)
109 14:58:40.170941 progress 70 % (7 MB)
110 14:58:40.253818 progress 75 % (8 MB)
111 14:58:40.337948 progress 80 % (8 MB)
112 14:58:40.414595 progress 85 % (9 MB)
113 14:58:40.497370 progress 90 % (9 MB)
114 14:58:40.575180 progress 95 % (10 MB)
115 14:58:40.652507 progress 100 % (11 MB)
116 14:58:40.662944 11 MB downloaded in 1.66 s (6.68 MB/s)
117 14:58:40.663540 end: 1.4.1 http-download (duration 00:00:02) [common]
119 14:58:40.664767 end: 1.4 download-retry (duration 00:00:02) [common]
120 14:58:40.665298 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 14:58:40.665819 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 14:58:40.666306 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 14:58:40.666806 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 14:58:40.667775 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2
125 14:58:40.668698 makedir: /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin
126 14:58:40.669339 makedir: /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/tests
127 14:58:40.669949 makedir: /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/results
128 14:58:40.670548 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-add-keys
129 14:58:40.671455 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-add-sources
130 14:58:40.672407 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-background-process-start
131 14:58:40.673350 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-background-process-stop
132 14:58:40.674330 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-common-functions
133 14:58:40.675235 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-echo-ipv4
134 14:58:40.676178 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-install-packages
135 14:58:40.677107 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-installed-packages
136 14:58:40.678001 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-os-build
137 14:58:40.678881 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-probe-channel
138 14:58:40.679763 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-probe-ip
139 14:58:40.680702 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-target-ip
140 14:58:40.681592 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-target-mac
141 14:58:40.682470 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-target-storage
142 14:58:40.683358 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-test-case
143 14:58:40.684295 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-test-event
144 14:58:40.685189 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-test-feedback
145 14:58:40.686074 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-test-raise
146 14:58:40.686958 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-test-reference
147 14:58:40.687949 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-test-runner
148 14:58:40.688899 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-test-set
149 14:58:40.689784 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-test-shell
150 14:58:40.690710 Updating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-install-packages (oe)
151 14:58:40.691657 Updating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/bin/lava-installed-packages (oe)
152 14:58:40.692525 Creating /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/environment
153 14:58:40.693239 LAVA metadata
154 14:58:40.693717 - LAVA_JOB_ID=940320
155 14:58:40.694141 - LAVA_DISPATCHER_IP=192.168.6.2
156 14:58:40.694806 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 14:58:40.696657 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 14:58:40.697246 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 14:58:40.697653 skipped lava-vland-overlay
160 14:58:40.698141 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 14:58:40.698642 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 14:58:40.699065 skipped lava-multinode-overlay
163 14:58:40.699543 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 14:58:40.700073 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 14:58:40.700570 Loading test definitions
166 14:58:40.701116 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 14:58:40.701554 Using /lava-940320 at stage 0
168 14:58:40.703677 uuid=940320_1.5.2.4.1 testdef=None
169 14:58:40.704192 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 14:58:40.704475 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 14:58:40.706265 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 14:58:40.707081 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 14:58:40.709305 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 14:58:40.710144 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 14:58:40.712289 runner path: /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/0/tests/0_igt-gpu-panfrost test_uuid 940320_1.5.2.4.1
178 14:58:40.712885 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 14:58:40.713696 Creating lava-test-runner.conf files
181 14:58:40.713903 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/940320/lava-overlay-fk18h2s2/lava-940320/0 for stage 0
182 14:58:40.714246 - 0_igt-gpu-panfrost
183 14:58:40.714592 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 14:58:40.714875 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 14:58:40.738648 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 14:58:40.739049 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 14:58:40.739314 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 14:58:40.739583 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 14:58:40.739849 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 14:58:48.035846 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 14:58:48.036898 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 14:58:48.037395 extracting modules file /var/lib/lava/dispatcher/tmp/940320/tftp-deploy-ss1q1dte/modules/modules.tar to /var/lib/lava/dispatcher/tmp/940320/extract-overlay-ramdisk-zniiw87l/ramdisk
193 14:58:49.471228 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 14:58:49.471709 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 14:58:49.472013 [common] Applying overlay /var/lib/lava/dispatcher/tmp/940320/compress-overlay-7av6ort9/overlay-1.5.2.5.tar.gz to ramdisk
196 14:58:49.472233 [common] Applying overlay /var/lib/lava/dispatcher/tmp/940320/compress-overlay-7av6ort9/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/940320/extract-overlay-ramdisk-zniiw87l/ramdisk
197 14:58:49.502855 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 14:58:49.503282 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 14:58:49.503557 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 14:58:49.503787 Converting downloaded kernel to a uImage
201 14:58:49.504112 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/940320/tftp-deploy-ss1q1dte/kernel/Image /var/lib/lava/dispatcher/tmp/940320/tftp-deploy-ss1q1dte/kernel/uImage
202 14:58:49.966880 output: Image Name:
203 14:58:49.967281 output: Created: Tue Nov 5 14:58:49 2024
204 14:58:49.967492 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 14:58:49.967698 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 14:58:49.967898 output: Load Address: 01080000
207 14:58:49.968141 output: Entry Point: 01080000
208 14:58:49.968345 output:
209 14:58:49.968671 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 14:58:49.968937 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 14:58:49.969205 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 14:58:49.969458 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 14:58:49.969714 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 14:58:49.969980 Building ramdisk /var/lib/lava/dispatcher/tmp/940320/extract-overlay-ramdisk-zniiw87l/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/940320/extract-overlay-ramdisk-zniiw87l/ramdisk
215 14:58:56.509412 >> 502362 blocks
216 14:59:17.298508 Adding RAMdisk u-boot header.
217 14:59:17.298961 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/940320/extract-overlay-ramdisk-zniiw87l/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/940320/extract-overlay-ramdisk-zniiw87l/ramdisk.cpio.gz.uboot
218 14:59:17.968321 output: Image Name:
219 14:59:17.968753 output: Created: Tue Nov 5 14:59:17 2024
220 14:59:17.968981 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 14:59:17.969198 output: Data Size: 65705573 Bytes = 64165.60 KiB = 62.66 MiB
222 14:59:17.969407 output: Load Address: 00000000
223 14:59:17.969614 output: Entry Point: 00000000
224 14:59:17.969821 output:
225 14:59:17.970513 rename /var/lib/lava/dispatcher/tmp/940320/extract-overlay-ramdisk-zniiw87l/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/940320/tftp-deploy-ss1q1dte/ramdisk/ramdisk.cpio.gz.uboot
226 14:59:17.970952 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 14:59:17.971256 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 14:59:17.971581 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 14:59:17.971837 No LXC device requested
230 14:59:17.972147 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 14:59:17.972434 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 14:59:17.972701 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 14:59:17.972921 Checking files for TFTP limit of 4294967296 bytes.
234 14:59:17.974406 end: 1 tftp-deploy (duration 00:00:40) [common]
235 14:59:17.974733 start: 2 uboot-action (timeout 00:05:00) [common]
236 14:59:17.975018 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 14:59:17.975287 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 14:59:17.975560 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 14:59:17.975859 Using kernel file from prepare-kernel: 940320/tftp-deploy-ss1q1dte/kernel/uImage
240 14:59:17.976219 substitutions:
241 14:59:17.976444 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 14:59:17.976658 - {DTB_ADDR}: 0x01070000
243 14:59:17.976865 - {DTB}: 940320/tftp-deploy-ss1q1dte/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 14:59:17.977070 - {INITRD}: 940320/tftp-deploy-ss1q1dte/ramdisk/ramdisk.cpio.gz.uboot
245 14:59:17.977277 - {KERNEL_ADDR}: 0x01080000
246 14:59:17.977483 - {KERNEL}: 940320/tftp-deploy-ss1q1dte/kernel/uImage
247 14:59:17.977687 - {LAVA_MAC}: None
248 14:59:17.977919 - {PRESEED_CONFIG}: None
249 14:59:17.978130 - {PRESEED_LOCAL}: None
250 14:59:17.978334 - {RAMDISK_ADDR}: 0x08000000
251 14:59:17.978533 - {RAMDISK}: 940320/tftp-deploy-ss1q1dte/ramdisk/ramdisk.cpio.gz.uboot
252 14:59:17.978740 - {ROOT_PART}: None
253 14:59:17.978944 - {ROOT}: None
254 14:59:17.979144 - {SERVER_IP}: 192.168.6.2
255 14:59:17.979347 - {TEE_ADDR}: 0x83000000
256 14:59:17.979549 - {TEE}: None
257 14:59:17.979749 Parsed boot commands:
258 14:59:17.979941 - setenv autoload no
259 14:59:17.980163 - setenv initrd_high 0xffffffff
260 14:59:17.980367 - setenv fdt_high 0xffffffff
261 14:59:17.980568 - dhcp
262 14:59:17.980772 - setenv serverip 192.168.6.2
263 14:59:17.980973 - tftpboot 0x01080000 940320/tftp-deploy-ss1q1dte/kernel/uImage
264 14:59:17.981175 - tftpboot 0x08000000 940320/tftp-deploy-ss1q1dte/ramdisk/ramdisk.cpio.gz.uboot
265 14:59:17.981378 - tftpboot 0x01070000 940320/tftp-deploy-ss1q1dte/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 14:59:17.981579 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 14:59:17.981785 - bootm 0x01080000 0x08000000 0x01070000
268 14:59:17.982063 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 14:59:17.982859 start: 2.3 connect-device (timeout 00:05:00) [common]
271 14:59:17.983109 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 14:59:17.996182 Setting prompt string to ['lava-test: # ']
273 14:59:17.997117 end: 2.3 connect-device (duration 00:00:00) [common]
274 14:59:17.997452 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 14:59:17.997761 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 14:59:17.998054 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 14:59:17.998679 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 14:59:18.035871 >> OK - accepted request
279 14:59:18.038314 Returned 0 in 0 seconds
280 14:59:18.139179 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 14:59:18.140270 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 14:59:18.140591 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 14:59:18.140886 Setting prompt string to ['Hit any key to stop autoboot']
285 14:59:18.141139 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 14:59:18.142086 Trying 192.168.56.21...
287 14:59:18.142402 Connected to conserv1.
288 14:59:18.142630 Escape character is '^]'.
289 14:59:18.142860
290 14:59:18.143091 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 14:59:18.143316
292 14:59:25.781567 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 14:59:25.782047 bl2_stage_init 0x01
294 14:59:25.782294 bl2_stage_init 0x81
295 14:59:25.787211 hw id: 0x0000 - pwm id 0x01
296 14:59:25.787737 bl2_stage_init 0xc1
297 14:59:25.793145 bl2_stage_init 0x02
298 14:59:25.793619
299 14:59:25.793966 L0:00000000
300 14:59:25.794299 L1:00000703
301 14:59:25.794618 L2:00008067
302 14:59:25.794857 L3:15000000
303 14:59:25.798165 S1:00000000
304 14:59:25.798500 B2:20282000
305 14:59:25.798722 B1:a0f83180
306 14:59:25.798930
307 14:59:25.799141 TE: 71235
308 14:59:25.799349
309 14:59:25.803771 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 14:59:25.804099
311 14:59:25.809512 Board ID = 1
312 14:59:25.809823 Set cpu clk to 24M
313 14:59:25.810042 Set clk81 to 24M
314 14:59:25.815146 Use GP1_pll as DSU clk.
315 14:59:25.815504 DSU clk: 1200 Mhz
316 14:59:25.815724 CPU clk: 1200 MHz
317 14:59:25.820630 Set clk81 to 166.6M
318 14:59:25.827230 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 14:59:25.827575 board id: 1
320 14:59:25.833383 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 14:59:25.844324 fw parse done
322 14:59:25.850250 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 14:59:25.893371 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 14:59:25.904526 PIEI prepare done
325 14:59:25.904931 fastboot data load
326 14:59:25.905166 fastboot data verify
327 14:59:25.910012 verify result: 266
328 14:59:25.915795 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 14:59:25.916155 LPDDR4 probe
330 14:59:25.916392 ddr clk to 1584MHz
331 14:59:25.924270 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 14:59:25.961631
333 14:59:25.962049 dmc_version 0001
334 14:59:25.968558 Check phy result
335 14:59:25.974456 INFO : End of CA training
336 14:59:25.974790 INFO : End of initialization
337 14:59:25.980035 INFO : Training has run successfully!
338 14:59:25.980334 Check phy result
339 14:59:25.985557 INFO : End of initialization
340 14:59:25.985892 INFO : End of read enable training
341 14:59:25.988926 INFO : End of fine write leveling
342 14:59:25.994555 INFO : End of Write leveling coarse delay
343 14:59:26.000179 INFO : Training has run successfully!
344 14:59:26.000544 Check phy result
345 14:59:26.000778 INFO : End of initialization
346 14:59:26.005680 INFO : End of read dq deskew training
347 14:59:26.011290 INFO : End of MPR read delay center optimization
348 14:59:26.011641 INFO : End of write delay center optimization
349 14:59:26.016871 INFO : End of read delay center optimization
350 14:59:26.022504 INFO : End of max read latency training
351 14:59:26.022951 INFO : Training has run successfully!
352 14:59:26.028114 1D training succeed
353 14:59:26.034159 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 14:59:26.082342 Check phy result
355 14:59:26.082765 INFO : End of initialization
356 14:59:26.109829 INFO : End of 2D read delay Voltage center optimization
357 14:59:26.133901 INFO : End of 2D read delay Voltage center optimization
358 14:59:26.190694 INFO : End of 2D write delay Voltage center optimization
359 14:59:26.244693 INFO : End of 2D write delay Voltage center optimization
360 14:59:26.250285 INFO : Training has run successfully!
361 14:59:26.250660
362 14:59:26.250901 channel==0
363 14:59:26.256109 RxClkDly_Margin_A0==78 ps 8
364 14:59:26.256466 TxDqDly_Margin_A0==98 ps 10
365 14:59:26.259026 RxClkDly_Margin_A1==88 ps 9
366 14:59:26.259336 TxDqDly_Margin_A1==98 ps 10
367 14:59:26.264593 TrainedVREFDQ_A0==74
368 14:59:26.264936 TrainedVREFDQ_A1==75
369 14:59:26.270166 VrefDac_Margin_A0==22
370 14:59:26.270491 DeviceVref_Margin_A0==40
371 14:59:26.270717 VrefDac_Margin_A1==22
372 14:59:26.275708 DeviceVref_Margin_A1==39
373 14:59:26.276076
374 14:59:26.276317
375 14:59:26.276535 channel==1
376 14:59:26.276750 RxClkDly_Margin_A0==78 ps 8
377 14:59:26.279282 TxDqDly_Margin_A0==98 ps 10
378 14:59:26.284853 RxClkDly_Margin_A1==78 ps 8
379 14:59:26.285218 TxDqDly_Margin_A1==88 ps 9
380 14:59:26.285452 TrainedVREFDQ_A0==78
381 14:59:26.290393 TrainedVREFDQ_A1==75
382 14:59:26.290726 VrefDac_Margin_A0==23
383 14:59:26.296045 DeviceVref_Margin_A0==36
384 14:59:26.296392 VrefDac_Margin_A1==22
385 14:59:26.296615 DeviceVref_Margin_A1==39
386 14:59:26.296830
387 14:59:26.301622 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 14:59:26.301969
389 14:59:26.335204 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 14:59:26.335637 2D training succeed
391 14:59:26.340858 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 14:59:26.346389 auto size-- 65535DDR cs0 size: 2048MB
393 14:59:26.346708 DDR cs1 size: 2048MB
394 14:59:26.352028 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 14:59:26.352361 cs0 DataBus test pass
396 14:59:26.352586 cs1 DataBus test pass
397 14:59:26.357560 cs0 AddrBus test pass
398 14:59:26.357865 cs1 AddrBus test pass
399 14:59:26.358084
400 14:59:26.363243 100bdlr_step_size ps== 471
401 14:59:26.363579 result report
402 14:59:26.363805 boot times 0Enable ddr reg access
403 14:59:26.372904 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 14:59:26.386747 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 14:59:27.046165 bl2z: ptr: 05129330, size: 00001e40
406 14:59:27.055190 0.0;M3 CHK:0;cm4_sp_mode 0
407 14:59:27.055713 MVN_1=0x00000000
408 14:59:27.056215 MVN_2=0x00000000
409 14:59:27.066612 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 14:59:27.067135 OPS=0x04
411 14:59:27.067586 ring efuse init
412 14:59:27.072238 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 14:59:27.072743 [0.017354 Inits done]
414 14:59:27.073187 secure task start!
415 14:59:27.080366 high task start!
416 14:59:27.080870 low task start!
417 14:59:27.081308 run into bl31
418 14:59:27.088996 NOTICE: BL31: v1.3(release):4fc40b1
419 14:59:27.096783 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 14:59:27.097298 NOTICE: BL31: G12A normal boot!
421 14:59:27.112365 NOTICE: BL31: BL33 decompress pass
422 14:59:27.118056 ERROR: Error initializing runtime service opteed_fast
423 14:59:29.830340 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 14:59:29.830800 bl2_stage_init 0x01
425 14:59:29.831031 bl2_stage_init 0x81
426 14:59:29.835941 hw id: 0x0000 - pwm id 0x01
427 14:59:29.836306 bl2_stage_init 0xc1
428 14:59:29.841529 bl2_stage_init 0x02
429 14:59:29.841881
430 14:59:29.842108 L0:00000000
431 14:59:29.842314 L1:00000703
432 14:59:29.842519 L2:00008067
433 14:59:29.842721 L3:15000000
434 14:59:29.847550 S1:00000000
435 14:59:29.847891 B2:20282000
436 14:59:29.848137 B1:a0f83180
437 14:59:29.848343
438 14:59:29.848546 TE: 68992
439 14:59:29.848765
440 14:59:29.852561 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 14:59:29.852839
442 14:59:29.858210 Board ID = 1
443 14:59:29.858512 Set cpu clk to 24M
444 14:59:29.858724 Set clk81 to 24M
445 14:59:29.863881 Use GP1_pll as DSU clk.
446 14:59:29.864251 DSU clk: 1200 Mhz
447 14:59:29.864464 CPU clk: 1200 MHz
448 14:59:29.869503 Set clk81 to 166.6M
449 14:59:29.875094 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 14:59:29.875436 board id: 1
451 14:59:29.882228 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 14:59:29.893141 fw parse done
453 14:59:29.898881 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 14:59:29.941539 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 14:59:29.952540 PIEI prepare done
456 14:59:29.952905 fastboot data load
457 14:59:29.953118 fastboot data verify
458 14:59:29.958043 verify result: 266
459 14:59:29.963653 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 14:59:29.963958 LPDDR4 probe
461 14:59:29.964207 ddr clk to 1584MHz
462 14:59:29.971679 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 14:59:30.008900
464 14:59:30.009298 dmc_version 0001
465 14:59:30.015577 Check phy result
466 14:59:30.021427 INFO : End of CA training
467 14:59:30.021717 INFO : End of initialization
468 14:59:30.027025 INFO : Training has run successfully!
469 14:59:30.027329 Check phy result
470 14:59:30.032652 INFO : End of initialization
471 14:59:30.032955 INFO : End of read enable training
472 14:59:30.038231 INFO : End of fine write leveling
473 14:59:30.043820 INFO : End of Write leveling coarse delay
474 14:59:30.044131 INFO : Training has run successfully!
475 14:59:30.044347 Check phy result
476 14:59:30.049441 INFO : End of initialization
477 14:59:30.049737 INFO : End of read dq deskew training
478 14:59:30.055015 INFO : End of MPR read delay center optimization
479 14:59:30.060660 INFO : End of write delay center optimization
480 14:59:30.066265 INFO : End of read delay center optimization
481 14:59:30.066579 INFO : End of max read latency training
482 14:59:30.071849 INFO : Training has run successfully!
483 14:59:30.072294 1D training succeed
484 14:59:30.081024 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 14:59:30.128775 Check phy result
486 14:59:30.129197 INFO : End of initialization
487 14:59:30.151076 INFO : End of 2D read delay Voltage center optimization
488 14:59:30.170179 INFO : End of 2D read delay Voltage center optimization
489 14:59:30.222065 INFO : End of 2D write delay Voltage center optimization
490 14:59:30.271238 INFO : End of 2D write delay Voltage center optimization
491 14:59:30.276778 INFO : Training has run successfully!
492 14:59:30.277087
493 14:59:30.277302 channel==0
494 14:59:30.282371 RxClkDly_Margin_A0==78 ps 8
495 14:59:30.282816 TxDqDly_Margin_A0==98 ps 10
496 14:59:30.288031 RxClkDly_Margin_A1==88 ps 9
497 14:59:30.288527 TxDqDly_Margin_A1==98 ps 10
498 14:59:30.288900 TrainedVREFDQ_A0==74
499 14:59:30.293591 TrainedVREFDQ_A1==75
500 14:59:30.293917 VrefDac_Margin_A0==23
501 14:59:30.294141 DeviceVref_Margin_A0==40
502 14:59:30.299179 VrefDac_Margin_A1==23
503 14:59:30.299636 DeviceVref_Margin_A1==39
504 14:59:30.300011
505 14:59:30.300388
506 14:59:30.304760 channel==1
507 14:59:30.305057 RxClkDly_Margin_A0==78 ps 8
508 14:59:30.305281 TxDqDly_Margin_A0==98 ps 10
509 14:59:30.310366 RxClkDly_Margin_A1==78 ps 8
510 14:59:30.311028 TxDqDly_Margin_A1==88 ps 9
511 14:59:30.315973 TrainedVREFDQ_A0==78
512 14:59:30.316460 TrainedVREFDQ_A1==75
513 14:59:30.316702 VrefDac_Margin_A0==22
514 14:59:30.321570 DeviceVref_Margin_A0==36
515 14:59:30.321861 VrefDac_Margin_A1==22
516 14:59:30.327161 DeviceVref_Margin_A1==39
517 14:59:30.327846
518 14:59:30.328253 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 14:59:30.328517
520 14:59:30.360787 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000019 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
521 14:59:30.361344 2D training succeed
522 14:59:30.366376 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 14:59:30.371951 auto size-- 65535DDR cs0 size: 2048MB
524 14:59:30.372278 DDR cs1 size: 2048MB
525 14:59:30.377598 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 14:59:30.378008 cs0 DataBus test pass
527 14:59:30.383193 cs1 DataBus test pass
528 14:59:30.383507 cs0 AddrBus test pass
529 14:59:30.383721 cs1 AddrBus test pass
530 14:59:30.383923
531 14:59:30.388780 100bdlr_step_size ps== 478
532 14:59:30.389078 result report
533 14:59:30.394361 boot times 0Enable ddr reg access
534 14:59:30.399661 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 14:59:30.413463 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 14:59:31.067964 bl2z: ptr: 05129330, size: 00001e40
537 14:59:31.075134 0.0;M3 CHK:0;cm4_sp_mode 0
538 14:59:31.075696 MVN_1=0x00000000
539 14:59:31.076217 MVN_2=0x00000000
540 14:59:31.086675 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 14:59:31.087195 OPS=0x04
542 14:59:31.087664 ring efuse init
543 14:59:31.092233 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 14:59:31.092757 [0.017310 Inits done]
545 14:59:31.093218 secure task start!
546 14:59:31.100171 high task start!
547 14:59:31.100693 low task start!
548 14:59:31.101154 run into bl31
549 14:59:31.108755 NOTICE: BL31: v1.3(release):4fc40b1
550 14:59:31.116525 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 14:59:31.117042 NOTICE: BL31: G12A normal boot!
552 14:59:31.132120 NOTICE: BL31: BL33 decompress pass
553 14:59:31.137839 ERROR: Error initializing runtime service opteed_fast
554 14:59:32.533013 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 14:59:32.533424 bl2_stage_init 0x01
556 14:59:32.533640 bl2_stage_init 0x81
557 14:59:32.538810 hw id: 0x0000 - pwm id 0x01
558 14:59:32.539098 bl2_stage_init 0xc1
559 14:59:32.539306 bl2_stage_init 0x02
560 14:59:32.539515
561 14:59:32.544222 L0:00000000
562 14:59:32.544491 L1:00000703
563 14:59:32.544696 L2:00008067
564 14:59:32.544905 L3:15000000
565 14:59:32.545112 S1:00000000
566 14:59:32.546281 B2:20282000
567 14:59:32.551786 B1:a0f83180
568 14:59:32.552054
569 14:59:32.552509 TE: 72046
570 14:59:32.552968
571 14:59:32.557648 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 14:59:32.558182
573 14:59:32.558645 Board ID = 1
574 14:59:32.559098 Set cpu clk to 24M
575 14:59:32.563078 Set clk81 to 24M
576 14:59:32.563353 Use GP1_pll as DSU clk.
577 14:59:32.563585 DSU clk: 1200 Mhz
578 14:59:32.566591 CPU clk: 1200 MHz
579 14:59:32.566872 Set clk81 to 166.6M
580 14:59:32.577767 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 14:59:32.578079 board id: 1
582 14:59:32.584186 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 14:59:32.595073 fw parse done
584 14:59:32.601060 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 14:59:32.644246 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 14:59:32.655321 PIEI prepare done
587 14:59:32.655658 fastboot data load
588 14:59:32.655895 fastboot data verify
589 14:59:32.660965 verify result: 266
590 14:59:32.666545 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 14:59:32.666882 LPDDR4 probe
592 14:59:32.667106 ddr clk to 1584MHz
593 14:59:32.674521 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 14:59:32.712296
595 14:59:32.712674 dmc_version 0001
596 14:59:32.719400 Check phy result
597 14:59:32.725330 INFO : End of CA training
598 14:59:32.725873 INFO : End of initialization
599 14:59:32.730925 INFO : Training has run successfully!
600 14:59:32.731442 Check phy result
601 14:59:32.736522 INFO : End of initialization
602 14:59:32.737037 INFO : End of read enable training
603 14:59:32.739918 INFO : End of fine write leveling
604 14:59:32.745315 INFO : End of Write leveling coarse delay
605 14:59:32.751076 INFO : Training has run successfully!
606 14:59:32.751596 Check phy result
607 14:59:32.752096 INFO : End of initialization
608 14:59:32.756532 INFO : End of read dq deskew training
609 14:59:32.760022 INFO : End of MPR read delay center optimization
610 14:59:32.765496 INFO : End of write delay center optimization
611 14:59:32.771131 INFO : End of read delay center optimization
612 14:59:32.771651 INFO : End of max read latency training
613 14:59:32.776924 INFO : Training has run successfully!
614 14:59:32.777444 1D training succeed
615 14:59:32.784903 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 14:59:32.833176 Check phy result
617 14:59:32.833718 INFO : End of initialization
618 14:59:32.860471 INFO : End of 2D read delay Voltage center optimization
619 14:59:32.884662 INFO : End of 2D read delay Voltage center optimization
620 14:59:32.941507 INFO : End of 2D write delay Voltage center optimization
621 14:59:32.995391 INFO : End of 2D write delay Voltage center optimization
622 14:59:33.000986 INFO : Training has run successfully!
623 14:59:33.001503
624 14:59:33.001994 channel==0
625 14:59:33.006552 RxClkDly_Margin_A0==88 ps 9
626 14:59:33.007058 TxDqDly_Margin_A0==88 ps 9
627 14:59:33.012221 RxClkDly_Margin_A1==88 ps 9
628 14:59:33.012740 TxDqDly_Margin_A1==88 ps 9
629 14:59:33.013212 TrainedVREFDQ_A0==74
630 14:59:33.017791 TrainedVREFDQ_A1==74
631 14:59:33.018296 VrefDac_Margin_A0==23
632 14:59:33.018758 DeviceVref_Margin_A0==40
633 14:59:33.023278 VrefDac_Margin_A1==22
634 14:59:33.023773 DeviceVref_Margin_A1==40
635 14:59:33.024290
636 14:59:33.024750
637 14:59:33.025197 channel==1
638 14:59:33.028968 RxClkDly_Margin_A0==88 ps 9
639 14:59:33.029476 TxDqDly_Margin_A0==98 ps 10
640 14:59:33.034557 RxClkDly_Margin_A1==78 ps 8
641 14:59:33.035058 TxDqDly_Margin_A1==88 ps 9
642 14:59:33.040133 TrainedVREFDQ_A0==78
643 14:59:33.040640 TrainedVREFDQ_A1==75
644 14:59:33.041100 VrefDac_Margin_A0==22
645 14:59:33.045661 DeviceVref_Margin_A0==36
646 14:59:33.046150 VrefDac_Margin_A1==22
647 14:59:33.046618 DeviceVref_Margin_A1==39
648 14:59:33.051258
649 14:59:33.051767 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 14:59:33.052269
651 14:59:33.084866 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
652 14:59:33.085420 2D training succeed
653 14:59:33.090460 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 14:59:33.096105 auto size-- 65535DDR cs0 size: 2048MB
655 14:59:33.096613 DDR cs1 size: 2048MB
656 14:59:33.101715 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 14:59:33.102231 cs0 DataBus test pass
658 14:59:33.107274 cs1 DataBus test pass
659 14:59:33.107776 cs0 AddrBus test pass
660 14:59:33.108267 cs1 AddrBus test pass
661 14:59:33.108720
662 14:59:33.112875 100bdlr_step_size ps== 485
663 14:59:33.113392 result report
664 14:59:33.118477 boot times 0Enable ddr reg access
665 14:59:33.123569 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 14:59:33.137503 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 14:59:33.797489 bl2z: ptr: 05129330, size: 00001e40
668 14:59:33.803828 0.0;M3 CHK:0;cm4_sp_mode 0
669 14:59:33.804187 MVN_1=0x00000000
670 14:59:33.804422 MVN_2=0x00000000
671 14:59:33.815370 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 14:59:33.815764 OPS=0x04
673 14:59:33.816007 ring efuse init
674 14:59:33.820945 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 14:59:33.821278 [0.017354 Inits done]
676 14:59:33.821498 secure task start!
677 14:59:33.829048 high task start!
678 14:59:33.829366 low task start!
679 14:59:33.829677 run into bl31
680 14:59:33.838170 NOTICE: BL31: v1.3(release):4fc40b1
681 14:59:33.845481 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 14:59:33.845816 NOTICE: BL31: G12A normal boot!
683 14:59:33.861043 NOTICE: BL31: BL33 decompress pass
684 14:59:33.866649 ERROR: Error initializing runtime service opteed_fast
685 14:59:34.662114
686 14:59:34.662793
687 14:59:34.667426 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 14:59:34.667942
689 14:59:34.670930 Model: Libre Computer AML-S905D3-CC Solitude
690 14:59:34.818027 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 14:59:34.833346 DRAM: 2 GiB (effective 3.8 GiB)
692 14:59:34.934427 Core: 406 devices, 33 uclasses, devicetree: separate
693 14:59:34.940179 WDT: Not starting watchdog@f0d0
694 14:59:34.965298 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 14:59:34.977481 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 14:59:34.982455 ** Bad device specification mmc 0 **
697 14:59:34.992560 Card did not respond to voltage select! : -110
698 14:59:35.000299 ** Bad device specification mmc 0 **
699 14:59:35.000868 Couldn't find partition mmc 0
700 14:59:35.008518 Card did not respond to voltage select! : -110
701 14:59:35.014036 ** Bad device specification mmc 0 **
702 14:59:35.014576 Couldn't find partition mmc 0
703 14:59:35.019091 Error: could not access storage.
704 14:59:35.316676 Net: eth0: ethernet@ff3f0000
705 14:59:35.317122 starting USB...
706 14:59:35.561304 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 14:59:35.561936 Starting the controller
708 14:59:35.568196 USB XHCI 1.10
709 14:59:37.122278 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 14:59:37.130621 scanning usb for storage devices... 0 Storage Device(s) found
712 14:59:37.182571 Hit any key to stop autoboot: 1
713 14:59:37.184057 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 14:59:37.184700 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 14:59:37.184982 Setting prompt string to ['=>']
716 14:59:37.185244 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 14:59:37.196647 0
718 14:59:37.197330 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 14:59:37.298249 => setenv autoload no
721 14:59:37.299000 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 14:59:37.303818 setenv autoload no
724 14:59:37.405427 => setenv initrd_high 0xffffffff
725 14:59:37.406150 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 14:59:37.410423 setenv initrd_high 0xffffffff
728 14:59:37.511914 => setenv fdt_high 0xffffffff
729 14:59:37.513149 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
730 14:59:37.516771 setenv fdt_high 0xffffffff
732 14:59:37.617916 => dhcp
733 14:59:37.618623 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 14:59:37.622594 dhcp
735 14:59:38.178074 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 14:59:38.178498 Speed: 1000, full duplex
737 14:59:38.178716 BOOTP broadcast 1
738 14:59:38.425855 BOOTP broadcast 2
739 14:59:38.450300 DHCP client bound to address 192.168.6.21 (272 ms)
741 14:59:38.551420 => setenv serverip 192.168.6.2
742 14:59:38.551962 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
743 14:59:38.556501 setenv serverip 192.168.6.2
745 14:59:38.657597 => tftpboot 0x01080000 940320/tftp-deploy-ss1q1dte/kernel/uImage
746 14:59:38.658130 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
747 14:59:38.664824 tftpboot 0x01080000 940320/tftp-deploy-ss1q1dte/kernel/uImage
748 14:59:38.665125 Speed: 1000, full duplex
749 14:59:38.665335 Using ethernet@ff3f0000 device
750 14:59:38.670418 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 14:59:38.675908 Filename '940320/tftp-deploy-ss1q1dte/kernel/uImage'.
752 14:59:38.679798 Load address: 0x1080000
753 14:59:41.586401 Loading: *################################################## 43.6 MiB
754 14:59:41.587026 15 MiB/s
755 14:59:41.587433 done
756 14:59:41.590616 Bytes transferred = 45713984 (2b98a40 hex)
758 14:59:41.692095 => tftpboot 0x08000000 940320/tftp-deploy-ss1q1dte/ramdisk/ramdisk.cpio.gz.uboot
759 14:59:41.692814 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
760 14:59:41.699581 tftpboot 0x08000000 940320/tftp-deploy-ss1q1dte/ramdisk/ramdisk.cpio.gz.uboot
761 14:59:41.700114 Speed: 1000, full duplex
762 14:59:41.700524 Using ethernet@ff3f0000 device
763 14:59:41.705187 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
764 14:59:41.714982 Filename '940320/tftp-deploy-ss1q1dte/ramdisk/ramdisk.cpio.gz.uboot'.
765 14:59:41.715464 Load address: 0x8000000
766 14:59:50.877606 Loading: *##########################T ####################### UDP wrong checksum 0000000f 0000679f
767 14:59:55.878789 T UDP wrong checksum 0000000f 0000679f
768 15:00:05.880757 T T UDP wrong checksum 0000000f 0000679f
769 15:00:25.884908 T T T T UDP wrong checksum 0000000f 0000679f
770 15:00:26.052309 UDP wrong checksum 000000ff 0000590a
771 15:00:26.062515 UDP wrong checksum 000000ff 0000e1fc
772 15:00:40.888807 T T
773 15:00:40.889241 Retry count exceeded; starting again
775 15:00:40.890102 end: 2.4.3 bootloader-commands (duration 00:01:04) [common]
778 15:00:40.891026 end: 2.4 uboot-commands (duration 00:01:23) [common]
780 15:00:40.891714 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
782 15:00:40.892325 end: 2 uboot-action (duration 00:01:23) [common]
784 15:00:40.893143 Cleaning after the job
785 15:00:40.893453 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/940320/tftp-deploy-ss1q1dte/ramdisk
786 15:00:40.894293 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/940320/tftp-deploy-ss1q1dte/kernel
787 15:00:40.910875 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/940320/tftp-deploy-ss1q1dte/dtb
788 15:00:40.911779 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/940320/tftp-deploy-ss1q1dte/modules
789 15:00:40.916466 start: 4.1 power-off (timeout 00:00:30) [common]
790 15:00:40.917083 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
791 15:00:40.950794 >> OK - accepted request
792 15:00:40.952975 Returned 0 in 0 seconds
793 15:00:41.053769 end: 4.1 power-off (duration 00:00:00) [common]
795 15:00:41.054794 start: 4.2 read-feedback (timeout 00:10:00) [common]
796 15:00:41.055453 Listened to connection for namespace 'common' for up to 1s
797 15:00:42.056308 Finalising connection for namespace 'common'
798 15:00:42.056841 Disconnecting from shell: Finalise
799 15:00:42.057181 =>
800 15:00:42.157910 end: 4.2 read-feedback (duration 00:00:01) [common]
801 15:00:42.158385 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/940320
802 15:00:42.792782 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/940320
803 15:00:42.793421 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.