Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 8
- Errors: 0
- Boot result: PASS
- Kernel Errors: 6
1 14:46:37.047416 lava-dispatcher, installed at version: 2024.01
2 14:46:37.048214 start: 0 validate
3 14:46:37.048710 Start time: 2024-11-05 14:46:37.048680+00:00 (UTC)
4 14:46:37.049239 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 14:46:37.049785 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 14:46:37.091968 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 14:46:37.092574 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-60-ge38568da5f05b%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 14:46:37.128092 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 14:46:37.128704 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-60-ge38568da5f05b%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 14:46:37.162109 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 14:46:37.162848 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 14:46:37.195666 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 14:46:37.196193 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-60-ge38568da5f05b%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 14:46:37.242786 validate duration: 0.19
16 14:46:37.244276 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 14:46:37.244877 start: 1.1 download-retry (timeout 00:10:00) [common]
18 14:46:37.245468 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 14:46:37.246394 Not decompressing ramdisk as can be used compressed.
20 14:46:37.247162 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 14:46:37.247665 saving as /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/ramdisk/initrd.cpio.gz
22 14:46:37.248188 total size: 5628169 (5 MB)
23 14:46:37.290681 progress 0 % (0 MB)
24 14:46:37.298793 progress 5 % (0 MB)
25 14:46:37.307378 progress 10 % (0 MB)
26 14:46:37.314912 progress 15 % (0 MB)
27 14:46:37.323014 progress 20 % (1 MB)
28 14:46:37.329029 progress 25 % (1 MB)
29 14:46:37.333039 progress 30 % (1 MB)
30 14:46:37.337044 progress 35 % (1 MB)
31 14:46:37.340599 progress 40 % (2 MB)
32 14:46:37.344512 progress 45 % (2 MB)
33 14:46:37.348065 progress 50 % (2 MB)
34 14:46:37.352061 progress 55 % (2 MB)
35 14:46:37.355960 progress 60 % (3 MB)
36 14:46:37.359661 progress 65 % (3 MB)
37 14:46:37.363581 progress 70 % (3 MB)
38 14:46:37.367121 progress 75 % (4 MB)
39 14:46:37.371240 progress 80 % (4 MB)
40 14:46:37.374794 progress 85 % (4 MB)
41 14:46:37.378722 progress 90 % (4 MB)
42 14:46:37.382541 progress 95 % (5 MB)
43 14:46:37.385792 progress 100 % (5 MB)
44 14:46:37.386448 5 MB downloaded in 0.14 s (38.82 MB/s)
45 14:46:37.386985 end: 1.1.1 http-download (duration 00:00:00) [common]
47 14:46:37.387886 end: 1.1 download-retry (duration 00:00:00) [common]
48 14:46:37.388217 start: 1.2 download-retry (timeout 00:10:00) [common]
49 14:46:37.388497 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 14:46:37.388963 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-60-ge38568da5f05b/arm64/defconfig/gcc-12/kernel/Image
51 14:46:37.389213 saving as /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/kernel/Image
52 14:46:37.389427 total size: 45713920 (43 MB)
53 14:46:37.389641 No compression specified
54 14:46:37.430230 progress 0 % (0 MB)
55 14:46:37.458605 progress 5 % (2 MB)
56 14:46:37.486897 progress 10 % (4 MB)
57 14:46:37.514557 progress 15 % (6 MB)
58 14:46:37.542350 progress 20 % (8 MB)
59 14:46:37.570040 progress 25 % (10 MB)
60 14:46:37.597768 progress 30 % (13 MB)
61 14:46:37.626851 progress 35 % (15 MB)
62 14:46:37.655611 progress 40 % (17 MB)
63 14:46:37.684899 progress 45 % (19 MB)
64 14:46:37.714047 progress 50 % (21 MB)
65 14:46:37.743284 progress 55 % (24 MB)
66 14:46:37.773006 progress 60 % (26 MB)
67 14:46:37.803747 progress 65 % (28 MB)
68 14:46:37.831784 progress 70 % (30 MB)
69 14:46:37.860218 progress 75 % (32 MB)
70 14:46:37.888144 progress 80 % (34 MB)
71 14:46:37.915825 progress 85 % (37 MB)
72 14:46:37.943736 progress 90 % (39 MB)
73 14:46:37.971696 progress 95 % (41 MB)
74 14:46:37.998849 progress 100 % (43 MB)
75 14:46:37.999364 43 MB downloaded in 0.61 s (71.48 MB/s)
76 14:46:37.999858 end: 1.2.1 http-download (duration 00:00:01) [common]
78 14:46:38.000743 end: 1.2 download-retry (duration 00:00:01) [common]
79 14:46:38.001030 start: 1.3 download-retry (timeout 00:09:59) [common]
80 14:46:38.001305 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 14:46:38.001785 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-60-ge38568da5f05b/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 14:46:38.002074 saving as /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/dtb/meson-g12b-a311d-libretech-cc.dtb
83 14:46:38.002291 total size: 54703 (0 MB)
84 14:46:38.002504 No compression specified
85 14:46:38.045254 progress 59 % (0 MB)
86 14:46:38.046094 progress 100 % (0 MB)
87 14:46:38.046665 0 MB downloaded in 0.04 s (1.18 MB/s)
88 14:46:38.047140 end: 1.3.1 http-download (duration 00:00:00) [common]
90 14:46:38.047974 end: 1.3 download-retry (duration 00:00:00) [common]
91 14:46:38.048299 start: 1.4 download-retry (timeout 00:09:59) [common]
92 14:46:38.048576 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 14:46:38.049032 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 14:46:38.049289 saving as /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/nfsrootfs/full.rootfs.tar
95 14:46:38.049498 total size: 120894716 (115 MB)
96 14:46:38.049713 Using unxz to decompress xz
97 14:46:38.086804 progress 0 % (0 MB)
98 14:46:38.872142 progress 5 % (5 MB)
99 14:46:39.696888 progress 10 % (11 MB)
100 14:46:40.489624 progress 15 % (17 MB)
101 14:46:41.219045 progress 20 % (23 MB)
102 14:46:41.819007 progress 25 % (28 MB)
103 14:46:42.641474 progress 30 % (34 MB)
104 14:46:43.436325 progress 35 % (40 MB)
105 14:46:43.788074 progress 40 % (46 MB)
106 14:46:44.174572 progress 45 % (51 MB)
107 14:46:44.884618 progress 50 % (57 MB)
108 14:46:45.766122 progress 55 % (63 MB)
109 14:46:46.543599 progress 60 % (69 MB)
110 14:46:47.293786 progress 65 % (74 MB)
111 14:46:48.099550 progress 70 % (80 MB)
112 14:46:48.922240 progress 75 % (86 MB)
113 14:46:49.703067 progress 80 % (92 MB)
114 14:46:50.461785 progress 85 % (98 MB)
115 14:46:51.320220 progress 90 % (103 MB)
116 14:46:52.098834 progress 95 % (109 MB)
117 14:46:52.934570 progress 100 % (115 MB)
118 14:46:52.947419 115 MB downloaded in 14.90 s (7.74 MB/s)
119 14:46:52.948279 end: 1.4.1 http-download (duration 00:00:15) [common]
121 14:46:52.950016 end: 1.4 download-retry (duration 00:00:15) [common]
122 14:46:52.950565 start: 1.5 download-retry (timeout 00:09:44) [common]
123 14:46:52.951097 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 14:46:52.952257 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-60-ge38568da5f05b/arm64/defconfig/gcc-12/modules.tar.xz
125 14:46:52.952815 saving as /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/modules/modules.tar
126 14:46:52.953241 total size: 11603148 (11 MB)
127 14:46:52.953673 Using unxz to decompress xz
128 14:46:53.003766 progress 0 % (0 MB)
129 14:46:53.073323 progress 5 % (0 MB)
130 14:46:53.149214 progress 10 % (1 MB)
131 14:46:53.246689 progress 15 % (1 MB)
132 14:46:53.338042 progress 20 % (2 MB)
133 14:46:53.416544 progress 25 % (2 MB)
134 14:46:53.491360 progress 30 % (3 MB)
135 14:46:53.564277 progress 35 % (3 MB)
136 14:46:53.639792 progress 40 % (4 MB)
137 14:46:53.714628 progress 45 % (5 MB)
138 14:46:53.796882 progress 50 % (5 MB)
139 14:46:53.872281 progress 55 % (6 MB)
140 14:46:53.955630 progress 60 % (6 MB)
141 14:46:54.034936 progress 65 % (7 MB)
142 14:46:54.110138 progress 70 % (7 MB)
143 14:46:54.191169 progress 75 % (8 MB)
144 14:46:54.273070 progress 80 % (8 MB)
145 14:46:54.347445 progress 85 % (9 MB)
146 14:46:54.428779 progress 90 % (9 MB)
147 14:46:54.505040 progress 95 % (10 MB)
148 14:46:54.581161 progress 100 % (11 MB)
149 14:46:54.591350 11 MB downloaded in 1.64 s (6.76 MB/s)
150 14:46:54.592249 end: 1.5.1 http-download (duration 00:00:02) [common]
152 14:46:54.593900 end: 1.5 download-retry (duration 00:00:02) [common]
153 14:46:54.594442 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 14:46:54.594981 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 14:47:10.849249 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/940325/extract-nfsrootfs-v394bfrr
156 14:47:10.849857 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 14:47:10.850146 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 14:47:10.850836 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s
159 14:47:10.851276 makedir: /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin
160 14:47:10.851599 makedir: /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/tests
161 14:47:10.851909 makedir: /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/results
162 14:47:10.852302 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-add-keys
163 14:47:10.852829 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-add-sources
164 14:47:10.853323 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-background-process-start
165 14:47:10.853845 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-background-process-stop
166 14:47:10.854386 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-common-functions
167 14:47:10.854878 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-echo-ipv4
168 14:47:10.855359 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-install-packages
169 14:47:10.855824 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-installed-packages
170 14:47:10.856332 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-os-build
171 14:47:10.856810 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-probe-channel
172 14:47:10.857277 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-probe-ip
173 14:47:10.857764 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-target-ip
174 14:47:10.858242 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-target-mac
175 14:47:10.858712 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-target-storage
176 14:47:10.859190 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-test-case
177 14:47:10.859657 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-test-event
178 14:47:10.860215 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-test-feedback
179 14:47:10.860701 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-test-raise
180 14:47:10.861167 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-test-reference
181 14:47:10.861660 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-test-runner
182 14:47:10.862148 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-test-set
183 14:47:10.862616 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-test-shell
184 14:47:10.863091 Updating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-add-keys (debian)
185 14:47:10.863615 Updating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-add-sources (debian)
186 14:47:10.864129 Updating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-install-packages (debian)
187 14:47:10.864626 Updating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-installed-packages (debian)
188 14:47:10.865112 Updating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/bin/lava-os-build (debian)
189 14:47:10.865541 Creating /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/environment
190 14:47:10.865900 LAVA metadata
191 14:47:10.866162 - LAVA_JOB_ID=940325
192 14:47:10.866378 - LAVA_DISPATCHER_IP=192.168.6.2
193 14:47:10.866739 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 14:47:10.867680 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 14:47:10.868040 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 14:47:10.868260 skipped lava-vland-overlay
197 14:47:10.868505 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 14:47:10.868765 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 14:47:10.868987 skipped lava-multinode-overlay
200 14:47:10.869231 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 14:47:10.869485 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 14:47:10.869731 Loading test definitions
203 14:47:10.870010 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 14:47:10.870230 Using /lava-940325 at stage 0
205 14:47:10.871314 uuid=940325_1.6.2.4.1 testdef=None
206 14:47:10.871623 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 14:47:10.871889 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 14:47:10.873460 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 14:47:10.874256 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 14:47:10.876173 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 14:47:10.877010 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 14:47:10.878828 runner path: /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/0/tests/0_timesync-off test_uuid 940325_1.6.2.4.1
215 14:47:10.879387 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 14:47:10.880280 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 14:47:10.880516 Using /lava-940325 at stage 0
219 14:47:10.880872 Fetching tests from https://github.com/kernelci/test-definitions.git
220 14:47:10.881165 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/0/tests/1_kselftest-alsa'
221 14:47:14.429160 Running '/usr/bin/git checkout kernelci.org
222 14:47:14.782222 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 14:47:14.783677 uuid=940325_1.6.2.4.5 testdef=None
224 14:47:14.784053 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 14:47:14.784829 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 14:47:14.787731 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 14:47:14.788593 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 14:47:14.792370 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 14:47:14.793252 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 14:47:14.796934 runner path: /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/0/tests/1_kselftest-alsa test_uuid 940325_1.6.2.4.5
234 14:47:14.797236 BOARD='meson-g12b-a311d-libretech-cc'
235 14:47:14.797446 BRANCH='broonie-spi'
236 14:47:14.797649 SKIPFILE='/dev/null'
237 14:47:14.797853 SKIP_INSTALL='True'
238 14:47:14.798051 TESTPROG_URL='http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-60-ge38568da5f05b/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 14:47:14.798292 TST_CASENAME=''
240 14:47:14.798494 TST_CMDFILES='alsa'
241 14:47:14.799059 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 14:47:14.799859 Creating lava-test-runner.conf files
244 14:47:14.800095 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/940325/lava-overlay-8amygi2s/lava-940325/0 for stage 0
245 14:47:14.800458 - 0_timesync-off
246 14:47:14.800700 - 1_kselftest-alsa
247 14:47:14.801035 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 14:47:14.801320 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 14:47:39.653703 end: 1.6.2.5 compress-overlay (duration 00:00:25) [common]
250 14:47:39.654161 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 14:47:39.654429 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 14:47:39.654708 end: 1.6.2 lava-overlay (duration 00:00:29) [common]
253 14:47:39.654981 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 14:47:40.275809 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 14:47:40.276355 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 14:47:40.276635 extracting modules file /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/940325/extract-nfsrootfs-v394bfrr
257 14:47:41.667608 extracting modules file /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/940325/extract-overlay-ramdisk-_rfzgkt1/ramdisk
258 14:47:43.074704 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 14:47:43.075187 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 14:47:43.075471 [common] Applying overlay to NFS
261 14:47:43.075691 [common] Applying overlay /var/lib/lava/dispatcher/tmp/940325/compress-overlay-hz89vcyx/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/940325/extract-nfsrootfs-v394bfrr
262 14:47:45.803071 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 14:47:45.803529 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 14:47:45.803807 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 14:47:45.804068 Converting downloaded kernel to a uImage
266 14:47:45.804389 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/kernel/Image /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/kernel/uImage
267 14:47:46.278078 output: Image Name:
268 14:47:46.278487 output: Created: Tue Nov 5 14:47:45 2024
269 14:47:46.278704 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 14:47:46.278915 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 14:47:46.279121 output: Load Address: 01080000
272 14:47:46.279327 output: Entry Point: 01080000
273 14:47:46.279531 output:
274 14:47:46.279867 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 14:47:46.280185 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 14:47:46.280465 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 14:47:46.280726 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 14:47:46.280989 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 14:47:46.281248 Building ramdisk /var/lib/lava/dispatcher/tmp/940325/extract-overlay-ramdisk-_rfzgkt1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/940325/extract-overlay-ramdisk-_rfzgkt1/ramdisk
280 14:47:48.402141 >> 166774 blocks
281 14:47:56.156215 Adding RAMdisk u-boot header.
282 14:47:56.156672 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/940325/extract-overlay-ramdisk-_rfzgkt1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/940325/extract-overlay-ramdisk-_rfzgkt1/ramdisk.cpio.gz.uboot
283 14:47:56.432897 output: Image Name:
284 14:47:56.433323 output: Created: Tue Nov 5 14:47:56 2024
285 14:47:56.433538 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 14:47:56.433749 output: Data Size: 23428294 Bytes = 22879.19 KiB = 22.34 MiB
287 14:47:56.433955 output: Load Address: 00000000
288 14:47:56.434161 output: Entry Point: 00000000
289 14:47:56.434365 output:
290 14:47:56.435344 rename /var/lib/lava/dispatcher/tmp/940325/extract-overlay-ramdisk-_rfzgkt1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/ramdisk/ramdisk.cpio.gz.uboot
291 14:47:56.436160 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 14:47:56.436758 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 14:47:56.437436 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 14:47:56.438048 No LXC device requested
295 14:47:56.438638 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 14:47:56.439166 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 14:47:56.439670 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 14:47:56.440124 Checking files for TFTP limit of 4294967296 bytes.
299 14:47:56.442811 end: 1 tftp-deploy (duration 00:01:19) [common]
300 14:47:56.443404 start: 2 uboot-action (timeout 00:05:00) [common]
301 14:47:56.443938 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 14:47:56.444484 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 14:47:56.444999 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 14:47:56.445537 Using kernel file from prepare-kernel: 940325/tftp-deploy-mkzwf0bj/kernel/uImage
305 14:47:56.446171 substitutions:
306 14:47:56.446585 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 14:47:56.446995 - {DTB_ADDR}: 0x01070000
308 14:47:56.447401 - {DTB}: 940325/tftp-deploy-mkzwf0bj/dtb/meson-g12b-a311d-libretech-cc.dtb
309 14:47:56.447809 - {INITRD}: 940325/tftp-deploy-mkzwf0bj/ramdisk/ramdisk.cpio.gz.uboot
310 14:47:56.448250 - {KERNEL_ADDR}: 0x01080000
311 14:47:56.448649 - {KERNEL}: 940325/tftp-deploy-mkzwf0bj/kernel/uImage
312 14:47:56.449050 - {LAVA_MAC}: None
313 14:47:56.449489 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/940325/extract-nfsrootfs-v394bfrr
314 14:47:56.449900 - {NFS_SERVER_IP}: 192.168.6.2
315 14:47:56.450298 - {PRESEED_CONFIG}: None
316 14:47:56.450696 - {PRESEED_LOCAL}: None
317 14:47:56.451097 - {RAMDISK_ADDR}: 0x08000000
318 14:47:56.451489 - {RAMDISK}: 940325/tftp-deploy-mkzwf0bj/ramdisk/ramdisk.cpio.gz.uboot
319 14:47:56.451884 - {ROOT_PART}: None
320 14:47:56.452307 - {ROOT}: None
321 14:47:56.452703 - {SERVER_IP}: 192.168.6.2
322 14:47:56.453097 - {TEE_ADDR}: 0x83000000
323 14:47:56.453488 - {TEE}: None
324 14:47:56.453882 Parsed boot commands:
325 14:47:56.454266 - setenv autoload no
326 14:47:56.454660 - setenv initrd_high 0xffffffff
327 14:47:56.455050 - setenv fdt_high 0xffffffff
328 14:47:56.455437 - dhcp
329 14:47:56.455825 - setenv serverip 192.168.6.2
330 14:47:56.456286 - tftpboot 0x01080000 940325/tftp-deploy-mkzwf0bj/kernel/uImage
331 14:47:56.456687 - tftpboot 0x08000000 940325/tftp-deploy-mkzwf0bj/ramdisk/ramdisk.cpio.gz.uboot
332 14:47:56.457080 - tftpboot 0x01070000 940325/tftp-deploy-mkzwf0bj/dtb/meson-g12b-a311d-libretech-cc.dtb
333 14:47:56.457475 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/940325/extract-nfsrootfs-v394bfrr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 14:47:56.457877 - bootm 0x01080000 0x08000000 0x01070000
335 14:47:56.458398 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 14:47:56.459901 start: 2.3 connect-device (timeout 00:05:00) [common]
338 14:47:56.460431 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 14:47:56.476669 Setting prompt string to ['lava-test: # ']
340 14:47:56.478249 end: 2.3 connect-device (duration 00:00:00) [common]
341 14:47:56.478882 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 14:47:56.479450 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 14:47:56.480011 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 14:47:56.481194 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 14:47:56.519710 >> OK - accepted request
346 14:47:56.521926 Returned 0 in 0 seconds
347 14:47:56.622772 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 14:47:56.623826 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 14:47:56.624190 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 14:47:56.624485 Setting prompt string to ['Hit any key to stop autoboot']
352 14:47:56.624723 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 14:47:56.625669 Trying 192.168.56.21...
354 14:47:56.625962 Connected to conserv1.
355 14:47:56.626182 Escape character is '^]'.
356 14:47:56.626390
357 14:47:56.626609 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 14:47:56.626819
359 14:48:07.530597 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 14:48:07.531228 bl2_stage_init 0x01
361 14:48:07.531637 bl2_stage_init 0x81
362 14:48:07.536073 hw id: 0x0000 - pwm id 0x01
363 14:48:07.536580 bl2_stage_init 0xc1
364 14:48:07.536998 bl2_stage_init 0x02
365 14:48:07.537410
366 14:48:07.541596 L0:00000000
367 14:48:07.542101 L1:20000703
368 14:48:07.542515 L2:00008067
369 14:48:07.542921 L3:14000000
370 14:48:07.547232 B2:00402000
371 14:48:07.547718 B1:e0f83180
372 14:48:07.548164
373 14:48:07.548560 TE: 58159
374 14:48:07.548955
375 14:48:07.552926 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 14:48:07.553405
377 14:48:07.553801 Board ID = 1
378 14:48:07.558388 Set A53 clk to 24M
379 14:48:07.558860 Set A73 clk to 24M
380 14:48:07.559260 Set clk81 to 24M
381 14:48:07.564057 A53 clk: 1200 MHz
382 14:48:07.564526 A73 clk: 1200 MHz
383 14:48:07.564926 CLK81: 166.6M
384 14:48:07.565317 smccc: 00012ab5
385 14:48:07.569594 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 14:48:07.575039 board id: 1
387 14:48:07.581043 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 14:48:07.591536 fw parse done
389 14:48:07.597515 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 14:48:07.640112 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 14:48:07.651018 PIEI prepare done
392 14:48:07.651342 fastboot data load
393 14:48:07.651568 fastboot data verify
394 14:48:07.656767 verify result: 266
395 14:48:07.662281 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 14:48:07.662587 LPDDR4 probe
397 14:48:07.662807 ddr clk to 1584MHz
398 14:48:07.670227 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 14:48:07.707752
400 14:48:07.708175 dmc_version 0001
401 14:48:07.714130 Check phy result
402 14:48:07.720034 INFO : End of CA training
403 14:48:07.720350 INFO : End of initialization
404 14:48:07.725781 INFO : Training has run successfully!
405 14:48:07.726081 Check phy result
406 14:48:07.731237 INFO : End of initialization
407 14:48:07.731543 INFO : End of read enable training
408 14:48:07.736874 INFO : End of fine write leveling
409 14:48:07.742453 INFO : End of Write leveling coarse delay
410 14:48:07.742760 INFO : Training has run successfully!
411 14:48:07.742982 Check phy result
412 14:48:07.748184 INFO : End of initialization
413 14:48:07.748750 INFO : End of read dq deskew training
414 14:48:07.753825 INFO : End of MPR read delay center optimization
415 14:48:07.759254 INFO : End of write delay center optimization
416 14:48:07.764868 INFO : End of read delay center optimization
417 14:48:07.765403 INFO : End of max read latency training
418 14:48:07.770443 INFO : Training has run successfully!
419 14:48:07.770990 1D training succeed
420 14:48:07.779601 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 14:48:07.827225 Check phy result
422 14:48:07.827808 INFO : End of initialization
423 14:48:07.848954 INFO : End of 2D read delay Voltage center optimization
424 14:48:07.869147 INFO : End of 2D read delay Voltage center optimization
425 14:48:07.921207 INFO : End of 2D write delay Voltage center optimization
426 14:48:07.970596 INFO : End of 2D write delay Voltage center optimization
427 14:48:07.976194 INFO : Training has run successfully!
428 14:48:07.976523
429 14:48:07.976761 channel==0
430 14:48:07.981797 RxClkDly_Margin_A0==88 ps 9
431 14:48:07.982114 TxDqDly_Margin_A0==98 ps 10
432 14:48:07.987374 RxClkDly_Margin_A1==88 ps 9
433 14:48:07.987690 TxDqDly_Margin_A1==98 ps 10
434 14:48:07.987919 TrainedVREFDQ_A0==74
435 14:48:07.992982 TrainedVREFDQ_A1==74
436 14:48:07.993306 VrefDac_Margin_A0==25
437 14:48:07.993542 DeviceVref_Margin_A0==40
438 14:48:07.998601 VrefDac_Margin_A1==25
439 14:48:07.998925 DeviceVref_Margin_A1==40
440 14:48:07.999157
441 14:48:07.999381
442 14:48:08.004201 channel==1
443 14:48:08.004525 RxClkDly_Margin_A0==98 ps 10
444 14:48:08.004764 TxDqDly_Margin_A0==98 ps 10
445 14:48:08.009804 RxClkDly_Margin_A1==98 ps 10
446 14:48:08.010134 TxDqDly_Margin_A1==88 ps 9
447 14:48:08.015373 TrainedVREFDQ_A0==77
448 14:48:08.015702 TrainedVREFDQ_A1==77
449 14:48:08.015937 VrefDac_Margin_A0==23
450 14:48:08.020989 DeviceVref_Margin_A0==37
451 14:48:08.021320 VrefDac_Margin_A1==22
452 14:48:08.026610 DeviceVref_Margin_A1==37
453 14:48:08.026944
454 14:48:08.027186 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 14:48:08.032207
456 14:48:08.060171 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 14:48:08.060602 2D training succeed
458 14:48:08.065808 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 14:48:08.071379 auto size-- 65535DDR cs0 size: 2048MB
460 14:48:08.071709 DDR cs1 size: 2048MB
461 14:48:08.076984 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 14:48:08.077309 cs0 DataBus test pass
463 14:48:08.082611 cs1 DataBus test pass
464 14:48:08.082939 cs0 AddrBus test pass
465 14:48:08.083177 cs1 AddrBus test pass
466 14:48:08.083402
467 14:48:08.088213 100bdlr_step_size ps== 420
468 14:48:08.088552 result report
469 14:48:08.093862 boot times 0Enable ddr reg access
470 14:48:08.099257 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 14:48:08.112687 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 14:48:08.686322 0.0;M3 CHK:0;cm4_sp_mode 0
473 14:48:08.686758 MVN_1=0x00000000
474 14:48:08.691889 MVN_2=0x00000000
475 14:48:08.697598 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 14:48:08.697935 OPS=0x10
477 14:48:08.698169 ring efuse init
478 14:48:08.698388 chipver efuse init
479 14:48:08.703151 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 14:48:08.708860 [0.018961 Inits done]
481 14:48:08.709206 secure task start!
482 14:48:08.709437 high task start!
483 14:48:08.713341 low task start!
484 14:48:08.713808 run into bl31
485 14:48:08.720123 NOTICE: BL31: v1.3(release):4fc40b1
486 14:48:08.728011 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 14:48:08.728638 NOTICE: BL31: G12A normal boot!
488 14:48:08.753215 NOTICE: BL31: BL33 decompress pass
489 14:48:08.758954 ERROR: Error initializing runtime service opteed_fast
490 14:48:09.991804
491 14:48:09.992563
492 14:48:10.000155 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 14:48:10.000740
494 14:48:10.001242 Model: Libre Computer AML-A311D-CC Alta
495 14:48:10.208567 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 14:48:10.232019 DRAM: 2 GiB (effective 3.8 GiB)
497 14:48:10.375005 Core: 408 devices, 31 uclasses, devicetree: separate
498 14:48:10.380813 WDT: Not starting watchdog@f0d0
499 14:48:10.413133 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 14:48:10.425538 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 14:48:10.430516 ** Bad device specification mmc 0 **
502 14:48:10.440870 Card did not respond to voltage select! : -110
503 14:48:10.448517 ** Bad device specification mmc 0 **
504 14:48:10.449118 Couldn't find partition mmc 0
505 14:48:10.456864 Card did not respond to voltage select! : -110
506 14:48:10.462344 ** Bad device specification mmc 0 **
507 14:48:10.462985 Couldn't find partition mmc 0
508 14:48:10.467388 Error: could not access storage.
509 14:48:11.730883 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
510 14:48:11.731579 bl2_stage_init 0x81
511 14:48:11.736369 hw id: 0x0000 - pwm id 0x01
512 14:48:11.736924 bl2_stage_init 0xc1
513 14:48:11.737439 bl2_stage_init 0x02
514 14:48:11.737913
515 14:48:11.741944 L0:00000000
516 14:48:11.742507 L1:20000703
517 14:48:11.742969 L2:00008067
518 14:48:11.743415 L3:14000000
519 14:48:11.743863 B2:00402000
520 14:48:11.744726 B1:e0f83180
521 14:48:11.745212
522 14:48:11.745673 TE: 58150
523 14:48:11.746145
524 14:48:11.756027 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 14:48:11.756645
526 14:48:11.757113 Board ID = 1
527 14:48:11.757584 Set A53 clk to 24M
528 14:48:11.758064 Set A73 clk to 24M
529 14:48:11.761553 Set clk81 to 24M
530 14:48:11.762079 A53 clk: 1200 MHz
531 14:48:11.762538 A73 clk: 1200 MHz
532 14:48:11.767148 CLK81: 166.6M
533 14:48:11.767945 smccc: 00012aab
534 14:48:11.772755 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 14:48:11.773311 board id: 1
536 14:48:11.781435 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 14:48:11.792108 fw parse done
538 14:48:11.797968 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 14:48:11.840612 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 14:48:11.851503 PIEI prepare done
541 14:48:11.852091 fastboot data load
542 14:48:11.852610 fastboot data verify
543 14:48:11.857152 verify result: 266
544 14:48:11.862745 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 14:48:11.863278 LPDDR4 probe
546 14:48:11.863735 ddr clk to 1584MHz
547 14:48:11.870741 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 14:48:11.908129
549 14:48:11.908514 dmc_version 0001
550 14:48:11.914666 Check phy result
551 14:48:11.920542 INFO : End of CA training
552 14:48:11.921119 INFO : End of initialization
553 14:48:11.926168 INFO : Training has run successfully!
554 14:48:11.926757 Check phy result
555 14:48:11.931748 INFO : End of initialization
556 14:48:11.932336 INFO : End of read enable training
557 14:48:11.937444 INFO : End of fine write leveling
558 14:48:11.942947 INFO : End of Write leveling coarse delay
559 14:48:11.943505 INFO : Training has run successfully!
560 14:48:11.944015 Check phy result
561 14:48:11.948556 INFO : End of initialization
562 14:48:11.949153 INFO : End of read dq deskew training
563 14:48:11.954166 INFO : End of MPR read delay center optimization
564 14:48:11.959750 INFO : End of write delay center optimization
565 14:48:11.965436 INFO : End of read delay center optimization
566 14:48:11.966025 INFO : End of max read latency training
567 14:48:11.970979 INFO : Training has run successfully!
568 14:48:11.971563 1D training succeed
569 14:48:11.980151 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 14:48:12.027788 Check phy result
571 14:48:12.028487 INFO : End of initialization
572 14:48:12.050388 INFO : End of 2D read delay Voltage center optimization
573 14:48:12.070606 INFO : End of 2D read delay Voltage center optimization
574 14:48:12.122676 INFO : End of 2D write delay Voltage center optimization
575 14:48:12.172112 INFO : End of 2D write delay Voltage center optimization
576 14:48:12.177623 INFO : Training has run successfully!
577 14:48:12.178247
578 14:48:12.178762 channel==0
579 14:48:12.183232 RxClkDly_Margin_A0==88 ps 9
580 14:48:12.183836 TxDqDly_Margin_A0==98 ps 10
581 14:48:12.186488 RxClkDly_Margin_A1==88 ps 9
582 14:48:12.187056 TxDqDly_Margin_A1==98 ps 10
583 14:48:12.191971 TrainedVREFDQ_A0==74
584 14:48:12.192371 TrainedVREFDQ_A1==74
585 14:48:12.197594 VrefDac_Margin_A0==24
586 14:48:12.198120 DeviceVref_Margin_A0==40
587 14:48:12.198503 VrefDac_Margin_A1==25
588 14:48:12.203218 DeviceVref_Margin_A1==40
589 14:48:12.203634
590 14:48:12.203917
591 14:48:12.204221 channel==1
592 14:48:12.204483 RxClkDly_Margin_A0==98 ps 10
593 14:48:12.208806 TxDqDly_Margin_A0==98 ps 10
594 14:48:12.209205 RxClkDly_Margin_A1==98 ps 10
595 14:48:12.214506 TxDqDly_Margin_A1==88 ps 9
596 14:48:12.214918 TrainedVREFDQ_A0==77
597 14:48:12.215172 TrainedVREFDQ_A1==77
598 14:48:12.219995 VrefDac_Margin_A0==22
599 14:48:12.220403 DeviceVref_Margin_A0==37
600 14:48:12.225579 VrefDac_Margin_A1==22
601 14:48:12.226154 DeviceVref_Margin_A1==37
602 14:48:12.226579
603 14:48:12.231204 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 14:48:12.231620
605 14:48:12.259205 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
606 14:48:12.264805 2D training succeed
607 14:48:12.270504 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 14:48:12.270923 auto size-- 65535DDR cs0 size: 2048MB
609 14:48:12.276050 DDR cs1 size: 2048MB
610 14:48:12.276472 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 14:48:12.281606 cs0 DataBus test pass
612 14:48:12.282171 cs1 DataBus test pass
613 14:48:12.282639 cs0 AddrBus test pass
614 14:48:12.287227 cs1 AddrBus test pass
615 14:48:12.287623
616 14:48:12.288102 100bdlr_step_size ps== 420
617 14:48:12.288460 result report
618 14:48:12.292830 boot times 0Enable ddr reg access
619 14:48:12.300627 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 14:48:12.314115 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 14:48:12.887308 0.0;M3 CHK:0;cm4_sp_mode 0
622 14:48:12.888046 MVN_1=0x00000000
623 14:48:12.892680 MVN_2=0x00000000
624 14:48:12.898428 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 14:48:12.899030 OPS=0x10
626 14:48:12.899521 ring efuse init
627 14:48:12.900031 chipver efuse init
628 14:48:12.906928 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 14:48:12.907571 [0.018961 Inits done]
630 14:48:12.908056 secure task start!
631 14:48:12.914306 high task start!
632 14:48:12.914799 low task start!
633 14:48:12.915242 run into bl31
634 14:48:12.920952 NOTICE: BL31: v1.3(release):4fc40b1
635 14:48:12.928794 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 14:48:12.929386 NOTICE: BL31: G12A normal boot!
637 14:48:12.954674 NOTICE: BL31: BL33 decompress pass
638 14:48:12.960534 ERROR: Error initializing runtime service opteed_fast
639 14:48:14.193442
640 14:48:14.194125
641 14:48:14.201921 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 14:48:14.202549
643 14:48:14.203097 Model: Libre Computer AML-A311D-CC Alta
644 14:48:14.410173 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 14:48:14.433475 DRAM: 2 GiB (effective 3.8 GiB)
646 14:48:14.576532 Core: 408 devices, 31 uclasses, devicetree: separate
647 14:48:14.582361 WDT: Not starting watchdog@f0d0
648 14:48:14.614803 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 14:48:14.627196 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 14:48:14.632123 ** Bad device specification mmc 0 **
651 14:48:14.642317 Card did not respond to voltage select! : -110
652 14:48:14.650026 ** Bad device specification mmc 0 **
653 14:48:14.650638 Couldn't find partition mmc 0
654 14:48:14.658309 Card did not respond to voltage select! : -110
655 14:48:14.664029 ** Bad device specification mmc 0 **
656 14:48:14.664637 Couldn't find partition mmc 0
657 14:48:14.669047 Error: could not access storage.
658 14:48:15.011515 Net: eth0: ethernet@ff3f0000
659 14:48:15.012268 starting USB...
660 14:48:15.263356 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 14:48:15.264094 Starting the controller
662 14:48:15.270156 USB XHCI 1.10
663 14:48:16.979757 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
664 14:48:16.980275 bl2_stage_init 0x01
665 14:48:16.980539 bl2_stage_init 0x81
666 14:48:16.985391 hw id: 0x0000 - pwm id 0x01
667 14:48:16.986007 bl2_stage_init 0xc1
668 14:48:16.986409 bl2_stage_init 0x02
669 14:48:16.986785
670 14:48:16.990941 L0:00000000
671 14:48:16.991331 L1:20000703
672 14:48:16.992086 L2:00008067
673 14:48:16.992393 L3:14000000
674 14:48:16.993834 B2:00402000
675 14:48:16.994325 B1:e0f83180
676 14:48:16.994744
677 14:48:16.995164 TE: 58159
678 14:48:16.995606
679 14:48:17.005051 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 14:48:17.005492
681 14:48:17.005794 Board ID = 1
682 14:48:17.006078 Set A53 clk to 24M
683 14:48:17.006367 Set A73 clk to 24M
684 14:48:17.010742 Set clk81 to 24M
685 14:48:17.011170 A53 clk: 1200 MHz
686 14:48:17.011444 A73 clk: 1200 MHz
687 14:48:17.016377 CLK81: 166.6M
688 14:48:17.016803 smccc: 00012ab5
689 14:48:17.021812 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 14:48:17.022234 board id: 1
691 14:48:17.030504 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 14:48:17.040859 fw parse done
693 14:48:17.046864 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 14:48:17.089633 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 14:48:17.100341 PIEI prepare done
696 14:48:17.100933 fastboot data load
697 14:48:17.101255 fastboot data verify
698 14:48:17.105984 verify result: 266
699 14:48:17.111636 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 14:48:17.112081 LPDDR4 probe
701 14:48:17.112357 ddr clk to 1584MHz
702 14:48:17.119656 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 14:48:17.159835
704 14:48:17.160465 dmc_version 0001
705 14:48:17.163548 Check phy result
706 14:48:17.169345 INFO : End of CA training
707 14:48:17.169751 INFO : End of initialization
708 14:48:17.175004 INFO : Training has run successfully!
709 14:48:17.175392 Check phy result
710 14:48:17.180673 INFO : End of initialization
711 14:48:17.181282 INFO : End of read enable training
712 14:48:17.184061 INFO : End of fine write leveling
713 14:48:17.189672 INFO : End of Write leveling coarse delay
714 14:48:17.195137 INFO : Training has run successfully!
715 14:48:17.195558 Check phy result
716 14:48:17.195804 INFO : End of initialization
717 14:48:17.200684 INFO : End of read dq deskew training
718 14:48:17.206253 INFO : End of MPR read delay center optimization
719 14:48:17.206608 INFO : End of write delay center optimization
720 14:48:17.212112 INFO : End of read delay center optimization
721 14:48:17.217571 INFO : End of max read latency training
722 14:48:17.218142 INFO : Training has run successfully!
723 14:48:17.223116 1D training succeed
724 14:48:17.229033 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 14:48:17.276488 Check phy result
726 14:48:17.276895 INFO : End of initialization
727 14:48:17.298210 INFO : End of 2D read delay Voltage center optimization
728 14:48:17.318395 INFO : End of 2D read delay Voltage center optimization
729 14:48:17.370413 INFO : End of 2D write delay Voltage center optimization
730 14:48:17.419478 INFO : End of 2D write delay Voltage center optimization
731 14:48:17.425025 INFO : Training has run successfully!
732 14:48:17.425598
733 14:48:17.426075 channel==0
734 14:48:17.430483 RxClkDly_Margin_A0==88 ps 9
735 14:48:17.430858 TxDqDly_Margin_A0==98 ps 10
736 14:48:17.436302 RxClkDly_Margin_A1==88 ps 9
737 14:48:17.436869 TxDqDly_Margin_A1==98 ps 10
738 14:48:17.437346 TrainedVREFDQ_A0==74
739 14:48:17.441854 TrainedVREFDQ_A1==74
740 14:48:17.442448 VrefDac_Margin_A0==25
741 14:48:17.442933 DeviceVref_Margin_A0==40
742 14:48:17.447437 VrefDac_Margin_A1==25
743 14:48:17.448054 DeviceVref_Margin_A1==40
744 14:48:17.448555
745 14:48:17.449031
746 14:48:17.453070 channel==1
747 14:48:17.453677 RxClkDly_Margin_A0==98 ps 10
748 14:48:17.454163 TxDqDly_Margin_A0==98 ps 10
749 14:48:17.458652 RxClkDly_Margin_A1==98 ps 10
750 14:48:17.459227 TxDqDly_Margin_A1==88 ps 9
751 14:48:17.464308 TrainedVREFDQ_A0==77
752 14:48:17.464646 TrainedVREFDQ_A1==77
753 14:48:17.464906 VrefDac_Margin_A0==22
754 14:48:17.469806 DeviceVref_Margin_A0==37
755 14:48:17.470388 VrefDac_Margin_A1==24
756 14:48:17.475439 DeviceVref_Margin_A1==37
757 14:48:17.476055
758 14:48:17.476549 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 14:48:17.481008
760 14:48:17.508975 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
761 14:48:17.509630 2D training succeed
762 14:48:17.514623 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 14:48:17.520357 auto size-- 65535DDR cs0 size: 2048MB
764 14:48:17.520735 DDR cs1 size: 2048MB
765 14:48:17.525702 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 14:48:17.526260 cs0 DataBus test pass
767 14:48:17.531318 cs1 DataBus test pass
768 14:48:17.531654 cs0 AddrBus test pass
769 14:48:17.531889 cs1 AddrBus test pass
770 14:48:17.532159
771 14:48:17.537045 100bdlr_step_size ps== 420
772 14:48:17.537640 result report
773 14:48:17.542626 boot times 0Enable ddr reg access
774 14:48:17.548097 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 14:48:17.561547 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 14:48:18.133450 0.0;M3 CHK:0;cm4_sp_mode 0
777 14:48:18.134140 MVN_1=0x00000000
778 14:48:18.139027 MVN_2=0x00000000
779 14:48:18.144719 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 14:48:18.145302 OPS=0x10
781 14:48:18.145755 ring efuse init
782 14:48:18.146191 chipver efuse init
783 14:48:18.150257 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 14:48:18.155847 [0.018961 Inits done]
785 14:48:18.156383 secure task start!
786 14:48:18.156824 high task start!
787 14:48:18.160428 low task start!
788 14:48:18.160919 run into bl31
789 14:48:18.167213 NOTICE: BL31: v1.3(release):4fc40b1
790 14:48:18.174929 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 14:48:18.175460 NOTICE: BL31: G12A normal boot!
792 14:48:18.200426 NOTICE: BL31: BL33 decompress pass
793 14:48:18.205990 ERROR: Error initializing runtime service opteed_fast
794 14:48:19.438863
795 14:48:19.439501
796 14:48:19.447247 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 14:48:19.447755
798 14:48:19.448237 Model: Libre Computer AML-A311D-CC Alta
799 14:48:19.655778 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 14:48:19.679302 DRAM: 2 GiB (effective 3.8 GiB)
801 14:48:19.822140 Core: 408 devices, 31 uclasses, devicetree: separate
802 14:48:19.828079 WDT: Not starting watchdog@f0d0
803 14:48:19.860288 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 14:48:19.872670 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 14:48:19.877711 ** Bad device specification mmc 0 **
806 14:48:19.888082 Card did not respond to voltage select! : -110
807 14:48:19.895680 ** Bad device specification mmc 0 **
808 14:48:19.896269 Couldn't find partition mmc 0
809 14:48:19.904158 Card did not respond to voltage select! : -110
810 14:48:19.909866 ** Bad device specification mmc 0 **
811 14:48:19.910554 Couldn't find partition mmc 0
812 14:48:19.914663 Error: could not access storage.
813 14:48:20.257036 Net: eth0: ethernet@ff3f0000
814 14:48:20.257465 starting USB...
815 14:48:20.508728 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 14:48:20.509166 Starting the controller
817 14:48:20.514747 USB XHCI 1.10
818 14:48:22.679565 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 14:48:22.680056 bl2_stage_init 0x01
820 14:48:22.680321 bl2_stage_init 0x81
821 14:48:22.685165 hw id: 0x0000 - pwm id 0x01
822 14:48:22.685541 bl2_stage_init 0xc1
823 14:48:22.685796 bl2_stage_init 0x02
824 14:48:22.686028
825 14:48:22.690678 L0:00000000
826 14:48:22.691209 L1:20000703
827 14:48:22.691467 L2:00008067
828 14:48:22.691682 L3:14000000
829 14:48:22.696300 B2:00402000
830 14:48:22.696612 B1:e0f83180
831 14:48:22.696844
832 14:48:22.697068 TE: 58124
833 14:48:22.697823
834 14:48:22.702019 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 14:48:22.702461
836 14:48:22.702731 Board ID = 1
837 14:48:22.707531 Set A53 clk to 24M
838 14:48:22.707945 Set A73 clk to 24M
839 14:48:22.708240 Set clk81 to 24M
840 14:48:22.713106 A53 clk: 1200 MHz
841 14:48:22.713414 A73 clk: 1200 MHz
842 14:48:22.713647 CLK81: 166.6M
843 14:48:22.713883 smccc: 00012a92
844 14:48:22.718631 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 14:48:22.724161 board id: 1
846 14:48:22.730041 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 14:48:22.740927 fw parse done
848 14:48:22.746739 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 14:48:22.788468 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 14:48:22.800246 PIEI prepare done
851 14:48:22.800738 fastboot data load
852 14:48:22.801154 fastboot data verify
853 14:48:22.805921 verify result: 266
854 14:48:22.811462 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 14:48:22.811925 LPDDR4 probe
856 14:48:22.812382 ddr clk to 1584MHz
857 14:48:22.819477 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 14:48:22.856789
859 14:48:22.857279 dmc_version 0001
860 14:48:22.863392 Check phy result
861 14:48:22.869221 INFO : End of CA training
862 14:48:22.869678 INFO : End of initialization
863 14:48:22.874894 INFO : Training has run successfully!
864 14:48:22.875349 Check phy result
865 14:48:22.880467 INFO : End of initialization
866 14:48:22.880923 INFO : End of read enable training
867 14:48:22.886130 INFO : End of fine write leveling
868 14:48:22.891683 INFO : End of Write leveling coarse delay
869 14:48:22.892168 INFO : Training has run successfully!
870 14:48:22.892580 Check phy result
871 14:48:22.897272 INFO : End of initialization
872 14:48:22.897723 INFO : End of read dq deskew training
873 14:48:22.902943 INFO : End of MPR read delay center optimization
874 14:48:22.908468 INFO : End of write delay center optimization
875 14:48:22.914073 INFO : End of read delay center optimization
876 14:48:22.914538 INFO : End of max read latency training
877 14:48:22.919679 INFO : Training has run successfully!
878 14:48:22.920180 1D training succeed
879 14:48:22.928964 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 14:48:22.976512 Check phy result
881 14:48:22.977041 INFO : End of initialization
882 14:48:22.998274 INFO : End of 2D read delay Voltage center optimization
883 14:48:23.018514 INFO : End of 2D read delay Voltage center optimization
884 14:48:23.070549 INFO : End of 2D write delay Voltage center optimization
885 14:48:23.120034 INFO : End of 2D write delay Voltage center optimization
886 14:48:23.125462 INFO : Training has run successfully!
887 14:48:23.125922
888 14:48:23.126338 channel==0
889 14:48:23.131056 RxClkDly_Margin_A0==88 ps 9
890 14:48:23.131503 TxDqDly_Margin_A0==98 ps 10
891 14:48:23.136705 RxClkDly_Margin_A1==88 ps 9
892 14:48:23.137169 TxDqDly_Margin_A1==98 ps 10
893 14:48:23.137592 TrainedVREFDQ_A0==74
894 14:48:23.142365 TrainedVREFDQ_A1==74
895 14:48:23.142857 VrefDac_Margin_A0==25
896 14:48:23.143265 DeviceVref_Margin_A0==40
897 14:48:23.148032 VrefDac_Margin_A1==25
898 14:48:23.148514 DeviceVref_Margin_A1==40
899 14:48:23.148905
900 14:48:23.149290
901 14:48:23.153532 channel==1
902 14:48:23.153985 RxClkDly_Margin_A0==98 ps 10
903 14:48:23.154377 TxDqDly_Margin_A0==98 ps 10
904 14:48:23.159082 RxClkDly_Margin_A1==88 ps 9
905 14:48:23.159537 TxDqDly_Margin_A1==88 ps 9
906 14:48:23.164743 TrainedVREFDQ_A0==77
907 14:48:23.165209 TrainedVREFDQ_A1==77
908 14:48:23.165605 VrefDac_Margin_A0==22
909 14:48:23.170285 DeviceVref_Margin_A0==37
910 14:48:23.170742 VrefDac_Margin_A1==24
911 14:48:23.176038 DeviceVref_Margin_A1==37
912 14:48:23.176516
913 14:48:23.176941 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 14:48:23.177338
915 14:48:23.209468 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
916 14:48:23.209977 2D training succeed
917 14:48:23.215110 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 14:48:23.220721 auto size-- 65535DDR cs0 size: 2048MB
919 14:48:23.221188 DDR cs1 size: 2048MB
920 14:48:23.226267 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 14:48:23.226723 cs0 DataBus test pass
922 14:48:23.232060 cs1 DataBus test pass
923 14:48:23.232532 cs0 AddrBus test pass
924 14:48:23.232921 cs1 AddrBus test pass
925 14:48:23.233307
926 14:48:23.237441 100bdlr_step_size ps== 420
927 14:48:23.237916 result report
928 14:48:23.243168 boot times 0Enable ddr reg access
929 14:48:23.247468 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 14:48:23.260926 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 14:48:23.835443 0.0;M3 CHK:0;cm4_sp_mode 0
932 14:48:23.836127 MVN_1=0x00000000
933 14:48:23.841060 MVN_2=0x00000000
934 14:48:23.847623 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 14:48:23.848188 OPS=0x10
936 14:48:23.848619 ring efuse init
937 14:48:23.849028 chipver efuse init
938 14:48:23.855027 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 14:48:23.855568 [0.018961 Inits done]
940 14:48:23.864263 secure task start!
941 14:48:23.864852 high task start!
942 14:48:23.865294 low task start!
943 14:48:23.865706 run into bl31
944 14:48:23.869182 NOTICE: BL31: v1.3(release):4fc40b1
945 14:48:23.878363 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 14:48:23.878926 NOTICE: BL31: G12A normal boot!
947 14:48:23.903837 NOTICE: BL31: BL33 decompress pass
948 14:48:23.908140 ERROR: Error initializing runtime service opteed_fast
949 14:48:25.140746
950 14:48:25.141169
951 14:48:25.148544 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 14:48:25.148874
953 14:48:25.149109 Model: Libre Computer AML-A311D-CC Alta
954 14:48:25.357590 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 14:48:25.381023 DRAM: 2 GiB (effective 3.8 GiB)
956 14:48:25.524105 Core: 408 devices, 31 uclasses, devicetree: separate
957 14:48:25.529946 WDT: Not starting watchdog@f0d0
958 14:48:25.562250 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 14:48:25.574673 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 14:48:25.578651 ** Bad device specification mmc 0 **
961 14:48:25.589961 Card did not respond to voltage select! : -110
962 14:48:25.597645 ** Bad device specification mmc 0 **
963 14:48:25.598063 Couldn't find partition mmc 0
964 14:48:25.605982 Card did not respond to voltage select! : -110
965 14:48:25.611475 ** Bad device specification mmc 0 **
966 14:48:25.611836 Couldn't find partition mmc 0
967 14:48:25.616537 Error: could not access storage.
968 14:48:25.959117 Net: eth0: ethernet@ff3f0000
969 14:48:25.959740 starting USB...
970 14:48:26.210797 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 14:48:26.211238 Starting the controller
972 14:48:26.217778 USB XHCI 1.10
973 14:48:28.079525 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
974 14:48:28.080151 bl2_stage_init 0x01
975 14:48:28.080420 bl2_stage_init 0x81
976 14:48:28.085020 hw id: 0x0000 - pwm id 0x01
977 14:48:28.085325 bl2_stage_init 0xc1
978 14:48:28.085541 bl2_stage_init 0x02
979 14:48:28.085760
980 14:48:28.090933 L0:00000000
981 14:48:28.091229 L1:20000703
982 14:48:28.091458 L2:00008067
983 14:48:28.091678 L3:14000000
984 14:48:28.096217 B2:00402000
985 14:48:28.096502 B1:e0f83180
986 14:48:28.096732
987 14:48:28.096958 TE: 58124
988 14:48:28.097171
989 14:48:28.101814 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 14:48:28.102109
991 14:48:28.102338 Board ID = 1
992 14:48:28.107425 Set A53 clk to 24M
993 14:48:28.107715 Set A73 clk to 24M
994 14:48:28.107928 Set clk81 to 24M
995 14:48:28.113017 A53 clk: 1200 MHz
996 14:48:28.113307 A73 clk: 1200 MHz
997 14:48:28.113521 CLK81: 166.6M
998 14:48:28.113742 smccc: 00012a92
999 14:48:28.118736 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 14:48:28.124213 board id: 1
1001 14:48:28.129355 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 14:48:28.140814 fw parse done
1003 14:48:28.146822 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 14:48:28.189265 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 14:48:28.200173 PIEI prepare done
1006 14:48:28.200503 fastboot data load
1007 14:48:28.200722 fastboot data verify
1008 14:48:28.205770 verify result: 266
1009 14:48:28.211351 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 14:48:28.211649 LPDDR4 probe
1011 14:48:28.211863 ddr clk to 1584MHz
1012 14:48:28.218377 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 14:48:28.255750
1014 14:48:28.256141 dmc_version 0001
1015 14:48:28.263298 Check phy result
1016 14:48:28.269103 INFO : End of CA training
1017 14:48:28.269375 INFO : End of initialization
1018 14:48:28.274727 INFO : Training has run successfully!
1019 14:48:28.275006 Check phy result
1020 14:48:28.280333 INFO : End of initialization
1021 14:48:28.280621 INFO : End of read enable training
1022 14:48:28.283626 INFO : End of fine write leveling
1023 14:48:28.289152 INFO : End of Write leveling coarse delay
1024 14:48:28.294759 INFO : Training has run successfully!
1025 14:48:28.295056 Check phy result
1026 14:48:28.295288 INFO : End of initialization
1027 14:48:28.300425 INFO : End of read dq deskew training
1028 14:48:28.305939 INFO : End of MPR read delay center optimization
1029 14:48:28.306234 INFO : End of write delay center optimization
1030 14:48:28.311623 INFO : End of read delay center optimization
1031 14:48:28.317151 INFO : End of max read latency training
1032 14:48:28.317578 INFO : Training has run successfully!
1033 14:48:28.322760 1D training succeed
1034 14:48:28.328729 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 14:48:28.376370 Check phy result
1036 14:48:28.376763 INFO : End of initialization
1037 14:48:28.398977 INFO : End of 2D read delay Voltage center optimization
1038 14:48:28.419137 INFO : End of 2D read delay Voltage center optimization
1039 14:48:28.470252 INFO : End of 2D write delay Voltage center optimization
1040 14:48:28.520638 INFO : End of 2D write delay Voltage center optimization
1041 14:48:28.526120 INFO : Training has run successfully!
1042 14:48:28.526454
1043 14:48:28.526709 channel==0
1044 14:48:28.531687 RxClkDly_Margin_A0==88 ps 9
1045 14:48:28.532228 TxDqDly_Margin_A0==98 ps 10
1046 14:48:28.537345 RxClkDly_Margin_A1==88 ps 9
1047 14:48:28.537722 TxDqDly_Margin_A1==98 ps 10
1048 14:48:28.537974 TrainedVREFDQ_A0==74
1049 14:48:28.542876 TrainedVREFDQ_A1==74
1050 14:48:28.543207 VrefDac_Margin_A0==25
1051 14:48:28.543453 DeviceVref_Margin_A0==40
1052 14:48:28.548584 VrefDac_Margin_A1==25
1053 14:48:28.548934 DeviceVref_Margin_A1==40
1054 14:48:28.549200
1055 14:48:28.549446
1056 14:48:28.554094 channel==1
1057 14:48:28.554432 RxClkDly_Margin_A0==98 ps 10
1058 14:48:28.554687 TxDqDly_Margin_A0==98 ps 10
1059 14:48:28.559747 RxClkDly_Margin_A1==88 ps 9
1060 14:48:28.560083 TxDqDly_Margin_A1==88 ps 9
1061 14:48:28.565364 TrainedVREFDQ_A0==77
1062 14:48:28.565875 TrainedVREFDQ_A1==77
1063 14:48:28.566309 VrefDac_Margin_A0==22
1064 14:48:28.570932 DeviceVref_Margin_A0==37
1065 14:48:28.571409 VrefDac_Margin_A1==24
1066 14:48:28.576645 DeviceVref_Margin_A1==37
1067 14:48:28.577121
1068 14:48:28.577545 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 14:48:28.577954
1070 14:48:28.610106 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1071 14:48:28.610630 2D training succeed
1072 14:48:28.615703 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 14:48:28.621324 auto size-- 65535DDR cs0 size: 2048MB
1074 14:48:28.621802 DDR cs1 size: 2048MB
1075 14:48:28.626918 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 14:48:28.627386 cs0 DataBus test pass
1077 14:48:28.632680 cs1 DataBus test pass
1078 14:48:28.633157 cs0 AddrBus test pass
1079 14:48:28.633584 cs1 AddrBus test pass
1080 14:48:28.633999
1081 14:48:28.638373 100bdlr_step_size ps== 420
1082 14:48:28.638854 result report
1083 14:48:28.643726 boot times 0Enable ddr reg access
1084 14:48:28.648207 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 14:48:28.662599 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 14:48:29.236287 0.0;M3 CHK:0;cm4_sp_mode 0
1087 14:48:29.236924 MVN_1=0x00000000
1088 14:48:29.241750 MVN_2=0x00000000
1089 14:48:29.247446 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 14:48:29.247771 OPS=0x10
1091 14:48:29.248032 ring efuse init
1092 14:48:29.248262 chipver efuse init
1093 14:48:29.255672 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 14:48:29.256012 [0.018961 Inits done]
1095 14:48:29.262753 secure task start!
1096 14:48:29.263148 high task start!
1097 14:48:29.263367 low task start!
1098 14:48:29.263575 run into bl31
1099 14:48:29.269944 NOTICE: BL31: v1.3(release):4fc40b1
1100 14:48:29.276880 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 14:48:29.277393 NOTICE: BL31: G12A normal boot!
1102 14:48:29.303066 NOTICE: BL31: BL33 decompress pass
1103 14:48:29.308902 ERROR: Error initializing runtime service opteed_fast
1104 14:48:30.541670
1105 14:48:30.542348
1106 14:48:30.549053 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 14:48:30.549598
1108 14:48:30.550096 Model: Libre Computer AML-A311D-CC Alta
1109 14:48:30.758516 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 14:48:30.780886 DRAM: 2 GiB (effective 3.8 GiB)
1111 14:48:30.924844 Core: 408 devices, 31 uclasses, devicetree: separate
1112 14:48:30.929716 WDT: Not starting watchdog@f0d0
1113 14:48:30.963092 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 14:48:30.975476 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 14:48:30.979496 ** Bad device specification mmc 0 **
1116 14:48:30.990730 Card did not respond to voltage select! : -110
1117 14:48:30.998472 ** Bad device specification mmc 0 **
1118 14:48:30.999144 Couldn't find partition mmc 0
1119 14:48:31.006682 Card did not respond to voltage select! : -110
1120 14:48:31.012227 ** Bad device specification mmc 0 **
1121 14:48:31.012786 Couldn't find partition mmc 0
1122 14:48:31.016318 Error: could not access storage.
1123 14:48:31.360779 Net: eth0: ethernet@ff3f0000
1124 14:48:31.361157 starting USB...
1125 14:48:31.612584 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 14:48:31.613135 Starting the controller
1127 14:48:31.619523 USB XHCI 1.10
1128 14:48:33.173753 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 14:48:33.182108 scanning usb for storage devices... 0 Storage Device(s) found
1131 14:48:33.233295 Hit any key to stop autoboot: 1
1132 14:48:33.234253 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1133 14:48:33.234657 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1134 14:48:33.234935 Setting prompt string to ['=>']
1135 14:48:33.235214 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1136 14:48:33.249773 0
1137 14:48:33.251137 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 14:48:33.251479 Sending with 10 millisecond of delay
1140 14:48:34.388476 => setenv autoload no
1141 14:48:34.399352 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1142 14:48:34.404692 setenv autoload no
1143 14:48:34.405496 Sending with 10 millisecond of delay
1145 14:48:36.210078 => setenv initrd_high 0xffffffff
1146 14:48:36.220841 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1147 14:48:36.221428 setenv initrd_high 0xffffffff
1148 14:48:36.221914 Sending with 10 millisecond of delay
1150 14:48:37.841519 => setenv fdt_high 0xffffffff
1151 14:48:37.852282 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1152 14:48:37.852845 setenv fdt_high 0xffffffff
1153 14:48:37.853301 Sending with 10 millisecond of delay
1155 14:48:38.144786 => dhcp
1156 14:48:38.155557 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1157 14:48:38.156143 dhcp
1158 14:48:38.156385 Speed: 1000, full duplex
1159 14:48:38.156597 BOOTP broadcast 1
1160 14:48:38.163735 DHCP client bound to address 192.168.6.27 (8 ms)
1161 14:48:38.164429 Sending with 10 millisecond of delay
1163 14:48:39.844581 => setenv serverip 192.168.6.2
1164 14:48:39.856776 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1165 14:48:39.857383 setenv serverip 192.168.6.2
1166 14:48:39.858506 Sending with 10 millisecond of delay
1168 14:48:43.581941 => tftpboot 0x01080000 940325/tftp-deploy-mkzwf0bj/kernel/uImage
1169 14:48:43.592831 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1170 14:48:43.593506 tftpboot 0x01080000 940325/tftp-deploy-mkzwf0bj/kernel/uImage
1171 14:48:43.593806 Speed: 1000, full duplex
1172 14:48:43.594078 Using ethernet@ff3f0000 device
1173 14:48:43.595204 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1174 14:48:43.600860 Filename '940325/tftp-deploy-mkzwf0bj/kernel/uImage'.
1175 14:48:43.604776 Load address: 0x1080000
1176 14:48:46.457032 Loading: *################################################## 43.6 MiB
1177 14:48:46.458188 15.3 MiB/s
1178 14:48:46.458521 done
1179 14:48:46.461492 Bytes transferred = 45713984 (2b98a40 hex)
1180 14:48:46.462285 Sending with 10 millisecond of delay
1182 14:48:51.147952 => tftpboot 0x08000000 940325/tftp-deploy-mkzwf0bj/ramdisk/ramdisk.cpio.gz.uboot
1183 14:48:51.158773 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1184 14:48:51.159634 tftpboot 0x08000000 940325/tftp-deploy-mkzwf0bj/ramdisk/ramdisk.cpio.gz.uboot
1185 14:48:51.160124 Speed: 1000, full duplex
1186 14:48:51.160546 Using ethernet@ff3f0000 device
1187 14:48:51.161695 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1188 14:48:51.173465 Filename '940325/tftp-deploy-mkzwf0bj/ramdisk/ramdisk.cpio.gz.uboot'.
1189 14:48:51.173986 Load address: 0x8000000
1190 14:48:57.710604 Loading: *#######################T ########################### 22.3 MiB
1191 14:48:57.711028 3.4 MiB/s
1192 14:48:57.711265 done
1193 14:48:57.714865 Bytes transferred = 23428358 (1657d06 hex)
1194 14:48:57.715421 Sending with 10 millisecond of delay
1196 14:49:02.885618 => tftpboot 0x01070000 940325/tftp-deploy-mkzwf0bj/dtb/meson-g12b-a311d-libretech-cc.dtb
1197 14:49:02.896308 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:54)
1198 14:49:02.896830 tftpboot 0x01070000 940325/tftp-deploy-mkzwf0bj/dtb/meson-g12b-a311d-libretech-cc.dtb
1199 14:49:02.897073 Speed: 1000, full duplex
1200 14:49:02.897291 Using ethernet@ff3f0000 device
1201 14:49:02.901180 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1202 14:49:02.913928 Filename '940325/tftp-deploy-mkzwf0bj/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1203 14:49:02.914365 Load address: 0x1070000
1204 14:49:02.930027 Loading: *################################################## 53.4 KiB
1205 14:49:02.930454 2.9 MiB/s
1206 14:49:02.930781 done
1207 14:49:02.936426 Bytes transferred = 54703 (d5af hex)
1208 14:49:02.937021 Sending with 10 millisecond of delay
1210 14:49:16.234068 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/940325/extract-nfsrootfs-v394bfrr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1211 14:49:16.246168 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:40)
1212 14:49:16.246684 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/940325/extract-nfsrootfs-v394bfrr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1213 14:49:16.247131 Sending with 10 millisecond of delay
1215 14:49:18.590203 => bootm 0x01080000 0x08000000 0x01070000
1216 14:49:18.600896 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1217 14:49:18.601433 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:38)
1218 14:49:18.602130 bootm 0x01080000 0x08000000 0x01070000
1219 14:49:18.602433 ## Booting kernel from Legacy Image at 01080000 ...
1220 14:49:18.605723 Image Name:
1221 14:49:18.611309 Image Type: AArch64 Linux Kernel Image (uncompressed)
1222 14:49:18.611642 Data Size: 45713920 Bytes = 43.6 MiB
1223 14:49:18.616769 Load Address: 01080000
1224 14:49:18.617094 Entry Point: 01080000
1225 14:49:18.812118 Verifying Checksum ... OK
1226 14:49:18.812556 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1227 14:49:18.817663 Image Name:
1228 14:49:18.823041 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1229 14:49:18.823443 Data Size: 23428294 Bytes = 22.3 MiB
1230 14:49:18.825361 Load Address: 00000000
1231 14:49:18.832728 Entry Point: 00000000
1232 14:49:18.930654 Verifying Checksum ... OK
1233 14:49:18.931067 ## Flattened Device Tree blob at 01070000
1234 14:49:18.936143 Booting using the fdt blob at 0x1070000
1235 14:49:18.936537 Working FDT set to 1070000
1236 14:49:18.940569 Loading Kernel Image
1237 14:49:19.091957 Loading Ramdisk to 7e9a8000, end 7ffffcc6 ... OK
1238 14:49:19.100224 Loading Device Tree to 000000007e997000, end 000000007e9a75ae ... OK
1239 14:49:19.100669 Working FDT set to 7e997000
1240 14:49:19.100927
1241 14:49:19.101563 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1242 14:49:19.101942 start: 2.4.4 auto-login-action (timeout 00:03:37) [common]
1243 14:49:19.102220 Setting prompt string to ['Linux version [0-9]']
1244 14:49:19.102477 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1245 14:49:19.102727 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1246 14:49:19.103857 Starting kernel ...
1247 14:49:19.104188
1248 14:49:19.140621 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1249 14:49:19.141372 start: 2.4.4.1 login-action (timeout 00:03:37) [common]
1250 14:49:19.141821 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1251 14:49:19.142115 Setting prompt string to []
1252 14:49:19.142391 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1253 14:49:19.142638 Using line separator: #'\n'#
1254 14:49:19.142849 No login prompt set.
1255 14:49:19.143081 Parsing kernel messages
1256 14:49:19.143330 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1257 14:49:19.143763 [login-action] Waiting for messages, (timeout 00:03:37)
1258 14:49:19.144032 Waiting using forced prompt support (timeout 00:01:49)
1259 14:49:19.156970 [ 0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j363320-arm64-gcc-12-defconfig-wwd8c) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Tue Nov 5 13:41:51 UTC 2024
1260 14:49:19.162643 [ 0.000000] KASLR disabled due to lack of seed
1261 14:49:19.168136 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1262 14:49:19.173544 [ 0.000000] efi: UEFI not found.
1263 14:49:19.179176 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1264 14:49:19.184550 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1265 14:49:19.195489 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1266 14:49:19.206544 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1267 14:49:19.212086 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1268 14:49:19.223171 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1269 14:49:19.234098 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1270 14:49:19.239600 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1271 14:49:19.245143 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1272 14:49:19.250650 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1273 14:49:19.251108 [ 0.000000] Zone ranges:
1274 14:49:19.256172 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1275 14:49:19.261677 [ 0.000000] DMA32 empty
1276 14:49:19.262113 [ 0.000000] Normal empty
1277 14:49:19.267211 [ 0.000000] Movable zone start for each node
1278 14:49:19.272730 [ 0.000000] Early memory node ranges
1279 14:49:19.278304 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1280 14:49:19.283769 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1281 14:49:19.289329 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1282 14:49:19.294793 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1283 14:49:19.322154 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1284 14:49:19.327675 [ 0.000000] psci: probing for conduit method from DT.
1285 14:49:19.328175 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1286 14:49:19.333188 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1287 14:49:19.338716 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1288 14:49:19.344331 [ 0.000000] psci: SMC Calling Convention v1.1
1289 14:49:19.349775 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1290 14:49:19.355382 [ 0.000000] Detected VIPT I-cache on CPU0
1291 14:49:19.360839 [ 0.000000] CPU features: detected: ARM erratum 845719
1292 14:49:19.366350 [ 0.000000] alternatives: applying boot alternatives
1293 14:49:19.382918 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/940325/extract-nfsrootfs-v394bfrr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1294 14:49:19.394043 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1295 14:49:19.399582 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1296 14:49:19.405047 <6>[ 0.000000] Fallback order for Node 0: 0
1297 14:49:19.410553 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1298 14:49:19.416076 <6>[ 0.000000] Policy zone: DMA
1299 14:49:19.421613 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1300 14:49:19.427121 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1301 14:49:19.432566 <6>[ 0.000000] software IO TLB: area num 8.
1302 14:49:19.441607 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1303 14:49:19.488287 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1304 14:49:19.493769 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1305 14:49:19.497422 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1306 14:49:19.502858 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1307 14:49:19.508376 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1308 14:49:19.513870 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1309 14:49:19.524933 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1310 14:49:19.530451 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1311 14:49:19.535977 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1312 14:49:19.546991 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1313 14:49:19.552505 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1314 14:49:19.558038 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1315 14:49:19.563586 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1316 14:49:19.569954 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1317 14:49:19.582598 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1318 14:49:19.593609 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1319 14:49:19.599167 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1320 14:49:19.604640 <6>[ 0.008796] Console: colour dummy device 80x25
1321 14:49:19.615700 <6>[ 0.012938] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1322 14:49:19.621208 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1323 14:49:19.626728 <6>[ 0.028189] LSM: initializing lsm=capability
1324 14:49:19.632245 <6>[ 0.032728] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1325 14:49:19.637788 <6>[ 0.040210] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1326 14:49:19.643384 <6>[ 0.052300] rcu: Hierarchical SRCU implementation.
1327 14:49:19.648785 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1328 14:49:19.659879 <6>[ 0.058884] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1329 14:49:19.668510 <6>[ 0.071591] EFI services will not be available.
1330 14:49:19.669047 <6>[ 0.075242] smp: Bringing up secondary CPUs ...
1331 14:49:19.680655 <6>[ 0.077139] Detected VIPT I-cache on CPU1
1332 14:49:19.686171 <6>[ 0.077258] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1333 14:49:19.691691 <6>[ 0.078601] CPU features: detected: Spectre-v2
1334 14:49:19.697175 <6>[ 0.078616] CPU features: detected: Spectre-v4
1335 14:49:19.702695 <6>[ 0.078621] CPU features: detected: Spectre-BHB
1336 14:49:19.708247 <6>[ 0.078627] CPU features: detected: ARM erratum 858921
1337 14:49:19.713775 <6>[ 0.078636] Detected VIPT I-cache on CPU2
1338 14:49:19.719281 <6>[ 0.078709] arch_timer: Enabling local workaround for ARM erratum 858921
1339 14:49:19.724802 <6>[ 0.078726] arch_timer: CPU2: Trapping CNTVCT access
1340 14:49:19.730326 <6>[ 0.078736] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1341 14:49:19.735841 <6>[ 0.083515] Detected VIPT I-cache on CPU3
1342 14:49:19.741370 <6>[ 0.083559] arch_timer: Enabling local workaround for ARM erratum 858921
1343 14:49:19.746875 <6>[ 0.083569] arch_timer: CPU3: Trapping CNTVCT access
1344 14:49:19.752405 <6>[ 0.083577] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1345 14:49:19.757938 <6>[ 0.087635] Detected VIPT I-cache on CPU4
1346 14:49:19.763465 <6>[ 0.087683] arch_timer: Enabling local workaround for ARM erratum 858921
1347 14:49:19.768955 <6>[ 0.087692] arch_timer: CPU4: Trapping CNTVCT access
1348 14:49:19.779933 <6>[ 0.087699] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1349 14:49:19.780502 <6>[ 0.091548] Detected VIPT I-cache on CPU5
1350 14:49:19.790978 <6>[ 0.091595] arch_timer: Enabling local workaround for ARM erratum 858921
1351 14:49:19.791513 <6>[ 0.091605] arch_timer: CPU5: Trapping CNTVCT access
1352 14:49:19.802027 <6>[ 0.091612] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1353 14:49:19.802567 <6>[ 0.091724] smp: Brought up 1 node, 6 CPUs
1354 14:49:19.807648 <6>[ 0.212951] SMP: Total of 6 processors activated.
1355 14:49:19.813131 <6>[ 0.217856] CPU: All CPU(s) started at EL2
1356 14:49:19.818638 <6>[ 0.222206] CPU features: detected: 32-bit EL0 Support
1357 14:49:19.824201 <6>[ 0.227518] CPU features: detected: 32-bit EL1 Support
1358 14:49:19.829678 <6>[ 0.232864] CPU features: detected: CRC32 instructions
1359 14:49:19.835195 <6>[ 0.238269] alternatives: applying system-wide alternatives
1360 14:49:19.853035 <6>[ 0.245482] Memory: 3557440K/4012396K available (17280K kernel code, 4898K rwdata, 11880K rodata, 10432K init, 742K bss, 187792K reserved, 262144K cma-reserved)
1361 14:49:19.853595 <6>[ 0.259798] devtmpfs: initialized
1362 14:49:19.864102 <6>[ 0.268937] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1363 14:49:19.869671 <6>[ 0.273290] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1364 14:49:19.875173 <6>[ 0.284089] 21392 pages in range for non-PLT usage
1365 14:49:19.880690 <6>[ 0.284099] 512912 pages in range for PLT usage
1366 14:49:19.886203 <6>[ 0.285647] pinctrl core: initialized pinctrl subsystem
1367 14:49:19.891736 <6>[ 0.297712] DMI not present or invalid.
1368 14:49:19.897265 <6>[ 0.302017] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1369 14:49:19.902788 <6>[ 0.306764] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1370 14:49:19.913769 <6>[ 0.313528] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1371 14:49:19.919339 <6>[ 0.321631] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1372 14:49:19.924864 <6>[ 0.329122] audit: initializing netlink subsys (disabled)
1373 14:49:19.935851 <5>[ 0.334851] audit: type=2000 audit(0.256:1): state=initialized audit_enabled=0 res=1
1374 14:49:19.941420 <6>[ 0.336250] thermal_sys: Registered thermal governor 'step_wise'
1375 14:49:19.946927 <6>[ 0.342628] thermal_sys: Registered thermal governor 'power_allocator'
1376 14:49:19.952446 <6>[ 0.348889] cpuidle: using governor menu
1377 14:49:19.957989 <6>[ 0.359919] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1378 14:49:19.963490 <6>[ 0.366805] ASID allocator initialised with 65536 entries
1379 14:49:19.971831 <6>[ 0.374357] Serial: AMBA PL011 UART driver
1380 14:49:19.979678 <6>[ 0.384955] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1381 14:49:19.994743 <6>[ 0.400363] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1382 14:49:20.005788 <6>[ 0.403028] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1383 14:49:20.011367 <6>[ 0.416148] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1384 14:49:20.016865 <6>[ 0.419405] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1385 14:49:20.027876 <6>[ 0.427831] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1386 14:49:20.033449 <6>[ 0.435454] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1387 14:49:20.044424 <6>[ 0.449030] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1388 14:49:20.050011 <6>[ 0.451274] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1389 14:49:20.055510 <6>[ 0.457754] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1390 14:49:20.061035 <6>[ 0.464732] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1391 14:49:20.072054 <6>[ 0.471202] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1392 14:49:20.077630 <6>[ 0.478187] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1393 14:49:20.083114 <6>[ 0.484656] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1394 14:49:20.088667 <6>[ 0.491641] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1395 14:49:20.094152 <6>[ 0.499660] ACPI: Interpreter disabled.
1396 14:49:20.099669 <6>[ 0.505143] iommu: Default domain type: Translated
1397 14:49:20.105192 <6>[ 0.507176] iommu: DMA domain TLB invalidation policy: strict mode
1398 14:49:20.110702 <5>[ 0.513877] SCSI subsystem initialized
1399 14:49:20.116261 <6>[ 0.517820] usbcore: registered new interface driver usbfs
1400 14:49:20.121742 <6>[ 0.523234] usbcore: registered new interface driver hub
1401 14:49:20.127258 <6>[ 0.528748] usbcore: registered new device driver usb
1402 14:49:20.132782 <6>[ 0.535004] pps_core: LinuxPPS API ver. 1 registered
1403 14:49:20.138295 <6>[ 0.539169] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1404 14:49:20.143823 <6>[ 0.548489] PTP clock support registered
1405 14:49:20.149368 <6>[ 0.552730] EDAC MC: Ver: 3.0.0
1406 14:49:20.154876 <6>[ 0.556382] scmi_core: SCMI protocol bus registered
1407 14:49:20.155375 <6>[ 0.562028] FPGA manager framework
1408 14:49:20.160402 <6>[ 0.564750] Advanced Linux Sound Architecture Driver Initialized.
1409 14:49:20.165899 <6>[ 0.571712] vgaarb: loaded
1410 14:49:20.171427 <6>[ 0.574253] clocksource: Switched to clocksource arch_sys_counter
1411 14:49:20.176936 <5>[ 0.580391] VFS: Disk quotas dquot_6.6.0
1412 14:49:20.182473 <6>[ 0.584383] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1413 14:49:20.188026 <6>[ 0.591593] pnp: PnP ACPI: disabled
1414 14:49:20.193486 <6>[ 0.600048] NET: Registered PF_INET protocol family
1415 14:49:20.198994 <6>[ 0.600413] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1416 14:49:20.209996 <6>[ 0.610585] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1417 14:49:20.215656 <6>[ 0.616589] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1418 14:49:20.226589 <6>[ 0.624482] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1419 14:49:20.232173 <6>[ 0.632719] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1420 14:49:20.237688 <6>[ 0.640515] TCP: Hash tables configured (established 32768 bind 32768)
1421 14:49:20.243186 <6>[ 0.646992] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1422 14:49:20.254174 <6>[ 0.653837] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1423 14:49:20.259762 <6>[ 0.661269] NET: Registered PF_UNIX/PF_LOCAL protocol family
1424 14:49:20.265257 <6>[ 0.667356] RPC: Registered named UNIX socket transport module.
1425 14:49:20.270794 <6>[ 0.673126] RPC: Registered udp transport module.
1426 14:49:20.276299 <6>[ 0.678031] RPC: Registered tcp transport module.
1427 14:49:20.281825 <6>[ 0.682946] RPC: Registered tcp-with-tls transport module.
1428 14:49:20.287352 <6>[ 0.688639] RPC: Registered tcp NFSv4.1 backchannel transport module.
1429 14:49:20.292862 <6>[ 0.695287] PCI: CLS 0 bytes, default 64
1430 14:49:20.293364 <6>[ 0.699608] Unpacking initramfs...
1431 14:49:20.298396 <6>[ 0.705789] kvm [1]: nv: 554 coarse grained trap handlers
1432 14:49:20.303904 <6>[ 0.708967] kvm [1]: IPA Size Limit: 40 bits
1433 14:49:20.309431 <6>[ 0.714574] kvm [1]: vgic interrupt IRQ9
1434 14:49:20.314946 <6>[ 0.717298] kvm [1]: Hyp nVHE mode initialized successfully
1435 14:49:20.320463 <5>[ 0.724693] Initialise system trusted keyrings
1436 14:49:20.325981 <6>[ 0.727949] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1437 14:49:20.331530 <6>[ 0.734581] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1438 14:49:20.337029 <5>[ 0.740688] NFS: Registering the id_resolver key type
1439 14:49:20.342558 <5>[ 0.745696] Key type id_resolver registered
1440 14:49:20.348080 <5>[ 0.750052] Key type id_legacy registered
1441 14:49:20.353679 <6>[ 0.754289] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1442 14:49:20.359107 <6>[ 0.761177] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1443 14:49:20.366505 <6>[ 0.768989] 9p: Installing v9fs 9p2000 file system support
1444 14:49:20.404721 <5>[ 0.815738] Key type asymmetric registered
1445 14:49:20.410229 <5>[ 0.815776] Asymmetric key parser 'x509' registered
1446 14:49:20.421152 <6>[ 0.819644] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1447 14:49:20.421666 <6>[ 0.827163] io scheduler mq-deadline registered
1448 14:49:20.426716 <6>[ 0.831914] io scheduler kyber registered
1449 14:49:20.432265 <6>[ 0.836179] io scheduler bfq registered
1450 14:49:20.438746 <6>[ 0.843978] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1451 14:49:20.454942 <6>[ 0.862356] ledtrig-cpu: registered to indicate activity on CPUs
1452 14:49:20.487527 <6>[ 0.893695] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1453 14:49:20.507274 <6>[ 0.907173] Serial: 8250/16550 driver, 4 port<6>[ 0.911731] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1454 14:49:20.512897 <6>[ 0.921359] printk: legacy console [ttyAML0] enabled
1455 14:49:20.518422 <6>[ 0.921359] printk: legacy console [ttyAML0] enabled
1456 14:49:20.523972 <6>[ 0.926159] printk: legacy bootconsole [meson0] disabled
1457 14:49:20.529534 <6>[ 0.926159] printk: legacy bootconsole [meson0] disabled
1458 14:49:20.535054 <6>[ 0.939071] msm_serial: driver initialized
1459 14:49:20.540681 <6>[ 0.942127] SuperH (H)SCI(F) driver initialized
1460 14:49:20.541178 <6>[ 0.946637] STM32 USART driver initialized
1461 14:49:20.546147 <5>[ 0.952830] random: crng init done
1462 14:49:20.553194 <6>[ 0.958494] loop: module loaded
1463 14:49:20.553697 <6>[ 0.959776] megasas: 07.727.03.00-rc1
1464 14:49:20.558748 <6>[ 0.968675] tun: Universal TUN/TAP device driver, 1.6
1465 14:49:20.564278 <6>[ 0.969849] thunder_xcv, ver 1.0
1466 14:49:20.564780 <6>[ 0.971879] thunder_bgx, ver 1.0
1467 14:49:20.569826 <6>[ 0.975311] nicpf, ver 1.0
1468 14:49:20.575363 <6>[ 0.979926] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1469 14:49:20.580966 <6>[ 0.985696] hns3: Copyright (c) 2017 Huawei Corporation.
1470 14:49:20.586453 <6>[ 0.991286] hclge is initializing
1471 14:49:20.592020 <6>[ 0.994826] e1000: Intel(R) PRO/1000 Network Driver
1472 14:49:20.597563 <6>[ 0.999905] e1000: Copyright (c) 1999-2006 Intel Corporation.
1473 14:49:20.603089 <6>[ 1.005928] e1000e: Intel(R) PRO/1000 Network Driver
1474 14:49:20.608699 <6>[ 1.011084] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1475 14:49:20.614204 <6>[ 1.017268] igb: Intel(R) Gigabit Ethernet Network Driver
1476 14:49:20.619737 <6>[ 1.022870] igb: Copyright (c) 2007-2014 Intel Corporation.
1477 14:49:20.625313 <6>[ 1.028707] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1478 14:49:20.630829 <6>[ 1.035186] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1479 14:49:20.636378 <6>[ 1.041938] sky2: driver version 1.30
1480 14:49:20.641928 <6>[ 1.047107] VFIO - User Level meta-driver version: 0.3
1481 14:49:20.647469 <6>[ 1.054600] usbcore: registered new interface driver usb-storage
1482 14:49:20.653403 <6>[ 1.060768] i2c_dev: i2c /dev entries driver
1483 14:49:20.666236 <6>[ 1.071809] sdhci: Secure Digital Host Controller Interface driver
1484 14:49:20.666739 <6>[ 1.072611] sdhci: Copyright(c) Pierre Ossman
1485 14:49:20.677316 <6>[ 1.078344] Synopsys Designware Multimedia Card Interface Driver
1486 14:49:20.682930 <6>[ 1.084877] sdhci-pltfm: SDHCI platform and OF driver helper
1487 14:49:20.683430 <6>[ 1.092531] meson-sm: secure-monitor enabled
1488 14:49:20.695749 <6>[ 1.095102] usbcore: registered new interface driver usbhid
1489 14:49:20.696291 <6>[ 1.099678] usbhid: USB HID core driver
1490 14:49:20.703334 <6>[ 1.114425] NET: Registered PF_PACKET protocol family
1491 14:49:20.708872 <6>[ 1.114518] 9pnet: Installing 9P2000 support
1492 14:49:20.715951 <5>[ 1.118662] Key type dns_resolver registered
1493 14:49:20.721506 <6>[ 1.130226] registered taskstats version 1
1494 14:49:20.727032 <5>[ 1.130401] Loading compiled-in X.509 certificates
1495 14:49:20.730628 <6>[ 1.139071] Demotion targets for Node 0: null
1496 14:49:20.757366 <6>[ 1.168430] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1497 14:49:20.762899 <6>[ 1.168470] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1498 14:49:20.773945 <4>[ 1.177614] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1499 14:49:20.779542 <4>[ 1.181221] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1500 14:49:20.785093 <6>[ 1.188744] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1501 14:49:20.790731 <6>[ 1.198022] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1502 14:49:20.801706 <6>[ 1.201545] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1503 14:49:20.812820 <6>[ 1.209503] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1504 14:49:20.818381 <6>[ 1.219030] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1505 14:49:20.823887 <6>[ 1.225265] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1506 14:49:20.829498 <6>[ 1.230876] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1507 14:49:20.835008 <6>[ 1.238760] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1508 14:49:20.840543 <6>[ 1.246031] hub 1-0:1.0: USB hub found
1509 14:49:20.846089 <6>[ 1.249528] hub 1-0:1.0: 2 ports detected
1510 14:49:20.851741 <6>[ 1.255664] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1511 14:49:20.857188 <6>[ 1.262513] hub 2-0:1.0: USB hub found
1512 14:49:20.862258 <6>[ 1.266062] hub 2-0:1.0: 1 port detected
1513 14:49:20.883207 <6>[ 1.291732] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1514 14:49:20.895795 <6>[ 1.303581] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1515 14:49:20.929979 <6>[ 1.337422] Trying to probe devices needed for running init ...
1516 14:49:21.095482 <6>[ 1.502287] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1517 14:49:21.244138 <6>[ 1.649649] mmc0: new ultra high speed SDR104 SDXC card at address e624
1518 14:49:21.250402 <6>[ 1.651438] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1519 14:49:21.250928 <6>[ 1.657274] mmcblk0: p1
1520 14:49:21.266570 <6>[ 1.675816] Freeing initrd memory: 22876K
1521 14:49:21.282827 <6>[ 1.693870] hub 1-1:1.0: USB hub found
1522 14:49:21.288537 <6>[ 1.694168] hub 1-1:1.0: 4 ports detected
1523 14:49:21.359577 <6>[ 1.766391] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1524 14:49:21.411428 <6>[ 1.822471] hub 2-1:1.0: USB hub found
1525 14:49:21.417146 <6>[ 1.823296] hub 2-1:1.0: 4 ports detected
1526 14:49:33.204102 <6>[ 13.614346] clk: Disabling unused clocks
1527 14:49:33.209441 <6>[ 13.614592] PM: genpd: Disabling unused power domains
1528 14:49:33.217197 <6>[ 13.618237] ALSA device list:
1529 14:49:33.217667 <6>[ 13.621401] No soundcards found.
1530 14:49:33.224263 <6>[ 13.635264] Freeing unused kernel memory: 10432K
1531 14:49:33.230627 <6>[ 13.635393] Run /init as init process
1532 14:49:33.236282 Loading, please wait...
1533 14:49:33.276373 Starting systemd-udevd version 252.22-1~deb12u1
1534 14:49:33.729404 <6>[ 14.138234] mc: Linux media interface: v0.10
1535 14:49:33.746109 <6>[ 14.157142] Registered IR keymap rc-empty
1536 14:49:33.757168 <6>[ 14.157269] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1537 14:49:33.760679 <6>[ 14.165986] videodev: Linux video capture interface: v2.00
1538 14:49:33.771616 <6>[ 14.175902] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1539 14:49:33.772131 <6>[ 14.179994] rc rc0: sw decoder init
1540 14:49:33.777255 <6>[ 14.182714] meson-ir ff808000.ir: receiver initialized
1541 14:49:33.782846 <6>[ 14.183950] panfrost ffe40000.gpu: clock rate = 24000000
1542 14:49:33.793869 <3>[ 14.193632] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1543 14:49:33.799468 <6>[ 14.203648] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1544 14:49:33.810624 <4>[ 14.203691] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1545 14:49:33.816107 <6>[ 14.204851] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1546 14:49:33.827098 <6>[ 14.204867] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1547 14:49:33.838158 <6>[ 14.204876] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1548 14:49:33.843778 <6>[ 14.204885] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1549 14:49:33.849314 <6>[ 14.206993] meson-vrtc ff8000a8.rtc: registered as rtc0
1550 14:49:33.854855 <6>[ 14.207033] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1551 14:49:33.865907 <6>[ 14.270299] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1552 14:49:33.871507 <6>[ 14.270371] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1553 14:49:33.877040 <6>[ 14.272705] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1554 14:49:33.888116 <3>[ 14.277598] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1555 14:49:33.893679 <6>[ 14.293832] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1556 14:49:33.899221 <6>[ 14.300083] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1557 14:49:33.904767 <6>[ 14.306921] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1558 14:49:33.910309 <6>[ 14.313586] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1559 14:49:33.915910 <6>[ 14.319066] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1560 14:49:33.926908 <6>[ 14.326739] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1561 14:49:33.932499 <6>[ 14.334448] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1562 14:49:33.943558 <6>[ 14.334737] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1563 14:49:33.949137 <6>[ 14.339909] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1564 14:49:33.954695 <6>[ 14.339915] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1565 14:49:33.960264 <6>[ 14.350839] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1566 14:49:33.971285 <4>[ 14.364423] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1567 14:49:33.982364 <6>[ 14.370331] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1568 14:49:33.987825 <6>[ 14.370401] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1569 14:49:33.993351 <6>[ 14.370411] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1570 14:49:34.004530 <6>[ 14.403708] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1571 14:49:34.010164 <3>[ 14.411773] meson-drm ff900000.vpu: DSI transceiver device is disabled
1572 14:49:34.015699 <6>[ 14.418760] usbcore: registered new device driver onboard-usb-dev
1573 14:49:34.021263 <6>[ 14.419236] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1574 14:49:34.026751 <6>[ 14.432015] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1575 14:49:34.045556 <6>[ 14.448194] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1576 14:49:34.219885 <6>[ 14.607010] Console: switching to colour frame buffer device 128x48
1577 14:49:34.225761 <6>[ 14.626374] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1578 14:49:34.466730 <6>[ 14.877870] hub 1-1:1.0: USB hub found
1579 14:49:34.472394 <6>[ 14.878178] hub 1-1:1.0: 4 ports detected
1580 14:49:34.612570 <4>[ 15.018271] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1581 14:49:34.618096 <3>[ 15.020639] onboard-usb-dev 1-1: Failed to suspend device, error -32
1582 14:49:34.625081 <3>[ 15.027067] onboard-usb-dev 1-1: can't set config #1, error -71
1583 14:49:34.640580 <4>[ 15.046313] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1584 14:49:34.646136 <3>[ 15.048649] onboard-usb-dev 1-1: Failed to suspend device, error -32
1585 14:49:34.651682 <6>[ 15.048685] onboard-usb-dev 1-1: USB disconnect, device number 2
1586 14:49:34.657219 Begin: Loading essential drivers ... done.
1587 14:49:34.662760 Begin: Running /scripts/init-premount ... done.
1588 14:49:34.668304 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1589 14:49:34.673873 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1590 14:49:34.680511 Device /sys/class/net/end0 found
1591 14:49:34.680919 done.
1592 14:49:34.697395 Begin: Waiting up to 180 secs for any network device to become available ... done.
1593 14:49:34.742333 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.143463] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1594 14:49:34.742849
1595 14:49:34.831451 <6>[ 15.234372] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=32)
1596 14:49:34.845475 <6>[ 15.251070] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1597 14:49:34.851104 <6>[ 15.253257] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1598 14:49:34.860228 <6>[ 15.260606] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1599 14:49:34.907425 <6>[ 15.314291] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1600 14:49:35.075029 <6>[ 15.485977] hub 1-1:1.0: USB hub found
1601 14:49:35.080544 <6>[ 15.486496] hub 1-1:1.0: 4 ports detected
1602 14:49:35.239102 <6>[ 15.645812] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1603 14:49:35.511279 <6>[ 15.918038] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1604 14:49:36.297819 IP-Config: no response after 2 secs - giving up
1605 14:49:36.363039 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1606 14:49:37.059327 <4>[ 17.470272] rc rc0: two consecutive events of type space
1607 14:49:37.810631 <6>[ 18.215683] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1608 14:49:38.472506 IP-Config: end0 guessed broadcast address 192.168.6.255
1609 14:49:38.478007 IP-Config: end0 complete (dhcp from 192.168.6.1):
1610 14:49:38.483535 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1611 14:49:38.494624 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1612 14:49:38.495170 rootserver: 192.168.6.1 rootpath:
1613 14:49:38.498071 filename :
1614 14:49:38.618439 done.
1615 14:49:38.628918 Begin: Running /scripts/nfs-bottom ... done.
1616 14:49:38.643461 Begin: Running /scripts/init-bottom ... done.
1617 14:49:38.967097 <30>[ 19.373635] systemd[1]: System time before build time, advancing clock.
1618 14:49:39.031016 <6>[ 19.441961] NET: Registered PF_INET6 protocol family
1619 14:49:39.036574 <6>[ 19.444434] Segment Routing with IPv6
1620 14:49:39.041797 <6>[ 19.445463] In-situ OAM (IOAM) with IPv6
1621 14:49:39.116935 <30>[ 19.500284] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1622 14:49:39.122616 <30>[ 19.527778] systemd[1]: Detected architecture arm64.
1623 14:49:39.123131
1624 14:49:39.129961 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1625 14:49:39.130449
1626 14:49:39.148964 <30>[ 19.556095] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1627 14:49:39.842527 <30>[ 20.248630] systemd[1]: Queued start job for default target graphical.target.
1628 14:49:39.887081 <30>[ 20.292632] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1629 14:49:39.895718 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1630 14:49:39.906782 <30>[ 20.311233] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1631 14:49:39.914057 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1632 14:49:39.925790 <30>[ 20.331364] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1633 14:49:39.939254 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1634 14:49:39.944625 <30>[ 20.351013] systemd[1]: Created slice user.slice - User and Session Slice.
1635 14:49:39.951052 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1636 14:49:39.962195 <30>[ 20.366524] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1637 14:49:39.973726 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1638 14:49:39.984767 <30>[ 20.386460] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1639 14:49:39.991393 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1640 14:49:40.013519 <30>[ 20.406440] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1641 14:49:40.019138 <30>[ 20.420502] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1642 14:49:40.026797 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1643 14:49:40.037847 <30>[ 20.442354] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1644 14:49:40.045017 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1645 14:49:40.060770 <30>[ 20.466364] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1646 14:49:40.074495 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1647 14:49:40.080094 <30>[ 20.486394] systemd[1]: Reached target paths.target - Path Units.
1648 14:49:40.088515 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1649 14:49:40.094027 <30>[ 20.502362] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1650 14:49:40.105739 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1651 14:49:40.111358 <30>[ 20.518350] systemd[1]: Reached target slices.target - Slice Units.
1652 14:49:40.119435 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1653 14:49:40.124958 <30>[ 20.534361] systemd[1]: Reached target swap.target - Swaps.
1654 14:49:40.132831 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1655 14:49:40.144786 <30>[ 20.550381] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1656 14:49:40.153671 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1657 14:49:40.168921 <30>[ 20.574542] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1658 14:49:40.178149 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1659 14:49:40.191070 <30>[ 20.596701] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1660 14:49:40.199852 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1661 14:49:40.213655 <30>[ 20.619259] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1662 14:49:40.223049 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1663 14:49:40.237089 <30>[ 20.642688] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1664 14:49:40.244466 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1665 14:49:40.257734 <30>[ 20.663305] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1666 14:49:40.266854 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1667 14:49:40.278723 <30>[ 20.684330] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1668 14:49:40.284420 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1669 14:49:40.296999 <30>[ 20.702604] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1670 14:49:40.305531 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1671 14:49:40.344869 <30>[ 20.750461] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1672 14:49:40.351643 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1673 14:49:40.363436 <30>[ 20.769025] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1674 14:49:40.371014 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1675 14:49:40.383473 <30>[ 20.789047] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1676 14:49:40.391291 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1677 14:49:40.407842 <30>[ 20.806690] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1678 14:49:40.418953 <30>[ 20.819822] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1679 14:49:40.424854 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1680 14:49:40.473099 <30>[ 20.878684] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1681 14:49:40.481069 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1682 14:49:40.495538 <30>[ 20.901151] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1683 14:49:40.503205 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1684 14:49:40.516550 <30>[ 20.922132] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1685 14:49:40.532552 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel <6>[ 20.932342] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1686 14:49:40.533058 Module drm...
1687 14:49:40.543601 <30>[ 20.949204] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1688 14:49:40.551955 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1689 14:49:40.563023 <30>[ 20.968623] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1690 14:49:40.570327 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1691 14:49:40.579784 <6>[ 20.990883] fuse: init (API version 7.41)
1692 14:49:40.590824 <30>[ 20.993132] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1693 14:49:40.594805 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1694 14:49:40.645066 <30>[ 21.050665] systemd[1]: Starting systemd-journald.service - Journal Service...
1695 14:49:40.651505 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1696 14:49:40.667473 <30>[ 21.073070] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1697 14:49:40.675023 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1698 14:49:40.690671 <30>[ 21.096243] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1699 14:49:40.700048 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1700 14:49:40.723038 <30>[ 21.128645] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1701 14:49:40.731836 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1702 14:49:40.756094 <30>[ 21.161638] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1703 14:49:40.764134 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1704 14:49:40.782228 <30>[ 21.187813] systemd[1]: Started systemd-journald.service - Journal Service.
1705 14:49:40.789102 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1706 14:49:40.802314 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1707 14:49:40.817567 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1708 14:49:40.829548 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1709 14:49:40.841754 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1710 14:49:40.854088 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1711 14:49:40.865940 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1712 14:49:40.877673 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1713 14:49:40.889999 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1714 14:49:40.901789 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1715 14:49:40.921832 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1716 14:49:40.941967 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1717 14:49:40.957756 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1718 14:49:40.973820 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1719 14:49:40.990073 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1720 14:49:41.028543 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1721 14:49:41.038865 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1722 14:49:41.050305 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1723 14:49:41.066992 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1724 14:49:41.080634 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1725 14:49:41.097086 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1726 14:49:41.104454 <46>[ 21.509876] systemd-journald[229]: Received client request to flush runtime journal.
1727 14:49:41.118010 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1728 14:49:41.129664 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1729 14:49:41.141500 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1730 14:49:41.157907 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1731 14:49:41.174035 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1732 14:49:41.228662 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1733 14:49:41.276653 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1734 14:49:41.366303 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1735 14:49:41.385467 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1736 14:49:41.392981 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1737 14:49:41.408783 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1738 14:49:41.456855 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1739 14:49:41.471077 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1740 14:49:41.666724 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1741 14:49:41.717126 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1742 14:49:41.738121 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1743 14:49:41.824258 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1744 14:49:41.873665 <5>[ 22.279284] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1745 14:49:41.896708 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1746 14:49:41.915711 Starting [0;1;39msystemd-update-ut…rd System Boot/Shu<5>[ 22.317322] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1747 14:49:41.921297 <5>[ 22.322562] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1748 14:49:41.932346 <4>[ 22.331307] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1749 14:49:41.932865 <6>[ 22.338409] cfg80211: failed to load regulatory.db
1750 14:49:41.936683 tdown in UTMP...
1751 14:49:42.000977 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1752 14:49:42.018140 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1753 14:49:42.034000 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1754 14:49:42.045786 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1755 14:49:42.066732 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1756 14:49:42.090857 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1757 14:49:42.104516 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1758 14:49:42.136343 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1759 14:49:42.150779 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1760 14:49:42.167431 <46>[ 22.559960] systemd-journald[229]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1761 14:49:42.183060 <46>[ 22.576163] systemd-journald[229]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1762 14:49:42.198664 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1763 14:49:42.217413 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1764 14:49:42.230295 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1765 14:49:42.309470 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1766 14:49:42.316287 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1767 14:49:42.338451 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1768 14:49:42.377102 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1769 14:49:42.389627 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1770 14:49:42.449252 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1771 14:49:42.464931 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1772 14:49:42.473742 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1773 14:49:42.491491 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1774 14:49:42.499586 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1775 14:49:42.508149 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1776 14:49:42.515829 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1777 14:49:42.560624 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1778 14:49:42.570662 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1779 14:49:42.592662 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1780 14:49:42.611488 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1781 14:49:42.623064 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1782 14:49:42.637313 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1783 14:49:42.644701 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1784 14:49:42.663481 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1785 14:49:42.669979 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1786 14:49:42.683497 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1787 14:49:42.698641 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1788 14:49:42.704802 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1789 14:49:42.725219 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1790 14:49:42.742068 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1791 14:49:42.757484 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1792 14:49:42.773083 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1793 14:49:42.816888 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1794 14:49:42.853902 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1795 14:49:42.893984
1796 14:49:42.894683 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1797 14:49:42.895197
1798 14:49:42.901009 debian-bookworm-arm64 login: root (automatic login)
1799 14:49:42.901564
1800 14:49:43.092768 Linux debian-bookworm-arm64 6.12.0-rc2 #1 SMP PREEMPT Tue Nov 5 13:41:51 UTC 2024 aarch64
1801 14:49:43.093230
1802 14:49:43.098331 The programs included with the Debian GNU/Linux system are free software;
1803 14:49:43.103913 the exact distribution terms for each program are described in the
1804 14:49:43.109450 individual files in /usr/share/doc/*/copyright.
1805 14:49:43.109804
1806 14:49:43.114933 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1807 14:49:43.117173 permitted by applicable law.
1808 14:49:43.742764 Matched prompt #10: / #
1810 14:49:43.744340 Setting prompt string to ['/ #']
1811 14:49:43.744888 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1813 14:49:43.746249 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1814 14:49:43.746778 start: 2.4.5 expect-shell-connection (timeout 00:03:13) [common]
1815 14:49:43.747207 Setting prompt string to ['/ #']
1816 14:49:43.747606 Forcing a shell prompt, looking for ['/ #']
1818 14:49:43.798611 / #
1819 14:49:43.799431 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1820 14:49:43.799892 Waiting using forced prompt support (timeout 00:02:30)
1821 14:49:43.805008
1822 14:49:43.805788 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1823 14:49:43.806330 start: 2.4.6 export-device-env (timeout 00:03:13) [common]
1824 14:49:43.806794 Sending with 10 millisecond of delay
1826 14:49:48.793682 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/940325/extract-nfsrootfs-v394bfrr'
1827 14:49:48.804614 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/940325/extract-nfsrootfs-v394bfrr'
1828 14:49:48.805381 Sending with 10 millisecond of delay
1830 14:49:50.902984 / # export NFS_SERVER_IP='192.168.6.2'
1831 14:49:50.913883 export NFS_SERVER_IP='192.168.6.2'
1832 14:49:50.914739 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1833 14:49:50.915331 end: 2.4 uboot-commands (duration 00:01:54) [common]
1834 14:49:50.915924 end: 2 uboot-action (duration 00:01:54) [common]
1835 14:49:50.916555 start: 3 lava-test-retry (timeout 00:06:46) [common]
1836 14:49:50.917136 start: 3.1 lava-test-shell (timeout 00:06:46) [common]
1837 14:49:50.917609 Using namespace: common
1839 14:49:51.018762 / # #
1840 14:49:51.019440 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1841 14:49:51.024245 #
1842 14:49:51.024985 Using /lava-940325
1844 14:49:51.126147 / # export SHELL=/bin/bash
1845 14:49:51.131553 export SHELL=/bin/bash
1847 14:49:51.232971 / # . /lava-940325/environment
1848 14:49:51.237548 . /lava-940325/environment
1850 14:49:51.342286 / # /lava-940325/bin/lava-test-runner /lava-940325/0
1851 14:49:51.342908 Test shell timeout: 10s (minimum of the action and connection timeout)
1852 14:49:51.346793 /lava-940325/bin/lava-test-runner /lava-940325/0
1853 14:49:51.555533 + export TESTRUN_ID=0_timesync-off
1854 14:49:51.563109 + TESTRUN_ID=0_timesync-off
1855 14:49:51.563614 + cd /lava-940325/0/tests/0_timesync-off
1856 14:49:51.564084 ++ cat uuid
1857 14:49:51.568632 + UUID=940325_1.6.2.4.1
1858 14:49:51.569083 + set +x
1859 14:49:51.576625 <LAVA_SIGNAL_STARTRUN 0_timesync-off 940325_1.6.2.4.1>
1860 14:49:51.577082 + systemctl stop systemd-timesyncd
1861 14:49:51.577783 Received signal: <STARTRUN> 0_timesync-off 940325_1.6.2.4.1
1862 14:49:51.578229 Starting test lava.0_timesync-off (940325_1.6.2.4.1)
1863 14:49:51.578763 Skipping test definition patterns.
1864 14:49:51.614283 + set +x
1865 14:49:51.614775 <LAVA_SIGNAL_ENDRUN 0_timesync-off 940325_1.6.2.4.1>
1866 14:49:51.615437 Received signal: <ENDRUN> 0_timesync-off 940325_1.6.2.4.1
1867 14:49:51.615918 Ending use of test pattern.
1868 14:49:51.616365 Ending test lava.0_timesync-off (940325_1.6.2.4.1), duration 0.04
1870 14:49:51.700371 + export TESTRUN_ID=1_kselftest-alsa
1871 14:49:51.708707 + TESTRUN_ID=1_kselftest-alsa
1872 14:49:51.709172 + cd /lava-940325/0/tests/1_kselftest-alsa
1873 14:49:51.709602 ++ cat uuid
1874 14:49:51.717194 + UUID=940325_1.6.2.4.5
1875 14:49:51.717652 + set +x
1876 14:49:51.722748 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 940325_1.6.2.4.5>
1877 14:49:51.723197 + cd ./automated/linux/kselftest/
1878 14:49:51.723880 Received signal: <STARTRUN> 1_kselftest-alsa 940325_1.6.2.4.5
1879 14:49:51.724366 Starting test lava.1_kselftest-alsa (940325_1.6.2.4.5)
1880 14:49:51.724863 Skipping test definition patterns.
1881 14:49:51.752833 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-60-ge38568da5f05b/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g broonie-spi -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1882 14:49:51.795345 INFO: install_deps skipped
1883 14:49:51.938530 --2024-11-05 14:49:51-- http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-60-ge38568da5f05b/arm64/defconfig/gcc-12/kselftest.tar.xz
1884 14:49:52.210824 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1885 14:49:52.353452 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1886 14:49:52.494630 HTTP request sent, awaiting response... 200 OK
1887 14:49:52.495158 Length: 6924096 (6.6M) [application/octet-stream]
1888 14:49:52.500045 Saving to: 'kselftest_armhf.tar.gz'
1889 14:49:52.500510
1890 14:49:53.647297
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 49.92K 180KB/s
kselftest_armhf.tar 3%[ ] 218.67K 393KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.05MB/s
kselftest_armhf.tar 53%[=========> ] 3.51M 3.15MB/s
kselftest_armhf.tar 100%[===================>] 6.60M 5.75MB/s in 1.1s
1891 14:49:53.648300
1892 14:49:53.743668 2024-11-05 14:49:53 (5.75 MB/s) - 'kselftest_armhf.tar.gz' saved [6924096/6924096]
1893 14:49:53.744336
1894 14:50:02.867233 skiplist:
1895 14:50:02.867722 ========================================
1896 14:50:02.872854 ========================================
1897 14:50:02.915638 alsa:mixer-test
1898 14:50:02.916056 alsa:pcm-test
1899 14:50:02.916305 alsa:test-pcmtest-driver
1900 14:50:02.919677 alsa:utimer-test
1901 14:50:02.932708 ============== Tests to run ===============
1902 14:50:02.932992 alsa:mixer-test
1903 14:50:02.938202 alsa:pcm-test
1904 14:50:02.938472 alsa:test-pcmtest-driver
1905 14:50:02.938689 alsa:utimer-test
1906 14:50:02.945457 ===========End Tests to run ===============
1907 14:50:02.945767 shardfile-alsa pass
1908 14:50:03.052441 <12>[ 43.461474] kselftest: Running tests in alsa
1909 14:50:03.056779 TAP version 13
1910 14:50:03.068603 1..4
1911 14:50:03.091794 # timeout set to 45
1912 14:50:03.092096 # selftests: alsa: mixer-test
1913 14:50:03.251076 # TAP version 13
1914 14:50:03.251497 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1915 14:50:03.256386 # 1..427
1916 14:50:03.256646 # ok 1 get_value.LCALTA.60
1917 14:50:03.256862 # # LCALTA.60 TDMOUT_A SRC SEL
1918 14:50:03.261922 # ok 2 name.LCALTA.60
1919 14:50:03.262179 # ok 3 write_default.LCALTA.60
1920 14:50:03.267541 # ok 4 write_valid.LCALTA.60
1921 14:50:03.267797 # ok 5 write_invalid.LCALTA.60
1922 14:50:03.273056 # ok 6 event_missing.LCALTA.60
1923 14:50:03.273303 # ok 7 event_spurious.LCALTA.60
1924 14:50:03.278641 # ok 8 get_value.LCALTA.59
1925 14:50:03.278903 # # LCALTA.59 TDMOUT_B SRC SEL
1926 14:50:03.284147 # ok 9 name.LCALTA.59
1927 14:50:03.284409 # ok 10 write_default.LCALTA.59
1928 14:50:03.289701 # ok 11 write_valid.LCALTA.59
1929 14:50:03.289992 # ok 12 write_invalid.LCALTA.59
1930 14:50:03.295205 # ok 13 event_missing.LCALTA.59
1931 14:50:03.295539 # ok 14 event_spurious.LCALTA.59
1932 14:50:03.300696 # ok 15 get_value.LCALTA.58
1933 14:50:03.300953 # # LCALTA.58 TDMOUT_C SRC SEL
1934 14:50:03.306243 # ok 16 name.LCALTA.58
1935 14:50:03.306539 # ok 17 write_default.LCALTA.58
1936 14:50:03.311796 # ok 18 write_valid.LCALTA.58
1937 14:50:03.312206 # ok 19 write_invalid.LCALTA.58
1938 14:50:03.317382 # ok 20 event_missing.LCALTA.58
1939 14:50:03.317826 # ok 21 event_spurious.LCALTA.58
1940 14:50:03.322914 # ok 22 get_value.LCALTA.57
1941 14:50:03.323347 # # LCALTA.57 TDMIN_A SRC SEL
1942 14:50:03.323751 # ok 23 name.LCALTA.57
1943 14:50:03.328457 # ok 24 write_default.LCALTA.57
1944 14:50:03.328893 # ok 25 write_valid.LCALTA.57
1945 14:50:03.334024 # ok 26 write_invalid.LCALTA.57
1946 14:50:03.334511 # ok 27 event_missing.LCALTA.57
1947 14:50:03.339576 # ok 28 event_spurious.LCALTA.57
1948 14:50:03.340089 # ok 29 get_value.LCALTA.56
1949 14:50:03.345144 # # LCALTA.56 TDMIN_B SRC SEL
1950 14:50:03.345584 # ok 30 name.LCALTA.56
1951 14:50:03.361809 # ok 31 write_default.LCALTA.56<3>[ 43.759685] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1952 14:50:03.362329
1953 14:50:03.362739 # ok 32 write_valid.LCALTA.56
1954 14:50:03.367337 # ok 33 write_invalid.LCALTA.56
1955 14:50:03.367781 # ok 34 event_missing.LCALTA.56
1956 14:50:03.372855 # ok 35 event_spurious.LCALTA.56
1957 14:50:03.373295 # ok 36 get_value.LCALTA.55
1958 14:50:03.378432 # # LCALTA.55 TDMIN_C SRC SEL
1959 14:50:03.378865 # ok 37 name.LCALTA.55
1960 14:50:03.383964 # ok 38 write_default.LCALTA.55
1961 14:50:03.384426 # ok 39 write_valid.LCALTA.55
1962 14:50:03.389504 # ok 40 write_invalid.LCALTA.55
1963 14:50:03.389943 # ok 41 event_missing.LCALTA.55
1964 14:50:03.395055 # ok 42 event_spurious.LCALTA.55
1965 14:50:03.395481 # ok 43 get_value.LCALTA.54
1966 14:50:03.400595 # # LCALTA.54 ACODEC Left DAC Sel
1967 14:50:03.401027 # ok 44 name.LCALTA.54
1968 14:50:03.406141 # ok 45 write_default.LCALTA.54
1969 14:50:03.406574 # ok 46 write_valid.LCALTA.54
1970 14:50:03.411675 # ok 47 write_invalid.LCALTA.54
1971 14:50:03.412129 # ok 48 event_missing.LCALTA.54
1972 14:50:03.417244 # ok 49 event_spurious.LCALTA.54
1973 14:50:03.417676 # ok 50 get_value.LCALTA.53
1974 14:50:03.422786 # # LCALTA.53 ACODEC Right DAC Sel
1975 14:50:03.423221 # ok 51 name.LCALTA.53
1976 14:50:03.428317 # ok 52 write_default.LCALTA.53
1977 14:50:03.428747 # ok 53 write_valid.LCALTA.53
1978 14:50:03.433865 # ok 54 write_invalid.LCALTA.53
1979 14:50:03.434298 # ok 55 event_missing.LCALTA.53
1980 14:50:03.439386 # ok 56 event_spurious.LCALTA.53
1981 14:50:03.439823 # ok 57 get_value.LCALTA.52
1982 14:50:03.444945 # # LCALTA.52 TOACODEC OUT EN Switch
1983 14:50:03.445379 # ok 58 name.LCALTA.52
1984 14:50:03.450487 # ok 59 write_default.LCALTA.52
1985 14:50:03.450918 # ok 60 write_valid.LCALTA.52
1986 14:50:03.456037 # ok 61 write_invalid.LCALTA.52
1987 14:50:03.456468 # ok 62 event_missing.LCALTA.52
1988 14:50:03.461585 # ok 63 event_spurious.LCALTA.52
1989 14:50:03.462011 # ok 64 get_value.LCALTA.51
1990 14:50:03.467117 # # LCALTA.51 TOACODEC SRC
1991 14:50:03.467546 # ok 65 name.LCALTA.51
1992 14:50:03.472670 # ok 66 write_default.LCALTA.51
1993 14:50:03.473094 # ok 67 write_valid.LCALTA.51
1994 14:50:03.478213 # ok 68 write_invalid.LCALTA.51
1995 14:50:03.478640 # ok 69 event_missing.LCALTA.51
1996 14:50:03.483804 # ok 70 event_spurious.LCALTA.51
1997 14:50:03.484276 # ok 71 get_value.LCALTA.50
1998 14:50:03.489330 # # LCALTA.50 TOHDMITX SPDIF SRC
1999 14:50:03.489758 # ok 72 name.LCALTA.50
2000 14:50:03.490155 # ok 73 write_default.LCALTA.50
2001 14:50:03.494845 # ok 74 write_valid.LCALTA.50
2002 14:50:03.495273 # ok 75 write_invalid.LCALTA.50
2003 14:50:03.500380 # ok 76 event_missing.LCALTA.50
2004 14:50:03.505957 # ok 77 event_spurious.LCALTA.50
2005 14:50:03.506387 # ok 78 get_value.LCALTA.49
2006 14:50:03.506787 # # LCALTA.49 TOHDMITX Switch
2007 14:50:03.511491 # ok 79 name.LCALTA.49
2008 14:50:03.511924 # ok 80 write_default.LCALTA.49
2009 14:50:03.517057 # ok 81 write_valid.LCALTA.49
2010 14:50:03.517493 # ok 82 write_invalid.LCALTA.49
2011 14:50:03.522589 # ok 83 event_missing.LCALTA.49
2012 14:50:03.523016 # ok 84 event_spurious.LCALTA.49
2013 14:50:03.528167 # ok 85 get_value.LCALTA.48
2014 14:50:03.528616 # # LCALTA.48 TOHDMITX I2S SRC
2015 14:50:03.533714 # ok 86 name.LCALTA.48
2016 14:50:03.534147 # ok 87 write_default.LCALTA.48
2017 14:50:03.539243 # ok 88 write_valid.LCALTA.48
2018 14:50:03.539672 # ok 89 write_invalid.LCALTA.48
2019 14:50:03.544794 # ok 90 event_missing.LCALTA.48
2020 14:50:03.545227 # ok 91 event_spurious.LCALTA.48
2021 14:50:03.550313 # ok 92 get_value.LCALTA.47
2022 14:50:03.550755 # # LCALTA.47 TODDR_C SRC SEL
2023 14:50:03.555877 # ok 93 name.LCALTA.47
2024 14:50:03.556331 # ok 94 write_default.LCALTA.47
2025 14:50:03.561435 # ok 95 write_valid.LCALTA.47
2026 14:50:03.561867 # ok 96 write_invalid.LCALTA.47
2027 14:50:03.566965 # ok 97 event_missing.LCALTA.47
2028 14:50:03.567396 # ok 98 event_spurious.LCALTA.47
2029 14:50:03.572528 # ok 99 get_value.LCALTA.46
2030 14:50:03.572986 # # LCALTA.46 TODDR_B SRC SEL
2031 14:50:03.573390 # ok 100 name.LCALTA.46
2032 14:50:03.578065 # ok 101 write_default.LCALTA.46
2033 14:50:03.583608 # ok 102 write_valid.LCALTA.46
2034 14:50:03.584081 # ok 103 write_invalid.LCALTA.46
2035 14:50:03.589244 # ok 104 event_missing.LCALTA.46
2036 14:50:03.589676 # ok 105 event_spurious.LCALTA.46
2037 14:50:03.594783 # ok 106 get_value.LCALTA.45
2038 14:50:03.595214 # # LCALTA.45 TODDR_A SRC SEL
2039 14:50:03.595615 # ok 107 name.LCALTA.45
2040 14:50:03.600306 # ok 108 write_default.LCALTA.45
2041 14:50:03.605844 # ok 109 write_valid.LCALTA.45
2042 14:50:03.606272 # ok 110 write_invalid.LCALTA.45
2043 14:50:03.611385 # ok 111 event_missing.LCALTA.45
2044 14:50:03.611832 # ok 112 event_spurious.LCALTA.45
2045 14:50:03.616924 # ok 113 get_value.LCALTA.44
2046 14:50:03.617359 # # LCALTA.44 FRDDR_C SINK 3 SEL
2047 14:50:03.622516 # ok 114 name.LCALTA.44
2048 14:50:03.622945 # ok 115 write_default.LCALTA.44
2049 14:50:03.628025 # ok 116 write_valid.LCALTA.44
2050 14:50:03.628458 # ok 117 write_invalid.LCALTA.44
2051 14:50:03.633551 # ok 118 event_missing.LCALTA.44
2052 14:50:03.633980 # ok 119 event_spurious.LCALTA.44
2053 14:50:03.639069 # ok 120 get_value.LCALTA.43
2054 14:50:03.639504 # # LCALTA.43 FRDDR_C SINK 2 SEL
2055 14:50:03.644610 # ok 121 name.LCALTA.43
2056 14:50:03.645043 # ok 122 write_default.LCALTA.43
2057 14:50:03.650183 # ok 123 write_valid.LCALTA.43
2058 14:50:03.650614 # ok 124 write_invalid.LCALTA.43
2059 14:50:03.655709 # ok 125 event_missing.LCALTA.43
2060 14:50:03.656161 # ok 126 event_spurious.LCALTA.43
2061 14:50:03.661263 # ok 127 get_value.LCALTA.42
2062 14:50:03.661688 # # LCALTA.42 FRDDR_C SINK 1 SEL
2063 14:50:03.666799 # ok 128 name.LCALTA.42
2064 14:50:03.667231 # ok 129 write_default.LCALTA.42
2065 14:50:03.672386 # ok 130 write_valid.LCALTA.42
2066 14:50:03.672812 # ok 131 write_invalid.LCALTA.42
2067 14:50:03.677924 # ok 132 event_missing.LCALTA.42
2068 14:50:03.678355 # ok 133 event_spurious.LCALTA.42
2069 14:50:03.683476 # ok 134 get_value.LCALTA.41
2070 14:50:03.683902 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
2071 14:50:03.689002 # ok 135 name.LCALTA.41
2072 14:50:03.689434 # ok 136 write_default.LCALTA.41
2073 14:50:03.694538 # ok 137 write_valid.LCALTA.41
2074 14:50:03.694966 # ok 138 write_invalid.LCALTA.41
2075 14:50:03.700064 # ok 139 event_missing.LCALTA.41
2076 14:50:03.700509 # ok 140 event_spurious.LCALTA.41
2077 14:50:03.705654 # ok 141 get_value.LCALTA.40
2078 14:50:03.706084 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
2079 14:50:03.711168 # ok 142 name.LCALTA.40
2080 14:50:03.711593 # ok 143 write_default.LCALTA.40
2081 14:50:03.716753 # ok 144 write_valid.LCALTA.40
2082 14:50:03.717236 # ok 145 write_invalid.LCALTA.40
2083 14:50:03.722282 # ok 146 event_missing.LCALTA.40
2084 14:50:03.722727 # ok 147 event_spurious.LCALTA.40
2085 14:50:03.727855 # ok 148 get_value.LCALTA.39
2086 14:50:03.733445 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
2087 14:50:03.733880 # ok 149 name.LCALTA.39
2088 14:50:03.734277 # ok 150 write_default.LCALTA.39
2089 14:50:03.738994 # ok 151 write_valid.LCALTA.39
2090 14:50:03.739424 # ok 152 write_invalid.LCALTA.39
2091 14:50:03.744546 # ok 153 event_missing.LCALTA.39
2092 14:50:03.750088 # ok 154 event_spurious.LCALTA.39
2093 14:50:03.750527 # ok 155 get_value.LCALTA.38
2094 14:50:03.755619 # # LCALTA.38 FRDDR_B SINK 3 SEL
2095 14:50:03.756094 # ok 156 name.LCALTA.38
2096 14:50:03.756493 # ok 157 write_default.LCALTA.38
2097 14:50:03.761152 # ok 158 write_valid.LCALTA.38
2098 14:50:03.761580 # ok 159 write_invalid.LCALTA.38
2099 14:50:03.766680 # ok 160 event_missing.LCALTA.38
2100 14:50:03.772237 # ok 161 event_spurious.LCALTA.38
2101 14:50:03.772660 # ok 162 get_value.LCALTA.37
2102 14:50:03.777783 # # LCALTA.37 FRDDR_B SINK 2 SEL
2103 14:50:03.778216 # ok 163 name.LCALTA.37
2104 14:50:03.778612 # ok 164 write_default.LCALTA.37
2105 14:50:03.783293 # ok 165 write_valid.LCALTA.37
2106 14:50:03.788826 # ok 166 write_invalid.LCALTA.37
2107 14:50:03.789254 # ok 167 event_missing.LCALTA.37
2108 14:50:03.794459 # ok 168 event_spurious.LCALTA.37
2109 14:50:03.794884 # ok 169 get_value.LCALTA.36
2110 14:50:03.799937 # # LCALTA.36 FRDDR_B SINK 1 SEL
2111 14:50:03.800398 # ok 170 name.LCALTA.36
2112 14:50:03.805500 # ok 171 write_default.LCALTA.36
2113 14:50:03.805940 # ok 172 write_valid.LCALTA.36
2114 14:50:03.811037 # ok 173 write_invalid.LCALTA.36
2115 14:50:03.811544 # ok 174 event_missing.LCALTA.36
2116 14:50:03.816580 # ok 175 event_spurious.LCALTA.36
2117 14:50:03.817030 # ok 176 get_value.LCALTA.35
2118 14:50:03.822111 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
2119 14:50:03.822542 # ok 177 name.LCALTA.35
2120 14:50:03.827698 # ok 178 write_default.LCALTA.35
2121 14:50:03.828158 # ok 179 write_valid.LCALTA.35
2122 14:50:03.833211 # ok 180 write_invalid.LCALTA.35
2123 14:50:03.833646 # ok 181 event_missing.LCALTA.35
2124 14:50:03.838767 # ok 182 event_spurious.LCALTA.35
2125 14:50:03.839198 # ok 183 get_value.LCALTA.34
2126 14:50:03.844323 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
2127 14:50:03.844755 # ok 184 name.LCALTA.34
2128 14:50:03.849851 # ok 185 write_default.LCALTA.34
2129 14:50:03.850279 # ok 186 write_valid.LCALTA.34
2130 14:50:03.855448 # ok 187 write_invalid.LCALTA.34
2131 14:50:03.855874 # ok 188 event_missing.LCALTA.34
2132 14:50:03.860959 # ok 189 event_spurious.LCALTA.34
2133 14:50:03.861420 # ok 190 get_value.LCALTA.33
2134 14:50:03.866509 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
2135 14:50:03.866955 # ok 191 name.LCALTA.33
2136 14:50:03.872063 # ok 192 write_default.LCALTA.33
2137 14:50:03.872500 # ok 193 write_valid.LCALTA.33
2138 14:50:03.877585 # ok 194 write_invalid.LCALTA.33
2139 14:50:03.878015 # ok 195 event_missing.LCALTA.33
2140 14:50:03.883150 # ok 196 event_spurious.LCALTA.33
2141 14:50:03.883576 # ok 197 get_value.LCALTA.32
2142 14:50:03.888737 # # LCALTA.32 FRDDR_A SINK 3 SEL
2143 14:50:03.889172 # ok 198 name.LCALTA.32
2144 14:50:03.894241 # ok 199 write_default.LCALTA.32
2145 14:50:03.894715 # ok 200 write_valid.LCALTA.32
2146 14:50:03.899835 # ok 201 write_invalid.LCALTA.32
2147 14:50:03.900317 # ok 202 event_missing.LCALTA.32
2148 14:50:03.905401 # ok 203 event_spurious.LCALTA.32
2149 14:50:03.905842 # ok 204 get_value.LCALTA.31
2150 14:50:03.910891 # # LCALTA.31 FRDDR_A SINK 2 SEL
2151 14:50:03.911334 # ok 205 name.LCALTA.31
2152 14:50:03.916510 # ok 206 write_default.LCALTA.31
2153 14:50:03.916953 # ok 207 write_valid.LCALTA.31
2154 14:50:03.922036 # ok 208 write_invalid.LCALTA.31
2155 14:50:03.922481 # ok 209 event_missing.LCALTA.31
2156 14:50:03.927540 # ok 210 event_spurious.LCALTA.31
2157 14:50:03.928000 # ok 211 get_value.LCALTA.30
2158 14:50:03.933069 # # LCALTA.30 FRDDR_A SINK 1 SEL
2159 14:50:03.933503 # ok 212 name.LCALTA.30
2160 14:50:03.938611 # ok 213 write_default.LCALTA.30
2161 14:50:03.939037 # ok 214 write_valid.LCALTA.30
2162 14:50:03.944198 # ok 215 write_invalid.LCALTA.30
2163 14:50:03.949703 # ok 216 event_missing.LCALTA.30
2164 14:50:03.950143 # ok 217 event_spurious.LCALTA.30
2165 14:50:03.955264 # ok 218 get_value.LCALTA.29
2166 14:50:03.955698 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2167 14:50:03.960809 # ok 219 name.LCALTA.29
2168 14:50:03.961245 # ok 220 write_default.LCALTA.29
2169 14:50:03.966386 # ok 221 write_valid.LCALTA.29
2170 14:50:03.966819 # ok 222 write_invalid.LCALTA.29
2171 14:50:03.971897 # ok 223 event_missing.LCALTA.29
2172 14:50:03.972356 # ok 224 event_spurious.LCALTA.29
2173 14:50:03.977504 # ok 225 get_value.LCALTA.28
2174 14:50:03.977940 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2175 14:50:03.982994 # ok 226 name.LCALTA.28
2176 14:50:03.983430 # ok 227 write_default.LCALTA.28
2177 14:50:03.988550 # ok 228 write_valid.LCALTA.28
2178 14:50:03.988984 # ok 229 write_invalid.LCALTA.28
2179 14:50:03.994096 # ok 230 event_missing.LCALTA.28
2180 14:50:03.994530 # ok 231 event_spurious.LCALTA.28
2181 14:50:03.999621 # ok 232 get_value.LCALTA.27
2182 14:50:04.000092 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2183 14:50:04.005176 # ok 233 name.LCALTA.27
2184 14:50:04.005611 # ok 234 write_default.LCALTA.27
2185 14:50:04.010742 # ok 235 write_valid.LCALTA.27
2186 14:50:04.011176 # ok 236 write_invalid.LCALTA.27
2187 14:50:04.016271 # ok 237 event_missing.LCALTA.27
2188 14:50:04.016705 # ok 238 event_spurious.LCALTA.27
2189 14:50:04.021828 # ok 239 get_value.LCALTA.26
2190 14:50:04.022263 # # LCALTA.26 ELD
2191 14:50:04.027376 # ok 240 name.LCALTA.26
2192 14:50:04.027818 # # ELD is not writeable
2193 14:50:04.032927 # ok 241 # SKIP write_default.LCALTA.26
2194 14:50:04.033366 # # ELD is not writeable
2195 14:50:04.038481 # ok 242 # SKIP write_valid.LCALTA.26
2196 14:50:04.038914 # # ELD is not writeable
2197 14:50:04.044026 # ok 243 # SKIP write_invalid.LCALTA.26
2198 14:50:04.044461 # ok 244 event_missing.LCALTA.26
2199 14:50:04.049565 # ok 245 event_spurious.LCALTA.26
2200 14:50:04.049998 # ok 246 get_value.LCALTA.25
2201 14:50:04.055094 # # LCALTA.25 IEC958 Playback Default
2202 14:50:04.055532 # ok 247 name.LCALTA.25
2203 14:50:04.060610 # ok 248 write_default.LCALTA.25
2204 14:50:04.061040 # ok 249 # SKIP write_valid.LCALTA.25
2205 14:50:04.066165 # ok 250 # SKIP write_invalid.LCALTA.25
2206 14:50:04.071719 # ok 251 event_missing.LCALTA.25
2207 14:50:04.072171 # ok 252 event_spurious.LCALTA.25
2208 14:50:04.077273 # ok 253 get_value.LCALTA.24
2209 14:50:04.077703 # # LCALTA.24 IEC958 Playback Mask
2210 14:50:04.078109 # ok 254 name.LCALTA.24
2211 14:50:04.082787 # # IEC958 Playback Mask is not writeable
2212 14:50:04.088375 # ok 255 # SKIP write_default.LCALTA.24
2213 14:50:04.088813 # # IEC958 Playback Mask is not writeable
2214 14:50:04.093921 # ok 256 # SKIP write_valid.LCALTA.24
2215 14:50:04.099703 # # IEC958 Playback Mask is not writeable
2216 14:50:04.100380 # ok 257 # SKIP write_invalid.LCALTA.24
2217 14:50:04.105094 # ok 258 event_missing.LCALTA.24
2218 14:50:04.105589 # ok 259 event_spurious.LCALTA.24
2219 14:50:04.110614 # ok 260 get_value.LCALTA.23
2220 14:50:04.111089 # # LCALTA.23 Playback Channel Map
2221 14:50:04.116695 # ok 261 name.LCALTA.23
2222 14:50:04.121788 # # Playback Channel Map is not writeable
2223 14:50:04.122259 # ok 262 # SKIP write_default.LCALTA.23
2224 14:50:04.127369 # # Playback Channel Map is not writeable
2225 14:50:04.127841 # ok 263 # SKIP write_valid.LCALTA.23
2226 14:50:04.133109 # # Playback Channel Map is not writeable
2227 14:50:04.138631 # ok 264 # SKIP write_invalid.LCALTA.23
2228 14:50:04.139097 # ok 265 event_missing.LCALTA.23
2229 14:50:04.144105 # ok 266 event_spurious.LCALTA.23
2230 14:50:04.144569 # ok 267 get_value.LCALTA.22
2231 14:50:04.149614 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2232 14:50:04.150079 # ok 268 name.LCALTA.22
2233 14:50:04.155069 # ok 269 write_default.LCALTA.22
2234 14:50:04.155525 # ok 270 write_valid.LCALTA.22
2235 14:50:04.160685 # ok 271 write_invalid.LCALTA.22
2236 14:50:04.161146 # ok 272 event_missing.LCALTA.22
2237 14:50:04.166050 # ok 273 event_spurious.LCALTA.22
2238 14:50:04.171551 # ok 274 get_value.LCALTA.21
2239 14:50:04.172041 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2240 14:50:04.172459 # ok 275 name.LCALTA.21
2241 14:50:04.177117 # ok 276 write_default.LCALTA.21
2242 14:50:04.182745 # ok 277 write_valid.LCALTA.21
2243 14:50:04.183204 # ok 278 write_invalid.LCALTA.21
2244 14:50:04.188322 # ok 279 event_missing.LCALTA.21
2245 14:50:04.188842 # ok 280 event_spurious.LCALTA.21
2246 14:50:04.193781 # ok 281 get_value.LCALTA.20
2247 14:50:04.194238 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2248 14:50:04.199342 # ok 282 name.LCALTA.20
2249 14:50:04.199799 # ok 283 write_default.LCALTA.20
2250 14:50:04.204864 # ok 284 write_valid.LCALTA.20
2251 14:50:04.205323 # ok 285 write_invalid.LCALTA.20
2252 14:50:04.210425 # ok 286 event_missing.LCALTA.20
2253 14:50:04.210871 # ok 287 event_spurious.LCALTA.20
2254 14:50:04.215941 # ok 288 get_value.LCALTA.19
2255 14:50:04.216431 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2256 14:50:04.221517 # ok 289 name.LCALTA.19
2257 14:50:04.221959 # ok 290 write_default.LCALTA.19
2258 14:50:04.227029 # ok 291 write_valid.LCALTA.19
2259 14:50:04.227465 # ok 292 write_invalid.LCALTA.19
2260 14:50:04.232571 # ok 293 event_missing.LCALTA.19
2261 14:50:04.233002 # ok 294 event_spurious.LCALTA.19
2262 14:50:04.238192 # ok 295 get_value.LCALTA.18
2263 14:50:04.238682 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2264 14:50:04.243752 # ok 296 name.LCALTA.18
2265 14:50:04.244273 # ok 297 write_default.LCALTA.18
2266 14:50:04.249263 # ok 298 write_valid.LCALTA.18
2267 14:50:04.249700 # ok 299 write_invalid.LCALTA.18
2268 14:50:04.254821 # ok 300 event_missing.LCALTA.18
2269 14:50:04.255255 # ok 301 event_spurious.LCALTA.18
2270 14:50:04.260307 # ok 302 get_value.LCALTA.17
2271 14:50:04.265859 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2272 14:50:04.266294 # ok 303 name.LCALTA.17
2273 14:50:04.266695 # ok 304 write_default.LCALTA.17
2274 14:50:04.271473 # ok 305 write_valid.LCALTA.17
2275 14:50:04.276981 # ok 306 write_invalid.LCALTA.17
2276 14:50:04.277414 # ok 307 event_missing.LCALTA.17
2277 14:50:04.282530 # ok 308 event_spurious.LCALTA.17
2278 14:50:04.282959 # ok 309 get_value.LCALTA.16
2279 14:50:04.288072 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2280 14:50:04.288501 # ok 310 name.LCALTA.16
2281 14:50:04.293613 # ok 311 write_default.LCALTA.16
2282 14:50:04.294036 # ok 312 write_valid.LCALTA.16
2283 14:50:04.299146 # ok 313 write_invalid.LCALTA.16
2284 14:50:04.299574 # ok 314 event_missing.LCALTA.16
2285 14:50:04.304699 # ok 315 event_spurious.LCALTA.16
2286 14:50:04.305128 # ok 316 get_value.LCALTA.15
2287 14:50:04.310237 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2288 14:50:04.310663 # ok 317 name.LCALTA.15
2289 14:50:04.315794 # ok 318 write_default.LCALTA.15
2290 14:50:04.316257 # ok 319 write_valid.LCALTA.15
2291 14:50:04.321353 # ok 320 write_invalid.LCALTA.15
2292 14:50:04.321781 # ok 321 event_missing.LCALTA.15
2293 14:50:04.326886 # ok 322 event_spurious.LCALTA.15
2294 14:50:04.327309 # ok 323 get_value.LCALTA.14
2295 14:50:04.332419 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2296 14:50:04.332853 # ok 324 name.LCALTA.14
2297 14:50:04.337983 # ok 325 write_default.LCALTA.14
2298 14:50:04.338417 # ok 326 write_valid.LCALTA.14
2299 14:50:04.343558 # ok 327 write_invalid.LCALTA.14
2300 14:50:04.344007 # ok 328 event_missing.LCALTA.14
2301 14:50:04.349048 # ok 329 event_spurious.LCALTA.14
2302 14:50:04.349479 # ok 330 get_value.LCALTA.13
2303 14:50:04.354606 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2304 14:50:04.355029 # ok 331 name.LCALTA.13
2305 14:50:04.360186 # ok 332 write_default.LCALTA.13
2306 14:50:04.360664 # ok 333 write_valid.LCALTA.13
2307 14:50:04.365716 # ok 334 write_invalid.LCALTA.13
2308 14:50:04.366149 # ok 335 event_missing.LCALTA.13
2309 14:50:04.371245 # ok 336 event_spurious.LCALTA.13
2310 14:50:04.371679 # ok 337 get_value.LCALTA.12
2311 14:50:04.376806 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2312 14:50:04.377237 # ok 338 name.LCALTA.12
2313 14:50:04.382360 # ok 339 write_default.LCALTA.12
2314 14:50:04.387917 # ok 340 write_valid.LCALTA.12
2315 14:50:04.388374 # ok 341 write_invalid.LCALTA.12
2316 14:50:04.393420 # ok 342 event_missing.LCALTA.12
2317 14:50:04.393848 # ok 343 event_spurious.LCALTA.12
2318 14:50:04.398981 # ok 344 get_value.LCALTA.11
2319 14:50:04.399406 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2320 14:50:04.404559 # ok 345 name.LCALTA.11
2321 14:50:04.404996 # ok 346 write_default.LCALTA.11
2322 14:50:04.410082 # ok 347 write_valid.LCALTA.11
2323 14:50:04.410511 # ok 348 write_invalid.LCALTA.11
2324 14:50:04.415604 # ok 349 event_missing.LCALTA.11
2325 14:50:04.416069 # ok 350 event_spurious.LCALTA.11
2326 14:50:04.421147 # ok 351 get_value.LCALTA.10
2327 14:50:04.421575 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2328 14:50:04.426709 # ok 352 name.LCALTA.10
2329 14:50:04.427130 # ok 353 write_default.LCALTA.10
2330 14:50:04.432257 # ok 354 write_valid.LCALTA.10
2331 14:50:04.432680 # ok 355 write_invalid.LCALTA.10
2332 14:50:04.437783 # ok 356 event_missing.LCALTA.10
2333 14:50:04.438214 # ok 357 event_spurious.LCALTA.10
2334 14:50:04.443340 # ok 358 get_value.LCALTA.9
2335 14:50:04.443774 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2336 14:50:04.448890 # ok 359 name.LCALTA.9
2337 14:50:04.449315 # ok 360 write_default.LCALTA.9
2338 14:50:04.454421 # ok 361 write_valid.LCALTA.9
2339 14:50:04.454846 # ok 362 write_invalid.LCALTA.9
2340 14:50:04.459999 # ok 363 event_missing.LCALTA.9
2341 14:50:04.460429 # ok 364 event_spurious.LCALTA.9
2342 14:50:04.465614 # ok 365 get_value.LCALTA.8
2343 14:50:04.466152 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2344 14:50:04.471096 # ok 366 name.LCALTA.8
2345 14:50:04.471580 # ok 367 write_default.LCALTA.8
2346 14:50:04.476646 # ok 368 write_valid.LCALTA.8
2347 14:50:04.477091 # ok 369 write_invalid.LCALTA.8
2348 14:50:04.482177 # ok 370 event_missing.LCALTA.8
2349 14:50:04.482612 # ok 371 event_spurious.LCALTA.8
2350 14:50:04.487724 # ok 372 get_value.LCALTA.7
2351 14:50:04.488187 # # LCALTA.7 ACODEC Unmute Ramp Switch
2352 14:50:04.493262 # ok 373 name.LCALTA.7
2353 14:50:04.493699 # ok 374 write_default.LCALTA.7
2354 14:50:04.498803 # ok 375 write_valid.LCALTA.7
2355 14:50:04.499229 # ok 376 write_invalid.LCALTA.7
2356 14:50:04.504370 # ok 377 event_missing.LCALTA.7
2357 14:50:04.504798 # ok 378 event_spurious.LCALTA.7
2358 14:50:04.509901 # ok 379 get_value.LCALTA.6
2359 14:50:04.510326 # # LCALTA.6 ACODEC Mute Ramp Switch
2360 14:50:04.515449 # ok 380 name.LCALTA.6
2361 14:50:04.515873 # ok 381 write_default.LCALTA.6
2362 14:50:04.520972 # ok 382 write_valid.LCALTA.6
2363 14:50:04.521403 # ok 383 write_invalid.LCALTA.6
2364 14:50:04.526603 # ok 384 event_missing.LCALTA.6
2365 14:50:04.527032 # ok 385 event_spurious.LCALTA.6
2366 14:50:04.532197 # ok 386 get_value.LCALTA.5
2367 14:50:04.532625 # # LCALTA.5 ACODEC Volume Ramp Switch
2368 14:50:04.537695 # ok 387 name.LCALTA.5
2369 14:50:04.538118 # ok 388 write_default.LCALTA.5
2370 14:50:04.543240 # ok 389 write_valid.LCALTA.5
2371 14:50:04.543667 # ok 390 write_invalid.LCALTA.5
2372 14:50:04.548794 # ok 391 event_missing.LCALTA.5
2373 14:50:04.549227 # ok 392 event_spurious.LCALTA.5
2374 14:50:04.554334 # ok 393 get_value.LCALTA.4
2375 14:50:04.554767 # # LCALTA.4 ACODEC Ramp Rate
2376 14:50:04.559910 # ok 394 name.LCALTA.4
2377 14:50:04.560369 # ok 395 write_default.LCALTA.4
2378 14:50:04.565453 # ok 396 write_valid.LCALTA.4
2379 14:50:04.565879 # ok 397 write_invalid.LCALTA.4
2380 14:50:04.570989 # ok 398 event_missing.LCALTA.4
2381 14:50:04.571414 # ok 399 event_spurious.LCALTA.4
2382 14:50:04.576524 # ok 400 get_value.LCALTA.3
2383 14:50:04.576955 # # LCALTA.3 ACODEC Playback Volume
2384 14:50:04.582080 # ok 401 name.LCALTA.3
2385 14:50:04.582510 # ok 402 write_default.LCALTA.3
2386 14:50:04.587622 # ok 403 write_valid.LCALTA.3
2387 14:50:04.588074 # ok 404 write_invalid.LCALTA.3
2388 14:50:04.593164 # ok 405 event_missing.LCALTA.3
2389 14:50:04.593597 # ok 406 event_spurious.LCALTA.3
2390 14:50:04.598708 # ok 407 get_value.LCALTA.2
2391 14:50:04.599156 # # LCALTA.2 ACODEC Playback Switch
2392 14:50:04.604321 # ok 408 name.LCALTA.2
2393 14:50:04.604758 # ok 409 write_default.LCALTA.2
2394 14:50:04.609814 # ok 410 write_valid.LCALTA.2
2395 14:50:04.610243 # ok 411 write_invalid.LCALTA.2
2396 14:50:04.615370 # ok 412 event_missing.LCALTA.2
2397 14:50:04.615796 # ok 413 event_spurious.LCALTA.2
2398 14:50:04.620910 # ok 414 get_value.LCALTA.1
2399 14:50:04.621342 # # LCALTA.1 ACODEC Playback Channel Mode
2400 14:50:04.626450 # ok 415 name.LCALTA.1
2401 14:50:04.626880 # ok 416 write_default.LCALTA.1
2402 14:50:04.632016 # ok 417 write_valid.LCALTA.1
2403 14:50:04.632453 # ok 418 write_invalid.LCALTA.1
2404 14:50:04.637566 # ok 419 event_missing.LCALTA.1
2405 14:50:04.637994 # ok 420 event_spurious.LCALTA.1
2406 14:50:04.643085 # ok 421 get_value.LCALTA.0
2407 14:50:04.643582 # # LCALTA.0 TOACODEC Lane Select
2408 14:50:04.648643 # ok 422 name.LCALTA.0
2409 14:50:04.649143 # ok 423 write_default.LCALTA.0
2410 14:50:04.654141 # ok 424 write_valid.LCALTA.0
2411 14:50:04.654579 # ok 425 write_invalid.LCALTA.0
2412 14:50:04.659695 # ok 426 event_missing.LCALTA.0
2413 14:50:04.660159 # ok 427 event_spurious.LCALTA.0
2414 14:50:04.665238 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2415 14:50:04.670807 ok 1 selftests: alsa: mixer-test
2416 14:50:04.671238 # timeout set to 45
2417 14:50:04.671635 # selftests: alsa: pcm-test
2418 14:50:04.676349 # TAP version 13
2419 14:50:04.676777 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2420 14:50:04.681925 # # LCALTA.0 - fe.dai-link-0 (*)
2421 14:50:04.682360 # # LCALTA.0 - fe.dai-link-1 (*)
2422 14:50:04.687443 # # LCALTA.0 - fe.dai-link-2 (*)
2423 14:50:04.687870 # # LCALTA.0 - fe.dai-link-3 (*)
2424 14:50:04.692988 # # LCALTA.0 - fe.dai-link-4 (*)
2425 14:50:04.693416 # # LCALTA.0 - fe.dai-link-5 (*)
2426 14:50:04.698525 # 1..42
2427 14:50:04.704067 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2428 14:50:04.704503 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2429 14:50:04.709650 # # snd_pcm_hw_params: Invalid argument
2430 14:50:04.715140 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2431 14:50:04.720694 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2432 14:50:04.721157 # # snd_pcm_hw_params: Invalid argument
2433 14:50:04.726226 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2434 14:50:04.731758 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2435 14:50:04.737314 # # snd_pcm_hw_params: Invalid argument
2436 14:50:04.742854 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2437 14:50:04.748410 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2438 14:50:04.748839 # # snd_pcm_hw_params: Invalid argument
2439 14:50:04.753980 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2440 14:50:04.759576 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2441 14:50:04.765039 # # snd_pcm_hw_params: Invalid argument
2442 14:50:04.770607 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2443 14:50:04.776155 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2444 14:50:04.776581 # # snd_pcm_hw_params: Invalid argument
2445 14:50:04.781735 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2446 14:50:04.787229 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2447 14:50:04.792799 # # snd_pcm_hw_params: Invalid argument
2448 14:50:04.798321 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2449 14:50:04.798752 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2450 14:50:04.803858 # # snd_pcm_hw_params: Invalid argument
2451 14:50:04.809422 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2452 14:50:04.814948 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2453 14:50:04.815373 # # snd_pcm_hw_params: Invalid argument
2454 14:50:04.826090 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2455 14:50:04.826524 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2456 14:50:04.831651 # # snd_pcm_hw_params: Invalid argument
2457 14:50:04.837163 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2458 14:50:04.842709 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2459 14:50:04.843139 # # snd_pcm_hw_params: Invalid argument
2460 14:50:04.848260 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2461 14:50:04.853793 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2462 14:50:04.859357 # # snd_pcm_hw_params: Invalid argument
2463 14:50:04.864875 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2464 14:50:04.870440 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2465 14:50:04.870869 # # snd_pcm_hw_params: Invalid argument
2466 14:50:04.876034 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2467 14:50:04.881592 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2468 14:50:04.887067 # # snd_pcm_hw_params: Invalid argument
2469 14:50:04.892651 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2470 14:50:04.898158 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2471 14:50:04.898581 # # snd_pcm_hw_params: Invalid argument
2472 14:50:04.903711 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2473 14:50:04.909266 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2474 14:50:04.914800 # # snd_pcm_hw_params: Invalid argument
2475 14:50:04.920387 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2476 14:50:04.920815 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2477 14:50:04.925914 # # snd_pcm_hw_params: Invalid argument
2478 14:50:04.931436 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2479 14:50:04.937002 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2480 14:50:04.942641 # # snd_pcm_hw_params: Invalid argument
2481 14:50:04.948122 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2482 14:50:04.948551 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2483 14:50:04.953665 # # snd_pcm_hw_params: Invalid argument
2484 14:50:04.959176 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2485 14:50:04.964741 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2486 14:50:04.970267 # # snd_pcm_hw_params: Invalid argument
2487 14:50:04.975841 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2488 14:50:04.976304 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2489 14:50:04.981395 # # snd_pcm_hw_params: Invalid argument
2490 14:50:04.986931 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2491 14:50:04.992515 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2492 14:50:04.992939 # # snd_pcm_hw_params: Invalid argument
2493 14:50:04.998020 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2494 14:50:05.003603 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2495 14:50:05.009112 # # snd_pcm_hw_params: Invalid argument
2496 14:50:05.014635 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2497 14:50:05.020191 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2498 14:50:05.020620 # # snd_pcm_hw_params: Invalid argument
2499 14:50:05.025744 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2500 14:50:05.031276 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2501 14:50:05.036831 # # snd_pcm_hw_params: Invalid argument
2502 14:50:05.042391 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2503 14:50:05.047923 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2504 14:50:05.048371 # # snd_pcm_hw_params: Invalid argument
2505 14:50:05.053472 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2506 14:50:05.059021 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2507 14:50:05.064615 # # snd_pcm_hw_params: Invalid argument
2508 14:50:05.070101 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2509 14:50:05.075636 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2510 14:50:05.076091 # # snd_pcm_hw_params: Invalid argument
2511 14:50:05.081251 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2512 14:50:05.086776 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2513 14:50:05.092296 # # snd_pcm_hw_params: Invalid argument
2514 14:50:05.097831 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2515 14:50:05.103405 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2516 14:50:05.103837 # # snd_pcm_hw_params: Invalid argument
2517 14:50:05.108929 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2518 14:50:05.114499 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2519 14:50:05.120054 # # snd_pcm_hw_params: Invalid argument
2520 14:50:05.125617 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2521 14:50:05.131119 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2522 14:50:05.131548 # # snd_pcm_hw_params: Invalid argument
2523 14:50:05.136658 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2524 14:50:05.142217 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2525 14:50:05.147758 # # snd_pcm_hw_params: Invalid argument
2526 14:50:05.153311 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2527 14:50:05.158864 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2528 14:50:05.159295 # # snd_pcm_hw_params: Invalid argument
2529 14:50:05.164414 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2530 14:50:05.169951 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2531 14:50:05.175502 # # snd_pcm_hw_params: Invalid argument
2532 14:50:05.181043 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2533 14:50:05.186624 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2534 14:50:05.187050 # # snd_pcm_hw_params: Invalid argument
2535 14:50:05.192149 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2536 14:50:05.197682 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2537 14:50:05.203227 # # snd_pcm_hw_params: Invalid argument
2538 14:50:05.208818 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2539 14:50:05.214337 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2540 14:50:05.214770 # # snd_pcm_hw_params: Invalid argument
2541 14:50:05.219866 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2542 14:50:05.225478 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2543 14:50:05.231022 # # snd_pcm_hw_params: Invalid argument
2544 14:50:05.236574 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2545 14:50:05.242168 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2546 14:50:05.242656 # # snd_pcm_hw_params: Invalid argument
2547 14:50:05.247728 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2548 14:50:05.253209 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2549 14:50:05.258742 # # snd_pcm_hw_params: Invalid argument
2550 14:50:05.264292 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2551 14:50:05.269851 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2552 14:50:05.270282 # # snd_pcm_hw_params: Invalid argument
2553 14:50:05.275375 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2554 14:50:05.280917 ok 2 selftests: alsa: pcm-test
2555 14:50:05.281358 # timeout set to 45
2556 14:50:05.286440 # selftests: alsa: test-pcmtest-driver
2557 14:50:05.286875 # TAP version 13
2558 14:50:05.287274 # 1..5
2559 14:50:05.292004 # # Starting 5 tests from 1 test cases.
2560 14:50:05.292442 # # RUN pcmtest.playback ...
2561 14:50:05.297531 # # SKIP Can't read patterns. Probably, module isn't loaded
2562 14:50:05.303064 # # OK pcmtest.playback
2563 14:50:05.308669 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2564 14:50:05.314158 # # RUN pcmtest.capture ...
2565 14:50:05.319709 # # SKIP Can't read patterns. Probably, module isn't loaded
2566 14:50:05.325265 # # OK pcmtest.capture
2567 14:50:05.330850 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2568 14:50:05.336386 # # RUN pcmtest.ni_capture ...
2569 14:50:05.341925 # # SKIP Can't read patterns. Probably, module isn't loaded
2570 14:50:05.342372 # # OK pcmtest.ni_capture
2571 14:50:05.353045 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2572 14:50:05.353509 # # RUN pcmtest.ni_playback ...
2573 14:50:05.358564 # # SKIP Can't read patterns. Probably, module isn't loaded
2574 14:50:05.364117 # # OK pcmtest.ni_playback
2575 14:50:05.369692 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2576 14:50:05.375188 # # RUN pcmtest.reset_ioctl ...
2577 14:50:05.380748 # # SKIP Can't read patterns. Probably, module isn't loaded
2578 14:50:05.386293 # # OK pcmtest.reset_ioctl
2579 14:50:05.391857 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2580 14:50:05.397381 # # PASSED: 5 / 5 tests passed.
2581 14:50:05.402950 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2582 14:50:05.403376 ok 3 selftests: alsa: test-pcmtest-driver
2583 14:50:05.408472 # timeout set to 45
2584 14:50:05.408903 # selftests: alsa: utimer-test
2585 14:50:05.409300 # TAP version 13
2586 14:50:05.409696 # 1..2
2587 14:50:05.414001 # # Starting 2 tests from 2 test cases.
2588 14:50:05.419586 # # RUN global.wrong_timers_test ...
2589 14:50:05.425139 # # OK global.wrong_timers_test
2590 14:50:05.425573 # ok 1 global.wrong_timers_test
2591 14:50:05.430682 # # RUN timer_f.utimer ...
2592 14:50:05.436235 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2593 14:50:05.441753 # # utimer: Test terminated by assertion
2594 14:50:05.447333 # # FAIL timer_f.utimer
2595 14:50:05.447767 # not ok 2 timer_f.utimer
2596 14:50:05.452834 # # FAILED: 1 / 2 tests passed.
2597 14:50:05.460234 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2598 14:50:05.460668 not ok 4 selftests: alsa: utimer-test # exit=1
2599 14:50:05.989793 alsa_mixer-test_get_value_LCALTA_60 pass
2600 14:50:05.995146 alsa_mixer-test_name_LCALTA_60 pass
2601 14:50:05.995599 alsa_mixer-test_write_default_LCALTA_60 pass
2602 14:50:06.000644 alsa_mixer-test_write_valid_LCALTA_60 pass
2603 14:50:06.004118 alsa_mixer-test_write_invalid_LCALTA_60 pass
2604 14:50:06.009656 alsa_mixer-test_event_missing_LCALTA_60 pass
2605 14:50:06.015193 alsa_mixer-test_event_spurious_LCALTA_60 pass
2606 14:50:06.015625 alsa_mixer-test_get_value_LCALTA_59 pass
2607 14:50:06.020749 alsa_mixer-test_name_LCALTA_59 pass
2608 14:50:06.026263 alsa_mixer-test_write_default_LCALTA_59 pass
2609 14:50:06.026695 alsa_mixer-test_write_valid_LCALTA_59 pass
2610 14:50:06.031832 alsa_mixer-test_write_invalid_LCALTA_59 pass
2611 14:50:06.037408 alsa_mixer-test_event_missing_LCALTA_59 pass
2612 14:50:06.037843 alsa_mixer-test_event_spurious_LCALTA_59 pass
2613 14:50:06.042949 alsa_mixer-test_get_value_LCALTA_58 pass
2614 14:50:06.048473 alsa_mixer-test_name_LCALTA_58 pass
2615 14:50:06.048913 alsa_mixer-test_write_default_LCALTA_58 pass
2616 14:50:06.054052 alsa_mixer-test_write_valid_LCALTA_58 pass
2617 14:50:06.059569 alsa_mixer-test_write_invalid_LCALTA_58 pass
2618 14:50:06.065127 alsa_mixer-test_event_missing_LCALTA_58 pass
2619 14:50:06.065583 alsa_mixer-test_event_spurious_LCALTA_58 pass
2620 14:50:06.070672 alsa_mixer-test_get_value_LCALTA_57 pass
2621 14:50:06.076200 alsa_mixer-test_name_LCALTA_57 pass
2622 14:50:06.076637 alsa_mixer-test_write_default_LCALTA_57 pass
2623 14:50:06.081741 alsa_mixer-test_write_valid_LCALTA_57 pass
2624 14:50:06.087312 alsa_mixer-test_write_invalid_LCALTA_57 pass
2625 14:50:06.087741 alsa_mixer-test_event_missing_LCALTA_57 pass
2626 14:50:06.092833 alsa_mixer-test_event_spurious_LCALTA_57 pass
2627 14:50:06.098393 alsa_mixer-test_get_value_LCALTA_56 pass
2628 14:50:06.098825 alsa_mixer-test_name_LCALTA_56 pass
2629 14:50:06.103933 alsa_mixer-test_write_default_LCALTA_56 pass
2630 14:50:06.109476 alsa_mixer-test_write_valid_LCALTA_56 pass
2631 14:50:06.109909 alsa_mixer-test_write_invalid_LCALTA_56 pass
2632 14:50:06.115033 alsa_mixer-test_event_missing_LCALTA_56 pass
2633 14:50:06.120576 alsa_mixer-test_event_spurious_LCALTA_56 pass
2634 14:50:06.126112 alsa_mixer-test_get_value_LCALTA_55 pass
2635 14:50:06.126547 alsa_mixer-test_name_LCALTA_55 pass
2636 14:50:06.131649 alsa_mixer-test_write_default_LCALTA_55 pass
2637 14:50:06.137202 alsa_mixer-test_write_valid_LCALTA_55 pass
2638 14:50:06.137638 alsa_mixer-test_write_invalid_LCALTA_55 pass
2639 14:50:06.142759 alsa_mixer-test_event_missing_LCALTA_55 pass
2640 14:50:06.148311 alsa_mixer-test_event_spurious_LCALTA_55 pass
2641 14:50:06.148742 alsa_mixer-test_get_value_LCALTA_54 pass
2642 14:50:06.153877 alsa_mixer-test_name_LCALTA_54 pass
2643 14:50:06.159402 alsa_mixer-test_write_default_LCALTA_54 pass
2644 14:50:06.159837 alsa_mixer-test_write_valid_LCALTA_54 pass
2645 14:50:06.164942 alsa_mixer-test_write_invalid_LCALTA_54 pass
2646 14:50:06.170546 alsa_mixer-test_event_missing_LCALTA_54 pass
2647 14:50:06.176061 alsa_mixer-test_event_spurious_LCALTA_54 pass
2648 14:50:06.176494 alsa_mixer-test_get_value_LCALTA_53 pass
2649 14:50:06.181582 alsa_mixer-test_name_LCALTA_53 pass
2650 14:50:06.187147 alsa_mixer-test_write_default_LCALTA_53 pass
2651 14:50:06.187573 alsa_mixer-test_write_valid_LCALTA_53 pass
2652 14:50:06.192687 alsa_mixer-test_write_invalid_LCALTA_53 pass
2653 14:50:06.198220 alsa_mixer-test_event_missing_LCALTA_53 pass
2654 14:50:06.198649 alsa_mixer-test_event_spurious_LCALTA_53 pass
2655 14:50:06.203771 alsa_mixer-test_get_value_LCALTA_52 pass
2656 14:50:06.209311 alsa_mixer-test_name_LCALTA_52 pass
2657 14:50:06.209741 alsa_mixer-test_write_default_LCALTA_52 pass
2658 14:50:06.214863 alsa_mixer-test_write_valid_LCALTA_52 pass
2659 14:50:06.220398 alsa_mixer-test_write_invalid_LCALTA_52 pass
2660 14:50:06.220833 alsa_mixer-test_event_missing_LCALTA_52 pass
2661 14:50:06.225943 alsa_mixer-test_event_spurious_LCALTA_52 pass
2662 14:50:06.231494 alsa_mixer-test_get_value_LCALTA_51 pass
2663 14:50:06.231927 alsa_mixer-test_name_LCALTA_51 pass
2664 14:50:06.237037 alsa_mixer-test_write_default_LCALTA_51 pass
2665 14:50:06.242620 alsa_mixer-test_write_valid_LCALTA_51 pass
2666 14:50:06.248152 alsa_mixer-test_write_invalid_LCALTA_51 pass
2667 14:50:06.248594 alsa_mixer-test_event_missing_LCALTA_51 pass
2668 14:50:06.253701 alsa_mixer-test_event_spurious_LCALTA_51 pass
2669 14:50:06.259240 alsa_mixer-test_get_value_LCALTA_50 pass
2670 14:50:06.259668 alsa_mixer-test_name_LCALTA_50 pass
2671 14:50:06.264778 alsa_mixer-test_write_default_LCALTA_50 pass
2672 14:50:06.270382 alsa_mixer-test_write_valid_LCALTA_50 pass
2673 14:50:06.270815 alsa_mixer-test_write_invalid_LCALTA_50 pass
2674 14:50:06.275881 alsa_mixer-test_event_missing_LCALTA_50 pass
2675 14:50:06.281520 alsa_mixer-test_event_spurious_LCALTA_50 pass
2676 14:50:06.281958 alsa_mixer-test_get_value_LCALTA_49 pass
2677 14:50:06.287035 alsa_mixer-test_name_LCALTA_49 pass
2678 14:50:06.292574 alsa_mixer-test_write_default_LCALTA_49 pass
2679 14:50:06.293004 alsa_mixer-test_write_valid_LCALTA_49 pass
2680 14:50:06.298129 alsa_mixer-test_write_invalid_LCALTA_49 pass
2681 14:50:06.303657 alsa_mixer-test_event_missing_LCALTA_49 pass
2682 14:50:06.309238 alsa_mixer-test_event_spurious_LCALTA_49 pass
2683 14:50:06.309674 alsa_mixer-test_get_value_LCALTA_48 pass
2684 14:50:06.314752 alsa_mixer-test_name_LCALTA_48 pass
2685 14:50:06.320296 alsa_mixer-test_write_default_LCALTA_48 pass
2686 14:50:06.320727 alsa_mixer-test_write_valid_LCALTA_48 pass
2687 14:50:06.325830 alsa_mixer-test_write_invalid_LCALTA_48 pass
2688 14:50:06.331385 alsa_mixer-test_event_missing_LCALTA_48 pass
2689 14:50:06.331820 alsa_mixer-test_event_spurious_LCALTA_48 pass
2690 14:50:06.336940 alsa_mixer-test_get_value_LCALTA_47 pass
2691 14:50:06.342453 alsa_mixer-test_name_LCALTA_47 pass
2692 14:50:06.342888 alsa_mixer-test_write_default_LCALTA_47 pass
2693 14:50:06.348039 alsa_mixer-test_write_valid_LCALTA_47 pass
2694 14:50:06.353600 alsa_mixer-test_write_invalid_LCALTA_47 pass
2695 14:50:06.359213 alsa_mixer-test_event_missing_LCALTA_47 pass
2696 14:50:06.359677 alsa_mixer-test_event_spurious_LCALTA_47 pass
2697 14:50:06.364678 alsa_mixer-test_get_value_LCALTA_46 pass
2698 14:50:06.365119 alsa_mixer-test_name_LCALTA_46 pass
2699 14:50:06.370195 alsa_mixer-test_write_default_LCALTA_46 pass
2700 14:50:06.375835 alsa_mixer-test_write_valid_LCALTA_46 pass
2701 14:50:06.381299 alsa_mixer-test_write_invalid_LCALTA_46 pass
2702 14:50:06.381730 alsa_mixer-test_event_missing_LCALTA_46 pass
2703 14:50:06.386858 alsa_mixer-test_event_spurious_LCALTA_46 pass
2704 14:50:06.392356 alsa_mixer-test_get_value_LCALTA_45 pass
2705 14:50:06.392793 alsa_mixer-test_name_LCALTA_45 pass
2706 14:50:06.397898 alsa_mixer-test_write_default_LCALTA_45 pass
2707 14:50:06.403452 alsa_mixer-test_write_valid_LCALTA_45 pass
2708 14:50:06.403884 alsa_mixer-test_write_invalid_LCALTA_45 pass
2709 14:50:06.408995 alsa_mixer-test_event_missing_LCALTA_45 pass
2710 14:50:06.414556 alsa_mixer-test_event_spurious_LCALTA_45 pass
2711 14:50:06.420101 alsa_mixer-test_get_value_LCALTA_44 pass
2712 14:50:06.420535 alsa_mixer-test_name_LCALTA_44 pass
2713 14:50:06.425632 alsa_mixer-test_write_default_LCALTA_44 pass
2714 14:50:06.431176 alsa_mixer-test_write_valid_LCALTA_44 pass
2715 14:50:06.431608 alsa_mixer-test_write_invalid_LCALTA_44 pass
2716 14:50:06.436732 alsa_mixer-test_event_missing_LCALTA_44 pass
2717 14:50:06.442285 alsa_mixer-test_event_spurious_LCALTA_44 pass
2718 14:50:06.442717 alsa_mixer-test_get_value_LCALTA_43 pass
2719 14:50:06.447871 alsa_mixer-test_name_LCALTA_43 pass
2720 14:50:06.453392 alsa_mixer-test_write_default_LCALTA_43 pass
2721 14:50:06.453828 alsa_mixer-test_write_valid_LCALTA_43 pass
2722 14:50:06.458938 alsa_mixer-test_write_invalid_LCALTA_43 pass
2723 14:50:06.464468 alsa_mixer-test_event_missing_LCALTA_43 pass
2724 14:50:06.464903 alsa_mixer-test_event_spurious_LCALTA_43 pass
2725 14:50:06.470086 alsa_mixer-test_get_value_LCALTA_42 pass
2726 14:50:06.475584 alsa_mixer-test_name_LCALTA_42 pass
2727 14:50:06.476085 alsa_mixer-test_write_default_LCALTA_42 pass
2728 14:50:06.481108 alsa_mixer-test_write_valid_LCALTA_42 pass
2729 14:50:06.486649 alsa_mixer-test_write_invalid_LCALTA_42 pass
2730 14:50:06.492217 alsa_mixer-test_event_missing_LCALTA_42 pass
2731 14:50:06.492660 alsa_mixer-test_event_spurious_LCALTA_42 pass
2732 14:50:06.497830 alsa_mixer-test_get_value_LCALTA_41 pass
2733 14:50:06.503314 alsa_mixer-test_name_LCALTA_41 pass
2734 14:50:06.503749 alsa_mixer-test_write_default_LCALTA_41 pass
2735 14:50:06.508894 alsa_mixer-test_write_valid_LCALTA_41 pass
2736 14:50:06.514389 alsa_mixer-test_write_invalid_LCALTA_41 pass
2737 14:50:06.514824 alsa_mixer-test_event_missing_LCALTA_41 pass
2738 14:50:06.519949 alsa_mixer-test_event_spurious_LCALTA_41 pass
2739 14:50:06.525483 alsa_mixer-test_get_value_LCALTA_40 pass
2740 14:50:06.525916 alsa_mixer-test_name_LCALTA_40 pass
2741 14:50:06.531029 alsa_mixer-test_write_default_LCALTA_40 pass
2742 14:50:06.536595 alsa_mixer-test_write_valid_LCALTA_40 pass
2743 14:50:06.537024 alsa_mixer-test_write_invalid_LCALTA_40 pass
2744 14:50:06.542165 alsa_mixer-test_event_missing_LCALTA_40 pass
2745 14:50:06.547666 alsa_mixer-test_event_spurious_LCALTA_40 pass
2746 14:50:06.553211 alsa_mixer-test_get_value_LCALTA_39 pass
2747 14:50:06.553644 alsa_mixer-test_name_LCALTA_39 pass
2748 14:50:06.558876 alsa_mixer-test_write_default_LCALTA_39 pass
2749 14:50:06.564329 alsa_mixer-test_write_valid_LCALTA_39 pass
2750 14:50:06.564764 alsa_mixer-test_write_invalid_LCALTA_39 pass
2751 14:50:06.569885 alsa_mixer-test_event_missing_LCALTA_39 pass
2752 14:50:06.575407 alsa_mixer-test_event_spurious_LCALTA_39 pass
2753 14:50:06.575840 alsa_mixer-test_get_value_LCALTA_38 pass
2754 14:50:06.580960 alsa_mixer-test_name_LCALTA_38 pass
2755 14:50:06.586525 alsa_mixer-test_write_default_LCALTA_38 pass
2756 14:50:06.586957 alsa_mixer-test_write_valid_LCALTA_38 pass
2757 14:50:06.592063 alsa_mixer-test_write_invalid_LCALTA_38 pass
2758 14:50:06.597583 alsa_mixer-test_event_missing_LCALTA_38 pass
2759 14:50:06.603148 alsa_mixer-test_event_spurious_LCALTA_38 pass
2760 14:50:06.603577 alsa_mixer-test_get_value_LCALTA_37 pass
2761 14:50:06.608708 alsa_mixer-test_name_LCALTA_37 pass
2762 14:50:06.614266 alsa_mixer-test_write_default_LCALTA_37 pass
2763 14:50:06.614699 alsa_mixer-test_write_valid_LCALTA_37 pass
2764 14:50:06.619832 alsa_mixer-test_write_invalid_LCALTA_37 pass
2765 14:50:06.625347 alsa_mixer-test_event_missing_LCALTA_37 pass
2766 14:50:06.625782 alsa_mixer-test_event_spurious_LCALTA_37 pass
2767 14:50:06.630922 alsa_mixer-test_get_value_LCALTA_36 pass
2768 14:50:06.636432 alsa_mixer-test_name_LCALTA_36 pass
2769 14:50:06.636863 alsa_mixer-test_write_default_LCALTA_36 pass
2770 14:50:06.641951 alsa_mixer-test_write_valid_LCALTA_36 pass
2771 14:50:06.647491 alsa_mixer-test_write_invalid_LCALTA_36 pass
2772 14:50:06.647919 alsa_mixer-test_event_missing_LCALTA_36 pass
2773 14:50:06.653100 alsa_mixer-test_event_spurious_LCALTA_36 pass
2774 14:50:06.658595 alsa_mixer-test_get_value_LCALTA_35 pass
2775 14:50:06.659041 alsa_mixer-test_name_LCALTA_35 pass
2776 14:50:06.664141 alsa_mixer-test_write_default_LCALTA_35 pass
2777 14:50:06.669709 alsa_mixer-test_write_valid_LCALTA_35 pass
2778 14:50:06.675242 alsa_mixer-test_write_invalid_LCALTA_35 pass
2779 14:50:06.675675 alsa_mixer-test_event_missing_LCALTA_35 pass
2780 14:50:06.680834 alsa_mixer-test_event_spurious_LCALTA_35 pass
2781 14:50:06.686352 alsa_mixer-test_get_value_LCALTA_34 pass
2782 14:50:06.686780 alsa_mixer-test_name_LCALTA_34 pass
2783 14:50:06.691894 alsa_mixer-test_write_default_LCALTA_34 pass
2784 14:50:06.697408 alsa_mixer-test_write_valid_LCALTA_34 pass
2785 14:50:06.697845 alsa_mixer-test_write_invalid_LCALTA_34 pass
2786 14:50:06.702963 alsa_mixer-test_event_missing_LCALTA_34 pass
2787 14:50:06.708536 alsa_mixer-test_event_spurious_LCALTA_34 pass
2788 14:50:06.708969 alsa_mixer-test_get_value_LCALTA_33 pass
2789 14:50:06.714059 alsa_mixer-test_name_LCALTA_33 pass
2790 14:50:06.719630 alsa_mixer-test_write_default_LCALTA_33 pass
2791 14:50:06.720117 alsa_mixer-test_write_valid_LCALTA_33 pass
2792 14:50:06.725157 alsa_mixer-test_write_invalid_LCALTA_33 pass
2793 14:50:06.730725 alsa_mixer-test_event_missing_LCALTA_33 pass
2794 14:50:06.736247 alsa_mixer-test_event_spurious_LCALTA_33 pass
2795 14:50:06.736682 alsa_mixer-test_get_value_LCALTA_32 pass
2796 14:50:06.741838 alsa_mixer-test_name_LCALTA_32 pass
2797 14:50:06.747342 alsa_mixer-test_write_default_LCALTA_32 pass
2798 14:50:06.747774 alsa_mixer-test_write_valid_LCALTA_32 pass
2799 14:50:06.752895 alsa_mixer-test_write_invalid_LCALTA_32 pass
2800 14:50:06.758427 alsa_mixer-test_event_missing_LCALTA_32 pass
2801 14:50:06.758860 alsa_mixer-test_event_spurious_LCALTA_32 pass
2802 14:50:06.764000 alsa_mixer-test_get_value_LCALTA_31 pass
2803 14:50:06.769530 alsa_mixer-test_name_LCALTA_31 pass
2804 14:50:06.769958 alsa_mixer-test_write_default_LCALTA_31 pass
2805 14:50:06.775091 alsa_mixer-test_write_valid_LCALTA_31 pass
2806 14:50:06.780627 alsa_mixer-test_write_invalid_LCALTA_31 pass
2807 14:50:06.786180 alsa_mixer-test_event_missing_LCALTA_31 pass
2808 14:50:06.786608 alsa_mixer-test_event_spurious_LCALTA_31 pass
2809 14:50:06.791737 alsa_mixer-test_get_value_LCALTA_30 pass
2810 14:50:06.792197 alsa_mixer-test_name_LCALTA_30 pass
2811 14:50:06.797267 alsa_mixer-test_write_default_LCALTA_30 pass
2812 14:50:06.802839 alsa_mixer-test_write_valid_LCALTA_30 pass
2813 14:50:06.808337 alsa_mixer-test_write_invalid_LCALTA_30 pass
2814 14:50:06.808774 alsa_mixer-test_event_missing_LCALTA_30 pass
2815 14:50:06.813911 alsa_mixer-test_event_spurious_LCALTA_30 pass
2816 14:50:06.819484 alsa_mixer-test_get_value_LCALTA_29 pass
2817 14:50:06.819917 alsa_mixer-test_name_LCALTA_29 pass
2818 14:50:06.824996 alsa_mixer-test_write_default_LCALTA_29 pass
2819 14:50:06.830540 alsa_mixer-test_write_valid_LCALTA_29 pass
2820 14:50:06.830968 alsa_mixer-test_write_invalid_LCALTA_29 pass
2821 14:50:06.836221 alsa_mixer-test_event_missing_LCALTA_29 pass
2822 14:50:06.841816 alsa_mixer-test_event_spurious_LCALTA_29 pass
2823 14:50:06.847278 alsa_mixer-test_get_value_LCALTA_28 pass
2824 14:50:06.847706 alsa_mixer-test_name_LCALTA_28 pass
2825 14:50:06.852864 alsa_mixer-test_write_default_LCALTA_28 pass
2826 14:50:06.858407 alsa_mixer-test_write_valid_LCALTA_28 pass
2827 14:50:06.858841 alsa_mixer-test_write_invalid_LCALTA_28 pass
2828 14:50:06.863972 alsa_mixer-test_event_missing_LCALTA_28 pass
2829 14:50:06.869466 alsa_mixer-test_event_spurious_LCALTA_28 pass
2830 14:50:06.869899 alsa_mixer-test_get_value_LCALTA_27 pass
2831 14:50:06.875002 alsa_mixer-test_name_LCALTA_27 pass
2832 14:50:06.880575 alsa_mixer-test_write_default_LCALTA_27 pass
2833 14:50:06.881004 alsa_mixer-test_write_valid_LCALTA_27 pass
2834 14:50:06.886097 alsa_mixer-test_write_invalid_LCALTA_27 pass
2835 14:50:06.891623 alsa_mixer-test_event_missing_LCALTA_27 pass
2836 14:50:06.892076 alsa_mixer-test_event_spurious_LCALTA_27 pass
2837 14:50:06.897190 alsa_mixer-test_get_value_LCALTA_26 pass
2838 14:50:06.902736 alsa_mixer-test_name_LCALTA_26 pass
2839 14:50:06.903169 alsa_mixer-test_write_default_LCALTA_26 skip
2840 14:50:06.908274 alsa_mixer-test_write_valid_LCALTA_26 skip
2841 14:50:06.913835 alsa_mixer-test_write_invalid_LCALTA_26 skip
2842 14:50:06.919370 alsa_mixer-test_event_missing_LCALTA_26 pass
2843 14:50:06.919804 alsa_mixer-test_event_spurious_LCALTA_26 pass
2844 14:50:06.924951 alsa_mixer-test_get_value_LCALTA_25 pass
2845 14:50:06.930425 alsa_mixer-test_name_LCALTA_25 pass
2846 14:50:06.930860 alsa_mixer-test_write_default_LCALTA_25 pass
2847 14:50:06.936012 alsa_mixer-test_write_valid_LCALTA_25 skip
2848 14:50:06.941548 alsa_mixer-test_write_invalid_LCALTA_25 skip
2849 14:50:06.941976 alsa_mixer-test_event_missing_LCALTA_25 pass
2850 14:50:06.947121 alsa_mixer-test_event_spurious_LCALTA_25 pass
2851 14:50:06.952656 alsa_mixer-test_get_value_LCALTA_24 pass
2852 14:50:06.953092 alsa_mixer-test_name_LCALTA_24 pass
2853 14:50:06.958208 alsa_mixer-test_write_default_LCALTA_24 skip
2854 14:50:06.963777 alsa_mixer-test_write_valid_LCALTA_24 skip
2855 14:50:06.964237 alsa_mixer-test_write_invalid_LCALTA_24 skip
2856 14:50:06.969293 alsa_mixer-test_event_missing_LCALTA_24 pass
2857 14:50:06.974837 alsa_mixer-test_event_spurious_LCALTA_24 pass
2858 14:50:06.980390 alsa_mixer-test_get_value_LCALTA_23 pass
2859 14:50:06.980816 alsa_mixer-test_name_LCALTA_23 pass
2860 14:50:06.985969 alsa_mixer-test_write_default_LCALTA_23 skip
2861 14:50:06.991495 alsa_mixer-test_write_valid_LCALTA_23 skip
2862 14:50:06.991923 alsa_mixer-test_write_invalid_LCALTA_23 skip
2863 14:50:06.997023 alsa_mixer-test_event_missing_LCALTA_23 pass
2864 14:50:07.002574 alsa_mixer-test_event_spurious_LCALTA_23 pass
2865 14:50:07.003004 alsa_mixer-test_get_value_LCALTA_22 pass
2866 14:50:07.008134 alsa_mixer-test_name_LCALTA_22 pass
2867 14:50:07.013684 alsa_mixer-test_write_default_LCALTA_22 pass
2868 14:50:07.014114 alsa_mixer-test_write_valid_LCALTA_22 pass
2869 14:50:07.019216 alsa_mixer-test_write_invalid_LCALTA_22 pass
2870 14:50:07.024734 alsa_mixer-test_event_missing_LCALTA_22 pass
2871 14:50:07.030308 alsa_mixer-test_event_spurious_LCALTA_22 pass
2872 14:50:07.030738 alsa_mixer-test_get_value_LCALTA_21 pass
2873 14:50:07.035877 alsa_mixer-test_name_LCALTA_21 pass
2874 14:50:07.041402 alsa_mixer-test_write_default_LCALTA_21 pass
2875 14:50:07.041840 alsa_mixer-test_write_valid_LCALTA_21 pass
2876 14:50:07.046982 alsa_mixer-test_write_invalid_LCALTA_21 pass
2877 14:50:07.052604 alsa_mixer-test_event_missing_LCALTA_21 pass
2878 14:50:07.053035 alsa_mixer-test_event_spurious_LCALTA_21 pass
2879 14:50:07.058058 alsa_mixer-test_get_value_LCALTA_20 pass
2880 14:50:07.063680 alsa_mixer-test_name_LCALTA_20 pass
2881 14:50:07.064136 alsa_mixer-test_write_default_LCALTA_20 pass
2882 14:50:07.069252 alsa_mixer-test_write_valid_LCALTA_20 pass
2883 14:50:07.074757 alsa_mixer-test_write_invalid_LCALTA_20 pass
2884 14:50:07.075190 alsa_mixer-test_event_missing_LCALTA_20 pass
2885 14:50:07.080310 alsa_mixer-test_event_spurious_LCALTA_20 pass
2886 14:50:07.085831 alsa_mixer-test_get_value_LCALTA_19 pass
2887 14:50:07.086262 alsa_mixer-test_name_LCALTA_19 pass
2888 14:50:07.091376 alsa_mixer-test_write_default_LCALTA_19 pass
2889 14:50:07.096940 alsa_mixer-test_write_valid_LCALTA_19 pass
2890 14:50:07.102509 alsa_mixer-test_write_invalid_LCALTA_19 pass
2891 14:50:07.102945 alsa_mixer-test_event_missing_LCALTA_19 pass
2892 14:50:07.108067 alsa_mixer-test_event_spurious_LCALTA_19 pass
2893 14:50:07.113573 alsa_mixer-test_get_value_LCALTA_18 pass
2894 14:50:07.114007 alsa_mixer-test_name_LCALTA_18 pass
2895 14:50:07.119112 alsa_mixer-test_write_default_LCALTA_18 pass
2896 14:50:07.124676 alsa_mixer-test_write_valid_LCALTA_18 pass
2897 14:50:07.125130 alsa_mixer-test_write_invalid_LCALTA_18 pass
2898 14:50:07.130178 alsa_mixer-test_event_missing_LCALTA_18 pass
2899 14:50:07.135741 alsa_mixer-test_event_spurious_LCALTA_18 pass
2900 14:50:07.136208 alsa_mixer-test_get_value_LCALTA_17 pass
2901 14:50:07.141291 alsa_mixer-test_name_LCALTA_17 pass
2902 14:50:07.146857 alsa_mixer-test_write_default_LCALTA_17 pass
2903 14:50:07.147289 alsa_mixer-test_write_valid_LCALTA_17 pass
2904 14:50:07.152339 alsa_mixer-test_write_invalid_LCALTA_17 pass
2905 14:50:07.157886 alsa_mixer-test_event_missing_LCALTA_17 pass
2906 14:50:07.163434 alsa_mixer-test_event_spurious_LCALTA_17 pass
2907 14:50:07.163865 alsa_mixer-test_get_value_LCALTA_16 pass
2908 14:50:07.168996 alsa_mixer-test_name_LCALTA_16 pass
2909 14:50:07.174575 alsa_mixer-test_write_default_LCALTA_16 pass
2910 14:50:07.175008 alsa_mixer-test_write_valid_LCALTA_16 pass
2911 14:50:07.180104 alsa_mixer-test_write_invalid_LCALTA_16 pass
2912 14:50:07.185597 alsa_mixer-test_event_missing_LCALTA_16 pass
2913 14:50:07.186034 alsa_mixer-test_event_spurious_LCALTA_16 pass
2914 14:50:07.191169 alsa_mixer-test_get_value_LCALTA_15 pass
2915 14:50:07.196727 alsa_mixer-test_name_LCALTA_15 pass
2916 14:50:07.197170 alsa_mixer-test_write_default_LCALTA_15 pass
2917 14:50:07.202275 alsa_mixer-test_write_valid_LCALTA_15 pass
2918 14:50:07.207807 alsa_mixer-test_write_invalid_LCALTA_15 pass
2919 14:50:07.213415 alsa_mixer-test_event_missing_LCALTA_15 pass
2920 14:50:07.213872 alsa_mixer-test_event_spurious_LCALTA_15 pass
2921 14:50:07.218914 alsa_mixer-test_get_value_LCALTA_14 pass
2922 14:50:07.219352 alsa_mixer-test_name_LCALTA_14 pass
2923 14:50:07.224453 alsa_mixer-test_write_default_LCALTA_14 pass
2924 14:50:07.229963 alsa_mixer-test_write_valid_LCALTA_14 pass
2925 14:50:07.235544 alsa_mixer-test_write_invalid_LCALTA_14 pass
2926 14:50:07.236015 alsa_mixer-test_event_missing_LCALTA_14 pass
2927 14:50:07.241082 alsa_mixer-test_event_spurious_LCALTA_14 pass
2928 14:50:07.246633 alsa_mixer-test_get_value_LCALTA_13 pass
2929 14:50:07.247080 alsa_mixer-test_name_LCALTA_13 pass
2930 14:50:07.252200 alsa_mixer-test_write_default_LCALTA_13 pass
2931 14:50:07.257739 alsa_mixer-test_write_valid_LCALTA_13 pass
2932 14:50:07.258180 alsa_mixer-test_write_invalid_LCALTA_13 pass
2933 14:50:07.263265 alsa_mixer-test_event_missing_LCALTA_13 pass
2934 14:50:07.268835 alsa_mixer-test_event_spurious_LCALTA_13 pass
2935 14:50:07.274376 alsa_mixer-test_get_value_LCALTA_12 pass
2936 14:50:07.274822 alsa_mixer-test_name_LCALTA_12 pass
2937 14:50:07.279896 alsa_mixer-test_write_default_LCALTA_12 pass
2938 14:50:07.285482 alsa_mixer-test_write_valid_LCALTA_12 pass
2939 14:50:07.285913 alsa_mixer-test_write_invalid_LCALTA_12 pass
2940 14:50:07.291006 alsa_mixer-test_event_missing_LCALTA_12 pass
2941 14:50:07.296559 alsa_mixer-test_event_spurious_LCALTA_12 pass
2942 14:50:07.297007 alsa_mixer-test_get_value_LCALTA_11 pass
2943 14:50:07.302055 alsa_mixer-test_name_LCALTA_11 pass
2944 14:50:07.307649 alsa_mixer-test_write_default_LCALTA_11 pass
2945 14:50:07.308101 alsa_mixer-test_write_valid_LCALTA_11 pass
2946 14:50:07.313194 alsa_mixer-test_write_invalid_LCALTA_11 pass
2947 14:50:07.318753 alsa_mixer-test_event_missing_LCALTA_11 pass
2948 14:50:07.319187 alsa_mixer-test_event_spurious_LCALTA_11 pass
2949 14:50:07.324293 alsa_mixer-test_get_value_LCALTA_10 pass
2950 14:50:07.329812 alsa_mixer-test_name_LCALTA_10 pass
2951 14:50:07.330244 alsa_mixer-test_write_default_LCALTA_10 pass
2952 14:50:07.335393 alsa_mixer-test_write_valid_LCALTA_10 pass
2953 14:50:07.340910 alsa_mixer-test_write_invalid_LCALTA_10 pass
2954 14:50:07.346480 alsa_mixer-test_event_missing_LCALTA_10 pass
2955 14:50:07.346915 alsa_mixer-test_event_spurious_LCALTA_10 pass
2956 14:50:07.352030 alsa_mixer-test_get_value_LCALTA_9 pass
2957 14:50:07.357556 alsa_mixer-test_name_LCALTA_9 pass
2958 14:50:07.357993 alsa_mixer-test_write_default_LCALTA_9 pass
2959 14:50:07.363166 alsa_mixer-test_write_valid_LCALTA_9 pass
2960 14:50:07.368675 alsa_mixer-test_write_invalid_LCALTA_9 pass
2961 14:50:07.369116 alsa_mixer-test_event_missing_LCALTA_9 pass
2962 14:50:07.374206 alsa_mixer-test_event_spurious_LCALTA_9 pass
2963 14:50:07.379759 alsa_mixer-test_get_value_LCALTA_8 pass
2964 14:50:07.380214 alsa_mixer-test_name_LCALTA_8 pass
2965 14:50:07.385290 alsa_mixer-test_write_default_LCALTA_8 pass
2966 14:50:07.390823 alsa_mixer-test_write_valid_LCALTA_8 pass
2967 14:50:07.391256 alsa_mixer-test_write_invalid_LCALTA_8 pass
2968 14:50:07.396373 alsa_mixer-test_event_missing_LCALTA_8 pass
2969 14:50:07.401904 alsa_mixer-test_event_spurious_LCALTA_8 pass
2970 14:50:07.402341 alsa_mixer-test_get_value_LCALTA_7 pass
2971 14:50:07.407460 alsa_mixer-test_name_LCALTA_7 pass
2972 14:50:07.413004 alsa_mixer-test_write_default_LCALTA_7 pass
2973 14:50:07.413437 alsa_mixer-test_write_valid_LCALTA_7 pass
2974 14:50:07.418560 alsa_mixer-test_write_invalid_LCALTA_7 pass
2975 14:50:07.424091 alsa_mixer-test_event_missing_LCALTA_7 pass
2976 14:50:07.424524 alsa_mixer-test_event_spurious_LCALTA_7 pass
2977 14:50:07.429661 alsa_mixer-test_get_value_LCALTA_6 pass
2978 14:50:07.435201 alsa_mixer-test_name_LCALTA_6 pass
2979 14:50:07.435633 alsa_mixer-test_write_default_LCALTA_6 pass
2980 14:50:07.440763 alsa_mixer-test_write_valid_LCALTA_6 pass
2981 14:50:07.446316 alsa_mixer-test_write_invalid_LCALTA_6 pass
2982 14:50:07.446754 alsa_mixer-test_event_missing_LCALTA_6 pass
2983 14:50:07.451848 alsa_mixer-test_event_spurious_LCALTA_6 pass
2984 14:50:07.457409 alsa_mixer-test_get_value_LCALTA_5 pass
2985 14:50:07.457841 alsa_mixer-test_name_LCALTA_5 pass
2986 14:50:07.463028 alsa_mixer-test_write_default_LCALTA_5 pass
2987 14:50:07.468497 alsa_mixer-test_write_valid_LCALTA_5 pass
2988 14:50:07.468926 alsa_mixer-test_write_invalid_LCALTA_5 pass
2989 14:50:07.474041 alsa_mixer-test_event_missing_LCALTA_5 pass
2990 14:50:07.479562 alsa_mixer-test_event_spurious_LCALTA_5 pass
2991 14:50:07.480014 alsa_mixer-test_get_value_LCALTA_4 pass
2992 14:50:07.485139 alsa_mixer-test_name_LCALTA_4 pass
2993 14:50:07.490672 alsa_mixer-test_write_default_LCALTA_4 pass
2994 14:50:07.491101 alsa_mixer-test_write_valid_LCALTA_4 pass
2995 14:50:07.496221 alsa_mixer-test_write_invalid_LCALTA_4 pass
2996 14:50:07.501767 alsa_mixer-test_event_missing_LCALTA_4 pass
2997 14:50:07.507323 alsa_mixer-test_event_spurious_LCALTA_4 pass
2998 14:50:07.507750 alsa_mixer-test_get_value_LCALTA_3 pass
2999 14:50:07.512867 alsa_mixer-test_name_LCALTA_3 pass
3000 14:50:07.513296 alsa_mixer-test_write_default_LCALTA_3 pass
3001 14:50:07.518422 alsa_mixer-test_write_valid_LCALTA_3 pass
3002 14:50:07.523966 alsa_mixer-test_write_invalid_LCALTA_3 pass
3003 14:50:07.529499 alsa_mixer-test_event_missing_LCALTA_3 pass
3004 14:50:07.529935 alsa_mixer-test_event_spurious_LCALTA_3 pass
3005 14:50:07.535086 alsa_mixer-test_get_value_LCALTA_2 pass
3006 14:50:07.535517 alsa_mixer-test_name_LCALTA_2 pass
3007 14:50:07.540591 alsa_mixer-test_write_default_LCALTA_2 pass
3008 14:50:07.546150 alsa_mixer-test_write_valid_LCALTA_2 pass
3009 14:50:07.551691 alsa_mixer-test_write_invalid_LCALTA_2 pass
3010 14:50:07.552156 alsa_mixer-test_event_missing_LCALTA_2 pass
3011 14:50:07.557244 alsa_mixer-test_event_spurious_LCALTA_2 pass
3012 14:50:07.562794 alsa_mixer-test_get_value_LCALTA_1 pass
3013 14:50:07.563219 alsa_mixer-test_name_LCALTA_1 pass
3014 14:50:07.568339 alsa_mixer-test_write_default_LCALTA_1 pass
3015 14:50:07.573875 alsa_mixer-test_write_valid_LCALTA_1 pass
3016 14:50:07.574301 alsa_mixer-test_write_invalid_LCALTA_1 pass
3017 14:50:07.579421 alsa_mixer-test_event_missing_LCALTA_1 pass
3018 14:50:07.585058 alsa_mixer-test_event_spurious_LCALTA_1 pass
3019 14:50:07.585492 alsa_mixer-test_get_value_LCALTA_0 pass
3020 14:50:07.590521 alsa_mixer-test_name_LCALTA_0 pass
3021 14:50:07.596099 alsa_mixer-test_write_default_LCALTA_0 pass
3022 14:50:07.596527 alsa_mixer-test_write_valid_LCALTA_0 pass
3023 14:50:07.601617 alsa_mixer-test_write_invalid_LCALTA_0 pass
3024 14:50:07.607190 alsa_mixer-test_event_missing_LCALTA_0 pass
3025 14:50:07.607626 alsa_mixer-test_event_spurious_LCALTA_0 pass
3026 14:50:07.612713 alsa_mixer-test pass
3027 14:50:07.618231 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
3028 14:50:07.618666 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
3029 14:50:07.623774 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
3030 14:50:07.629340 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
3031 14:50:07.634919 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
3032 14:50:07.640449 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
3033 14:50:07.640879 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
3034 14:50:07.646052 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
3035 14:50:07.651552 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
3036 14:50:07.657142 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
3037 14:50:07.662628 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
3038 14:50:07.668261 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
3039 14:50:07.668705 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
3040 14:50:07.673760 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
3041 14:50:07.679283 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
3042 14:50:07.684825 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
3043 14:50:07.690345 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
3044 14:50:07.695905 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
3045 14:50:07.696369 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
3046 14:50:07.701462 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
3047 14:50:07.707070 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
3048 14:50:07.712567 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
3049 14:50:07.718077 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
3050 14:50:07.723636 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
3051 14:50:07.724128 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
3052 14:50:07.729162 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
3053 14:50:07.734713 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
3054 14:50:07.740278 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
3055 14:50:07.745790 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
3056 14:50:07.751300 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
3057 14:50:07.756857 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
3058 14:50:07.757305 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
3059 14:50:07.762378 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
3060 14:50:07.768023 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
3061 14:50:07.773487 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
3062 14:50:07.779038 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
3063 14:50:07.784593 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
3064 14:50:07.785030 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
3065 14:50:07.790103 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
3066 14:50:07.795655 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
3067 14:50:07.801235 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
3068 14:50:07.806795 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
3069 14:50:07.807230 alsa_pcm-test pass
3070 14:50:07.817860 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3071 14:50:07.823403 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3072 14:50:07.834593 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3073 14:50:07.840179 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3074 14:50:07.851181 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3075 14:50:07.851630 alsa_test-pcmtest-driver pass
3076 14:50:07.856763 alsa_utimer-test_global_wrong_timers_test pass
3077 14:50:07.862271 alsa_utimer-test_timer_f_utimer fail
3078 14:50:07.862708 alsa_utimer-test fail
3079 14:50:07.867806 + ../../utils/send-to-lava.sh ./output/result.txt
3080 14:50:07.873362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
3081 14:50:07.874236 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
3083 14:50:07.878942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
3084 14:50:07.879632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
3086 14:50:07.886762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
3087 14:50:07.887448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
3089 14:50:07.905225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
3090 14:50:07.905942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
3092 14:50:07.949837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
3093 14:50:07.950560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
3095 14:50:07.993604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
3096 14:50:07.994396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
3098 14:50:08.044889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
3099 14:50:08.045650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
3101 14:50:08.090576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
3102 14:50:08.091332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
3104 14:50:08.135122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
3105 14:50:08.135820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
3107 14:50:08.180072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
3108 14:50:08.180820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
3110 14:50:08.225591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
3111 14:50:08.226304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
3113 14:50:08.271270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
3114 14:50:08.272029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
3116 14:50:08.317987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
3117 14:50:08.318681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
3119 14:50:08.362313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
3120 14:50:08.362878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
3122 14:50:08.409116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
3123 14:50:08.409712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
3125 14:50:08.452075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
3126 14:50:08.452655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
3128 14:50:08.498967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
3129 14:50:08.499570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
3131 14:50:08.543671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
3132 14:50:08.544313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
3134 14:50:08.588898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
3135 14:50:08.589697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
3137 14:50:08.632491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
3138 14:50:08.633263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
3140 14:50:08.675593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
3141 14:50:08.676416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
3143 14:50:08.727125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
3144 14:50:08.727916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
3146 14:50:08.774328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
3147 14:50:08.775121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
3149 14:50:08.818589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
3150 14:50:08.819380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
3152 14:50:08.871846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
3153 14:50:08.872669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
3155 14:50:08.920887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3156 14:50:08.921663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3158 14:50:08.965445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3159 14:50:08.966252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3161 14:50:09.015688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3162 14:50:09.016515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3164 14:50:09.066381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3165 14:50:09.067164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3167 14:50:09.109199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3168 14:50:09.109979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3170 14:50:09.160778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3171 14:50:09.161558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3173 14:50:09.212770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3174 14:50:09.213717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3176 14:50:09.264332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3177 14:50:09.265226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3179 14:50:09.327057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3180 14:50:09.327918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3182 14:50:09.370854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3183 14:50:09.371674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3185 14:50:09.413149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3186 14:50:09.413960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3188 14:50:09.457204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3189 14:50:09.457983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3191 14:50:09.512785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3192 14:50:09.513553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3194 14:50:09.567199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3195 14:50:09.567976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3197 14:50:09.610699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3198 14:50:09.611461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3200 14:50:09.661631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3201 14:50:09.662404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3203 14:50:09.719752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3204 14:50:09.720575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3206 14:50:09.763482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3207 14:50:09.764274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3209 14:50:09.813484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3210 14:50:09.814248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3212 14:50:09.858532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3213 14:50:09.859288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3215 14:50:09.906505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3216 14:50:09.907266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3218 14:50:09.955936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3219 14:50:09.956734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3221 14:50:10.004254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3222 14:50:10.005023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3224 14:50:10.054209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3225 14:50:10.054969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3227 14:50:10.098102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3228 14:50:10.098865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3230 14:50:10.153804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3231 14:50:10.154560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3233 14:50:10.198375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3234 14:50:10.199138 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3236 14:50:10.253456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3237 14:50:10.254205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3239 14:50:10.300083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3240 14:50:10.300843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3242 14:50:10.352041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3243 14:50:10.352805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3245 14:50:10.402354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3246 14:50:10.403110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3248 14:50:10.446563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3249 14:50:10.447306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3251 14:50:10.498146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3252 14:50:10.498937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3254 14:50:10.545826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3255 14:50:10.546664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3257 14:50:10.591626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3258 14:50:10.592458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3260 14:50:10.641320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3261 14:50:10.642110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3263 14:50:10.690896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3264 14:50:10.691692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3266 14:50:10.739645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3267 14:50:10.740477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3269 14:50:10.790079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3270 14:50:10.790872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3272 14:50:10.835224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3273 14:50:10.835842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3275 14:50:10.884209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3276 14:50:10.884988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3278 14:50:10.929869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3279 14:50:10.930609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3281 14:50:10.973799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3282 14:50:10.974564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3284 14:50:11.018051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3285 14:50:11.018797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3287 14:50:11.062151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3288 14:50:11.062891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3290 14:50:11.107469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3291 14:50:11.108210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3293 14:50:11.152747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3294 14:50:11.153482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3296 14:50:11.195804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3297 14:50:11.196575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3299 14:50:11.242485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3300 14:50:11.243219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3302 14:50:11.286516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3303 14:50:11.287270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3305 14:50:11.330976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3306 14:50:11.331703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3308 14:50:11.374143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3309 14:50:11.374881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3311 14:50:11.419596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3312 14:50:11.420360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3314 14:50:11.463155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3315 14:50:11.463881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3317 14:50:11.507344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3318 14:50:11.508074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3320 14:50:11.553005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3321 14:50:11.553725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3323 14:50:11.610972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3324 14:50:11.611714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3326 14:50:11.654836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3327 14:50:11.655561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3329 14:50:11.698016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3330 14:50:11.698745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3332 14:50:11.745741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3333 14:50:11.746470 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3335 14:50:11.792908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3336 14:50:11.793637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3338 14:50:11.840324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3339 14:50:11.841042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3341 14:50:11.893087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3342 14:50:11.893816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3344 14:50:11.938654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3345 14:50:11.939379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3347 14:50:11.983208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3348 14:50:11.983955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3350 14:50:12.029671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3351 14:50:12.030410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3353 14:50:12.075070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3354 14:50:12.075808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3356 14:50:12.119361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3357 14:50:12.120088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3359 14:50:12.162258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3360 14:50:12.162982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3362 14:50:12.206473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3363 14:50:12.207202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3365 14:50:12.250177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3366 14:50:12.250892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3368 14:50:12.303964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3369 14:50:12.304720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3371 14:50:12.351506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3372 14:50:12.352251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3374 14:50:12.401053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3375 14:50:12.401773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3377 14:50:12.442567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3378 14:50:12.443285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3380 14:50:12.487347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3381 14:50:12.488094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3383 14:50:12.531149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3384 14:50:12.531868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3386 14:50:12.574321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3387 14:50:12.575085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3389 14:50:12.620275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3390 14:50:12.621028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3392 14:50:12.666230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3393 14:50:12.666979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3395 14:50:12.716719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3396 14:50:12.717499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3398 14:50:12.766326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3399 14:50:12.767120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3401 14:50:12.810457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3402 14:50:12.811226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3404 14:50:12.858156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3405 14:50:12.858926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3407 14:50:12.909062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3408 14:50:12.909812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3410 14:50:12.954049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3411 14:50:12.954805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3413 14:50:13.001299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3414 14:50:13.002107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3416 14:50:13.044586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3417 14:50:13.045313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3419 14:50:13.088287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3420 14:50:13.089008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3422 14:50:13.131263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3423 14:50:13.132023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3425 14:50:13.178474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3426 14:50:13.179202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3428 14:50:13.228202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3429 14:50:13.228928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3431 14:50:13.282453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3432 14:50:13.283211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3434 14:50:13.329612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3435 14:50:13.330369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3437 14:50:13.374349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3438 14:50:13.375126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3440 14:50:13.418703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3441 14:50:13.419460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3443 14:50:13.464273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3444 14:50:13.465128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3446 14:50:13.515612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3447 14:50:13.516492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3449 14:50:13.563804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3450 14:50:13.564716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3452 14:50:13.611974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3453 14:50:13.612869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3455 14:50:13.661169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3456 14:50:13.662032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3458 14:50:13.710303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3459 14:50:13.711272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3461 14:50:13.760899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3462 14:50:13.761761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3464 14:50:13.805676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3465 14:50:13.806525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3467 14:50:13.852522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3468 14:50:13.853399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3470 14:50:13.896316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3471 14:50:13.897107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3473 14:50:13.940321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3474 14:50:13.941109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3476 14:50:14.027461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3477 14:50:14.028378 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3479 14:50:14.078407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3480 14:50:14.079251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3482 14:50:14.127478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3483 14:50:14.128352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3485 14:50:14.180434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3486 14:50:14.181440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3488 14:50:14.224827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3489 14:50:14.225733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3491 14:50:14.275785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3492 14:50:14.276675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3494 14:50:14.322530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3495 14:50:14.323499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3497 14:50:14.387817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3498 14:50:14.388787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3500 14:50:14.439202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3501 14:50:14.440102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3503 14:50:14.509559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3504 14:50:14.510388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3506 14:50:14.555859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3507 14:50:14.556646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3509 14:50:14.603281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3510 14:50:14.604049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3512 14:50:14.652638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3513 14:50:14.653373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3515 14:50:14.699181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3516 14:50:14.699930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3518 14:50:14.745116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3519 14:50:14.745853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3521 14:50:14.790923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3522 14:50:14.791657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3524 14:50:14.839511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3525 14:50:14.840284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3527 14:50:14.884433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3528 14:50:14.885156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3530 14:50:14.929816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3531 14:50:14.930537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3533 14:50:14.975207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3534 14:50:14.975931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3536 14:50:15.022748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3537 14:50:15.023476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3539 14:50:15.069398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3540 14:50:15.070124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3542 14:50:15.115881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3543 14:50:15.116651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3545 14:50:15.161284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3546 14:50:15.162023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3548 14:50:15.207332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3549 14:50:15.208076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3551 14:50:15.257495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3552 14:50:15.258237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3554 14:50:15.302397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3555 14:50:15.303124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3557 14:50:15.349997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3558 14:50:15.350725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3560 14:50:15.396667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3561 14:50:15.397396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3563 14:50:15.441748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3564 14:50:15.442467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3566 14:50:15.487213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3567 14:50:15.487942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3569 14:50:15.532215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3570 14:50:15.532943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3572 14:50:15.576758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3573 14:50:15.577505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3575 14:50:15.629296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3576 14:50:15.630049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3578 14:50:15.675077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3579 14:50:15.675821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3581 14:50:15.722614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3582 14:50:15.723350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3584 14:50:15.768838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3585 14:50:15.769573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3587 14:50:15.816734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3588 14:50:15.817483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3590 14:50:15.864655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3591 14:50:15.865376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3593 14:50:15.910089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3594 14:50:15.910827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3596 14:50:15.963229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3597 14:50:15.963977 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3599 14:50:16.009902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3600 14:50:16.010625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3602 14:50:16.053639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3603 14:50:16.054367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3605 14:50:16.098691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3606 14:50:16.099416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3608 14:50:16.142537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3609 14:50:16.143251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3611 14:50:16.187130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3612 14:50:16.187865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3614 14:50:16.232848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3615 14:50:16.233580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3617 14:50:16.278163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3618 14:50:16.278891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3620 14:50:16.322574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3621 14:50:16.323316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3623 14:50:16.368264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3624 14:50:16.368993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3626 14:50:16.413448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3627 14:50:16.414190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3629 14:50:16.466047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3630 14:50:16.466774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3632 14:50:16.512242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3633 14:50:16.512992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3635 14:50:16.557750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3636 14:50:16.558502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3638 14:50:16.601203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3639 14:50:16.601958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3641 14:50:16.653081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3642 14:50:16.653814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3644 14:50:16.705575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3645 14:50:16.706352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3647 14:50:16.758055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3648 14:50:16.758799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3650 14:50:16.801880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3651 14:50:16.802613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3653 14:50:16.851452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3654 14:50:16.852216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3656 14:50:16.897314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3657 14:50:16.898051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3659 14:50:16.943624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3660 14:50:16.944392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3662 14:50:16.990825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3663 14:50:16.991569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3665 14:50:17.035098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3666 14:50:17.035832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3668 14:50:17.080788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3669 14:50:17.081519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3671 14:50:17.125212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3672 14:50:17.125946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3674 14:50:17.172385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3675 14:50:17.173114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3677 14:50:17.219359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3678 14:50:17.220088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3680 14:50:17.265476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3681 14:50:17.266204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3683 14:50:17.311238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3684 14:50:17.311970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3686 14:50:17.357129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3687 14:50:17.357864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3689 14:50:17.403529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3690 14:50:17.404298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3692 14:50:17.448825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3693 14:50:17.449551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3695 14:50:17.492245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3696 14:50:17.492983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3698 14:50:17.548579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3699 14:50:17.549310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3701 14:50:17.595975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3702 14:50:17.596767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3704 14:50:17.651346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3705 14:50:17.652076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3707 14:50:17.698542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3708 14:50:17.699267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3710 14:50:17.751274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3711 14:50:17.752064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3713 14:50:17.796055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3714 14:50:17.796795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3716 14:50:17.842349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3717 14:50:17.843085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3719 14:50:17.896898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3720 14:50:17.897773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3722 14:50:17.949664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3723 14:50:17.950429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3725 14:50:17.999871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3726 14:50:18.000652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3728 14:50:18.051603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3729 14:50:18.052401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3731 14:50:18.100250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3732 14:50:18.100973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3734 14:50:18.153224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3735 14:50:18.153934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3737 14:50:18.202898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3738 14:50:18.203650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3740 14:50:18.247024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3741 14:50:18.247745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3743 14:50:18.305763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3744 14:50:18.306523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3746 14:50:18.350781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3747 14:50:18.351518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3749 14:50:18.405432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3750 14:50:18.406168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3752 14:50:18.458860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3753 14:50:18.459627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3755 14:50:18.512085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3756 14:50:18.512840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3758 14:50:18.561944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3759 14:50:18.562678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3761 14:50:18.611273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3762 14:50:18.612038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3764 14:50:18.662111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3765 14:50:18.662842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3767 14:50:18.708620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3768 14:50:18.709355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3770 14:50:18.760814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3771 14:50:18.761565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3773 14:50:18.812993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3774 14:50:18.813730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3776 14:50:18.865076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3777 14:50:18.865812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3779 14:50:18.908921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3780 14:50:18.909659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3782 14:50:18.958936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3783 14:50:18.959668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3785 14:50:19.013017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3786 14:50:19.013749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3788 14:50:19.063680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3789 14:50:19.064455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3791 14:50:19.110155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3792 14:50:19.110878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3794 14:50:19.160723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3795 14:50:19.161457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3797 14:50:19.213029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3798 14:50:19.213752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3800 14:50:19.258289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3801 14:50:19.259017 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3803 14:50:19.312009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3804 14:50:19.312734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3806 14:50:19.359083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3807 14:50:19.359818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3809 14:50:19.412987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3810 14:50:19.413727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3812 14:50:19.464950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3813 14:50:19.465673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3815 14:50:19.513634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3816 14:50:19.514393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3818 14:50:19.563453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3819 14:50:19.564221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3821 14:50:19.617766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3822 14:50:19.618514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3824 14:50:19.669292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3825 14:50:19.670029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3827 14:50:19.713831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3828 14:50:19.714575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3830 14:50:19.761775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3831 14:50:19.762540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3833 14:50:19.813444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3834 14:50:19.814231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3836 14:50:19.870575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3837 14:50:19.871354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3839 14:50:19.917256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3840 14:50:19.918019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3842 14:50:19.973393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3843 14:50:19.974146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3845 14:50:20.033031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3846 14:50:20.033769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3848 14:50:20.084809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3849 14:50:20.085583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3851 14:50:20.138842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3852 14:50:20.139622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3854 14:50:20.191718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3855 14:50:20.192560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3857 14:50:20.238495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3858 14:50:20.239271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3860 14:50:20.288503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3861 14:50:20.289263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3863 14:50:20.337434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3864 14:50:20.338214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3866 14:50:20.392984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3867 14:50:20.393720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3869 14:50:20.446864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3870 14:50:20.447613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3872 14:50:20.507123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3873 14:50:20.507876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3875 14:50:20.555401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3876 14:50:20.556141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3878 14:50:20.607675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3879 14:50:20.608586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3881 14:50:20.660548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3882 14:50:20.661294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3884 14:50:20.714594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3885 14:50:20.715349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3887 14:50:20.768518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3888 14:50:20.769272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3890 14:50:20.824053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3891 14:50:20.824784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3893 14:50:20.872854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3894 14:50:20.873584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3896 14:50:20.931933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3897 14:50:20.932812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3899 14:50:20.986627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3900 14:50:20.987622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3902 14:50:21.038679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3903 14:50:21.039449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3905 14:50:21.088567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3906 14:50:21.089306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3908 14:50:21.136335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3909 14:50:21.137057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3911 14:50:21.181499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3912 14:50:21.182214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3914 14:50:21.233473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3915 14:50:21.234192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3917 14:50:21.287574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3918 14:50:21.288327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3920 14:50:21.337992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3921 14:50:21.338711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3923 14:50:21.389721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3924 14:50:21.390435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3926 14:50:21.436450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3927 14:50:21.437170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3929 14:50:21.498027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3930 14:50:21.498763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3932 14:50:21.547337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3933 14:50:21.548079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3935 14:50:21.597856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3936 14:50:21.598569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3938 14:50:21.649363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3939 14:50:21.650086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3941 14:50:21.699050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3942 14:50:21.699762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3944 14:50:21.759878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3945 14:50:21.760643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3947 14:50:21.812938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3948 14:50:21.813666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3950 14:50:21.864075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3951 14:50:21.864800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3953 14:50:21.916451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3954 14:50:21.917158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3956 14:50:21.969836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3957 14:50:21.970549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3959 14:50:22.021390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3960 14:50:22.022099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3962 14:50:22.079287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3963 14:50:22.080034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3965 14:50:22.133105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3966 14:50:22.133820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3968 14:50:22.184073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3969 14:50:22.184785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3971 14:50:22.238141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3972 14:50:22.238860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3974 14:50:22.290513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3975 14:50:22.291231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3977 14:50:22.347460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3978 14:50:22.348169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3980 14:50:22.392279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3981 14:50:22.393010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3983 14:50:22.443286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3984 14:50:22.444033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3986 14:50:22.491079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3987 14:50:22.491790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3989 14:50:22.535940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3990 14:50:22.536692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3992 14:50:22.592209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3993 14:50:22.592937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3995 14:50:22.637185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3996 14:50:22.637929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3998 14:50:22.696488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3999 14:50:22.697208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
4001 14:50:22.746792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
4002 14:50:22.747520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
4004 14:50:22.811172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
4005 14:50:22.811905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
4007 14:50:22.863677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
4008 14:50:22.864435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
4010 14:50:22.914068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
4011 14:50:22.914779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
4013 14:50:22.971784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
4014 14:50:22.972528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
4016 14:50:23.018413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
4017 14:50:23.019129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
4019 14:50:23.072234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
4020 14:50:23.072979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
4022 14:50:23.117138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
4023 14:50:23.117836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
4025 14:50:23.164718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
4026 14:50:23.165423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
4028 14:50:23.212687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
4029 14:50:23.213388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
4031 14:50:23.262465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
4032 14:50:23.263168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
4034 14:50:23.312854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
4035 14:50:23.313591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
4037 14:50:23.362593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
4038 14:50:23.363307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
4040 14:50:23.413933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
4041 14:50:23.414671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
4043 14:50:23.465875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
4044 14:50:23.466604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
4046 14:50:23.521924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
4047 14:50:23.522638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
4049 14:50:23.573778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
4050 14:50:23.574496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
4052 14:50:23.621714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
4053 14:50:23.622426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
4055 14:50:23.671136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
4056 14:50:23.671860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
4058 14:50:23.719076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
4059 14:50:23.719793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
4061 14:50:23.765519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
4062 14:50:23.766237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
4064 14:50:23.812019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
4065 14:50:23.812738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
4067 14:50:23.864510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
4068 14:50:23.865219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
4070 14:50:23.914553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
4071 14:50:23.915268 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
4073 14:50:23.966766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
4074 14:50:23.967479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
4076 14:50:24.024586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
4077 14:50:24.025297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
4079 14:50:24.088753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
4080 14:50:24.089466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
4082 14:50:24.141596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
4083 14:50:24.142300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
4085 14:50:24.192449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
4086 14:50:24.193176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
4088 14:50:24.251543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
4089 14:50:24.252307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
4091 14:50:24.309451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
4092 14:50:24.310174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
4094 14:50:24.361733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
4095 14:50:24.362443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
4097 14:50:24.415644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
4098 14:50:24.416398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
4100 14:50:24.466552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
4101 14:50:24.467257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
4103 14:50:24.514155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
4104 14:50:24.514872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
4106 14:50:24.568251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
4107 14:50:24.568984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
4109 14:50:24.623364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
4110 14:50:24.624088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
4112 14:50:24.674976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
4113 14:50:24.675709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
4115 14:50:24.734995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
4116 14:50:24.735730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
4118 14:50:24.794691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
4119 14:50:24.795411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
4121 14:50:24.845830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
4122 14:50:24.846868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
4124 14:50:24.915639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
4125 14:50:24.916383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
4127 14:50:24.974343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
4128 14:50:24.975220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
4130 14:50:25.029969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
4131 14:50:25.030707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
4133 14:50:25.080811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
4134 14:50:25.081541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
4136 14:50:25.137859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
4137 14:50:25.138590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
4139 14:50:25.193508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
4140 14:50:25.194236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
4142 14:50:25.248762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
4143 14:50:25.249486 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
4145 14:50:25.306031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
4146 14:50:25.306754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
4148 14:50:25.357121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
4149 14:50:25.357837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
4151 14:50:25.401034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
4152 14:50:25.401748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
4154 14:50:25.448031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
4155 14:50:25.448739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4157 14:50:25.494556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4158 14:50:25.495275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4160 14:50:25.551936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4161 14:50:25.552701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4163 14:50:25.601309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4164 14:50:25.602046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4166 14:50:25.649057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4167 14:50:25.649775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4169 14:50:25.697787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4170 14:50:25.698502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4172 14:50:25.750826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4173 14:50:25.751557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4175 14:50:25.800554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4176 14:50:25.801283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4178 14:50:25.857097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4179 14:50:25.857825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4181 14:50:25.909237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4182 14:50:25.909957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4184 14:50:25.962810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4185 14:50:25.963523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4187 14:50:26.015272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4188 14:50:26.016006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4190 14:50:26.061591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4191 14:50:26.062308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4193 14:50:26.112311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4194 14:50:26.113029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4196 14:50:26.167521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4197 14:50:26.168277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4199 14:50:26.219717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4200 14:50:26.220471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4202 14:50:26.268552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4203 14:50:26.269287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4205 14:50:26.313069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4206 14:50:26.313792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4208 14:50:26.366052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4209 14:50:26.366772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4211 14:50:26.408918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4212 14:50:26.409638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4214 14:50:26.455116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4215 14:50:26.455844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4217 14:50:26.499439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4218 14:50:26.500157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4220 14:50:26.558405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4221 14:50:26.559132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4223 14:50:26.603389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4224 14:50:26.604120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4226 14:50:26.649961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4227 14:50:26.650684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4229 14:50:26.695163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4230 14:50:26.695874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4232 14:50:26.745922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4233 14:50:26.746645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4235 14:50:26.799312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4236 14:50:26.800057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4238 14:50:26.853707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4239 14:50:26.854428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4241 14:50:26.903850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4242 14:50:26.904611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4244 14:50:26.953152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4245 14:50:26.953867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4247 14:50:27.004969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4248 14:50:27.005687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4250 14:50:27.056239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4251 14:50:27.056948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4253 14:50:27.106810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4254 14:50:27.107528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4256 14:50:27.159265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4257 14:50:27.159976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4259 14:50:27.204041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4260 14:50:27.204751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4262 14:50:27.257227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4263 14:50:27.257957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4265 14:50:27.301062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4266 14:50:27.301786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4268 14:50:27.350378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4269 14:50:27.351088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4271 14:50:27.393541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4272 14:50:27.394338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4274 14:50:27.443795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4275 14:50:27.444602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4277 14:50:27.496108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4278 14:50:27.496863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4280 14:50:27.547674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4281 14:50:27.548467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4283 14:50:27.591265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4284 14:50:27.592079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4286 14:50:27.643514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4287 14:50:27.644275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4289 14:50:27.697422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4290 14:50:27.698151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4292 14:50:27.744236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4293 14:50:27.744954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4295 14:50:27.803043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4296 14:50:27.803763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4298 14:50:27.860559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4299 14:50:27.861284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4301 14:50:27.916324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4302 14:50:27.917039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4304 14:50:27.968639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4305 14:50:27.969363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4307 14:50:28.013964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4308 14:50:28.014690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4310 14:50:28.058560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4311 14:50:28.059286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4313 14:50:28.110377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4314 14:50:28.111123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4316 14:50:28.160614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4317 14:50:28.161313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4319 14:50:28.217725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4320 14:50:28.218434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4322 14:50:28.275294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4323 14:50:28.276032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4325 14:50:28.330353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4326 14:50:28.331062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4328 14:50:28.388453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4329 14:50:28.389172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4331 14:50:28.441310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4332 14:50:28.442025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4334 14:50:28.498906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4335 14:50:28.499630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4337 14:50:28.555277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4338 14:50:28.556032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4340 14:50:28.606224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4341 14:50:28.606959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4343 14:50:28.663446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4344 14:50:28.664175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4346 14:50:28.726226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4347 14:50:28.726940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4349 14:50:28.788766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4350 14:50:28.789496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4352 14:50:28.845524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4353 14:50:28.846241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4355 14:50:28.895444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4356 14:50:28.896163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4358 14:50:28.951460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4359 14:50:28.952180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4361 14:50:29.008073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4362 14:50:29.008813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4364 14:50:29.054227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4366 14:50:29.057216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4367 14:50:29.111442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4368 14:50:29.112161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4370 14:50:29.169539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4371 14:50:29.170253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4373 14:50:29.227512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4374 14:50:29.228266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4376 14:50:29.285796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4377 14:50:29.286510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4379 14:50:29.341171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4380 14:50:29.341892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4382 14:50:29.386537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4383 14:50:29.387260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4385 14:50:29.444786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4386 14:50:29.445502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4388 14:50:29.498590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4389 14:50:29.499313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4391 14:50:29.551721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4392 14:50:29.552469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4394 14:50:29.605695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4395 14:50:29.606423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4397 14:50:29.664487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4398 14:50:29.665220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4400 14:50:29.710074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4401 14:50:29.710798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4403 14:50:29.763479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4404 14:50:29.764202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4406 14:50:29.818042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4407 14:50:29.818763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4409 14:50:29.873771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4410 14:50:29.874492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4412 14:50:29.919180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4413 14:50:29.919922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4415 14:50:29.977201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4416 14:50:29.977923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4418 14:50:30.027966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4419 14:50:30.028716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4421 14:50:30.083030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4422 14:50:30.083760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4424 14:50:30.134417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4425 14:50:30.135134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4427 14:50:30.182071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4428 14:50:30.182784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4430 14:50:30.236319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4431 14:50:30.237154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4433 14:50:30.295306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4434 14:50:30.296144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4436 14:50:30.360238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4437 14:50:30.361113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4439 14:50:30.414458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4440 14:50:30.415204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4442 14:50:30.463331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4443 14:50:30.464072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4445 14:50:30.507070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4446 14:50:30.507796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4448 14:50:30.560945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4449 14:50:30.561680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4451 14:50:30.618559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4452 14:50:30.619290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4454 14:50:30.668780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4455 14:50:30.669511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4457 14:50:30.714806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4458 14:50:30.715531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4460 14:50:30.764692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4461 14:50:30.765421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4463 14:50:30.813370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4464 14:50:30.814102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4466 14:50:30.858609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4467 14:50:30.859399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4469 14:50:30.909379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4470 14:50:30.910193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4472 14:50:30.960762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4473 14:50:30.961501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4475 14:50:31.011546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4476 14:50:31.012320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4478 14:50:31.068952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4479 14:50:31.069688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4481 14:50:31.120486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4482 14:50:31.121216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4484 14:50:31.165156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4485 14:50:31.165899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4487 14:50:31.214561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4488 14:50:31.215305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4490 14:50:31.266770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4491 14:50:31.267512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4493 14:50:31.308790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4494 14:50:31.309530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4496 14:50:31.362705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4497 14:50:31.363437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4499 14:50:31.408781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4500 14:50:31.409519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4502 14:50:31.456647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4503 14:50:31.457391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4505 14:50:31.512814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4506 14:50:31.513553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4508 14:50:31.566917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4509 14:50:31.567657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4511 14:50:31.619501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4512 14:50:31.620260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4514 14:50:31.677234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4515 14:50:31.677965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4517 14:50:31.724158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4518 14:50:31.724899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4520 14:50:31.774196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4522 14:50:31.779248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4523 14:50:31.779720 + set +x
4524 14:50:31.785194 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 940325_1.6.2.4.5>
4525 14:50:31.785658 <LAVA_TEST_RUNNER EXIT>
4526 14:50:31.786312 Received signal: <ENDRUN> 1_kselftest-alsa 940325_1.6.2.4.5
4527 14:50:31.786762 Ending use of test pattern.
4528 14:50:31.787169 Ending test lava.1_kselftest-alsa (940325_1.6.2.4.5), duration 40.06
4530 14:50:31.788707 ok: lava_test_shell seems to have completed
4531 14:50:31.811231 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4532 14:50:31.812965 end: 3.1 lava-test-shell (duration 00:00:41) [common]
4533 14:50:31.813538 end: 3 lava-test-retry (duration 00:00:41) [common]
4534 14:50:31.814109 start: 4 finalize (timeout 00:06:05) [common]
4535 14:50:31.814671 start: 4.1 power-off (timeout 00:00:30) [common]
4536 14:50:31.815602 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4537 14:50:31.850735 >> OK - accepted request
4538 14:50:31.852730 Returned 0 in 0 seconds
4539 14:50:31.953851 end: 4.1 power-off (duration 00:00:00) [common]
4541 14:50:31.955485 start: 4.2 read-feedback (timeout 00:06:05) [common]
4542 14:50:31.956636 Listened to connection for namespace 'common' for up to 1s
4543 14:50:32.957369 Finalising connection for namespace 'common'
4544 14:50:32.958038 Disconnecting from shell: Finalise
4545 14:50:32.958557 / #
4546 14:50:33.059522 end: 4.2 read-feedback (duration 00:00:01) [common]
4547 14:50:33.060287 end: 4 finalize (duration 00:00:01) [common]
4548 14:50:33.060987 Cleaning after the job
4549 14:50:33.061672 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/ramdisk
4550 14:50:33.075469 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/kernel
4551 14:50:33.102207 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/dtb
4552 14:50:33.103500 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/nfsrootfs
4553 14:50:33.134548 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/940325/tftp-deploy-mkzwf0bj/modules
4554 14:50:33.140773 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/940325
4555 14:50:36.137396 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/940325
4556 14:50:36.137977 Job finished correctly