Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 14:39:16.755928 lava-dispatcher, installed at version: 2024.01
2 14:39:16.756721 start: 0 validate
3 14:39:16.757194 Start time: 2024-11-05 14:39:16.757164+00:00 (UTC)
4 14:39:16.757720 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 14:39:16.758261 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 14:39:16.798504 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 14:39:16.799061 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-60-ge38568da5f05b%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 14:39:16.830429 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 14:39:16.831125 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-60-ge38568da5f05b%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 14:39:16.862223 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 14:39:16.862714 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 14:39:16.891330 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 14:39:16.891807 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-60-ge38568da5f05b%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 14:39:16.930042 validate duration: 0.17
16 14:39:16.930879 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 14:39:16.931209 start: 1.1 download-retry (timeout 00:10:00) [common]
18 14:39:16.931527 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 14:39:16.932132 Not decompressing ramdisk as can be used compressed.
20 14:39:16.932620 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 14:39:16.932918 saving as /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/ramdisk/initrd.cpio.gz
22 14:39:16.933190 total size: 5628169 (5 MB)
23 14:39:16.968784 progress 0 % (0 MB)
24 14:39:16.976171 progress 5 % (0 MB)
25 14:39:16.983830 progress 10 % (0 MB)
26 14:39:16.990651 progress 15 % (0 MB)
27 14:39:16.997190 progress 20 % (1 MB)
28 14:39:17.000818 progress 25 % (1 MB)
29 14:39:17.004782 progress 30 % (1 MB)
30 14:39:17.008706 progress 35 % (1 MB)
31 14:39:17.012235 progress 40 % (2 MB)
32 14:39:17.016135 progress 45 % (2 MB)
33 14:39:17.019592 progress 50 % (2 MB)
34 14:39:17.023536 progress 55 % (2 MB)
35 14:39:17.027426 progress 60 % (3 MB)
36 14:39:17.030911 progress 65 % (3 MB)
37 14:39:17.034761 progress 70 % (3 MB)
38 14:39:17.038333 progress 75 % (4 MB)
39 14:39:17.042244 progress 80 % (4 MB)
40 14:39:17.045725 progress 85 % (4 MB)
41 14:39:17.049679 progress 90 % (4 MB)
42 14:39:17.053484 progress 95 % (5 MB)
43 14:39:17.056722 progress 100 % (5 MB)
44 14:39:17.057369 5 MB downloaded in 0.12 s (43.23 MB/s)
45 14:39:17.057915 end: 1.1.1 http-download (duration 00:00:00) [common]
47 14:39:17.058829 end: 1.1 download-retry (duration 00:00:00) [common]
48 14:39:17.059140 start: 1.2 download-retry (timeout 00:10:00) [common]
49 14:39:17.059427 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 14:39:17.059907 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-60-ge38568da5f05b/arm64/defconfig/gcc-12/kernel/Image
51 14:39:17.060185 saving as /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/kernel/Image
52 14:39:17.060405 total size: 45713920 (43 MB)
53 14:39:17.060622 No compression specified
54 14:39:17.097859 progress 0 % (0 MB)
55 14:39:17.125304 progress 5 % (2 MB)
56 14:39:17.153334 progress 10 % (4 MB)
57 14:39:17.180722 progress 15 % (6 MB)
58 14:39:17.208342 progress 20 % (8 MB)
59 14:39:17.235519 progress 25 % (10 MB)
60 14:39:17.263001 progress 30 % (13 MB)
61 14:39:17.291093 progress 35 % (15 MB)
62 14:39:17.318944 progress 40 % (17 MB)
63 14:39:17.346586 progress 45 % (19 MB)
64 14:39:17.374562 progress 50 % (21 MB)
65 14:39:17.402318 progress 55 % (24 MB)
66 14:39:17.430431 progress 60 % (26 MB)
67 14:39:17.457812 progress 65 % (28 MB)
68 14:39:17.485686 progress 70 % (30 MB)
69 14:39:17.513516 progress 75 % (32 MB)
70 14:39:17.541413 progress 80 % (34 MB)
71 14:39:17.569003 progress 85 % (37 MB)
72 14:39:17.596657 progress 90 % (39 MB)
73 14:39:17.624391 progress 95 % (41 MB)
74 14:39:17.651378 progress 100 % (43 MB)
75 14:39:17.651920 43 MB downloaded in 0.59 s (73.70 MB/s)
76 14:39:17.652446 end: 1.2.1 http-download (duration 00:00:01) [common]
78 14:39:17.653305 end: 1.2 download-retry (duration 00:00:01) [common]
79 14:39:17.653603 start: 1.3 download-retry (timeout 00:09:59) [common]
80 14:39:17.653888 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 14:39:17.654363 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-60-ge38568da5f05b/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 14:39:17.654644 saving as /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/dtb/meson-g12b-a311d-libretech-cc.dtb
83 14:39:17.654864 total size: 54703 (0 MB)
84 14:39:17.655082 No compression specified
85 14:39:17.696054 progress 59 % (0 MB)
86 14:39:17.696895 progress 100 % (0 MB)
87 14:39:17.697463 0 MB downloaded in 0.04 s (1.23 MB/s)
88 14:39:17.697935 end: 1.3.1 http-download (duration 00:00:00) [common]
90 14:39:17.698766 end: 1.3 download-retry (duration 00:00:00) [common]
91 14:39:17.699039 start: 1.4 download-retry (timeout 00:09:59) [common]
92 14:39:17.699312 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 14:39:17.699763 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 14:39:17.700041 saving as /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/nfsrootfs/full.rootfs.tar
95 14:39:17.700260 total size: 120894716 (115 MB)
96 14:39:17.700478 Using unxz to decompress xz
97 14:39:17.732825 progress 0 % (0 MB)
98 14:39:18.526397 progress 5 % (5 MB)
99 14:39:19.360978 progress 10 % (11 MB)
100 14:39:20.158650 progress 15 % (17 MB)
101 14:39:20.902108 progress 20 % (23 MB)
102 14:39:21.503057 progress 25 % (28 MB)
103 14:39:22.347289 progress 30 % (34 MB)
104 14:39:23.149188 progress 35 % (40 MB)
105 14:39:23.512070 progress 40 % (46 MB)
106 14:39:23.895878 progress 45 % (51 MB)
107 14:39:24.609487 progress 50 % (57 MB)
108 14:39:25.485431 progress 55 % (63 MB)
109 14:39:26.267316 progress 60 % (69 MB)
110 14:39:27.022533 progress 65 % (74 MB)
111 14:39:27.808149 progress 70 % (80 MB)
112 14:39:28.629331 progress 75 % (86 MB)
113 14:39:29.415008 progress 80 % (92 MB)
114 14:39:30.172843 progress 85 % (98 MB)
115 14:39:31.023101 progress 90 % (103 MB)
116 14:39:31.797035 progress 95 % (109 MB)
117 14:39:32.626796 progress 100 % (115 MB)
118 14:39:32.640210 115 MB downloaded in 14.94 s (7.72 MB/s)
119 14:39:32.640905 end: 1.4.1 http-download (duration 00:00:15) [common]
121 14:39:32.641896 end: 1.4 download-retry (duration 00:00:15) [common]
122 14:39:32.642215 start: 1.5 download-retry (timeout 00:09:44) [common]
123 14:39:32.642534 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 14:39:32.643170 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-60-ge38568da5f05b/arm64/defconfig/gcc-12/modules.tar.xz
125 14:39:32.643479 saving as /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/modules/modules.tar
126 14:39:32.643729 total size: 11603148 (11 MB)
127 14:39:32.644069 Using unxz to decompress xz
128 14:39:32.685436 progress 0 % (0 MB)
129 14:39:32.752442 progress 5 % (0 MB)
130 14:39:32.827034 progress 10 % (1 MB)
131 14:39:32.924288 progress 15 % (1 MB)
132 14:39:33.019198 progress 20 % (2 MB)
133 14:39:33.100507 progress 25 % (2 MB)
134 14:39:33.175094 progress 30 % (3 MB)
135 14:39:33.247924 progress 35 % (3 MB)
136 14:39:33.323696 progress 40 % (4 MB)
137 14:39:33.400078 progress 45 % (5 MB)
138 14:39:33.486554 progress 50 % (5 MB)
139 14:39:33.564956 progress 55 % (6 MB)
140 14:39:33.649493 progress 60 % (6 MB)
141 14:39:33.729588 progress 65 % (7 MB)
142 14:39:33.806997 progress 70 % (7 MB)
143 14:39:33.888826 progress 75 % (8 MB)
144 14:39:33.972650 progress 80 % (8 MB)
145 14:39:34.051890 progress 85 % (9 MB)
146 14:39:34.134716 progress 90 % (9 MB)
147 14:39:34.213000 progress 95 % (10 MB)
148 14:39:34.291566 progress 100 % (11 MB)
149 14:39:34.301917 11 MB downloaded in 1.66 s (6.67 MB/s)
150 14:39:34.302524 end: 1.5.1 http-download (duration 00:00:02) [common]
152 14:39:34.303355 end: 1.5 download-retry (duration 00:00:02) [common]
153 14:39:34.303627 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 14:39:34.303894 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 14:39:50.703187 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/940302/extract-nfsrootfs-279fzkhd
156 14:39:50.703797 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 14:39:50.704144 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 14:39:50.704941 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea
159 14:39:50.705442 makedir: /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin
160 14:39:50.705853 makedir: /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/tests
161 14:39:50.706238 makedir: /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/results
162 14:39:50.706637 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-add-keys
163 14:39:50.707219 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-add-sources
164 14:39:50.707743 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-background-process-start
165 14:39:50.708328 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-background-process-stop
166 14:39:50.708854 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-common-functions
167 14:39:50.709359 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-echo-ipv4
168 14:39:50.709833 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-install-packages
169 14:39:50.710291 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-installed-packages
170 14:39:50.710743 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-os-build
171 14:39:50.711206 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-probe-channel
172 14:39:50.711660 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-probe-ip
173 14:39:50.712147 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-target-ip
174 14:39:50.712618 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-target-mac
175 14:39:50.713082 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-target-storage
176 14:39:50.713550 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-test-case
177 14:39:50.714011 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-test-event
178 14:39:50.714468 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-test-feedback
179 14:39:50.714923 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-test-raise
180 14:39:50.715409 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-test-reference
181 14:39:50.715904 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-test-runner
182 14:39:50.716410 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-test-set
183 14:39:50.716877 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-test-shell
184 14:39:50.717349 Updating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-add-keys (debian)
185 14:39:50.717861 Updating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-add-sources (debian)
186 14:39:50.718346 Updating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-install-packages (debian)
187 14:39:50.718826 Updating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-installed-packages (debian)
188 14:39:50.719301 Updating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/bin/lava-os-build (debian)
189 14:39:50.719766 Creating /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/environment
190 14:39:50.720156 LAVA metadata
191 14:39:50.720411 - LAVA_JOB_ID=940302
192 14:39:50.720624 - LAVA_DISPATCHER_IP=192.168.6.2
193 14:39:50.720973 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 14:39:50.721888 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 14:39:50.722187 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 14:39:50.722391 skipped lava-vland-overlay
197 14:39:50.722628 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 14:39:50.722880 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 14:39:50.723093 skipped lava-multinode-overlay
200 14:39:50.723332 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 14:39:50.723578 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 14:39:50.723817 Loading test definitions
203 14:39:50.724112 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 14:39:50.724331 Using /lava-940302 at stage 0
205 14:39:50.725380 uuid=940302_1.6.2.4.1 testdef=None
206 14:39:50.725676 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 14:39:50.725935 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 14:39:50.727426 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 14:39:50.728259 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 14:39:50.730122 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 14:39:50.730919 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 14:39:50.732716 runner path: /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/0/tests/0_timesync-off test_uuid 940302_1.6.2.4.1
215 14:39:50.733240 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 14:39:50.734037 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 14:39:50.734256 Using /lava-940302 at stage 0
219 14:39:50.734598 Fetching tests from https://github.com/kernelci/test-definitions.git
220 14:39:50.734882 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/0/tests/1_kselftest-dt'
221 14:39:54.317101 Running '/usr/bin/git checkout kernelci.org
222 14:39:54.603602 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 14:39:54.605044 uuid=940302_1.6.2.4.5 testdef=None
224 14:39:54.605389 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 14:39:54.606133 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 14:39:54.608944 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 14:39:54.609751 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 14:39:54.613388 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 14:39:54.614226 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 14:39:54.617748 runner path: /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/0/tests/1_kselftest-dt test_uuid 940302_1.6.2.4.5
234 14:39:54.618024 BOARD='meson-g12b-a311d-libretech-cc'
235 14:39:54.618228 BRANCH='broonie-spi'
236 14:39:54.618424 SKIPFILE='/dev/null'
237 14:39:54.618618 SKIP_INSTALL='True'
238 14:39:54.618812 TESTPROG_URL='http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-60-ge38568da5f05b/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 14:39:54.619034 TST_CASENAME=''
240 14:39:54.619229 TST_CMDFILES='dt'
241 14:39:54.619757 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 14:39:54.620549 Creating lava-test-runner.conf files
244 14:39:54.620753 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/940302/lava-overlay-svtjsdea/lava-940302/0 for stage 0
245 14:39:54.621104 - 0_timesync-off
246 14:39:54.621338 - 1_kselftest-dt
247 14:39:54.621661 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 14:39:54.621936 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 14:40:17.934975 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 14:40:17.935431 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 14:40:17.935728 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 14:40:17.936068 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 14:40:17.936377 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 14:40:18.549157 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 14:40:18.549632 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 14:40:18.549885 extracting modules file /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/940302/extract-nfsrootfs-279fzkhd
257 14:40:19.998524 extracting modules file /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/940302/extract-overlay-ramdisk-fj4379sp/ramdisk
258 14:40:21.399005 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 14:40:21.399486 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
260 14:40:21.399764 [common] Applying overlay to NFS
261 14:40:21.400002 [common] Applying overlay /var/lib/lava/dispatcher/tmp/940302/compress-overlay-waa36a17/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/940302/extract-nfsrootfs-279fzkhd
262 14:40:24.123062 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 14:40:24.123532 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 14:40:24.123804 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 14:40:24.124059 Converting downloaded kernel to a uImage
266 14:40:24.124373 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/kernel/Image /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/kernel/uImage
267 14:40:24.631561 output: Image Name:
268 14:40:24.632015 output: Created: Tue Nov 5 14:40:24 2024
269 14:40:24.632249 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 14:40:24.632470 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 14:40:24.632687 output: Load Address: 01080000
272 14:40:24.632903 output: Entry Point: 01080000
273 14:40:24.633110 output:
274 14:40:24.633466 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 14:40:24.633950 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 14:40:24.634376 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 14:40:24.634692 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 14:40:24.634991 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 14:40:24.635284 Building ramdisk /var/lib/lava/dispatcher/tmp/940302/extract-overlay-ramdisk-fj4379sp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/940302/extract-overlay-ramdisk-fj4379sp/ramdisk
280 14:40:26.790299 >> 166774 blocks
281 14:40:34.488366 Adding RAMdisk u-boot header.
282 14:40:34.488817 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/940302/extract-overlay-ramdisk-fj4379sp/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/940302/extract-overlay-ramdisk-fj4379sp/ramdisk.cpio.gz.uboot
283 14:40:34.735742 output: Image Name:
284 14:40:34.736340 output: Created: Tue Nov 5 14:40:34 2024
285 14:40:34.736802 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 14:40:34.737273 output: Data Size: 23426875 Bytes = 22877.81 KiB = 22.34 MiB
287 14:40:34.737715 output: Load Address: 00000000
288 14:40:34.738155 output: Entry Point: 00000000
289 14:40:34.738593 output:
290 14:40:34.739668 rename /var/lib/lava/dispatcher/tmp/940302/extract-overlay-ramdisk-fj4379sp/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/ramdisk/ramdisk.cpio.gz.uboot
291 14:40:34.740478 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 14:40:34.741075 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 14:40:34.741651 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 14:40:34.742145 No LXC device requested
295 14:40:34.742687 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 14:40:34.743244 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 14:40:34.743785 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 14:40:34.744268 Checking files for TFTP limit of 4294967296 bytes.
299 14:40:34.747170 end: 1 tftp-deploy (duration 00:01:18) [common]
300 14:40:34.747792 start: 2 uboot-action (timeout 00:05:00) [common]
301 14:40:34.748403 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 14:40:34.748951 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 14:40:34.749502 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 14:40:34.750077 Using kernel file from prepare-kernel: 940302/tftp-deploy-uylh40cu/kernel/uImage
305 14:40:34.750770 substitutions:
306 14:40:34.751219 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 14:40:34.751662 - {DTB_ADDR}: 0x01070000
308 14:40:34.752138 - {DTB}: 940302/tftp-deploy-uylh40cu/dtb/meson-g12b-a311d-libretech-cc.dtb
309 14:40:34.752587 - {INITRD}: 940302/tftp-deploy-uylh40cu/ramdisk/ramdisk.cpio.gz.uboot
310 14:40:34.753026 - {KERNEL_ADDR}: 0x01080000
311 14:40:34.753460 - {KERNEL}: 940302/tftp-deploy-uylh40cu/kernel/uImage
312 14:40:34.753893 - {LAVA_MAC}: None
313 14:40:34.754370 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/940302/extract-nfsrootfs-279fzkhd
314 14:40:34.754809 - {NFS_SERVER_IP}: 192.168.6.2
315 14:40:34.755236 - {PRESEED_CONFIG}: None
316 14:40:34.755664 - {PRESEED_LOCAL}: None
317 14:40:34.756121 - {RAMDISK_ADDR}: 0x08000000
318 14:40:34.756551 - {RAMDISK}: 940302/tftp-deploy-uylh40cu/ramdisk/ramdisk.cpio.gz.uboot
319 14:40:34.756982 - {ROOT_PART}: None
320 14:40:34.757405 - {ROOT}: None
321 14:40:34.757830 - {SERVER_IP}: 192.168.6.2
322 14:40:34.758253 - {TEE_ADDR}: 0x83000000
323 14:40:34.758676 - {TEE}: None
324 14:40:34.759098 Parsed boot commands:
325 14:40:34.759510 - setenv autoload no
326 14:40:34.759933 - setenv initrd_high 0xffffffff
327 14:40:34.760418 - setenv fdt_high 0xffffffff
328 14:40:34.760844 - dhcp
329 14:40:34.761266 - setenv serverip 192.168.6.2
330 14:40:34.761692 - tftpboot 0x01080000 940302/tftp-deploy-uylh40cu/kernel/uImage
331 14:40:34.762122 - tftpboot 0x08000000 940302/tftp-deploy-uylh40cu/ramdisk/ramdisk.cpio.gz.uboot
332 14:40:34.762554 - tftpboot 0x01070000 940302/tftp-deploy-uylh40cu/dtb/meson-g12b-a311d-libretech-cc.dtb
333 14:40:34.762980 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/940302/extract-nfsrootfs-279fzkhd,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 14:40:34.763419 - bootm 0x01080000 0x08000000 0x01070000
335 14:40:34.763972 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 14:40:34.765636 start: 2.3 connect-device (timeout 00:05:00) [common]
338 14:40:34.766095 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 14:40:34.781672 Setting prompt string to ['lava-test: # ']
340 14:40:34.783312 end: 2.3 connect-device (duration 00:00:00) [common]
341 14:40:34.784023 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 14:40:34.784661 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 14:40:34.785247 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 14:40:34.786498 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 14:40:34.824093 >> OK - accepted request
346 14:40:34.826123 Returned 0 in 0 seconds
347 14:40:34.927273 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 14:40:34.929048 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 14:40:34.929653 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 14:40:34.930205 Setting prompt string to ['Hit any key to stop autoboot']
352 14:40:34.930873 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 14:40:34.932629 Trying 192.168.56.21...
354 14:40:34.933151 Connected to conserv1.
355 14:40:34.933608 Escape character is '^]'.
356 14:40:34.934049
357 14:40:34.934509 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 14:40:34.934961
359 14:40:46.576322 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 14:40:46.576983 bl2_stage_init 0x01
361 14:40:46.577435 bl2_stage_init 0x81
362 14:40:46.582007 hw id: 0x0000 - pwm id 0x01
363 14:40:46.582549 bl2_stage_init 0xc1
364 14:40:46.583001 bl2_stage_init 0x02
365 14:40:46.583450
366 14:40:46.587462 L0:00000000
367 14:40:46.587959 L1:20000703
368 14:40:46.588469 L2:00008067
369 14:40:46.588914 L3:14000000
370 14:40:46.590593 B2:00402000
371 14:40:46.591075 B1:e0f83180
372 14:40:46.591521
373 14:40:46.591954 TE: 58159
374 14:40:46.592423
375 14:40:46.601793 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 14:40:46.602262
377 14:40:46.602693 Board ID = 1
378 14:40:46.603115 Set A53 clk to 24M
379 14:40:46.603536 Set A73 clk to 24M
380 14:40:46.607301 Set clk81 to 24M
381 14:40:46.607763 A53 clk: 1200 MHz
382 14:40:46.608231 A73 clk: 1200 MHz
383 14:40:46.612867 CLK81: 166.6M
384 14:40:46.613322 smccc: 00012ab5
385 14:40:46.618496 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 14:40:46.618953 board id: 1
387 14:40:46.627029 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 14:40:46.637641 fw parse done
389 14:40:46.643652 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 14:40:46.686072 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 14:40:46.696955 PIEI prepare done
392 14:40:46.697408 fastboot data load
393 14:40:46.697838 fastboot data verify
394 14:40:46.702665 verify result: 266
395 14:40:46.708250 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 14:40:46.708710 LPDDR4 probe
397 14:40:46.709141 ddr clk to 1584MHz
398 14:40:46.716233 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 14:40:46.753465
400 14:40:46.753972 dmc_version 0001
401 14:40:46.760159 Check phy result
402 14:40:46.766008 INFO : End of CA training
403 14:40:46.766465 INFO : End of initialization
404 14:40:46.771612 INFO : Training has run successfully!
405 14:40:46.772113 Check phy result
406 14:40:46.777212 INFO : End of initialization
407 14:40:46.777670 INFO : End of read enable training
408 14:40:46.782810 INFO : End of fine write leveling
409 14:40:46.788411 INFO : End of Write leveling coarse delay
410 14:40:46.788868 INFO : Training has run successfully!
411 14:40:46.789299 Check phy result
412 14:40:46.794020 INFO : End of initialization
413 14:40:46.794479 INFO : End of read dq deskew training
414 14:40:46.799598 INFO : End of MPR read delay center optimization
415 14:40:46.805233 INFO : End of write delay center optimization
416 14:40:46.810808 INFO : End of read delay center optimization
417 14:40:46.811263 INFO : End of max read latency training
418 14:40:46.816425 INFO : Training has run successfully!
419 14:40:46.816900 1D training succeed
420 14:40:46.825617 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 14:40:46.873179 Check phy result
422 14:40:46.873681 INFO : End of initialization
423 14:40:46.894782 INFO : End of 2D read delay Voltage center optimization
424 14:40:46.914902 INFO : End of 2D read delay Voltage center optimization
425 14:40:46.966798 INFO : End of 2D write delay Voltage center optimization
426 14:40:47.016050 INFO : End of 2D write delay Voltage center optimization
427 14:40:47.021612 INFO : Training has run successfully!
428 14:40:47.022073
429 14:40:47.022508 channel==0
430 14:40:47.027210 RxClkDly_Margin_A0==88 ps 9
431 14:40:47.027666 TxDqDly_Margin_A0==98 ps 10
432 14:40:47.032857 RxClkDly_Margin_A1==88 ps 9
433 14:40:47.033354 TxDqDly_Margin_A1==98 ps 10
434 14:40:47.033787 TrainedVREFDQ_A0==74
435 14:40:47.038385 TrainedVREFDQ_A1==74
436 14:40:47.038850 VrefDac_Margin_A0==25
437 14:40:47.039282 DeviceVref_Margin_A0==40
438 14:40:47.044009 VrefDac_Margin_A1==25
439 14:40:47.044469 DeviceVref_Margin_A1==40
440 14:40:47.044899
441 14:40:47.045327
442 14:40:47.049657 channel==1
443 14:40:47.050229 RxClkDly_Margin_A0==98 ps 10
444 14:40:47.050682 TxDqDly_Margin_A0==98 ps 10
445 14:40:47.055309 RxClkDly_Margin_A1==88 ps 9
446 14:40:47.055823 TxDqDly_Margin_A1==88 ps 9
447 14:40:47.060917 TrainedVREFDQ_A0==77
448 14:40:47.061417 TrainedVREFDQ_A1==77
449 14:40:47.061858 VrefDac_Margin_A0==22
450 14:40:47.066473 DeviceVref_Margin_A0==37
451 14:40:47.066972 VrefDac_Margin_A1==24
452 14:40:47.072096 DeviceVref_Margin_A1==37
453 14:40:47.072595
454 14:40:47.073040 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 14:40:47.073473
456 14:40:47.105639 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 14:40:47.106213 2D training succeed
458 14:40:47.111305 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 14:40:47.116928 auto size-- 65535DDR cs0 size: 2048MB
460 14:40:47.117436 DDR cs1 size: 2048MB
461 14:40:47.122476 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 14:40:47.122993 cs0 DataBus test pass
463 14:40:47.128106 cs1 DataBus test pass
464 14:40:47.128623 cs0 AddrBus test pass
465 14:40:47.129062 cs1 AddrBus test pass
466 14:40:47.129492
467 14:40:47.133700 100bdlr_step_size ps== 420
468 14:40:47.134240 result report
469 14:40:47.139321 boot times 0Enable ddr reg access
470 14:40:47.144681 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 14:40:47.158064 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 14:40:47.730060 0.0;M3 CHK:0;cm4_sp_mode 0
473 14:40:47.730680 MVN_1=0x00000000
474 14:40:47.735545 MVN_2=0x00000000
475 14:40:47.741277 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 14:40:47.741798 OPS=0x10
477 14:40:47.742262 ring efuse init
478 14:40:47.742711 chipver efuse init
479 14:40:47.746914 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 14:40:47.752469 [0.018961 Inits done]
481 14:40:47.753014 secure task start!
482 14:40:47.753479 high task start!
483 14:40:47.757059 low task start!
484 14:40:47.757576 run into bl31
485 14:40:47.763723 NOTICE: BL31: v1.3(release):4fc40b1
486 14:40:47.771506 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 14:40:47.772047 NOTICE: BL31: G12A normal boot!
488 14:40:47.796915 NOTICE: BL31: BL33 decompress pass
489 14:40:47.802560 ERROR: Error initializing runtime service opteed_fast
490 14:40:49.035445
491 14:40:49.036108
492 14:40:49.043833 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 14:40:49.044403
494 14:40:49.044869 Model: Libre Computer AML-A311D-CC Alta
495 14:40:49.252284 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 14:40:49.275645 DRAM: 2 GiB (effective 3.8 GiB)
497 14:40:49.418629 Core: 408 devices, 31 uclasses, devicetree: separate
498 14:40:49.424515 WDT: Not starting watchdog@f0d0
499 14:40:49.456759 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 14:40:49.469246 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 14:40:49.474262 ** Bad device specification mmc 0 **
502 14:40:49.484565 Card did not respond to voltage select! : -110
503 14:40:49.492246 ** Bad device specification mmc 0 **
504 14:40:49.492765 Couldn't find partition mmc 0
505 14:40:49.500552 Card did not respond to voltage select! : -110
506 14:40:49.506148 ** Bad device specification mmc 0 **
507 14:40:49.506675 Couldn't find partition mmc 0
508 14:40:49.511184 Error: could not access storage.
509 14:40:50.776828 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 14:40:50.777286 bl2_stage_init 0x01
511 14:40:50.777507 bl2_stage_init 0x81
512 14:40:50.782383 hw id: 0x0000 - pwm id 0x01
513 14:40:50.783029 bl2_stage_init 0xc1
514 14:40:50.783477 bl2_stage_init 0x02
515 14:40:50.783909
516 14:40:50.788017 L0:00000000
517 14:40:50.788577 L1:20000703
518 14:40:50.788996 L2:00008067
519 14:40:50.789401 L3:14000000
520 14:40:50.793615 B2:00402000
521 14:40:50.794180 B1:e0f83180
522 14:40:50.794602
523 14:40:50.795013 TE: 58124
524 14:40:50.795422
525 14:40:50.799220 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 14:40:50.799801
527 14:40:50.800269 Board ID = 1
528 14:40:50.804790 Set A53 clk to 24M
529 14:40:50.805355 Set A73 clk to 24M
530 14:40:50.805786 Set clk81 to 24M
531 14:40:50.810371 A53 clk: 1200 MHz
532 14:40:50.810923 A73 clk: 1200 MHz
533 14:40:50.811345 CLK81: 166.6M
534 14:40:50.811747 smccc: 00012a92
535 14:40:50.816031 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 14:40:50.821597 board id: 1
537 14:40:50.827453 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 14:40:50.838143 fw parse done
539 14:40:50.844046 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 14:40:50.886631 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 14:40:50.897567 PIEI prepare done
542 14:40:50.898111 fastboot data load
543 14:40:50.898533 fastboot data verify
544 14:40:50.903290 verify result: 266
545 14:40:50.908868 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 14:40:50.909408 LPDDR4 probe
547 14:40:50.909823 ddr clk to 1584MHz
548 14:40:50.916907 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 14:40:50.954110
550 14:40:50.954668 dmc_version 0001
551 14:40:50.960792 Check phy result
552 14:40:50.966671 INFO : End of CA training
553 14:40:50.967223 INFO : End of initialization
554 14:40:50.972326 INFO : Training has run successfully!
555 14:40:50.972870 Check phy result
556 14:40:50.977900 INFO : End of initialization
557 14:40:50.978456 INFO : End of read enable training
558 14:40:50.983631 INFO : End of fine write leveling
559 14:40:50.989120 INFO : End of Write leveling coarse delay
560 14:40:50.989692 INFO : Training has run successfully!
561 14:40:50.990136 Check phy result
562 14:40:50.994651 INFO : End of initialization
563 14:40:50.995158 INFO : End of read dq deskew training
564 14:40:51.000230 INFO : End of MPR read delay center optimization
565 14:40:51.005762 INFO : End of write delay center optimization
566 14:40:51.011378 INFO : End of read delay center optimization
567 14:40:51.011872 INFO : End of max read latency training
568 14:40:51.017024 INFO : Training has run successfully!
569 14:40:51.017526 1D training succeed
570 14:40:51.026130 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 14:40:51.073823 Check phy result
572 14:40:51.074370 INFO : End of initialization
573 14:40:51.096403 INFO : End of 2D read delay Voltage center optimization
574 14:40:51.116583 INFO : End of 2D read delay Voltage center optimization
575 14:40:51.168676 INFO : End of 2D write delay Voltage center optimization
576 14:40:51.218053 INFO : End of 2D write delay Voltage center optimization
577 14:40:51.223593 INFO : Training has run successfully!
578 14:40:51.224125
579 14:40:51.224548 channel==0
580 14:40:51.229170 RxClkDly_Margin_A0==78 ps 8
581 14:40:51.229653 TxDqDly_Margin_A0==98 ps 10
582 14:40:51.232503 RxClkDly_Margin_A1==88 ps 9
583 14:40:51.232987 TxDqDly_Margin_A1==98 ps 10
584 14:40:51.238078 TrainedVREFDQ_A0==74
585 14:40:51.238561 TrainedVREFDQ_A1==74
586 14:40:51.238976 VrefDac_Margin_A0==25
587 14:40:51.243705 DeviceVref_Margin_A0==40
588 14:40:51.244222 VrefDac_Margin_A1==24
589 14:40:51.249307 DeviceVref_Margin_A1==40
590 14:40:51.249792
591 14:40:51.250207
592 14:40:51.250609 channel==1
593 14:40:51.251002 RxClkDly_Margin_A0==98 ps 10
594 14:40:51.254879 TxDqDly_Margin_A0==98 ps 10
595 14:40:51.255365 RxClkDly_Margin_A1==98 ps 10
596 14:40:51.260514 TxDqDly_Margin_A1==88 ps 9
597 14:40:51.261011 TrainedVREFDQ_A0==77
598 14:40:51.261425 TrainedVREFDQ_A1==77
599 14:40:51.266129 VrefDac_Margin_A0==22
600 14:40:51.266624 DeviceVref_Margin_A0==37
601 14:40:51.271705 VrefDac_Margin_A1==22
602 14:40:51.272222 DeviceVref_Margin_A1==37
603 14:40:51.272632
604 14:40:51.277286 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 14:40:51.277768
606 14:40:51.305245 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 14:40:51.310945 2D training succeed
608 14:40:51.316527 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 14:40:51.317028 auto size-- 65535DDR cs0 size: 2048MB
610 14:40:51.322111 DDR cs1 size: 2048MB
611 14:40:51.322620 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 14:40:51.327704 cs0 DataBus test pass
613 14:40:51.328241 cs1 DataBus test pass
614 14:40:51.328658 cs0 AddrBus test pass
615 14:40:51.333320 cs1 AddrBus test pass
616 14:40:51.333806
617 14:40:51.334215 100bdlr_step_size ps== 420
618 14:40:51.334626 result report
619 14:40:51.338882 boot times 0Enable ddr reg access
620 14:40:51.346608 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 14:40:51.360080 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 14:40:51.933884 0.0;M3 CHK:0;cm4_sp_mode 0
623 14:40:51.934476 MVN_1=0x00000000
624 14:40:51.939371 MVN_2=0x00000000
625 14:40:51.945015 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 14:40:51.945517 OPS=0x10
627 14:40:51.945927 ring efuse init
628 14:40:51.946322 chipver efuse init
629 14:40:51.953306 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 14:40:51.953840 [0.018961 Inits done]
631 14:40:51.960882 secure task start!
632 14:40:51.961346 high task start!
633 14:40:51.961735 low task start!
634 14:40:51.962121 run into bl31
635 14:40:51.967424 NOTICE: BL31: v1.3(release):4fc40b1
636 14:40:51.975369 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 14:40:51.975835 NOTICE: BL31: G12A normal boot!
638 14:40:52.000581 NOTICE: BL31: BL33 decompress pass
639 14:40:52.006282 ERROR: Error initializing runtime service opteed_fast
640 14:40:53.239295
641 14:40:53.239915
642 14:40:53.247727 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 14:40:53.248263
644 14:40:53.248684 Model: Libre Computer AML-A311D-CC Alta
645 14:40:53.456165 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 14:40:53.479498 DRAM: 2 GiB (effective 3.8 GiB)
647 14:40:53.622398 Core: 408 devices, 31 uclasses, devicetree: separate
648 14:40:53.628364 WDT: Not starting watchdog@f0d0
649 14:40:53.660695 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 14:40:53.672904 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 14:40:53.678066 ** Bad device specification mmc 0 **
652 14:40:53.688262 Card did not respond to voltage select! : -110
653 14:40:53.696112 ** Bad device specification mmc 0 **
654 14:40:53.696592 Couldn't find partition mmc 0
655 14:40:53.704314 Card did not respond to voltage select! : -110
656 14:40:53.709841 ** Bad device specification mmc 0 **
657 14:40:53.710311 Couldn't find partition mmc 0
658 14:40:53.714877 Error: could not access storage.
659 14:40:54.057401 Net: eth0: ethernet@ff3f0000
660 14:40:54.057993 starting USB...
661 14:40:54.309234 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 14:40:54.309780 Starting the controller
663 14:40:54.316264 USB XHCI 1.10
664 14:40:56.027041 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 14:40:56.027700 bl2_stage_init 0x01
666 14:40:56.028199 bl2_stage_init 0x81
667 14:40:56.032722 hw id: 0x0000 - pwm id 0x01
668 14:40:56.033322 bl2_stage_init 0xc1
669 14:40:56.033770 bl2_stage_init 0x02
670 14:40:56.034202
671 14:40:56.038339 L0:00000000
672 14:40:56.038943 L1:20000703
673 14:40:56.039420 L2:00008067
674 14:40:56.039856 L3:14000000
675 14:40:56.044064 B2:00402000
676 14:40:56.044659 B1:e0f83180
677 14:40:56.045074
678 14:40:56.045498 TE: 58159
679 14:40:56.045911
680 14:40:56.049595 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 14:40:56.050208
682 14:40:56.050640 Board ID = 1
683 14:40:56.055107 Set A53 clk to 24M
684 14:40:56.055743 Set A73 clk to 24M
685 14:40:56.056222 Set clk81 to 24M
686 14:40:56.060653 A53 clk: 1200 MHz
687 14:40:56.061217 A73 clk: 1200 MHz
688 14:40:56.061631 CLK81: 166.6M
689 14:40:56.062042 smccc: 00012ab5
690 14:40:56.066230 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 14:40:56.071762 board id: 1
692 14:40:56.077749 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 14:40:56.088328 fw parse done
694 14:40:56.094217 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 14:40:56.136867 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 14:40:56.147753 PIEI prepare done
697 14:40:56.148126 fastboot data load
698 14:40:56.148361 fastboot data verify
699 14:40:56.153380 verify result: 266
700 14:40:56.158874 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 14:40:56.159168 LPDDR4 probe
702 14:40:56.159379 ddr clk to 1584MHz
703 14:40:56.166853 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 14:40:56.204345
705 14:40:56.204934 dmc_version 0001
706 14:40:56.210949 Check phy result
707 14:40:56.216750 INFO : End of CA training
708 14:40:56.217270 INFO : End of initialization
709 14:40:56.222383 INFO : Training has run successfully!
710 14:40:56.222753 Check phy result
711 14:40:56.227954 INFO : End of initialization
712 14:40:56.228488 INFO : End of read enable training
713 14:40:56.231317 INFO : End of fine write leveling
714 14:40:56.236889 INFO : End of Write leveling coarse delay
715 14:40:56.242463 INFO : Training has run successfully!
716 14:40:56.242823 Check phy result
717 14:40:56.243062 INFO : End of initialization
718 14:40:56.248096 INFO : End of read dq deskew training
719 14:40:56.253647 INFO : End of MPR read delay center optimization
720 14:40:56.254118 INFO : End of write delay center optimization
721 14:40:56.259260 INFO : End of read delay center optimization
722 14:40:56.264858 INFO : End of max read latency training
723 14:40:56.265228 INFO : Training has run successfully!
724 14:40:56.270447 1D training succeed
725 14:40:56.276344 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 14:40:56.324020 Check phy result
727 14:40:56.324606 INFO : End of initialization
728 14:40:56.346633 INFO : End of 2D read delay Voltage center optimization
729 14:40:56.366023 INFO : End of 2D read delay Voltage center optimization
730 14:40:56.418164 INFO : End of 2D write delay Voltage center optimization
731 14:40:56.467474 INFO : End of 2D write delay Voltage center optimization
732 14:40:56.473070 INFO : Training has run successfully!
733 14:40:56.473577
734 14:40:56.473992 channel==0
735 14:40:56.478715 RxClkDly_Margin_A0==88 ps 9
736 14:40:56.479204 TxDqDly_Margin_A0==98 ps 10
737 14:40:56.481924 RxClkDly_Margin_A1==88 ps 9
738 14:40:56.482415 TxDqDly_Margin_A1==98 ps 10
739 14:40:56.487566 TrainedVREFDQ_A0==74
740 14:40:56.488089 TrainedVREFDQ_A1==74
741 14:40:56.488506 VrefDac_Margin_A0==25
742 14:40:56.493164 DeviceVref_Margin_A0==40
743 14:40:56.493645 VrefDac_Margin_A1==25
744 14:40:56.498755 DeviceVref_Margin_A1==40
745 14:40:56.499239
746 14:40:56.499650
747 14:40:56.500086 channel==1
748 14:40:56.500495 RxClkDly_Margin_A0==88 ps 9
749 14:40:56.502105 TxDqDly_Margin_A0==88 ps 9
750 14:40:56.507675 RxClkDly_Margin_A1==88 ps 9
751 14:40:56.508186 TxDqDly_Margin_A1==88 ps 9
752 14:40:56.508604 TrainedVREFDQ_A0==77
753 14:40:56.513359 TrainedVREFDQ_A1==77
754 14:40:56.513837 VrefDac_Margin_A0==23
755 14:40:56.518882 DeviceVref_Margin_A0==37
756 14:40:56.519353 VrefDac_Margin_A1==24
757 14:40:56.519762 DeviceVref_Margin_A1==37
758 14:40:56.520202
759 14:40:56.527845 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 14:40:56.528367
761 14:40:56.555878 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000018 00000016 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 14:40:56.556463 2D training succeed
763 14:40:56.561500 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 14:40:56.567100 auto size-- 65535DDR cs0 size: 2048MB
765 14:40:56.567590 DDR cs1 size: 2048MB
766 14:40:56.572559 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 14:40:56.573041 cs0 DataBus test pass
768 14:40:56.578151 cs1 DataBus test pass
769 14:40:56.578619 cs0 AddrBus test pass
770 14:40:56.583758 cs1 AddrBus test pass
771 14:40:56.584264
772 14:40:56.584676 100bdlr_step_size ps== 420
773 14:40:56.585091 result report
774 14:40:56.589330 boot times 0Enable ddr reg access
775 14:40:56.595641 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 14:40:56.609297 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 14:40:57.182748 0.0;M3 CHK:0;cm4_sp_mode 0
778 14:40:57.183145 MVN_1=0x00000000
779 14:40:57.188221 MVN_2=0x00000000
780 14:40:57.193983 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 14:40:57.194285 OPS=0x10
782 14:40:57.194511 ring efuse init
783 14:40:57.194722 chipver efuse init
784 14:40:57.199602 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 14:40:57.205123 [0.018961 Inits done]
786 14:40:57.205475 secure task start!
787 14:40:57.205708 high task start!
788 14:40:57.209659 low task start!
789 14:40:57.209964 run into bl31
790 14:40:57.216304 NOTICE: BL31: v1.3(release):4fc40b1
791 14:40:57.224272 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 14:40:57.224600 NOTICE: BL31: G12A normal boot!
793 14:40:57.249517 NOTICE: BL31: BL33 decompress pass
794 14:40:57.255188 ERROR: Error initializing runtime service opteed_fast
795 14:40:58.488139
796 14:40:58.488582
797 14:40:58.496484 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 14:40:58.496987
799 14:40:58.497362 Model: Libre Computer AML-A311D-CC Alta
800 14:40:58.704987 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 14:40:58.728377 DRAM: 2 GiB (effective 3.8 GiB)
802 14:40:58.871380 Core: 408 devices, 31 uclasses, devicetree: separate
803 14:40:58.877172 WDT: Not starting watchdog@f0d0
804 14:40:58.909467 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 14:40:58.921870 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 14:40:58.926848 ** Bad device specification mmc 0 **
807 14:40:58.937200 Card did not respond to voltage select! : -110
808 14:40:58.944847 ** Bad device specification mmc 0 **
809 14:40:58.945197 Couldn't find partition mmc 0
810 14:40:58.953203 Card did not respond to voltage select! : -110
811 14:40:58.958866 ** Bad device specification mmc 0 **
812 14:40:58.959395 Couldn't find partition mmc 0
813 14:40:58.963869 Error: could not access storage.
814 14:40:59.307518 Net: eth0: ethernet@ff3f0000
815 14:40:59.308352 starting USB...
816 14:40:59.559137 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 14:40:59.559574 Starting the controller
818 14:40:59.566153 USB XHCI 1.10
819 14:41:01.732425 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 14:41:01.733193 bl2_stage_init 0x01
821 14:41:01.733538 bl2_stage_init 0x81
822 14:41:01.734344 hw id: 0x0000 - pwm id 0x01
823 14:41:01.734688 bl2_stage_init 0xc1
824 14:41:01.735010 bl2_stage_init 0x02
825 14:41:01.735318
826 14:41:01.740020 L0:00000000
827 14:41:01.747459 L1:20000703
828 14:41:01.748147 L2:00008067
829 14:41:01.748759 L3:14000000
830 14:41:01.749642 B2:00402000
831 14:41:01.750372 B1:e0f83180
832 14:41:01.750826
833 14:41:01.751181 TE: 58159
834 14:41:01.751431
835 14:41:01.754120 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 14:41:01.755087
837 14:41:01.755679 Board ID = 1
838 14:41:01.756197 Set A53 clk to 24M
839 14:41:01.756494 Set A73 clk to 24M
840 14:41:01.760683 Set clk81 to 24M
841 14:41:01.761072 A53 clk: 1200 MHz
842 14:41:01.761303 A73 clk: 1200 MHz
843 14:41:01.765484 CLK81: 166.6M
844 14:41:01.765910 smccc: 00012ab5
845 14:41:01.770633 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 14:41:01.771032 board id: 1
847 14:41:01.779209 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 14:41:01.789972 fw parse done
849 14:41:01.795872 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 14:41:01.838397 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 14:41:01.849357 PIEI prepare done
852 14:41:01.849987 fastboot data load
853 14:41:01.850457 fastboot data verify
854 14:41:01.855129 verify result: 266
855 14:41:01.860558 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 14:41:01.860955 LPDDR4 probe
857 14:41:01.861211 ddr clk to 1584MHz
858 14:41:01.868606 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 14:41:01.905938
860 14:41:01.906617 dmc_version 0001
861 14:41:01.912507 Check phy result
862 14:41:01.918240 INFO : End of CA training
863 14:41:01.918778 INFO : End of initialization
864 14:41:01.923959 INFO : Training has run successfully!
865 14:41:01.924521 Check phy result
866 14:41:01.929426 INFO : End of initialization
867 14:41:01.929947 INFO : End of read enable training
868 14:41:01.935073 INFO : End of fine write leveling
869 14:41:01.940720 INFO : End of Write leveling coarse delay
870 14:41:01.941264 INFO : Training has run successfully!
871 14:41:01.941754 Check phy result
872 14:41:01.946205 INFO : End of initialization
873 14:41:01.946739 INFO : End of read dq deskew training
874 14:41:01.951919 INFO : End of MPR read delay center optimization
875 14:41:01.957659 INFO : End of write delay center optimization
876 14:41:01.963120 INFO : End of read delay center optimization
877 14:41:01.963661 INFO : End of max read latency training
878 14:41:01.968736 INFO : Training has run successfully!
879 14:41:01.969279 1D training succeed
880 14:41:01.977819 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 14:41:02.025473 Check phy result
882 14:41:02.026124 INFO : End of initialization
883 14:41:02.047165 INFO : End of 2D read delay Voltage center optimization
884 14:41:02.067630 INFO : End of 2D read delay Voltage center optimization
885 14:41:02.119509 INFO : End of 2D write delay Voltage center optimization
886 14:41:02.168803 INFO : End of 2D write delay Voltage center optimization
887 14:41:02.174634 INFO : Training has run successfully!
888 14:41:02.175315
889 14:41:02.175777 channel==0
890 14:41:02.180005 RxClkDly_Margin_A0==88 ps 9
891 14:41:02.180483 TxDqDly_Margin_A0==98 ps 10
892 14:41:02.185666 RxClkDly_Margin_A1==88 ps 9
893 14:41:02.186037 TxDqDly_Margin_A1==88 ps 9
894 14:41:02.186267 TrainedVREFDQ_A0==74
895 14:41:02.191233 TrainedVREFDQ_A1==74
896 14:41:02.191874 VrefDac_Margin_A0==25
897 14:41:02.192630 DeviceVref_Margin_A0==40
898 14:41:02.196851 VrefDac_Margin_A1==25
899 14:41:02.197367 DeviceVref_Margin_A1==40
900 14:41:02.197804
901 14:41:02.198240
902 14:41:02.198673 channel==1
903 14:41:02.202456 RxClkDly_Margin_A0==98 ps 10
904 14:41:02.202960 TxDqDly_Margin_A0==98 ps 10
905 14:41:02.208111 RxClkDly_Margin_A1==98 ps 10
906 14:41:02.208692 TxDqDly_Margin_A1==88 ps 9
907 14:41:02.213674 TrainedVREFDQ_A0==77
908 14:41:02.214301 TrainedVREFDQ_A1==77
909 14:41:02.214738 VrefDac_Margin_A0==22
910 14:41:02.219565 DeviceVref_Margin_A0==37
911 14:41:02.220168 VrefDac_Margin_A1==22
912 14:41:02.224792 DeviceVref_Margin_A1==37
913 14:41:02.225147
914 14:41:02.225446 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 14:41:02.225914
916 14:41:02.258355 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
917 14:41:02.258798 2D training succeed
918 14:41:02.264001 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 14:41:02.269834 auto size-- 65535DDR cs0 size: 2048MB
920 14:41:02.270261 DDR cs1 size: 2048MB
921 14:41:02.275700 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 14:41:02.276481 cs0 DataBus test pass
923 14:41:02.281088 cs1 DataBus test pass
924 14:41:02.281497 cs0 AddrBus test pass
925 14:41:02.282393 cs1 AddrBus test pass
926 14:41:02.282877
927 14:41:02.287823 100bdlr_step_size ps== 420
928 14:41:02.288509 result report
929 14:41:02.293169 boot times 0Enable ddr reg access
930 14:41:02.297333 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 14:41:02.310948 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 14:41:02.884572 0.0;M3 CHK:0;cm4_sp_mode 0
933 14:41:02.885252 MVN_1=0x00000000
934 14:41:02.890213 MVN_2=0x00000000
935 14:41:02.895861 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 14:41:02.896632 OPS=0x10
937 14:41:02.896879 ring efuse init
938 14:41:02.897204 chipver efuse init
939 14:41:02.901306 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 14:41:02.907107 [0.018961 Inits done]
941 14:41:02.907931 secure task start!
942 14:41:02.908266 high task start!
943 14:41:02.911457 low task start!
944 14:41:02.911800 run into bl31
945 14:41:02.918450 NOTICE: BL31: v1.3(release):4fc40b1
946 14:41:02.925954 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 14:41:02.926365 NOTICE: BL31: G12A normal boot!
948 14:41:02.951368 NOTICE: BL31: BL33 decompress pass
949 14:41:02.957496 ERROR: Error initializing runtime service opteed_fast
950 14:41:04.189956
951 14:41:04.190384
952 14:41:04.198281 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 14:41:04.198745
954 14:41:04.199074 Model: Libre Computer AML-A311D-CC Alta
955 14:41:04.406791 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 14:41:04.430152 DRAM: 2 GiB (effective 3.8 GiB)
957 14:41:04.573127 Core: 408 devices, 31 uclasses, devicetree: separate
958 14:41:04.580264 WDT: Not starting watchdog@f0d0
959 14:41:04.611401 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 14:41:04.623754 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 14:41:04.628789 ** Bad device specification mmc 0 **
962 14:41:04.639128 Card did not respond to voltage select! : -110
963 14:41:04.646763 ** Bad device specification mmc 0 **
964 14:41:04.647451 Couldn't find partition mmc 0
965 14:41:04.655106 Card did not respond to voltage select! : -110
966 14:41:04.660614 ** Bad device specification mmc 0 **
967 14:41:04.661297 Couldn't find partition mmc 0
968 14:41:04.665687 Error: could not access storage.
969 14:41:05.008141 Net: eth0: ethernet@ff3f0000
970 14:41:05.008903 starting USB...
971 14:41:05.259967 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 14:41:05.260743 Starting the controller
973 14:41:05.266893 USB XHCI 1.10
974 14:41:07.128532 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 14:41:07.129327 bl2_stage_init 0x01
976 14:41:07.129899 bl2_stage_init 0x81
977 14:41:07.134175 hw id: 0x0000 - pwm id 0x01
978 14:41:07.134810 bl2_stage_init 0xc1
979 14:41:07.135354 bl2_stage_init 0x02
980 14:41:07.135885
981 14:41:07.139828 L0:00000000
982 14:41:07.140495 L1:20000703
983 14:41:07.141041 L2:00008067
984 14:41:07.141558 L3:14000000
985 14:41:07.145396 B2:00402000
986 14:41:07.146019 B1:e0f83180
987 14:41:07.146552
988 14:41:07.147088 TE: 58159
989 14:41:07.147604
990 14:41:07.150965 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 14:41:07.151608
992 14:41:07.152198 Board ID = 1
993 14:41:07.156576 Set A53 clk to 24M
994 14:41:07.157209 Set A73 clk to 24M
995 14:41:07.157745 Set clk81 to 24M
996 14:41:07.162104 A53 clk: 1200 MHz
997 14:41:07.162739 A73 clk: 1200 MHz
998 14:41:07.163278 CLK81: 166.6M
999 14:41:07.163796 smccc: 00012ab5
1000 14:41:07.167820 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 14:41:07.173238 board id: 1
1002 14:41:07.179112 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 14:41:07.189823 fw parse done
1004 14:41:07.195862 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 14:41:07.238348 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 14:41:07.249267 PIEI prepare done
1007 14:41:07.249914 fastboot data load
1008 14:41:07.250440 fastboot data verify
1009 14:41:07.254943 verify result: 266
1010 14:41:07.260532 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 14:41:07.261155 LPDDR4 probe
1012 14:41:07.261663 ddr clk to 1584MHz
1013 14:41:07.268505 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 14:41:07.305807
1015 14:41:07.306427 dmc_version 0001
1016 14:41:07.312487 Check phy result
1017 14:41:07.318371 INFO : End of CA training
1018 14:41:07.318988 INFO : End of initialization
1019 14:41:07.323971 INFO : Training has run successfully!
1020 14:41:07.324606 Check phy result
1021 14:41:07.329582 INFO : End of initialization
1022 14:41:07.330253 INFO : End of read enable training
1023 14:41:07.332796 INFO : End of fine write leveling
1024 14:41:07.338428 INFO : End of Write leveling coarse delay
1025 14:41:07.344011 INFO : Training has run successfully!
1026 14:41:07.344657 Check phy result
1027 14:41:07.345205 INFO : End of initialization
1028 14:41:07.349646 INFO : End of read dq deskew training
1029 14:41:07.355200 INFO : End of MPR read delay center optimization
1030 14:41:07.355815 INFO : End of write delay center optimization
1031 14:41:07.360805 INFO : End of read delay center optimization
1032 14:41:07.366389 INFO : End of max read latency training
1033 14:41:07.367006 INFO : Training has run successfully!
1034 14:41:07.371974 1D training succeed
1035 14:41:07.377988 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 14:41:07.425528 Check phy result
1037 14:41:07.426180 INFO : End of initialization
1038 14:41:07.447308 INFO : End of 2D read delay Voltage center optimization
1039 14:41:07.467533 INFO : End of 2D read delay Voltage center optimization
1040 14:41:07.519890 INFO : End of 2D write delay Voltage center optimization
1041 14:41:07.569149 INFO : End of 2D write delay Voltage center optimization
1042 14:41:07.574586 INFO : Training has run successfully!
1043 14:41:07.575097
1044 14:41:07.575528 channel==0
1045 14:41:07.580105 RxClkDly_Margin_A0==88 ps 9
1046 14:41:07.580615 TxDqDly_Margin_A0==98 ps 10
1047 14:41:07.583388 RxClkDly_Margin_A1==88 ps 9
1048 14:41:07.583875 TxDqDly_Margin_A1==88 ps 9
1049 14:41:07.589050 TrainedVREFDQ_A0==74
1050 14:41:07.589579 TrainedVREFDQ_A1==74
1051 14:41:07.589996 VrefDac_Margin_A0==25
1052 14:41:07.594629 DeviceVref_Margin_A0==40
1053 14:41:07.595142 VrefDac_Margin_A1==25
1054 14:41:07.600237 DeviceVref_Margin_A1==40
1055 14:41:07.600759
1056 14:41:07.601188
1057 14:41:07.601598 channel==1
1058 14:41:07.601999 RxClkDly_Margin_A0==98 ps 10
1059 14:41:07.605820 TxDqDly_Margin_A0==98 ps 10
1060 14:41:07.606329 RxClkDly_Margin_A1==88 ps 9
1061 14:41:07.611397 TxDqDly_Margin_A1==88 ps 9
1062 14:41:07.611916 TrainedVREFDQ_A0==77
1063 14:41:07.612369 TrainedVREFDQ_A1==77
1064 14:41:07.616981 VrefDac_Margin_A0==22
1065 14:41:07.617477 DeviceVref_Margin_A0==37
1066 14:41:07.622609 VrefDac_Margin_A1==24
1067 14:41:07.623096 DeviceVref_Margin_A1==37
1068 14:41:07.623533
1069 14:41:07.628123 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 14:41:07.628624
1071 14:41:07.656054 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 14:41:07.661713 2D training succeed
1073 14:41:07.667297 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 14:41:07.667789 auto size-- 65535DDR cs0 size: 2048MB
1075 14:41:07.672927 DDR cs1 size: 2048MB
1076 14:41:07.673425 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 14:41:07.678489 cs0 DataBus test pass
1078 14:41:07.678974 cs1 DataBus test pass
1079 14:41:07.679382 cs0 AddrBus test pass
1080 14:41:07.684094 cs1 AddrBus test pass
1081 14:41:07.684591
1082 14:41:07.685006 100bdlr_step_size ps== 420
1083 14:41:07.685425 result report
1084 14:41:07.689701 boot times 0Enable ddr reg access
1085 14:41:07.697347 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 14:41:07.710838 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 14:41:08.284421 0.0;M3 CHK:0;cm4_sp_mode 0
1088 14:41:08.284985 MVN_1=0x00000000
1089 14:41:08.289861 MVN_2=0x00000000
1090 14:41:08.295620 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 14:41:08.296141 OPS=0x10
1092 14:41:08.296569 ring efuse init
1093 14:41:08.296974 chipver efuse init
1094 14:41:08.301214 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 14:41:08.306817 [0.018961 Inits done]
1096 14:41:08.307290 secure task start!
1097 14:41:08.307698 high task start!
1098 14:41:08.311400 low task start!
1099 14:41:08.311872 run into bl31
1100 14:41:08.318090 NOTICE: BL31: v1.3(release):4fc40b1
1101 14:41:08.325875 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 14:41:08.326345 NOTICE: BL31: G12A normal boot!
1103 14:41:08.351209 NOTICE: BL31: BL33 decompress pass
1104 14:41:08.356890 ERROR: Error initializing runtime service opteed_fast
1105 14:41:09.589843
1106 14:41:09.590451
1107 14:41:09.598163 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 14:41:09.598656
1109 14:41:09.599074 Model: Libre Computer AML-A311D-CC Alta
1110 14:41:09.806627 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 14:41:09.830098 DRAM: 2 GiB (effective 3.8 GiB)
1112 14:41:09.973028 Core: 408 devices, 31 uclasses, devicetree: separate
1113 14:41:09.978805 WDT: Not starting watchdog@f0d0
1114 14:41:10.011084 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 14:41:10.023530 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 14:41:10.029086 ** Bad device specification mmc 0 **
1117 14:41:10.039011 Card did not respond to voltage select! : -110
1118 14:41:10.046492 ** Bad device specification mmc 0 **
1119 14:41:10.046944 Couldn't find partition mmc 0
1120 14:41:10.054828 Card did not respond to voltage select! : -110
1121 14:41:10.060339 ** Bad device specification mmc 0 **
1122 14:41:10.060776 Couldn't find partition mmc 0
1123 14:41:10.065397 Error: could not access storage.
1124 14:41:10.407953 Net: eth0: ethernet@ff3f0000
1125 14:41:10.408575 starting USB...
1126 14:41:10.659717 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 14:41:10.660286 Starting the controller
1128 14:41:10.666640 USB XHCI 1.10
1129 14:41:12.223841 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 14:41:12.232245 scanning usb for storage devices... 0 Storage Device(s) found
1132 14:41:12.283856 Hit any key to stop autoboot: 1
1133 14:41:12.284872 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 14:41:12.285734 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1135 14:41:12.286344 Setting prompt string to ['=>']
1136 14:41:12.286969 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1137 14:41:12.299701 0
1138 14:41:12.300699 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 14:41:12.301193 Sending with 10 millisecond of delay
1141 14:41:13.436064 => setenv autoload no
1142 14:41:13.447099 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1143 14:41:13.449844 setenv autoload no
1144 14:41:13.450511 Sending with 10 millisecond of delay
1146 14:41:15.247910 => setenv initrd_high 0xffffffff
1147 14:41:15.258957 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1148 14:41:15.260132 setenv initrd_high 0xffffffff
1149 14:41:15.261011 Sending with 10 millisecond of delay
1151 14:41:16.878248 => setenv fdt_high 0xffffffff
1152 14:41:16.889252 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 14:41:16.890338 setenv fdt_high 0xffffffff
1154 14:41:16.891207 Sending with 10 millisecond of delay
1156 14:41:17.183396 => dhcp
1157 14:41:17.194423 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 14:41:17.195496 dhcp
1159 14:41:17.196101 Speed: 1000, full duplex
1160 14:41:17.196632 BOOTP broadcast 1
1161 14:41:17.202831 DHCP client bound to address 192.168.6.27 (8 ms)
1162 14:41:17.203724 Sending with 10 millisecond of delay
1164 14:41:18.880960 => setenv serverip 192.168.6.2
1165 14:41:18.892029 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 14:41:18.893158 setenv serverip 192.168.6.2
1167 14:41:18.893992 Sending with 10 millisecond of delay
1169 14:41:22.618211 => tftpboot 0x01080000 940302/tftp-deploy-uylh40cu/kernel/uImage
1170 14:41:22.629196 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 14:41:22.630267 tftpboot 0x01080000 940302/tftp-deploy-uylh40cu/kernel/uImage
1172 14:41:22.630845 Speed: 1000, full duplex
1173 14:41:22.631384 Using ethernet@ff3f0000 device
1174 14:41:22.632251 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 14:41:22.637559 Filename '940302/tftp-deploy-uylh40cu/kernel/uImage'.
1176 14:41:22.641526 Load address: 0x1080000
1177 14:41:25.422079 Loading: *################################################## 43.6 MiB
1178 14:41:25.422698 15.7 MiB/s
1179 14:41:25.423125 done
1180 14:41:25.426730 Bytes transferred = 45713984 (2b98a40 hex)
1181 14:41:25.427524 Sending with 10 millisecond of delay
1183 14:41:30.114101 => tftpboot 0x08000000 940302/tftp-deploy-uylh40cu/ramdisk/ramdisk.cpio.gz.uboot
1184 14:41:30.124896 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 14:41:30.125718 tftpboot 0x08000000 940302/tftp-deploy-uylh40cu/ramdisk/ramdisk.cpio.gz.uboot
1186 14:41:30.126160 Speed: 1000, full duplex
1187 14:41:30.126567 Using ethernet@ff3f0000 device
1188 14:41:30.127688 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 14:41:30.139550 Filename '940302/tftp-deploy-uylh40cu/ramdisk/ramdisk.cpio.gz.uboot'.
1190 14:41:30.140063 Load address: 0x8000000
1191 14:41:37.040470 Loading: *########################T ######################### UDP wrong checksum 00000005 00006832
1192 14:41:42.040528 T UDP wrong checksum 00000005 00006832
1193 14:41:52.043803 T T UDP wrong checksum 00000005 00006832
1194 14:42:12.049060 T T T T UDP wrong checksum 00000005 00006832
1195 14:42:12.551419 UDP wrong checksum 000000ff 0000b4dc
1196 14:42:12.607417 UDP wrong checksum 000000ff 000045cf
1197 14:42:16.192021 UDP wrong checksum 000000ff 00008efc
1198 14:42:16.224291 UDP wrong checksum 000000ff 0000e778
1199 14:42:27.052216 T T
1200 14:42:27.052814 Retry count exceeded; starting again
1202 14:42:27.054226 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1205 14:42:27.056090 end: 2.4 uboot-commands (duration 00:01:52) [common]
1207 14:42:27.057526 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1209 14:42:27.058560 end: 2 uboot-action (duration 00:01:52) [common]
1211 14:42:27.060089 Cleaning after the job
1212 14:42:27.060630 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/ramdisk
1213 14:42:27.061875 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/kernel
1214 14:42:27.070926 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/dtb
1215 14:42:27.072050 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/nfsrootfs
1216 14:42:27.113748 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/940302/tftp-deploy-uylh40cu/modules
1217 14:42:27.120288 start: 4.1 power-off (timeout 00:00:30) [common]
1218 14:42:27.120862 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1219 14:42:27.152466 >> OK - accepted request
1220 14:42:27.154125 Returned 0 in 0 seconds
1221 14:42:27.254851 end: 4.1 power-off (duration 00:00:00) [common]
1223 14:42:27.255811 start: 4.2 read-feedback (timeout 00:10:00) [common]
1224 14:42:27.256503 Listened to connection for namespace 'common' for up to 1s
1225 14:42:28.257444 Finalising connection for namespace 'common'
1226 14:42:28.258132 Disconnecting from shell: Finalise
1227 14:42:28.258639 =>
1228 14:42:28.359610 end: 4.2 read-feedback (duration 00:00:01) [common]
1229 14:42:28.360321 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/940302
1230 14:42:31.119701 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/940302
1231 14:42:31.120327 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.