Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:24:05.513400 lava-dispatcher, installed at version: 2024.01
2 02:24:05.514211 start: 0 validate
3 02:24:05.514689 Start time: 2024-11-07 02:24:05.514659+00:00 (UTC)
4 02:24:05.515222 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:24:05.515772 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 02:24:05.559743 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:24:05.560322 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-62-g773a2a71b65d8%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:24:05.589612 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:24:05.590280 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-62-g773a2a71b65d8%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:24:05.624665 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:24:05.625196 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-62-g773a2a71b65d8%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 02:24:05.665139 validate duration: 0.15
14 02:24:05.666006 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 02:24:05.666357 start: 1.1 download-retry (timeout 00:10:00) [common]
16 02:24:05.666673 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 02:24:05.667254 Not decompressing ramdisk as can be used compressed.
18 02:24:05.667705 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 02:24:05.667953 saving as /var/lib/lava/dispatcher/tmp/949953/tftp-deploy-ac4a9eou/ramdisk/rootfs.cpio.gz
20 02:24:05.668242 total size: 47897469 (45 MB)
21 02:24:05.708105 progress 0 % (0 MB)
22 02:24:05.739054 progress 5 % (2 MB)
23 02:24:05.768473 progress 10 % (4 MB)
24 02:24:05.797720 progress 15 % (6 MB)
25 02:24:05.827084 progress 20 % (9 MB)
26 02:24:05.856107 progress 25 % (11 MB)
27 02:24:05.885383 progress 30 % (13 MB)
28 02:24:05.914284 progress 35 % (16 MB)
29 02:24:05.943082 progress 40 % (18 MB)
30 02:24:05.972351 progress 45 % (20 MB)
31 02:24:06.001204 progress 50 % (22 MB)
32 02:24:06.030326 progress 55 % (25 MB)
33 02:24:06.060020 progress 60 % (27 MB)
34 02:24:06.088856 progress 65 % (29 MB)
35 02:24:06.117683 progress 70 % (32 MB)
36 02:24:06.146460 progress 75 % (34 MB)
37 02:24:06.175685 progress 80 % (36 MB)
38 02:24:06.204597 progress 85 % (38 MB)
39 02:24:06.233481 progress 90 % (41 MB)
40 02:24:06.262616 progress 95 % (43 MB)
41 02:24:06.290307 progress 100 % (45 MB)
42 02:24:06.291048 45 MB downloaded in 0.62 s (73.35 MB/s)
43 02:24:06.291629 end: 1.1.1 http-download (duration 00:00:01) [common]
45 02:24:06.292609 end: 1.1 download-retry (duration 00:00:01) [common]
46 02:24:06.292929 start: 1.2 download-retry (timeout 00:09:59) [common]
47 02:24:06.293219 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 02:24:06.293710 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-62-g773a2a71b65d8/arm64/defconfig/gcc-12/kernel/Image
49 02:24:06.293970 saving as /var/lib/lava/dispatcher/tmp/949953/tftp-deploy-ac4a9eou/kernel/Image
50 02:24:06.294189 total size: 45713920 (43 MB)
51 02:24:06.294410 No compression specified
52 02:24:06.339820 progress 0 % (0 MB)
53 02:24:06.366649 progress 5 % (2 MB)
54 02:24:06.394235 progress 10 % (4 MB)
55 02:24:06.421576 progress 15 % (6 MB)
56 02:24:06.448521 progress 20 % (8 MB)
57 02:24:06.475007 progress 25 % (10 MB)
58 02:24:06.502740 progress 30 % (13 MB)
59 02:24:06.531953 progress 35 % (15 MB)
60 02:24:06.558867 progress 40 % (17 MB)
61 02:24:06.585425 progress 45 % (19 MB)
62 02:24:06.612302 progress 50 % (21 MB)
63 02:24:06.638691 progress 55 % (24 MB)
64 02:24:06.665388 progress 60 % (26 MB)
65 02:24:06.691607 progress 65 % (28 MB)
66 02:24:06.718762 progress 70 % (30 MB)
67 02:24:06.745571 progress 75 % (32 MB)
68 02:24:06.772375 progress 80 % (34 MB)
69 02:24:06.799103 progress 85 % (37 MB)
70 02:24:06.825781 progress 90 % (39 MB)
71 02:24:06.852280 progress 95 % (41 MB)
72 02:24:06.878042 progress 100 % (43 MB)
73 02:24:06.878537 43 MB downloaded in 0.58 s (74.61 MB/s)
74 02:24:06.879016 end: 1.2.1 http-download (duration 00:00:01) [common]
76 02:24:06.879832 end: 1.2 download-retry (duration 00:00:01) [common]
77 02:24:06.880135 start: 1.3 download-retry (timeout 00:09:59) [common]
78 02:24:06.880404 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 02:24:06.880862 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-62-g773a2a71b65d8/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 02:24:06.881135 saving as /var/lib/lava/dispatcher/tmp/949953/tftp-deploy-ac4a9eou/dtb/meson-g12b-a311d-libretech-cc.dtb
81 02:24:06.881348 total size: 54703 (0 MB)
82 02:24:06.881558 No compression specified
83 02:24:06.917815 progress 59 % (0 MB)
84 02:24:06.918643 progress 100 % (0 MB)
85 02:24:06.919185 0 MB downloaded in 0.04 s (1.38 MB/s)
86 02:24:06.919640 end: 1.3.1 http-download (duration 00:00:00) [common]
88 02:24:06.920495 end: 1.3 download-retry (duration 00:00:00) [common]
89 02:24:06.920759 start: 1.4 download-retry (timeout 00:09:59) [common]
90 02:24:06.921019 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 02:24:06.921477 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-62-g773a2a71b65d8/arm64/defconfig/gcc-12/modules.tar.xz
92 02:24:06.921723 saving as /var/lib/lava/dispatcher/tmp/949953/tftp-deploy-ac4a9eou/modules/modules.tar
93 02:24:06.921927 total size: 11609296 (11 MB)
94 02:24:06.922137 Using unxz to decompress xz
95 02:24:06.955603 progress 0 % (0 MB)
96 02:24:07.021539 progress 5 % (0 MB)
97 02:24:07.095532 progress 10 % (1 MB)
98 02:24:07.191142 progress 15 % (1 MB)
99 02:24:07.283508 progress 20 % (2 MB)
100 02:24:07.375068 progress 25 % (2 MB)
101 02:24:07.451698 progress 30 % (3 MB)
102 02:24:07.530234 progress 35 % (3 MB)
103 02:24:07.603464 progress 40 % (4 MB)
104 02:24:07.679089 progress 45 % (5 MB)
105 02:24:07.763229 progress 50 % (5 MB)
106 02:24:07.840174 progress 55 % (6 MB)
107 02:24:07.925145 progress 60 % (6 MB)
108 02:24:08.005153 progress 65 % (7 MB)
109 02:24:08.085521 progress 70 % (7 MB)
110 02:24:08.163555 progress 75 % (8 MB)
111 02:24:08.246984 progress 80 % (8 MB)
112 02:24:08.326669 progress 85 % (9 MB)
113 02:24:08.406450 progress 90 % (9 MB)
114 02:24:08.484286 progress 95 % (10 MB)
115 02:24:08.561646 progress 100 % (11 MB)
116 02:24:08.573023 11 MB downloaded in 1.65 s (6.71 MB/s)
117 02:24:08.573642 end: 1.4.1 http-download (duration 00:00:02) [common]
119 02:24:08.574468 end: 1.4 download-retry (duration 00:00:02) [common]
120 02:24:08.574742 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 02:24:08.575012 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 02:24:08.575263 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 02:24:08.575521 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 02:24:08.576218 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o
125 02:24:08.577163 makedir: /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin
126 02:24:08.577876 makedir: /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/tests
127 02:24:08.578711 makedir: /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/results
128 02:24:08.579410 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-add-keys
129 02:24:08.580469 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-add-sources
130 02:24:08.581489 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-background-process-start
131 02:24:08.582514 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-background-process-stop
132 02:24:08.583614 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-common-functions
133 02:24:08.584667 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-echo-ipv4
134 02:24:08.585738 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-install-packages
135 02:24:08.586727 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-installed-packages
136 02:24:08.587704 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-os-build
137 02:24:08.588754 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-probe-channel
138 02:24:08.589738 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-probe-ip
139 02:24:08.590759 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-target-ip
140 02:24:08.591739 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-target-mac
141 02:24:08.592766 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-target-storage
142 02:24:08.593770 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-test-case
143 02:24:08.594750 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-test-event
144 02:24:08.595718 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-test-feedback
145 02:24:08.596738 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-test-raise
146 02:24:08.597706 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-test-reference
147 02:24:08.598739 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-test-runner
148 02:24:08.599721 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-test-set
149 02:24:08.600738 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-test-shell
150 02:24:08.601782 Updating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-install-packages (oe)
151 02:24:08.602850 Updating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/bin/lava-installed-packages (oe)
152 02:24:08.603765 Creating /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/environment
153 02:24:08.604662 LAVA metadata
154 02:24:08.605200 - LAVA_JOB_ID=949953
155 02:24:08.605679 - LAVA_DISPATCHER_IP=192.168.6.2
156 02:24:08.606402 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 02:24:08.608406 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 02:24:08.609061 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 02:24:08.609519 skipped lava-vland-overlay
160 02:24:08.610055 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 02:24:08.610615 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 02:24:08.611085 skipped lava-multinode-overlay
163 02:24:08.611611 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 02:24:08.612199 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 02:24:08.612726 Loading test definitions
166 02:24:08.613324 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 02:24:08.613811 Using /lava-949953 at stage 0
168 02:24:08.616252 uuid=949953_1.5.2.4.1 testdef=None
169 02:24:08.616883 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 02:24:08.617463 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 02:24:08.621050 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 02:24:08.622757 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 02:24:08.627070 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 02:24:08.628717 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 02:24:08.632807 runner path: /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/0/tests/0_igt-gpu-panfrost test_uuid 949953_1.5.2.4.1
178 02:24:08.633825 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 02:24:08.635358 Creating lava-test-runner.conf files
181 02:24:08.635764 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949953/lava-overlay-7r3gpx8o/lava-949953/0 for stage 0
182 02:24:08.636437 - 0_igt-gpu-panfrost
183 02:24:08.637082 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 02:24:08.637640 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 02:24:08.667807 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 02:24:08.668244 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 02:24:08.668513 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 02:24:08.668785 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 02:24:08.669053 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 02:24:15.498974 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 02:24:15.499451 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 02:24:15.499725 extracting modules file /var/lib/lava/dispatcher/tmp/949953/tftp-deploy-ac4a9eou/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949953/extract-overlay-ramdisk-vf2w5azl/ramdisk
193 02:24:16.907702 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 02:24:16.908245 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 02:24:16.908544 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949953/compress-overlay-ep3r55o0/overlay-1.5.2.5.tar.gz to ramdisk
196 02:24:16.908763 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949953/compress-overlay-ep3r55o0/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949953/extract-overlay-ramdisk-vf2w5azl/ramdisk
197 02:24:16.939718 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 02:24:16.940236 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 02:24:16.940520 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 02:24:16.940755 Converting downloaded kernel to a uImage
201 02:24:16.941074 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949953/tftp-deploy-ac4a9eou/kernel/Image /var/lib/lava/dispatcher/tmp/949953/tftp-deploy-ac4a9eou/kernel/uImage
202 02:24:17.446852 output: Image Name:
203 02:24:17.447294 output: Created: Thu Nov 7 02:24:16 2024
204 02:24:17.447506 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 02:24:17.447710 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 02:24:17.447911 output: Load Address: 01080000
207 02:24:17.448149 output: Entry Point: 01080000
208 02:24:17.448351 output:
209 02:24:17.448693 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 02:24:17.448966 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 02:24:17.449238 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 02:24:17.449497 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 02:24:17.449752 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 02:24:17.450012 Building ramdisk /var/lib/lava/dispatcher/tmp/949953/extract-overlay-ramdisk-vf2w5azl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949953/extract-overlay-ramdisk-vf2w5azl/ramdisk
215 02:24:24.057068 >> 502362 blocks
216 02:24:44.740111 Adding RAMdisk u-boot header.
217 02:24:44.740868 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949953/extract-overlay-ramdisk-vf2w5azl/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949953/extract-overlay-ramdisk-vf2w5azl/ramdisk.cpio.gz.uboot
218 02:24:45.415233 output: Image Name:
219 02:24:45.415655 output: Created: Thu Nov 7 02:24:44 2024
220 02:24:45.415865 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 02:24:45.416275 output: Data Size: 65711939 Bytes = 64171.82 KiB = 62.67 MiB
222 02:24:45.416683 output: Load Address: 00000000
223 02:24:45.417094 output: Entry Point: 00000000
224 02:24:45.417482 output:
225 02:24:45.418454 rename /var/lib/lava/dispatcher/tmp/949953/extract-overlay-ramdisk-vf2w5azl/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949953/tftp-deploy-ac4a9eou/ramdisk/ramdisk.cpio.gz.uboot
226 02:24:45.419151 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 02:24:45.419684 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 02:24:45.420237 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 02:24:45.420699 No LXC device requested
230 02:24:45.421188 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 02:24:45.421682 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 02:24:45.422163 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 02:24:45.422562 Checking files for TFTP limit of 4294967296 bytes.
234 02:24:45.425220 end: 1 tftp-deploy (duration 00:00:40) [common]
235 02:24:45.425790 start: 2 uboot-action (timeout 00:05:00) [common]
236 02:24:45.426306 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 02:24:45.426794 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 02:24:45.427285 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 02:24:45.427805 Using kernel file from prepare-kernel: 949953/tftp-deploy-ac4a9eou/kernel/uImage
240 02:24:45.428435 substitutions:
241 02:24:45.428838 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 02:24:45.429237 - {DTB_ADDR}: 0x01070000
243 02:24:45.429628 - {DTB}: 949953/tftp-deploy-ac4a9eou/dtb/meson-g12b-a311d-libretech-cc.dtb
244 02:24:45.430018 - {INITRD}: 949953/tftp-deploy-ac4a9eou/ramdisk/ramdisk.cpio.gz.uboot
245 02:24:45.430408 - {KERNEL_ADDR}: 0x01080000
246 02:24:45.430794 - {KERNEL}: 949953/tftp-deploy-ac4a9eou/kernel/uImage
247 02:24:45.431183 - {LAVA_MAC}: None
248 02:24:45.431611 - {PRESEED_CONFIG}: None
249 02:24:45.432023 - {PRESEED_LOCAL}: None
250 02:24:45.432411 - {RAMDISK_ADDR}: 0x08000000
251 02:24:45.432792 - {RAMDISK}: 949953/tftp-deploy-ac4a9eou/ramdisk/ramdisk.cpio.gz.uboot
252 02:24:45.433181 - {ROOT_PART}: None
253 02:24:45.433564 - {ROOT}: None
254 02:24:45.433950 - {SERVER_IP}: 192.168.6.2
255 02:24:45.434338 - {TEE_ADDR}: 0x83000000
256 02:24:45.434722 - {TEE}: None
257 02:24:45.435105 Parsed boot commands:
258 02:24:45.435482 - setenv autoload no
259 02:24:45.435865 - setenv initrd_high 0xffffffff
260 02:24:45.436281 - setenv fdt_high 0xffffffff
261 02:24:45.436666 - dhcp
262 02:24:45.437049 - setenv serverip 192.168.6.2
263 02:24:45.437430 - tftpboot 0x01080000 949953/tftp-deploy-ac4a9eou/kernel/uImage
264 02:24:45.437816 - tftpboot 0x08000000 949953/tftp-deploy-ac4a9eou/ramdisk/ramdisk.cpio.gz.uboot
265 02:24:45.438199 - tftpboot 0x01070000 949953/tftp-deploy-ac4a9eou/dtb/meson-g12b-a311d-libretech-cc.dtb
266 02:24:45.438587 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 02:24:45.438979 - bootm 0x01080000 0x08000000 0x01070000
268 02:24:45.439482 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 02:24:45.441014 start: 2.3 connect-device (timeout 00:05:00) [common]
271 02:24:45.441459 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 02:24:45.456409 Setting prompt string to ['lava-test: # ']
273 02:24:45.458084 end: 2.3 connect-device (duration 00:00:00) [common]
274 02:24:45.458698 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 02:24:45.459244 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 02:24:45.459761 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 02:24:45.460941 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 02:24:45.500604 >> OK - accepted request
279 02:24:45.502899 Returned 0 in 0 seconds
280 02:24:45.604069 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 02:24:45.605726 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 02:24:45.606269 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 02:24:45.606774 Setting prompt string to ['Hit any key to stop autoboot']
285 02:24:45.607223 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 02:24:45.608892 Trying 192.168.56.21...
287 02:24:45.609379 Connected to conserv1.
288 02:24:45.609782 Escape character is '^]'.
289 02:24:45.610180
290 02:24:45.610597 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 02:24:45.611011
292 02:24:56.987307 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 02:24:56.987939 bl2_stage_init 0x01
294 02:24:56.988427 bl2_stage_init 0x81
295 02:24:56.993018 hw id: 0x0000 - pwm id 0x01
296 02:24:56.993562 bl2_stage_init 0xc1
297 02:24:56.993986 bl2_stage_init 0x02
298 02:24:56.994397
299 02:24:56.998483 L0:00000000
300 02:24:56.998927 L1:20000703
301 02:24:56.999319 L2:00008067
302 02:24:56.999708 L3:14000000
303 02:24:57.004037 B2:00402000
304 02:24:57.004468 B1:e0f83180
305 02:24:57.004856
306 02:24:57.005244 TE: 58167
307 02:24:57.005631
308 02:24:57.009535 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 02:24:57.009956
310 02:24:57.010344 Board ID = 1
311 02:24:57.015175 Set A53 clk to 24M
312 02:24:57.015605 Set A73 clk to 24M
313 02:24:57.016017 Set clk81 to 24M
314 02:24:57.020856 A53 clk: 1200 MHz
315 02:24:57.021294 A73 clk: 1200 MHz
316 02:24:57.021686 CLK81: 166.6M
317 02:24:57.022068 smccc: 00012abe
318 02:24:57.026329 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 02:24:57.032034 board id: 1
320 02:24:57.038032 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 02:24:57.048391 fw parse done
322 02:24:57.054322 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 02:24:57.096961 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 02:24:57.107867 PIEI prepare done
325 02:24:57.108332 fastboot data load
326 02:24:57.108725 fastboot data verify
327 02:24:57.113590 verify result: 266
328 02:24:57.119161 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 02:24:57.119595 LPDDR4 probe
330 02:24:57.120029 ddr clk to 1584MHz
331 02:24:57.127132 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 02:24:57.164387
333 02:24:57.164822 dmc_version 0001
334 02:24:57.171057 Check phy result
335 02:24:57.176940 INFO : End of CA training
336 02:24:57.177368 INFO : End of initialization
337 02:24:57.182536 INFO : Training has run successfully!
338 02:24:57.182953 Check phy result
339 02:24:57.188178 INFO : End of initialization
340 02:24:57.188595 INFO : End of read enable training
341 02:24:57.193734 INFO : End of fine write leveling
342 02:24:57.199325 INFO : End of Write leveling coarse delay
343 02:24:57.199739 INFO : Training has run successfully!
344 02:24:57.200165 Check phy result
345 02:24:57.204932 INFO : End of initialization
346 02:24:57.205346 INFO : End of read dq deskew training
347 02:24:57.210512 INFO : End of MPR read delay center optimization
348 02:24:57.216090 INFO : End of write delay center optimization
349 02:24:57.221687 INFO : End of read delay center optimization
350 02:24:57.222120 INFO : End of max read latency training
351 02:24:57.227317 INFO : Training has run successfully!
352 02:24:57.227734 1D training succeed
353 02:24:57.236497 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 02:24:57.284158 Check phy result
355 02:24:57.284602 INFO : End of initialization
356 02:24:57.305964 INFO : End of 2D read delay Voltage center optimization
357 02:24:57.326123 INFO : End of 2D read delay Voltage center optimization
358 02:24:57.378158 INFO : End of 2D write delay Voltage center optimization
359 02:24:57.427618 INFO : End of 2D write delay Voltage center optimization
360 02:24:57.433099 INFO : Training has run successfully!
361 02:24:57.433538
362 02:24:57.433938 channel==0
363 02:24:57.438686 RxClkDly_Margin_A0==88 ps 9
364 02:24:57.439113 TxDqDly_Margin_A0==98 ps 10
365 02:24:57.444277 RxClkDly_Margin_A1==88 ps 9
366 02:24:57.444694 TxDqDly_Margin_A1==98 ps 10
367 02:24:57.445089 TrainedVREFDQ_A0==74
368 02:24:57.449893 TrainedVREFDQ_A1==74
369 02:24:57.450316 VrefDac_Margin_A0==25
370 02:24:57.450704 DeviceVref_Margin_A0==40
371 02:24:57.455503 VrefDac_Margin_A1==25
372 02:24:57.455929 DeviceVref_Margin_A1==40
373 02:24:57.456351
374 02:24:57.456742
375 02:24:57.461096 channel==1
376 02:24:57.461516 RxClkDly_Margin_A0==98 ps 10
377 02:24:57.461902 TxDqDly_Margin_A0==88 ps 9
378 02:24:57.466664 RxClkDly_Margin_A1==88 ps 9
379 02:24:57.467102 TxDqDly_Margin_A1==88 ps 9
380 02:24:57.472280 TrainedVREFDQ_A0==76
381 02:24:57.472698 TrainedVREFDQ_A1==77
382 02:24:57.473091 VrefDac_Margin_A0==22
383 02:24:57.477894 DeviceVref_Margin_A0==38
384 02:24:57.478308 VrefDac_Margin_A1==24
385 02:24:57.483450 DeviceVref_Margin_A1==37
386 02:24:57.483861
387 02:24:57.484285 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 02:24:57.484676
389 02:24:57.517081 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 02:24:57.517614 2D training succeed
391 02:24:57.522703 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 02:24:57.528294 auto size-- 65535DDR cs0 size: 2048MB
393 02:24:57.528741 DDR cs1 size: 2048MB
394 02:24:57.533922 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 02:24:57.534348 cs0 DataBus test pass
396 02:24:57.539494 cs1 DataBus test pass
397 02:24:57.539928 cs0 AddrBus test pass
398 02:24:57.540358 cs1 AddrBus test pass
399 02:24:57.540743
400 02:24:57.545100 100bdlr_step_size ps== 420
401 02:24:57.545536 result report
402 02:24:57.550687 boot times 0Enable ddr reg access
403 02:24:57.556014 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 02:24:57.569439 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 02:24:58.143272 0.0;M3 CHK:0;cm4_sp_mode 0
406 02:24:58.143968 MVN_1=0x00000000
407 02:24:58.148692 MVN_2=0x00000000
408 02:24:58.154422 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 02:24:58.154945 OPS=0x10
410 02:24:58.155410 ring efuse init
411 02:24:58.155860 chipver efuse init
412 02:24:58.160072 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 02:24:58.165625 [0.018960 Inits done]
414 02:24:58.166136 secure task start!
415 02:24:58.166589 high task start!
416 02:24:58.170219 low task start!
417 02:24:58.170724 run into bl31
418 02:24:58.176894 NOTICE: BL31: v1.3(release):4fc40b1
419 02:24:58.184712 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 02:24:58.185239 NOTICE: BL31: G12A normal boot!
421 02:24:58.210144 NOTICE: BL31: BL33 decompress pass
422 02:24:58.215779 ERROR: Error initializing runtime service opteed_fast
423 02:24:59.448698
424 02:24:59.449390
425 02:24:59.457104 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 02:24:59.457725
427 02:24:59.458212 Model: Libre Computer AML-A311D-CC Alta
428 02:24:59.665514 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 02:24:59.688887 DRAM: 2 GiB (effective 3.8 GiB)
430 02:24:59.831728 Core: 408 devices, 31 uclasses, devicetree: separate
431 02:24:59.837577 WDT: Not starting watchdog@f0d0
432 02:24:59.870316 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 02:24:59.882283 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 02:24:59.887277 ** Bad device specification mmc 0 **
435 02:24:59.897676 Card did not respond to voltage select! : -110
436 02:24:59.905394 ** Bad device specification mmc 0 **
437 02:24:59.905783 Couldn't find partition mmc 0
438 02:24:59.913601 Card did not respond to voltage select! : -110
439 02:24:59.919230 ** Bad device specification mmc 0 **
440 02:24:59.919776 Couldn't find partition mmc 0
441 02:24:59.924746 Error: could not access storage.
442 02:25:01.187406 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 02:25:01.187836 bl2_stage_init 0x01
444 02:25:01.188099 bl2_stage_init 0x81
445 02:25:01.192916 hw id: 0x0000 - pwm id 0x01
446 02:25:01.193220 bl2_stage_init 0xc1
447 02:25:01.193441 bl2_stage_init 0x02
448 02:25:01.193664
449 02:25:01.198821 L0:00000000
450 02:25:01.199128 L1:20000703
451 02:25:01.199353 L2:00008067
452 02:25:01.199568 L3:14000000
453 02:25:01.204131 B2:00402000
454 02:25:01.204422 B1:e0f83180
455 02:25:01.204639
456 02:25:01.204854 TE: 58124
457 02:25:01.205062
458 02:25:01.209744 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 02:25:01.210203
460 02:25:01.210617 Board ID = 1
461 02:25:01.215334 Set A53 clk to 24M
462 02:25:01.215784 Set A73 clk to 24M
463 02:25:01.216232 Set clk81 to 24M
464 02:25:01.220946 A53 clk: 1200 MHz
465 02:25:01.221395 A73 clk: 1200 MHz
466 02:25:01.221807 CLK81: 166.6M
467 02:25:01.222209 smccc: 00012a92
468 02:25:01.226515 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 02:25:01.232149 board id: 1
470 02:25:01.237963 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 02:25:01.248682 fw parse done
472 02:25:01.254623 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 02:25:01.297316 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 02:25:01.308210 PIEI prepare done
475 02:25:01.308687 fastboot data load
476 02:25:01.309108 fastboot data verify
477 02:25:01.313887 verify result: 266
478 02:25:01.319444 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 02:25:01.319917 LPDDR4 probe
480 02:25:01.320375 ddr clk to 1584MHz
481 02:25:01.327486 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 02:25:01.364709
483 02:25:01.365215 dmc_version 0001
484 02:25:01.371405 Check phy result
485 02:25:01.377282 INFO : End of CA training
486 02:25:01.377765 INFO : End of initialization
487 02:25:01.382889 INFO : Training has run successfully!
488 02:25:01.383361 Check phy result
489 02:25:01.388503 INFO : End of initialization
490 02:25:01.388973 INFO : End of read enable training
491 02:25:01.394039 INFO : End of fine write leveling
492 02:25:01.399663 INFO : End of Write leveling coarse delay
493 02:25:01.400167 INFO : Training has run successfully!
494 02:25:01.400413 Check phy result
495 02:25:01.405256 INFO : End of initialization
496 02:25:01.405763 INFO : End of read dq deskew training
497 02:25:01.410872 INFO : End of MPR read delay center optimization
498 02:25:01.416586 INFO : End of write delay center optimization
499 02:25:01.422103 INFO : End of read delay center optimization
500 02:25:01.422588 INFO : End of max read latency training
501 02:25:01.427722 INFO : Training has run successfully!
502 02:25:01.428252 1D training succeed
503 02:25:01.436846 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 02:25:01.484487 Check phy result
505 02:25:01.485082 INFO : End of initialization
506 02:25:01.506065 INFO : End of 2D read delay Voltage center optimization
507 02:25:01.526516 INFO : End of 2D read delay Voltage center optimization
508 02:25:01.578159 INFO : End of 2D write delay Voltage center optimization
509 02:25:01.627322 INFO : End of 2D write delay Voltage center optimization
510 02:25:01.632898 INFO : Training has run successfully!
511 02:25:01.633377
512 02:25:01.633795 channel==0
513 02:25:01.638553 RxClkDly_Margin_A0==88 ps 9
514 02:25:01.639031 TxDqDly_Margin_A0==98 ps 10
515 02:25:01.644071 RxClkDly_Margin_A1==88 ps 9
516 02:25:01.644554 TxDqDly_Margin_A1==98 ps 10
517 02:25:01.644985 TrainedVREFDQ_A0==74
518 02:25:01.649655 TrainedVREFDQ_A1==74
519 02:25:01.650125 VrefDac_Margin_A0==25
520 02:25:01.650538 DeviceVref_Margin_A0==40
521 02:25:01.655247 VrefDac_Margin_A1==25
522 02:25:01.655702 DeviceVref_Margin_A1==40
523 02:25:01.656141
524 02:25:01.656551
525 02:25:01.660892 channel==1
526 02:25:01.661345 RxClkDly_Margin_A0==98 ps 10
527 02:25:01.661751 TxDqDly_Margin_A0==98 ps 10
528 02:25:01.666519 RxClkDly_Margin_A1==88 ps 9
529 02:25:01.666980 TxDqDly_Margin_A1==88 ps 9
530 02:25:01.672062 TrainedVREFDQ_A0==77
531 02:25:01.672529 TrainedVREFDQ_A1==77
532 02:25:01.672937 VrefDac_Margin_A0==22
533 02:25:01.677707 DeviceVref_Margin_A0==37
534 02:25:01.678161 VrefDac_Margin_A1==24
535 02:25:01.683298 DeviceVref_Margin_A1==37
536 02:25:01.683772
537 02:25:01.684233 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 02:25:01.684645
539 02:25:01.716834 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 02:25:01.717396 2D training succeed
541 02:25:01.722488 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 02:25:01.728148 auto size-- 65535DDR cs0 size: 2048MB
543 02:25:01.728684 DDR cs1 size: 2048MB
544 02:25:01.733654 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 02:25:01.734146 cs0 DataBus test pass
546 02:25:01.739243 cs1 DataBus test pass
547 02:25:01.739715 cs0 AddrBus test pass
548 02:25:01.740163 cs1 AddrBus test pass
549 02:25:01.740579
550 02:25:01.744902 100bdlr_step_size ps== 420
551 02:25:01.745471 result report
552 02:25:01.750502 boot times 0Enable ddr reg access
553 02:25:01.755792 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 02:25:01.769259 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 02:25:02.341364 0.0;M3 CHK:0;cm4_sp_mode 0
556 02:25:02.341799 MVN_1=0x00000000
557 02:25:02.346985 MVN_2=0x00000000
558 02:25:02.352623 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 02:25:02.352998 OPS=0x10
560 02:25:02.353229 ring efuse init
561 02:25:02.353445 chipver efuse init
562 02:25:02.358142 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 02:25:02.363779 [0.018960 Inits done]
564 02:25:02.364153 secure task start!
565 02:25:02.364392 high task start!
566 02:25:02.368225 low task start!
567 02:25:02.368523 run into bl31
568 02:25:02.375027 NOTICE: BL31: v1.3(release):4fc40b1
569 02:25:02.382802 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 02:25:02.383176 NOTICE: BL31: G12A normal boot!
571 02:25:02.408149 NOTICE: BL31: BL33 decompress pass
572 02:25:02.414051 ERROR: Error initializing runtime service opteed_fast
573 02:25:03.646898
574 02:25:03.647564
575 02:25:03.655145 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 02:25:03.655656
577 02:25:03.656155 Model: Libre Computer AML-A311D-CC Alta
578 02:25:03.863640 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 02:25:03.886985 DRAM: 2 GiB (effective 3.8 GiB)
580 02:25:04.030087 Core: 408 devices, 31 uclasses, devicetree: separate
581 02:25:04.035824 WDT: Not starting watchdog@f0d0
582 02:25:04.068047 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 02:25:04.080480 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 02:25:04.085472 ** Bad device specification mmc 0 **
585 02:25:04.095810 Card did not respond to voltage select! : -110
586 02:25:04.103494 ** Bad device specification mmc 0 **
587 02:25:04.104014 Couldn't find partition mmc 0
588 02:25:04.111796 Card did not respond to voltage select! : -110
589 02:25:04.117286 ** Bad device specification mmc 0 **
590 02:25:04.117780 Couldn't find partition mmc 0
591 02:25:04.122415 Error: could not access storage.
592 02:25:04.465950 Net: eth0: ethernet@ff3f0000
593 02:25:04.466528 starting USB...
594 02:25:04.719320 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 02:25:04.724815 Starting the controller
596 02:25:04.725337 USB XHCI 1.10
597 02:25:06.439522 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 02:25:06.440263 bl2_stage_init 0x01
599 02:25:06.440747 bl2_stage_init 0x81
600 02:25:06.444935 hw id: 0x0000 - pwm id 0x01
601 02:25:06.445450 bl2_stage_init 0xc1
602 02:25:06.445910 bl2_stage_init 0x02
603 02:25:06.446361
604 02:25:06.450489 L0:00000000
605 02:25:06.450981 L1:20000703
606 02:25:06.451431 L2:00008067
607 02:25:06.451876 L3:14000000
608 02:25:06.453326 B2:00402000
609 02:25:06.453810 B1:e0f83180
610 02:25:06.454258
611 02:25:06.454705 TE: 58124
612 02:25:06.455151
613 02:25:06.464432 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 02:25:06.464977
615 02:25:06.465451 Board ID = 1
616 02:25:06.465907 Set A53 clk to 24M
617 02:25:06.466356 Set A73 clk to 24M
618 02:25:06.469999 Set clk81 to 24M
619 02:25:06.470808 A53 clk: 1200 MHz
620 02:25:06.471308 A73 clk: 1200 MHz
621 02:25:06.473572 CLK81: 166.6M
622 02:25:06.474061 smccc: 00012a92
623 02:25:06.479144 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 02:25:06.484850 board id: 1
625 02:25:06.489909 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 02:25:06.500591 fw parse done
627 02:25:06.506528 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 02:25:06.549210 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 02:25:06.560485 PIEI prepare done
630 02:25:06.561034 fastboot data load
631 02:25:06.561499 fastboot data verify
632 02:25:06.565855 verify result: 266
633 02:25:06.571451 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 02:25:06.572021 LPDDR4 probe
635 02:25:06.572490 ddr clk to 1584MHz
636 02:25:06.579348 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 02:25:06.616662
638 02:25:06.617429 dmc_version 0001
639 02:25:06.623261 Check phy result
640 02:25:06.629151 INFO : End of CA training
641 02:25:06.629734 INFO : End of initialization
642 02:25:06.634714 INFO : Training has run successfully!
643 02:25:06.635260 Check phy result
644 02:25:06.640330 INFO : End of initialization
645 02:25:06.640846 INFO : End of read enable training
646 02:25:06.643617 INFO : End of fine write leveling
647 02:25:06.649265 INFO : End of Write leveling coarse delay
648 02:25:06.654887 INFO : Training has run successfully!
649 02:25:06.655425 Check phy result
650 02:25:06.655881 INFO : End of initialization
651 02:25:06.660452 INFO : End of read dq deskew training
652 02:25:06.666034 INFO : End of MPR read delay center optimization
653 02:25:06.666607 INFO : End of write delay center optimization
654 02:25:06.671879 INFO : End of read delay center optimization
655 02:25:06.677215 INFO : End of max read latency training
656 02:25:06.677756 INFO : Training has run successfully!
657 02:25:06.682840 1D training succeed
658 02:25:06.688691 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 02:25:06.736336 Check phy result
660 02:25:06.736727 INFO : End of initialization
661 02:25:06.757901 INFO : End of 2D read delay Voltage center optimization
662 02:25:06.778019 INFO : End of 2D read delay Voltage center optimization
663 02:25:06.830255 INFO : End of 2D write delay Voltage center optimization
664 02:25:06.879248 INFO : End of 2D write delay Voltage center optimization
665 02:25:06.884944 INFO : Training has run successfully!
666 02:25:06.885253
667 02:25:06.885473 channel==0
668 02:25:06.890315 RxClkDly_Margin_A0==88 ps 9
669 02:25:06.890723 TxDqDly_Margin_A0==98 ps 10
670 02:25:06.896420 RxClkDly_Margin_A1==88 ps 9
671 02:25:06.896832 TxDqDly_Margin_A1==98 ps 10
672 02:25:06.897165 TrainedVREFDQ_A0==74
673 02:25:06.901489 TrainedVREFDQ_A1==75
674 02:25:06.901797 VrefDac_Margin_A0==25
675 02:25:06.902013 DeviceVref_Margin_A0==40
676 02:25:06.907090 VrefDac_Margin_A1==25
677 02:25:06.907502 DeviceVref_Margin_A1==39
678 02:25:06.907829
679 02:25:06.908308
680 02:25:06.912876 channel==1
681 02:25:06.913374 RxClkDly_Margin_A0==98 ps 10
682 02:25:06.913826 TxDqDly_Margin_A0==98 ps 10
683 02:25:06.918301 RxClkDly_Margin_A1==88 ps 9
684 02:25:06.918792 TxDqDly_Margin_A1==88 ps 9
685 02:25:06.924010 TrainedVREFDQ_A0==77
686 02:25:06.924508 TrainedVREFDQ_A1==77
687 02:25:06.924954 VrefDac_Margin_A0==22
688 02:25:06.929613 DeviceVref_Margin_A0==37
689 02:25:06.930099 VrefDac_Margin_A1==24
690 02:25:06.935147 DeviceVref_Margin_A1==37
691 02:25:06.935638
692 02:25:06.936271 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 02:25:06.936798
694 02:25:06.968594 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
695 02:25:06.969119 2D training succeed
696 02:25:06.974206 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 02:25:06.979793 auto size-- 65535DDR cs0 size: 2048MB
698 02:25:06.980289 DDR cs1 size: 2048MB
699 02:25:06.985431 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 02:25:06.985886 cs0 DataBus test pass
701 02:25:06.991002 cs1 DataBus test pass
702 02:25:06.991448 cs0 AddrBus test pass
703 02:25:06.991845 cs1 AddrBus test pass
704 02:25:06.992279
705 02:25:06.996591 100bdlr_step_size ps== 420
706 02:25:06.997046 result report
707 02:25:07.002223 boot times 0Enable ddr reg access
708 02:25:07.007552 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 02:25:07.021011 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 02:25:07.593117 0.0;M3 CHK:0;cm4_sp_mode 0
711 02:25:07.593802 MVN_1=0x00000000
712 02:25:07.598552 MVN_2=0x00000000
713 02:25:07.604455 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 02:25:07.605051 OPS=0x10
715 02:25:07.605582 ring efuse init
716 02:25:07.606059 chipver efuse init
717 02:25:07.609882 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 02:25:07.615439 [0.018961 Inits done]
719 02:25:07.615951 secure task start!
720 02:25:07.616443 high task start!
721 02:25:07.620043 low task start!
722 02:25:07.620544 run into bl31
723 02:25:07.626632 NOTICE: BL31: v1.3(release):4fc40b1
724 02:25:07.634493 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 02:25:07.635067 NOTICE: BL31: G12A normal boot!
726 02:25:07.659889 NOTICE: BL31: BL33 decompress pass
727 02:25:07.665551 ERROR: Error initializing runtime service opteed_fast
728 02:25:08.898433
729 02:25:08.899096
730 02:25:08.906786 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 02:25:08.907303
732 02:25:08.907771 Model: Libre Computer AML-A311D-CC Alta
733 02:25:09.115248 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 02:25:09.138581 DRAM: 2 GiB (effective 3.8 GiB)
735 02:25:09.281619 Core: 408 devices, 31 uclasses, devicetree: separate
736 02:25:09.287434 WDT: Not starting watchdog@f0d0
737 02:25:09.319708 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 02:25:09.332175 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 02:25:09.337135 ** Bad device specification mmc 0 **
740 02:25:09.347484 Card did not respond to voltage select! : -110
741 02:25:09.355106 ** Bad device specification mmc 0 **
742 02:25:09.355613 Couldn't find partition mmc 0
743 02:25:09.363475 Card did not respond to voltage select! : -110
744 02:25:09.368972 ** Bad device specification mmc 0 **
745 02:25:09.369474 Couldn't find partition mmc 0
746 02:25:09.374067 Error: could not access storage.
747 02:25:09.716602 Net: eth0: ethernet@ff3f0000
748 02:25:09.717251 starting USB...
749 02:25:09.968362 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 02:25:09.968925 Starting the controller
751 02:25:09.975379 USB XHCI 1.10
752 02:25:12.187799 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
753 02:25:12.188530 bl2_stage_init 0x81
754 02:25:12.193393 hw id: 0x0000 - pwm id 0x01
755 02:25:12.193901 bl2_stage_init 0xc1
756 02:25:12.194363 bl2_stage_init 0x02
757 02:25:12.194815
758 02:25:12.199061 L0:00000000
759 02:25:12.199553 L1:20000703
760 02:25:12.200038 L2:00008067
761 02:25:12.200493 L3:14000000
762 02:25:12.200935 B2:00402000
763 02:25:12.204490 B1:e0f83180
764 02:25:12.204981
765 02:25:12.205433 TE: 58150
766 02:25:12.205881
767 02:25:12.210109 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 02:25:12.210606
769 02:25:12.211058 Board ID = 1
770 02:25:12.215777 Set A53 clk to 24M
771 02:25:12.216349 Set A73 clk to 24M
772 02:25:12.216811 Set clk81 to 24M
773 02:25:12.221391 A53 clk: 1200 MHz
774 02:25:12.221884 A73 clk: 1200 MHz
775 02:25:12.222338 CLK81: 166.6M
776 02:25:12.222776 smccc: 00012aab
777 02:25:12.227045 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 02:25:12.232567 board id: 1
779 02:25:12.238322 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 02:25:12.249050 fw parse done
781 02:25:12.254989 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 02:25:12.297532 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 02:25:12.308362 PIEI prepare done
784 02:25:12.308850 fastboot data load
785 02:25:12.309302 fastboot data verify
786 02:25:12.314008 verify result: 266
787 02:25:12.319563 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 02:25:12.320090 LPDDR4 probe
789 02:25:12.320551 ddr clk to 1584MHz
790 02:25:12.327552 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 02:25:12.364825
792 02:25:12.365330 dmc_version 0001
793 02:25:12.371484 Check phy result
794 02:25:12.377363 INFO : End of CA training
795 02:25:12.377880 INFO : End of initialization
796 02:25:12.382973 INFO : Training has run successfully!
797 02:25:12.383468 Check phy result
798 02:25:12.388566 INFO : End of initialization
799 02:25:12.389053 INFO : End of read enable training
800 02:25:12.394153 INFO : End of fine write leveling
801 02:25:12.399753 INFO : End of Write leveling coarse delay
802 02:25:12.400271 INFO : Training has run successfully!
803 02:25:12.400724 Check phy result
804 02:25:12.405365 INFO : End of initialization
805 02:25:12.405854 INFO : End of read dq deskew training
806 02:25:12.410962 INFO : End of MPR read delay center optimization
807 02:25:12.416560 INFO : End of write delay center optimization
808 02:25:12.422133 INFO : End of read delay center optimization
809 02:25:12.422612 INFO : End of max read latency training
810 02:25:12.427813 INFO : Training has run successfully!
811 02:25:12.428365 1D training succeed
812 02:25:12.436986 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 02:25:12.484561 Check phy result
814 02:25:12.485068 INFO : End of initialization
815 02:25:12.506946 INFO : End of 2D read delay Voltage center optimization
816 02:25:12.527084 INFO : End of 2D read delay Voltage center optimization
817 02:25:12.578951 INFO : End of 2D write delay Voltage center optimization
818 02:25:12.628210 INFO : End of 2D write delay Voltage center optimization
819 02:25:12.633771 INFO : Training has run successfully!
820 02:25:12.634306
821 02:25:12.634760 channel==0
822 02:25:12.639355 RxClkDly_Margin_A0==88 ps 9
823 02:25:12.639879 TxDqDly_Margin_A0==98 ps 10
824 02:25:12.644995 RxClkDly_Margin_A1==88 ps 9
825 02:25:12.645473 TxDqDly_Margin_A1==88 ps 9
826 02:25:12.645910 TrainedVREFDQ_A0==74
827 02:25:12.650564 TrainedVREFDQ_A1==74
828 02:25:12.651031 VrefDac_Margin_A0==24
829 02:25:12.651459 DeviceVref_Margin_A0==40
830 02:25:12.656147 VrefDac_Margin_A1==24
831 02:25:12.656628 DeviceVref_Margin_A1==40
832 02:25:12.657056
833 02:25:12.657483
834 02:25:12.657905 channel==1
835 02:25:12.661721 RxClkDly_Margin_A0==98 ps 10
836 02:25:12.662183 TxDqDly_Margin_A0==98 ps 10
837 02:25:12.667379 RxClkDly_Margin_A1==88 ps 9
838 02:25:12.667839 TxDqDly_Margin_A1==108 ps 11
839 02:25:12.672971 TrainedVREFDQ_A0==77
840 02:25:12.673483 TrainedVREFDQ_A1==77
841 02:25:12.673915 VrefDac_Margin_A0==22
842 02:25:12.678561 DeviceVref_Margin_A0==37
843 02:25:12.679035 VrefDac_Margin_A1==24
844 02:25:12.684190 DeviceVref_Margin_A1==37
845 02:25:12.684655
846 02:25:12.685086 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 02:25:12.689741
848 02:25:12.717731 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
849 02:25:12.718238 2D training succeed
850 02:25:12.723336 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 02:25:12.728991 auto size-- 65535DDR cs0 size: 2048MB
852 02:25:12.729459 DDR cs1 size: 2048MB
853 02:25:12.734495 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 02:25:12.734955 cs0 DataBus test pass
855 02:25:12.740175 cs1 DataBus test pass
856 02:25:12.740639 cs0 AddrBus test pass
857 02:25:12.741067 cs1 AddrBus test pass
858 02:25:12.741488
859 02:25:12.745747 100bdlr_step_size ps== 420
860 02:25:12.746213 result report
861 02:25:12.751342 boot times 0Enable ddr reg access
862 02:25:12.756773 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 02:25:12.770246 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 02:25:13.342248 0.0;M3 CHK:0;cm4_sp_mode 0
865 02:25:13.342673 MVN_1=0x00000000
866 02:25:13.347674 MVN_2=0x00000000
867 02:25:13.353480 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 02:25:13.353986 OPS=0x10
869 02:25:13.354420 ring efuse init
870 02:25:13.354835 chipver efuse init
871 02:25:13.359047 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 02:25:13.364647 [0.018961 Inits done]
873 02:25:13.365095 secure task start!
874 02:25:13.365508 high task start!
875 02:25:13.369256 low task start!
876 02:25:13.369704 run into bl31
877 02:25:13.376064 NOTICE: BL31: v1.3(release):4fc40b1
878 02:25:13.383714 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 02:25:13.384215 NOTICE: BL31: G12A normal boot!
880 02:25:13.409069 NOTICE: BL31: BL33 decompress pass
881 02:25:13.414858 ERROR: Error initializing runtime service opteed_fast
882 02:25:14.647672
883 02:25:14.648334
884 02:25:14.656019 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 02:25:14.656501
886 02:25:14.656923 Model: Libre Computer AML-A311D-CC Alta
887 02:25:14.864459 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 02:25:14.887809 DRAM: 2 GiB (effective 3.8 GiB)
889 02:25:15.030861 Core: 408 devices, 31 uclasses, devicetree: separate
890 02:25:15.036669 WDT: Not starting watchdog@f0d0
891 02:25:15.068938 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 02:25:15.081400 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 02:25:15.086366 ** Bad device specification mmc 0 **
894 02:25:15.096702 Card did not respond to voltage select! : -110
895 02:25:15.104344 ** Bad device specification mmc 0 **
896 02:25:15.104801 Couldn't find partition mmc 0
897 02:25:15.112689 Card did not respond to voltage select! : -110
898 02:25:15.118205 ** Bad device specification mmc 0 **
899 02:25:15.118652 Couldn't find partition mmc 0
900 02:25:15.123292 Error: could not access storage.
901 02:25:15.464882 Net: eth0: ethernet@ff3f0000
902 02:25:15.465447 starting USB...
903 02:25:15.717725 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 02:25:15.718335 Starting the controller
905 02:25:15.724522 USB XHCI 1.10
906 02:25:17.588551 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 02:25:17.589229 bl2_stage_init 0x01
908 02:25:17.589703 bl2_stage_init 0x81
909 02:25:17.594047 hw id: 0x0000 - pwm id 0x01
910 02:25:17.594567 bl2_stage_init 0xc1
911 02:25:17.595028 bl2_stage_init 0x02
912 02:25:17.595472
913 02:25:17.599587 L0:00000000
914 02:25:17.600152 L1:20000703
915 02:25:17.600611 L2:00008067
916 02:25:17.601052 L3:14000000
917 02:25:17.605225 B2:00402000
918 02:25:17.605733 B1:e0f83180
919 02:25:17.606184
920 02:25:17.606631 TE: 58159
921 02:25:17.607075
922 02:25:17.610908 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 02:25:17.611429
924 02:25:17.611890 Board ID = 1
925 02:25:17.616586 Set A53 clk to 24M
926 02:25:17.617124 Set A73 clk to 24M
927 02:25:17.617577 Set clk81 to 24M
928 02:25:17.622089 A53 clk: 1200 MHz
929 02:25:17.622606 A73 clk: 1200 MHz
930 02:25:17.623062 CLK81: 166.6M
931 02:25:17.623507 smccc: 00012ab5
932 02:25:17.627580 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 02:25:17.633229 board id: 1
934 02:25:17.639117 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 02:25:17.649876 fw parse done
936 02:25:17.655771 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 02:25:17.698212 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 02:25:17.709123 PIEI prepare done
939 02:25:17.709623 fastboot data load
940 02:25:17.710058 fastboot data verify
941 02:25:17.714834 verify result: 266
942 02:25:17.720412 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 02:25:17.720913 LPDDR4 probe
944 02:25:17.721341 ddr clk to 1584MHz
945 02:25:17.728360 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 02:25:17.765687
947 02:25:17.766221 dmc_version 0001
948 02:25:17.772404 Check phy result
949 02:25:17.778214 INFO : End of CA training
950 02:25:17.778723 INFO : End of initialization
951 02:25:17.783817 INFO : Training has run successfully!
952 02:25:17.784356 Check phy result
953 02:25:17.789464 INFO : End of initialization
954 02:25:17.789977 INFO : End of read enable training
955 02:25:17.795145 INFO : End of fine write leveling
956 02:25:17.800646 INFO : End of Write leveling coarse delay
957 02:25:17.801167 INFO : Training has run successfully!
958 02:25:17.801626 Check phy result
959 02:25:17.806296 INFO : End of initialization
960 02:25:17.806807 INFO : End of read dq deskew training
961 02:25:17.811814 INFO : End of MPR read delay center optimization
962 02:25:17.817442 INFO : End of write delay center optimization
963 02:25:17.823012 INFO : End of read delay center optimization
964 02:25:17.823525 INFO : End of max read latency training
965 02:25:17.828651 INFO : Training has run successfully!
966 02:25:17.829172 1D training succeed
967 02:25:17.837838 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 02:25:17.885564 Check phy result
969 02:25:17.886129 INFO : End of initialization
970 02:25:17.907110 INFO : End of 2D read delay Voltage center optimization
971 02:25:17.927180 INFO : End of 2D read delay Voltage center optimization
972 02:25:17.979138 INFO : End of 2D write delay Voltage center optimization
973 02:25:18.028353 INFO : End of 2D write delay Voltage center optimization
974 02:25:18.033918 INFO : Training has run successfully!
975 02:25:18.034453
976 02:25:18.034916 channel==0
977 02:25:18.039472 RxClkDly_Margin_A0==88 ps 9
978 02:25:18.040019 TxDqDly_Margin_A0==98 ps 10
979 02:25:18.045124 RxClkDly_Margin_A1==88 ps 9
980 02:25:18.045631 TxDqDly_Margin_A1==98 ps 10
981 02:25:18.046090 TrainedVREFDQ_A0==74
982 02:25:18.050698 TrainedVREFDQ_A1==74
983 02:25:18.051220 VrefDac_Margin_A0==25
984 02:25:18.051667 DeviceVref_Margin_A0==40
985 02:25:18.056373 VrefDac_Margin_A1==25
986 02:25:18.056891 DeviceVref_Margin_A1==40
987 02:25:18.057341
988 02:25:18.057787
989 02:25:18.061942 channel==1
990 02:25:18.062451 RxClkDly_Margin_A0==98 ps 10
991 02:25:18.062901 TxDqDly_Margin_A0==88 ps 9
992 02:25:18.067596 RxClkDly_Margin_A1==98 ps 10
993 02:25:18.068140 TxDqDly_Margin_A1==88 ps 9
994 02:25:18.073184 TrainedVREFDQ_A0==77
995 02:25:18.073698 TrainedVREFDQ_A1==77
996 02:25:18.074151 VrefDac_Margin_A0==22
997 02:25:18.078674 DeviceVref_Margin_A0==37
998 02:25:18.079180 VrefDac_Margin_A1==22
999 02:25:18.084325 DeviceVref_Margin_A1==37
1000 02:25:18.084834
1001 02:25:18.085289 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 02:25:18.085733
1003 02:25:18.117775 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 0000001a 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1004 02:25:18.118358 2D training succeed
1005 02:25:18.123438 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 02:25:18.129050 auto size-- 65535DDR cs0 size: 2048MB
1007 02:25:18.129564 DDR cs1 size: 2048MB
1008 02:25:18.134615 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 02:25:18.135124 cs0 DataBus test pass
1010 02:25:18.140241 cs1 DataBus test pass
1011 02:25:18.140746 cs0 AddrBus test pass
1012 02:25:18.141202 cs1 AddrBus test pass
1013 02:25:18.141643
1014 02:25:18.145821 100bdlr_step_size ps== 420
1015 02:25:18.146333 result report
1016 02:25:18.151407 boot times 0Enable ddr reg access
1017 02:25:18.156752 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 02:25:18.170186 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 02:25:18.742208 0.0;M3 CHK:0;cm4_sp_mode 0
1020 02:25:18.742871 MVN_1=0x00000000
1021 02:25:18.747659 MVN_2=0x00000000
1022 02:25:18.753452 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 02:25:18.753969 OPS=0x10
1024 02:25:18.754429 ring efuse init
1025 02:25:18.754873 chipver efuse init
1026 02:25:18.759032 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 02:25:18.764625 [0.018960 Inits done]
1028 02:25:18.765125 secure task start!
1029 02:25:18.765576 high task start!
1030 02:25:18.769228 low task start!
1031 02:25:18.769730 run into bl31
1032 02:25:18.775882 NOTICE: BL31: v1.3(release):4fc40b1
1033 02:25:18.783674 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 02:25:18.784223 NOTICE: BL31: G12A normal boot!
1035 02:25:18.809065 NOTICE: BL31: BL33 decompress pass
1036 02:25:18.814759 ERROR: Error initializing runtime service opteed_fast
1037 02:25:20.047598
1038 02:25:20.048308
1039 02:25:20.056102 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 02:25:20.056653
1041 02:25:20.057135 Model: Libre Computer AML-A311D-CC Alta
1042 02:25:20.264450 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 02:25:20.287859 DRAM: 2 GiB (effective 3.8 GiB)
1044 02:25:20.430856 Core: 408 devices, 31 uclasses, devicetree: separate
1045 02:25:20.436706 WDT: Not starting watchdog@f0d0
1046 02:25:20.468953 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 02:25:20.481387 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 02:25:20.486366 ** Bad device specification mmc 0 **
1049 02:25:20.496704 Card did not respond to voltage select! : -110
1050 02:25:20.504375 ** Bad device specification mmc 0 **
1051 02:25:20.504912 Couldn't find partition mmc 0
1052 02:25:20.512698 Card did not respond to voltage select! : -110
1053 02:25:20.518236 ** Bad device specification mmc 0 **
1054 02:25:20.518774 Couldn't find partition mmc 0
1055 02:25:20.523274 Error: could not access storage.
1056 02:25:20.866746 Net: eth0: ethernet@ff3f0000
1057 02:25:20.867376 starting USB...
1058 02:25:21.118625 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 02:25:21.119251 Starting the controller
1060 02:25:21.125548 USB XHCI 1.10
1061 02:25:22.681719 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 02:25:22.690074 scanning usb for storage devices... 0 Storage Device(s) found
1064 02:25:22.741867 Hit any key to stop autoboot: 1
1065 02:25:22.742734 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1066 02:25:22.743510 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1067 02:25:22.744067 Setting prompt string to ['=>']
1068 02:25:22.744596 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1069 02:25:22.757492 0
1070 02:25:22.758444 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 02:25:22.758983 Sending with 10 millisecond of delay
1073 02:25:23.893856 => setenv autoload no
1074 02:25:23.904704 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1075 02:25:23.910126 setenv autoload no
1076 02:25:23.910919 Sending with 10 millisecond of delay
1078 02:25:25.709697 => setenv initrd_high 0xffffffff
1079 02:25:25.720549 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1080 02:25:25.721494 setenv initrd_high 0xffffffff
1081 02:25:25.722265 Sending with 10 millisecond of delay
1083 02:25:27.339089 => setenv fdt_high 0xffffffff
1084 02:25:27.349911 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1085 02:25:27.350824 setenv fdt_high 0xffffffff
1086 02:25:27.351588 Sending with 10 millisecond of delay
1088 02:25:27.643625 => dhcp
1089 02:25:27.654484 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1090 02:25:27.655455 dhcp
1091 02:25:27.655934 Speed: 1000, full duplex
1092 02:25:27.656438 BOOTP broadcast 1
1093 02:25:27.866711 DHCP client bound to address 192.168.6.27 (212 ms)
1094 02:25:27.867646 Sending with 10 millisecond of delay
1096 02:25:29.544699 => setenv serverip 192.168.6.2
1097 02:25:29.555528 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1098 02:25:29.556487 setenv serverip 192.168.6.2
1099 02:25:29.557236 Sending with 10 millisecond of delay
1101 02:25:33.281312 => tftpboot 0x01080000 949953/tftp-deploy-ac4a9eou/kernel/uImage
1102 02:25:33.292198 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1103 02:25:33.293174 tftpboot 0x01080000 949953/tftp-deploy-ac4a9eou/kernel/uImage
1104 02:25:33.293639 Speed: 1000, full duplex
1105 02:25:33.294076 Using ethernet@ff3f0000 device
1106 02:25:33.295156 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1107 02:25:33.300606 Filename '949953/tftp-deploy-ac4a9eou/kernel/uImage'.
1108 02:25:33.304439 Load address: 0x1080000
1109 02:25:36.191661 Loading: *################################################## 43.6 MiB
1110 02:25:36.192397 15.1 MiB/s
1111 02:25:36.192872 done
1112 02:25:36.214652 Bytes transferred = 45713984 (2b98a40 hex)
1113 02:25:36.215742 Sending with 10 millisecond of delay
1115 02:25:40.905691 => tftpboot 0x08000000 949953/tftp-deploy-ac4a9eou/ramdisk/ramdisk.cpio.gz.uboot
1116 02:25:40.916577 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1117 02:25:40.917542 tftpboot 0x08000000 949953/tftp-deploy-ac4a9eou/ramdisk/ramdisk.cpio.gz.uboot
1118 02:25:40.918044 Speed: 1000, full duplex
1119 02:25:40.918512 Using ethernet@ff3f0000 device
1120 02:25:40.919304 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1121 02:25:40.927846 Filename '949953/tftp-deploy-ac4a9eou/ramdisk/ramdisk.cpio.gz.uboot'.
1122 02:25:40.928317 Load address: 0x8000000
1123 02:25:50.324498 Loading: *#######T ########################################## UDP wrong checksum 0000000f 00005a40
1124 02:25:55.325619 T UDP wrong checksum 0000000f 00005a40
1125 02:26:05.327542 T T UDP wrong checksum 0000000f 00005a40
1126 02:26:09.182434 UDP wrong checksum 000000ff 000062f1
1127 02:26:09.231436 UDP wrong checksum 000000ff 0000f3e3
1128 02:26:12.319310 T UDP wrong checksum 000000ff 00009957
1129 02:26:12.370266 UDP wrong checksum 000000ff 0000244a
1130 02:26:25.332810 T T T UDP wrong checksum 0000000f 00005a40
1131 02:26:40.336985 T T
1132 02:26:40.337619 Retry count exceeded; starting again
1134 02:26:40.339194 end: 2.4.3 bootloader-commands (duration 00:01:18) [common]
1137 02:26:40.341296 end: 2.4 uboot-commands (duration 00:01:55) [common]
1139 02:26:40.342771 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1141 02:26:40.343908 end: 2 uboot-action (duration 00:01:55) [common]
1143 02:26:40.345636 Cleaning after the job
1144 02:26:40.346258 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949953/tftp-deploy-ac4a9eou/ramdisk
1145 02:26:40.347719 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949953/tftp-deploy-ac4a9eou/kernel
1146 02:26:40.396078 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949953/tftp-deploy-ac4a9eou/dtb
1147 02:26:40.396879 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949953/tftp-deploy-ac4a9eou/modules
1148 02:26:40.420012 start: 4.1 power-off (timeout 00:00:30) [common]
1149 02:26:40.420690 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1150 02:26:40.458611 >> OK - accepted request
1151 02:26:40.460779 Returned 0 in 0 seconds
1152 02:26:40.561820 end: 4.1 power-off (duration 00:00:00) [common]
1154 02:26:40.562754 start: 4.2 read-feedback (timeout 00:10:00) [common]
1155 02:26:40.563418 Listened to connection for namespace 'common' for up to 1s
1156 02:26:41.564284 Finalising connection for namespace 'common'
1157 02:26:41.565049 Disconnecting from shell: Finalise
1158 02:26:41.565577 =>
1159 02:26:41.666675 end: 4.2 read-feedback (duration 00:00:01) [common]
1160 02:26:41.667405 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949953
1161 02:26:42.307773 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949953
1162 02:26:42.308422 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.