Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:56:31.083031 lava-dispatcher, installed at version: 2024.01
2 21:56:31.083812 start: 0 validate
3 21:56:31.084315 Start time: 2024-11-07 21:56:31.084285+00:00 (UTC)
4 21:56:31.084864 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:56:31.085390 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 21:56:31.129317 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:56:31.129958 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-63-g2e9baed573ee%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 21:56:31.162204 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:56:31.162854 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-63-g2e9baed573ee%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:56:32.212373 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:56:32.212942 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-63-g2e9baed573ee%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 21:56:32.257041 validate duration: 1.17
14 21:56:32.258006 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:56:32.258355 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:56:32.258683 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:56:32.259286 Not decompressing ramdisk as can be used compressed.
18 21:56:32.259758 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 21:56:32.260040 saving as /var/lib/lava/dispatcher/tmp/955836/tftp-deploy-93t_19qq/ramdisk/rootfs.cpio.gz
20 21:56:32.260313 total size: 8181887 (7 MB)
21 21:56:32.309178 progress 0 % (0 MB)
22 21:56:32.321381 progress 5 % (0 MB)
23 21:56:32.329572 progress 10 % (0 MB)
24 21:56:32.338417 progress 15 % (1 MB)
25 21:56:32.348254 progress 20 % (1 MB)
26 21:56:32.356722 progress 25 % (1 MB)
27 21:56:32.363840 progress 30 % (2 MB)
28 21:56:32.374352 progress 35 % (2 MB)
29 21:56:32.382258 progress 40 % (3 MB)
30 21:56:32.392880 progress 45 % (3 MB)
31 21:56:32.400441 progress 50 % (3 MB)
32 21:56:32.407972 progress 55 % (4 MB)
33 21:56:32.418440 progress 60 % (4 MB)
34 21:56:32.426021 progress 65 % (5 MB)
35 21:56:32.433085 progress 70 % (5 MB)
36 21:56:32.443693 progress 75 % (5 MB)
37 21:56:32.450591 progress 80 % (6 MB)
38 21:56:32.457871 progress 85 % (6 MB)
39 21:56:32.467413 progress 90 % (7 MB)
40 21:56:32.474902 progress 95 % (7 MB)
41 21:56:32.481011 progress 100 % (7 MB)
42 21:56:32.481868 7 MB downloaded in 0.22 s (35.22 MB/s)
43 21:56:32.482646 end: 1.1.1 http-download (duration 00:00:00) [common]
45 21:56:32.483820 end: 1.1 download-retry (duration 00:00:00) [common]
46 21:56:32.486563 start: 1.2 download-retry (timeout 00:10:00) [common]
47 21:56:32.487146 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 21:56:32.487801 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-63-g2e9baed573ee/arm64/defconfig/gcc-12/kernel/Image
49 21:56:32.488190 saving as /var/lib/lava/dispatcher/tmp/955836/tftp-deploy-93t_19qq/kernel/Image
50 21:56:32.488482 total size: 45713920 (43 MB)
51 21:56:32.488808 No compression specified
52 21:56:32.535568 progress 0 % (0 MB)
53 21:56:32.571425 progress 5 % (2 MB)
54 21:56:32.613683 progress 10 % (4 MB)
55 21:56:32.653420 progress 15 % (6 MB)
56 21:56:32.685286 progress 20 % (8 MB)
57 21:56:32.716107 progress 25 % (10 MB)
58 21:56:32.746848 progress 30 % (13 MB)
59 21:56:32.778044 progress 35 % (15 MB)
60 21:56:32.808072 progress 40 % (17 MB)
61 21:56:32.838579 progress 45 % (19 MB)
62 21:56:32.869874 progress 50 % (21 MB)
63 21:56:32.900305 progress 55 % (24 MB)
64 21:56:32.931255 progress 60 % (26 MB)
65 21:56:32.961345 progress 65 % (28 MB)
66 21:56:32.992071 progress 70 % (30 MB)
67 21:56:33.022928 progress 75 % (32 MB)
68 21:56:33.053541 progress 80 % (34 MB)
69 21:56:33.083895 progress 85 % (37 MB)
70 21:56:33.114222 progress 90 % (39 MB)
71 21:56:33.144722 progress 95 % (41 MB)
72 21:56:33.174438 progress 100 % (43 MB)
73 21:56:33.174959 43 MB downloaded in 0.69 s (63.51 MB/s)
74 21:56:33.175439 end: 1.2.1 http-download (duration 00:00:01) [common]
76 21:56:33.176292 end: 1.2 download-retry (duration 00:00:01) [common]
77 21:56:33.176572 start: 1.3 download-retry (timeout 00:09:59) [common]
78 21:56:33.176834 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 21:56:33.177297 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-63-g2e9baed573ee/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 21:56:33.177577 saving as /var/lib/lava/dispatcher/tmp/955836/tftp-deploy-93t_19qq/dtb/meson-g12b-a311d-libretech-cc.dtb
81 21:56:33.177786 total size: 54703 (0 MB)
82 21:56:33.177995 No compression specified
83 21:56:33.217307 progress 59 % (0 MB)
84 21:56:33.218209 progress 100 % (0 MB)
85 21:56:33.218811 0 MB downloaded in 0.04 s (1.27 MB/s)
86 21:56:33.219281 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:56:33.220122 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:56:33.220387 start: 1.4 download-retry (timeout 00:09:59) [common]
90 21:56:33.220649 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 21:56:33.221174 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-63-g2e9baed573ee/arm64/defconfig/gcc-12/modules.tar.xz
92 21:56:33.221419 saving as /var/lib/lava/dispatcher/tmp/955836/tftp-deploy-93t_19qq/modules/modules.tar
93 21:56:33.221624 total size: 11603932 (11 MB)
94 21:56:33.221833 Using unxz to decompress xz
95 21:56:33.255932 progress 0 % (0 MB)
96 21:56:33.322211 progress 5 % (0 MB)
97 21:56:33.397770 progress 10 % (1 MB)
98 21:56:33.495022 progress 15 % (1 MB)
99 21:56:33.588930 progress 20 % (2 MB)
100 21:56:33.668695 progress 25 % (2 MB)
101 21:56:33.745389 progress 30 % (3 MB)
102 21:56:33.822146 progress 35 % (3 MB)
103 21:56:33.900525 progress 40 % (4 MB)
104 21:56:33.977637 progress 45 % (5 MB)
105 21:56:34.062599 progress 50 % (5 MB)
106 21:56:34.140571 progress 55 % (6 MB)
107 21:56:34.226526 progress 60 % (6 MB)
108 21:56:34.307941 progress 65 % (7 MB)
109 21:56:34.385781 progress 70 % (7 MB)
110 21:56:34.469548 progress 75 % (8 MB)
111 21:56:34.553992 progress 80 % (8 MB)
112 21:56:34.634944 progress 85 % (9 MB)
113 21:56:34.714016 progress 90 % (9 MB)
114 21:56:34.792144 progress 95 % (10 MB)
115 21:56:34.869803 progress 100 % (11 MB)
116 21:56:34.880397 11 MB downloaded in 1.66 s (6.67 MB/s)
117 21:56:34.880987 end: 1.4.1 http-download (duration 00:00:02) [common]
119 21:56:34.881810 end: 1.4 download-retry (duration 00:00:02) [common]
120 21:56:34.882081 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 21:56:34.882345 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 21:56:34.882592 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:56:34.882846 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 21:56:34.883459 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4
125 21:56:34.883919 makedir: /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin
126 21:56:34.884577 makedir: /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/tests
127 21:56:34.885319 makedir: /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/results
128 21:56:34.885991 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-add-keys
129 21:56:34.887048 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-add-sources
130 21:56:34.888104 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-background-process-start
131 21:56:34.889201 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-background-process-stop
132 21:56:34.890283 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-common-functions
133 21:56:34.891281 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-echo-ipv4
134 21:56:34.892332 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-install-packages
135 21:56:34.893329 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-installed-packages
136 21:56:34.894297 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-os-build
137 21:56:34.895277 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-probe-channel
138 21:56:34.896298 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-probe-ip
139 21:56:34.897296 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-target-ip
140 21:56:34.898314 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-target-mac
141 21:56:34.899280 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-target-storage
142 21:56:34.900297 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-test-case
143 21:56:34.901284 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-test-event
144 21:56:34.902248 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-test-feedback
145 21:56:34.903478 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-test-raise
146 21:56:34.904543 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-test-reference
147 21:56:34.905528 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-test-runner
148 21:56:34.906502 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-test-set
149 21:56:34.907527 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-test-shell
150 21:56:34.908648 Updating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-install-packages (oe)
151 21:56:34.909881 Updating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/bin/lava-installed-packages (oe)
152 21:56:34.910970 Creating /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/environment
153 21:56:34.911847 LAVA metadata
154 21:56:34.912420 - LAVA_JOB_ID=955836
155 21:56:34.912897 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:56:34.913632 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 21:56:34.915558 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:56:34.916229 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 21:56:34.916688 skipped lava-vland-overlay
160 21:56:34.917229 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:56:34.917786 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 21:56:34.918257 skipped lava-multinode-overlay
163 21:56:34.918787 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:56:34.919336 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 21:56:34.919856 Loading test definitions
166 21:56:34.920490 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 21:56:34.920975 Using /lava-955836 at stage 0
168 21:56:34.923466 uuid=955836_1.5.2.4.1 testdef=None
169 21:56:34.924124 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:56:34.924701 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 21:56:34.928442 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:56:34.930151 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 21:56:34.935185 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:56:34.937005 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 21:56:34.941526 runner path: /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/0/tests/0_dmesg test_uuid 955836_1.5.2.4.1
178 21:56:34.942543 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:56:34.944058 Creating lava-test-runner.conf files
181 21:56:34.944473 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/955836/lava-overlay-q6dsd2v4/lava-955836/0 for stage 0
182 21:56:34.945113 - 0_dmesg
183 21:56:34.945770 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:56:34.946303 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 21:56:34.971200 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:56:34.971599 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 21:56:34.971866 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:56:34.972167 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:56:34.972433 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 21:56:35.986138 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 21:56:35.986718 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 21:56:35.987050 extracting modules file /var/lib/lava/dispatcher/tmp/955836/tftp-deploy-93t_19qq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955836/extract-overlay-ramdisk-t5he4obl/ramdisk
193 21:56:37.451972 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 21:56:37.452632 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 21:56:37.453037 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955836/compress-overlay-0sq046ac/overlay-1.5.2.5.tar.gz to ramdisk
196 21:56:37.453306 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955836/compress-overlay-0sq046ac/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/955836/extract-overlay-ramdisk-t5he4obl/ramdisk
197 21:56:37.493528 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:56:37.494123 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 21:56:37.494479 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 21:56:37.494763 Converting downloaded kernel to a uImage
201 21:56:37.495139 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/955836/tftp-deploy-93t_19qq/kernel/Image /var/lib/lava/dispatcher/tmp/955836/tftp-deploy-93t_19qq/kernel/uImage
202 21:56:37.968915 output: Image Name:
203 21:56:37.969341 output: Created: Thu Nov 7 21:56:37 2024
204 21:56:37.969552 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:56:37.969760 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 21:56:37.969964 output: Load Address: 01080000
207 21:56:37.970163 output: Entry Point: 01080000
208 21:56:37.970362 output:
209 21:56:37.970693 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 21:56:37.970962 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 21:56:37.971233 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 21:56:37.971488 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:56:37.971745 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 21:56:37.972036 Building ramdisk /var/lib/lava/dispatcher/tmp/955836/extract-overlay-ramdisk-t5he4obl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/955836/extract-overlay-ramdisk-t5he4obl/ramdisk
215 21:56:40.392791 >> 181557 blocks
216 21:56:48.896318 Adding RAMdisk u-boot header.
217 21:56:48.896781 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/955836/extract-overlay-ramdisk-t5he4obl/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/955836/extract-overlay-ramdisk-t5he4obl/ramdisk.cpio.gz.uboot
218 21:56:49.172412 output: Image Name:
219 21:56:49.173108 output: Created: Thu Nov 7 21:56:48 2024
220 21:56:49.173564 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:56:49.174054 output: Data Size: 26054533 Bytes = 25443.88 KiB = 24.85 MiB
222 21:56:49.174514 output: Load Address: 00000000
223 21:56:49.174955 output: Entry Point: 00000000
224 21:56:49.175387 output:
225 21:56:49.176464 rename /var/lib/lava/dispatcher/tmp/955836/extract-overlay-ramdisk-t5he4obl/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/955836/tftp-deploy-93t_19qq/ramdisk/ramdisk.cpio.gz.uboot
226 21:56:49.177249 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 21:56:49.177846 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 21:56:49.178421 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 21:56:49.178920 No LXC device requested
230 21:56:49.179506 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:56:49.180149 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 21:56:49.180704 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:56:49.181225 Checking files for TFTP limit of 4294967296 bytes.
234 21:56:49.184244 end: 1 tftp-deploy (duration 00:00:17) [common]
235 21:56:49.184906 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:56:49.185535 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:56:49.186078 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:56:49.186633 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:56:49.187221 Using kernel file from prepare-kernel: 955836/tftp-deploy-93t_19qq/kernel/uImage
240 21:56:49.187884 substitutions:
241 21:56:49.188370 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:56:49.188818 - {DTB_ADDR}: 0x01070000
243 21:56:49.189254 - {DTB}: 955836/tftp-deploy-93t_19qq/dtb/meson-g12b-a311d-libretech-cc.dtb
244 21:56:49.189721 - {INITRD}: 955836/tftp-deploy-93t_19qq/ramdisk/ramdisk.cpio.gz.uboot
245 21:56:49.190254 - {KERNEL_ADDR}: 0x01080000
246 21:56:49.190741 - {KERNEL}: 955836/tftp-deploy-93t_19qq/kernel/uImage
247 21:56:49.191190 - {LAVA_MAC}: None
248 21:56:49.191672 - {PRESEED_CONFIG}: None
249 21:56:49.192161 - {PRESEED_LOCAL}: None
250 21:56:49.192592 - {RAMDISK_ADDR}: 0x08000000
251 21:56:49.193017 - {RAMDISK}: 955836/tftp-deploy-93t_19qq/ramdisk/ramdisk.cpio.gz.uboot
252 21:56:49.193448 - {ROOT_PART}: None
253 21:56:49.193873 - {ROOT}: None
254 21:56:49.194330 - {SERVER_IP}: 192.168.6.2
255 21:56:49.194779 - {TEE_ADDR}: 0x83000000
256 21:56:49.195206 - {TEE}: None
257 21:56:49.195633 Parsed boot commands:
258 21:56:49.196077 - setenv autoload no
259 21:56:49.196508 - setenv initrd_high 0xffffffff
260 21:56:49.196937 - setenv fdt_high 0xffffffff
261 21:56:49.197364 - dhcp
262 21:56:49.197791 - setenv serverip 192.168.6.2
263 21:56:49.198215 - tftpboot 0x01080000 955836/tftp-deploy-93t_19qq/kernel/uImage
264 21:56:49.198659 - tftpboot 0x08000000 955836/tftp-deploy-93t_19qq/ramdisk/ramdisk.cpio.gz.uboot
265 21:56:49.199190 - tftpboot 0x01070000 955836/tftp-deploy-93t_19qq/dtb/meson-g12b-a311d-libretech-cc.dtb
266 21:56:49.199652 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:56:49.200129 - bootm 0x01080000 0x08000000 0x01070000
268 21:56:49.200715 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:56:49.202361 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:56:49.202857 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 21:56:49.218337 Setting prompt string to ['lava-test: # ']
273 21:56:49.220022 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:56:49.220695 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:56:49.221334 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:56:49.221962 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:56:49.223287 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 21:56:49.260838 >> OK - accepted request
279 21:56:49.263089 Returned 0 in 0 seconds
280 21:56:49.364347 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:56:49.366126 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:56:49.366743 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:56:49.367294 Setting prompt string to ['Hit any key to stop autoboot']
285 21:56:49.367783 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:56:49.369567 Trying 192.168.56.21...
287 21:56:49.370101 Connected to conserv1.
288 21:56:49.370564 Escape character is '^]'.
289 21:56:49.371020
290 21:56:49.371488 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 21:56:49.371951
292 21:57:00.979315 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 21:57:00.980285 bl2_stage_init 0x01
294 21:57:00.981070 bl2_stage_init 0x81
295 21:57:00.984716 hw id: 0x0000 - pwm id 0x01
296 21:57:00.985535 bl2_stage_init 0xc1
297 21:57:00.986153 bl2_stage_init 0x02
298 21:57:00.986761
299 21:57:00.990308 L0:00000000
300 21:57:00.990850 L1:20000703
301 21:57:00.991305 L2:00008067
302 21:57:00.991744 L3:14000000
303 21:57:00.995930 B2:00402000
304 21:57:00.996503 B1:e0f83180
305 21:57:00.996955
306 21:57:00.997398 TE: 58124
307 21:57:00.997839
308 21:57:01.001587 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 21:57:01.002396
310 21:57:01.003016 Board ID = 1
311 21:57:01.007293 Set A53 clk to 24M
312 21:57:01.008091 Set A73 clk to 24M
313 21:57:01.008712 Set clk81 to 24M
314 21:57:01.012620 A53 clk: 1200 MHz
315 21:57:01.013130 A73 clk: 1200 MHz
316 21:57:01.013575 CLK81: 166.6M
317 21:57:01.014012 smccc: 00012a92
318 21:57:01.018320 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 21:57:01.023884 board id: 1
320 21:57:01.029787 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 21:57:01.040399 fw parse done
322 21:57:01.046382 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 21:57:01.089007 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 21:57:01.099957 PIEI prepare done
325 21:57:01.100865 fastboot data load
326 21:57:01.101532 fastboot data verify
327 21:57:01.105660 verify result: 266
328 21:57:01.111234 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 21:57:01.112127 LPDDR4 probe
330 21:57:01.112803 ddr clk to 1584MHz
331 21:57:01.119208 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 21:57:01.156492
333 21:57:01.157180 dmc_version 0001
334 21:57:01.163160 Check phy result
335 21:57:01.169017 INFO : End of CA training
336 21:57:01.169622 INFO : End of initialization
337 21:57:01.174585 INFO : Training has run successfully!
338 21:57:01.175195 Check phy result
339 21:57:01.180267 INFO : End of initialization
340 21:57:01.181154 INFO : End of read enable training
341 21:57:01.183610 INFO : End of fine write leveling
342 21:57:01.188986 INFO : End of Write leveling coarse delay
343 21:57:01.194779 INFO : Training has run successfully!
344 21:57:01.195570 Check phy result
345 21:57:01.196283 INFO : End of initialization
346 21:57:01.200316 INFO : End of read dq deskew training
347 21:57:01.203666 INFO : End of MPR read delay center optimization
348 21:57:01.209140 INFO : End of write delay center optimization
349 21:57:01.214705 INFO : End of read delay center optimization
350 21:57:01.215306 INFO : End of max read latency training
351 21:57:01.220478 INFO : Training has run successfully!
352 21:57:01.221275 1D training succeed
353 21:57:01.228602 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 21:57:01.276231 Check phy result
355 21:57:01.277145 INFO : End of initialization
356 21:57:01.298659 INFO : End of 2D read delay Voltage center optimization
357 21:57:01.318840 INFO : End of 2D read delay Voltage center optimization
358 21:57:01.370733 INFO : End of 2D write delay Voltage center optimization
359 21:57:01.419918 INFO : End of 2D write delay Voltage center optimization
360 21:57:01.425417 INFO : Training has run successfully!
361 21:57:01.425941
362 21:57:01.426388 channel==0
363 21:57:01.431022 RxClkDly_Margin_A0==88 ps 9
364 21:57:01.431665 TxDqDly_Margin_A0==98 ps 10
365 21:57:01.436703 RxClkDly_Margin_A1==88 ps 9
366 21:57:01.437234 TxDqDly_Margin_A1==98 ps 10
367 21:57:01.437679 TrainedVREFDQ_A0==74
368 21:57:01.442267 TrainedVREFDQ_A1==74
369 21:57:01.442836 VrefDac_Margin_A0==25
370 21:57:01.443281 DeviceVref_Margin_A0==40
371 21:57:01.447721 VrefDac_Margin_A1==24
372 21:57:01.448261 DeviceVref_Margin_A1==40
373 21:57:01.448702
374 21:57:01.449140
375 21:57:01.453410 channel==1
376 21:57:01.453919 RxClkDly_Margin_A0==98 ps 10
377 21:57:01.454358 TxDqDly_Margin_A0==98 ps 10
378 21:57:01.461622 RxClkDly_Margin_A1==98 ps 10
379 21:57:01.462212 TxDqDly_Margin_A1==88 ps 9
380 21:57:01.464802 TrainedVREFDQ_A0==77
381 21:57:01.465375 TrainedVREFDQ_A1==77
382 21:57:01.465853 VrefDac_Margin_A0==22
383 21:57:01.470291 DeviceVref_Margin_A0==37
384 21:57:01.470871 VrefDac_Margin_A1==22
385 21:57:01.479667 DeviceVref_Margin_A1==37
386 21:57:01.480258
387 21:57:01.480674 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 21:57:01.481369
389 21:57:01.509481 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
390 21:57:01.510157 2D training succeed
391 21:57:01.514908 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 21:57:01.520700 auto size-- 65535DDR cs0 size: 2048MB
393 21:57:01.521247 DDR cs1 size: 2048MB
394 21:57:01.525988 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 21:57:01.526496 cs0 DataBus test pass
396 21:57:01.531809 cs1 DataBus test pass
397 21:57:01.532426 cs0 AddrBus test pass
398 21:57:01.532837 cs1 AddrBus test pass
399 21:57:01.533234
400 21:57:01.537182 100bdlr_step_size ps== 420
401 21:57:01.537697 result report
402 21:57:01.546614 boot times 0Enable ddr reg access
403 21:57:01.551357 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 21:57:01.564797 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 21:57:02.133714 0.0;M3 CHK:0;cm4_sp_mode 0
406 21:57:02.134132 MVN_1=0x00000000
407 21:57:02.139195 MVN_2=0x00000000
408 21:57:02.144924 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 21:57:02.145425 OPS=0x10
410 21:57:02.145833 ring efuse init
411 21:57:02.146231 chipver efuse init
412 21:57:02.153216 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 21:57:02.153828 [0.018960 Inits done]
414 21:57:02.160753 secure task start!
415 21:57:02.161260 high task start!
416 21:57:02.161693 low task start!
417 21:57:02.162095 run into bl31
418 21:57:02.167392 NOTICE: BL31: v1.3(release):4fc40b1
419 21:57:02.175205 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 21:57:02.175670 NOTICE: BL31: G12A normal boot!
421 21:57:02.200687 NOTICE: BL31: BL33 decompress pass
422 21:57:02.206237 ERROR: Error initializing runtime service opteed_fast
423 21:57:03.439198
424 21:57:03.439802
425 21:57:03.447595 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 21:57:03.448088
427 21:57:03.448496 Model: Libre Computer AML-A311D-CC Alta
428 21:57:03.656165 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 21:57:03.679385 DRAM: 2 GiB (effective 3.8 GiB)
430 21:57:03.822356 Core: 408 devices, 31 uclasses, devicetree: separate
431 21:57:03.828216 WDT: Not starting watchdog@f0d0
432 21:57:03.860518 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 21:57:03.872899 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 21:57:03.877872 ** Bad device specification mmc 0 **
435 21:57:03.888221 Card did not respond to voltage select! : -110
436 21:57:03.895888 ** Bad device specification mmc 0 **
437 21:57:03.896263 Couldn't find partition mmc 0
438 21:57:03.904206 Card did not respond to voltage select! : -110
439 21:57:03.909805 ** Bad device specification mmc 0 **
440 21:57:03.910119 Couldn't find partition mmc 0
441 21:57:03.914875 Error: could not access storage.
442 21:57:05.179701 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 21:57:05.180463 bl2_stage_init 0x01
444 21:57:05.180955 bl2_stage_init 0x81
445 21:57:05.185173 hw id: 0x0000 - pwm id 0x01
446 21:57:05.185752 bl2_stage_init 0xc1
447 21:57:05.186200 bl2_stage_init 0x02
448 21:57:05.186636
449 21:57:05.190624 L0:00000000
450 21:57:05.191157 L1:20000703
451 21:57:05.191606 L2:00008067
452 21:57:05.192157 L3:14000000
453 21:57:05.196230 B2:00402000
454 21:57:05.196753 B1:e0f83180
455 21:57:05.197193
456 21:57:05.197631 TE: 58124
457 21:57:05.198068
458 21:57:05.201833 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 21:57:05.202343
460 21:57:05.202788 Board ID = 1
461 21:57:05.207440 Set A53 clk to 24M
462 21:57:05.207808 Set A73 clk to 24M
463 21:57:05.208081 Set clk81 to 24M
464 21:57:05.213093 A53 clk: 1200 MHz
465 21:57:05.213452 A73 clk: 1200 MHz
466 21:57:05.213660 CLK81: 166.6M
467 21:57:05.213880 smccc: 00012a91
468 21:57:05.218667 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 21:57:05.224231 board id: 1
470 21:57:05.230120 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 21:57:05.240823 fw parse done
472 21:57:05.246817 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 21:57:05.289925 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 21:57:05.300428 PIEI prepare done
475 21:57:05.301088 fastboot data load
476 21:57:05.301547 fastboot data verify
477 21:57:05.306049 verify result: 266
478 21:57:05.311473 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 21:57:05.311831 LPDDR4 probe
480 21:57:05.312112 ddr clk to 1584MHz
481 21:57:05.319446 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 21:57:05.356877
483 21:57:05.357555 dmc_version 0001
484 21:57:05.363675 Check phy result
485 21:57:05.369301 INFO : End of CA training
486 21:57:05.369686 INFO : End of initialization
487 21:57:05.374882 INFO : Training has run successfully!
488 21:57:05.375261 Check phy result
489 21:57:05.380495 INFO : End of initialization
490 21:57:05.380906 INFO : End of read enable training
491 21:57:05.386072 INFO : End of fine write leveling
492 21:57:05.391770 INFO : End of Write leveling coarse delay
493 21:57:05.392397 INFO : Training has run successfully!
494 21:57:05.392854 Check phy result
495 21:57:05.397404 INFO : End of initialization
496 21:57:05.397959 INFO : End of read dq deskew training
497 21:57:05.402975 INFO : End of MPR read delay center optimization
498 21:57:05.408640 INFO : End of write delay center optimization
499 21:57:05.414254 INFO : End of read delay center optimization
500 21:57:05.414854 INFO : End of max read latency training
501 21:57:05.419717 INFO : Training has run successfully!
502 21:57:05.420141 1D training succeed
503 21:57:05.428920 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 21:57:05.476532 Check phy result
505 21:57:05.476971 INFO : End of initialization
506 21:57:05.499229 INFO : End of 2D read delay Voltage center optimization
507 21:57:05.521672 INFO : End of 2D read delay Voltage center optimization
508 21:57:05.571546 INFO : End of 2D write delay Voltage center optimization
509 21:57:05.620836 INFO : End of 2D write delay Voltage center optimization
510 21:57:05.626355 INFO : Training has run successfully!
511 21:57:05.626921
512 21:57:05.627375 channel==0
513 21:57:05.631867 RxClkDly_Margin_A0==88 ps 9
514 21:57:05.632460 TxDqDly_Margin_A0==98 ps 10
515 21:57:05.637499 RxClkDly_Margin_A1==88 ps 9
516 21:57:05.638159 TxDqDly_Margin_A1==88 ps 9
517 21:57:05.638697 TrainedVREFDQ_A0==74
518 21:57:05.643097 TrainedVREFDQ_A1==74
519 21:57:05.643666 VrefDac_Margin_A0==24
520 21:57:05.644166 DeviceVref_Margin_A0==40
521 21:57:05.648696 VrefDac_Margin_A1==24
522 21:57:05.649220 DeviceVref_Margin_A1==40
523 21:57:05.649665
524 21:57:05.650110
525 21:57:05.650543 channel==1
526 21:57:05.654379 RxClkDly_Margin_A0==98 ps 10
527 21:57:05.655043 TxDqDly_Margin_A0==98 ps 10
528 21:57:05.660032 RxClkDly_Margin_A1==88 ps 9
529 21:57:05.660673 TxDqDly_Margin_A1==88 ps 9
530 21:57:05.665523 TrainedVREFDQ_A0==77
531 21:57:05.666218 TrainedVREFDQ_A1==77
532 21:57:05.666762 VrefDac_Margin_A0==22
533 21:57:05.679134 DeviceVref_Margin_A0==37
534 21:57:05.679583 VrefDac_Margin_A1==24
535 21:57:05.679829 DeviceVref_Margin_A1==37
536 21:57:05.680090
537 21:57:05.680307 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 21:57:05.680517
539 21:57:05.710312 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 21:57:05.710783 2D training succeed
541 21:57:05.715953 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 21:57:05.721393 auto size-- 65535DDR cs0 size: 2048MB
543 21:57:05.721736 DDR cs1 size: 2048MB
544 21:57:05.727039 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 21:57:05.727350 cs0 DataBus test pass
546 21:57:05.732533 cs1 DataBus test pass
547 21:57:05.732811 cs0 AddrBus test pass
548 21:57:05.733125 cs1 AddrBus test pass
549 21:57:05.733354
550 21:57:05.738157 100bdlr_step_size ps== 420
551 21:57:05.738444 result report
552 21:57:05.743725 boot times 0Enable ddr reg access
553 21:57:05.749025 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 21:57:05.762502 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 21:57:06.336356 0.0;M3 CHK:0;cm4_sp_mode 0
556 21:57:06.336815 MVN_1=0x00000000
557 21:57:06.341728 MVN_2=0x00000000
558 21:57:06.347605 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 21:57:06.348014 OPS=0x10
560 21:57:06.348264 ring efuse init
561 21:57:06.348486 chipver efuse init
562 21:57:06.353183 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 21:57:06.358772 [0.018961 Inits done]
564 21:57:06.359131 secure task start!
565 21:57:06.359362 high task start!
566 21:57:06.363338 low task start!
567 21:57:06.364107 run into bl31
568 21:57:06.369957 NOTICE: BL31: v1.3(release):4fc40b1
569 21:57:06.377823 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 21:57:06.378284 NOTICE: BL31: G12A normal boot!
571 21:57:06.403153 NOTICE: BL31: BL33 decompress pass
572 21:57:06.408817 ERROR: Error initializing runtime service opteed_fast
573 21:57:07.641930
574 21:57:07.642581
575 21:57:07.649013 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 21:57:07.649527
577 21:57:07.649979 Model: Libre Computer AML-A311D-CC Alta
578 21:57:07.857510 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 21:57:07.880882 DRAM: 2 GiB (effective 3.8 GiB)
580 21:57:08.024725 Core: 408 devices, 31 uclasses, devicetree: separate
581 21:57:08.030522 WDT: Not starting watchdog@f0d0
582 21:57:08.062908 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 21:57:08.075420 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 21:57:08.080341 ** Bad device specification mmc 0 **
585 21:57:08.090599 Card did not respond to voltage select! : -110
586 21:57:08.098290 ** Bad device specification mmc 0 **
587 21:57:08.098981 Couldn't find partition mmc 0
588 21:57:08.106670 Card did not respond to voltage select! : -110
589 21:57:08.112202 ** Bad device specification mmc 0 **
590 21:57:08.112926 Couldn't find partition mmc 0
591 21:57:08.117238 Error: could not access storage.
592 21:57:08.459818 Net: eth0: ethernet@ff3f0000
593 21:57:08.460682 starting USB...
594 21:57:08.711732 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 21:57:08.712637 Starting the controller
596 21:57:08.718451 USB XHCI 1.10
597 21:57:10.431014 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 21:57:10.431627 bl2_stage_init 0x01
599 21:57:10.432110 bl2_stage_init 0x81
600 21:57:10.436521 hw id: 0x0000 - pwm id 0x01
601 21:57:10.437016 bl2_stage_init 0xc1
602 21:57:10.437436 bl2_stage_init 0x02
603 21:57:10.437843
604 21:57:10.442175 L0:00000000
605 21:57:10.442675 L1:20000703
606 21:57:10.443097 L2:00008067
607 21:57:10.443505 L3:14000000
608 21:57:10.447718 B2:00402000
609 21:57:10.448202 B1:e0f83180
610 21:57:10.448607
611 21:57:10.449009 TE: 58124
612 21:57:10.449409
613 21:57:10.453312 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 21:57:10.453846
615 21:57:10.454263 Board ID = 1
616 21:57:10.459020 Set A53 clk to 24M
617 21:57:10.459650 Set A73 clk to 24M
618 21:57:10.460183 Set clk81 to 24M
619 21:57:10.464577 A53 clk: 1200 MHz
620 21:57:10.465143 A73 clk: 1200 MHz
621 21:57:10.465605 CLK81: 166.6M
622 21:57:10.466057 smccc: 00012a91
623 21:57:10.470176 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 21:57:10.475758 board id: 1
625 21:57:10.480711 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 21:57:10.492809 fw parse done
627 21:57:10.499856 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 21:57:10.540364 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 21:57:10.552041 PIEI prepare done
630 21:57:10.552708 fastboot data load
631 21:57:10.553229 fastboot data verify
632 21:57:10.557598 verify result: 266
633 21:57:10.563218 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 21:57:10.564056 LPDDR4 probe
635 21:57:10.564778 ddr clk to 1584MHz
636 21:57:10.570181 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 21:57:10.608383
638 21:57:10.609033 dmc_version 0001
639 21:57:10.616169 Check phy result
640 21:57:10.622321 INFO : End of CA training
641 21:57:10.622959 INFO : End of initialization
642 21:57:10.626588 INFO : Training has run successfully!
643 21:57:10.627249 Check phy result
644 21:57:10.632243 INFO : End of initialization
645 21:57:10.632976 INFO : End of read enable training
646 21:57:10.637726 INFO : End of fine write leveling
647 21:57:10.643343 INFO : End of Write leveling coarse delay
648 21:57:10.644132 INFO : Training has run successfully!
649 21:57:10.644774 Check phy result
650 21:57:10.649051 INFO : End of initialization
651 21:57:10.649813 INFO : End of read dq deskew training
652 21:57:10.654474 INFO : End of MPR read delay center optimization
653 21:57:10.660209 INFO : End of write delay center optimization
654 21:57:10.665800 INFO : End of read delay center optimization
655 21:57:10.666500 INFO : End of max read latency training
656 21:57:10.677181 INFO : Training has run successfully!
657 21:57:10.677915 1D training succeed
658 21:57:10.679609 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 21:57:10.727113 Check phy result
660 21:57:10.727565 INFO : End of initialization
661 21:57:10.750587 INFO : End of 2D read delay Voltage center optimization
662 21:57:10.769918 INFO : End of 2D read delay Voltage center optimization
663 21:57:10.822974 INFO : End of 2D write delay Voltage center optimization
664 21:57:10.872274 INFO : End of 2D write delay Voltage center optimization
665 21:57:10.877922 INFO : Training has run successfully!
666 21:57:10.878345
667 21:57:10.878676 channel==0
668 21:57:10.883400 RxClkDly_Margin_A0==88 ps 9
669 21:57:10.883745 TxDqDly_Margin_A0==98 ps 10
670 21:57:10.889071 RxClkDly_Margin_A1==88 ps 9
671 21:57:10.889494 TxDqDly_Margin_A1==98 ps 10
672 21:57:10.889812 TrainedVREFDQ_A0==74
673 21:57:10.894605 TrainedVREFDQ_A1==74
674 21:57:10.894962 VrefDac_Margin_A0==25
675 21:57:10.895220 DeviceVref_Margin_A0==40
676 21:57:10.900354 VrefDac_Margin_A1==24
677 21:57:10.900736 DeviceVref_Margin_A1==40
678 21:57:10.900959
679 21:57:10.901164
680 21:57:10.905908 channel==1
681 21:57:10.906271 RxClkDly_Margin_A0==98 ps 10
682 21:57:10.906497 TxDqDly_Margin_A0==98 ps 10
683 21:57:10.912195 RxClkDly_Margin_A1==88 ps 9
684 21:57:10.912555 TxDqDly_Margin_A1==88 ps 9
685 21:57:10.917171 TrainedVREFDQ_A0==77
686 21:57:10.917764 TrainedVREFDQ_A1==77
687 21:57:10.918221 VrefDac_Margin_A0==22
688 21:57:10.922648 DeviceVref_Margin_A0==37
689 21:57:10.923205 VrefDac_Margin_A1==24
690 21:57:10.928449 DeviceVref_Margin_A1==37
691 21:57:10.929040
692 21:57:10.929496 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 21:57:10.929940
694 21:57:10.962075 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
695 21:57:10.962734 2D training succeed
696 21:57:10.967447 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 21:57:10.973161 auto size-- 65535DDR cs0 size: 2048MB
698 21:57:10.973947 DDR cs1 size: 2048MB
699 21:57:10.978694 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 21:57:10.979375 cs0 DataBus test pass
701 21:57:10.984287 cs1 DataBus test pass
702 21:57:10.985043 cs0 AddrBus test pass
703 21:57:10.985660 cs1 AddrBus test pass
704 21:57:10.986336
705 21:57:10.989966 100bdlr_step_size ps== 420
706 21:57:10.990576 result report
707 21:57:10.995427 boot times 0Enable ddr reg access
708 21:57:11.001038 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 21:57:11.014447 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 21:57:11.588551 0.0;M3 CHK:0;cm4_sp_mode 0
711 21:57:11.589044 MVN_1=0x00000000
712 21:57:11.593267 MVN_2=0x00000000
713 21:57:11.599120 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 21:57:11.599572 OPS=0x10
715 21:57:11.599860 ring efuse init
716 21:57:11.600192 chipver efuse init
717 21:57:11.607780 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 21:57:11.608217 [0.018961 Inits done]
719 21:57:11.608494 secure task start!
720 21:57:11.615083 high task start!
721 21:57:11.615578 low task start!
722 21:57:11.615892 run into bl31
723 21:57:11.621545 NOTICE: BL31: v1.3(release):4fc40b1
724 21:57:11.629398 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 21:57:11.629852 NOTICE: BL31: G12A normal boot!
726 21:57:11.654715 NOTICE: BL31: BL33 decompress pass
727 21:57:11.660394 ERROR: Error initializing runtime service opteed_fast
728 21:57:12.893392
729 21:57:12.893866
730 21:57:12.901785 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 21:57:12.902206
732 21:57:12.902470 Model: Libre Computer AML-A311D-CC Alta
733 21:57:13.110223 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 21:57:13.133643 DRAM: 2 GiB (effective 3.8 GiB)
735 21:57:13.276433 Core: 408 devices, 31 uclasses, devicetree: separate
736 21:57:13.282411 WDT: Not starting watchdog@f0d0
737 21:57:13.314763 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 21:57:13.327152 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 21:57:13.332232 ** Bad device specification mmc 0 **
740 21:57:13.342525 Card did not respond to voltage select! : -110
741 21:57:13.350114 ** Bad device specification mmc 0 **
742 21:57:13.350654 Couldn't find partition mmc 0
743 21:57:13.358531 Card did not respond to voltage select! : -110
744 21:57:13.364068 ** Bad device specification mmc 0 **
745 21:57:13.364820 Couldn't find partition mmc 0
746 21:57:13.369072 Error: could not access storage.
747 21:57:13.712622 Net: eth0: ethernet@ff3f0000
748 21:57:13.713045 starting USB...
749 21:57:13.964221 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 21:57:13.964886 Starting the controller
751 21:57:13.971433 USB XHCI 1.10
752 21:57:16.129966 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 21:57:16.130656 bl2_stage_init 0x01
754 21:57:16.131148 bl2_stage_init 0x81
755 21:57:16.135512 hw id: 0x0000 - pwm id 0x01
756 21:57:16.136116 bl2_stage_init 0xc1
757 21:57:16.136587 bl2_stage_init 0x02
758 21:57:16.137045
759 21:57:16.141204 L0:00000000
760 21:57:16.142079 L1:20000703
761 21:57:16.142752 L2:00008067
762 21:57:16.143473 L3:14000000
763 21:57:16.146661 B2:00402000
764 21:57:16.147451 B1:e0f83180
765 21:57:16.148248
766 21:57:16.148950 TE: 58159
767 21:57:16.149633
768 21:57:16.152321 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 21:57:16.153180
770 21:57:16.153940 Board ID = 1
771 21:57:16.157824 Set A53 clk to 24M
772 21:57:16.158559 Set A73 clk to 24M
773 21:57:16.159254 Set clk81 to 24M
774 21:57:16.163547 A53 clk: 1200 MHz
775 21:57:16.164351 A73 clk: 1200 MHz
776 21:57:16.165082 CLK81: 166.6M
777 21:57:16.165805 smccc: 00012ab5
778 21:57:16.169061 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 21:57:16.179768 board id: 1
780 21:57:16.180780 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 21:57:16.191004 fw parse done
782 21:57:16.196926 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 21:57:16.239574 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 21:57:16.250498 PIEI prepare done
785 21:57:16.251007 fastboot data load
786 21:57:16.251455 fastboot data verify
787 21:57:16.256231 verify result: 266
788 21:57:16.261778 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 21:57:16.262262 LPDDR4 probe
790 21:57:16.262701 ddr clk to 1584MHz
791 21:57:16.269933 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 21:57:16.307155
793 21:57:16.307686 dmc_version 0001
794 21:57:16.313755 Check phy result
795 21:57:16.319541 INFO : End of CA training
796 21:57:16.320047 INFO : End of initialization
797 21:57:16.325136 INFO : Training has run successfully!
798 21:57:16.325616 Check phy result
799 21:57:16.330680 INFO : End of initialization
800 21:57:16.330932 INFO : End of read enable training
801 21:57:16.336319 INFO : End of fine write leveling
802 21:57:16.341966 INFO : End of Write leveling coarse delay
803 21:57:16.342584 INFO : Training has run successfully!
804 21:57:16.343075 Check phy result
805 21:57:16.347510 INFO : End of initialization
806 21:57:16.348105 INFO : End of read dq deskew training
807 21:57:16.353084 INFO : End of MPR read delay center optimization
808 21:57:16.358689 INFO : End of write delay center optimization
809 21:57:16.364336 INFO : End of read delay center optimization
810 21:57:16.364909 INFO : End of max read latency training
811 21:57:16.369888 INFO : Training has run successfully!
812 21:57:16.370451 1D training succeed
813 21:57:16.379251 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 21:57:16.426929 Check phy result
815 21:57:16.427581 INFO : End of initialization
816 21:57:16.448385 INFO : End of 2D read delay Voltage center optimization
817 21:57:16.469773 INFO : End of 2D read delay Voltage center optimization
818 21:57:16.519683 INFO : End of 2D write delay Voltage center optimization
819 21:57:16.568890 INFO : End of 2D write delay Voltage center optimization
820 21:57:16.574354 INFO : Training has run successfully!
821 21:57:16.574951
822 21:57:16.575439 channel==0
823 21:57:16.579945 RxClkDly_Margin_A0==88 ps 9
824 21:57:16.580560 TxDqDly_Margin_A0==98 ps 10
825 21:57:16.586847 RxClkDly_Margin_A1==88 ps 9
826 21:57:16.587388 TxDqDly_Margin_A1==98 ps 10
827 21:57:16.587834 TrainedVREFDQ_A0==74
828 21:57:16.591181 TrainedVREFDQ_A1==74
829 21:57:16.591797 VrefDac_Margin_A0==25
830 21:57:16.592345 DeviceVref_Margin_A0==40
831 21:57:16.596880 VrefDac_Margin_A1==25
832 21:57:16.597414 DeviceVref_Margin_A1==40
833 21:57:16.597847
834 21:57:16.598279
835 21:57:16.602260 channel==1
836 21:57:16.602736 RxClkDly_Margin_A0==98 ps 10
837 21:57:16.603169 TxDqDly_Margin_A0==88 ps 9
838 21:57:16.607842 RxClkDly_Margin_A1==88 ps 9
839 21:57:16.608364 TxDqDly_Margin_A1==88 ps 9
840 21:57:16.613480 TrainedVREFDQ_A0==77
841 21:57:16.613956 TrainedVREFDQ_A1==77
842 21:57:16.614391 VrefDac_Margin_A0==23
843 21:57:16.619038 DeviceVref_Margin_A0==37
844 21:57:16.619524 VrefDac_Margin_A1==24
845 21:57:16.624627 DeviceVref_Margin_A1==37
846 21:57:16.625104
847 21:57:16.625536 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 21:57:16.625969
849 21:57:16.658248 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
850 21:57:16.658862 2D training succeed
851 21:57:16.663838 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 21:57:16.669548 auto size-- 65535DDR cs0 size: 2048MB
853 21:57:16.670124 DDR cs1 size: 2048MB
854 21:57:16.675046 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 21:57:16.675588 cs0 DataBus test pass
856 21:57:16.680645 cs1 DataBus test pass
857 21:57:16.681188 cs0 AddrBus test pass
858 21:57:16.681656 cs1 AddrBus test pass
859 21:57:16.682110
860 21:57:16.686251 100bdlr_step_size ps== 420
861 21:57:16.686786 result report
862 21:57:16.691917 boot times 0Enable ddr reg access
863 21:57:16.697113 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 21:57:16.710551 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 21:57:17.282722 0.0;M3 CHK:0;cm4_sp_mode 0
866 21:57:17.283399 MVN_1=0x00000000
867 21:57:17.288181 MVN_2=0x00000000
868 21:57:17.293899 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 21:57:17.294397 OPS=0x10
870 21:57:17.294839 ring efuse init
871 21:57:17.295275 chipver efuse init
872 21:57:17.299507 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 21:57:17.306226 [0.018961 Inits done]
874 21:57:17.306720 secure task start!
875 21:57:17.307158 high task start!
876 21:57:17.309762 low task start!
877 21:57:17.310244 run into bl31
878 21:57:17.316438 NOTICE: BL31: v1.3(release):4fc40b1
879 21:57:17.324268 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 21:57:17.324763 NOTICE: BL31: G12A normal boot!
881 21:57:17.349751 NOTICE: BL31: BL33 decompress pass
882 21:57:17.355478 ERROR: Error initializing runtime service opteed_fast
883 21:57:18.588274
884 21:57:18.588970
885 21:57:18.596521 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 21:57:18.597028
887 21:57:18.597477 Model: Libre Computer AML-A311D-CC Alta
888 21:57:18.805058 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 21:57:18.828384 DRAM: 2 GiB (effective 3.8 GiB)
890 21:57:18.971373 Core: 408 devices, 31 uclasses, devicetree: separate
891 21:57:18.977166 WDT: Not starting watchdog@f0d0
892 21:57:19.009415 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 21:57:19.022046 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 21:57:19.027037 ** Bad device specification mmc 0 **
895 21:57:19.037209 Card did not respond to voltage select! : -110
896 21:57:19.044937 ** Bad device specification mmc 0 **
897 21:57:19.045433 Couldn't find partition mmc 0
898 21:57:19.053256 Card did not respond to voltage select! : -110
899 21:57:19.058730 ** Bad device specification mmc 0 **
900 21:57:19.059212 Couldn't find partition mmc 0
901 21:57:19.063784 Error: could not access storage.
902 21:57:19.406577 Net: eth0: ethernet@ff3f0000
903 21:57:19.407182 starting USB...
904 21:57:19.658511 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 21:57:19.659149 Starting the controller
906 21:57:19.665323 USB XHCI 1.10
907 21:57:21.529673 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 21:57:21.530338 bl2_stage_init 0x01
909 21:57:21.530813 bl2_stage_init 0x81
910 21:57:21.535196 hw id: 0x0000 - pwm id 0x01
911 21:57:21.535698 bl2_stage_init 0xc1
912 21:57:21.536205 bl2_stage_init 0x02
913 21:57:21.536655
914 21:57:21.540804 L0:00000000
915 21:57:21.541300 L1:20000703
916 21:57:21.541768 L2:00008067
917 21:57:21.542224 L3:14000000
918 21:57:21.543722 B2:00402000
919 21:57:21.544239 B1:e0f83180
920 21:57:21.544688
921 21:57:21.545133 TE: 58159
922 21:57:21.545576
923 21:57:21.554847 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 21:57:21.555368
925 21:57:21.555826 Board ID = 1
926 21:57:21.556319 Set A53 clk to 24M
927 21:57:21.556766 Set A73 clk to 24M
928 21:57:21.560507 Set clk81 to 24M
929 21:57:21.560982 A53 clk: 1200 MHz
930 21:57:21.561426 A73 clk: 1200 MHz
931 21:57:21.566075 CLK81: 166.6M
932 21:57:21.566550 smccc: 00012ab5
933 21:57:21.571691 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 21:57:21.572252 board id: 1
935 21:57:21.580241 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 21:57:21.590810 fw parse done
937 21:57:21.596773 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 21:57:21.639488 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 21:57:21.650562 PIEI prepare done
940 21:57:21.651063 fastboot data load
941 21:57:21.651507 fastboot data verify
942 21:57:21.656068 verify result: 266
943 21:57:21.661603 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 21:57:21.662078 LPDDR4 probe
945 21:57:21.662508 ddr clk to 1584MHz
946 21:57:21.669580 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 21:57:21.706867
948 21:57:21.707359 dmc_version 0001
949 21:57:21.713606 Check phy result
950 21:57:21.719464 INFO : End of CA training
951 21:57:21.719940 INFO : End of initialization
952 21:57:21.725074 INFO : Training has run successfully!
953 21:57:21.725607 Check phy result
954 21:57:21.730611 INFO : End of initialization
955 21:57:21.731086 INFO : End of read enable training
956 21:57:21.733902 INFO : End of fine write leveling
957 21:57:21.739405 INFO : End of Write leveling coarse delay
958 21:57:21.745005 INFO : Training has run successfully!
959 21:57:21.745469 Check phy result
960 21:57:21.745913 INFO : End of initialization
961 21:57:21.750647 INFO : End of read dq deskew training
962 21:57:21.756273 INFO : End of MPR read delay center optimization
963 21:57:21.756752 INFO : End of write delay center optimization
964 21:57:21.761857 INFO : End of read delay center optimization
965 21:57:21.767464 INFO : End of max read latency training
966 21:57:21.767942 INFO : Training has run successfully!
967 21:57:21.773040 1D training succeed
968 21:57:21.779131 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 21:57:21.826603 Check phy result
970 21:57:21.827091 INFO : End of initialization
971 21:57:21.848269 INFO : End of 2D read delay Voltage center optimization
972 21:57:21.867445 INFO : End of 2D read delay Voltage center optimization
973 21:57:21.919462 INFO : End of 2D write delay Voltage center optimization
974 21:57:21.968649 INFO : End of 2D write delay Voltage center optimization
975 21:57:21.974189 INFO : Training has run successfully!
976 21:57:21.974670
977 21:57:21.975122 channel==0
978 21:57:21.979877 RxClkDly_Margin_A0==88 ps 9
979 21:57:21.980396 TxDqDly_Margin_A0==98 ps 10
980 21:57:21.985372 RxClkDly_Margin_A1==88 ps 9
981 21:57:21.985868 TxDqDly_Margin_A1==98 ps 10
982 21:57:21.986320 TrainedVREFDQ_A0==74
983 21:57:21.991050 TrainedVREFDQ_A1==74
984 21:57:21.991528 VrefDac_Margin_A0==25
985 21:57:21.991974 DeviceVref_Margin_A0==40
986 21:57:21.996635 VrefDac_Margin_A1==25
987 21:57:21.997109 DeviceVref_Margin_A1==40
988 21:57:21.997550
989 21:57:21.997990
990 21:57:22.002223 channel==1
991 21:57:22.002696 RxClkDly_Margin_A0==88 ps 9
992 21:57:22.003140 TxDqDly_Margin_A0==98 ps 10
993 21:57:22.007784 RxClkDly_Margin_A1==98 ps 10
994 21:57:22.008289 TxDqDly_Margin_A1==88 ps 9
995 21:57:22.013345 TrainedVREFDQ_A0==77
996 21:57:22.013821 TrainedVREFDQ_A1==77
997 21:57:22.014270 VrefDac_Margin_A0==23
998 21:57:22.019039 DeviceVref_Margin_A0==37
999 21:57:22.019516 VrefDac_Margin_A1==23
1000 21:57:22.024635 DeviceVref_Margin_A1==37
1001 21:57:22.025112
1002 21:57:22.025557 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 21:57:22.025998
1004 21:57:22.058144 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1005 21:57:22.058745 2D training succeed
1006 21:57:22.063732 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 21:57:22.069302 auto size-- 65535DDR cs0 size: 2048MB
1008 21:57:22.069794 DDR cs1 size: 2048MB
1009 21:57:22.074963 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 21:57:22.075442 cs0 DataBus test pass
1011 21:57:22.080529 cs1 DataBus test pass
1012 21:57:22.081008 cs0 AddrBus test pass
1013 21:57:22.081452 cs1 AddrBus test pass
1014 21:57:22.081892
1015 21:57:22.086133 100bdlr_step_size ps== 420
1016 21:57:22.086693 result report
1017 21:57:22.091703 boot times 0Enable ddr reg access
1018 21:57:22.097083 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 21:57:22.110614 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 21:57:22.682628 0.0;M3 CHK:0;cm4_sp_mode 0
1021 21:57:22.683308 MVN_1=0x00000000
1022 21:57:22.687949 MVN_2=0x00000000
1023 21:57:22.693712 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 21:57:22.694199 OPS=0x10
1025 21:57:22.694657 ring efuse init
1026 21:57:22.695105 chipver efuse init
1027 21:57:22.699369 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 21:57:22.704962 [0.018960 Inits done]
1029 21:57:22.705442 secure task start!
1030 21:57:22.705887 high task start!
1031 21:57:22.709475 low task start!
1032 21:57:22.709941 run into bl31
1033 21:57:22.716217 NOTICE: BL31: v1.3(release):4fc40b1
1034 21:57:22.723974 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 21:57:22.724494 NOTICE: BL31: G12A normal boot!
1036 21:57:22.749325 NOTICE: BL31: BL33 decompress pass
1037 21:57:22.754988 ERROR: Error initializing runtime service opteed_fast
1038 21:57:23.987937
1039 21:57:23.988398
1040 21:57:23.996212 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 21:57:23.996512
1042 21:57:23.996739 Model: Libre Computer AML-A311D-CC Alta
1043 21:57:24.204810 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 21:57:24.228047 DRAM: 2 GiB (effective 3.8 GiB)
1045 21:57:24.371061 Core: 408 devices, 31 uclasses, devicetree: separate
1046 21:57:24.376879 WDT: Not starting watchdog@f0d0
1047 21:57:24.409160 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 21:57:24.421619 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 21:57:24.426572 ** Bad device specification mmc 0 **
1050 21:57:24.436964 Card did not respond to voltage select! : -110
1051 21:57:24.444582 ** Bad device specification mmc 0 **
1052 21:57:24.444860 Couldn't find partition mmc 0
1053 21:57:24.452899 Card did not respond to voltage select! : -110
1054 21:57:24.458518 ** Bad device specification mmc 0 **
1055 21:57:24.458929 Couldn't find partition mmc 0
1056 21:57:24.463498 Error: could not access storage.
1057 21:57:24.807027 Net: eth0: ethernet@ff3f0000
1058 21:57:24.807438 starting USB...
1059 21:57:25.058887 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 21:57:25.059333 Starting the controller
1061 21:57:25.065831 USB XHCI 1.10
1062 21:57:26.620092 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 21:57:26.628330 scanning usb for storage devices... 0 Storage Device(s) found
1065 21:57:26.679860 Hit any key to stop autoboot: 1
1066 21:57:26.680741 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 21:57:26.681320 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 21:57:26.681782 Setting prompt string to ['=>']
1069 21:57:26.682251 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 21:57:26.695774 0
1071 21:57:26.696670 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 21:57:26.697158 Sending with 10 millisecond of delay
1074 21:57:27.832360 => setenv autoload no
1075 21:57:27.843419 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1076 21:57:27.849911 setenv autoload no
1077 21:57:27.850957 Sending with 10 millisecond of delay
1079 21:57:29.649418 => setenv initrd_high 0xffffffff
1080 21:57:29.660220 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 21:57:29.661068 setenv initrd_high 0xffffffff
1082 21:57:29.661768 Sending with 10 millisecond of delay
1084 21:57:31.279154 => setenv fdt_high 0xffffffff
1085 21:57:31.290247 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 21:57:31.291382 setenv fdt_high 0xffffffff
1087 21:57:31.292301 Sending with 10 millisecond of delay
1089 21:57:31.584717 => dhcp
1090 21:57:31.595510 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 21:57:31.596358 dhcp
1092 21:57:31.596800 Speed: 1000, full duplex
1093 21:57:31.597210 BOOTP broadcast 1
1094 21:57:31.603828 DHCP client bound to address 192.168.6.27 (8 ms)
1095 21:57:31.604565 Sending with 10 millisecond of delay
1097 21:57:33.281293 => setenv serverip 192.168.6.2
1098 21:57:33.292087 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 21:57:33.292955 setenv serverip 192.168.6.2
1100 21:57:33.293638 Sending with 10 millisecond of delay
1102 21:57:37.018208 => tftpboot 0x01080000 955836/tftp-deploy-93t_19qq/kernel/uImage
1103 21:57:37.029210 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 21:57:37.030274 tftpboot 0x01080000 955836/tftp-deploy-93t_19qq/kernel/uImage
1105 21:57:37.030857 Speed: 1000, full duplex
1106 21:57:37.031384 Using ethernet@ff3f0000 device
1107 21:57:37.032061 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 21:57:37.037428 Filename '955836/tftp-deploy-93t_19qq/kernel/uImage'.
1109 21:57:37.041291 Load address: 0x1080000
1110 21:57:39.896214 Loading: *################################################## 43.6 MiB
1111 21:57:39.896855 15.3 MiB/s
1112 21:57:39.897328 done
1113 21:57:39.899760 Bytes transferred = 45713984 (2b98a40 hex)
1114 21:57:39.900632 Sending with 10 millisecond of delay
1116 21:57:44.587968 => tftpboot 0x08000000 955836/tftp-deploy-93t_19qq/ramdisk/ramdisk.cpio.gz.uboot
1117 21:57:44.598842 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1118 21:57:44.599697 tftpboot 0x08000000 955836/tftp-deploy-93t_19qq/ramdisk/ramdisk.cpio.gz.uboot
1119 21:57:44.600220 Speed: 1000, full duplex
1120 21:57:44.600680 Using ethernet@ff3f0000 device
1121 21:57:44.601463 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 21:57:44.613131 Filename '955836/tftp-deploy-93t_19qq/ramdisk/ramdisk.cpio.gz.uboot'.
1123 21:57:44.613625 Load address: 0x8000000
1124 21:57:47.056783 Loading: *#################### UDP wrong checksum 00000005 0000844b
1125 21:57:51.216230 T ############################# UDP wrong checksum 00000005 0000fc3a
1126 21:57:56.216439 T UDP wrong checksum 00000005 0000fc3a
1127 21:58:06.219972 T T UDP wrong checksum 00000005 0000fc3a
1128 21:58:17.797458 T T UDP wrong checksum 000000ff 000078ae
1129 21:58:17.821277 UDP wrong checksum 000000ff 00000ca1
1130 21:58:26.223938 T T UDP wrong checksum 00000005 0000fc3a
1131 21:58:41.228180 T T
1132 21:58:41.228917 Retry count exceeded; starting again
1134 21:58:41.231503 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1137 21:58:41.233707 end: 2.4 uboot-commands (duration 00:01:52) [common]
1139 21:58:41.235259 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1141 21:58:41.236422 end: 2 uboot-action (duration 00:01:52) [common]
1143 21:58:41.238069 Cleaning after the job
1144 21:58:41.238667 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955836/tftp-deploy-93t_19qq/ramdisk
1145 21:58:41.240110 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955836/tftp-deploy-93t_19qq/kernel
1146 21:58:41.248207 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955836/tftp-deploy-93t_19qq/dtb
1147 21:58:41.249485 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955836/tftp-deploy-93t_19qq/modules
1148 21:58:41.263052 start: 4.1 power-off (timeout 00:00:30) [common]
1149 21:58:41.264218 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1150 21:58:41.299738 >> OK - accepted request
1151 21:58:41.302427 Returned 0 in 0 seconds
1152 21:58:41.403632 end: 4.1 power-off (duration 00:00:00) [common]
1154 21:58:41.405465 start: 4.2 read-feedback (timeout 00:10:00) [common]
1155 21:58:41.406677 Listened to connection for namespace 'common' for up to 1s
1156 21:58:42.406479 Finalising connection for namespace 'common'
1157 21:58:42.407259 Disconnecting from shell: Finalise
1158 21:58:42.407831 =>
1159 21:58:42.508957 end: 4.2 read-feedback (duration 00:00:01) [common]
1160 21:58:42.509411 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/955836
1161 21:58:42.762156 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/955836
1162 21:58:42.762759 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.