Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:01:57.790101 lava-dispatcher, installed at version: 2024.01
2 01:01:57.790861 start: 0 validate
3 01:01:57.791325 Start time: 2024-11-08 01:01:57.791295+00:00 (UTC)
4 01:01:57.791861 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:01:57.792420 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:01:57.835740 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:01:57.836342 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-63-g2e9baed573ee%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:01:57.868295 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:01:57.868908 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-63-g2e9baed573ee%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 01:01:57.900656 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:01:57.901381 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-63-g2e9baed573ee%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 01:01:57.936215 validate duration: 0.15
14 01:01:57.937065 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:01:57.937380 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:01:57.937670 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:01:57.938247 Not decompressing ramdisk as can be used compressed.
18 01:01:57.938668 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 01:01:57.938933 saving as /var/lib/lava/dispatcher/tmp/955840/tftp-deploy-nl3nq4j1/ramdisk/rootfs.cpio.gz
20 01:01:57.939196 total size: 47897469 (45 MB)
21 01:01:57.989199 progress 0 % (0 MB)
22 01:01:58.021992 progress 5 % (2 MB)
23 01:01:58.051511 progress 10 % (4 MB)
24 01:01:58.081172 progress 15 % (6 MB)
25 01:01:58.110623 progress 20 % (9 MB)
26 01:01:58.140421 progress 25 % (11 MB)
27 01:01:58.170277 progress 30 % (13 MB)
28 01:01:58.202109 progress 35 % (16 MB)
29 01:01:58.231682 progress 40 % (18 MB)
30 01:01:58.261680 progress 45 % (20 MB)
31 01:01:58.291637 progress 50 % (22 MB)
32 01:01:58.321765 progress 55 % (25 MB)
33 01:01:58.351886 progress 60 % (27 MB)
34 01:01:58.384006 progress 65 % (29 MB)
35 01:01:58.413454 progress 70 % (32 MB)
36 01:01:58.442964 progress 75 % (34 MB)
37 01:01:58.472339 progress 80 % (36 MB)
38 01:01:58.501920 progress 85 % (38 MB)
39 01:01:58.531656 progress 90 % (41 MB)
40 01:01:58.561052 progress 95 % (43 MB)
41 01:01:58.589970 progress 100 % (45 MB)
42 01:01:58.590708 45 MB downloaded in 0.65 s (70.11 MB/s)
43 01:01:58.591269 end: 1.1.1 http-download (duration 00:00:01) [common]
45 01:01:58.592185 end: 1.1 download-retry (duration 00:00:01) [common]
46 01:01:58.592481 start: 1.2 download-retry (timeout 00:09:59) [common]
47 01:01:58.592755 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 01:01:58.593232 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-63-g2e9baed573ee/arm64/defconfig/gcc-12/kernel/Image
49 01:01:58.593481 saving as /var/lib/lava/dispatcher/tmp/955840/tftp-deploy-nl3nq4j1/kernel/Image
50 01:01:58.593692 total size: 45713920 (43 MB)
51 01:01:58.593905 No compression specified
52 01:01:58.637010 progress 0 % (0 MB)
53 01:01:58.664916 progress 5 % (2 MB)
54 01:01:58.692841 progress 10 % (4 MB)
55 01:01:58.721199 progress 15 % (6 MB)
56 01:01:58.749702 progress 20 % (8 MB)
57 01:01:58.777501 progress 25 % (10 MB)
58 01:01:58.805443 progress 30 % (13 MB)
59 01:01:58.833155 progress 35 % (15 MB)
60 01:01:58.861337 progress 40 % (17 MB)
61 01:01:58.888559 progress 45 % (19 MB)
62 01:01:58.916387 progress 50 % (21 MB)
63 01:01:58.944345 progress 55 % (24 MB)
64 01:01:58.971947 progress 60 % (26 MB)
65 01:01:58.999299 progress 65 % (28 MB)
66 01:01:59.027101 progress 70 % (30 MB)
67 01:01:59.055236 progress 75 % (32 MB)
68 01:01:59.082905 progress 80 % (34 MB)
69 01:01:59.110198 progress 85 % (37 MB)
70 01:01:59.138010 progress 90 % (39 MB)
71 01:01:59.165878 progress 95 % (41 MB)
72 01:01:59.193382 progress 100 % (43 MB)
73 01:01:59.193910 43 MB downloaded in 0.60 s (72.64 MB/s)
74 01:01:59.194395 end: 1.2.1 http-download (duration 00:00:01) [common]
76 01:01:59.195214 end: 1.2 download-retry (duration 00:00:01) [common]
77 01:01:59.195489 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:01:59.195753 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:01:59.196251 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-63-g2e9baed573ee/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 01:01:59.196534 saving as /var/lib/lava/dispatcher/tmp/955840/tftp-deploy-nl3nq4j1/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 01:01:59.196743 total size: 53209 (0 MB)
82 01:01:59.196953 No compression specified
83 01:01:59.239532 progress 61 % (0 MB)
84 01:01:59.240412 progress 100 % (0 MB)
85 01:01:59.240985 0 MB downloaded in 0.04 s (1.15 MB/s)
86 01:01:59.241437 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:01:59.242242 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:01:59.242503 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:01:59.242765 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:01:59.243225 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-63-g2e9baed573ee/arm64/defconfig/gcc-12/modules.tar.xz
92 01:01:59.243465 saving as /var/lib/lava/dispatcher/tmp/955840/tftp-deploy-nl3nq4j1/modules/modules.tar
93 01:01:59.243669 total size: 11603932 (11 MB)
94 01:01:59.243878 Using unxz to decompress xz
95 01:01:59.284185 progress 0 % (0 MB)
96 01:01:59.349639 progress 5 % (0 MB)
97 01:01:59.424237 progress 10 % (1 MB)
98 01:01:59.520438 progress 15 % (1 MB)
99 01:01:59.613264 progress 20 % (2 MB)
100 01:01:59.692395 progress 25 % (2 MB)
101 01:01:59.768429 progress 30 % (3 MB)
102 01:01:59.842644 progress 35 % (3 MB)
103 01:01:59.919574 progress 40 % (4 MB)
104 01:01:59.995528 progress 45 % (5 MB)
105 01:02:00.079594 progress 50 % (5 MB)
106 01:02:00.156692 progress 55 % (6 MB)
107 01:02:00.242135 progress 60 % (6 MB)
108 01:02:00.322358 progress 65 % (7 MB)
109 01:02:00.398425 progress 70 % (7 MB)
110 01:02:00.481075 progress 75 % (8 MB)
111 01:02:00.567458 progress 80 % (8 MB)
112 01:02:00.649590 progress 85 % (9 MB)
113 01:02:00.728649 progress 90 % (9 MB)
114 01:02:00.805626 progress 95 % (10 MB)
115 01:02:00.882251 progress 100 % (11 MB)
116 01:02:00.892744 11 MB downloaded in 1.65 s (6.71 MB/s)
117 01:02:00.893338 end: 1.4.1 http-download (duration 00:00:02) [common]
119 01:02:00.894170 end: 1.4 download-retry (duration 00:00:02) [common]
120 01:02:00.894443 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 01:02:00.894711 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 01:02:00.894963 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:02:00.895218 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 01:02:00.895851 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8
125 01:02:00.896885 makedir: /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin
126 01:02:00.897584 makedir: /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/tests
127 01:02:00.898313 makedir: /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/results
128 01:02:00.898955 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-add-keys
129 01:02:00.899918 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-add-sources
130 01:02:00.900910 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-background-process-start
131 01:02:00.901856 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-background-process-stop
132 01:02:00.902876 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-common-functions
133 01:02:00.903797 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-echo-ipv4
134 01:02:00.904749 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-install-packages
135 01:02:00.905647 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-installed-packages
136 01:02:00.906534 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-os-build
137 01:02:00.907419 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-probe-channel
138 01:02:00.908373 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-probe-ip
139 01:02:00.909306 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-target-ip
140 01:02:00.910199 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-target-mac
141 01:02:00.911118 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-target-storage
142 01:02:00.912054 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-test-case
143 01:02:00.912964 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-test-event
144 01:02:00.913851 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-test-feedback
145 01:02:00.914734 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-test-raise
146 01:02:00.915651 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-test-reference
147 01:02:00.916596 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-test-runner
148 01:02:00.917497 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-test-set
149 01:02:00.918391 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-test-shell
150 01:02:00.919297 Updating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-install-packages (oe)
151 01:02:00.920321 Updating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/bin/lava-installed-packages (oe)
152 01:02:00.921252 Creating /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/environment
153 01:02:00.921989 LAVA metadata
154 01:02:00.922505 - LAVA_JOB_ID=955840
155 01:02:00.922937 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:02:00.923593 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 01:02:00.925479 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:02:00.926106 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 01:02:00.926526 skipped lava-vland-overlay
160 01:02:00.927012 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:02:00.927522 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 01:02:00.927948 skipped lava-multinode-overlay
163 01:02:00.928470 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:02:00.928976 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 01:02:00.929450 Loading test definitions
166 01:02:00.929994 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 01:02:00.930446 Using /lava-955840 at stage 0
168 01:02:00.932435 uuid=955840_1.5.2.4.1 testdef=None
169 01:02:00.932785 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:02:00.933078 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 01:02:00.934854 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:02:00.935687 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 01:02:00.937884 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:02:00.938784 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 01:02:00.940928 runner path: /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/0/tests/0_igt-gpu-panfrost test_uuid 955840_1.5.2.4.1
178 01:02:00.941545 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:02:00.942408 Creating lava-test-runner.conf files
181 01:02:00.942626 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/955840/lava-overlay-aahtina8/lava-955840/0 for stage 0
182 01:02:00.942978 - 0_igt-gpu-panfrost
183 01:02:00.943352 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:02:00.943646 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 01:02:00.967642 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:02:00.968073 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 01:02:00.968359 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:02:00.968633 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:02:00.968906 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 01:02:07.954203 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 01:02:07.954939 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 01:02:07.955408 extracting modules file /var/lib/lava/dispatcher/tmp/955840/tftp-deploy-nl3nq4j1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955840/extract-overlay-ramdisk-hmb56gos/ramdisk
193 01:02:09.436519 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 01:02:09.436984 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 01:02:09.437264 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955840/compress-overlay-zdwjzxtz/overlay-1.5.2.5.tar.gz to ramdisk
196 01:02:09.437480 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955840/compress-overlay-zdwjzxtz/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/955840/extract-overlay-ramdisk-hmb56gos/ramdisk
197 01:02:09.467776 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:02:09.468213 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 01:02:09.468491 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 01:02:09.468719 Converting downloaded kernel to a uImage
201 01:02:09.469023 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/955840/tftp-deploy-nl3nq4j1/kernel/Image /var/lib/lava/dispatcher/tmp/955840/tftp-deploy-nl3nq4j1/kernel/uImage
202 01:02:09.926033 output: Image Name:
203 01:02:09.926441 output: Created: Fri Nov 8 01:02:09 2024
204 01:02:09.926652 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:02:09.926857 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 01:02:09.927059 output: Load Address: 01080000
207 01:02:09.927258 output: Entry Point: 01080000
208 01:02:09.927456 output:
209 01:02:09.927787 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 01:02:09.928090 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 01:02:09.928372 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 01:02:09.928627 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:02:09.928883 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 01:02:09.929145 Building ramdisk /var/lib/lava/dispatcher/tmp/955840/extract-overlay-ramdisk-hmb56gos/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/955840/extract-overlay-ramdisk-hmb56gos/ramdisk
215 01:02:16.393002 >> 502362 blocks
216 01:02:36.916874 Adding RAMdisk u-boot header.
217 01:02:36.917578 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/955840/extract-overlay-ramdisk-hmb56gos/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/955840/extract-overlay-ramdisk-hmb56gos/ramdisk.cpio.gz.uboot
218 01:02:37.657567 output: Image Name:
219 01:02:37.657983 output: Created: Fri Nov 8 01:02:36 2024
220 01:02:37.658191 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:02:37.658396 output: Data Size: 65713581 Bytes = 64173.42 KiB = 62.67 MiB
222 01:02:37.658596 output: Load Address: 00000000
223 01:02:37.658803 output: Entry Point: 00000000
224 01:02:37.659020 output:
225 01:02:37.659675 rename /var/lib/lava/dispatcher/tmp/955840/extract-overlay-ramdisk-hmb56gos/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/955840/tftp-deploy-nl3nq4j1/ramdisk/ramdisk.cpio.gz.uboot
226 01:02:37.660184 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 01:02:37.660778 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 01:02:37.661308 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 01:02:37.661755 No LXC device requested
230 01:02:37.662245 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:02:37.662744 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 01:02:37.663256 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:02:37.663665 Checking files for TFTP limit of 4294967296 bytes.
234 01:02:37.666319 end: 1 tftp-deploy (duration 00:00:40) [common]
235 01:02:37.666939 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:02:37.667498 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:02:37.668048 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:02:37.668592 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:02:37.669152 Using kernel file from prepare-kernel: 955840/tftp-deploy-nl3nq4j1/kernel/uImage
240 01:02:37.669804 substitutions:
241 01:02:37.670232 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:02:37.670635 - {DTB_ADDR}: 0x01070000
243 01:02:37.671030 - {DTB}: 955840/tftp-deploy-nl3nq4j1/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 01:02:37.671425 - {INITRD}: 955840/tftp-deploy-nl3nq4j1/ramdisk/ramdisk.cpio.gz.uboot
245 01:02:37.671816 - {KERNEL_ADDR}: 0x01080000
246 01:02:37.672235 - {KERNEL}: 955840/tftp-deploy-nl3nq4j1/kernel/uImage
247 01:02:37.672646 - {LAVA_MAC}: None
248 01:02:37.673084 - {PRESEED_CONFIG}: None
249 01:02:37.673477 - {PRESEED_LOCAL}: None
250 01:02:37.673877 - {RAMDISK_ADDR}: 0x08000000
251 01:02:37.674277 - {RAMDISK}: 955840/tftp-deploy-nl3nq4j1/ramdisk/ramdisk.cpio.gz.uboot
252 01:02:37.674682 - {ROOT_PART}: None
253 01:02:37.675076 - {ROOT}: None
254 01:02:37.675466 - {SERVER_IP}: 192.168.6.2
255 01:02:37.675861 - {TEE_ADDR}: 0x83000000
256 01:02:37.676282 - {TEE}: None
257 01:02:37.676673 Parsed boot commands:
258 01:02:37.677049 - setenv autoload no
259 01:02:37.677435 - setenv initrd_high 0xffffffff
260 01:02:37.677820 - setenv fdt_high 0xffffffff
261 01:02:37.678201 - dhcp
262 01:02:37.678588 - setenv serverip 192.168.6.2
263 01:02:37.678972 - tftpboot 0x01080000 955840/tftp-deploy-nl3nq4j1/kernel/uImage
264 01:02:37.679358 - tftpboot 0x08000000 955840/tftp-deploy-nl3nq4j1/ramdisk/ramdisk.cpio.gz.uboot
265 01:02:37.679744 - tftpboot 0x01070000 955840/tftp-deploy-nl3nq4j1/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 01:02:37.680186 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:02:37.680606 - bootm 0x01080000 0x08000000 0x01070000
268 01:02:37.681137 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:02:37.682696 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:02:37.683159 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 01:02:37.697032 Setting prompt string to ['lava-test: # ']
273 01:02:37.698532 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:02:37.699119 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:02:37.699699 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:02:37.700296 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:02:37.701435 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 01:02:37.736173 >> OK - accepted request
279 01:02:37.738378 Returned 0 in 0 seconds
280 01:02:37.839543 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:02:37.841342 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:02:37.841906 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:02:37.842419 Setting prompt string to ['Hit any key to stop autoboot']
285 01:02:37.842889 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:02:37.844511 Trying 192.168.56.21...
287 01:02:37.845009 Connected to conserv1.
288 01:02:37.845422 Escape character is '^]'.
289 01:02:37.845833
290 01:02:37.846262 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 01:02:37.846705
292 01:02:45.331223 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 01:02:45.331866 bl2_stage_init 0x01
294 01:02:45.332401 bl2_stage_init 0x81
295 01:02:45.336726 hw id: 0x0000 - pwm id 0x01
296 01:02:45.337192 bl2_stage_init 0xc1
297 01:02:45.342386 bl2_stage_init 0x02
298 01:02:45.342846
299 01:02:45.343274 L0:00000000
300 01:02:45.343689 L1:00000703
301 01:02:45.344126 L2:00008067
302 01:02:45.344528 L3:15000000
303 01:02:45.348038 S1:00000000
304 01:02:45.348480 B2:20282000
305 01:02:45.348885 B1:a0f83180
306 01:02:45.349283
307 01:02:45.349681 TE: 68784
308 01:02:45.350077
309 01:02:45.353612 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 01:02:45.354055
311 01:02:45.359086 Board ID = 1
312 01:02:45.359519 Set cpu clk to 24M
313 01:02:45.359918 Set clk81 to 24M
314 01:02:45.364710 Use GP1_pll as DSU clk.
315 01:02:45.365153 DSU clk: 1200 Mhz
316 01:02:45.365554 CPU clk: 1200 MHz
317 01:02:45.370411 Set clk81 to 166.6M
318 01:02:45.375997 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 01:02:45.376448 board id: 1
320 01:02:45.383107 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:02:45.393733 fw parse done
322 01:02:45.399629 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:02:45.442379 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:02:45.453235 PIEI prepare done
325 01:02:45.453686 fastboot data load
326 01:02:45.454099 fastboot data verify
327 01:02:45.458917 verify result: 266
328 01:02:45.464424 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 01:02:45.464874 LPDDR4 probe
330 01:02:45.465279 ddr clk to 1584MHz
331 01:02:45.472394 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:02:45.509691
333 01:02:45.510150 dmc_version 0001
334 01:02:45.516444 Check phy result
335 01:02:45.522354 INFO : End of CA training
336 01:02:45.522795 INFO : End of initialization
337 01:02:45.528053 INFO : Training has run successfully!
338 01:02:45.528503 Check phy result
339 01:02:45.533543 INFO : End of initialization
340 01:02:45.533980 INFO : End of read enable training
341 01:02:45.539235 INFO : End of fine write leveling
342 01:02:45.544728 INFO : End of Write leveling coarse delay
343 01:02:45.545162 INFO : Training has run successfully!
344 01:02:45.545566 Check phy result
345 01:02:45.550363 INFO : End of initialization
346 01:02:45.550817 INFO : End of read dq deskew training
347 01:02:45.556030 INFO : End of MPR read delay center optimization
348 01:02:45.561460 INFO : End of write delay center optimization
349 01:02:45.567116 INFO : End of read delay center optimization
350 01:02:45.567568 INFO : End of max read latency training
351 01:02:45.572675 INFO : Training has run successfully!
352 01:02:45.573127 1D training succeed
353 01:02:45.581824 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:02:45.629485 Check phy result
355 01:02:45.629941 INFO : End of initialization
356 01:02:45.651794 INFO : End of 2D read delay Voltage center optimization
357 01:02:45.671037 INFO : End of 2D read delay Voltage center optimization
358 01:02:45.723003 INFO : End of 2D write delay Voltage center optimization
359 01:02:45.772153 INFO : End of 2D write delay Voltage center optimization
360 01:02:45.777772 INFO : Training has run successfully!
361 01:02:45.778206
362 01:02:45.778614 channel==0
363 01:02:45.783297 RxClkDly_Margin_A0==88 ps 9
364 01:02:45.783728 TxDqDly_Margin_A0==98 ps 10
365 01:02:45.788949 RxClkDly_Margin_A1==88 ps 9
366 01:02:45.789393 TxDqDly_Margin_A1==88 ps 9
367 01:02:45.789831 TrainedVREFDQ_A0==74
368 01:02:45.794455 TrainedVREFDQ_A1==74
369 01:02:45.794899 VrefDac_Margin_A0==24
370 01:02:45.795301 DeviceVref_Margin_A0==40
371 01:02:45.800044 VrefDac_Margin_A1==23
372 01:02:45.800523 DeviceVref_Margin_A1==40
373 01:02:45.800951
374 01:02:45.801368
375 01:02:45.801776 channel==1
376 01:02:45.805758 RxClkDly_Margin_A0==78 ps 8
377 01:02:45.806282 TxDqDly_Margin_A0==98 ps 10
378 01:02:45.811289 RxClkDly_Margin_A1==78 ps 8
379 01:02:45.811747 TxDqDly_Margin_A1==88 ps 9
380 01:02:45.818472 TrainedVREFDQ_A0==78
381 01:02:45.818914 TrainedVREFDQ_A1==75
382 01:02:45.820653 VrefDac_Margin_A0==22
383 01:02:45.821082 DeviceVref_Margin_A0==36
384 01:02:45.821486 VrefDac_Margin_A1==23
385 01:02:45.826239 DeviceVref_Margin_A1==39
386 01:02:45.826663
387 01:02:45.831954 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:02:45.832419
389 01:02:45.861009 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000019 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 01:02:45.861531 2D training succeed
391 01:02:45.866569 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:02:45.872195 auto size-- 65535DDR cs0 size: 2048MB
393 01:02:45.872631 DDR cs1 size: 2048MB
394 01:02:45.877771 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:02:45.878202 cs0 DataBus test pass
396 01:02:45.883367 cs1 DataBus test pass
397 01:02:45.883795 cs0 AddrBus test pass
398 01:02:45.884254 cs1 AddrBus test pass
399 01:02:45.884657
400 01:02:45.889026 100bdlr_step_size ps== 478
401 01:02:45.889470 result report
402 01:02:45.894668 boot times 0Enable ddr reg access
403 01:02:45.900389 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:02:45.914218 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 01:02:46.569239 bl2z: ptr: 05129330, size: 00001e40
406 01:02:46.574837 0.0;M3 CHK:0;cm4_sp_mode 0
407 01:02:46.575313 MVN_1=0x00000000
408 01:02:46.575732 MVN_2=0x00000000
409 01:02:46.586273 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 01:02:46.586745 OPS=0x04
411 01:02:46.587162 ring efuse init
412 01:02:46.591939 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 01:02:46.592421 [0.017319 Inits done]
414 01:02:46.592832 secure task start!
415 01:02:46.598321 high task start!
416 01:02:46.598764 low task start!
417 01:02:46.599171 run into bl31
418 01:02:46.607929 NOTICE: BL31: v1.3(release):4fc40b1
419 01:02:46.615729 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 01:02:46.616203 NOTICE: BL31: G12A normal boot!
421 01:02:46.631353 NOTICE: BL31: BL33 decompress pass
422 01:02:46.636862 ERROR: Error initializing runtime service opteed_fast
423 01:02:47.882842 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 01:02:47.883448 bl2_stage_init 0x01
425 01:02:47.883884 bl2_stage_init 0x81
426 01:02:47.888398 hw id: 0x0000 - pwm id 0x01
427 01:02:47.888909 bl2_stage_init 0xc1
428 01:02:47.893193 bl2_stage_init 0x02
429 01:02:47.893676
430 01:02:47.894074 L0:00000000
431 01:02:47.894462 L1:00000703
432 01:02:47.894847 L2:00008067
433 01:02:47.898664 L3:15000000
434 01:02:47.899095 S1:00000000
435 01:02:47.899484 B2:20282000
436 01:02:47.899869 B1:a0f83180
437 01:02:47.900290
438 01:02:47.900678 TE: 70447
439 01:02:47.901064
440 01:02:47.909852 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 01:02:47.910282
442 01:02:47.910674 Board ID = 1
443 01:02:47.911057 Set cpu clk to 24M
444 01:02:47.911436 Set clk81 to 24M
445 01:02:47.915467 Use GP1_pll as DSU clk.
446 01:02:47.915888 DSU clk: 1200 Mhz
447 01:02:47.916307 CPU clk: 1200 MHz
448 01:02:47.921144 Set clk81 to 166.6M
449 01:02:47.926744 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 01:02:47.927162 board id: 1
451 01:02:47.934749 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 01:02:47.945646 fw parse done
453 01:02:47.951605 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 01:02:47.994778 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 01:02:48.005905 PIEI prepare done
456 01:02:48.006342 fastboot data load
457 01:02:48.006734 fastboot data verify
458 01:02:48.011474 verify result: 266
459 01:02:48.017220 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 01:02:48.017586 LPDDR4 probe
461 01:02:48.017816 ddr clk to 1584MHz
462 01:02:49.382148 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd000 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 01:02:49.382820 bl2_stage_init 0x01
464 01:02:49.383301 bl2_stage_init 0x81
465 01:02:49.387279 hw id: 0x0000 - pwm id 0x01
466 01:02:49.387778 bl2_stage_init 0xc1
467 01:02:49.392871 bl2_stage_init 0x02
468 01:02:49.393352
469 01:02:49.393772 L0:00000000
470 01:02:49.394174 L1:00000703
471 01:02:49.394578 L2:00008067
472 01:02:49.394981 L3:15000000
473 01:02:49.398481 S1:00000000
474 01:02:49.398969 B2:20282000
475 01:02:49.399380 B1:a0f83180
476 01:02:49.399777
477 01:02:49.400224 TE: 69627
478 01:02:49.400630
479 01:02:49.404057 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 01:02:49.404596
481 01:02:49.409706 Board ID = 1
482 01:02:49.410246 Set cpu clk to 24M
483 01:02:49.410690 Set clk81 to 24M
484 01:02:49.415322 Use GP1_pll as DSU clk.
485 01:02:49.416147 DSU clk: 1200 Mhz
486 01:02:49.416631 CPU clk: 1200 MHz
487 01:02:49.420851 Set clk81 to 166.6M
488 01:02:49.426440 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 01:02:49.426913 board id: 1
490 01:02:49.433601 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 01:02:49.444526 fw parse done
492 01:02:49.450455 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 01:02:49.493620 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 01:02:49.504853 PIEI prepare done
495 01:02:49.505359 fastboot data load
496 01:02:49.505776 fastboot data verify
497 01:02:49.510550 verify result: 266
498 01:02:49.516075 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 01:02:49.516563 LPDDR4 probe
500 01:02:49.516978 ddr clk to 1584MHz
501 01:02:49.523928 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 01:02:49.561822
503 01:02:49.562385 dmc_version 0001
504 01:02:49.568789 Check phy result
505 01:02:49.574756 INFO : End of CA training
506 01:02:49.575243 INFO : End of initialization
507 01:02:49.580395 INFO : Training has run successfully!
508 01:02:49.580896 Check phy result
509 01:02:49.586023 INFO : End of initialization
510 01:02:49.586556 INFO : End of read enable training
511 01:02:49.591571 INFO : End of fine write leveling
512 01:02:49.597161 INFO : End of Write leveling coarse delay
513 01:02:49.597633 INFO : Training has run successfully!
514 01:02:49.598046 Check phy result
515 01:02:49.602787 INFO : End of initialization
516 01:02:49.603256 INFO : End of read dq deskew training
517 01:02:49.608337 INFO : End of MPR read delay center optimization
518 01:02:49.613931 INFO : End of write delay center optimization
519 01:02:49.619555 INFO : End of read delay center optimization
520 01:02:49.620079 INFO : End of max read latency training
521 01:02:49.625141 INFO : Training has run successfully!
522 01:02:49.625614 1D training succeed
523 01:02:49.634317 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 01:02:49.682648 Check phy result
525 01:02:49.683196 INFO : End of initialization
526 01:02:49.710065 INFO : End of 2D read delay Voltage center optimization
527 01:02:49.734282 INFO : End of 2D read delay Voltage center optimization
528 01:02:49.790896 INFO : End of 2D write delay Voltage center optimization
529 01:02:49.844894 INFO : End of 2D write delay Voltage center optimization
530 01:02:49.850569 INFO : Training has run successfully!
531 01:02:49.851037
532 01:02:49.851468 channel==0
533 01:02:49.856093 RxClkDly_Margin_A0==69 ps 7
534 01:02:49.856566 TxDqDly_Margin_A0==98 ps 10
535 01:02:49.861655 RxClkDly_Margin_A1==88 ps 9
536 01:02:49.862119 TxDqDly_Margin_A1==98 ps 10
537 01:02:49.862534 TrainedVREFDQ_A0==74
538 01:02:49.867247 TrainedVREFDQ_A1==75
539 01:02:49.867710 VrefDac_Margin_A0==24
540 01:02:49.868157 DeviceVref_Margin_A0==40
541 01:02:49.872857 VrefDac_Margin_A1==23
542 01:02:49.873327 DeviceVref_Margin_A1==39
543 01:02:49.873743
544 01:02:49.874147
545 01:02:49.878577 channel==1
546 01:02:49.879041 RxClkDly_Margin_A0==78 ps 8
547 01:02:49.879453 TxDqDly_Margin_A0==98 ps 10
548 01:02:49.884096 RxClkDly_Margin_A1==78 ps 8
549 01:02:49.884564 TxDqDly_Margin_A1==78 ps 8
550 01:02:49.889638 TrainedVREFDQ_A0==78
551 01:02:49.890103 TrainedVREFDQ_A1==75
552 01:02:49.890517 VrefDac_Margin_A0==22
553 01:02:49.895266 DeviceVref_Margin_A0==36
554 01:02:49.895743 VrefDac_Margin_A1==22
555 01:02:49.900852 DeviceVref_Margin_A1==39
556 01:02:49.901314
557 01:02:49.901726 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 01:02:49.902129
559 01:02:49.934536 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000014 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
560 01:02:49.935063 2D training succeed
561 01:02:49.940061 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 01:02:49.945643 auto size-- 65535DDR cs0 size: 2048MB
563 01:02:49.946117 DDR cs1 size: 2048MB
564 01:02:49.951261 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 01:02:49.951731 cs0 DataBus test pass
566 01:02:49.956865 cs1 DataBus test pass
567 01:02:49.957334 cs0 AddrBus test pass
568 01:02:49.957743 cs1 AddrBus test pass
569 01:02:49.958140
570 01:02:49.962450 100bdlr_step_size ps== 471
571 01:02:49.962930 result report
572 01:02:49.968079 boot times 0Enable ddr reg access
573 01:02:49.973346 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 01:02:49.987131 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 01:02:50.647204 bl2z: ptr: 05129330, size: 00001e40
576 01:02:50.655665 0.0;M3 CHK:0;cm4_sp_mode 0
577 01:02:50.656201 MVN_1=0x00000000
578 01:02:50.656621 MVN_2=0x00000000
579 01:02:50.667186 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 01:02:50.667667 OPS=0x04
581 01:02:50.668123 ring efuse init
582 01:02:50.672764 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 01:02:50.673237 [0.017354 Inits done]
584 01:02:50.673647 secure task start!
585 01:02:50.680736 high task start!
586 01:02:50.681199 low task start!
587 01:02:50.681607 run into bl31
588 01:02:50.689358 NOTICE: BL31: v1.3(release):4fc40b1
589 01:02:50.697179 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 01:02:50.697656 NOTICE: BL31: G12A normal boot!
591 01:02:50.712722 NOTICE: BL31: BL33 decompress pass
592 01:02:50.720892 ERROR: Error initializing runtime service opteed_fast
593 01:02:51.931559 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 01:02:51.932179 bl2_stage_init 0x01
595 01:02:51.932606 bl2_stage_init 0x81
596 01:02:51.937031 hw id: 0x0000 - pwm id 0x01
597 01:02:51.937325 bl2_stage_init 0xc1
598 01:02:51.942653 bl2_stage_init 0x02
599 01:02:51.942942
600 01:02:51.943152 L0:00000000
601 01:02:51.943355 L1:00000703
602 01:02:51.943553 L2:00008067
603 01:02:51.943753 L3:15000000
604 01:02:51.948205 S1:00000000
605 01:02:51.948480 B2:20282000
606 01:02:51.948694 B1:a0f83180
607 01:02:51.948896
608 01:02:51.949109 TE: 69100
609 01:02:51.949308
610 01:02:51.953844 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 01:02:51.954230
612 01:02:51.959484 Board ID = 1
613 01:02:51.959873 Set cpu clk to 24M
614 01:02:51.960210 Set clk81 to 24M
615 01:02:51.964944 Use GP1_pll as DSU clk.
616 01:02:51.965225 DSU clk: 1200 Mhz
617 01:02:51.965429 CPU clk: 1200 MHz
618 01:02:51.970685 Set clk81 to 166.6M
619 01:02:51.976260 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 01:02:51.976659 board id: 1
621 01:02:51.983516 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 01:02:51.994369 fw parse done
623 01:02:52.000364 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 01:02:52.043339 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 01:02:52.054478 PIEI prepare done
626 01:02:52.054782 fastboot data load
627 01:02:52.054995 fastboot data verify
628 01:02:52.060058 verify result: 266
629 01:02:52.065630 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 01:02:52.066043 LPDDR4 probe
631 01:02:52.066377 ddr clk to 1584MHz
632 01:02:52.073668 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 01:02:52.111421
634 01:02:52.111829 dmc_version 0001
635 01:02:52.118503 Check phy result
636 01:02:52.124456 INFO : End of CA training
637 01:02:52.125034 INFO : End of initialization
638 01:02:52.130001 INFO : Training has run successfully!
639 01:02:52.130548 Check phy result
640 01:02:52.135641 INFO : End of initialization
641 01:02:52.136437 INFO : End of read enable training
642 01:02:52.138846 INFO : End of fine write leveling
643 01:02:52.144475 INFO : End of Write leveling coarse delay
644 01:02:52.149969 INFO : Training has run successfully!
645 01:02:52.150317 Check phy result
646 01:02:52.150529 INFO : End of initialization
647 01:02:52.155623 INFO : End of read dq deskew training
648 01:02:52.159038 INFO : End of MPR read delay center optimization
649 01:02:52.164549 INFO : End of write delay center optimization
650 01:02:52.170192 INFO : End of read delay center optimization
651 01:02:52.170524 INFO : End of max read latency training
652 01:02:52.175833 INFO : Training has run successfully!
653 01:02:52.176329 1D training succeed
654 01:02:52.184023 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 01:02:52.232334 Check phy result
656 01:02:52.232709 INFO : End of initialization
657 01:02:52.259698 INFO : End of 2D read delay Voltage center optimization
658 01:02:52.284113 INFO : End of 2D read delay Voltage center optimization
659 01:02:52.340585 INFO : End of 2D write delay Voltage center optimization
660 01:02:52.394664 INFO : End of 2D write delay Voltage center optimization
661 01:02:52.400135 INFO : Training has run successfully!
662 01:02:52.400746
663 01:02:52.401240 channel==0
664 01:02:52.405727 RxClkDly_Margin_A0==78 ps 8
665 01:02:52.406325 TxDqDly_Margin_A0==88 ps 9
666 01:02:52.409447 RxClkDly_Margin_A1==88 ps 9
667 01:02:52.410043 TxDqDly_Margin_A1==98 ps 10
668 01:02:52.414789 TrainedVREFDQ_A0==74
669 01:02:52.415395 TrainedVREFDQ_A1==74
670 01:02:52.415906 VrefDac_Margin_A0==23
671 01:02:52.420322 DeviceVref_Margin_A0==40
672 01:02:52.420950 VrefDac_Margin_A1==22
673 01:02:52.425861 DeviceVref_Margin_A1==40
674 01:02:52.426456
675 01:02:52.426949
676 01:02:52.427423 channel==1
677 01:02:52.427874 RxClkDly_Margin_A0==78 ps 8
678 01:02:52.431360 TxDqDly_Margin_A0==98 ps 10
679 01:02:52.431944 RxClkDly_Margin_A1==78 ps 8
680 01:02:52.437013 TxDqDly_Margin_A1==88 ps 9
681 01:02:52.437600 TrainedVREFDQ_A0==78
682 01:02:52.438075 TrainedVREFDQ_A1==74
683 01:02:52.442660 VrefDac_Margin_A0==22
684 01:02:52.443484 DeviceVref_Margin_A0==36
685 01:02:52.448311 VrefDac_Margin_A1==20
686 01:02:52.448893 DeviceVref_Margin_A1==40
687 01:02:52.449371
688 01:02:52.453855 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 01:02:52.454455
690 01:02:52.481832 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000019 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000019 00000019 00000017 00000019 00000015 00000017 00000015 00000015 00000017 00000018 0000001a 00000018 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000060
691 01:02:52.487360 2D training succeed
692 01:02:52.492910 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 01:02:52.493533 auto size-- 65535DDR cs0 size: 2048MB
694 01:02:52.498489 DDR cs1 size: 2048MB
695 01:02:52.499317 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 01:02:52.504147 cs0 DataBus test pass
697 01:02:52.504777 cs1 DataBus test pass
698 01:02:52.505272 cs0 AddrBus test pass
699 01:02:52.509680 cs1 AddrBus test pass
700 01:02:52.510206
701 01:02:52.510679 100bdlr_step_size ps== 478
702 01:02:52.511157 result report
703 01:02:52.515244 boot times 0Enable ddr reg access
704 01:02:52.522927 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 01:02:52.536687 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 01:02:53.196836 bl2z: ptr: 05129330, size: 00001e40
707 01:02:53.204340 0.0;M3 CHK:0;cm4_sp_mode 0
708 01:02:53.204920 MVN_1=0x00000000
709 01:02:53.205366 MVN_2=0x00000000
710 01:02:53.216129 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 01:02:53.216717 OPS=0x04
712 01:02:53.217161 ring efuse init
713 01:02:53.221444 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 01:02:53.221942 [0.017354 Inits done]
715 01:02:53.222378 secure task start!
716 01:02:53.229230 high task start!
717 01:02:53.229714 low task start!
718 01:02:53.230148 run into bl31
719 01:02:53.237881 NOTICE: BL31: v1.3(release):4fc40b1
720 01:02:53.245666 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 01:02:53.246169 NOTICE: BL31: G12A normal boot!
722 01:02:53.261214 NOTICE: BL31: BL33 decompress pass
723 01:02:53.266982 ERROR: Error initializing runtime service opteed_fast
724 01:02:54.062333
725 01:02:54.062739
726 01:02:54.067747 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 01:02:54.068210
728 01:02:54.071218 Model: Libre Computer AML-S905D3-CC Solitude
729 01:02:54.218328 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 01:02:54.233592 DRAM: 2 GiB (effective 3.8 GiB)
731 01:02:54.334629 Core: 406 devices, 33 uclasses, devicetree: separate
732 01:02:54.340470 WDT: Not starting watchdog@f0d0
733 01:02:54.365576 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 01:02:54.377801 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 01:02:54.382729 ** Bad device specification mmc 0 **
736 01:02:54.392808 Card did not respond to voltage select! : -110
737 01:02:54.400555 ** Bad device specification mmc 0 **
738 01:02:54.401150 Couldn't find partition mmc 0
739 01:02:54.408898 Card did not respond to voltage select! : -110
740 01:02:54.414449 ** Bad device specification mmc 0 **
741 01:02:54.414998 Couldn't find partition mmc 0
742 01:02:54.419449 Error: could not access storage.
743 01:02:54.715941 Net: eth0: ethernet@ff3f0000
744 01:02:54.716631 starting USB...
745 01:02:54.960596 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 01:02:54.961223 Starting the controller
747 01:02:54.967553 USB XHCI 1.10
748 01:02:56.521694 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 01:02:56.529970 scanning usb for storage devices... 0 Storage Device(s) found
751 01:02:56.581650 Hit any key to stop autoboot: 1
752 01:02:56.582742 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 01:02:56.583452 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 01:02:56.584066 Setting prompt string to ['=>']
755 01:02:56.584615 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 01:02:56.595959 0
757 01:02:56.596950 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 01:02:56.698304 => setenv autoload no
760 01:02:56.699566 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 01:02:56.705353 setenv autoload no
763 01:02:56.807284 => setenv initrd_high 0xffffffff
764 01:02:56.807808 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 01:02:56.812178 setenv initrd_high 0xffffffff
767 01:02:56.913203 => setenv fdt_high 0xffffffff
768 01:02:56.913933 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 01:02:56.918195 setenv fdt_high 0xffffffff
771 01:02:57.019783 => dhcp
772 01:02:57.020626 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 01:02:57.024584 dhcp
774 01:02:58.030601 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 01:02:58.031285 Speed: 1000, full duplex
776 01:02:58.031766 BOOTP broadcast 1
777 01:02:58.279301 BOOTP broadcast 2
778 01:02:58.293945 DHCP client bound to address 192.168.6.21 (263 ms)
780 01:02:58.395718 => setenv serverip 192.168.6.2
781 01:02:58.396537 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
782 01:02:58.401038 setenv serverip 192.168.6.2
784 01:02:58.502616 => tftpboot 0x01080000 955840/tftp-deploy-nl3nq4j1/kernel/uImage
785 01:02:58.503493 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
786 01:02:58.510116 tftpboot 0x01080000 955840/tftp-deploy-nl3nq4j1/kernel/uImage
787 01:02:58.510712 Speed: 1000, full duplex
788 01:02:58.511347 Using ethernet@ff3f0000 device
789 01:02:58.515558 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
790 01:02:58.521139 Filename '955840/tftp-deploy-nl3nq4j1/kernel/uImage'.
791 01:02:58.524978 Load address: 0x1080000
792 01:02:58.551378 Loading: * UDP wrong checksum 00000005 000032a6
793 01:03:00.674552 ################################### UDP wrong checksum 000000ff 00006e95
794 01:03:00.688990 # UDP wrong checksum 000000ff 0000f787
795 01:03:01.564215 ############## 43.6 MiB
796 01:03:01.564592 14.3 MiB/s
797 01:03:01.565019 done
798 01:03:01.568785 Bytes transferred = 45713984 (2b98a40 hex)
800 01:03:01.670309 => tftpboot 0x08000000 955840/tftp-deploy-nl3nq4j1/ramdisk/ramdisk.cpio.gz.uboot
801 01:03:01.671217 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
802 01:03:01.677939 tftpboot 0x08000000 955840/tftp-deploy-nl3nq4j1/ramdisk/ramdisk.cpio.gz.uboot
803 01:03:01.678433 Speed: 1000, full duplex
804 01:03:01.678850 Using ethernet@ff3f0000 device
805 01:03:01.683345 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
806 01:03:01.693115 Filename '955840/tftp-deploy-nl3nq4j1/ramdisk/ramdisk.cpio.gz.uboot'.
807 01:03:01.693632 Load address: 0x8000000
808 01:03:02.745298 Loading: *########### UDP wrong checksum 000000ff 00003edc
809 01:03:02.786625 # UDP wrong checksum 000000ff 0000d1ce
810 01:03:11.602137 ##########T ########################### UDP wrong checksum 0000000f 00003fc2
811 01:03:16.603416 T UDP wrong checksum 0000000f 00003fc2
812 01:03:26.177916 T UDP wrong checksum 000000ff 00000aa3
813 01:03:26.237989 UDP wrong checksum 000000ff 0000a595
814 01:03:26.605303 T UDP wrong checksum 0000000f 00003fc2
815 01:03:37.838831 T T UDP wrong checksum 000000ff 000077b3
816 01:03:37.878612 UDP wrong checksum 000000ff 000008a6
817 01:03:46.608422 T UDP wrong checksum 0000000f 00003fc2
818 01:03:50.748245 T UDP wrong checksum 000000ff 00008faa
819 01:03:50.818240 UDP wrong checksum 000000ff 0000199d
820 01:04:01.613077 T T
821 01:04:01.613517 Retry count exceeded; starting again
823 01:04:01.614931 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
826 01:04:01.615938 end: 2.4 uboot-commands (duration 00:01:24) [common]
828 01:04:01.616794 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
830 01:04:01.617431 end: 2 uboot-action (duration 00:01:24) [common]
832 01:04:01.618315 Cleaning after the job
833 01:04:01.618680 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955840/tftp-deploy-nl3nq4j1/ramdisk
834 01:04:01.619474 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955840/tftp-deploy-nl3nq4j1/kernel
835 01:04:01.643311 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955840/tftp-deploy-nl3nq4j1/dtb
836 01:04:01.644581 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955840/tftp-deploy-nl3nq4j1/modules
837 01:04:01.666227 start: 4.1 power-off (timeout 00:00:30) [common]
838 01:04:01.666927 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
839 01:04:01.698546 >> OK - accepted request
840 01:04:01.700754 Returned 0 in 0 seconds
841 01:04:01.801611 end: 4.1 power-off (duration 00:00:00) [common]
843 01:04:01.802650 start: 4.2 read-feedback (timeout 00:10:00) [common]
844 01:04:01.803331 Listened to connection for namespace 'common' for up to 1s
845 01:04:02.803528 Finalising connection for namespace 'common'
846 01:04:02.804364 Disconnecting from shell: Finalise
847 01:04:02.804941 =>
848 01:04:02.905969 end: 4.2 read-feedback (duration 00:00:01) [common]
849 01:04:02.906464 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/955840
850 01:04:03.635401 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/955840
851 01:04:03.636265 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.